PSoC® 4: 4200 BLE Family Datasheet by Cypress Semiconductor Corp

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PSoC® 4: 4200_BLE
Family Datasheet
Programmable System-on-Chip (PSoC®)
Cypress Semiconductor Corporation 198 Champion Court San Jose,CA 95134-1709 408-943-2600
Document Number: 002-23053 Rev. ** Revised February 22, 2018
General Description
PSoC® 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an
Arm® Cortex®-M0 CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. The
PSoC 4200_BL product family, based on this platform, is a combination of a microcontroller with an integrated Bluetooth Low Energy
(BLE), also known as Bluetooth Smart, radio and subsystem (BLESS). The other features include digital programmable logic,
high-performance analog-to-digital conversion (ADC), opamps with Comparator mode, and standard communication and timing
peripherals. The programmable analog and digital subsystems allow flexibility and in-field tuning of the design.
Features
32-bit MCU Subsystem
48-MHz Arm Cortex-M0 CPU with single-cycle multiply and
DMA
Up to 256 KB of flash with Read Accelerator
Up to 32 KB of SRAM
BLE Radio and Subsystem
BLE 4.2 support
2.4-GHz RF transceiver with 50- antenna drive
Digital PHY
Link-Layer engine supporting master and slave modes
RF output power: –18 dBm to +3 dBm
RX sensitivity: –89 dBm
RX current: 18.7 mA
TX current: 15.6 mA at 0 dBm
RSSI: 1-dB resolution
Programmable Analog
Four opamps with reconfigurable high-drive external and
high-bandwidth internal drive, Comparator modes, and ADC
input buffering capability. Can operate in Deep Sleep mode.
12-bit, 1-Msps SAR ADC with differential and single-ended
modes; Channel Sequencer with signal averaging
Two current DACs (IDACs) for general-purpose or capacitive
sensing applications on any pin
Two low-power comparators that operate in Deep Sleep mode
Programmable Digital
Four programmable logic blocks called universal digital blocks,
(UDBs), each with eight macrocells and data path
Cypress-provided peripheral component library, user-defined
state machines, and Verilog input
Power Management
Active mode: 1.7 mA at 3-MHz flash program execution
Deep Sleep mode: 1.5 µA with watch crystal oscillator (WCO)
on
Hibernate mode: 150 nA with RAM retention
Stop mode: 60 nA
Capacitive Sensing
Cypress Capacitive Sigma-Delta (CSD) provides best-in-class
SNR (>5:1) and liquid tolerance
Cypress-supplied software component makes capacitive
sensing design easy
Automatic hardware tuning algorithm (SmartSense™)
Segment LCD Drive
LCD drive supported on all pins (common or segment)
Operates in Deep Sleep mode with four bits per pin memory
Serial Communication
Two independent run-time reconfigurable serial communi-
cation blocks (SCBs) with reconfigurable I2C, SPI, or UART
functionality
Timing and Pulse-Width Modulation
Four 16-bit timer/counter pulse-width modulator (TCPWM)
blocks
Center-aligned, Edge, and Pseudo-random modes
Comparator-based triggering of Kill signals for motor drive and
other high-reliability digital logic applications
Up to 36 Programmable GPIOs
7mm × 7mm 56-pin QFN package
76-ball CSP package
68-ball CSP package
Any GPIO pin can be CapSense, LCD, analog, or digital
Two overvoltage-tolerant (OVT) pins; drive modes, strengths,
and slew rates are programmable
PSoC Creator™ Design Environment
Integrated Design Environment (IDE) provides schematic
design entry and build (with analog and digital automatic
routing)
API components for all fixed-function and programmable
peripherals
Industry-Standard Tool Compatibility
After schematic entry, development can be done with
Arm-based industry-standard development tools
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PSoC® 4: 4200_BLE
Family Datasheet
Document Number: 002-23053 Rev. ** Page 2 of 49
More Information
Cypress provides a wealth of data at http://www.cypress.com to
help you to select the right PSoC device for your design, and to
help you to quickly and effectively integrate the device into your
design. For a comprehensive list of resources, see the intro-
duction page for Bluetooth® Low Energy (BLE) Products.
Following is an abbreviated list for PRoC BLE:
Overview: PSoC Portfolio, PSoC Roadmap
Product Selectors: PSoC 1, PSoC 3, PSoC 4, PRoC BLE,
PSoC 4 BLE, PSoC 5LP In addition, PSoC Creator includes a
device selection tool.
Application Notes: Cypress offers a large number of PSoC
application notes coverting a broad range of topics, from basic
to advanced level. Recommended application notes for getting
started with PRoC BLE are:
AN94020: Getting Started with PRoC BLE
AN97060: PSoC 4 BLE and PRoC BLE - Over-The-Air (OTA)
Device Firmware Upgrade (DFU) Guide
AN91184: PSoC 4 BLE - Designing BLE Applications
AN91162: Creating a BLE Custom Profile
AN91445: Antenna Design and RF Layout Guidelines
AN96841: Getting Started With EZ-BLE Module
AN85951: PSoC 4 CapSense Design Guide
AN95089: PSoC 4/PRoC BLE Crystal Oscillator Selection
and Tuning Techniques
AN92584: Designing for Low Power and Estimating Battery
Life for BLE Applications
Technical Reference Manual (TRM) is in two documents:
Architecture TRM details each PRoC BLE functional block
Registers TRM describes each of the PRoC BLE registers
Development Kits:
CY8CKIT-042-BLE-A Pioneer Kit, is a flexible, Arduino-com-
patible, Bluetooth LE development kit for PSoC 4 BLE and
PRoC BLE.
CY8CKIT-142, PSoC 4 BLE Module, features a PSoC 4 BLE
device, two crystals for the antenna matching network, a PCB
antenna and other passives, while providing access to all
GPIOs of the device.
CY8CKIT-143, PSoC 4 BLE 256KB Module, features a PSoC
4 BLE 256KB device, two crystals for the antenna matching
network, a PCB antenna and other passives, while providing
access to all GPIOs of the device.
The MiniProg3 device provides an interface for flash pro-
gramming and debug.
PSoC Creator
PSoC Creator is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design
of PSoC 3, PSoC 4, and PSoC 5LP based systems. Create designs using classic, familiar schematic capture supported by over 100
pre-verified, production-ready PSoC Components; see the list of component datasheets. With PSoC Creator, you can:
1. Drag and drop component icons to build your hardware
system design in the main design workspace
2. Codesign your application firmware with the PSoC hardware,
using the PSoC Creator IDE C compiler
3. Configure components using the configuration tools
4. Explore the library of 100+ components
5. Review component datasheets
Figure 1. Multiple-Sensor Example Project in PSoC Creator Contents
3
1
24
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Document Number: 002-23053 Rev. ** Page 3 of 49
Contents
Functional Definition........................................................ 5
CPU and Memory Subsystem ..................................... 5
System Resources ...................................................... 5
BLE Radio and Subsystem ......................................... 6
Analog Blocks.............................................................. 7
Programmable Digital.................................................. 8
Fixed-Function Digital.................................................. 9
GPIO ........................................................................... 9
Special-Function Peripherals .................................... 10
Pinouts ............................................................................ 11
Power............................................................................... 16
Development Support .................................................... 17
Documentation .......................................................... 17
Online ........................................................................ 17
Tools.......................................................................... 17
Electrical Specifications ................................................ 18
Absolute Maximum Ratings ...................................... 18
Device-Level Specifications ...................................... 18
Analog Peripherals .................................................... 23
Digital Peripherals ..................................................... 27
Memory ..................................................................... 29
System Resources .................................................... 30
Ordering Information...................................................... 37
Ordering Code Definitions......................................... 38
Packaging........................................................................ 39
WLCSP Compatibility................................................ 41
Acronyms........................................................................ 45
Document Conventions................................................. 47
Units of Measure ....................................................... 47
Revision History............................................................. 48
Sales, Solutions, and Legal Information...................... 49
Worldwide Sales and Design Support....................... 49
Products .................................................................... 49
PSoC® Solutions ...................................................... 49
Cypress Developer Community................................. 49
Technical Support ..................................................... 49
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Document Number: 002-23053 Rev. ** Page 4 of 49
Figure 2. Block Diagram
The PSoC 4200_BL devices include extensive support for
programming, testing, debugging, and tracing both hardware
and firmware.
The Arm SWD interface supports all programming and debug
features of the device.
Complete debug-on-chip functionality enables full-device
debugging in the final system using the standard production
device. It does not require special interfaces, debugging pods,
simulators, or emulators. Only the standard programming
connections are required to fully support debugging.
The PSoC Creator IDE provides fully integrated programming
and debugging support for the PSoC 4200_BL devices. The
SWD interface is fully compatible with industry-standard
third-party tools. With the ability to disable debug features, very
robust flash protection, and allowing customer-proprietary
functionality to be implemented in on-chip programmable blocks,
the PSoC 4200_BL family provides a level of security not
possible with multi-chip application solutions or with microcon-
trollers.
Debug circuits are enabled by default and can only be disabled
in firmware. If not enabled, the only way to re-enable them is to
erase the entire device, clear flash protection, and reprogram the
device with the new firmware that enables debugging.
Additionally, all device interfaces can be permanently disabled
(device security) for applications concerned about phishing
attacks due to a maliciously reprogrammed device or attempts to
defeat security by starting and interrupting flash programming
sequences. Because all programming, debug, and test inter-
faces are disabled when maximum device security is enabled,
PSoC 4200_BL with device security enabled may not be
returned for failure analysis. This is a trade-off the
PSoC 4200_BL allows the customer to make.
Peripherals
CPU Subsystem
System Interconnect (Multi Layer AHB)
PSoC
4200
DeepSleep
Hibernate
Active/Sleep
Power Modes
Digital DFT
Test
Analog DFT
System Resources
Power
Clock
Reset
Clock Control
IMO
Sleep Control
REF
POR
Reset Control
WIC
XRES
WDT
ILO
IOSS GPIO (7x ports)
IO Subsystem
Peripheral Interconnect (MMIO)
PCLK
SWD/TC
NVIC, IRQMUX
Cortex
M0
48 MHz
FAST MUL
FLASH
Up to 256 KB
Read Accelerator
SPCIF
SRAM
Up to 32 KB
SRAM Controller
ROM
8 KB
ROM Controller
NVLatches
PWRSYS
BOD
32-bit
AHB-Lite
LVD
4x TCPWM
x4
UDB...
Programmable
Digital
UDB
CapSense
2x SCB-I2C/SPI/UART
LCD
2x LP Comparator
Port Interface & Digital System Interconnect (DSI)
36x GPIOs, 2x GPIO_OVT
SAR ADC
(12-bit)
x1
CTBm x2
2x OpAmp
Programmable
Analog
SARMUX
High Speed I/O Matrix
Bluetooth Low
Energy Subsystem
BLE Baseband
Peripheral
GFSK Modem
2.4 GHz
GFSK
Radio
24MHz XO
LDO
I/O: Antenna/Power/Crystal
1KB SRAM
32kHz XO
DataWire/
DMA
Initiator/MMIO
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Functional Definition
CPU and Memory Subsystem
CPU
The Cortex-M0 CPU in PSoC 4200_BL is part of the 32-bit MCU
subsystem, which is optimized for low-power operation with
extensive clock gating. It mostly uses 16-bit instructions and
executes a subset of the Thumb-2 instruction set. This enables
fully compatible binary upward migration of the code to
higher-performance processors such as Cortex-M3 and M4. The
Cypress implementation includes a hardware multiplier that
provides a 32-bit result in one cycle. It includes a nested vectored
interrupt controller (NVIC) block with 32 interrupt inputs and a
wakeup interrupt controller (WIC). The WIC can wake the
processor up from the Deep Sleep mode, allowing power to the
main processor to be switched off when the chip is in the Deep
Sleep mode. The Cortex-M0 CPU provides a nonmaskable
interrupt (NMI) input, which is made available to the user when
it is not in use for system functions requested by the user.
The CPU also includes an SWD interface, which is a 2-wire form
of JTAG; the debug configuration used for PSoC 4200_BL has
four break-point (address) comparators and two watchpoint
(data) comparators.
Flash
The PSoC 4200_BL device has a flash module with 256 KB of
flash memory, tightly coupled to the CPU to improve average
access times from the flash block. The flash block is designed to
deliver 2 wait-state (WS) access time at 48 MHz and with 1-WS
access time at 24 MHz. The flash accelerator delivers 85% of
single-cycle SRAM access performance on average. Part of the
flash module can be used to emulate EEPROM operation if
required. Maximum erase and program time is 20 ms per row
(256 bytes). This also applies to the emulated EEPROM.
SRAM
SRAM memory is retained during Hibernate.
SROM
The 8-KB supervisory ROM contains a library of executable
functions for flash programming. These functions are accessed
through supervisory calls (SVC) and enable in-system
programming of the flash memory.
DMA
A DMA engine, with eight channels, is provided that can do 32-bit
transfers and has chainable ping-pong descriptors.
System Resources
Power System
The power system is described in detail in the section Power on
page 16. It provides an assurance that the voltage levels are as
required for the respective modes, and can either delay the mode
entry (on power-on reset (POR), for example) until voltage levels
are as required or generate resets (brownout detect (BOD)) or
interrupts when the power supply reaches a particular program-
mable level between 1.8 and 4.5 V (low voltage detect (LVD)).
PSoC 4200_BL operates with a single external supply (1.71 to
5.5 V without radio, and 1.9 V to 5.5 V with radio). The device
has five different power modes; transitions between these modes
are managed by the power system. PSoC 4200_BL provides
Sleep, Deep Sleep, Hibernate, and Stop low-power modes. Refer
to the Technical Reference Manual for more details.
Clock System
The PSoC 4200_BL clock system is responsible for providing
clocks to all subsystems that require clocks and for switching
between different clock sources without glitching. In addition, the
clock system ensures that no metastable conditions occur.
The clock system for PSoC 4200_BL consists of the internal
main oscillator (IMO), the internal low-speed oscillator (ILO), the
24-MHz external crystal oscillator (ECO) and the 32-kHz watch
crystal oscillator (WCO). In addition, an external clock may be
supplied from a pin.
IMO Clock Source
The IMO is the primary source of internal clocking in
PSoC 4200_BL. It is trimmed during testing to achieve the
specified accuracy. Trim values are stored in nonvolatile latches
(NVL). Additional trim settings from flash can be used to
compensate for changes. The IMO default frequency is 24 MHz
and it can be adjusted between 3 to 48 MHz in steps of 1 MHz.
The IMO tolerance with Cypress-provided calibration settings is
±2%.
ILO Clock Source
The ILO is a very low-power oscillator, which is primarily used to
generate clocks for the peripheral operation in the Deep Sleep
mode. ILO-driven counters can be calibrated to the IMO to
improve accuracy. Cypress provides a software component,
which does the calibration.
External Crystal Oscillator (ECO)
The ECO is used as the active clock for the BLE subsystem to
meet the ±50-ppm clock accuracy of the Bluetooth 4.2
Specification. PSoC 4200_BL includes a tunable load capacitor
to tune the crystal clock frequency by measuring the actual clock
frequency. The high-accuracy ECO clock can also be used as a
system clock.
Watch Crystal Oscillator (WCO)
The WCO is used as the sleep clock for the BLE subsystem to
meet the ±500-ppm clock accuracy for the Bluetooth 4.2
Specification. The sleep clock provides an accurate sleep timing
and enables wakeup at the specified advertisement and
connection intervals. The WCO output can be used to realize the
real-time clock (RTC) function in firmware.
Watchdog Timer
A watchdog timer is implemented in the clock block running from
the ILO or from the WCO; this allows the watchdog operation
during Deep Sleep and generates a watchdog reset if not
serviced before the timeout occurs. The watchdog reset is
recorded in the Reset Cause register. With the WCO and
firmware, an accurate real-time clock (within the bounds of the
32-kHz crystal accuracy) can be realized.
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Figure 3. PSoC 4200_BL MCU Clocking Architecture
The HFCLK signal can be divided down (see Figure 3) to
generate synchronous clocks for the UDBs, and the analog and
digital peripherals. There are a total of 12 clock dividers for
PSoC 4200_BL: ten with 16-bit divide capability and two with
16.5-bit divide capability. This allows the generation of 16 divided
clock signals, which can be used by peripheral blocks. The
analog clock leads the digital clocks to allow analog events to
occur before the digital clock-related noise is generated. The
16-bit and 16.5-bit dividers allow a lot of flexibility in generating
fine-grained frequency values and are fully supported in PSoC
Creator.
Reset
PSoC 4200_BL device can be reset from a variety of sources
including a software reset. Reset events are asynchronous and
guarantee reversion to a known state. The reset cause is
recorded in a register, which is sticky through resets and allows
the software to determine the cause of the reset. An XRES pin
is reserved for an external reset to avoid complications with the
configuration and multiple pin functions during power-on or
reconfiguration. The XRES pin has an internal pull-up resistor
that is always enabled.
Voltage Reference
The PSoC 4200_BL reference system generates all internally
required references. A one-percent voltage reference spec is
provided for the 12-bit ADC. To allow better signal-to-noise ratios
(SNR) and better absolute accuracy, it is possible to bypass the
internal reference using a GPIO pin or use an external reference
for the SAR. Refer to Table 19, “SAR ADC AC Specifications,”
on page 26 for details.
BLE Radio and Subsystem
PSoC 4200_BL incorporates a Bluetooth Smart subsystem that
contains the Physical Layer (PHY) and Link Layer (LL) engines
with an embedded AES-128 security engine. The physical layer
consists of the digital PHY and the RF transceiver that transmits
and receives GFSK packets at 1 Mbps over a 2.4-GHz ISM band,
which is compliant with Bluetooth Smart Bluetooth Specification
4.2. The baseband controller is a composite hardware and
firmware implementation that supports both master and slave
modes. Key protocol elements, such as HCI and link control, are
implemented in firmware. Time-critical functional blocks, such as
encryption, CRC, data whitening, and access code correlation,
are implemented in hardware (in the LL engine).
The RF transceiver contains an integrated balun, which provides
a single-ended RF port pin to drive a 50- antenna via a
matching/filtering network. In the receive direction, this block
converts the RF signal from the antenna to a digital bit stream
after performing GFSK demodulation. In the transmit direction,
this block performs GFSK modulation and then converts a digital
baseband signal to a radio frequency before transmitting it to air
through the antenna.
The Bluetooth Smart Radio and Subsystem (BLESS) requires a
1.9-V minimum supply (the range varies from 1.9 V to 5.5 V).
Key features of BLESS are as follows:
Master and slave single-mode protocol stack with logical link
control and adaptation protocol (L2CAP), attribute (ATT), and
security manager (SM) protocols
API access to generic attribute profile (GATT), generic access
profile (GAP), and L2CAP
L2CAP connection-oriented channel
GAP features
Broadcaster, Observer, Peripheral, and Central roles
Security mode 1: Level 1, 2, 3, and 4
Security mode 2: Level 1 and 2
User-defined advertising data
Multiple bond support
GATT features
GATT client and server
Supports GATT sub-procedures
32-bit universally unique identifier (UUID)
Security Manager (SM)
Pairing methods: Just works, Passkey Entry, Out of Band and
Numeric Comparison
Authenticated man-in-the-middle (MITM) protection and data
signing
LE Secure Connections (Bluetooth 4.2 feature)
Link Layer (LL)
Master and Slave roles
128-bit AES engine
Encryption
Low-duty cycle advertising
LE Ping
LE Data Packet Length Extension (Bluetooth 4.2 feature)
Link Layer Privacy (with extended scanning filter policy, Blue-
tooth 4.2 feature)
Supports all SIG-adopted BLE profiles
IMO
ILO
EXTCLK
LFCLK
Presca le r SYSCLK
Divider 0
(/16)
PER0_CLK
Divider 9
(/16)
Fra ctional
Divider 0
(/16.5)
Fra ctional
Divider 1
(/16.5)
ECO
WCO
HFCLK
PER15_CLK
Divider
/2n (n=0..3)
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Document Number: 002-23053 Rev. ** Page 7 of 49
Analog Blocks
12-bit SAR ADC
The 12-bit, 1-Msps SAR ADC can operate at a maximum clock
rate of 18 MHz and requires a minimum of 18 clocks at that
frequency to do a 12-bit conversion.
The block functionality is augmented for the user by adding a
reference buffer to it (trimmable to ±1%) and by providing the
choice of three internal voltage references, VDD, VDD/2, and
VREF (nominally 1.024 V), as well as an external reference
through a GPIO pin. The Sample-and-Hold (S/H) aperture is
programmable; it allows the gain bandwidth requirements of the
amplifier driving the SAR inputs, which determine its settling
time, to be relaxed if required. System performance will be 65 dB
for true 12-bit precision provided appropriate references are
used and system noise levels permit it. To improve the perfor-
mance in noisy conditions, it is possible to provide an external
bypass (through a fixed pin location) for the internal reference
amplifier.
The SAR is connected to a fixed set of pins through an 8-input
sequencer. The sequencer cycles through the selected channels
autonomously (sequencer scan) and does so with zero switching
overhead (that is, the aggregate sampling bandwidth is equal to
1 Msps whether it is for a single channel or distributed over
several channels). The sequencer switching is effected through
a state machine or through firmware-driven switching. A feature
provided by the sequencer is the buffering of each channel to
reduce CPU interrupt-service requirements. To accommodate
signals with varying source impedances and frequencies, it is
possible to have different sample times programmable for each
channel. Also, the signal range specification through a pair of
range registers (low and high range values) is implemented with
a corresponding out-of-range interrupt if the digitized value
exceeds the programmed range; this allows fast detection of
out-of-range values without having to wait for a sequencer scan
to be completed and the CPU to read the values and check for
out-of-range values in software.
The SAR is able to digitize the output of the on-chip temperature
sensor for calibration and other temperature-dependent
functions. The SAR is not available in Deep Sleep and Hibernate
modes as it requires a high-speed clock (up to 18 MHz). The
SAR operating range is 1.71 to 5.5 V.
Figure 4. SAR ADC System Diagram
Opamps (CTBm Block)
PSoC 42X8_BLE has four opamps with Comparator modes,
which allow most common analog functions to be performed
on-chip, eliminating external components. PGAs, voltage
buffers, filters, transimpedance amplifiers, and other functions
can be realized with external passives saving power, cost, and
space. The on-chip opamps are designed with enough
bandwidth to drive the sample-and-hold circuit of the ADC
without requiring external buffering.
Temperature Sensor
PSoC 4200_BL has an on-chip temperature sensor. This
consists of a diode, which is biased by a current source that can
be disabled to save power. The temperature sensor is connected
to the ADC, which digitizes the reading and produces a temper-
ature value by using a Cypress-supplied software that includes
calibration and linearization.
Low-Power Comparators
PSoC 4200_BL has a pair of low-power comparators, which can
also operate in Deep Sleep and Hibernate modes. This allows
the analog system blocks to be disabled while retaining the ability
to monitor external voltage levels during low-power modes. The
comparator outputs are normally synchronized to avoid metasta-
bility unless operating in an asynchronous power mode
(Hibernate) where the system wake-up circuit is activated by a
comparator-switch event.
SARMUX
Port 3 (8 inputs)
vplusvminus
P0
P7
Data and
Status Flags
Reference
Selection
External
Reference
and
Bypass
(optional )
POS
NEG
SAR Sequencer
SARADC
Inputs from other Ports
VDD/2 VDDD VREF
AHB System Bus and Programmable Logic
Interconnect
Sequencing
and Control
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Programmable Digital
Universal Digital Blocks (UDBs) and Port Interfaces
The PSoC 4XX8 BLE 4.2 has four UDBs; the UDB array also
provides a switched Digital System Interconnect (DSI) fabric that
allows signals from peripherals and ports to be routed to and
through the UDBs for communication and control.
Figure 5. UDB Array
UDBs can be clocked from a clock-divider block, from a port
interface (required for peripherals such as SPI), and from the DSI
network directly or after synchronization.
A port interface is defined, which acts as a register that can be
clocked with the same source as the PLDs inside the UDB array.
This allows a faster operation because the inputs and outputs
can be registered at the port interface close to the I/O pins and
at the edge of the array. The port interface registers can be
clocked by one of the I/Os from the same port. This allows
interfaces such as SPI to operate at higher clock speeds by
eliminating the delay for the port input to be routed over DSI and
used to register other inputs (see Figure 6).
Figure 6. Port Interface
UDBs can generate interrupts (one UDB at a time) to the interrupt controller. UDBs retain the ability to connect to any pin on the chip
through the DSI.
Programmable Digital Subsystem
UDBIF
UDB UDB
UDB UDB
DSI DSI
DSI DSI
BUS IF CLK IF Port IF
Port IF
Port IF
High -Speed I/O Matrix
CPU
Sub-system
System
Interconnect Clocks
4 to 8
8 to 32
Routing
Channels
Other Digital
Signals in Chip
IRQ IF
Clock Selector
Block from
UDB
9
Digital
GlobalClocks
3 DSI Signals ,
1 I/O Signal
4
Reset Selector
Block from
UDB
2
2
Input Registers Output Registers
To DSI
8
From DSI
8
8 8
Enables
8
From DSI
4
4
7 6 . . . 0 7 6 . . . 0 3 2 1 0
High Speed I/O Matrix
To Clock
Tree
[0]
[0]
[1]
[1]
[1]
[1]
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Document Number: 002-23053 Rev. ** Page 9 of 49
Fixed-Function Digital
Timer/Counter/PWM Block
The timer/counter/PWM block consists of four 16-bit counters
with user-programmable period length. There is a Capture
register to record the count value at the time of an event (which
may be an I/O event), a period register which is used to either
stop or auto-reload the counter when its count is equal to the
period register, and compare registers to generate compare
value signals which are used as PWM duty cycle outputs. The
block also provides true and complementary outputs with
programmable offset between them to allow the use as
deadband programmable complementary PWM outputs. It also
has a Kill input to force outputs to a predetermined state; for
example, this is used in motor-drive systems when an
overcurrent state is indicated and the PWMs driving the FETs
need to be shut off immediately with no time for software
intervention.
Serial Communication Blocks (SCB)
PSoC 4200_BL has two SCBs, each of which can implement an
I2C, UART, or SPI interface.
I2C Mode: The hardware I2C block implements a full
multi-master and slave interface (it is capable of multimaster
arbitration). This block is capable of operating at speeds of up to
1 Mbps (Fast Mode Plus) and has flexible buffering options to
reduce the interrupt overhead and latency for the CPU. It also
supports EzI2C that creates a mailbox address range in the
memory of PSoC 4200_BL and effectively reduces the I2C
communication to reading from and writing to an array in the
memory. In addition, the block supports an 8-deep FIFO for
receive and transmit, which, by increasing the time given for the
CPU to read the data, greatly reduces the need for clock
stretching caused by the CPU not having read the data on time.
The FIFO mode is available in all channels and is very useful in
the absence of DMA.
The I2C peripheral is compatible with I2C Standard-mode,
Fast-mode, and Fast-Mode Plus devices as defined in the NXP
I2C-bus specification and user manual (UM10204). The I2C bus
I/O is implemented with GPIO in open-drain modes.
SCB1 is fully compliant with Standard mode (100 kHz), Fast
mode (400 kHz), and Fast-Mode Plus (1 MHz) I2C signaling
specifications when routed to GPIO pins P5[0] and P5[1], except
for hot-swap capability during I2C active communication. The
remaining GPIOs do not meet the hot-swap specification (VDD
off; draw < 10-µA current) for Fast mode and Fast-Mode Plus,
IOL Spec (20 mA) for Fast-Mode Plus, hysteresis spec (0.05 VDD)
for Fast mode and Fast-Mode Plus, and minimum fall time spec
for Fast mode and Fast-Mode Plus.
GPIO cells, including P5.0 and P5.1, cannot be hot-swapped
or powered up independent of the rest of the I2C system.
The GPIO pins P5.0 and P5.1 are over-voltage tolerant but
cannot be hot-swapped or powered up independent of the rest
of the I2C system
Fast-Mode Plus has an IOL specification of 20 mA at a VOL of
0.4 V. The GPIO cells can sink a maximum of 8 mA IOL with a
VOL maximum of 0.6 V.
Fast-mode and Fast-Mode Plus specify minimum Fall times,
which are not met with the GPIO cell; the Slow-Strong mode
can help meet this spec depending on the bus load.
UART Mode: This is a full-feature UART operating at up to
1 Mbps. It supports automotive single-wire interface (LIN),
infrared interface (IrDA), and SmartCard (ISO7816) protocols, all
of which are minor variants of the basic UART protocol. In
addition, it supports the 9-bit multiprocessor mode that allows the
addressing of peripherals connected over common RX and TX
lines. Common UART functions such as parity error, break
detect, and frame error are supported. An 8-deep FIFO allows
much greater CPU service latencies to be tolerated. Note that
hardware handshaking is not supported. This is not commonly
used and can be implemented with a UDB-based UART in the
system, if required.
SPI Mode: The SPI mode supports full Motorola SPI, TI Secure
Simple Pairing (SSP) (essentially adds a start pulse that is used
to synchronize SPI Codecs), and National Microwire (half-duplex
form of SPI). The SPI block can use the FIFO for transmit and
receive.
GPIO
PSoC 4200_BL has 36 GPIOs. The GPIO block implements the
following:
Eight drive strength modes:
Analog input mode (input and output buffers disabled)
Input only
Weak pull-up with strong pull-down
Strong pull-up with weak pull-down
Open drain with strong pull-down
Open drain with strong pull-up
Strong pull-up with strong pull-down
Weak pull-up with weak pull-down
Input threshold select (CMOS or LVTTL)
Pins 0 and 1 of Port 5 are overvoltage-tolerant pins
Individual control of input and output buffer enabling/disabling
in addition to drive-strength modes
Hold mode for latching previous state (used for retaining the
I/O state in Deep Sleep and Hibernate modes)
Selectable slew rates for dV/dt-related noise control to improve
EMI
The pins are organized in logical entities called ports, which are
8-bit in width. During power-on and reset, the blocks are forced
to the disable state so as not to crowbar any inputs and/or cause
excess turn-on current. A multiplexing network known as a
high-speed I/O matrix (HSIOM) is used to multiplex between
various signals that may connect to an I/O pin. Pin locations for
fixed-function peripherals are also fixed to reduce internal multi-
plexing complexity (these signals do not go through the DSI
network). DSI signals are not affected by this and any pin may
be routed to any UDB through the DSI network.
Data output and pin-state registers store, respectively, the values
to be driven on the pins and the states of the pins themselves.
Every I/O pin can generate an interrupt if so enabled and each
I/O port has an interrupt request (IRQ) and interrupt service
routine (ISR) vector associated with it (5 for PSoC 4200_BL).
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PSoC® 4: 4200_BLE
Family Datasheet
Document Number: 002-23053 Rev. ** Page 10 of 49
Special-Function Peripherals
LCD Segment Drive
PSoC 4200_BL has an LCD controller, which can drive up to four
commons and up to 32 segments. It uses full digital methods to
drive the LCD segments requiring no generation of internal LCD
voltages. The two methods used are referred to as digital corre-
lation and PWM.
The digital correlation method modulates the frequency and
levels of the common and segment signals to generate the
highest RMS voltage across a segment to light it up or to keep
the RMS signal zero. This method is good for STN displays but
may result in reduced contrast with TN (cheaper) displays.
The PWM method drives the panel with PWM signals to effec-
tively use the capacitance of the panel to provide the integration
of the modulated pulse-width to generate the desired LCD
voltage. This method results in higher power consumption but
can result in better results when driving TN displays. LCD
operation is supported during Deep Sleep mode, refreshing a
small display buffer (four bits; one 32-bit register per port).
CapSense
CapSense is supported on all pins in PSoC 4200_BL through a
CapSense Sigma-Delta (CSD) block that can be connected to
any pin through an analog mux bus that any GPIO pin can be
connected to via an Analog switch. CapSense function can thus
be provided on any pin or group of pins in a system under
software control. A Component is provided for the CapSense
block to make it easy for the user.
The shield voltage can be driven on another mux bus to provide
liquid-tolerance capability. Liquid tolerance is provided by driving
the shield electrode in phase with the sense electrode to keep
the shield capacitance from attenuating the sensed input.
The CapSense block has two IDACs which can be used for
general purposes if CapSense is not being used (both IDACs are
available in that case) or if CapSense is used without liquid
tolerance (one IDAC is available).
@chREss nnnnnnnnnnnnnnnnnn
PSoC® 4: 4200_BLE
Family Datasheet
Document Number: 002-23053 Rev. ** Page 11 of 49
Pinouts
Table 1 shows the pin list for the PSoC 4200_BL device. Port 3 consists of the high-speed analog inputs for the SAR mux. All pins
support CSD CapSense and analog mux bus connections.
Table 1. PSoC 4200_BL Pin List (QFN Package)
Pin Name Type Description
1 VDDD POWER 1.71-V to 5.5-V digital supply
2 XTAL32O/P6.0 CLOCK 32.768-kHz crystal
3 XTAL32I/P6.1 CLOCK 32.768-kHz crystal or external clock input
4 XRES RESET Reset, active LOW
5 P4.0 GPIO Port 4 Pin 0, lcd, csd
6 P4.1 GPIO Port 4 Pin 1, lcd, csd
7 P5.0 GPIO Port 5 Pin 0, lcd, csd
8 P5.1 GPIO Port 5 Pin 1, lcd, csd
9 VSSD GROUND Digital ground
10 VDDR POWER 1.9-V to 5.5-V radio supply
11 GANT1 GROUND Antenna shielding ground
12 ANT ANTENNA Antenna pin
13 GANT2 GROUND Antenna shielding ground
14 VDDR POWER 1.9-V to 5.5-V radio supply
15 VDDR POWER 1.9-V to 5.5-V radio supply
16 XTAL24I CLOCK 24-MHz crystal or external clock input
17 XTAL24O CLOCK 24-MHz crystal
18 VDDR POWER 1.9-V to 5.5-V radio supply
19 P0.0 GPIO Port 0 Pin 0, lcd, csd
20 P0.1 GPIO Port 0 Pin 1, lcd, csd
21 P0.2 GPIO Port 0 Pin 2, lcd, csd
22 P0.3 GPIO Port 0 Pin 3, lcd, csd
23 VDDD POWER 1.71-V to 5.5-V digital supply
24 P0.4 GPIO Port 0 Pin 4, lcd, csd
25 P0.5 GPIO Port 0 Pin 5, lcd, csd
26 P0.6 GPIO Port 0 Pin 6, lcd, csd
27 P0.7 GPIO Port 0 Pin 7, lcd, csd
28 P1.0 GPIO Port 1 Pin 0, lcd, csd
29 P1.1 GPIO Port 1 Pin 1, lcd, csd
30 P1.2 GPIO Port 1 Pin 2, lcd, csd
31 P1.3 GPIO Port 1 Pin 3, lcd, csd
32 P1.4 GPIO Port 1 Pin 4, lcd, csd
33 P1.5 GPIO Port 1 Pin 5, lcd, csd
34 P1.6 GPIO Port 1 Pin 6, lcd, csd
35 P1.7 GPIO Port 1 Pin 7, lcd, csd
36 VDDA POWER 1.71-V to 5.5-V analog supply
37 P2.0 GPIO Port 2 Pin 0, lcd, csd
38 P2.1 GPIO Port 2 Pin 1, lcd, csd
39 P2.2 GPIO Port 2 Pin 2, lcd, csd
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PSoC® 4: 4200_BLE
Family Datasheet
Document Number: 002-23053 Rev. ** Page 12 of 49
40 P2.3 GPIO Port 2 Pin 3, lcd, csd
41 P2.4 GPIO Port 2 Pin 4, lcd, csd
42 P2.5 GPIO Port 2 Pin 5, lcd, csd
43 P2.6 GPIO Port 2 Pin 6, lcd, csd
44 P2.7 GPIO Port 2 Pin 7, lcd, csd
45 VREF REF 1.024-V reference
46 VDDA POWER 1.71-V to 5.5-V analog supply
47 P3.0 GPIO Port 3 Pin 0, lcd, csd
48 P3.1 GPIO Port 3 Pin 1, lcd, csd
49 P3.2 GPIO Port 3 Pin 2, lcd, csd
50 P3.3 GPIO Port 3 Pin 3, lcd, csd
51 P3.4 GPIO Port 3 Pin 4, lcd, csd
52 P3.5 GPIO Port 3 Pin 5, lcd, csd
53 P3.6 GPIO Port 3 Pin 6, lcd, csd
54 P3.7 GPIO Port 3 Pin 7, lcd, csd
55 VSSA GROUND Analog ground
56 VCCD POWER Regulated 1.8-V supply, connect to 1.3-µF capacitor.
57 EPAD GROUND Ground paddle for the QFN package
Table 2. PSoC 4200_BL Pin List (WLCSP Package)
Pin Name Type Description
A1 NC NC Do not connect
A2 VREF REF 1.024-V reference
A3 VSSA GROUND Analog ground
A4 P3.3 GPIO Port 3 Pin 3, analog/digital/lcd/csd
A5 P3.7 GPIO Port 3 Pin 7, analog/digital/lcd/csd
A6 VSSD GROUND Digital ground
A7 VSSA GROUND Analog ground
A8 VCCD POWER Regulated 1.8-V supply, connect to 1-F capacitor
A9 VDDD POWER 1.71-V to 5.5-V digital supply
B1 NB NO BALL No Ball
B2 P2.3 GPIO Port 2 Pin 3, analog/digital/lcd/csd
B3 VSSA GROUND Analog ground
B4 P2.7 GPIO Port 2 Pin 7, analog/digital/lcd/csd
B5 P3.4 GPIO Port 3 Pin 4, analog/digital/lcd/csd
B6 P3.5 GPIO Port 3 Pin 5, analog/digital/lcd/csd
B7 P3.6 GPIO Port 3 Pin 6, analog/digital/lcd/csd
B8 XTAL32I/P6.1 CLOCK 32.768-kHz crystal or external clock input
B9 XTAL32O/P6.0 CLOCK 32.768-kHz crystal
C1 NC NC Do not connect
Table 1. PSoC 4200_BL Pin List (QFN Package) (continued)
Pin Name Type Description
@chREss nnnnnnnnnnnnnnnnnn
PSoC® 4: 4200_BLE
Family Datasheet
Document Number: 002-23053 Rev. ** Page 13 of 49
C2 VSSA GROUND Analog ground
C3 P2.2 GPIO Port 2 Pin 2, analog/digital/lcd/csd
C4 P2.6 GPIO Port 2 Pin 6, analog/digital/lcd/csd
C5 P3.0 GPIO Port 3 Pin 0, analog/digital/lcd/csd
C6 P3.1 GPIO Port 3 Pin 1, analog/digital/lcd/csd
C7 P3.2 GPIO Port 3 Pin 2, analog/digital/lcd/csd
C8 XRES RESET Reset, active LOW
C9 P4.0 GPIO Port 4 Pin 0, analog/digital/lcd/csd
D1 NC NC Do not connect
D2 P1.7 GPIO Port 1 Pin 7, analog/digital/lcd/csd
D3 VDDA POWER 1.71-V to 5.5-V analog supply
D4 P2.0 GPIO Port 2 Pin 0, analog/digital/lcd/csd
D5 P2.1 GPIO Port 2 Pin 1, analog/digital/lcd/csd
D6 P2.5 GPIO Port 2 Pin 5, analog/digital/lcd/csd
D7 VSSD GROUND Digital ground
D8 P4.1 GPIO Port 4 Pin 1, analog/digital/lcd/csd
D9 P5.0 GPIO Port 5 Pin 0, analog/digital/lcd/csd
E1 NC NC Do not connect
E2 P1.2 GPIO Port 1 Pin 2, analog/digital/lcd/csd
E3 P1.3 GPIO Port 1 Pin 3, analog/digital/lcd/csd
E4 P1.4 GPIO Port 1 Pin 4, analog/digital/lcd/csd
E5 P1.5 GPIO Port 1 Pin 5, analog/digital/lcd/csd
E6 P1.6 GPIO Port 1 Pin 6, analog/digital/lcd/csd
E7 P2.4 GPIO Port 2 Pin 4, analog/digital/lcd/csd
E8 P5.1 GPIO Port 5 Pin 1, analog/digital/lcd/csd
E9 VSSD GROUND Digital ground
F1 NC NC Do not connect
F2 VSSD GROUND Digital ground
F3 P0.7 GPIO Port 0 Pin 7, analog/digital/lcd/csd
F4 P0.3 GPIO Port 0 Pin 3, analog/digital/lcd/csd
F5 P1.0 GPIO Port 1 Pin 0, analog/digital/lcd/csd
F6 P1.1 GPIO Port 1 Pin 1, analog/digital/lcd/csd
F7 VSSR GROUND Radio ground
F8 VSSR GROUND Radio ground
F9 VDDR POWER 1.9-V to 5.5-V radio supply
G1 NC NC Do not connect
G2 P0.6 GPIO Port 0 Pin 6, analog/digital/lcd/csd
G3 VDDD POWER 1.71-V to 5.5-V digital supply
G4 P0.2 GPIO Port 0 Pin 2, analog/digital/lcd/csd
G5 VSSD GROUND Digital ground
Table 2. PSoC 4200_BL Pin List (WLCSP Package) (continued)
Pin Name Type Description
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PSoC® 4: 4200_BLE
Family Datasheet
Document Number: 002-23053 Rev. ** Page 14 of 49
High-speed I/O matrix (HSIOM) is a group of high-speed
switches that routes GPIOs to the resources inside the device.
These resources include CapSense, TCPWMs, I2C, SPI, UART,
and LCD. HSIOM_PORT_SELx are 32-bit-wide registers that
control the routing of GPIOs. Each register controls one port; four
dedicated bits are assigned to each GPIO in the port. This
provides up to 16 different options for GPIO routing as shown in
Table 3.
G6 VSSR GROUND Radio ground
G7 VSSR GROUND Radio ground
G8 GANT GROUND Antenna shielding ground
G9 VSSR GROUND Radio ground
H1 NC NC Do not connect
H2 P0.5 GPIO Port 0 Pin 5, analog/digital/lcd/csd
H3 P0.1 GPIO Port 0 Pin 1, analog/digital/lcd/csd
H4 XTAL24O CLOCK 24-MHz crystal
H5 XTAL24I CLOCK 24-MHz crystal or external clock input
H6 VSSR GROUND Radio ground
H7 VSSR GROUND Radio ground
H8 ANT ANTENNA Antenna pin
J1 NC NC Do not connect
J2 P0.4 GPIO Port 0 Pin 4, analog/digital/lcd/csd
J3 P0.0 GPIO Port 0 Pin 0, analog/digital/lcd/csd
J4 VDDR POWER 1.9-V to 5.5-V radio supply
J7 VDDR POWER 1.9-V to 5.5-V radio supply
J8 NO CONNECT ––
Table 2. PSoC 4200_BL Pin List (WLCSP Package) (continued)
Pin Name Type Description
Table 3. HSIOM Port Settings
Value Description
0 Firmware-controlled GPIO
1Output is firmware-controlled, but Output Enable (OE)
is controlled from DSI.
2 Both output and OE are controlled from DSI.
3Output is controlled from DSI, but OE is
firmware-controlled.
4 Pin is a CSD sense pin
5 Pin is a CSD shield pin
6 Pin is connected to AMUXA
7 Pin is connected to AMUXB
8 Pin-specific Active function #0
9 Pin-specific Active function #1
10 Pin-specific Active function #2
11 Reserved
12 Pin is an LCD common pin
13 Pin is an LCD segment pin
14 Pin-specific Deep-Sleep function #0
15 Pin-specific Deep-Sleep function #1
Table 3. HSIOM Port Settings (continued)
Value Description
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PSoC® 4: 4200_BLE
Family Datasheet
Document Number: 002-23053 Rev. ** Page 15 of 49
The selection of peripheral function for different GPIO pins is given in Table 4.
Table 4. Port Pin Connections
Name Analog Digital
GPIO Active #0 Active #1 Active #2 Deep Sleep #0 Deep Sleep #1
P0.0 COMP0_INP GPIO TCPWM0_P[3] SCB1_UART_RX[1] SCB1_I2C_SDA[1] SCB1_SPI_MOSI[1]
P0.1 COMP0_INN GPIO TCPWM0_N[3] SCB1_UART_TX[1] SCB1_I2C_SCL[1] SCB1_SPI_MISO[1]
P0.2 GPIO TCPWM1_P[3] SCB1_UART_RTS[1] COMP0_OUT[0] SCB1_SPI_SS0[1]
P0.3 GPIO TCPWM1_N[3] SCB1_UART_CTS[1] COMP1_OUT[0] SCB1_SPI_SCLK[1]
P0.4 COMP1_INP GPIO TCPWM1_P[0] SCB0_UART_RX[1] EXT_CLK[0]/
ECO_OUT[0] SCB0_I2C_SDA[1] SCB0_SPI_MOSI[1]
P0.5 COMP1_INN GPIO TCPWM1_N[0] SCB0_UART_TX[1] SCB0_I2C_SCL[1] SCB0_SPI_MISO[1]
P0.6 GPIO TCPWM2_P[0] SCB0_UART_RTS[1] SWDIO[0] SCB0_SPI_SS0[1]
P0.7 GPIO TCPWM2_N[0] SCB0_UART_CTS[1] SWDCLK[0] SCB0_SPI_SCLK[1]
P1.0 CTBm1_OA0_INP GPIO TCPWM0_P[1] COMP0_OUT[1] WCO_OUT[2]
P1.1 CTBm1_OA0_INN GPIO TCPWM0_N[1] COMP1_OUT[1] SCB1_SPI_SS1
P1.2 CTBm1_OA0_OUT GPIO TCPWM1_P[1] SCB1_SPI_SS2
P1.3 CTBm1_OA1_OUT GPIO TCPWM1_N[1] SCB1_SPI_SS3
P1.4 CTBm1_OA1_INN GPIO TCPWM2_P[1] SCB0_UART_RX[0] SCB0_I2C_SDA[0] SCB0_SPI_MOSI[1]
P1.5 CTBm1_OA1_INP GPIO TCPWM2_N[1] SCB0_UART_TX[0] SCB0_I2C_SCL[0] SCB0_SPI_MISO[1]
P1.6 CTBm1_OA0_INP GPIO TCPWM3_P[1] SCB0_UART_RTS[0] SCB0_SPI_SS0[1]
P1.7 CTBm1_OA1_INP GPIO TCPWM3_N[1] SCB0_UART_CTS[0] SCB0_SPI_SCLK[1]
P2.0 CTBm0_OA0_INP GPIO SCB0_SPI_SS1
P2.1 CTBm0_OA0_INN GPIO SCB0_SPI_SS2
P2.2 CTBm0_OA0_OUT GPIO WAKEUP SCB0_SPI_SS3
P2.3 CTBm0_OA1_OUT GPIO WCO_OUT[1]
P2.4 CTBm0_OA1_INN GPIO
P2.5 CTBm0_OA1_INP GPIO
P2.6 CTBm0_OA0_INP GPIO
P2.7 CTBm0_OA1_INP GPIO EXT_CLK[1]/ECO_OUT[
1] ––
P3.0 SARMUX_0 GPIO TCPWM0_P[2] SCB0_UART_RX[2] SCB0_I2C_SDA[2]
P3.1 SARMUX_1 GPIO TCPWM0_N[2] SCB0_UART_TX[2] SCB0_I2C_SCL[2]
P3.2 SARMUX_2 GPIO TCPWM1_P[2] SCB0_UART_RTS[2]
P3.3 SARMUX_3 GPIO TCPWM1_N[2] SCB0_UART_CTS[2]
P3.4 SARMUX_4 GPIO TCPWM2_P[2] SCB1_UART_RX[2] SCB1_I2C_SDA[2]
P3.5 SARMUX_5 GPIO TCPWM2_N[2] SCB1_UART_TX[2] SCB1_I2C_SCL[2]
P3.6 SARMUX_6 GPIO TCPWM3_P[2] SCB1_UART_RTS[2]
P3.7 SARMUX_7 GPIO TCPWM3_N[2] SCB1_UART_CTS[2] WCO_OUT[0]
P4.0 CMOD GPIO TCPWM0_P[0] SCB1_UART_RTS[0] SCB1_SPI_MOSI[0]
P4.1 CTANK GPIO TCPWM0_N[0] SCB1_UART_CTS[0] SCB1_SPI_MISO[0]
P5.0 GPIO TCPWM3_P[0] SCB1_UART_RX[0] EXTPA_EN SCB1_I2C_SDA[0] SCB1_SPI_SS0[0]
P5.1 GPIO TCPWM3_N[0] SCB1_UART_TX[0] EXT_CLK[2]/ECO_OUT[
2] SCB1_I2C_SCL[0] SCB1_SPI_SCLK[0]
P6.0_XTAL32O GPIO –
P6.1_XTAL32I GPIO –
E :1 ?
PSoC® 4: 4200_BLE
Family Datasheet
Document Number: 002-23053 Rev. ** Page 16 of 49
The possible pin connections are shown for all analog and digital peripherals (except the radio, LCD, and CSD blocks, which were
shown in Table 1). A typical system application connection diagram is shown in Figure 7.
Figure 7. System Application Connection Diagram
Power
The PSoC 4200_BL device can be supplied from batteries with
a voltage range of 1.9 V to 5.5 V by directly connecting to the
digital supply (VDDD), analog supply (VDDA), and radio supply
(VDDR) pins. Internal LDOs in the device regulate the supply
voltage to the required levels for different blocks. The device has
one regulator for the digital circuitry and separate regulators for
radio circuitry for noise isolation. Analog circuits run directly from
the analog supply (VDDA) input. The device uses separate
regulators for Deep Sleep and Hibernate (lowered power supply
and retention) modes to minimize the power consumption. The
radio stops working below 1.9 V, but the device continues to
function down to 1.71 V without RF.
Bypass capacitors must be used from VDDx (x = A, D, or R) to
ground. The typical practice for systems in this frequency range
is to use a capacitor in the 1-µF range in parallel with a smaller
capacitor (for example, 0.1 µF). Note that these are simply rules
of thumb and that, for critical applications, the PCB layout, lead
inductance, and the bypass capacitor parasitic should be
simulated to design and obtain optimal bypassing.
SWDIO
SWDCLK
VDDR
VDDD
VDDR
VDDA
VDDA
VDDR
VDDD
C6
C1
1.0 uF
U1
PSoC 4XXX_BLE
56-QFN
VDDD
1
XTAL32O/P6.0
2
XTAL32I/P6.1
3
XRES
4
P4.0
5
P5.0
7
P5.1
8
VSS
9
VDDR
10
GANT1
11
ANT
12
GANT2
13
VDDR
14
P4.1
6
VDDR
15
XTAL24I
16
XTAL24O
17
VDDR
18
VDDD
23
P0.0
19
P0.1
20
P0.2
21
P0.3
22
P0.4
24
P0.5
25
P0.6
26
P0.7
27
P1.0
28
P1.1 29
P1.2 30
P1.3 31
P1.4 32
P1.5 33
P1.6 34
P1.7 35
P2.0 37
P2.1 38
P2.2 39
P2.3 40
P2.4 41
P2.5 42
P2.6 43
P2.7 44
VREF 45
VDDA 46
P3.0 47
P3.1 48
P3.2 49
P3.3 50
P3.4 51
P3.5 52
P3.6 53
P3.7 54
VSSA 55
VCCD 56
VDDA 36
EPAD 57
Y2
32.768KHz
12
C4
18 pF
C3
36 pF
C2
1.0 uF
Y1
24MHz
1
2
3
4
L1
ANTENNA
1
1
2
2
C5
1.3
47 pF
24 pF
Power Supply Bypass Capacitors
VDDD The internal bandgap may be bypassed
with a 1-µF to 10-µF.
VDDA 0.1-µF ceramic at each pin plus bulk
capacitor 1-µF to 10-µF.
VDDR 0.1-µF ceramic at each pin plus bulk
capacitor 1-µF to 10-µF.
VCCD 1.3-µF ceramic capacitor at the VCCD pin.
VREF (optional) The internal bandgap may be bypassed
with a 1-µF to 10-µF capacitor.
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PSoC® 4: 4200_BLE
Family Datasheet
Document Number: 002-23053 Rev. ** Page 17 of 49
Development Support
The PSoC 4200_BL family has a rich set of documentation,
development tools, and online resources to assist you during
your development process. Visit www.cypress.com/go/psoc4ble
to find out more.
Documentation
A suite of documentation supports the PSoC 4200_BL family to
ensure that you can find answers to your questions quickly. This
section contains a list of some of the key documents.
Software User Guide: A step-by-step guide for using PSoC
Creator. The software user guide shows you how the PSoC
Creator build process works in detail, how to use source control
with PSoC Creator, and much more.
Component Datasheets: The flexibility of PSoC allows the
creation of new peripherals (Components) long after the device
has gone into production. Component datasheets provide all of
the information needed to select and use a particular
Component, including a functional description, API documen-
tation, example code, and AC/DC specifications.
Application Notes: PSoC application notes discuss a particular
application of PSoC in depth; examples include creating
standard and custom BLE profiles. Application notes often
include example projects in addition to the application note
document.
Technical Reference Manual: The Technical Reference Manual
(TRM) contains all the technical detail you need to use a PSoC
device, including a complete description of all PSoC registers.
The TRM is available in the Documentation section at
www.cypress.com/psoc4.
Online
In addition to print documentation, the Cypress PSoC forums
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PSoC® 4: 4200_BLE
Family Datasheet
Document Number: 002-23053 Rev. ** Page 18 of 49
Electrical Specifications
Absolute Maximum Ratings
Device-Level Specifications
All specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
Note
1. Usage above the absolute maximum conditions listed in Tab l e 5 may cause permanent damage to the device. Exposure to absolute maximum conditions for extended
periods of time may affect device reliability. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature
Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification.
Table 5. Absolute Maximum Ratings[1]
Spec ID# Parameter Description Min Typ Max Units Details/
Conditions
SID1 VDDD_ABS
Analog, digital, or radio supply
relative to VSS (VSSD = VSSA) –0.5 – 6 V Absolute max
SID2 VCCD_ABS
Direct digital core voltage input
relative to VSSD
–0.5 – 1.95 V Absolute max
SID3 VGPIO_ABS GPIO voltage –0.5 VDD +0.5 V Absolute max
SID4 IGPIO_ABS Maximum current per GPIO –25 25 mA Absolute max
SID5 IGPIO_injection
GPIO injection current, Max for VIH
> VDDD, and Min for VIL < VSS
–0.5 0.5 mA Absolute max, current
injected per pin
BID57 ESD_HBM Electrostatic discharge human body
model 2200 – V
BID58 ESD_CDM Electrostatic discharge charged
device model 500 – V
BID61 LU Pin current for latch-up –200 200 mA
Table 6. DC Specifications
Spec ID# Parameter Description Min Typ Max Units Details/
Conditions
SID6 VDD
Power supply input voltage (VDDA =
VDDD = VDD)1.8 5.5 V With regulator enabled
SID7 VDD
Power supply input voltage unregulated
(VDDA = VDDD = VDD)1.71 1.8 1.89 V Internally unregulated
Supply
SID8 VDDR Radio supply voltage (Radio ON) 1.9 5.5 V
SID8A VDDR Radio supply voltage (Radio OFF) 1.71 5.5 V
SID9 VCCD
Digital regulator output voltage (for core
logic) –1.8– V
SID10 CVCCD
Digital regulator output bypass
capacitor 1 1.3 1.6 µF X5R ceramic or better
Active Mode, VDD = 1.71 V to 5.5 V
SID13 IDD3 Execute from flash; CPU at 3 MHz 2.1 mA T = 25 °C,
VDD = 3.3 V
SID14 IDD4 Execute from flash; CPU at 3 MHz mA T = –40 C to 85 °C
SID15 IDD5 Execute from flash; CPU at 6 MHz 2.5 mA T = 25 °C,
VDD = 3.3 V
SID16 IDD6 Execute from flash; CPU at 6 MHz mA T = –40 °C to 85 °C
SID17 IDD7 Execute from flash; CPU at 12 MHz 4 mA T = 25 °C,
VDD = 3.3 V
SID18 IDD8 Execute from flash; CPU at 12 MHz mA T = –40 °C to 85 °C
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PSoC® 4: 4200_BLE
Family Datasheet
Document Number: 002-23053 Rev. ** Page 19 of 49
SID19 IDD9 Execute from flash; CPU at 24 MHz 7.1 mA T = 25 °C,
VDD = 3.3 V
SID20 IDD10 Execute from flash; CPU at 24 MHz mA T = –40 °C to 85 °C
SID21 IDD11 Execute from flash; CPU at 48 MHz 13.4 mA T = 25 °C,
VDD = 3.3 V
SID22 IDD12 Execute from flash; CPU at 48 MHz mA T = –40 °C to 85 °C
Sleep Mode, VDD = 1.8 to 5.5 V
SID23 IDD13 IMO on mA
T = 25 °C,
VDD = 3.3 V, SYSCLK =
3MHz
Sleep Mode, VDD and VDDR = 1.9 to 5.5 V
SID24 IDD14 ECO on –––mA
T = 25 °C,
VDD = 3.3 V, SYSCLK =
3 MHz
Deep Sleep Mode, VDD = 1.8 to 3.6 V
SID25 IDD15 WDT with WCO on 1.5 µA T = 25 °C,
VDD = 3.3 V
SID26 IDD16 WDT with WCO on µA T = –40 °C to 85 °C
Deep Sleep Mode, VDD = 3.6 to 5.5 V
SID27 IDD17 WDT with WCO on µA T = 25 °C,
VDD = 5 V
SID28 IDD18 WDT with WCO on µA T = –40 °C to 85 °C
Deep Sleep Mode, VDD = 1.71 to 1.89 V (Regulator Bypassed)
SID29 IDD19 WDT with WCO on µA T = 25 °C
SID30 IDD20 WDT with WCO on µA T = –40 °C to 85 °C
Deep Sleep Mode, VDD = 1.8 to 3.6 V
SID31 IDD21 Opamp on µA T = 25 °C,
VDD = 3.3 V
SID32 IDD22 Opamp on µA T = –40 °C to 85 °C
Deep Sleep Mode, VDD = 3.6 to 5.5 V
SID33 IDD23 Opamp on µA T = 25 °C,
VDD = 5 V
SID34 IDD24 Opamp on µA T = –40 °C to 85 °C
Deep Sleep Mode, VDD = 1.71 to 1.89 V (Regulator Bypassed)
SID35 IDD25 Opamp on µA T = 25 °C
SID36 IDD26 Opamp on µA T = –40 °C to 85 °C
Hibernate Mode, VDD = 1.8 to 3.6 V
SID37 IDD27 GPIO and reset active 150 nA T = 25 °C,
VDD = 3.3V
SID38 IDD28 GPIO and reset active nA T = –40 °C to 85 °C
Hibernate Mode, VDD = 3.6 to 5.5 V
SID39 IDD29 GPIO and reset active nA T = 25 °C,
VDD = 5 V
SID40 IDD30 GPIO and reset active nA T = –40 °C to 85 °C
Hibernate Mode, VDD = 1.71 to 1.89 V (Regulator Bypassed)
Table 6. DC Specifications (continued)
Spec ID# Parameter Description Min Typ Max Units Details/
Conditions
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PSoC® 4: 4200_BLE
Family Datasheet
Document Number: 002-23053 Rev. ** Page 20 of 49
SID41 IDD31 GPIO and reset active nA T = 25 °C
SID42 IDD32 GPIO and reset active nA T = –40 °C to 85 °C
Stop Mode, VDD = 1.8 to 3.6 V
SID43 IDD33 Stop mode current (VDD)–20nA
T = 25 °C,
VDD = 3.3 V
SID44 IDD34 Stop mode current (VDDR) – 40 –- nA T = 25 °C,
VDDR = 3.3 V
SID45 IDD35 Stop mode current (VDD) nA T = –40 °C to 85 °C
SID46 IDD36 Stop mode current (VDDR) –––nA
T = –40 °C to 85 °C,
VDDR = 1.9 V to 3.6 V
Stop Mode, VDD = 3.6 to 5.5 V
SID47 IDD37 Stop mode current (VDD) –––nA
T = 25 °C,
VDD = 5 V
SID48 IDD38 Stop mode current (VDDR) –––nA
T = 25 °C,
VDDR = 5 V
SID49 IDD39 Stop mode current (VDD) nA T = –40 °C to 85 °C
SID50 IDD40 Stop mode current (VDDR) nA T = –40 °C to 85 °C
Stop Mode, VDD = 1.71 to 1.89 V (Regulator Bypassed)
SID51 IDD41 Stop mode current (VDD) –––nAT = 25 °C
SID52 IDD42 Stop mode current (VDD) nA T = –40 °C to 85 °C
Table 6. DC Specifications (continued)
Spec ID# Parameter Description Min Typ Max Units Details/
Conditions
Table 7. AC Specifications
Spec ID# Parameter Description Min Typ Max Units Details/
Conditions
SID53 FCPU CPU frequency DC 48 MHz 1.71 V VDD 5.5 V
SID54 TSLEEP Wakeup from Sleep mode 0 µs Guaranteed by
characterization
SID55 TDEEPSLEEP Wakeup from Deep Sleep mode 25 µs
24-MHz IMO.
Guaranteed by
characterization.
SID56 THIBERNATE Wakeup from Hibernate mode 0.7 ms Guaranteed by
characterization
SID57 TSTOP Wakeup from Stop mode 2.2 ms Guaranteed by
characterization
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PSoC® 4: 4200_BLE
Family Datasheet
Document Number: 002-23053 Rev. ** Page 21 of 49
GPIO
Note
2. VIH must not exceed VDDD + 0.2 V.
Table 8. GPIO DC Specifications
Spec ID# Parameter Description Min Typ Max Units Details/
Conditions
SID58 VIH Input voltage HIGH threshold 0.7 × VDD – – V CMOS input
SID59 VIL Input voltage LOW threshold 0.3 × VDD V CMOS input
SID60 VIH LVTTL input, VDD < 2.7V 0. V
DD – - V
SID61 VIL LVTTL input, VDD < 2.7 V 0.3× VDD V–
SID62 VIH LVTTL input, VDD >= 2.7 V 2.0 - V
SID63 VIL LVTTL input, VDD >= 2.7 V 0.8 V
SID64 VOH Output voltage HIGH level VDD –0.6 – V Ioh = 4-mA at
3.3-V VDD
SID65 VOH Output voltage HIGH level VDD –0.5 – – V Ioh = 1-mA at
1.8-V VDD
SID66 VOL Output voltage LOW level 0.6 V Iol = 8-mA at
3.3-V VDD
SID67 VOL Output voltage LOW level 0.6 V Iol = 4-mA at
1.8-V VDD
SID68 VOL Output voltage LOW level 0.4 V Iol = 3-mA at
3.3-V VDD
SID69 Rpullup Pull-up resistor 3.5 5.6 8.5 k
SID70 Rpulldown Pull-down resistor 3.5 5.6 8.5 k
SID71 IIL Input leakage current (absolute value) 2 nA 25 °C,
VDD = 3.3 V
SID72 IIL_CTBM Input leakage on CTBm input pins 4 nA
SID73 CIN Input capacitance 7 pF
SID74 Vhysttl Input hysteresis LVTTL 25 40 mV VDD > 2.7 V
SID75 Vhyscmos Input hysteresis CMOS 0.05 × VDD – – mV
SID76 Idiode Current through protection diode to
VDD/VSS
– – 100 µA
SID77 ITOT_GPIO
Maximum total source or sink chip
current – – 200 mA
Table 9. GPIO AC Specifications
Spec ID# Parameter Description Min Typ Max Units Details/
Conditions
SID78 TRISEF Rise time in Fast-Strong mode 2 12 ns 3.3-V VDDD,
CLOAD = 25-pF
SID79 TFALLF Fall time in Fast-Strong mode 2 12 ns 3.3-V VDDD,
CLOAD = 25-pF
SID80 TRISES Rise time in Slow-Strong mode 10 60 3.3-V VDDD,
CLOAD = 25-pF
SID81 TFALLS Fall time in Slow-Strong mode 10 60 3.3-V VDDD,
CLOAD = 25-pF
SID82 FGPIOUT1
GPIO Fout; 3.3 V VDD 5.5 V.
Fast-Strong mode ––33MHz
90/10%, 25-pF load, 60/40
duty cycle
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PSoC® 4: 4200_BLE
Family Datasheet
Document Number: 002-23053 Rev. ** Page 22 of 49
XRES
SID83 FGPIOUT2
GPIO Fout; 1.7 VVDD 3.3 V.
Fast-Strong mode ––16.7MHz
90/10%, 25-pF load, 60/40
duty cycle
SID84 FGPIOUT3
GPIO Fout; 3.3 V VDD 5.5 V.
Slow-Strong mode ––7MHz
90/10%, 25-pF load, 60/40
duty cycle
SID85 FGPIOUT4
GPIO Fout; 1.7 V VDD 3.3 V.
Slow-Strong mode ––3.5MHz
90/10%, 25-pF load, 60/40
duty cycle
SID86 FGPIOIN
GPIO input operating frequency;
1.71 V VDD 5.5 V 48 MHz 90/10% VIO
Table 9. GPIO AC Specifications (continued)
Spec ID# Parameter Description Min Typ Max Units Details/
Conditions
Table 10. OVT GPIO DC Specifications (P5_0 and P5_1 Only)
Spec ID# Parameter Description Min Typ Max Units Details/
Conditions
SID71A IIL
Input leakage current (absolute value),
VIH > VDD
10 µA 25 °C,
VDD = 0 V, VIH= 3.0 V
SID66A VOL Output voltage LOW level 0.4 V IOL = 20-mA, VDD >
2.9-V
Table 11. OVT GPIO AC Specifications (P5_0 and P5_1 Only)
Spec ID# Parameter Description Min Typ Max Units Details/
Conditions
SID78A TRISE_OVFS Output rise time in Fast-Strong mode 1.5 12 ns
25-pF load,
10%–90%,
VDD=3.3-V
SID79A TFALL_OVFS Output fall time in Fast-Strong mode 1.5 12 ns
25-pF load,
10%–90%,
VDD=3.3-V
SID80A TRISSS Output rise time in Slow-Strong mode 10 60 ns
25-pF load,
10%–90%,
VDD=3.3-V
SID81A TFALLSS Output fall time in Slow-Strong mode 10 60 ns
25-pF load,
10%–90%,
VDD=3.3-V
SID82A FGPIOUT1
GPIO FOUT
; 3.3 V ≤VDD 5.5 V
Fast-Strong mode ––24MHz
90/10%, 25-pF load,
60/40 duty cycle
SID83A FGPIOUT2
GPIO FOUT
; 1.71 V ≤VDD 3.3 V
Fast-Strong mode ––16MHz
90/10%, 25-pF load,
60/40 duty cycle
Table 12. XRES DC Specifications
Spec ID# Parameter Description Min Typ Max Units Details/
Conditions
SID87 VIH Input voltage HIGH threshold 0.7 × VDDD V CMOS input
SID88 VIL Input voltage LOW threshold 0.3 × VDDD V CMOS input
SID89 Rpullup Pull-up resistor 3.5 5.6 8.5 k
SID90 CIN Input capacitance 3 pF
SID91 VHYSXRES Input voltage hysteresis 100 mV
SID92 IDIODE
Current through protection diode to
VDDD/VSS
– 100 µA
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PSoC® 4: 4200_BLE
Family Datasheet
Document Number: 002-23053 Rev. ** Page 23 of 49
Analog Peripherals
Opamp
Table 13. XRES AC Specifications
Spec ID# Parameter Description Min Typ Max Units Details/Conditions
SID93 TRESETWIDTH Reset pulse width 1 µs
Table 14. Opamp Specifications
Spec ID# Parameter Description Min Typ Max Units Details/
Conditions
IDD (Opamp Block Current. VDD = 1.8 V. No Load)
SID94 IDD_HI Power = high 1000 1850 µA
SID95 IDD_MED Power = medium 500 950 µA
SID96 IDD_LOW Power = low 250 350 µA
GBW (Load = 20 pF, 0.1 mA. VDDA = 2.7 V)
SID97 GBW_HI Power = high 6 MHz
SID98 GBW_MED Power = medium 4 MHz
SID99 GBW_LO Power = low 1 MHz
IOUT_MAX (VDDA 2.7 V, 500 mV From Rail)
SID100 IOUT_MAX_HI Power = high 10 mA
SID101 IOUT_MAX_MID Power = medium 10 mA
SID102 IOUT_MAX_LO Power = low 5 mA
IOUT (VDDA = 1.71 V, 500 mV From Rail)
SID103 IOUT_MAX_HI Power = high 4 mA
SID104 IOUT_MAX_MID Power = medium 4 mA
SID105 IOUT_MAX_LO Power = low 2 mA
SID106 VIN Charge pump on, VDDA 2.7 V –0.05 VDDA – 0.2 V
SID107 VCM Charge pump on, VDDA 2.7 V –0.05 VDDA – 0.2 V
VOUT (VDDA 2.7 V)
SID108 VOUT_1 Power = high, ILOAD=10 mA 0.5 VDDA – 0.5 V
SID109 VOUT_2 Power = high, ILOAD=1 mA 0.2 VDDA – 0.2 V
SID110 VOUT_3 Power = medium, ILOAD=1 mA 0.2 VDDA – 0.2 V
SID111 VOUT_4 Power = low, ILOAD=0.1 mA 0.2 VDDA – 0.2 V
SID112 VOS_TR Offset voltage, trimmed 1 ±0.5 1 mV High mode
SID113 VOS_TR Offset voltage, trimmed ±1 mV Medium mode
SID114 VOS_TR Offset voltage, trimmed ±2 mV Low mode
SID115 VOS_DR_TR Offset voltage drift, trimmed –10 ±3 10 µV/C High mode
SID116 VOS_DR_TR Offset voltage drift, trimmed ±10 µV/C Medium mode
SID117 VOS_DR_TR Offset voltage drift, trimmed ±10 µV/C Low mode
SID118 CMRR DC 70 80 dB VDDD = 3.6-V
SID119 PSRR At 1 kHz, 100-mV ripple 70 85 dB VDDD = 3.6-V
Noise
SID120 VN1
Input referred, 1 Hz–1 GHz, power =
high – 94 µVrms
SID121 VN2 Input referred, 1-kHz, power = high 72 nV/rtHz
A A CYPRESS EHHEnnEDInInNcanw VOFFSEU VOFFSETZ DDD DDD ‘cMPz
PSoC® 4: 4200_BLE
Family Datasheet
Document Number: 002-23053 Rev. ** Page 24 of 49
SID122 VN3 Input referred, 10-kHz, power = high 28 nV/rtHz
SID123 VN4 Input referred, 100-kHz, power = high 15 nV/rtHz
SID124 CLOAD
Stable up to maximum load. Perfor-
mance specs at 50 pF – 125 pF
SID125 Slew_rate Cload = 50 pF, Power = High,
VDDA 2.7 V 6– –V/µsec
SID126 T_op_wake From disable to enable, no external RC
dominating –300 – µsec
Comp_mode (Comparator Mode; 50-mV Drive, TRISE = TFALL (Approx.)
SID127 TPD1 Response time; power = high 150 nsec
SID128 TPD2 Response time; power = medium 400 nsec
SID129 TPD3 Response time; power = low 2000 nsec
SID130 Vhyst_op Hysteresis 10 mV
Deep Sleep (Deep Sleep mode operation is only guaranteed for VDDA > 2.5 V)
SID131 GBW_DS Gain bandwidth product 50 kHz
SID132 IDD_DS Current 15 µA
SID133 Vos_DS Offset voltage 5 mV
SID134 Vos_dr_DS Offset voltage drift 20 µV/°C
SID135 Vout_DS Output voltage 0.2 VDD–0.2 V
SID136 Vcm_DS Common mode voltage 0.2 VDD–1.8 V
Table 14. Opamp Specifications (continued)
Spec ID# Parameter Description Min Typ Max Units Details/
Conditions
Note
3. ULP LCOMP operating conditions:
- VDDD 2.6 V-5.5 V for datasheet temp range < 0 °C
- VDDD 1.8 V-5.5 V for datasheet temp range 0 °C
Table 15. Comparator DC Specifications[3]
Spec ID# Parameter Description Min Typ Max Units Details/
Conditions
SID140 VOFFSET1 Input offset voltage, Factory trim ±10 mV
SID141 VOFFSET2 Input offset voltage, Custom trim ±6 mV
SID141A VOFFSET3
Input offset voltage, ultra-low-power
mode –±12– mV
VDDD 2.6 V for
Temp < 0°C,
VDDD 1.8 V for
Temp > 0 °C
SID142 VHYST
Hysteresis when enabled. Common
Mode voltage range from 0 to VDD –1 – 10 35 mV
SID143 VICM1
Input common mode voltage in normal
mode 0–
VDDD
–0.1 V Modes 1 and 2
SID144 VICM2
Input common mode voltage in low power
mode 0– V
DDD V–
SID145 VICM3
Input common mode voltage in ultra low
power mode 0–
VDDD
–1.15 V
VDDD 2.6 V for
Temp < 0°C,
VDDD 1.8 V for
Temp > 0 °C
SID146 CMRR Common mode rejection ratio 50 dB VDDD 2.7 V
SID147 CMRR Common mode rejection ratio 42 dB VDDD 2.7 V
SID148 ICMP1 Block current, normal mode 400 µA
SID149 ICMP2 Block current, low power mode 100 µA
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PSoC® 4: 4200_BLE
Family Datasheet
Document Number: 002-23053 Rev. ** Page 25 of 49
Temperature Sensor
SAR ADC
SID150 ICMP3 Block current in ultra low-power mode 6 µA
VDDD 2.6 V for
Temp < 0°C,
VDDD 1.8 V for
Temp > 0 °C
SID151 ZCMP DC input impedance of comparator 35 M
Table 15. Comparator DC Specifications[3] (continued)
Spec ID# Parameter Description Min Typ Max Units Details/
Conditions
Note
4. ULP LCOMP operating conditions:
- VDDD 2.6 V-5.5 V for datasheet temp range < 0 °C
- VDDD 1.8 V-5.5 V for datasheet temp range 0 °C
Table 16. Comparator AC Specifications[4]
Spec ID# Parameter Description Min Typ Max Units Details/
Conditions
SID152 TRESP1
Response time, normal mode, 50-mV
overdrive 38 – ns 50-mV overdrive
SID153 TRESP2
Response time, low power mode, 50-mV
overdrive 70 – ns 50-mV overdrive
SID154 TRESP3
Response time, ultra-low-power mode,
50-mV overdrive 2.3 – µs
200-mV overdrive.
VDDD 2.6 V for
Temp < 0°C,
VDDD 1.8 V for
Temp > 0 °C
Table 17. Temperature Sensor Specifications
Spec ID# Parameter Description Min Typ Max Units Details/Conditions
SID155 TSENSACC Temperature sensor accuracy –5 ±1 5 °C –40 to +85 °C
Table 18. SAR ADC DC Specifications
Spec ID# Parameter Description Min Typ Max Units Details/Conditions
SID156 A_RES Resolution 12 bits
SID157 A_CHNIS_S Number of channels - single-ended 16 8 full-speed
SID158 A-CHNKS_D Number of channels - differential 8 Diff inputs use
neighboring I/O
SID159 A-MONO Monotonicity – Yes
SID160 A_GAINERR Gain error ±0.1 % With external
reference.
SID161 A_OFFSET Input offset voltage 2 mV Measured with 1-V
VREF
SID162 A_ISAR Current consumption 1 mA
SID163 A_VINS Input voltage range - single-ended VSS –V
DDA V–
SID164 A_VIND Input voltage range - differential VSS – VDDA V–
SID165 A_INRES Input resistance 2.2 k
SID166 A_INCAP Input capacitance 10 pF
SID312 VREFSAR Trimmed internal reference to SAR –1 1 % Percentage of Vbg
(1.024-V)
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Family Datasheet
Document Number: 002-23053 Rev. ** Page 26 of 49
CSD
Table 19. SAR ADC AC Specifications
Spec ID# Parameter Description Min Typ Max Units Details/
Conditions
SID167 A_psrr Power supply rejection ratio 70 dB Measured at 1-V
reference
SID168 A_cmrr Common mode rejection ratio 66 dB
SID169 A_samp Sample rate 1 Msps
SID313 Fsarintref SAR operating speed without external
ref. bypass – – 100 Ksps 12-bit resolution
SID170 A_snr Signal-to-noise ratio (SNR) 65 dB Fin = 10 kHz
SID171 A_bw Input bandwidth without aliasing A_samp/2 kHz
SID172 A_inl Integral non linearity. VDD = 1.71 to
5.5 V, 1 Msps –1.7 2 LSB Vref = 1 V to VDD
SID173 A_INL Integral non linearity. VDDD = 1.71 to
3.6 V, 1 Msps –1.5 1.7 LSB Vref = 1.71 V to VDD
SID174 A_INL Integral non linearity. VDD = 1.71 to
5.5 V, 500 Ksps –1.5 1.7 LSB Vref = 1 V to VDD
SID175 A_dnl Differential non linearity. VDD = 1.71 to
5.5 V, 1 Msps –1 2.2 LSB Vref = 1 V to VDD
SID176 A_DNL Differential non linearity. VDD = 1.71 to
3.6 V, 1 Msps –1 2 LSB Vref = 1.71 V to VDD
SID177 A_DNL Differential non linearity. VDD = 1.71 to
5.5 V, 500 Ksps –1 2.2 LSB Vref = 1 V to VDD
SID178 A_thd Total harmonic distortion –65 dB Fin = 10 kHz
Table 20. CSD Block Specifications
Spec ID# Parameter Description Min Typ Max Units Details/
Conditions
SID179 VCSD Voltage range of operation 1.71 – 5.5 V
SID180 IDAC1 DNL for 8-bit resolution –1 1 LSB
SID181 IDAC1 INL for 8-bit resolution –3 3 LSB
SID182 IDAC2 DNL for 7-bit resolution –1 1 LSB
SID183 IDAC2 INL for 7-bit resolution –3 3 LSB
SID184 SNR Ratio of counts of finger to noise 5 Ratio
Capacitance range of 9 to
35 pF, 0.1 pF sensitivity.
Radio is not operating
during the scan
SID185 IDAC1_CRT1
Output current of IDAC1 (8 bits) in
High range – 612 µA
SID186 IDAC1_CRT2
Output current of IDAC1 (8 bits) in
Low range – 306 µA
SID187 IDAC2_CRT1
Output current of IDAC2 (7 bits) in
High range – 305 µA
SID188 IDAC2_CRT2
Output current of IDAC2 (7 bits) in
Low range – 153 µA
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Family Datasheet
Document Number: 002-23053 Rev. ** Page 27 of 49
Digital Peripherals
Timer
Counter
Pulse Width Modulation (PWM)
Table 21. Timer DC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID189 ITIM1 Block current consumption at 3 MHz 50 µA 16-bit timer
SID190 ITIM2 Block current consumption at 12 MHz 175 µA 16-bit timer
SID191 ITIM3 Block current consumption at 48 MHz 712 µA 16-bit timer
Table 22. Timer AC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID192 TTIMFREQ Operating frequency FCLK –48MHz –
SID193 TCAPWINT Capture pulse width (internal) 2 × TCLK ––ns –
SID194 TCAPWEXT Capture pulse width (external) 2 × TCLK ––ns –
SID195 TTIMRES Timer resolution TCLK ––ns –
SID196 TTENWIDINT Enable pulse width (internal) 2 × TCLK ––ns –
SID197 TTENWIDEXT Enable pulse width (external) 2 × TCLK ––ns –
SID198 TTIMRESWINT Reset pulse width (internal) 2 × TCLK ––ns –
SID199 TTIMRESEXT Reset pulse width (external) 2 × TCLK ––ns –
Table 23. Counter DC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID200 ICTR1 Block current consumption at 3 MHz 50 µA 16-bit counter
SID201 ICTR2 Block current consumption at 12 MHz 175 µA 16-bit counter
SID202 ICTR3 Block current consumption at 48 MHz 712 µA 16-bit counter
Table 24. Counter AC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID203 TCTRFREQ Operating frequency FCLK –48MHz –
SID204 TCTRPWINT Capture pulse width (internal) 2 × TCLK ––ns –
SID205 TCTRPWEXT Capture pulse width (external) 2 × TCLK ––ns –
SID206 TCTRES Counter Resolution TCLK ––ns –
SID207 TCENWIDINT Enable pulse width (internal) 2 × TCLK ––ns –
SID208 TCENWIDEXT Enable pulse width (external) 2 × TCLK ––ns –
SID209 TCTRRESWINT Reset pulse width (internal) 2 × TCLK ––ns –
SID210 TCTRRESWEXT Reset pulse width (external) 2 × TCLK –– ns
Table 25. PWM DC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID211 IPWM1 Block current consumption at 3 MHz 50 µA 16-bit PWM
SID212 IPWM2 Block current consumption at 12 MHz 175 µA 16-bit PWM
SID213 IPWM3 Block current consumption at 48 MHz 741 µA 16-bit PWM
LC VB‘AS LC VB‘AS
PSoC® 4: 4200_BLE
Family Datasheet
Document Number: 002-23053 Rev. ** Page 28 of 49
I2C
LCD Direct Drive
Table 26. PWM AC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID214 TPWMFREQ Operating frequency FCLK –48MHz –
SID215 TPWMPWINT Pulse width (internal) 2 × TCLK ––ns –
SID216 TPWMEXT Pulse width (external) 2 × TCLK ––ns –
SID217 TPWMKILLINT Kill pulse width (internal) 2 × TCLK ––ns –
SID218 TPWMKILLEXT Kill pulse width (external) 2 × TCLK ––ns –
SID219 TPWMEINT Enable pulse width (internal) 2 × TCLK ––ns –
SID220 TPWMENEXT Enable pulse width (external) 2 × TCLK ––ns –
SID221 TPWMRESWINT Reset pulse width (internal) 2 × TCLK ––ns –
SID222 TPWMRESWEXT Reset pulse width (external) 2 × TCLK ––ns –
Table 27. Fixed I2C DC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID223 II2C1 Block current consumption at 100 kHz 50 µA–
SID224 II2C2 Block current consumption at 400 kHz 155 µA–
SID225 II2C3 Block current consumption at 1 Mbps 390 µA–
SID226 II2C4 I2C enabled in Deep Sleep mode 1.4 µA–
Table 28. Fixed I2C AC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID227 FI2C1 Bit rate 1 Mbps
Table 29. LCD Direct Drive DC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID228 ILCDLOW Operating current in low-power mode 17.5 µA 16 × 4 small segment
display at 50 Hz
SID229 CLCDCAP
LCD capacitance per segment/common
driver 500 5000 pF
SID230 LCDOFFSET Long-term segment offset 20 mV
SID231 ILCDOP1
LCD system operating current
VBIAS = 5 V. –2mA
32 × 4 segments.
50 Hz at 25 °C
SID232 ILCDOP2
LCD system operating current.
VBIAS = 3.3 V –2mA
32 × 4 segments
50 Hz at 25 °C
Table 30. LCD Direct Drive AC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID233 FLCD LCD frame rate 10 50 150 Hz
Table 31. Fixed UART DC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID234 IUART1 Block current consumption at 100 kbps 55 µA–
SID235 IUART2
Block current consumption at
1000 kbps – 360 µA–
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Family Datasheet
Document Number: 002-23053 Rev. ** Page 29 of 49
SPI Specifications
Memory
Table 32. Fixed UART AC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID236 FUART Bit rate 1 Mbps
Table 33. Fixed SPI DC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID237 ISPI1 Block current consumption at 1 Mbps 360 µA
SID238 ISPI2 Block current consumption at 4 Mbps 560 µA
SID239 ISPI3 Block current consumption at 8 Mbps 600 µA
Table 34. Fixed SPI AC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID240 FSPI
SPI operating frequency (master; 6X
oversampling) –– 8MHz
Table 35. Fixed SPI Master Mode AC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID241 TDMO MOSI valid after Sclock driving edge 18 ns
SID242 TDSI
MISO valid before Sclock capturing edge.
Full clock, late MISO sampling used 20 – – ns Full clock, late MISO
sampling
SID243 THMO Previous MOSI data hold time 0 ns Referred to Slave
capturing edge
Table 36. Fixed SPI Slave Mode AC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID244 TDMI MOSI valid before Sclock capturing edge 40 ns
SID245 TDSO MISO valid after Sclock driving edge 42 + 3
× TCPU
ns –
SID246 TDSO_ext
MISO valid after Sclock driving edge in
external clock mode – – 53 ns VDD < 3.0 V
SID247 THSO Previous MISO data hold time 0 ns
SID248 TSSELSCK SSEL valid to first SCK valid edge 100 ns
Table 37. Flash DC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID249 VPE Erase and program voltage 1.71 5.5 V
SID309 TWS48 Number of Wait states at
32–48 MHz 2– CPU execution from
flash
SID310 TWS32 Number of Wait states at
16–32 MHz 1–CPU execution from
flash
SID311 TWS16 Number of Wait states for
0–16 MHz 0– CPU execution from
flash
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System Resources
Power-on-Reset (POR)
Note
5. It can take as much as 20 milliseconds to write to flash. During this time, the device should not be reset, or flash operations will be interrupted and cannot be relied
on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs.
Make certain that these are not inadvertently activated.
Table 38. Flash AC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID250 TROWWRITE[5] Row (block) write time (erase and
program) – – 20 ms
Row (block) = 128 bytes
for 128 KB flash devices
Row (block) = 256 bytes
for 256 KB flash devices
SID251 TROWERASE[5] Row erase time 13 ms
SID252 TROWPROGRAM[5] Row program time after erase 7 ms
SID253 TBULKERASE[5] Bulk erase time (256 KB) 35 ms
SID254 TDEVPROG[5] Total device program time ––50
seconds 256 KB
SID254A 25 128 KB
SID255 FEND Flash endurance 100 K cycles
SID256 FRET
Flash retention. TA 55 °C, 100 K
P/E cycles 20 – years
SID257 FRET2
Flash retention. TA 85 °C, 10 K
P/E cycles 10 – – years
Table 39. POR DC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID258 VRISEIPOR Rising trip voltage 0.80 1.45 V
SID259 VFALLIPOR Falling trip voltage 0.75 1.40 V
SID260 VIPORHYST Hysteresis 15 200 mV
Table 40. POR AC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID264 TPPOR_TR
PPOR response time in Active
and Sleep modes ––1µs –
Table 41. Brown-Out Detect
Spec ID# Parameter Description Min Typ Max Units Details/
Conditions
SID261 VFALLPPOR
BOD trip voltage in Active and Sleep
modes 1.64 – – V
SID262 VFALLDPSLP BOD trip voltage in Deep Sleep mode 1.4 V
Table 42. Hibernate Reset
Spec ID# Parameter Description Min Typ Max Units Details/
Conditions
SID263 VHBRTRIP BOD trip voltage in Hibernate mode 1.1 V
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Family Datasheet
Document Number: 002-23053 Rev. ** Page 31 of 49
Voltage Monitors
SWD Interface
Internal Main Oscillator
Table 43. Voltage Monitor DC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID265 VLVI1 LVI_A/D_SEL[3:0] = 0000b 1.71 1.75 1.79 V
SID266 VLVI2 LVI_A/D_SEL[3:0] = 0001b 1.76 1.80 1.85 V
SID267 VLVI3 LVI_A/D_SEL[3:0] = 0010b 1.85 1.90 1.95 V
SID268 VLVI4 LVI_A/D_SEL[3:0] = 0011b 1.95 2.00 2.05 V
SID269 VLVI5 LVI_A/D_SEL[3:0] = 0100b 2.05 2.10 2.15 V
SID270 VLVI6 LVI_A/D_SEL[3:0] = 0101b 2.15 2.20 2.26 V
SID271 VLVI7 LVI_A/D_SEL[3:0] = 0110b 2.24 2.30 2.36 V
SID272 VLVI8 LVI_A/D_SEL[3:0] = 0111b 2.34 2.40 2.46 V
SID273 VLVI9 LVI_A/D_SEL[3:0] = 1000b 2.44 2.50 2.56 V
SID274 VLVI10 LVI_A/D_SEL[3:0] = 1001b 2.54 2.60 2.67 V
SID2705 VLVI11 LVI_A/D_SEL[3:0] = 1010b 2.63 2.70 2.77 V
SID276 VLVI12 LVI_A/D_SEL[3:0] = 1011b 2.73 2.80 2.87 V
SID277 VLVI13 LVI_A/D_SEL[3:0] = 1100b 2.83 2.90 2.97 V
SID278 VLVI14 LVI_A/D_SEL[3:0] = 1101b 2.93 3.00 3.08 V
SID279 VLVI15 LVI_A/D_SEL[3:0] = 1110b 3.12 3.20 3.28 V
SID280 VLVI16 LVI_A/D_SEL[3:0] = 1111b 4.39 4.50 4.61 V
SID281 LVI_IDD Block current 100 µA
Table 44. Voltage Monitor AC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID282 TMONTRIP Voltage monitor trip time 1 µs
Table 45. SWD Interface Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID283 F_SWDCLK1 3.3 V VDD 5.5 V 14 MHz SWDCLK 1/3 CPU
clock frequency
SID284 F_SWDCLK2 1.71 V VDD 3.3 V 7 MHz SWDCLK 1/3 CPU
clock frequency
SID285 T_SWDI_SETUP T = 1/f SWDCLK 0.25 × T ns
SID286 T_SWDI_HOLD T = 1/f SWDCLK 0.25 × T ns
SID287 T_SWDO_VALID T = 1/f SWDCLK 0.5 × T ns
SID288 T_SWDO_HOLD T = 1/f SWDCLK 1 ns
Table 46. IMO DC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID289 IIMO1 IMO operating current at 48 MHz 1000 µA
SID290 IIMO2 IMO operating current at 24 MHz 325 µA
SID291 IIMO3 IMO operating current at 12 MHz 225 µA
SID292 IIMO4 IMO operating current at 6 MHz 180 µA
SID293 IIMO5 IMO operating current at 3 MHz 150 µA
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Internal Low-Speed Oscillator
Table 47. IMO AC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID296 FIMOTOL3
Frequency variation from 3 to
48 MHz ––±2%
With API-called
calibration
SID297 FIMOTOL3 IMO startup time 12 µs
Table 48. ILO DC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID298 IILO2 ILO operating current at 32 kHz 0.3 1.05 µA
Table 49. ILO AC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID299 TSTARTILO1 ILO startup time 2 ms
SID300 FILOTRIM1 32-kHz trimmed frequency 15 32 50 kHz
Table 50. External Clock Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID301 ExtClkFreq External clock input frequency 0 48 MHz CMOS input level only
SID302 ExtClkDuty Duty cycle; Measured at VDD/2 45 55 % CMOS input level only
Table 51. UDB AC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
Data Path performance
SID303 FMAX-TIMER
Max frequency of 16-bit timer in a
UDB pair ––48MHz –
SID304 FMAX-ADDER
Max frequency of 16-bit adder in a
UDB pair ––48MHz –
SID305 FMAX_CRC
Max frequency of 16-bit CRC/PRS in
a UDB pair ––48MHz –
PLD Performance in UDB
SID306 FMAX_PLD
Max frequency of 2-pass PLD function
in a UDB pair ––48MHz –
Clock to Output Performance
SID307 TCLK_OUT_UDB1
Prop. delay for clock in to data out at
25 °C, Typical –15 – ns
SID308 TCLK_OUT_UDB2
Prop. delay for clock in to data out,
Worst case –25 – ns
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Family Datasheet
Document Number: 002-23053 Rev. ** Page 33 of 49
Table 52. BLE Subsystem
Spec ID# Parameter Description Min Typ Max Units Details/
Conditions
RF Receiver Specification
SID340
RXS, IDLE
RX sensitivity with idle transmitter –89 dBm
SID340A RX sensitivity with idle transmitter
excluding Balun loss –91 dBm Guaranteed by design
simulation
SID341 RXS, DIRTY RX sensitivity with dirty transmitter –87 –70 dBm RF-PHY Specification
(RCV-LE/CA/01/C)
SID342 RXS, HIGHGAIN RX sensitivity in high-gain mode with
idle transmitter – –91 – dBm
SID343 PRXMAX Maximum input power –10 –1 dBm RF-PHY Specification
(RCV-LE/CA/06/C)
SID344 CI1
Co-channel interference,
Wanted signal at –67 dBm and Inter-
ferer at FRX
–921dB
RF-PHY Specification
(RCV-LE/CA/03/C)
SID345 CI2
Adjacent channel interference
Wanted signal at –67 dBm and Inter-
ferer at FRX ±1 MHz
–315dB
RF-PHY Specification
(RCV-LE/CA/03/C)
SID346 CI3
Adjacent channel interference
Wanted signal at –67 dBm and Inter-
ferer at FRX ±2 MHz
–29 dB RF-PHY Specification
(RCV-LE/CA/03/C)
SID347 CI4
Adjacent channel interference
Wanted signal at –67 dBm and Inter-
ferer at FRX ±3 MHz
–39 dB RF-PHY Specification
(RCV-LE/CA/03/C)
SID348 CI5
Adjacent channel interference
Wanted Signal at –67 dBm and Inter-
ferer at Image frequency (FIMAGE)
–20 dB RF-PHY Specification
(RCV-LE/CA/03/C)
SID349 CI6
Adjacent channel interference
Wanted signal at –67 dBm and Inter-
ferer at Image frequency (FIMAGE ±
1MHz)
–30 dB RF-PHY Specification
(RCV-LE/CA/03/C)
SID350 OBB1
Out-of-band blocking,
Wanted signal at –67 dBm and Inter-
ferer at F = 30–2000 MHz
–30 –27 dBm RF-PHY Specification
(RCV-LE/CA/04/C)
SID351 OBB2
Out-of-band blocking,
Wanted signal at –67 dBm and Inter-
ferer at F = 2003–2399 MHz
–35 –27 dBm RF-PHY Specification
(RCV-LE/CA/04/C)
SID352 OBB3
Out-of-band blocking,
Wanted signal at –67 dBm and Inter-
ferer at F = 2484–2997 MHz
–35 –27 dBm RF-PHY Specification
(RCV-LE/CA/04/C)
SID353 OBB4
Out-of-band blocking,
Wanted signal a –67 dBm and Inter-
ferer at F = 3000–12750 MHz
–30 –27 dBm RF-PHY Specification
(RCV-LE/CA/04/C)
SID354 IMD
Intermodulation performance
Wanted signal at –64 dBm and 1-Mbps
BLE, third, fourth, and fifth offset
channel
–50 dBm RF-PHY Specification
(RCV-LE/CA/05/C)
SID355 RXSE1 Receiver spurious emission
30 MHz to 1.0 GHz –57 dBm
100-kHz measurement
bandwidth
ETSI EN300 328 V1.8.1
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Family Datasheet
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SID356 RXSE2 Receiver spurious emission
1.0 GHz to 12.75 GHz –47 dBm
1-MHz measurement
bandwidth
ETSI EN300 328 V1.8.1
RF Transmitter Specifications
SID357 TXP, ACC RF power accuracy ±1 dB
SID358 TXP, RANGE RF power control range 20 dB
SID359 TXP, 0dBm Output power, 0-dB Gain setting (PA7) 0 dBm
SID360 TXP, MAX Output power, maximum power setting
(PA10) –3–dBm –
SID361 TXP, MIN Output power, minimum power setting
(PA1) –18 – dBm
SID362 F2AVG Average frequency deviation for
10101010 pattern 185 kHz RF-PHY Specification
(TRM-LE/CA/05/C)
SID363 F1AVG Average frequency deviation for
11110000 pattern 225 250 275 kHz RF-PHY Specification
(TRM-LE/CA/05/C)
SID364 EO Eye opening = F2AVG/F1AVG 0.8 – RF-PHY Specification
(TRM-LE/CA/05/C)
SID365 FTX, ACC Frequency accuracy –150 150 kHz RF-PHY Specification
(TRM-LE/CA/06/C)
SID366 FTX, MAXDR Maximum frequency drift –50 50 kHz RF-PHY Specification
(TRM-LE/CA/06/C)
SID367 FTX, INITDR Initial frequency drift –20 20 kHz RF-PHY Specification
(TRM-LE/CA/06/C)
SID368 FTX, DR Maximum drift rate –20 20 kHz/
50 µs
RF-PHY Specification
(TRM-LE/CA/06/C)
SID369 IBSE1 In-band spurious emission at 2-MHz
offset –20 dBm RF-PHY Specification
(TRM-LE/CA/03/C)
SID370 IBSE2 In-band spurious emission at 3-MHz
offset ––-30dBm
RF-PHY Specification
(TRM-LE/CA/03/C)
SID371 TXSE1 Transmitter spurious emissions
(average), <1.0 GHz -55.5 dBm FCC-15.247
SID372 TXSE2 Transmitter spurious emissions
(average), >1.0 GHz -41.5 dBm FCC-15.247
RF Current Specifications
SID373 IRX Receive current in normal mode 18.7 mA
SID373A IRX_RF Radio receive current in normal mode 16.4 mA Measured at VDDR
SID374 IRX, HIGHGAIN Receive current in high-gain mode 21.5 mA
SID375 ITX, 3dBm TX current at 3-dBm setting (PA10) 20 mA
SID376 ITX, 0dBm TX current at 0-dBm setting (PA7) 16.5 mA
SID376A ITX_RF, 0dBm Radio TX current at 0 dBm setting
(PA7) 15.6 mA Measured at VDDR
SID376B ITX_RF, 0dBm Radio TX current at 0 dBm excluding
Balun loss 14.2 mA Guaranteed by design
simulation
SID377 ITX,-3dBm TX current at –3-dBm setting (PA4) 15.5 mA
Table 52. BLE Subsystem (continued)
Spec ID# Parameter Description Min Typ Max Units Details/
Conditions
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Family Datasheet
Document Number: 002-23053 Rev. ** Page 35 of 49
SID378 ITX,-6dBm TX current at –6-dBm setting (PA3) 14.5 mA
SID379 ITX,-12dBm TX current at –12-dBm setting (PA2) 13.2 mA
SID380 ITX,-18dBm TX current at –18-dBm setting (PA1) 12.5 mA
SID380A Iavg_1sec, 0dBm Average current at 1-second BLE
connection interval 17.1 – µA
TXP: 0 dBm; ±20-ppm
master and slave clock
accuracy.
SID380B Iavg_4sec, 0dBm Average current at 4-second BLE
connection interval –6.1– µA
TXP: 0 dBm; ±20-ppm
master and slave clock
accuracy.
General RF Specifications
SID381 FREQ RF operating frequency 2400 2482 MHz
SID382 CHBW Channel spacing 2 MHz
SID383 DR On-air data rate 1000 kbps
SID384 IDLE2TX BLE.IDLE to BLE. TX transition time 120 140 µs
SID385 IDLE2RX BLE.IDLE to BLE. RX transition time 75 120 µs
RSSI Specifications
SID386 RSSI, ACC RSSI accuracy ±5 dB
SID387 RSSI, RES RSSI resolution 1 dB
SID388 RSSI, PER RSSI sample period 6 µs
Table 52. BLE Subsystem (continued)
Spec ID# Parameter Description Min Typ Max Units Details/
Conditions
Table 53. ECO Specifications
Spec ID# Parameter Description Min Typ Max Units Details/
Conditions
SID389 FECO Crystal frequency 24 MHz
SID390 FTOL Frequency tolerance –50 50 ppm
SID391 ESR Equivalent series resistance 60
SID392 PD Drive level 100 µW
SID393 TSTART1 Startup time (Fast Charge on) 850 µs
SID394 TSTART2 Startup time (Fast Charge off) 3 ms
SID395 CLLoad capacitance 8 pF
SID396 C0 Shunt capacitance 1.1 pF
SID397 IECO Operating current 1400 µA
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Table 54. WCO Specifications
Spec ID# Parameter Description Min Typ Max Units Details/
Conditions
SID398 FWCO Crystal frequency 32.768 kHz
SID399 FTOL Frequency tolerance 50 ppm
SID400 ESR Equivalent series resistance 50 k
SID401 PD Drive level 1 µW
SID402 TSTART Startup time 500 ms
SID403 CLCrystal load capacitance 6 12.5 pF
SID404 C0 Crystal shunt capacitance 1.35 pF
SID405 IWCO1
Operating current (High-Power
mode) –– 8µA
SID406 IWCO2
Operating current (Low-Power
mode) ––2.6µA –
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Family Datasheet
Document Number: 002-23053 Rev. ** Page 37 of 49
Ordering Information
The PSoC 4200_BL part numbers and features are listed in Tab l e 5 5 .
Table 55. PSoC 4200_BL Part Numbers
Product Family
MPN
Max CPU Speed (MHz)
BLE subsystem
Flash (KB)
SRAM (KB)
UDB
Opamp
CapSense
TMG (Gestures)
Direct LCD Drive
12-bit SAR ADC
DMA
LP Comparators
TCPWM Blocks
SCB Blocks
GPIO
Package
Temperature Range
PSoC 4200_BL
CY8C4247LQI-BL473 48 4.1 128 16 4 4 1 Msps 2 4 2 36 QFN 85 °C
CY8C4247FNI-BL473 48 4.1 128 16 4 4 1 Msps 2 4 2 36 CSP 85 °C
CY8C4247LQI-BL453 48 4.1 128 16 4 4 1 1 Msps 2 4 2 36 QFN 85 °C
CY8C4247LQI-BL463 48 4.1 128 16 4 4 1 1 Msps 2 4 2 36 QFN 85 °C
CY8C4247LQI-BL483 48 4.1 128 16 4 4 1 1 1 Msps 2 4 2 36 QFN 85 °C
CY8C4247LQI-BL493 48 4.1 128 16 4 4 1 1 1 1 Msps 2 4 2 36 QFN 85 °C
CY8C4247FNI-BL483 48 4.1 128 16 4 4 1 1 1 Msps 2 4 2 36 68-CSP 85 °C
CY8C4247FNI-BL493 48 4.1 128 16 4 4 1 1 1 1 Msps 2 4 2 36 68-CSP 85 °C
CY8C4247FNQ-BL483 48 4.1 128 16 4 4 1 1 1 Msps 2 4 2 36 68-CSP 105 °C
CY8C4247LQQ-BL483 48 4.1 128 16 4 4 1 1 1 Msps 2 4 2 36 QFN 105 °C
CY8C4247FLI-BL493 48 4.1 128 16 4 4 1 1 1 1 Msps 2 4 2 36 Thin
68-CSP
85 °C
CY8C4248LQI-BL473 48 4.1 256 32 4 4 1 Msps 1 2 4 2 36 QFN 85 °C
CY8C4248LQI-BL453 48 4.1 256 32 4 4 1 1 Msps 1 2 4 2 36 QFN 85 °C
CY8C4248LQI-BL483 48 4.1 256 32 4 4 1 1 1 Msps 1 2 4 2 36 QFN 85 °C
CY8C4248FNI-BL483 48 4.1 256 32 4 4 1 1 1 Msps 1 2 4 2 36 76-CSP 85 °C
CY8C4248FLI-BL483 48 4.1 256 32 4 4 1 1 1 Msps 1 2 4 2 36 Thin
76-CSP
85 °C
CY8C4248LQI-BL543 48 4.2 256 32 2 1 Msps 1 4 2 36 QFN 85 °C
CY8C4248FNI-BL543 48 4.2 256 32 2 1 Msps 1 4 2 36 76-CSP 85 °C
CY8C4248LQI-BL573 48 4.2 256 32 4 4 1 Msps 1 2 4 2 36 QFN 85 °C
CY8C4248FNI-BL573 48 4.2 256 32 4 4 1 Msps 1 2 4 2 36 76-CSP 85 °C
CY8C4248LQI-BL553 48 4.2 256 32 4 4 1 1 Msps 1 2 4 2 36 QFN 85 °C
CY8C4248FNI-BL553 48 4.2 256 32 4 4 1 1 Msps 1 2 4 2 36 76-CSP 85 °C
CY8C4248LQI-BL563 48 4.2 256 32 4 4 1 1 Msps 1 2 4 2 36 QFN 85 °C
CY8C4248FNI-BL563 48 4.2 256 32 4 4 1 1 Msps 1 2 4 2 36 76-CSP 85 °C
CY8C4248LQI-BL583 48 4.2 256 32 4 4 1 1 1 Msps 1 2 4 2 36 QFN 85 °C
CY8C4248FNI-BL583 48 4.2 256 32 4 4 1 1 1 Msps 1 2 4 2 36 76-CSP 85 °C
CY8C4248FLI-BL583 48 4.2 256 32 4 4 1 1 1 Msps 1 2 4 2 36 Thin
76-CSP
85 °C
CY8C4248LQQ-BL583 48 4.2 256 32 4 4 1 1 1 Msps 1 2 4 2 36 QFN 105 °C
CY8C4248FNQ-BL583 48 4.2 256 32 4 4 1 1 1 Msps 1 2 4 2 36 76-CSP 105 °C
CY8C4248LQI-BL593 48 4.2 256 32 4 4 1 1 1 1 Msps 1 2 4 2 36 QFN 85 °C
CY8C4248FNI-BL593 48 4.2 256 32 4 4 1 1 1 1 Msps 1 2 4 2 36 76-CSP 85 °C
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PSoC® 4: 4200_BLE
Family Datasheet
Document Number: 002-23053 Rev. ** Page 38 of 49
PSoC 4 devices follow the part numbering convention described in the following table. All fields are single-character alphanumeric (0,
1, 2, …, 9, A,B, …, Z) unless stated otherwise.
Ordering Code Definitions
The Field Values are listed in the following table:
Architecture
Cypress Prefix
Family within Architecture
Speed Grade
Flash Capacity
Package Code
Temperature Range
Attributes Code
4: PSoC 4
4: 48MHz
8 : 256 KB
LQ : QFN
I : Industrial
Example CY8C 4 A EDCBFBLXYZ-
2 : 4200 Family
CY8 C
BLXYZ: Attributes
Field Description Values Meaning
CY8C Cypress Prefix
4 Architecture 4 PSoC 4
A Family within architecture 2 4200-BLE Family
B CPU Speed 4 48 MHz
C Flash Capacity 8, 7 256, 128 KB respectively
DE Package Code
FN WLCSP
LQ QFN
FL Thin CSP
F Temperature Range I Industrial
BLXYZ Attributes Code BL400-BL499 Bluetooth 4.1 compliant
BL500-BL599 Bluetooth 4.2 compliant
1chREss EHHEDnEnInInNnanw U U U 0 Package 0 Package 1) U 0 Package 0 Package 1)
PSoC® 4: 4200_BLE
Family Datasheet
Document Number: 002-23053 Rev. ** Page 39 of 49
Packaging
Table 56. Package Characteristics
Parameter Description Conditions Min Typ Max Units
TAOperating ambient temperature –40 25.00 105 °C
TJOperating junction temperature –40 125 °C
TJA Package JA (56-pin QFN) 16.9 – °C/watt
TJC Package JC (56-pin QFN) 9.7 – °C/watt
TJA Package JA (76-ball WLCSP) 20.1 °C/watt
TJC Package JC (76-ball WLCSP) 0.19 °C/watt
TJA Package JA (76-ball Thin WLCSP) 20.9 °C/watt
TJC Package JC (76-ball Thin WLCSP) 0.17 °C/watt
TJA Package JA (68-ball WLCSP) 16.6 °C/watt
TJC Package JC (68-ball WLCSP) 0.19 °C/watt
TJA Package JA (68-ball Thin WLCSP) 16.6 °C/watt
TJC Package JC (68-ball Thin WLCSP) 0.19 °C/watt
Table 57. Solder Reflow Peak Temperature
Package Maximum Peak
Temperature Maximum Time at Peak Temperature
All packages 260 °C 30 seconds
Table 58. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
Package MSL
56-pin QFN MSL 3
All WLCSP packages MSL 1
Table 59. Package Details
Spec ID Package Description
001-58740 Rev. *C 56-pin QFN 7.0 mm × 7.0 mm × 0.6 mm
001-96603 Rev. *A 76-ball WLCSP 4.04 mm × 3.87 mm × 0.55 mm
002-10658, Rev. ** 76-ball thin WLCSP 4.04 mm × 3.87 mm × 0.4 mm
001-92343 Rev. *A 68-ball WLCSP 3.52 mm × 3.91 mm × 0.55 mm
001-99408 Rev ** 68-ball Thin WLCSP 52 mm × 3.91 mm × 0.4 mm
achREss ' mum m Tum-Mum TOP VIEW _ i NOTES: 1.- SIDE VIEW BOTTOM VIEW
PSoC® 4: 4200_BLE
Family Datasheet
Document Number: 002-23053 Rev. ** Page 40 of 49
Figure 8. 56-Pin QFN 7 × 7 × 0.6 mm
The center pad on the QFN package should be connected to ground (VSS) for best mechanical, thermal, and electrical performance.
1. HATCH AREA IS SOLDERABLE EXPOSED PAD
NOTES:
2. BASED ON REF JEDEC # MO-248
3. ALL DIMENSIONS ARE IN MILLIMETERS
SIDE VIEW
TOP VIEW BOTTOM VIEW
001-58740 *C
Emsfiss EEEEEESE
PSoC® 4: 4200_BLE
Family Datasheet
Document Number: 002-23053 Rev. ** Page 41 of 49
WLCSP Compatibility
The PSoC 4XXX_BLE family has products with 128 KB (16KB SRAM) and 256 KB (32KB SRAM) Flash. Package pin-outs and sizes
are identical for the 56-pin QFN package but are different in one dimension for the 68-ball WLCSP.
The 256KB Flash product has an extra column of balls which are required for mechanical integrity purposes in the Chip-Scale package.
With consideration for this difference, the land pattern on the PCB may be designed such that either product may be used with no
change to the PCB design.
Figure 9 shows the 128KB and 256 KB Flash CSP packages.
Figure 9. 128KB and 256 KB Flash CSP Packages
The rightmost column of (all NC, No Connect) balls in the 256K BLE WLCSP is for mechanical integrity purposes. The package is
thus wider (3.2 mm versus 2.8 mm). All other dimensions are identical. Cypress will provide layout symbols for PCB layout.
The scheme in Figure 9 is implemented to design the PCB for the 256K BLE package with the appropriate space requirements thus
allowing use of either package at a later time without redesigning the Printed Circuit Board.
128K BLE 256K BLE
CONNECTED PADS
NC PADS
PACKAGE CENTER
PACK BOUNDARY
FIDUCIAL FOR 128K
FIDUCIAL FOR 256K
CYPRESS ' EHlEnnEnmkunmw 10p VIEW SIDE VIEW {illlivl pm I am aeuonzs k 35mm a NDTES: 1. REFERENCE JEDEc PUBLICATION as, DESIGN GUIDE 4.15 2. ALL DIMENSIONS ARE IN MILLIMETERS mp VIEw SIDE VIEW NOTES sumw VIEW 00000000 00000000 00000000 00000000 00000000 00000000 00000000 0000000 (3.29) In «u OD 000 (u w) « (22w) 4 aonom VIEW m mm a) [m]
PSoC® 4: 4200_BLE
Family Datasheet
Document Number: 002-23053 Rev. ** Page 42 of 49
Figure 10. 68-Ball WLCSP Package Outline
Figure 11. 68-Ball Thin WLCSP
001-92343 *A
H
G
F
E
D
C
B
A
12345678
12345678
H
G
F
E
D
C
B
A
TOP VIEW BOTTOM VIEW
SIDE VIEW
J
J
NOTES:
1. REFERENCE JEDEC PUBLICATION 95, DESIGN GUIDE 4.18
2. ALL DIMENSIONS ARE IN MILLIMETERS
001-99408 **
5-CYPRESS' ' mum m Iwnamw A mMENsmNS 5mm MM NOM MAX A r r a 55 m n u n 11 a 2‘ u a a? as: E ¢ 04 as: m a m as: a a m 35: MD a ME u N 75 g I: n 2: n is 0 2a .u n m use .E n m use SD u an 55: SE n 12‘ as: 0000 0000 0000 000' A 0000 0000 g 0000 0000 [1K 0000 0000 E:@ooo 0000 .000 0000 99‘ 900 Ha A SIDE VIEW ma ‘ m Dmmsm w MqurERs 1 50mm mm ammo" m m5 5mm swam 3 Rzmsmm sommm warm . swam w 5 NE W Mwa 5sz w NE 1:— New swam w m: m mm 5sz WE-E- mam N s M mam; popuwm mam Pusmous m mex smzmuxmz gnmm 17' ‘5 mswmnwz mm m mm M WE Wham WM 2 A'sD'AND 39m mammnmmmm mm: “mm 9mm: PosmoMonEcEmER sommm WE mam WHEN mm s m gamma a; mm“ w M om new. wmfiw WHEN mm s M W mam; mm“: w M om Row 'wummrw m AM comm BE mmzn “mm m m MK MN mm W wummwmmmms a mmmwmmmcamompopmm mm mm 9 Jzuzcspzcmmm W W
PSoC® 4: 4200_BLE
Family Datasheet
Document Number: 002-23053 Rev. ** Page 43 of 49
Figure 12. 76-Ball WLCSP Package Outline
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW,
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW,
DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
"SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
"e" REPRESENTS THE SOLDER BALL GRID PITCH.
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A
SOLDER BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.
"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED SOLDER
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK
8.
7.
6.
NOTES:
5.
4.
3.
2.
1. ALL DIMENSIONS ARE IN MILLIMETERS.
SD
b
eE
eD
ME
N
0.23
0.381 BSC
0.40 BSC
0.40 BSC
0.26
76
9
0.29
DIMENSIONS
D1
MD
E1
E
D
A
A1
SYMBOL
0.18
MIN.
-
3.20 BSC
3.20 BSC
9
4.04 BSC
3.87 BSC
NOM.
-0.55
0.24
MAX.
SE 0.321 BSC
0.21
METALIZED MARK, INDENTATION OR OTHER MEANS.
"SD" = eD/2 AND "SE" = eE/2.
PLANE PARALLEL TO DATUM C.
"SD" OR "SE" = 0.
SIZE MD X ME.
BALLS.
JEDEC SPECIFICATION NO. REF : N/A9.
PIN #1 MARK
A
B
J
H
G
F
E
D
C
B
A
987654321
J
H
G
F
E
D
C
B
A
987654321
D
E
TOP VIEW
SIDE VIEW
BOTTOM VIEW
E1
D1
76XØb 5
Ø0.06 C
M
C
Ø0.03 M
AB
C
A1
0.05 C
0.10 C
DETAIL
A
DETAIL A
eD
eE
SE
SD
7
6
6
A
001-96603 *B
5-CYPRESS' ' mum m Innnamw 000 0000 0000 000 A 0000 0000 Uqloooo oooo TLwooo 0000 6000 0000 D 000 0000 ? Q00 E JafE'A A DwMENsmNs 5mm MM mm MAX A , , a w N mm m am a a 37 asc E ‘ m asc m a 2n asc a a 2n asc MD 2 ME 2 N u z I: :22: n 25 023 .u n m asc .z n m asc sn 0 33‘ SE a 3n SIDE VIEW ma ‘ m nwmmz w WWW: 1 50mm mmmzsmm m m5 5mm swam: 3 Rzmsmm mmm mmm . swam 'Mn'ls NE W Mwassz M NE 1:— New swam w \swz m wuwx m WE-E- mum ms WE mam; mummy mmm mmm m mm SKEMDXME AMMW 17' ‘5 mmwwz mm m mm.“ WE Wham WM 2 Asp-w 39m wwwmsmm mm: “mm Dim”; PosmoMonEcEmER mm“ WE uquRwow mm mm .s m Gamma a; sommm w M cm W. 3vuw$r=n mm mm .s M W mam; smumm w M om Row 'sn' unrzANn'sE a: A." comm BE mmzn “mm m m MK MN mum WK mmmmammms a wcmsmmaxim.camompwmmmm mm
PSoC® 4: 4200_BLE
Family Datasheet
Document Number: 002-23053 Rev. ** Page 44 of 49
Figure 13. 76-Ball Thin WLCSP Package Outline
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW,
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW,
DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
"SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
"e" REPRESENTS THE SOLDER BALL GRID PITCH.
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A
SOLDER BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.
"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED SOLDER
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK
8.
7.
6.
NOTES:
5.
4.
3.
2.
1. ALL DIMENSIONS ARE IN MILLIMETERS.
SD
b
eE
eD
ME
N
0.22
0.381
0.40 BSC
0.40 BSC
0.25
76
9
0.28
DIMENSIONS
D1
MD
E1
E
D
A
A1
SYMBOL
0.072
MIN.
-
3.20 BSC
3.20 BSC
9
4.04 BSC
3.87 BSC
NOM.
-0.40
0.088
MAX.
SE 0.321
0.08
METALIZED MARK, INDENTATION OR OTHER MEANS.
"SD" = eD/2 AND "SE" = eE/2.
PLANE PARALLEL TO DATUM C.
"SD" OR "SE" = 0.
SIZE MD X ME.
BALLS.
PIN #1 MARK
A
B
J
H
G
F
E
D
C
B
A
987654321
J
H
G
F
E
D
C
B
A
987654321
D
E
TOP VIEW
SIDE VIEW
BOTTOM VIEW
E1
D1
76XØb 5
Ø0.06 C
M
C
Ø0.03 M
AB
C
A1
0.05 C
0.10 C
DETAIL
A
DETAIL A
eD
eE
SE
SD
7
6
6
A
002-10658 **
@chREss nnnnnnnnnnnnnnnnnn Arm®
PSoC® 4: 4200_BLE
Family Datasheet
Document Number: 002-23053 Rev. ** Page 45 of 49
Acronyms
Table 60. Acronyms Used in this Document
Acronym Description
abus analog local bus
ADC analog-to-digital converter
AG analog global
AHB AMBA (advanced microcontroller bus archi-
tecture) high-performance bus, an Arm data
transfer bus
ALU arithmetic logic unit
AMUXBUS analog multiplexer bus
API application programming interface
APSR application program status register
Arm®advanced RISC machine, a CPU architecture
ATM automatic thump mode
BW bandwidth
CAN Controller Area Network, a communications
protocol
CMRR common-mode rejection ratio
CPU central processing unit
CRC cyclic redundancy check, an error-checking
protocol
DAC digital-to-analog converter, see also IDAC, VDAC
DFB digital filter block
DIO digital input/output, GPIO with only digital
capabilities, no analog. See GPIO.
DMIPS Dhrystone million instructions per second
DMA direct memory access, see also TD
DNL differential nonlinearity, see also INL
DNU do not use
DR port write data registers
DSI digital system interconnect
DWT data watchpoint and trace
ECC error correcting code
ECO external crystal oscillator
EEPROM electrically erasable programmable read-only
memory
EMI electromagnetic interference
EMIF external memory interface
EOC end of conversion
EOF end of frame
EPSR execution program status register
ESD electrostatic discharge
ETM embedded trace macrocell
FIR finite impulse response, see also IIR
FPB flash patch and breakpoint
FS full-speed
GPIO general-purpose input/output, applies to a PSoC
pin
HVI high-voltage interrupt, see also LVI, LVD
IC integrated circuit
IDAC current DAC, see also DAC, VDAC
IDE integrated development environment
I2C, or IIC Inter-Integrated Circuit, a communications
protocol
IIR infinite impulse response, see also FIR
ILO internal low-speed oscillator, see also IMO
IMO internal main oscillator, see also ILO
INL integral nonlinearity, see also DNL
I/O input/output, see also GPIO, DIO, SIO, USBIO
IPOR initial power-on reset
IPSR interrupt program status register
IRQ interrupt request
ITM instrumentation trace macrocell
LCD liquid crystal display
LIN Local Interconnect Network, a communications
protocol.
LR link register
LUT lookup table
LVD low-voltage detect, see also LVI
LVI low-voltage interrupt, see also HVI
LVTTL low-voltage transistor-transistor logic
MAC multiply-accumulate
MCU microcontroller unit
MISO master-in slave-out
NC no connect
NMI nonmaskable interrupt
NRZ non-return-to-zero
NVIC nested vectored interrupt controller
NVL nonvolatile latch, see also WOL
opamp operational amplifier
PAL programmable array logic, see also PLD
Table 60. Acronyms Used in this Document (continued)
Acronym Description
nnnnnnnnnnnnnnnnnn @chREss PSoC®
PSoC® 4: 4200_BLE
Family Datasheet
Document Number: 002-23053 Rev. ** Page 46 of 49
PC program counter
PCB printed circuit board
PGA programmable gain amplifier
PHUB peripheral hub
PHY physical layer
PICU port interrupt control unit
PLA programmable logic array
PLD programmable logic device, see also PAL
PLL phase-locked loop
PMDD package material declaration data sheet
POR power-on reset
PRES precise power-on reset
PRS pseudo random sequence
PS port read data register
PSoC®Programmable System-on-Chip™
PSRR power supply rejection ratio
PWM pulse-width modulator
RAM random-access memory
RISC reduced-instruction-set computing
RMS root-mean-square
RTC real-time clock
RTL register transfer language
RTR remote transmission request
RX receive
SAR successive approximation register
SC/CT switched capacitor/continuous time
SCL I2C serial clock
SDA I2C serial data
S/H sample and hold
SINAD signal to noise and distortion ratio
SIO special input/output, GPIO with advanced
features. See GPIO.
SOC start of conversion
SOF start of frame
SPI Serial Peripheral Interface, a communications
protocol
SR slew rate
SRAM static random access memory
SRES software reset
SWD serial wire debug, a test protocol
Table 60. Acronyms Used in this Document (continued)
Acronym Description
SWV single-wire viewer
TD transaction descriptor, see also DMA
THD total harmonic distortion
TIA transimpedance amplifier
TRM technical reference manual
TTL transistor-transistor logic
TX transmit
UART Universal Asynchronous Transmitter Receiver, a
communications protocol
UDB universal digital block
USB Universal Serial Bus
USBIO USB input/output, PSoC pins used to connect to
a USB port
VDAC voltage DAC, see also DAC, IDAC
WDT watchdog timer
WOL write once latch, see also NVL
WRES watchdog timer reset
XRES external reset I/O pin
XTAL crystal
Table 60. Acronyms Used in this Document (continued)
Acronym Description
@chREss nnnnnnnnnnnnnnnnnn
PSoC® 4: 4200_BLE
Family Datasheet
Document Number: 002-23053 Rev. ** Page 47 of 49
Document Conventions
Units of Measure
Table 61. Units of Measure
Symbol Unit of Measure
°C degrees Celsius
dB decibel
fF femto farad
Hz hertz
KB 1024 bytes
kbps kilobits per second
Khr kilohour
kHz kilohertz
kkilo ohm
ksps kilosamples per second
LSB least significant bit
Mbps megabits per second
MHz megahertz
Mmega-ohm
Msps megasamples per second
µA microampere
µF microfarad
µH microhenry
µs microsecond
µV microvolt
µW microwatt
mA milliampere
ms millisecond
mV millivolt
nA nanoampere
ns nanosecond
nV nanovolt
ohm
pF picofarad
ppm parts per million
ps picosecond
s second
sps samples per second
sqrtHz square root of hertz
Vvolt
F306” (PSoc‘l’
PSoC® 4: 4200_BLE
Family Datasheet
Document Number: 002-23053 Rev. ** Page 48 of 49
Revision History
Description Title: PSoC® 4: 4200_BLE Family Datasheet Programmable System-on-Chip (PSoC®)
Document Number: 002-23053
Revision ECN Orig. of
Change Submission
Date Description of Change
** 6078076 PMAD/
WKA 02/22/2018 New datasheet
uuuuuuuuuu
Document Number: 002-23053 Rev. ** Revised February 22, 2018 Page 49 of 49
PSoC® 4: 4200_BLE
Family Datasheet
© Cypress Semiconductor Corporation, 2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including
any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide.
Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual
property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby
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reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either
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device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress does not assume any liability arising out of any security breach,
such as unauthorized access to or use of a Cypress product. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product
to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any
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