STLQ020 Datasheet by STMicroelectronics

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DFN6-2x2 Flip-Chip4
S OT323-5L
Features
Operating input voltage range: 2 V to 5.5 V
Output current up to 200 mA
Ultra-low quiescent current:
300 nA typ. at no load
100 μA typ. at 200 mA load
Controlled Iq in dropout conditions
Very low-dropout voltage: 160 mV at 200 mA
Output voltage accuracy: 2% at room temperature, 3% in full temperature range
Output voltage versions: from 0.8 V to 4.5 V, with 50 mV step and adjustable
Logic-controlled electronic shutdown
Output discharge feature (optional)
Internal overcurrent and thermal protections
Temperature range: from -40 °C to +125 °C
Packages: DFN6-2x2, SOT323-5L, Flip-Chip4
Applications
• Smartphones/tablets
Image sensors
Wearable accessories
Healthcare devices
• Metering
Description
The STLQ020 is a 200 mA low-dropout voltage regulator, able to work with an input
voltage ranging from 2 V to 5.5 V.
The typical dropout voltage at maximum load is 160 mV.
The ultra-low quiescent current, which is just 0.3 μA at no load, extends battery-life of
applications requiring very long standby time.
Even though the device intrinsic consumption is ultra-low, STLQ020 is able to provide
fast transient response and good PSRR performance, thanks to its adaptive biasing
circuit.
Enable pin puts the STLQ020 in shutdown mode, reducing total current consumption
to 5 nA.
The STLQ020 is designed to keep the quiescent current under control and at a low
value also during dropout operation, helping to extend even more the operating time
of battery- powered devices.
It also includes short-circuit constant-current limiting and thermal protection.
Several small package options are available.
Maturity status link
STLQ020
200 mA ultra-low quiescent current LDO
STLQ020
Datasheet
DS12072 - Rev 3 - June 2019
For further information contact your local STMicroelectronics sales office.
www.st.com
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1Block diagram
Figure 1. Block diagram (fixed version)
Figure 2. Block diagram (adjustable version)
VIN
GND
VOUT
OPAMP
Bias
generator
Bandgap
reference
EN
Thermal
protection
Enable
*
ADJ
Note: (*) output discharge function is optional.
STLQ020
Block diagram
DS12072 - Rev 3 page 2/31
VouT NC/ADJ E El SOT323-5L (top vlew) Vow NC/ADJ GND DFN6-2X2 {marking View) I‘x /‘\ IAZI (BZI \_/ \_,z I.\ l-\ 1A1) (B11 .\_z \ / Flip-Chip 4 {marking View) AMezooazm 712mm
2Pin configuration
Figure 3. Pin configuration
Table 1. Pin description
Symbol SOT323-5L DFN6-2x2 Flip-Chip4 Description
VIN 1 6 A1 LDO supply voltage
VOUT 5 1 A2 LDO output voltage
GND 2 3 B2 Ground
EN 3 4 B1
Enable input: set VEN = high to turn on the device;
VEN = low to turn off the device. Not internally
pulled-up, don’t leave floating.
NC/ADJ 4 2 -
Adjustable pin (only on ADJ version). Connect to
external resistor divider. Not connected on the
fixed version
NC - 5 - Not internally connected: it can be connected to
GND
Exposed
pad - Exposed pad - Must be connected to GND
STLQ020
Pin configuration
DS12072 - Rev 3 page 3/31
orr lpF ON lpF “F“; 2 VOUT
3Typical application diagram
Figure 4. Typical application diagram (fixed version)
VIN
GND
VI
EN
CIn
VO
VOUT
COut
STLQ020
OFF
ON
1µF 1µF
AMG270320170900MT
Figure 5. Typical application diagram (adjustable version)
Adjus table ve rsion
VIN
GND
VI
EN
CIn
VO
VOUT
COut
STLQ020
OFF
ON
1µF 1µF
R1
R2
ADJ
AMG270320170901MT
Note: R1 and R2 are calculated according to the following formula: R1 = R2 x (VOUT / VADJ - 1).
STLQ020
Typical application diagram
DS12072 - Rev 3 page 4/31
4Maximum ratings
Table 2. Absolute maximum ratings
Symbol Parameter Value Unit
VIN Input supply voltage -0.3 to 7 V
VOUT Output voltage -0.3 to VIN + 0.3 V
VADJ Adjustable pin voltage -0.3 to 2 V
IOUT Output current Internally limited A
EN Enable pin voltage -0.3 to VIN + 0.3 V
PDPower dissipation Internally limited W
ESD
Charged device model ±500
V
Human body model ±2000
TJ-OP Operating junction temperature -40 to 125 °C
TJ-MAX Maximum junction temperature 150 °C
TSTG Storage temperature -55 to 150 °C
Table 3. Thermal data
Symbol Parameter DFN6-2x2 Flip-Chip4 SOT323-5L Unit
Rthjc Thermal resistance, junction-to-case 15 130 °C/W
Rthja Thermal resistance, junction-to-ambient 65 180 250 °C/W
STLQ020
Maximum ratings
DS12072 - Rev 3 page 5/31
5Electrical characteristics
TJ = 25 °C, VIN = VOUT + 0.5 V or 2 V, whichever is greater; VEN = VIN; CIN = 1 μF; COUT = 1 μF; IOUT = 1 mA.
Table 4. Electrical characteristics (fixed version)
Symbol Parameter Test conditions Min. Typ. Max. Unit
VIN Operating input voltage range 2 5.5 V
VOUT Output voltage accuracy
TJ = 25 °C -2 2
%
-40 °C < TJ < 125 °C -3 3
∆VOUT%/
VIN
Static line regulation
VOUT + 0.5 V < VIN < 5.5 V (1) 0.005
%/V
-40 °C < TJ < 125 °C 0.05
∆VOUT%/
IOUT
Static load regulation
1 mA < IOUT < 0.2 A; TJ = 25 °C 0.0015
%/mA
-40 °C < TJ < 125 °C 0.005
VDROP Dropout voltage(2)
VOUT = 2.5 V; IOUT = 0.2 A 160 mV
VOUT = 2.5 V; IOUT = 20 mA 15 mV
eN Output noise voltage f = 10 Hz to 100 kHz 135 µVRMS/
VOUT
SVR Supply voltage rejection
VOUT = 2.5 V; VRIPPLE = 0.2 Vpp
52
dB
IOUT = 10 mA; f = 100 Hz
VOUT = 2.5 V; VRIPPLE = 0.2 Vpp
35
IOUT = 10 mA ; f = 1 kHz
VOUT = 2.5 V; VRIPPLE = 0.2 Vpp
45
IOUT = 10 mA; f = 10 kHz
Iq
Quiescent current
IOUT = 0 A 300
nA
IOUT = 0 A; -40 °C < TJ < 125 °C 1000
IOUT = 0.2 A 100
µA
IOUT = 0.2 A; -40 °C < TJ < 125 °C 150
Shutdown current VEN = 0 V, VIN = VOUT + 0.5 V (3) 0.005 0.05 µA
ISC Short-circuit current VOUT = 0 V 380 mA
RLOW (4) Output discharge resistance VEN = 0 V 100 Ω
VEN
Enable input logic low -40 °C < TJ < 125 °C 0.4
V
Enable input logic high 1.2
IEN Enable pin input current VEN = VIN; 1.25 < VIN < 6.0 V 1 nA
TSHDN
Thermal shutdown(5) IOUT > 1 mA 160
°C
Hysteresis 20
1. VIN = VOUT + 0.5 V or 2 V, whichever is greater.
2. Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value.
3. VIN = VOUT + 0.5 V or 2 V, whichever is greater.
4. On specific version only.
5. The thermal protection is not active when the load current is lower than 1 mA.
STLQ020
Electrical characteristics
DS12072 - Rev 3 page 6/31
TJ = 25 °C, VIN = 2 V, VEN = VIN; CIN = 1 μF; COUT = 1 μF; IOUT = 1 mA.
Table 5. Electrical characteristics (adjustable version)
Symbol Parameter Test conditions Min. Typ. Max. Unit
VIN Operating input voltage range 2 5.5 V
VADJ Reference voltage accuracy
TJ = 25 °C 0.784 0.8 0.816 V
-40 °C < TJ < 125 °C -3 3 %
IADJ Adjustable pin current 1 nA
∆VADJ%/∆VIN Static line regulation
2 V< VIN < 5.5 V 0.005
%/V
-40 °C < TJ < 125 °C 0.05
∆VADJ%/∆IOUT Static load regulation
1 mA < IOUT < 0.2 A; TJ = 25 °C 0.0015
%/mA
-40 °C < TJ < 125 °C 0.005
VDROP Dropout voltage(1)
VOUT = 2.0 V; IOUT = 0.2 A 200 mV
VOUT = 2.0 V; IOUT = 20 mA 20 mV
eN Output noise voltage f = 10 Hz to 100 kHz 135 µVRMS/
VOUT
SVR Supply voltage rejection
VOUT = 2.5 V; VRIPPLE = 0.2 Vpp
IOUT = 10 mA; f = 100 Hz 60
dB
VOUT = 2.5 V; VRIPPLE = 0.2 Vpp
IOUT = 10 mA ; f = 1 kHz 40
VOUT = 2.5 V; VRIPPLE = 0.2 Vpp
IOUT = 10 mA; f = 10 kHz 60
Iq
Quiescent current
IOUT = 0 A 300
nA
IOUT = 0 A; -40 °C < TJ < 125 °C 1000
IOUT = 0.2 A 80
µA
IOUT = 0.2 A; -40 °C < TJ < 125
°C 150
Shutdown current VEN = 0 V, VIN = 2 V 0.005 0.05 µA
ISC Short-circuit current VOUT = 0 V 380 mA
RLOW (2) Output discharge resistance VEN = 0 V 100 Ω
VEN
Enable input logic low -40 °C < TJ < 125 °C 0.4
V
Enable input logic high 1.2
IEN Enable pin input current VEN = VIN; 1.25 < VIN < 5.5 V 1 nA
TSHDN
Thermal shutdown(3) IOUT > 1 mA 160
°C
Hysteresis 20
1. Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value.
2. The thermal protection is not active when the load current is lower than 1 mA.
3. On specific version only.
STLQ020
Electrical characteristics
DS12072 - Rev 3 page 7/31
6Typical characteristics
The following plots are referred to the typical application circuit and, unless otherwise noted, at TA = 25 °C.
Figure 6. Output voltage vs. temperature
0.780
0.785
0.790
0.795
0.800
0.805
0.810
0.815
0.820
-60 -40 -20 0 20 40 60 80 100 120 140
VOUT [V]
Temperature [ºC]
VIN = 2 V, VOUT = VADJ, IOUT = 1 mA
Figure 7. Output voltage vs. temperature
VIN = 2 V, VOUT = VADJ, IOUT = 200 mA
0.780
0.785
0.790
0.795
0.800
0.805
0.810
0.815
0.820
-60 -40 -20 0 20 40 60 80 100 120 140
VOUT [V]
Temperature [ºC]
Figure 8. Output voltage vs. temperature
VIN = 2.3 V, VOUT = 1.8 V, IOUT = 1 mA
1.750
1.760
1.770
1.780
1.790
1.800
1.810
1.820
1.830
1.840
1.850
-60 -40 -20 0 20 40 60 80 100 120 140
VOUT [V]
Temperature [ºC]
Figure 9. Output voltage vs. temperature
VIN = 2.3 V, VOUT = 1.8 V, IOUT = 200 mA
1.750
1.760
1.770
1.780
1.790
1.800
1.810
1.820
1.830
1.840
1.850
-60 -40 -20 0 20 40 60 80 100 120 140
VOUT [V]
Temperature [ºC]
STLQ020
Typical characteristics
DS12072 - Rev 3 page 8/31
Figure 10. Line regulation vs. temperature
-0.050
-0.040
-0.030
-0.020
-0.010
0.000
0.010
0.020
0.030
0.040
0.050
-60 -40 -20 0 20 40 60 80 100 120 140
Line regulation [%/V]
Temperature [ºC]
VIN = 2.3 V to 5.5 V, VOUT = V
ADJ, IOUT = 1 mA
Figure 11. Load regulation vs. temperature
-0.005
-0.004
-0.003
-0.002
-0.001
0.000
0.001
0.002
0.003
0.004
0.005
-60 -40 -20 0 20 40 60 80 100 120 140
Line regulation [%/mA]
Temperature [ºC]
VIN = 2.3 V , VOUT = 1.8 V, IOUT = 1 mA to 200 mA
Figure 12. Short-circuit current vs. temp.
0
100
200
300
400
500
600
700
-60 -40 -20 0 20 40 60 80 100 120 140
ISHORT [mA]
Temperature [ºC]
VIN = 2 V, VOUT = GND
Figure 13. Quiescent current vs. temperature
0
100
200
300
400
500
600
700
800
900
1000
-60 -40 -20 0 20 40 60 80 100 120 140
Iq[nA]
Temperature [ºC]
VIN = 2 V, V
OUT = V
ADJ , IOUT = 0 mA
Figure 14. Quiescent current vs. temperature
0
20
40
60
80
100
120
140
160
-60 -40 -20 0 20 40 60 80 100 120 140
Iq[µA]
Temperature [ºC]
VIN = 2 V, V
OUT = V
ADJ, IOUT = 200 mA
Figure 15. Shutdown current vs. temperature
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0.16
0.18
0.2
-60 -40 -20 0 20 40 60 80 100 120 140
Iq-Off [µA]
Temperature [ºC]
VIN = 5.5 V, EN = GND
STLQ020
Typical characteristics
DS12072 - Rev 3 page 9/31
Figure 16. Quiescent current vs. load current
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
0 20 40 60 80 100 120 140 160 180 200
Iq [µA]
IOUT [mA]
VIN = 2 V, VOUT = V
ADJ, IOUT = 0 to 200 mA
Figure 17. Quiescent current vs. load current
(magnification)
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
11.0
0.000001 0.00001 0.0001 0.001 0.01 0.1 1
Iq [µA]
IOUT [mA]
VIN = 2 V, VOUT = VADJ, IOUT = 0 to 1 mA
Figure 18. Quiescent current vs. input voltage
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0 1 2 3 4 5 6
Iq [µA]
Input Voltage [V]
VIN = 0 to 5.5 V, VOUT = 2.5 V, IOUT = 0 mA
Figure 19. Output voltage vs. input voltage
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0 1 2 3 4 5 6
V
IN [V]
VIN = 0 to 5.5 V, V
OUT = 2.5 V, IOUT = 0 mA
VOUT (V)
Figure 20. Enable pin current vs. temperature
0
10
20
30
40
50
60
70
80
90
100
-60 -40 -20 0 20 40 60 80 100 120 140
IEN [nA]
Temperature [ºC]
VIN = 2 V
Figure 21. Dropout voltage vs. temperature
0
10
20
30
40
50
-60 -40 -20 0 20 40 60 80 100 120 140
VDROP [mV]
Temperature [ºC]
VOUT = 2 V, IOUT = 20 mA
STLQ020
Typical characteristics
DS12072 - Rev 3 page 10/31
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Figure 22. Dropout voltage vs. temperature
0
100
200
300
400
500
-60 -40 -20 0 20 40 60 80 100 120 140
VDROP [mV]
Temperature [ºC]
VOUT = 2 V, IOUT = 200 mA
Figure 23. Enable threshold vs. temperature
400
500
600
700
800
900
1000
1100
1200
-60 -40 -20 0 20 40 60 80 100 120 140
VEN [mV]
Temperature [ºC]
VEN-ON
VEN-OFF
Figure 24. PSRR vs. frequency
0
10
20
30
40
50
60
70
80
90
100
10 100 1000 10000 100000
PSRR [dB]
f [Hz]
Vout=0.8V
Vout=1.8V
I = 10 mA
OUT
Figure 25. Line transient (trise = 5 µs)
Figure 26. Line transient (trise = 1 µs) Figure 27. Line transient
STLQ020
Typical characteristics
DS12072 - Rev 3 page 11/31
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Figure 28. Load transient Figure 29. Load transient (trise = 5 µs)
Figure 30. Load transient (VOUT = 1.8 V) Figure 31. Load transient (VOUT = VADJ)
Figure 32. Startup transient Figure 33. Startup transient (trise = 10 µs)
STLQ020
Typical characteristics
DS12072 - Rev 3 page 12/31
7Application information
7.1 External capacitors
The STLQ020 voltage regulator requires external low ESR capacitors to assure the control loop stability. These
capacitors must be selected to meet the requirements of minimum capacitance and equivalent series resistance
defined in the following chapters. Input and output capacitors should be located as close as possible to the
relevant pins.
Input capacitor
An input capacitor, with a minimum value of 1 μF, must be located as close as possible to the input pin of the
device and returned to a clean analog ground. A good quality, low-ESR ceramic capacitor is suggested. It helps to
ensure stability of the control loop, reduces the effects of inductive sources and improves ripple rejection.
Capacitance higher than 1 µF can be chosen in case of fast load transients in application.
Output capacitor
STLQ020 requires a low-ESR capacitor connected on its output, to keep the control loop stable and reduce the
risk of ringing and oscillations. The control loop is designed to be stable with any good quality ceramic capacitor
(such as X5R/X7R types) with a minimum value of 1 µF and equivalent series resistance in the [3 – 500 mΩ]
range. It is important to highlight that the output capacitor must maintain its capacitance and ESR in the stable
region over the full operating temperature, load and input voltage ranges, to assure stability. Therefore,
capacitance and ESR variations must be taken into account in the design phase to ensure the device works in the
expected stability region. There is no maximum limit to the output capacitance, provided that the above conditions
are respected.
7.2 Output voltage adjustment (adjustable version)
In the adjustable version, available on the DFN6-2x2 and SOT323-5L packages, the output voltage can be
adjusted to any voltage, starting from 0.8 V (VADJ) up to the input voltage minus the voltage drop (VDROP) across
the internal power pass element, by connecting a resistor divider between the ADJ pin and the output, allowing
the remote voltage sensing.
The resistor divider should be selected using the following equation:
Equation 1
VOUT = VADJ (1 + R1 / R2)
with VADJ = 0.8 V (typ.) and VOUT < VIN-VDROP(MAX)
For best accuracy and stability the resistor divider should be designed in order to allow that a current of at least
500 nA flows across it. The current flowing into the ADJ pin is typically less than 1 nA, therefore causing negligible
change in final the output voltage.
7.3 Enable pin operation
This is a logic control pin, CMOS level-compatible, which can be used to turn On/Off the regulator.It is active high,
so when it is pulled down, the device enters the shutdown mode, drastically reducing the current consumption, to
less just few nA.
Since it is not internally pulled-up, when the enable feature is not used, this pin must not be left floating. It can be
tied to VIN to keep the regulator output in ON state all the time.
To assure reliable operation, the signal source used to drive the EN pin, must be able to swing above and below
the specified thresholds listed in the electrical characteristics table (VEN).
7.4 Power dissipation
A proper PCB design is recommended, to ensure that the device internal junction temperature is kept below
125°C, in all the operating condition.
Depending on the package option, the thermal energy generated by the device flows from the die surface to the
PCB copper area through the package leads, solder bumps and/or exposed pad.
STLQ020
Application information
DS12072 - Rev 3 page 13/31
The PCB copper area acts as a heat sink. The footprint copper pads should be as wider as possible to spread
and dissipate the heat to the surrounding environment. Thermal vias to the inner or backside copper layers
improve the overall thermal performance of the device.
The power dissipation of the LDO depends on the input voltage, output voltage and output current, and is given
by:
Equation 2
PD = (VIN -VOUT) IOUT
The junction temperature of the device is:
Equation 3
TJ_MAX = TA + RthJA x PD
where: TJ_MAX is the maximum junction of the die, 125 °C; TA is the ambient temperature; RthJA is the thermal
resistance junction-to-ambient.
With the above equation it is possible to calculate the maximum allowable power dissipation, therefore the
maximum load current for a certain voltage drop. Appropriate de-rating of the operating condition can be applied
accordingly.
7.5 Protection features
Current limit
The STLQ020 embeds a constant-current limit circuit, which acts in case of overload or short-circuit on the output,
clamping the load current to a safe value (typ. 380 mA).
Normal operation is restored if the overload disappears, but prolonged operation in current limit may lead to high
power dissipation inside the LDO and subsequently to thermal shutdown.
Thermal protection
An internal thermal feedback loop disables the output voltage if the die temperature reaches approximately
160 °C. This feature protects the device from excessive temperature that could lead to permanent damage to the
LDO.
Once the thermal protection is triggered and the device is shut down, normal operation is automatically recovered
if the die temperature falls below 140 °C (thermal protection hysteresis of 20 °C typically)
Important note: to keep the device power consumption below 500 nA in low load/no load condition, the internal
thermal protection is kept disabled for load current below 1 mA.
Current and thermal limit protections are designed to protect the LDO from excessive power dissipation and not
intended to replace a proper thermal and electrical design of the application.
Continuous operation above the maximum ratings may lead to permanent damage to the device.
STLQ020
Protection features
DS12072 - Rev 3 page 14/31
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8Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
8.1 SOT323-5L package information
Figure 34. SOT323-5L package outline
7091413_G
STLQ020
Package information
DS12072 - Rev 3 page 15/31
0.80 1.25
Table 6. SOT323-5L package mechanical data
Dim.
mm
Min. Typ. Max.
A 0.80 1.10
A1 0 0.10
A2 0.80 0.90 1
b 0.15 0.30
c 0.10 0.22
D 1.80 2 2.20
E 1.80 2.10 2.40
E1 1.15 1.25 1.35
e 0.65
e1 1.30
L 0.26 0.36 0.46
< 0°
Figure 35. SOT323-5L recommended footprint
STLQ020
SOT323-5L package information
DS12072 - Rev 3 page 16/31
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8.1.1 SOT323-5L tape and reel information
Figure 36. SOT323-5L tape outline
STLQ020
SOT323-5L package information
DS12072 - Rev 3 page 17/31
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Figure 37. SOT323-5L reel outline
STLQ020
SOT323-5L package information
DS12072 - Rev 3 page 18/31
750mm
8.2 Flip-Chip4 package information
Figure 38. Flip-Chip4 package outline
Table 7. Flip-Chip4 mechanical data
Dim.
mm
Min. Typ. Max.
A 0.51 0.56 0.61
A1 0.17 0.20 0.23
A2 0.34 0.36 0.38
b 0.23 0.26 0.29
D 0.743 0.773 0.803
D1 0.40
E 0.743 0.773 0.803
E1 0.40
SD 0.20
SE 0.20
f 0.187
ccc 0.075
STLQ020
Flip-Chip4 package information
DS12072 - Rev 3 page 19/31
M 0,8 2R5 1 L% _L_/A Grld locanent urea
Figure 39. Flip-Chip4 recommended footprint
STLQ020
Flip-Chip4 package information
DS12072 - Rev 3 page 20/31
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8.2.1 Flip-Chip4 reel information
Figure 40. Flip-Chip4 reel outline
STLQ020
Flip-Chip4 package information
DS12072 - Rev 3 page 21/31
4.00 10.10 4» 2.00 10.05 1.50 ‘O.1O 4.00 10.10 4» ¢ r 1.75 10.10 3.50 10.05 41 ¢ 0.20 10.05 .20 10.02 7 1‘1 .fi 3. MAX 0.50 20.03 jifi MAX 0.85 10.03
Figure 41. Flip-Chip4 tape outline
STLQ020
Flip-Chip4 package information
DS12072 - Rev 3 page 22/31
m1» . o m® c AM ddd® : k’fl H L_ m n F sumfi | rm: El -
8.3 DFN6 2x2 package information
Figure 42. DFN6 2x2 package outline
Bottom view
Side view
Top view
DM00205706
STLQ020
DFN6 2x2 package information
DS12072 - Rev 3 page 23/31
Table 8. DFN6 2x2 package mechanical data
Dim.
mm
Min. Typ. Max.
A 0.75 0.85 0.95
A1 0.00 0.02 0.05
A3 0.10 0.20 0.30
b 0.18 0.23 0.28
D 1.90 2.00 2.10
D2 1.33 1.43 1.53
E2 0.68 0.78 0.88
e 0.50
E 1.90 2.00 2.10
L 0.25 0.35 0.45
N 6
Figure 43. DFN6 2x2 recommended footprint
STLQ020
DFN6 2x2 package information
DS12072 - Rev 3 page 24/31
8:5 mwsemEc mmazz mmEmzji z, mzomfign j< md‘="" +="" oo.m="">> an as 6 6E .25 9o fiow + ooé ,n. 49.8 3 252:3 s 22 ‘ w . Exam .0 2 is 22 £53; ro + own i ,o~.o«y row + on: ox .333. 9 ko 3:333 3556 2: fiO‘ + mN.N om auxuan .c 2 uhzuu 2 fio‘ + mNN 04 :2 383» .9 2. i: so: 853»: e 7) 2 E ex A! > ‘ ‘ m. \M ‘9 M W 2:29.“ ( r r.“ W W E 335 ‘ , , L a A‘ > [a 33% 3033 k 5.33 S Smo.o«o.~ «m
8.3.1 DFN6 2x2 tape information
Figure 44. DFN6 2x2 tape outline
STLQ020
DFN6 2x2 package information
DS12072 - Rev 3 page 25/31
9Ordering information
Table 9. Order codes
Order code Package Output voltage Marking Packing
STLQ020C18R SOT323-5L 1.8 V QLJ Tape and reel
STLQ020C22R SOT323-5L 2.2 V QLS Tape and reel
STLQ020C28R SOT323-5L 2.8 V QM3 Tape and reel
STLQ020C33R SOT323-5L 3.3 V QMB Tape and reel
STLQ020J18R Flip-Chip 4 1.8 V LJ Tape and reel
STLQ020J25R Flip-Chip 4 2.5 V LX Tape and reel
STLQ020J30R Flip-Chip 4 3.0 V M7 Tape and reel
STLQ020J33R Flip-Chip 4 3.3 V MB Tape and reel
STLQ020PU19R DFN6-2x2 1.9 V QLL Tape and reel
STLQ020PU28R DFN6-2x2 2.8 V QM3 Tape and reel
STLQ020PUR DFN6-2x2 ADJ QAD Tape and reel
Figure 45. Marking composition (flip-chip)
xy
A1
STLQ020
Ordering information
DS12072 - Rev 3 page 26/31
Revision history
Table 10. Document revision history
Date Revision Changes
27-Mar-2017 1 Initial release.
05-Dec-2017 2 Added: Section 6 Typical characteristics and Section 7 Application information.
07-Jun-2019 3
Added: order codes Table 9. Order codes and reel information Section
8.1.1 SOT323-5L tape and reel information, Section 8.2.1 Flip-Chip4 reel
information and Section 8.3.1 DFN6 2x2 tape information.
STLQ020
DS12072 - Rev 3 page 27/31
Contents
1Block diagrams....................................................................2
2Pin configuration ..................................................................3
3Typical application.................................................................4
4Maximum ratings ..................................................................5
5Electrical characteristics...........................................................6
6Typical characteristics .............................................................8
7Application information...........................................................13
7.1 External capacitors ............................................................13
7.2 Output voltage adjustment (adjustable version) ....................................13
7.3 Enable pin operation...........................................................13
7.4 Power dissipation .............................................................13
7.5 Protection features ............................................................14
8Package information..............................................................15
8.1 SOT323-5L package information ................................................15
8.1.1 SOT323-5L tape and reel information ........................................16
8.2 Flip-Chip4 package information..................................................18
8.2.1 Flip-Chip4 reel information ................................................20
8.3 DFN6 2x2 package information ..................................................22
8.3.1 DFN6 2x2 reel information ................................................24
9Ordering information .............................................................26
Revision history .......................................................................27
Contents ..............................................................................28
List of tables ..........................................................................29
List of figures..........................................................................30
STLQ020
Contents
DS12072 - Rev 3 page 28/31
List of tables
Table 1. Pin description......................................................................3
Table 2. Absolute maximum ratings .............................................................5
Table 3. Thermal data.......................................................................5
Table 4. Electrical characteristics (fixed version).....................................................6
Table 5. Electrical characteristics (adjustable version).................................................7
Table 6. SOT323-5L package mechanical data .................................................... 16
Table 7. Flip-Chip4 mechanical data ............................................................ 19
Table 8. DFN6 2x2 package mechanical data ..................................................... 24
Table 9. Order codes ...................................................................... 26
Table 10. Document revision history ............................................................. 27
STLQ020
List of tables
DS12072 - Rev 3 page 29/31
List of figures
Figure 1. Block diagram (fixed version) ..........................................................2
Figure 2. Block diagram (adjustable version) ......................................................2
Figure 3. Pin configuration ...................................................................3
Figure 4. Typical application diagram (fixed version) .................................................4
Figure 5. Typical application diagram (adjustable version) .............................................4
Figure 6. Output voltage vs. temperature .........................................................8
Figure 7. Output voltage vs. temperature .........................................................8
Figure 8. Output voltage vs. temperature .........................................................8
Figure 9. Output voltage vs. temperature .........................................................8
Figure 10. Line regulation vs. temperature.........................................................9
Figure 11. Load regulation vs. temperature ........................................................9
Figure 12. Short-circuit current vs. temp. ..........................................................9
Figure 13. Quiescent current vs. temperature.......................................................9
Figure 14. Quiescent current vs. temperature.......................................................9
Figure 15. Shutdown current vs. temperature.......................................................9
Figure 16. Quiescent current vs. load current...................................................... 10
Figure 17. Quiescent current vs. load current (magnification) ........................................... 10
Figure 18. Quiescent current vs. input voltage ..................................................... 10
Figure 19. Output voltage vs. input voltage ....................................................... 10
Figure 20. Enable pin current vs. temperature ..................................................... 10
Figure 21. Dropout voltage vs. temperature ....................................................... 10
Figure 22. Dropout voltage vs. temperature ....................................................... 11
Figure 23. Enable threshold vs. temperature ...................................................... 11
Figure 24. PSRR vs. frequency ............................................................... 11
Figure 25. Line transient (trise = 5 µs) ........................................................... 11
Figure 26. Line transient (trise = 1 µs) ........................................................... 11
Figure 27. Line transient .................................................................... 11
Figure 28. Load transient ................................................................... 12
Figure 29. Load transient (trise = 5 µs)........................................................... 12
Figure 30. Load transient (VOUT = 1.8 V)......................................................... 12
Figure 31. Load transient (VOUT = VADJ)......................................................... 12
Figure 32. Startup transient .................................................................. 12
Figure 33. Startup transient (trise = 10 µs) ........................................................ 12
Figure 34. SOT323-5L package outline .......................................................... 15
Figure 35. SOT323-5L recommended footprint..................................................... 16
Figure 36. SOT323-5L tape outline............................................................. 17
Figure 37. SOT323-5L reel outline ............................................................. 18
Figure 38. Flip-Chip4 package outline ........................................................... 19
Figure 39. Flip-Chip4 recommended footprint ..................................................... 20
Figure 40. Flip-Chip4 reel outline .............................................................. 21
Figure 41. Flip-Chip4 tape outline.............................................................. 22
Figure 42. DFN6 2x2 package outline ........................................................... 23
Figure 43. DFN6 2x2 recommended footprint...................................................... 24
Figure 44. DFN6 2x2 tape outline .............................................................. 25
Figure 45. Marking composition (flip-chip) ........................................................ 26
STLQ020
List of figures
DS12072 - Rev 3 page 30/31
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STLQ020
DS12072 - Rev 3 page 31/31

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