74HC(T)193-Q100 Datasheet by Nexperia USA Inc.

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1. General description
The 74HC193-Q100; 74HCT193-Q100 is a 4-bit synchronous binary up/down counter.
Separate up/down clocks, CPU and CPD respectively, simplify operation. The outputs
change state synchronously with the LOW-to-HIGH transition of either clock input. If the
CPU clock is pulsed while CPD is held HIGH, the device counts up. If the CPD clock is
pulsed while CPU is held HIGH, the device counts down. Only one clock input can be held
HIGH at any time to guarantee predictable behavior. The device can be cleared at any
time by the asynchronous master reset input (MR). It may also be loaded in parallel by
activating the asynchronous parallel load input (PL). The terminal count up (TCU) and
terminal count down (TCD) outputs are normally HIGH. When the circuit has reached the
maximum count state of 15, the next HIGH-to-LOW transition of CPU causes TCU to go
LOW. TCU remains LOW until CPU goes HIGH again, duplicating the count up clock.
Likewise, the TCD output goes LOW when the circuit is in the zero state and the CPD
goes LOW. The terminal count outputs duplicate the clock waveforms and can be used as
the clock input signals to the next higher-order circuit in a multistage counter. Multistage
counters are not fully synchronous, since there is a slight delay time difference added for
each stage that is added. The counter may be preset by the asynchronous parallel load
capability of the circuit. Information on the parallel data inputs (D0 to D3), is loaded into
the counter. This information appears on the outputs (Q0 to Q3) regardless of the
conditions of the clock inputs when the parallel load (PL) input is LOW. A HIGH level on
the master reset (MR) input disables the parallel load gates. It overrides both clock inputs
and sets all outputs (Q0 to Q3) LOW. If one of the clock inputs is LOW during and after a
reset or load operation, the next LOW-to-HIGH transition of that clock is interpreted as a
legitimate signal and it is counted. Inputs include clamp diodes that enable the use of
current limiting resistors to interface inputs to voltages in excess of VCC.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Input levels:
For 74HC193-Q100: CMOS level
For 74HCT193-Q100: TTL level
Synchronous reversible 4-bit binary counting
Asynchronous parallel load
Asynchronous reset
Expandable without external logic
Complies with JEDEC standard no. 7A
74HC193-Q100; 74HCT193-Q100
Presettable synchronous 4-bit binary up/down counter
Rev. 1 — 12 July 2013 Product data sheet
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT139_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 1 — 12 July 2013 2 of 29
Nexperia 74HC193-Q100; 74HCT193-Q100
Presettable synchronous 4-bit binary up/down counter
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
3. Ordering information
4. Functional diagram
Table 1. Ordering information
Type number Package
Temperature
range Name Description Version
74HC193D-Q100 40 C to +125 C SO16 plastic small outline package; 16 leads;
body width 3.9 mm SOT109-1
74HC193DB-Q100 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm SOT338-1
74HC193PW-Q100 40 C to +125 C TSSOP16 plastic thin shrink small outline package;
16 leads; body width 4.4 mm SOT403-1
74HCT193D-Q100 40 C to +125 C SO16 plastic small outline package; 16 leads;
body width 3.9 mm SOT109-1
74HCT193DB-Q100 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm SOT338-1
74HCT193PW-Q100 40 C to +125 C TSSOP16 plastic thin shrink small outline package;
16 leads; body width 4.4 mm SOT403-1
Fig 1. Functional diagram Fig 2. Logic symbol
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FLIP-FLOPS
COUNTER
PL
11 CPU
5TCD 13
TCU 12
Q0
3267
151109
Q1 Q2 Q3
D0 D1 D2 D3
CPD
4
MR
14
001aag409
MR Q0 Q1 Q2 Q3
PL D0 D1 D2 D3
143267
11151109
4CPD TCD
TCU5
13
12CPU
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT139_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 1 — 12 July 2013 3 of 29
Nexperia 74HC193-Q100; 74HCT193-Q100
Presettable synchronous 4-bit binary up/down counter
Fig 3. IEC logic symbol
3D
CTR4
2CT = 0
1CT = 15
001aag410
10
3
6
15
12
97
13
12
G2
4G1
5
11 C3
2+
14 R
1
© Nexperia B.V. 2017. All rights reserved
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74HC_HCT139_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 1 — 12 July 2013 4 of 29
Nexperia 74HC193-Q100; 74HCT193-Q100
Presettable synchronous 4-bit binary up/down counter
Fig 4. Logic diagram
001aag412
D0 D1 D2 D3
Q0 Q1 Q2 Q3
TCD
PL
CPU
CPD
MR
SD
FF1
RD Q
Q
T
SD
FF2
RD Q
Q
T
SD
FF3
RD Q
Q
T
SD
FF4
RD Q
Q
T
TCU
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT139_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 1 — 12 July 2013 5 of 29
Nexperia 74HC193-Q100; 74HCT193-Q100
Presettable synchronous 4-bit binary up/down counter
5. Pinning information
5.1 Pinning
5.2 Pin description
[1] LOW-to-HIGH, edge triggered.
Fig 5. Pin configuration SO16 Fig 6. Pin configuration TSSOP16 and SSOP16
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Table 2. Pin description
Symbol Pin Description
D0 15 data input 0
D1 1 data input 1
D2 10 data input 2
D3 9 data input 3
Q0 3 flip-flop output 0
Q1 2 flip-flop output 1
Q2 6 flip-flop output 2
Q3 7 flip-flop output 3
CPD 4 count down clock input[1]
CPU 5 count up clock input[1]
GND 8 ground (0 V)
PL 11 asynchronous parallel load input (active LOW)
TCU 12 terminal count up (carry) output (active LOW)
TCD 13 terminal count down (borrow) output (active LOW)
MR 14 asynchronous master reset input (active HIGH)
VCC 16 supply voltage
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT139_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 1 — 12 July 2013 6 of 29
Nexperia 74HC193-Q100; 74HCT193-Q100
Presettable synchronous 4-bit binary up/down counter
6. Functional description
[1] H = HIGH voltage level
L = LOW voltage level
X = don’t care
= LOW-to-HIGH clock transition.
[2] TCU = CPU at terminal count up (HHHH)
[3] TCD = CPD at terminal count down (LLLL).
Table 3. Function table[1]
Operating mode Inputs Outputs
MR PL CPU CPD D0 D1 D2 D3 Q0 Q1 Q2 Q3 TCU TCD
Reset (clear) HXXLXXXXLLLLHL
HXXHXXXXLLLLHH
Parallel load LLXLLLLLLLLLHL
LLXHLLLLLLLLHH
LLLXHHHHHHHHL H
L L HXHHHHHHHHHH
Count up L H H X X X X count up H[2] H
Count down L H H X X X X count down H H[3]
© Nexperia B.V. 2017. All rights reserved
74HC_HCT139_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 1 — 12 July 2013 7 of 29
Nexperia 74HC193-Q100; 74HCT193-Q100
Presettable synchronous 4-bit binary up/down counter
(1) Clear overrides load, data and count inputs.
(2) When counting up, the count down clock input (CPD) must be HIGH, when counting down the count up clock input
(CPU) must be HIGH.
Sequence
Clear (reset outputs to zero);
load (preset) to binary thirteen;
count up to fourteen, fifteen, terminal count up, zero, one and two;
count down to one, zero, terminal count down, fifteen, fourteen and thirteen.
Fig 7. Typical clear, load and count sequence
001aag411
COUNT UP COUNT DOWN
013
CLEAR PRESET
1 0 15 14 1314 15 0 1 2
MR(1)
PL
D0
D1
D2
D3
CPU(2)
CPD(2)
Q0
Q1
Q2
Q3
TCU
TCD
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT139_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 1 — 12 July 2013 8 of 29
Nexperia 74HC193-Q100; 74HCT193-Q100
Presettable synchronous 4-bit binary up/down counter
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO16 packages: above 70 C the value of Ptot derates linearly at 8 mW/K.
For SSOP16 and TSSOP16 packages: above 60 C the value of Ptot derates linearly at 5.5 mW/K.
8. Recommended operating conditions
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7.0 V
IIK input clamping current VI < 0.5 V or VI>V
CC + 0.5 V [1] -20 mA
IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V [1] -20 mA
IOoutput current VO= 0.5 V to VCC + 0.5 V - 25 mA
ICC supply current - 50 mA
IGND ground current - 50 mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation [2] -500mW
Table 5. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
74HC193-Q100
VCC supply voltage 2.0 5.0 6.0 V
VIinput voltage 0- V
CC V
VOoutput voltage 0 - VCC V
Tamb ambient temperature 40 +25 +125 C
t/V input transition rise and
fall rate VCC = 2.0 V - - 625 ns/V
VCC = 4.5 V - 1.67 139 ns/V
VCC = 6.0 V --83ns/V
74HCT193-Q100
VCC supply voltage 4.5 5.0 5.5 V
VIinput voltage 0- V
CC V
VOoutput voltage 0 - VCC V
Tamb ambient temperature 40 +25 +125 C
t/V input transition rise and
fall rate VCC = 4.5 V - 1.67 139 ns/V
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT139_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 1 — 12 July 2013 9 of 29
Nexperia 74HC193-Q100; 74HCT193-Q100
Presettable synchronous 4-bit binary up/down counter
9. Static characteristics
Table 6. Static characteristics type 74HC193-Q100
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
Tamb = 25 C
VIH HIGH-level input voltage VCC = 2.0 V 1.5 1.2 - V
VCC = 4.5 V 3.15 2.4 - V
VCC = 6.0 V 4.2 3.2 - V
VIL LOW-level input voltage VCC = 2.0 V - 0.8 0.5 V
VCC = 4.5 V - 2.1 1.35 V
VCC = 6.0 V - 2.8 1.8 V
VOH HIGH-level output voltage VI = VIH or VIL ---
IO=20 A; VCC = 2.0 V 1.9 2.0 - V
IO=20 A; VCC = 4.5 V 4.4 4.5 - V
IO=20 A; VCC = 6.0 V 5.9 6.0 - V
IO = 4.0 mA; VCC = 4.5 V 3.984.32- V
IO = 5.2 mA; VCC = 6.0 V 5.485.81- V
VOL LOW-level output voltage VI = VIH or VIL
IO=20A; VCC = 2.0 V - 0 0.1 V
IO=20A; VCC = 4.5 V - 0 0.1 V
IO=20A; VCC = 6.0 V - 0 0.1 V
IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 V
IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 V
IIinput leakage current VI=V
CC or GND; VCC =6.0V - - 0.1 A
ICC supply current VI = VCC or GND; IO = 0 A;
VCC =6.0V --8.0A
Ciinput capacitance - 3.5 - pF
Tamb = 40 C to +85 C
VIH HIGH-level input voltage VCC = 2.0 V 1.5 - - V
VCC = 4.5 V 3.15 - - V
VCC = 6.0 V 4.2 - - V
VIL LOW-level input voltage VCC = 2.0 V - - 0.5 V
VCC = 4.5 V - - 1.35 V
VCC = 6.0 V - - 1.8 V
VOH HIGH-level output voltage VI = VIH or VIL
IO=20 A; VCC = 2.0 V 1.9 - - V
IO=20 A; VCC = 4.5 V 4.4 - - V
IO=20 A; VCC = 6.0 V 5.9 - - V
IO = 4.0 mA; VCC = 4.5 V 3.84 - - V
IO = 5.2 mA; VCC = 6.0 V 5.34 - - V
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT139_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 1 — 12 July 2013 10 of 29
Nexperia 74HC193-Q100; 74HCT193-Q100
Presettable synchronous 4-bit binary up/down counter
VOL LOW-level output voltage VI = VIH or VIL
IO=20A; VCC = 2.0 V - - 0.1 V
IO=20A; VCC = 4.5 V - - 0.1 V
IO=20A; VCC = 6.0 V - - 0.1 V
IO = 4.0 mA; VCC = 4.5 V - - 0.33 V
IO = 5.2 mA; VCC = 6.0 V - - 0.33 V
IIinput leakage current VI=V
CC or GND; VCC =6.0V - - 1.0 A
ICC supply current VI = VCC or GND; IO = 0 A;
VCC =6.0V --80A
Tamb = 40 C to +125 C
VIH HIGH-level input voltage VCC = 2.0 V 1.5 - - V
VCC = 4.5 V 3.15 - - V
VCC = 6.0 V 4.2 - - V
VIL LOW-level input voltage VCC = 2.0 V - - 0.5 V
VCC = 4.5 V - - 1.35 V
VCC = 6.0 V - - 1.8 V
VOH HIGH-level output voltage VI = VIH or VIL
IO=20 A; VCC = 2.0 V 1.9 - - V
IO=20 A; VCC = 4.5 V 4.4 - - V
IO=20 A; VCC = 6.0 V 5.9 - - V
IO = 4.0 mA; VCC = 4.5 V 3.7 - - V
IO = 5.2 mA; VCC = 6.0 V 5.2 - - V
VOL LOW-level output voltage VI = VIH or VIL
IO=20A; VCC = 2.0 V - - 0.1 V
IO=20A; VCC = 4.5 V - - 0.1 V
IO=20A; VCC = 6.0 V - - 0.1 V
IO = 4.0 mA; VCC = 4.5 V - - 0.4 V
IO = 5.2 mA; VCC = 6.0 V - - 0.4 V
IIinput leakage current VI=V
CC or GND; VCC =6.0V - - 1.0 A
ICC supply current VI=V
CC or GND; IO = 0 A;
VCC =6.0V - - 160 A
Table 6. Static characteristics type 74HC193-Q100 …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT139_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 1 — 12 July 2013 11 of 29
Nexperia 74HC193-Q100; 74HCT193-Q100
Presettable synchronous 4-bit binary up/down counter
Table 7. Static characteristics type 74HCT193-Q100
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
Tamb = 25 C
VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - V
VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 V
VOH HIGH-level output voltage VI=V
IH or VIL; VCC =4.5V
IO=20 A4.44.5-V
IO=4.0mA 3.984.32- V
VOL LOW-level output voltage VI=V
IH or VIL; VCC =4.5V
IO=20A-00.1V
IO= 4.0 mA - 0.15 0.26 V
IIinput leakage current VI=V
CC or GND; VCC =5.5V - - 0.1 A
ICC supply current VI = VCC or GND; IO = 0 A;
VCC =5.5V --8.0A
ICC additional supply current per input pin; VI=V
CC 2.1 V and
other inputs at VCC or GND;
IO=0A; V
CC = 4.5 V to 5.5 V
pin Dn - 35 126 A
pins CPU, CPD - 140 504 A
pin PL - 65 234 A
pin MR - 105 378 A
Ciinput capacitance - 3.5 - pF
Tamb = 40 C to +85 C
VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - V
VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 V
VOH HIGH-level output voltage VI=V
IH or VIL; VCC =4.5V
IO=20 A4.4--V
IO=4.0 mA 3.84 - - V
VOL LOW-level output voltage VI=V
IH or VIL; VCC =4.5V
IO=20A--0.1V
IO= 4.0 mA - - 0.33 V
IIinput leakage current VI=V
CC or GND; VCC =5.5V - - 1.0 A
ICC supply current VI = VCC or GND; IO = 0 A;
VCC =5.5V --80A
ICC additional supply current per input pin; VI=V
CC 2.1 V and
other inputs at VCC or GND;
IO=0A; V
CC = 4.5 V to 5.5 V
pin Dn - - 157.5 A
pins CPU, CPD - - 630 A
pin PL - - 292.5 A
pin MR - - 472.5 A
amp-m av 2m mmmmm
© Nexperia B.V. 2017. All rights reserved
74HC_HCT139_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 1 — 12 July 2013 12 of 29
Nexperia 74HC193-Q100; 74HCT193-Q100
Presettable synchronous 4-bit binary up/down counter
Tamb = 40 C to +125 C
VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - V
VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 V
VOH HIGH-level output voltage VI=V
IH or VIL; VCC =4.5V
IO=20 A4.4--V
IO=4.0 mA 3.7 - - V
VOL LOW-level output voltage VI=V
IH or VIL; VCC =4.5V
IO=20A--0.1V
IO = 4.0 mA - - 0.4 V
IIinput leakage current VI=V
CC or GND; VCC =5.5V - - 1.0 A
ICC supply current VI = VCC or GND; IO = 0 A;
VCC =5.5V - - 160 A
ICC additional supply current per input pin; VI=V
CC 2.1 V and
other inputs at VCC or GND;
IO=0A; V
CC = 4.5 V to 5.5 V
pin Dn - - 171.5 A
pins CPU, CPD - - 686 A
pin PL - - 318.5 A
pin MR - - 514.5 A
Table 7. Static characteristics type 74HCT193-Q100 …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
Figure 8 Figure 9 Figure 9 Figure 10 Figure 11 Figure 10 D: see Figure 13 D: see Figure 13 ”up-m av 2m AilwmillnN-fl
© Nexperia B.V. 2017. All rights reserved
74HC_HCT139_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 1 — 12 July 2013 13 of 29
Nexperia 74HC193-Q100; 74HCT193-Q100
Presettable synchronous 4-bit binary up/down counter
10. Dynamic characteristics
Table 8. Dynamic characteristics type 74HC193 -Q100
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
tpd propagation
delay CPU, CPD to Qn;
see Figure 8
[1] -
VCC = 2.0 V - 63 215 - 270 - 325 ns
VCC = 4.5 V - 23 43 - 54 - 65 ns
VCC = 6.0 V - 18 37 - 46 - 55 ns
CPU to TCU; see
Figure 9
VCC = 2.0 V - 39 125 - 155 - 190 ns
VCC = 4.5 V - 14 25 - 31 - 38 ns
VCC = 6.0 V - 11 21 - 26 - 32 ns
CPD to TCD; see
Figure 9
VCC = 2.0 V - 39 125 - 155 - 190 ns
VCC = 4.5 V - 14 25 - 31 - 38 ns
VCC = 6.0 V - 11 21 - 26 - 32 ns
PL to Qn; see
Figure 10
VCC = 2.0 V - 69 220 - 275 - 330 ns
VCC = 4.5 V - 25 44 - 55 - 66 ns
VCC = 6.0 V - 20 37 - 47 - 56 ns
MR to Qn; see
Figure 11
VCC = 2.0 V - 58 200 - 250 - 300 ns
VCC = 4.5 V - 21 40 - 50 - 60 ns
VCC = 6.0 V - 17 34 43 - 51 ns
Dn to Qn; see
Figure 10
VCC = 2.0 V - 69 210 - 265 - 315 ns
VCC = 4.5 V - 25 42 - 53 - 63 ns
VCC = 6.0 V - 20 36 - 45 - 54 ns
PL to TCU,PLto
TCD; see Figure 13
VCC = 2.0 V - 80 290 - 365 - 435 ns
VCC = 4.5 V - 29 58 - 73 - 87 ns
VCC = 6.0 V - 23 49 - 62 - 74 ns
MR to TCU,MRto
TCD; see Figure 13
VCC = 2.0 V - 74 285 - 355 - 430 ns
VCC = 4.5 V - 27 57 - 71 - 86 ns
VCC = 6.0 V - 22 48 - 60 - 73 ns
D: see Figure 13 Figure 11 Figure 11 Figure 8 Figure 11 Figure 10 Figure 10 Figure 11 amp-m av znw Ailflnmimm
© Nexperia B.V. 2017. All rights reserved
74HC_HCT139_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 1 — 12 July 2013 14 of 29
Nexperia 74HC193-Q100; 74HCT193-Q100
Presettable synchronous 4-bit binary up/down counter
tpd propagation
delay Dn to TCU,Dnto
TCD; see Figure 13
VCC = 2.0 V - 80 290 - 365 - 435 ns
VCC = 4.5 V - 29 58 - 73 - 87 ns
VCC = 6.0 V - 23 49 - 62 - 74 ns
tTHL HIGH to LOW
output transition
time
see Figure 11
VCC = 2.0 V - 19 75 - 95 - 110 ns
VCC =4.5V - 7 15 - 19 - 22 ns
VCC =6.0V - 6 13 - 16 - 19 ns
tTLH LOW to HIGH
output transition
time
see Figure 11
VCC = 2.0 V - 19 75 - 95 - 110 ns
VCC =4.5V - 7 15 - 19 - 22 ns
VCC =6.0V - 6 13 - 16 - 19 ns
tWpulse width CPU, CPD (HIGH
or LOW); see
Figure 8
VCC = 2.0 V 100 22 - 125 - 150 - ns
VCC =4.5V 20 8 - 25 - 30 - ns
VCC =6.0V 17 6 - 21 - 26 - ns
MR (HIGH); see
Figure 11
VCC = 2.0 V 100 25 - 125 - 150 - ns
VCC =4.5V 20 9 - 25 - 30 - ns
VCC =6.0V 17 7 - 21 - 26 - ns
PL (LOW); see
Figure 10
VCC = 2.0 V 100 19 - 125 - 150 - ns
VCC =4.5V 20 7 - 25 - 30 - ns
VCC =6.0V 17 6 - 21 - 26 - ns
trec recovery time PL to CPU, CPD;
see Figure 10
VCC =2.0V 50 8 - 65 - 75 - ns
VCC =4.5V 10 3 - 13 - 15 - ns
VCC =6.0V 9 2 - 11 - 13 - ns
MR to CPU, CPD;
see Figure 11
VCC =2.0V 50 0 - 65 - 75 - ns
VCC =4.5V 10 0 - 13 - 15 - ns
VCC =6.0V 9 0 - 11 - 13 - ns
Table 8. Dynamic characteristics type 74HC193 …continued-Q100
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
Figure 12 Figure 12 Figure 14 Figure 8 amp-m av 2m Autumn-um
© Nexperia B.V. 2017. All rights reserved
74HC_HCT139_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 1 — 12 July 2013 15 of 29
Nexperia 74HC193-Q100; 74HCT193-Q100
Presettable synchronous 4-bit binary up/down counter
[1] tpd is the same as tPHL and tPLH.
[2] CPD is used to determine the dynamic power dissipation (PD in W):
PD=C
PD VCC2fiN+(CLVCC2fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CLVCC2fo) = sum of outputs.
tsu set-up time Dn to PL; see
Figure 12; note:
CPU = CPD =
HIGH
VCC = 2.0 V 80 22 - 100 - 120 - ns
VCC =4.5V 16 8 - 20 - 24 - ns
VCC =6.0V 14 6 - 17 - 20 - ns
thhold time Dn to PL; see
Figure 12
VCC =2.0V 0 14 - 0 - 0 - ns
VCC =4.5V 0 5- 0 - 0 -ns
VCC =6.0V 0 4- 0 0 -ns
CPU to CPD,
CPD to CPU; see
Figure 14
VCC = 2.0 V 80 22 - 100 - 120 - ns
VCC =4.5V 16 8 - 20 - 24 - ns
VCC =6.0V 8 6 - 17 - 20 - ns
fmax maximum
frequency CPU, CPD; see
Figure 8
VCC = 2.0 V 4.0 13.5 - 3.2 - 2.6 - MHz
VCC =4.5V 20 41 - 16 - 13 - MHz
VCC =6.0V 24 49 - 19 - 15 - MHz
CPD power
dissipation
capacitance
VI = GND to VCC;
VCC =5V;
fi=1MHz
[2] -24- - - - -pF
Table 8. Dynamic characteristics type 74HC193 …continued-Q100
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
Figure 8 Figure 9 Figure 9 Figure 10 Figure 11 Figure 10 D: see Figure 13 D: see Figure 13 D: see Figure 13 Figure 11 Figure 11 Figure 8 Figure 11 Figure 10 ”up-m av 2m AilWMillnrvud
© Nexperia B.V. 2017. All rights reserved
74HC_HCT139_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 1 — 12 July 2013 16 of 29
Nexperia 74HC193-Q100; 74HCT193-Q100
Presettable synchronous 4-bit binary up/down counter
Table 9. Dynamic characteristics type 74HCT193 -Q100
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
tpd propagation
delay CPU, CPD to Qn;
see Figure 8
[1]
VCC = 4.5 V - 23 43 - 54 - 65 ns
CPU to TCU; see
Figure 9
VCC = 4.5 V - 15 27 - 34 - 41 ns
CPD to TCD; see
Figure 9
VCC = 4.5 V - 15 27 - 34 - 41 ns
PL to Qn; see
Figure 10
VCC = 4.5 V - 26 46 - 58 - 69 ns
MR to Qn; see
Figure 11
VCC = 4.5 V - 22 40 - 50 - 60 ns
Dn to Qn; see
Figure 10
VCC = 4.5 V - 27 46 - 58 - 69 ns
PL to TCU,PLto
TCD; see Figure 13
VCC = 4.5 V - 31 55 - 69 - 83 ns
MR to TCU,MRto
TCD; see Figure 13
VCC = 4.5 V - 29 55 - 69 - 83 ns
Dn to TCU,Dnto
TCD; see Figure 13
VCC = 4.5 V - 32 58 - 73 - 87 ns
tTHL HIGH to LOW
output transition
time
see Figure 11
VCC =4.5V - 7 15 - 19 - 22 ns
tTLH LOW to HIGH
output transition
time
see Figure 11
VCC =4.5V - 7 15 - 19 - 22 ns
tWpulse width CPU, CPD (HIGH
or LOW); see
Figure 8
VCC =4.5V 25 11 - 31 - 38 - ns
MR (HIGH); see
Figure 11
VCC =4.5V 20 7 - 25 - 30 - ns
PL (LOW); see
Figure 10
VCC =4.5V 20 8 - 25 - 30 - ns
Figure 10 Figure 11 Figure 12 Figure 12 Figure 14 Figure 8 ”up-m av 2m AilwmillnN-fl
© Nexperia B.V. 2017. All rights reserved
74HC_HCT139_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 1 — 12 July 2013 17 of 29
Nexperia 74HC193-Q100; 74HCT193-Q100
Presettable synchronous 4-bit binary up/down counter
[1] tpd is the same as tPHL and tPLH.
[2] CPD is used to determine the dynamic power dissipation (PD in W):
PD=C
PD VCC2fiN+(CLVCC2fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CLVCC2fo) = sum of outputs.
trec recovery time PL to CPU, CPD;
see Figure 10
VCC =4.5V 10 2 - 13 - 15 - ns
MR to CPU, CPD;
see Figure 11
VCC =4.5V 10 0 - 13 - 15 - ns
tsu set-up time Dn to PL; see
Figure 12; note:
CPU = CPD =
HIGH
VCC =4.5V 16 8 - 20 - 24 - ns
thhold time Dn to PL; see
Figure 12
VCC =4.5V 0 6- 0 - 0 -ns
CPU to CPD,
CPD to CPU; see
Figure 14
VCC =4.5V 16 7 - 20 - 24 - ns
fmax maximum
frequency CPU, CPD; see
Figure 8
VCC =4.5V 20 43 - 16 - 13 - MHz
CPD power
dissipation
capacitance
VI = GND to VCC
1.5 V; VCC =5V;
fi=1MHz
[2] -26- - - - -pF
Table 9. Dynamic characteristics type 74HCT193 …continued-Q100
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
uNsxD-naBV m mm “We
© Nexperia B.V. 2017. All rights reserved
74HC_HCT139_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 1 — 12 July 2013 18 of 29
Nexperia 74HC193-Q100; 74HCT193-Q100
Presettable synchronous 4-bit binary up/down counter
11. Waveforms
Measurement points are given in Table 10.
tPLH and tPHL are the same as tpd.
Logic levels VOL and VOH are typical output voltage levels that occur with the output load.
Fig 8. The clock (CPU, CPD) to output (Qn) propagation delays, the clock pulse width, and the maximum clock
pulse frequency
001aag413
CPU, CPD
input
VI
GND
VOH
VOL
Qn output
tPHL tPLH
tW
VM
VM
1/fmax
Measurement points are given in Table 10.
tPLH and tPHL are the same as tpd.
Logic levels VOL and VOH are typical output voltage levels that occur with the output load.
Fig 9. The clock (CPU, CPD) to terminal count output (TCU,TCD) propagation delays
001aag414
CPU, CPD
input
TCU, TCD
output
tPHL
VI
GND
VOH
VOL
tPLH
VM
VM
© Nexperia B.V. 2017. All rights reserved
74HC_HCT139_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 1 — 12 July 2013 19 of 29
Nexperia 74HC193-Q100; 74HCT193-Q100
Presettable synchronous 4-bit binary up/down counter
Measurement points are given in Table 10.
tPLH and tPHL are the same as tpd.
Logic levels VOL and VOH are typical output voltage levels that occur with the output load.
Fig 10. The parallel load input (PL) and data (Dn) to Qn output propagation delays and PL removal time to clock
input (CPU, CPD)
001aag415
Dn input
V
I
GND
V
I
GND
V
I
GND
V
OH
V
OL
Qn output
CPU, CPD
input
PL input V
M
V
M
V
M
V
M
t
W
t
rec
t
PLH
t
PHL
Measurement points are given in Table 10.
tPLH and tPHL are the same as tpd.
Logic levels VOL and VOH are typical output voltage levels that occur with the output load.
Fig 11. The master reset input (MR) pulse width, MR to Qn propagation delays, MR to CPU, CPD removal time and
output transition times
001aag416
MR input
Qn output
V
OH
V
OL
V
I
GND
V
I
GND
CPU, CPD
input V
M
V
M
V
M
10 %
90 %
t
rec
t
PHL
t
THL
t
W
t
TLH
The dale in nNsxD-na av m AH mummy
© Nexperia B.V. 2017. All rights reserved
74HC_HCT139_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 1 — 12 July 2013 20 of 29
Nexperia 74HC193-Q100; 74HCT193-Q100
Presettable synchronous 4-bit binary up/down counter
The shaded areas indicate when the input is permitted to change for predictable output performance.
Measurement points are given in Table 10.
Logic levels VOL and VOH are typical output voltage levels that occur with the output load.
Fig 12. The data input (Dn) to parallel load input (PL) set-up and hold times
001aag417
Dn input
Qn output
VOL
VOH
GND
VI
GND
VI
PL input VM
tsu th
VM
tsu th
Measurement points are given in Table 10.
tPLH and tPHL are the same as tpd.
Logic levels VOL and VOH are typical output voltage levels that occur with the output load.
Fig 13. The data input (Dn), parallel load input (PL) and the master reset input (MR) to the terminal count outputs
(TCU,TCD) propagation delays
001aag418
PL, MR, Dn
input
TCU, TCD
output
tPLH tPHL
VM
VM
VOL
VOH
GND
VI
Measurement points are given in Table 10.
Fig 14. The CPU to CPD or CPD to CPU hold times
001aag419
CPD or CPU
input
CPU or CPD
input
V
I
GND
V
I
GND
V
M
V
M
t
h
[:1
© Nexperia B.V. 2017. All rights reserved
74HC_HCT139_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 1 — 12 July 2013 21 of 29
Nexperia 74HC193-Q100; 74HCT193-Q100
Presettable synchronous 4-bit binary up/down counter
Table 10. Measurement points
Type Input Output
VMVIVM
74HC193-Q100 0.5 VCC GND to VCC 0.5 VCC
74HCT193-Q100 1.3 V GND to 3 V 1.3 V
Test data is given in Table 11.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator
CL = Load capacitance including jig and probe capacitance
RL = Load resistor
S1 = Test selection switch
Fig 15. Load circuitry for measuring switching times
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aad983
DUT
V
CC
V
CC
VIVO
RT
RLS1
CL
open
G
Table 11. Test data
Type Input Load S1 position
VItr, tfCLRLtPHL, tPLH
74HC193-Q100 VCC 6ns 15pF, 50 pF 1kopen
74HCT193-Q100 3 V 6 ns 15 pF, 50 pF 1 kopen
M nNsxD-na av m AH mummy
© Nexperia B.V. 2017. All rights reserved
74HC_HCT139_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 1 — 12 July 2013 22 of 29
Nexperia 74HC193-Q100; 74HCT193-Q100
Presettable synchronous 4-bit binary up/down counter
12. Application information
Fig 16. Application for cascaded up/down counter with parallel load
001aag420
data input
IC1 IC2
data output
up clock
down clock
carry
borrow
asynchronous
parallel load
reset
D0 D1 D2 D3
Q0 Q1 Q2 Q3
TCU
TCD
MR
CPU
CPD
PL
D0 D1 D2 D3
Q0 Q1 Q2 Q3
TCU
TCD
MR
CPU
CPD
PL
W FMHHHHHH ,/ 1 7 7 Hwy H HJH
© Nexperia B.V. 2017. All rights reserved
74HC_HCT139_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 1 — 12 July 2013 23 of 29
Nexperia 74HC193-Q100; 74HCT193-Q100
Presettable synchronous 4-bit binary up/down counter
13. Package outline
Fig 17. Package outline SOT109-1 (SO16)
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
8
9
1
16
y
pin 1 index
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10 1.45
1.25 0.25 0.49
0.36 0.25
0.19 10.0
9.8 4.0
3.8 1.27 6.2
5.8 0.7
0.6 0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT109-1 99-12-27
03-02-19
076E07 MS-012
0.069 0.010
0.004 0.057
0.049 0.01 0.019
0.014
0.0100
0.0075 0.39
0.38 0.16
0.15 0.05
1.05
0.041
0.244
0.228 0.028
0.020 0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
0 2.5 5 mm
scale
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
© Nexperia B.V. 2017. All rights reserved
74HC_HCT139_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 1 — 12 July 2013 24 of 29
Nexperia 74HC193-Q100; 74HCT193-Q100
Presettable synchronous 4-bit binary up/down counter
Fig 18. Package outline SOT338-1 (SSOP16)
UNIT A1A2A3bpcD
(1) E(1) eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05 1.80
1.65 0.25 0.38
0.25 0.20
0.09 6.4
6.0 5.4
5.2 0.65 1.25
7.9
7.6 1.03
0.63 0.9
0.7 1.00
0.55 8
0
o
o
0.130.2 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT338-1 99-12-27
03-02-19
(1)
wM
bp
D
HE
E
Z
e
c
vMA
X
A
y
18
16 9
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
MO-150
pin 1 index
0 2.5 5 mm
scale
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1
A
max.
2
ll “<7 \"/«_="" ’w‘="" whhhmhf="" *="" a="" i="" j="" 0‘!="" l?="" hhw="" ‘hhhh="" k”="" ,d="" ,‘l—="" |:|="" s©="">
© Nexperia B.V. 2017. All rights reserved
74HC_HCT139_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 1 — 12 July 2013 25 of 29
Nexperia 74HC193-Q100; 74HCT193-Q100
Presettable synchronous 4-bit binary up/down counter
Fig 19. Package outline SOT403-1 (TSSOP16)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 5.1
4.9 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.40
0.06 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT403-1 MO-153 99-12-27
03-02-18
wM
bp
D
Z
e
0.25
18
16 9
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
A
max.
1.1
pin 1 index
amp-m av znw mmmmm
© Nexperia B.V. 2017. All rights reserved
74HC_HCT139_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 1 — 12 July 2013 26 of 29
Nexperia 74HC193-Q100; 74HCT193-Q100
Presettable synchronous 4-bit binary up/down counter
14. Abbreviations
15. Revision history
Table 12. Abbreviations
Acronym Description
CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
LSTTL Low-power Schottky Transistor-Transistor Logic
MM Machine Model
MIL Military
TTL Transistor-Transistor Logic
Table 13. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT193_Q100 v.1 20130712 Product data sheet - -
amp-m av 2m mmmmm
© Nexperia B.V. 2017. All rights reserved
74HC_HCT139_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 1 — 12 July 2013 27 of 29
Nexperia 74HC193-Q100; 74HCT193-Q100
Presettable synchronous 4-bit binary up/down counter
16. Legal information
16.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nexperia.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the Nexperia product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no
responsibility for the content in this document if provided by an information
source outside of Nexperia.
In no event shall Nexperia be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of Nexperia.
Right to make changes — Nexperia reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use in automotive applications — This Nexperia
product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of a Nexperia product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. Nexperia and its suppliers accept no liability for
inclusion and/or use of Nexperia products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the Nexperia
product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Nexperia does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using Nexperia
products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). Nexperia does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — Nexperia
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nexperia.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. Nexperia hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of Nexperia products by customer.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
hnE://www.nexgeria salesaddresses®nexgeria amp-m av 2m whimsy-um
© Nexperia B.V. 2017. All rights reserved
74HC_HCT139_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 1 — 12 July 2013 28 of 29
Nexperia 74HC193-Q100; 74HCT193-Q100
Presettable synchronous 4-bit binary up/down counter
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Nexperia 74HC193-Q100; 74HCT193-Q100
Presettable synchronous 4-bit binary up/down counter
18. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
6 Functional description . . . . . . . . . . . . . . . . . . . 6
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8
8 Recommended operating conditions. . . . . . . . 8
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 9
10 Dynamic characteristics . . . . . . . . . . . . . . . . . 13
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
12 Application information. . . . . . . . . . . . . . . . . . 22
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 23
14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 26
15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 26
16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 27
16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 27
16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 27
16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 28
17 Contact information. . . . . . . . . . . . . . . . . . . . . 28
18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
© Nexperia B.V. 2017. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release:
12 July 2013

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