SM802zzz Datasheet by Microchip Technology

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‘ MICRQICHIP SMBOZXXX
2019 Microchip Technology Inc. DS20006176A-page 1
SM802XXX
Features
115 fs at 156.25 MHz (1.875 MHz to 20 MHz)
265 fs at 156.25 MHz (12 kHz to 20 MHz)
On-Chip Power Supply Regulation for Excellent
Board-Level Power Supply Noise Immunity
Generates up to 8 Combinations of Differential or
16 Single-Ended Clock Outputs
- LVPECL, LVDS, HCSL, LVCMOS (SE or Diff)
Selectable Input:
- Crystal: 11.4 MHz to 27 MHz
- Reference Input: 11.4 MHz to 80 MHz
No External Crystal Oscillator Capacitors
Required
2.5V or 3.3V Operating Power Supply
Available in Industrial Temperature Range
Available in Green, RoHS, and PFOS Compliant
QFN Packages:
- 44-pin, 7 mm × 7 mm
- 32-pin, 5 mm × 5 mm
- 24-pin, 4 mm × 4 mm
- 16-pin, 3 mm × 3.5 mm
Applications
1/10/40/100 Gigabit Ethernet (GbE)
•SONET/SDH
PCI Express
CPRI/OBSAI – Wireless Base Station
Fibre Channel
• SAS/SATA
•DIMM
General Description
The SM802xxx series is a member of the ClockWorks®
family of devices from Microchip and provide an
extremely low-noise timing solution for applications
such as (1-100) Gigabit Ethernet, SONET, wireless
base station, satellite communication, Fibre Channel,
SAS/SATA, and PCIe. It is based upon a unique PLL
architecture that provides less than 250 fs phase jitter.
The devices operate from a 2.5V or 3.3V power supply
and synthesize up to 8 different combinations
(LVPECL, LVDS, HCSL) of differential or 16
single-ended output clocks. The devices accept an
external reference clock or crystal input.
The SM802xxx series is fully programmable and a web
tool is available to configure a part for samples at the
ClockWorks Configurator tool.
Flexible Ultra-Low Jitter Clock Synthesizer
SM802XXX
DS20006176A-page 2 2019 Microchip Technology Inc.
Package Types
SM802XXX
Option 1: 44-Pin 7 mm x 7 mm QFN
(Top View)
SM802XXX
Option 3: 24-Pin 4 mm x 4 mm QFN
(Top View)
SM802XXX
Option 2: 32-Pin 5 mm x 5 mm QFN
(Top View)
SM802XXX
Option 4: 24-Pin 4 mm x 4 mm QFN
(Top View)
1
2
3
4
5
6
7
8
33
32
31
30
29
28
27
26
12 13 14 15 16 17 18 19
44 43 42 41 40 39 38 37
/QF
QF
VSSO2
/QG
QG
VSSO2
/QH
QH
QC
/QC
VDDO1
TEST
QB
/QB
TEST
QA
VSSO2
/QE
QE
VDDO2
VDDO2
VSSO1
VDDO1
VDDO1
9
10
11
25
24
23
20 21 22
35
PLL_BYPASS
XTAL_SEL
TEST
/QA
VSSO1
VSS
36 34
TEST
/QD
QD
VDDO2
OE1
FSEL
VDD
VDD
REF_IN
XIN
XOUT
OE2
VSS
TEST
VDDO2
VSSO2
/QG
QG
PLL_BYPASS
XTAL_SEL
TEST
VDD
XIN
REF_IN
OE1
FSEL
VDD
XOUT
TEST
OE2
1
2
3
4
5
6
7
8
9101112131415 16
24
23
22
21
20
19
18
17
32 31 30 29 28 27 26 25
TEST
VDDO1
QB
/QB
TEST
VSSO1
VSS
VSS
VSSO1
VSSO2
/QE
QE
VDDO2
VDDO1
QD
/QD
VDDO2
VSSO2
/QG
QG
PLL_BYPASS
XTAL_SEL
VDDO1
QB
/QB
TEST
VSS
VSS
/QD
VSSO1
/QE
QE
QD
TEST
XIN
REF_IN
VDD
TEST
XOUT
TEST
78 9101112
18
17
16
15
14
13
24 23 22 21 20 19
1
2
3
4
5
6
VDD
VSSO2
PLL_BYPASS
XTAL_SEL
TEST
FSEL
TEST
VDDO1
TEST
VSS
VSS
VSS
VSSO1
/QE
QE
VDDO2
QD
/QD
XOUT
XIN
REF_IN
OE1
TEST
OE2
78 9101112
18
17
16
15
14
13
24 23 22 21 20 19
1
2
3
4
5
6
SM802XXX
Option 5: 16-Pin 3 mm x 3.5 mm QFN
(Top View)
SM802XXX
Option 6: 16-Pin 3 mm x 3.5 mm QFN
(Top View)
/QF
QF
VSS
TEST
VSS
TEST
VSS
VSS
TEST
/QD
QD
VDDO1/2
TEST
REF_IN
FSEL
VDD
1
2
3
4
56 78
12
11
10
9
16 15 14 13
/QF
QF
VSS
TEST
VSS
TEST
VSS
VSS
TEST
/QD
QD
VDDO1/2
TEST
XOUT
XIN
VDD
1
2
3
4
56 78
12
11
10
9
16 15 14 13
2019 Microchip Technology Inc. DS20006176A-page 3
SM802XXX
Block Diagram
PLL 1
REFIN
QE
QF
QG
VDD Power Rail Regulation
FSEL
OE2
OE1
VSSO 2
VSSO 1
VDDO 2
VDDO 1
VSS
VDD
÷
÷
QH
QA
QB
QC
QD
PLL_BYPASS
XTAL_SEL
Div 1
Div 2
XO
INTERNAL PULL-UP
1
0
0
1
0
1
INTERNAL
PULL-UPS
INTERNAL
PULL-DOWN
SM802XXX
DS20006176A-page 4 2019 Microchip Technology Inc.
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Supply Voltage (VDD, VDDO1/2).................................................................................................................................+4.6V
Input Voltage (VIN).............................................................................................................................–0.5V to VDD + 0.5V
Operating Ratings ††
Supply Voltage (VDD, VDDO1/2).......................................................................................................... +2.375V to +3.465V
Notice: Exceeding the absolute maximum ratings may damage the device.
†† Notice: The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
DC ELECTRICAL CHARACTERISTICS (Note 1)
Electrical Characteristics: VDD = VDDO1/2 = 3.3V ±5% or 2.5V ±5%; VDD = 3.3V ±5%, VDDO1/2 = 3.3V ±5% or 2.5V
±5%; TA = –40°C to +85°C.
Parameter Symbol Min. Typ. Max. Units Conditions
3.3V Operating Voltage VDD,
VDDO1/2
3.135 3.3 3.465 VV
DDO1 = VDDO2
2.5V Operating Voltage 2.375 2.5 2.625
Total Supply Current,
VDD + VDDO
IDD
—275345
mA
8 LVPECL, 312.5 MHz (44-pin QFN)
Outputs open
—150185
4 HCSL (PCIe), 100 MHz (32-pin or
24-pin QFN)
Outputs 50 to VSS
—7090
2 LVCMOS, 125 MHz
(16-pin QFN)
Outputs open
Note 1: The circuit is designed to meet the AC and DC specifications shown in the Electrical Characteristics tables
after thermal equilibrium has been established.
LVCMOS INPUTS (OE1, OE2, PLL_BYPASS, XTAL_SEL, FSEL) DC ELECTRICAL
CHARACTERISTICS (Note 1)
Electrical Characteristics: VDD = 3.3V ±5% or 2.5V ±5%; TA = –40°C to +85°C.
Parameter Symbol Min. Typ. Max. Units Conditions
Input High Voltage VIH 2—V
DD +
0.3
V—
Input Low Voltage VIL –0.3 0.8 V —
Input High Current IIH ——150µAV
DD = VIN = 3.465V
Input Low Current IIL –150 µA VDD = 3.465V, VIN = 0V
Note 1: The circuit is designed to meet the AC and DC specifications shown in the Electrical Characteristics tables
after thermal equilibrium has been established.
D01! A L VDDO
2019 Microchip Technology Inc. DS20006176A-page 5
SM802XXX
LVDS OUTPUT DC ELECTRICAL CHARACTERISTICS (Note 1)
Electrical Characteristics: VDD = VDDO1/2 = 3.3V ±5% or 2.5V ±5%; VDD = 3.3V ±5%, VDDO1/2 = 3.3V ±5% or 2.5V
±5%; TA = –40°C to +85°C. RL = 100 across Q1 and /Q1.
Parameter Symbol Min. Typ. Max. Units Conditions
Differential Output Voltage VOD 275 350 475 mV Figure 5-8
VOD Magnitude Change VOD ——40mV
Offset Voltage VOS 1.15 1.25 1.50 V
VOS Magnitude Change VOS ——50mV
Note 1: The circuit is designed to meet the AC and DC specifications shown in the Electrical Characteristics tables
after thermal equilibrium has been established.
HCSL OUTPUT DC ELECTRICAL CHARACTERISTICS (Note 1)
Electrical Characteristics: VDD = VDDO1/2 = 3.3V ±5% or 2.5V ±5%; VDD = 3.3V ±5%, VDDO1/2 = 3.3V ±5% or 2.5V
±5%; TA = –40°C to +85°C. RL = 50 to VSS.
Parameter Symbol Min. Typ. Max. Units Conditions
Output High Voltage VOH 660 700 850 mV
Output Low Voltage VOL –150 0 27 mV —
Output Voltage Swing VSWING 250 350 550 mV
Note 1: The circuit is designed to meet the AC and DC specifications shown in the Electrical Characteristics tables
after thermal equilibrium has been established.
LVPECL OUTPUT DC ELECTRICAL CHARACTERISTICS (Note 1)
Electrical Characteristics: VDD = VDDO1/2 = 3.3V ±5% or 2.5V ±5%; VDD = 3.3V ±5%, VDDO1/2 = 3.3V ±5% or 2.5V
±5%; TA = –40°C to +85°C. RL = 50 to VDDO –2V.
Parameter Symbol Min. Typ. Max. Units Conditions
Output High Voltage VOH VDDO
1.145
VDDO
0.97
VDDO
0.845
V—
Output Low Voltage VOL VDDO
1.945
VDDO
1.77
VDDO
1.645
V—
Output Voltage Swing VSWING 0.6 0.8 1.0 V
Note 1: The circuit is designed to meet the AC and DC specifications shown in the Electrical Characteristics tables
after thermal equilibrium has been established.
LVCMOS OUTPUT DC ELECTRICAL CHARACTERISTICS (Note 1)
Electrical Characteristics: VDD = VDDO1/2 = 3.3V ±5% or 2.5V ±5%; VDD = 3.3V ±5%, VDDO1/2 = 3.3V ±5% or 2.5V
±5%; TA = –40°C to +85°C. RL = 50 to VDDO/2.
Parameter Symbol Min. Typ. Max. Units Conditions
Output High Voltage VOH VDDO
0.7
—— VFigure 5-9
Output Low Voltage VOL ——0.6VFigure 5-9
Note 1: The circuit is designed to meet the AC and DC specifications shown in the Electrical Characteristics tables
after thermal equilibrium has been established.
SM802XXX
DS20006176A-page 6 2019 Microchip Technology Inc.
REF_IN DC ELECTRICAL CHARACTERISTICS (Note 1)
Electrical Characteristics: VDD = 3.3V ±5% or 2.5V ±5%; TA = –40°C to +85°C.
Parameter Symbol Min. Typ. Max. Units Conditions
Input High Voltage VIH 1.1 — VDD +
0.3
V—
Input Low Voltage VIL –0.3 0.6 V —
Input Current IIN –5 5 µA XTAL_SEL = VIL, VIN = 0V to VDD
20 µA XTAL_SEL = VIH, VIN = VDD
Note 1: The circuit is designed to meet the AC and DC specifications shown in the Electrical Characteristics tables
after thermal equilibrium has been established.
CRYSTAL CHARACTERISTICS
Electrical Characteristics: VDD = 3.3V ±5% or 2.5V ±5%; TA = –40°C to +85°C.
Parameter Min. Typ. Max. Units Conditions
Mode of Oscillation Fundamental, parallel
resonant
10 pF load capacitance
Frequency 11.4 27 MHz —
Equivalent Series Resistance (ESR) 30
Shunt Capacitance, C0 2 5 pF
Correlation Drive Level 10 100 µW
LVPECL AC ELECTRICAL CHARACTERISTICS (Note 1, Note 2, Note 3, Note 4)
Electrical Characteristics: VDDA = VDD = 3.3V ±5% or 2.5V ±5%, VDDO = 2.5V or 3.3V ±5%, TA = –40°C to +85°C,
unless otherwise noted.
Parameter Symbol Min. Typ. Max. Units Conditions
Output Frequency FOUT 11 840 MHz —
LVPECL Output Rise/Fall
Time
tr/tf80 175 350 ps 20% - 80%
Output Duty Cycle ODC 48 50 52 % < 350 MHz
45 50 55 % 350 MHz
Output-to-Output Skew TSKEW ——45psNote 5
PLL Lock Time TLOCK ——20ms
RMS Phase Jitter @
156.25 MHz
Tjit(Ø) 265 fs Integration Range (12 kHz to
20 MHz)
115 fs Integration Range (1.875 MHz to
20 MHz)
Note 1: The circuit is designed to meet the AC and DC specifications shown in the Electrical Characteristics tables
after thermal equilibrium has been established.
2: See Figure 5-6 through Figure 5-9 for load test circuit examples.
3: All phase noise measurements were taken with an Agilent 5052B phase noise system.
4: Output load is 50 to VDD – 2V.
5: Defined as skew between outputs at the same supply voltage and with equal load conditions; Measured at
the output differential crossing points.
2019 Microchip Technology Inc. DS20006176A-page 7
SM802XXX
LVDS AC ELECTRICAL CHARACTERISTICS (Note 1, Note 2, Note 3, Note 4)
Electrical Characteristics: VDDA = VDD = 3.3V ±5% or 2.5V ±5%, VDDO = 2.5V or 3.3V ±5%, TA = –40°C to +85°C,
unless otherwise noted.
Parameter Symbol Min. Typ. Max. Units Conditions
Output Frequency FOUT 11.4 840 MHz —
LVDS Output Rise/Fall
Time
tr/tf100 160 400 ps 20% - 80%
Output Duty Cycle ODC 48 50 52 % < 350 MHz
45 50 55 % 350 MHz
Output-to-Output Skew TSKEW ——45psNote 5
PLL Lock Time TLOCK ——20ms
RMS Phase Jitter @
156.25 MHz
Tjit(Ø) 110 fs Integration Range (1.875 MHz to
20 MHz)
Note 1: The circuit is designed to meet the AC and DC specifications shown in the Electrical Characteristics tables
after thermal equilibrium has been established.
2: See Figure 5-6 through Figure 5-9 for load test circuit examples.
3: All phase noise measurements were taken with an Agilent 5052B phase noise system.
4: Outputs terminated 100 between Q and /Q. All unused outputs must be terminated.
5: Defined as skew between outputs at the same supply voltage and with equal load conditions; Measured at
the output differential crossing points.
HCSL AC ELECTRICAL CHARACTERISTICS (Note 1, Note 2, Note 3, Note 4)
Electrical Characteristics: VDDA = VDD = 3.3V ±5% or 2.5V ±5%, VDDO = 2.5V or 3.3V ±5%, TA = –40°C to +85°C,
unless otherwise noted.
Parameter Symbol Min. Typ. Max. Units Conditions
Output Frequency FOUT 11.4 840 MHz —
Output Rise/Fall Time tr/tf150 300 450 ps 20% - 80%
Output Duty Cycle ODC 48 50 52 % < 350 MHz
45 50 55 % 350 MHz
Output-to-Output Skew TSKEW ——50psNote 5
PLL Lock Time TLOCK ——20ms
RMS Phase Jitter @
100 MHz
Tjit(Ø) 265 fs Integration Range (12 kHz to
20 MHz)
115 fs Integration Range (1.875 MHz to
20 MHz)
Note 1: The circuit is designed to meet the AC and DC specifications shown in the Electrical Characteristics tables
after thermal equilibrium has been established.
2: See Figure 5-6 through Figure 5-9 for load test circuit examples.
3: All phase noise measurements were taken with an Agilent 5052B phase noise system.
4: Output load is 50 to VDD / 2.
5: Defined as skew between outputs at the same supply voltage and with equal load conditions; Measured at
the output differential crossing points.
SM802XXX
DS20006176A-page 8 2019 Microchip Technology Inc.
LVCMOS AC ELECTRICAL CHARACTERISTICS (Note 1, Note 2, Note 3, Note 4)
Electrical Characteristics: VDDA = VDD = 3.3V ±5% or 2.5V ±5%, VDDO = 2.5V or 3.3V ±5%, TA = –40°C to +85°C,
unless otherwise noted.
Parameter Symbol Min. Typ. Max. Units Conditions
Output Frequency FOUT 11.4 250 MHz —
REF_IN Frequency FREF 11 80 MHz —
Output Rise/Fall Time tr/tf100 500 ps 20% - 80%
Output Duty Cycle ODC 45 50 55 %
Output-to-Output Skew TSKEW ——60psNote 5
PLL Lock Time TLOCK ——20ms
RMS Phase Jitter @
125 MHz
Tjit(Ø) 115 fs Integration Range (1.875 MHz to
20 MHz)
Note 1: The circuit is designed to meet the AC and DC specifications shown in the Electrical Characteristics tables
after thermal equilibrium has been established.
2: See Figure 5-6 through Figure 5-9 for load test circuit examples.
3: All phase noise measurements were taken with an Agilent 5052B phase noise system.
4: Output load is 50 to VDD / 2.
5: Defined as skew between outputs at the same supply voltage and with equal load conditions; Measured at
the output differential crossing points.
2019 Microchip Technology Inc. DS20006176A-page 9
SM802XXX
TEMPERATURE SPECIFICATIONS
Parameters Sym. Min. Typ. Max. Units Conditions
Temperature Ranges
Ambient Temperature Range TA–40 +85 °C —
Lead Temperature +260 °C Soldering, 20s
Case Temperature +115 °C
Storage Temperature Range TS–65 +150 °C —
Package Thermal Resistances (Note 1)
Junction Thermal Resistance, 7 x 7
QFN-44Ld JA —24 —°C/W
Junction Thermal Resistance, 5 x 5
QFN-32Ld JA —34 —°C/W
Junction Thermal Resistance, 4 x 4
QFN-24Ld JA —50 —°C/W
Junction Thermal Resistance, 3 x 3.5
QFN-16Ld JA —60 —°C/W
Note 1: Package thermal resistance assumes the exposed pad is soldered (or equivalent) to the device’s most
negative potential on the PCB.
SM802XXX
DS20006176A-page 10 2019 Microchip Technology Inc.
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1: PIN FUNCTION TABLE
Pin Numbers by Package Option
Pin
Name Pin Type Pin
Level Pin Function
#1
44-pin
#2
32-pin
#3
24-pin
#4
24-pin
#5
16-pin
#6
16-pin
18 13 10 9 6 XIN I,O (SE) Crystal connections.
19 14 11 10 7 XOUT
17 12 9 8 7 REF_IN I, (SE) LVCMOS Reference clock input.
14 10 6 6 FSEL I, (SE) LVCMOS
Frequency Select, divides
output frequencies by 2.
0 = FREQ,
1 = FREQ/2, 45 k pull-up
10664
XTAL
SEL I, (SE) LVCMOS
XTAL Select, selects between
XTAL and REF_IN
0 = REF_IN,
1 = XTAL, 45 k pull-up
9553PLL
BYPASS I, (SE) LVCMOS
Bypasses the PLL and switches
the XTAL or REF_IN frequency
to all outputs
0 = PLL mode,
1 = Bypass mode, 45 k
pull-down
25————— /QA O Various
Clock Outputs from Bank 1
Each output can be
programmed to its own logic
type: LVPECL, LVDS, HCSL, or
LVCMOS (Note 1)
26————— QA
28 21 16 /QB O Various
29 22 17 QB
32————— /QC O Various
33————— QC
35 25 20 19 14 14 /QD O Various
36 26 21 20 15 15 QD
41 30 23 22 /QE O Various
Clock Outputs from Bank 2
Each output can be
programmed to its own logic
type: LVPECL, LVDS, HCSL, or
LVCMOS (Note 1)
42 31 24 23 QE
1 ——— 1 1 /QF O Various
2 ——— 2 2 QF
433/QG O Various
544—QG
7 ————— /QH O Various
8 ————— QH
31 23 18 17 16 16
VDDO1 PWR Power Supply for the outputs on
Bank 1.
3727————
38—————
16 1 1 24 16 16
VDDO2 PWR Power Supply for the outputs on
Bank 2.
4332————
44—————
24 19 22 21 VSSO1 PWR Power Supply Ground for the
outputs on Bank 1.
3928————
2019 Microchip Technology Inc. DS20006176A-page 11
SM802XXX
3222
VSSO2 PWR Power Supply Ground for the
outputs on Bank 2.
6 29————
40—————
1177544
TEST —
Used for production test.
Do not connect anything to
these pins.
20 15 12 11 8 8
27 20 15 16 11 11
30 24 19 18 13 13
34—————
1288155VDD PWR Core power supply.
13 9 ————
21 17 13 13 3 3
VSS PWR Core power supply ground.
23 18 14 14 9 9
15 10 10
————1212
——————EPAD —
The exposed pad must be
connected to the VSS ground
plane.
15 11 7 OE1 I, (SE) LVCMOS
Output Enable 1, OUT1–8
disables to tri-state,
0 = Disabled,
1 = Enabled, 45 k pull-up
22 16 12 OE2 I, (SE) LVCMOS
Output Enable 2, OUT9–16
disables to tri-state,
0 = Disabled,
1 = Enabled, 45 k pull-up
Note 1: In the case of LVCMOS, an output pair can provide two single-ended LVCMOS outputs.
TABLE 2-1: PIN FUNCTION TABLE (CONTINUED)
Pin Numbers by Package Option
Pin
Name Pin Type Pin
Level Pin Function
#1
44-pin
#2
32-pin
#3
24-pin
#4
24-pin
#5
16-pin
#6
16-pin
TABLE 2-2: TRUTH TABLE
Control Pin Internal Resistor
(Note 1)0 Level (Low) 1 Level (High)
OE1 Pull-Up Outputs QA~QD disabled to Hi Z
(Tri-State)
Outputs QA~QD enabled
OE2 Pull-Up Outputs QE~QH disabled to Hi Z
(Tri-State)
Outputs QE~QH enabled
XTAL_SEL Pull-Up External reference clock input is
selected
Crystal is selected
FSEL; (Note 2) Pull-Up Output = Target Frequency x2 or /2 Output = Target Frequency
PLL_BYPASS Pull-Down PLL frequency is connected to outputs PLL is bypassed, Crystal or Ref-in
is connected to outputs
Note 1: The internal resistor sets the default logic level on the control pin when the pin is left open. Pull up will set
default logic 1 and pull down will set default logic 0. When the pin is not available on a specific configura-
tion, the level will be the default logic level.
2: The FSEL pin behavior can be programmed between two types:
- At FSEL=0 (low), the output frequency changes to multiply by 2.
- At FSEL=0 (low), the output frequency changes to divide by 2.
The FSEL function affects all outputs the same way, all outputs change when the FSEL pin level changes.
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SM802XXX
DS20006176A-page 12 2019 Microchip Technology Inc.
3.0 PHASE NOISE PLOTS
FIGURE 3-1: 100 MHz HCSL, 254 fsRMS for 12 kHz to 20 MHz Integration Range.
FIGURE 3-2: 125 MHz LVCMOS, 114 fsRMS for 1.875 MHz to 20 MHz Integration Range.
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2019 Microchip Technology Inc. DS20006176A-page 13
SM802XXX
FIGURE 3-3: 156.25 MHz LVPECL, 245fsRMS for 12 kHz to 20 MHz Integration Range.
FIGURE 3-4: 644.53125 MHz LVDS, 293fsRMS for 12 kHz to 20 MHz Integration Range.
SM802XXX
DS20006176A-page 14 2019 Microchip Technology Inc.
4.0 APPLICATION INFORMATION
4.1 Input Reference
When operating with a crystal input reference, do not
apply a switching signal to REF_IN.
4.2 Crystal Layout
Keep the layers under the crystal as open as possible
and do not place switching signals or noisy supplies
under the crystal. Crystal load capacitance is built
inside the die, so no external capacitance is needed.
See the Microchip application note ANTC207 for
further details.
4.3 Power Supply Decoupling
Place the smallest value decoupling capacitor (4.7 nF
above) between the VDD and VSS pins, as close as
possible to those pins and at the same side of the PCB
as the IC. The shorter the physical path from VDD to
capacitor and back from capacitor to VSS, the more
effective the decoupling. Use one 4.7 nF capacitor for
each VDD pin on the SM802xxx.
The impedance value of the ferrite bead (FB) needs to
be between 80 and 240 with a saturation current
150 mA.
The VDDO1 and VDDO2 pins connect directly to the VDD
plane. All VDD pins on the SM802xxx connect to VDD
after the power supply filter.
4.4 Output Traces
Design the traces for the output signals according to
the output logic requirements. If LVCMOS is
unterminated, add a 30 resistor in series with the
output, as close as possible to the output pin, and start
a 50 trace on the other side of the resistor.
For differential traces, you can either use a differential
design or two separate 50 traces. For EMI reasons, it
is better to use a differential design.
LVDS can be AC-coupled or DC-coupled to its
termination.
l ill FIGURE 5-1: Preferred Filter, Using the MI094300 or MICQ4310 Ripple Blocker. /0 FIGURE 5-3: Duty Cycle Timing. FIGURE 5-6: LVPECL Output Load and FIGURE 5-4: All Outputs Rise/Fall Time. IQ PHASE N0 = E: = FIGURE 5-7: HCSL Output Load and Test FIGURE 5-5: RMS Phase/Noise/Jitter.
2019 Microchip Technology Inc. DS20006176A-page 15
SM802XXX
5.0 POWER SUPPLY FILTERING RECOMMENDATIONS
FIGURE 5-1: Preferred Filter, Using the MIC94300 or MIC94310 Ripple Blocker.
FIGURE 5-2: Alternative, Traditional Filter, Using a Ferrite Bead.
FIGURE 5-3: Duty Cycle Timing.
FIGURE 5-4: All Outputs Rise/Fall Time.
FIGURE 5-5: RMS Phase/Noise/Jitter.
FIGURE 5-6: LVPECL Output Load and
Test Circuit.
FIGURE 5-7: HCSL Output Load and Test
Circuit.
VDD PLANE
1μF 1μF 0.01μF 4.7nF
VDD
RIPPLE
BLOCKER
VDD PLANE
10μF 0.047μF 0.01μF 4.7nF
VDD
FB
0.5
VOH
VOL
VSWING
Q0
nQ0
T1
T2
ODC=
T
1
T2
×100%
80%
20%
TRTF
RMS PHASE NOISE/JITTER
NOISE POWER
PHASE NOISE PLOT
f1f2
OFFSET FREQUENCY
PHASE NOISE MASK
RMS JITTER = ¥AREA UNDER THE MASKED PHASE NOISE PLOT
Z0 = 50
50
Q
/Q
GND
VDD, VDDA, VDDO
2V
–1.3V or –0.5V
OSCILLOSCOPE
Z0 = 50
50
Q
/Q
VSS
VDDO
OSCILLOSCOPE
FIGURE 5-8: LVDS Output Load and Test FIGURE 5-9: LVCMOS Output Load and FIGURE 5-10: Crystal Input Interface.
SM802XXX
DS20006176A-page 16 2019 Microchip Technology Inc.
FIGURE 5-8: LVDS Output Load and Test
Circuit.
FIGURE 5-9: LVCMOS Output Load and
Test Circuit.
FIGURE 5-10: Crystal Input Interface.
Z0 = 50100
Q0
/Q0
GND
VDD = VDDA = 3.3V
VDDO = 2.5V or 3.3V
Z0 = 50
50
Q
–VDDO/2
+VDDO/2
OSCILLOSCOPE
VDDO
VSS
10pF PARALLEL CRYSTAL
XTAL_IN
XTAL_OUT
TITLE 44 LEAD QFN 7x7mm PACKAGE OUTLINE & RECOMMENDED LAND PATTERN DRAWING “IQFN77744LD7P171 UNIT | MM mu #1 u) 33010.10 Po 20 10010 05 FUN 1 \D——\ 05010 as 2 350:0 10 90 0:00 A o 50 BSC 4 Lamas 3mm may :DHDDHDHHDHH |:l WW : a 02 E E 0.0070475 is El 3 :u g :u 3% 2 EL ” :u 19/ E DUDE DUDE EDD: 32:: “‘le n A m an . m mung VWAIZ u m m 2 m ALLDHAILE ma 1; aumm in ALL mam 3 mm m 1: m4 m erL n ann um]: A um mm m mu nun-m mm mm» m :le mm .5 an—nzsu n1 mm. m mm .: (Winn m mu rnx m Yw mrmwca mm mm 55 5.1;“ “€va (mm mu) wzwzszm “an mm mm m umrm m “a. non-194nm m: m mmw, mm
2019 Microchip Technology Inc. DS20006176A-page 17
SM802XXX
6.0 PACKAGING INFORMATION
44-Lead QFN Package Outline and Recommended Land Pattern
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging.
TITLE 3 LEAD QFN ExSmm PACKAGE OUTLINE & RECOIVFMENDEJ LAND PATTERN DRAWING # IQF‘N55i32LDiPL71 UNIT —75wtoos % mm m M m‘lma\ :1 No 2 + 500x005 M 0351005 4L mm sEch mm a m REF uno~no§ 3] E VIEW "ma 1 m mm: mung I: m m a m muwmz am I: “new In ALL mkztrmus a PM an [s an my mm ya my: mm W q mu m m RD 2a rush m UUUUUUUU 3mm as N + 4 flflflflflflfl L ‘JUUUUUU flflflflflfl 17 ways ”an EEITTEIM VIEW DDDDDDDD 02320 uz 0504032 DDDDDDDD n in as: DDDDDDDD [DDDDDD 14mm 4 ZfllflDS 1—1 Imp: , ‘ my mm: m mm rmm anchE wsz vu m: SHEIULD x: 173%an m nwzm Am) mum n: cuNNEcrEn m cm: ruse m mam mmmmcz 5 man mums: (Mum AREA) mum: sums? mum mums u» muss: my arm 057mm m m ma, m7 Mn mm m: :Huuul a:
SM802XXX
DS20006176A-page 18 2019 Microchip Technology Inc.
32-Lead QFN Package Outline and Recommended Land Pattern
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging.
TITLE 24 LEA) QFN 4x4mm PACKAGE OUTLINE & RECOMMENDED LAND PATTERN DRAWING 1t IQFNQ‘IEZZILDEPLEI UNIT | MN games pm «I In W x W «i 4 no BSC 4— Dr» W a, mm ‘ mums PU U U U LP 2 3 I 3 3 mm + C2 “25’ ”5 C 25u1n05 4‘00 E30 3 C Em up 0500 Est): C i 3 4; H H H (I H H 25mm w T P v w w mm ., 2. 3 mm 2 3 481002 E D D D D D a Cl |:| m 055010.050 |:| |:| g Q o 05 C L, L E + Cl SEATING PLANE LoQozm 025 T C' E 0023 3 Cl Cl a Cl |:| SIDE vIEw 2 JDDDDL Hanna—— BEAiflfl TEOIOTD NEITET 1‘ MAX PACKAGE VARPAGE IS n‘ns MM 2‘ MAX ALLWAELE BURR I: DTD76MM RECDMMENDED LAND PATTERN Nam ., 5 IN ALL DIRECTIDNS 3‘ PIN #1 IS [IN TEIP WILL BE LASER MARKED 4‘ RED CIRCLE IN LAND PATTERN INDICATE THERMAL VIAT sIzE SHEIULD BE n‘auiu‘ssM IN DIAMETER AND SHEIULD BE CUNNECTED Tn END FDR MAX THERMAL PERFDPMANCE s EREEN REETANELES (SHADEEI AREA) mutate SEILDER STENEIL EIPENINE nu EXFEISED PAD AREAT S[ZE SHEIULD BE lTUflxlDfl MM IN SIZE, [ED MM PITCM
2019 Microchip Technology Inc. DS20006176A-page 19
SM802XXX
24-Lead QFN Package Outline and Recommended Land Pattern
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging.
TITLE 16 LEA: QFN 3.0x3.5mm PACKAGE OUTLINE & RECOMMENDED LAND PATTERN DRAWING # IQF‘N3035716LD7PL71 UNIT MM PIN I nuT 3v MARKINE ‘ Iannmnsn Exp w PIN NI IDENTIFICATJEIN \. U U U U‘ man 3 momma 25001030 3 CEoTESouxnusn P 3 C l 3 CE 4L U fl 0 afinnu m mammal k: mm 050% TDP VIEw EDIIDM yum m a 1 m u. 3 can Esc & n on 02030 R r‘ 0435:0050 { E 74D D D m L: In El 000070 0500] g g :I 8 5% :I ,‘s SIDE VIEw "’ m D m a D g I7 0 s: L mums NDTE 1‘ MAX PACKAGE VARPAGE Is ms MM 2 MAX ALLDWABLE BURR [S 00mm 2‘ PIN N Is EIN T0R WILL BE LASER ‘ REn cIRcLE IN LAND RNTTERN RERREsENT THERMAL VIA CDNNEETED TEI 6ND FDR MAX THERMAL 5 GREEN RECTANELES (SHARED AREA) RERREsENT SEILDER STENCIL EIFENINE EIN EXFDSED m: AREA NM, 020 NM SPACJNG IN ALL nIREchNs MARKED FEEFDRHANCE zsn as: R REcuNNENnEn mNETER IS nan 7 ms MN AND SHEIULD BE SIZE SHEIULD EE 050x050
SM802XXX
DS20006176A-page 20 2019 Microchip Technology Inc.
16-Lead QFN Package Outline and Recommended Land Pattern
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging.
2019 Microchip Technology Inc. DS20006176A-page 21
SM802XXX
APPENDIX A: REVISION HISTORY
Revision A (March 2019)
Converted Micrel document SM802xxx to Micro-
chip data sheet DS20006176A.
Minor text changes throughout.
Updated the Crystal and Reference Input fre-
quency ranges in the Features section and in
Crystal Characteristics table.
Updated ESR value in Crystal Characteristics
table.
Updated the 12 kHz to 20 MHz Phase Jitter to
265 fs in the Features and in LVPECL AC Electri-
cal Characteristics (Note 1, Note 2, Note 3,
Note 4).
Updated Output Frequency minimum and typical
Phase Jitter in LVDS AC Electrical Characteristics
(Note 1, Note 2, Note 3, Note 4), HCSL AC Elec-
trical Characteristics (Note 1, Note 2, Note 3,
Note 4), and LVCMOS AC Electrical Characteris-
tics (Note 1, Note 2, Note 3, Note 4).
Corrected the impedance values for using a ferrite
bead in Power Supply Decoupling section.
SM802XXX
DS20006176A-page 22 2019 Microchip Technology Inc.
NOTES:
PART NO. x v
2019 Microchip Technology Inc. DS20006176A-page 23
SM802XXX
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.
PART NO. X X
TemperaturePackage
Device
Device: SM802xxx: Flexible Ultra-Low Jitter Clock Synthesizer
Voltage Option: U = 2.5V/3.3V
Package Type: M = 44-, 32-, 24-, or 16-QFN; see the Package
Options Table (Note 1).
Temperature: G = –40°C to +85°C (NiPdAu Lead Free)
Special
Processing:
Blank = Tray
TR = Tape and Reel
X
Voltage
Option Type
X
Special
Processing
-
Examples:
a) SM802xxxUMG: Flexible Ultra-Low Jitter Clock
Synthesizer, 2.5V/3.3V Voltage
Option, QFN Package, –40°C to
+85°C Temperature Range, Tray
b) SM802xxxUMG-TR: Flexible Ultra-Low Jitter Clock
Synthesizer, 2.5V/3.3V Voltage
Option, QFN Package, –40°C to
+85°C Temperature Range, Tape &
Reel
Package Options Table (Note 1)
Package
Option
QFN
Package
# of
Outputs XTAL REF_IN XTAL_SEL FSEL OE1
OE2
PLL
BYPASS
#1 44-Pin 7x7 8 Diff. Yes Yes Yes Yes Yes Yes
#2 32-Pin 5x5 4 Diff. Yes Yes Yes Yes Yes Yes
#3 24-Pin 4x4 4 Diff. Yes Yes Yes No No Yes
#4 24-Pin 4x4 2 Diff. Yes Yes Yes Yes Yes Yes
#5 16-Pin 3x3.5 2 Diff. No Yes No Yes No No
#6 16-Pin 3x3.5 2 Diff. Yes No No No No No
Note 1: Use the web tool at http://clockworks.microchip.com/micrel/ to determine the desired configuration.
SM802XXX
DS20006176A-page 24 2019 Microchip Technology Inc.
NOTES:
YSTEM
2019 Microchip Technology Inc. DS20006176A-page 25
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
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OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
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intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo,
CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo,
JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus,
maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo,
SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
ClockWorks, The Embedded Control Solutions Company,
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trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity,
JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation,
PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon,
QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O,
SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
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SQTP is a service mark of Microchip Technology Incorporated in
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Silicon Storage Technology is a registered trademark of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
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Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2019, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-4300-1
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
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QUALITYMANAGEMENTS
YSTEM
CERTIFIEDBYDNV
== ISO/TS16949==
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DS20006176A-page 26 2019 Microchip Technology Inc.
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