SY54016R Datasheet by Microchip Technology

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SY54016R

Low Voltage 1.2V/1.8V CML Differential Line

Driver/Receiver with Fail Safe Input

3.2Gbps, 2.5GHz

Precision Edge is a registered trademark of Micrel, Inc.

MLF and MicroLeadFrame are registered trademarks of Amkor Technology.

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com

General Description

The SY54016R is a fully differential, low voltage

1.2V/1.8V CML Line Driver/Receiver with Fail-Safe

Input. The SY54016R can process clock signals as fast

as 2.5GHz or data patterns up to 3.2Gbps.

The differential input includes Micrel’s unique, 3-pin

input termination architecture that interfaces to LVPECL,

LVDS or CML differential signals, as small as 100mV

(200mVPP) without any level-shifting or termination

resistor networks in the signal path. For AC-coupled

input interface applications, an internal voltage

reference is provided to bias the VT pin. The outputs are

CML, with extremely fast rise/fall times guaranteed to be

less than 95ps.

The SY54016R operates from a 2.5V ±5% core supply

and a 1.8V or 1.2V ±5% output supply and is

guaranteed over the full industrial temperature range

(–40°C to +85°C). The SY54016R is part of Micrel’s

high-speed, Precision Edge® product line.

Data sheets and support documentation can be found

on Micrel’s web site at: www.micrel.com.

Functional Block Diagram

Precision Edge®

Features

•1.2V/1.8V CML Line Driver/Receiver with Fail-Safe

Input

•Guaranteed AC performance over temperature and

voltage:

– DC-to- > 3.2Gbps throughput

– <370ps propagation delay (IN-to-Q)

– <95ps rise/fall times

•Ultra-low jitter design

– <1psRMS random jitter

•High-speed CML outputs

•2.5V ±5% , 1.8/1.2V ±5% power supply operation

•Industrial temperature range: –40°C to +85°C

•Available in 8-pin (2mm x 2mm) MLF® package

Applications

•Data Distribution: OC-48, OC-48+FEC

•SONET clock and data distribution

•Fibre Channel clock and data distribution

•Gigabit Ethernet clock and data distribution

Markets

•Storage

•ATE

•Test and measurement

•Enterprise networking equipment

•High-end servers

•Metro area network equipment

June 2010 M9999-061110-A

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Ordering Information(1)

Part Number Package

Type Operating

Range Package Marking Lead

Finish

SY54016RMGTR(2) MLF-8 Industrial 016R with

Pb-Free bar-line indicator

NiPdAu

Pb-Free

Notes:

1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.

2. Tape and Reel.

Pin Configuration

8-Pin MLF® (MLF-8)

Pin Description

Pin Number Pin Name Pin Function

2,3

IN, /IN

Differential Input: This input pair is the differential signal input to the device. Input

accepts differential signals as small as 100mV (200mVPP). Each input pin internally

terminates with 50Ω to the VT pin. If the input swing falls below a certain threshold

(typical 30mV), the Fail Safe Input (FSI) feature will guarantee a stable output by

latching the output to its last valid state.

Input Termination Center-Tap: Each side of the differential input pair terminates to

VT pin. This pin provides a center-tap to a termination network for maximum

interface flexibility. An internal high impedance resistor divider biases VT to allow

input AC coupling. For AC-coupling, bypass VT with 0.1µF low ESR capacitor to

VCC. See “Interface Applications” subsection and Figure 2a.

8 VCC

Positive Power Supply: Bypass with 0.1uF//0.01uF low ESR capacitors as close to

the VCC pin as possible. Supplies input and core circuitry.

5 VCCO

Output Supply: Bypass with 0.1uF//0.01uF low ESR capacitors as close to the VCCO

pin as possible. Supplies the output buffer.

4 GND,

Exposed pad

Ground: Exposed pad must be connected to a ground plane that is the same

potential as the ground pin.

7,6

Q, /Q

CML Differential Output Pair: Differential buffered copy of the input signal. The

output swing is typically 390mV. See “Interface Applications” subsection for

termination information.

or (408) 955-1690

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Absolute Maximum Ratings(1)

Supply Voltage (VCC)............................... –0.5V to +3.0V

Supply Voltage (VCCO) ............................. –0.5V to +2.7V

VCC - VCCO ...............................................................<1.8V

VCCO - VCC ...............................................................<0.5V

Input Voltage (VIN) .......................................–0.5V to VCC

CML Output Voltage (VOUT)............... 0.6V to VCCO+0.5V

Current (VT)

Source or sink current on VT pin .................±100mA

Input Current

Source or sink current on (IN, /IN) .................±50mA

Maximum operating Junction Temperature .......... 125°C

Lead Temperature (soldering, 20sec.) .................. 260°C

Storage Temperature (Ts) ....................–65°C to +150°C

Operating Ratings(2)

Supply Voltage (VCC)..........................2.375V to 2.625V

(VCCO)………………... .....1.14V to 1.9V

Ambient Temperature (TA) ................... –40°C to +85°C

Package Thermal Resistance(3)

MLF®

Still-air (JA) ........................................... 93°C/W

Junction-to-board (JB).......................... 56°C/W

DC Electrical Characteristics(4)

TA = –40°C to +85°C, unless otherwise stated.

Symbol Parameter Condition Min Typ Max Units

VCC Power Supply Voltage Range VCC

VCCO

2.375

1.14

1.7

2.5

1.2

1.8

2.625

1.26

1.9

ICC Power Supply Current Max. VCC 13 19 mA

ICCO Power Supply Current No Load. Max. VCCO 16 21 mA

RIN Input Resistance

(IN-to-VT, /IN-to-VT )

45 50 55 Ω

RDIFF_IN Differential Input Resistance

(IN-to-/IN)

90 100 110 Ω

VIH

VIL

Input HIGH Voltage

(IN, /IN)

Input LOW Voltage

(IN, /IN)

IN, /IN

VIL with VIH = 1.2V

1.2

0.2

VIH–0.1

VIH

VIL

Input HIGH Voltage

(IN, /IN)

Input LOW Voltage

(IN, /IN)

IN, /IN

VIL with VIH = 1.14V, (1.2V-5%)

1.14

0.66

VIH–0.1

VIN Input Voltage Swing

(IN, /IN)

see Figure 3a 0.1 1.0 V

VDIFF_IN Differential Input Voltage Swing

(|IN - /IN|)

see Figure 3b 0.2 2.0 V

VIN_FSI Input Voltage Threshold that

Triggers FSI

30 100 mV

VT_IN Voltage from Input to VT 1.28 V

Notes:

1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not

implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions

for extended periods may affect device reliability.

2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.

3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. ψJB and θJA

values are determined for a 4-layer board in still-air number, unless otherwise stated.

4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.

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CML Outputs DC Electrical Characteristics(5)

VCCO = 1.14V to 1.26V RL = 50Ω to VCCO,

VCCO = 1.7V to 1.9V, RL = 50Ω to VCCO or 100Ω across the outputs,

VCC = 2.375V to 2.625V. TA = –40°C to +85°C, unless otherwise stated.

Symbol Parameter Condition Min Typ Max Units

VOH Output HIGH Voltage RL = 50Ω to VCCO V

CCO-0.020 VCCO-0.010 VCCO V

VOUT Output Voltage Swing See Figure 3a 300 390 475 mV

VDIFF_OUT Differential Output Voltage Swing See Figure 3b 600 780 950 mV

ROUT Output Source Impedance 45 50 55 Ω

Note:

5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.

AC Electrical Characteristics

VCCO = 1.14V to 1.26V RL = 50Ω to VCCO,

VCCO = 1.7V to 1.9V, RL = 50Ω to VCCO or 100Ω across the outputs,

VCC = 2.375V to 2.625V. TA = –40°C to +85°C, unless otherwise stated.

Symbol Parameter Condition Min Typ Max Units

NRZ Data 3.2 Gbps fMAX Maximum Frequency

VOUT > 200mV Clock 2.5 GHz

VIN: 100mV-200mV, Note 6,

Figure 1a

180 300 420 ps

tPD Propagation Delay IN-to-Q

VIN: >200mV, Note 6, Figure 1a 170 250 370 ps

tSkew Part-to-Part Skew Note 7 75 ps

tJitter Random Jitter 1 psRMS

tR tF Output Rise/Fall Times

(20% to 80%)

At full output swing. 30 60 95 ps

Duty Cycle Differential I/O 47 53 %

Notes:

6. Propagation delay is measured with input tr/tf ≤300ps (20% to 80%).

7. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the

respective inputs. VIN >200mV with input tr/tf ≤300ps (20% to 80%).

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Functional Description

Fail-Safe Input (FSI)

The input includes a special failsafe circuit to sense

the amplitude of the input signal and to latch the

output when there is no input signal present, or when

the amplitude of the input signal drops sufficiently

below 100mVPK (200mVPP), typically 30mVPK.

Maximum frequency of the SY54016R is limited by the

FSI function.

Input Clock Failure Case

If the input clock fails to a floating, static, or extremely

low signal swing, the FSI function will eliminate a

metastable condition and guarantee a stable output.

No ringing and no undetermined state will occur at the

output under these conditions.

Note that the FSI function will not prevent duty cycle

distortion in case of a slowly deteriorating (but still

toggling) input signal close to the FSI threshold. Due

to the FSI function, the propagation delay will depend

on rise and fall time of the input signal and on its

amplitude. Refer to “Typical Characteristics” for

detailed information

Interface Applications

For Input Interface Applications see Figures 4a-f and

for CML Output Termination see Figures 5a-d.

CML Output Termination with VCCO 1.2V

For VCCO of 1.2V, Figure 5a, terminate the output

with 50Ω-to-1.2V, DC-coupled, not 100Ω differentially

across the outputs.

If AC-coupling is used, Figure 5d, terminate into 50Ω-

to-1.2V before the coupling capacitor and then

connect to a high value resistor to a reference voltage.

Do not AC couple with internally terminated receiver.

For example, 50Ω ANY-IN input. AC-coupling will

offset the output voltage by 200mV and this offset

voltage will be too low for proper driver operation.

CML Output Termination with VCCO 1.8V

For VCCO of 1.8V, Figure 5a and Figure b, terminate

with either 50Ω to 1.8V or 100Ω differentially across

the outputs. AC- or DC-coupling is fine.

Input AC-Coupling

The SY54016R input can accept AC-coupling from

any driver. Tie VT to VCC with a capacitor as shown

in Figures 4c and 4d. VT has an internal high

impedance resistor divider as shown in Figure 2a, to

provide a bias voltage for AC-coupling.

/|N IQ VOU! / Decaying input slgnal _l—|_ /Q \\ FSI aclwated once input amplitude goes swgmﬁcantly below 100mV(typIcaHy somV)

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Timing Diagrams

Figure 1a. Propagation Delay

Figure 1b. Fail-Safe Feature

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Amp ude (mv) Amplitude vs. Frequency 450 400 350 300 250 200 1 50 l 00 50 Do MO 1000 1500 2000 200 300 3500 4000 4500 Frequency (MHz) Propagation Delay vs. Input Rise/Fall Time 400 375 350 325 300 275 250 225 200 05) Propaaallorl Delay ( 0 200 400 600 80010001200 lrlpul Rlse/Fall Tune (psi Propagatlon Delay (vs) Pmpagatlnn Delay (05) 255 260 255 250 245 240 235 230 ﬁ’ 350 325 300 275 250 225 200 175 0 Propagation Delay vs Temperature v‘ = zonmv ﬁancee o, mama: IOU 120 Tempeature we) Propagation Delay vs. Input Rise/Fall Time V“ = mornv mo eon sno eon 10001200 Inpul Else/Fall Time (psl Propagation Delay vs. lllpul Rise/Fall Time 600 550 500 450 400 350 300 250 200 150 Propagallon Delay (05) o o o o c o c: u

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Typical Characteristics

VCC = 2.5V, GND = 0V, RL = 50Ω to 1.2V, VIN = 100mV, TA = 25°C, unless otherwise stated.

or (408) 955-1690

Output Swing (1OUmV/div.) Output Swing (1OUmV/div.) Output Swing (1 GOmV/div.) 1.256bps Data TIME (200ps/dIv.) 2.56bps Data TIME (1 DOps/dIv.) 3.26bps Data TIME (aops/div.) 1.25Gbps Data Output Swing (1 UOmV/div.) Output Swing (1OUmV/div.) Output Swing (1 GOmV/div.) TIME (ZOOpS/div.) 2.56bps Data TIME (1 DOps/dIv.) 3.26bps Data TIME (aops/div.) hbwhelg@micrel.com

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Functional Characteristics

VCC = 2.5V, GND = 0V, VIN = 400mV, RL = 50Ω to VCCO, Data Pattern: 223-1, TA = 25°C, unless otherwise stated.

Output Eyes with VCCO = 1.2V Output Eyes with VCCO = 1.8V

or (408) 955-1690

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Functional Characteristics

VCC = 2.5V, GND = 0V, VIN = 400mV, RL = 50Ω to VCCO, TA = 25°C, unless otherwise stated.

or (408) 955-1690

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Input and Output Stage

Figure 2b. Simplified CML Output Buffer

Figure 2a. Simplified Differential Input Buffer

Single-Ended and Differential Swings

Figure 3a. Single-Ended Swing

Figure 3b. Differential Swing

or (408) 955-1690

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Input Interface Applications

Figure 4a. CML Interface

(DC-Coupled, 1.8V, 2.5V)

Figure 4b. CML Interface

(DC-Coupled, 1.2V)

Figure 4c. CML Interface

(AC-Coupled)

Figure 4d. LVPECL Interface

(AC-Coupled)

Figure 4e. LVPECL Interface

(DC-Coupled)

Figure 4f. LVDS Interface

or (408) 955-1690

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CML Output Termination

Figure 5a. 1.2 or 1.8V CML DC-Coupled Termination

Figure 5b. 1.8V CML DC-Coupled Termination

Figure 5c. CML AC-Coupled Termination

(VCCO 1.8V Only)

Figure 5d. CML AC-Coupled Termination

(VCCO 1.2V Only)