STM32H753xI Datasheet by STMicroelectronics

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This is information on a product in full production.
April 2019 DS12117 Rev 7 1/356
STM32H753xI
32-bit Arm
®
Cortex
®
-M7 480MHz MCUs, 2MB Flash,
1MB RAM, 46 com. and analog interfaces, crypto
Datasheet - production data
Features
Core
32-bit Arm® Cortex®-M7 core with double-
precision FPU and L1 cache: 16 Kbytes of data
and 16 Kbytes of instruction cache; frequency
up to 480 MHz, MPU, 1027 DMIPS/
2.14 DMIPS/MHz (Dhrystone 2.1), and DSP
instructions
Memories
2 Mbytes of Flash memory with read-while-
write support
1 Mbyte of RAM: 192 Kbytes of TCM RAM (inc.
64 Kbytes of ITCM RAM + 128 Kbytes of
DTCM RAM for time critical routines),
864 Kbytes of user SRAM, and 4 Kbytes of
SRAM in Backup domain
Dual mode Quad-SPI memory interface
running up to 133 MHz
Flexible external memory controller with up to
32-bit data bus: SRAM, PSRAM,
SDRAM/LPSDR SDRAM, NOR/NAND Flash
memory clocked up to 100 MHz in
Synchronous mode
CRC calculation unit
Security
ROP, PC-ROP, active tamper, secure firmware
upgrade support, Secure access mode
General-purpose input/outputs
Up to 168 I/O ports with interrupt capability
Reset and power management
3 separate power domains which can be
independently clock-gated or switched off:
D1: high-performance capabilities
D2: communication peripherals and timers
D3: reset/clock control/power management
1.62 to 3.6 V application supply and I/Os
POR, PDR, PVD and BOR
Dedicated USB power embedding a 3.3 V
internal regulator to supply the internal PHYs
Embedded regulator (LDO) with configurable
scalable output to supply the digital circuitry
Voltage scaling in Run and Stop mode (6
configurable ranges)
Backup regulator (~0.9 V)
Voltage reference for analog peripheral/VREF+
Low-power modes: Sleep, Stop, Standby and
VBAT supporting battery charging
Low-power consumption
VBAT battery operating mode with charging
capability
CPU and domain power state monitoring pins
2.95 µA in Standby mode (Backup SRAM OFF,
RTC/LSE ON)
Clock management
Internal oscillators: 64 MHz HSI, 48 MHz
HSI48, 4 MHz CSI, 32 kHz LSI
External oscillators: 4-48 MHz HSE,
32.768 kHz LSE
3× PLLs (1 for the system clock, 2 for kernel
clocks) with Fractional mode
FBGA
LQFP100
(14 x 14 mm)
LQFP144
(20 x 20 mm)
LQFP176
(24 x 24 mm)
LQFP208
(28 x 28 mm)
UFBGA169
(7 x 7 mm)
UFBGA176+25
(10 x 10 mm)
FBGA
TFBGA100
(8 x 8 mm)(1)
TFBGA240+25
(14 x 14 mm)
www.st.com
STM32H753xI
2/356 DS12117 Rev 7
Interconnect matrix
3 bus matrices (1 AXI and 2 AHB)
Bridges (5× AHB2-APB, 2× AXI2-AHB)
4 DMA controllers to unload the CPU
1× high-speed master direct memory access
controller (MDMA) with linked list support
2× dual-port DMAs with FIFO
1× basic DMA with request router capabilities
Up to 35 communication peripherals
4× I2Cs FM+ interfaces (SMBus/PMBus)
4× USARTs/4x UARTs (ISO7816 interface,
LIN, IrDA, up to 12.5 Mbit/s) and 1x LPUART
6× SPIs, 3 with muxed duplex I2S audio class
accuracy via internal audio PLL or external
clock, 1x I2S in LP domain (up to 150 MHz)
4x SAIs (serial audio interface)
SPDIFRX interface
SWPMI single-wire protocol master I/F
MDIO Slave interface
2× SD/SDIO/MMC interfaces (up to 125 MHz)
2× CAN controllers: 2 with CAN FD, 1 with
time-triggered CAN (TT-CAN)
2× USB OTG interfaces (1FS, 1HS/FS) crystal-
less solution with LPM and BCD
Ethernet MAC interface with DMA controller
HDMI-CEC
8- to 14-bit camera interface (up to 80 MHz)
11 analog peripherals
3× ADCs with 16-bit max. resolution (up to 36
channels, up to 3.6 MSPS)
1× temperature sensor
2× 12-bit D/A converters (1 MHz)
2× ultra-low-power comparators
2× operational amplifiers (7.3 MHz bandwidth)
1× digital filters for sigma delta modulator
(DFSDM) with 8 channels/4 filters
Graphics
LCD-TFT controller up to XGA resolution
Chrom-ART graphical hardware Accelerator™
(DMA2D) to reduce CPU load
Hardware JPEG Codec
Up to 22 timers and watchdogs
1× high-resolution timer (2.1 ns max
resolution)
2× 32-bit timers with up to 4 IC/OC/PWM or
pulse counter and quadrature (incremental)
encoder input (up to 240 MHz)
2× 16-bit advanced motor control timers (up to
240 MHz)
10× 16-bit general-purpose timers (up to
240 MHz)
5× 16-bit low-power timers (up to 240 MHz)
2× watchdogs (independent and window)
1× SysTick timer
RTC with sub-second accuracy and hardware
calendar
Cryptographic acceleration
AES 128, 192, 256, TDES,
HASH (MD5, SHA-1, SHA-2), HMAC
True random number generators
Debug mode
SWD & JTAG interfaces
4-Kbyte Embedded Trace Buffer
96-bit unique ID
All packages are ECOPACK®2 compliant
Table 1. Device summary
Reference Part number
STM32H753xI
STM32H753VI, STM32H753ZI,
STM32H753II, STM32H753BI,
STM32H753XI, STM32H753AI
DS12117 Rev 7 3/356
STM32H753xI Contents
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Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.1 Arm® Cortex®-M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2 Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3.1 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3.2 Secure access mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3.3 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.4 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.5 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.5.1 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.5.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.5.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.6 Low-power strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.7 Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.7.1 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.7.2 System reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.8 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.9 Bus-interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.10 DMA controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.11 Chrom-ART Accelerator™ (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.12 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 33
3.13 Extended interrupt and event controller (EXTI) . . . . . . . . . . . . . . . . . . . . 33
3.14 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 33
3.15 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.16 Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.17 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.18 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.19 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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3.20 Digital-to-analog converters (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.21 Ultra-low-power comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.22 Operational amplifiers (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.23 Digital filter for sigma-delta modulators (DFSDM) . . . . . . . . . . . . . . . . . . 37
3.24 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.25 LCD-TFT controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.26 JPEG Codec (JPEG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.27 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.28 Cryptographic acceleration (CRYP and HASH) . . . . . . . . . . . . . . . . . . . . 40
3.29 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.29.1 High-resolution timer (HRTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.29.2 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.29.3 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.29.4 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.29.5 Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5) . . . . 44
3.29.6 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.29.7 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.29.8 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.30 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 45
3.31 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.32 Universal synchronous/asynchronous receiver transmitter (USART) . . . 46
3.33 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 47
3.34 Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) . 48
3.35 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.36 SPDIFRX Receiver Interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.37 Single wire protocol master interface (SWPMI) . . . . . . . . . . . . . . . . . . . . 49
3.38 Management Data Input/Output (MDIO) slaves . . . . . . . . . . . . . . . . . . . . 50
3.39 SD/SDIO/MMC card host interfaces (SDMMC) . . . . . . . . . . . . . . . . . . . . 50
3.40 Controller area network (FDCAN1, FDCAN2) . . . . . . . . . . . . . . . . . . . . . 50
3.41 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 51
3.42 Ethernet MAC interface with dedicated DMA controller (ETH) . . . . . . . . . 51
3.43 High-definition multimedia interface (HDMI)
- consumer electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.44 Debug infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
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STM32H753xI Contents
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4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6 Electrical characteristics (rev Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.3.2 VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.3.3 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 108
6.3.4 Embedded reset and power control block characteristics . . . . . . . . . . 109
6.3.5 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
6.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.3.7 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 124
6.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 125
6.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 129
6.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
6.3.11 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
6.3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
6.3.13 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 136
6.3.14 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
6.3.15 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
6.3.16 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
6.3.17 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
6.3.18 Quad-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
6.3.19 Delay block (DLYB) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
6.3.20 16-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
6.3.21 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
6.3.22 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 177
Contents STM32H753xI
6/356 DS12117 Rev 7
6.3.23 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
6.3.24 Temperature and VBAT monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
6.3.25 Voltage booster for analog switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
6.3.26 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
6.3.27 Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 182
6.3.28 Digital filter for Sigma-Delta Modulators (DFSDM) characteristics . . . 185
6.3.29 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 188
6.3.30 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 189
6.3.31 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
6.3.32 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
6.3.33 JTAG/SWD interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 206
7 Electrical characteristics (rev V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
7.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
7.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
7.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
7.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
7.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
7.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
7.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
7.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 211
7.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
7.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
7.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
7.3.2 VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
7.3.3 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 216
7.3.4 Embedded reset and power control block characteristics . . . . . . . . . . 217
7.3.5 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
7.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
7.3.7 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 231
7.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 232
7.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 236
7.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
7.3.11 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
7.3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
7.3.13 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 244
7.3.14 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
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7.3.15 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
7.3.16 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
7.3.17 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
7.3.18 Quad-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
7.3.19 Delay block (DLYB) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
7.3.20 16-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
7.3.21 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
7.3.22 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . 290
7.3.23 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
7.3.24 Temperature and VBAT monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
7.3.25 Voltage booster for analog switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
7.3.26 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
7.3.27 Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 294
7.3.28 Digital filter for Sigma-Delta Modulators (DFSDM) characteristics . . . 296
7.3.29 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 299
7.3.30 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . 300
7.3.31 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
7.3.32 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
8 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
8.1 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
8.2 TFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
8.3 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
8.4 UFBGA169 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
8.5 LQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
8.6 LQFP208 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
8.7 UFBGA176+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
8.8 TFBGA240+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
8.9 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
8.9.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
9 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
List of tables STM32H753xI
8/356 DS12117 Rev 7
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Table 2. STM32H753xI features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 3. System vs domain low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 4. DFSDM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 5. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 6. USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 7. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 8. Pin/ball definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 9. Port A alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 10. Port B alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 11. Port C alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 12. Port D alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 13. Port E alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 14. Port F alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 15. Port G alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 16. Port H alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 17. Port I alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 18. Port J alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 19. Port K alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 20. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 21. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 22. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 23. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 24. VCAP operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 25. Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . 108
Table 26. Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 27. Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 28. Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 29. Typical and maximum current consumption in Run mode, code with data processing
running from ITCM, regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 30. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, cache ON, regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 31. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, cache OFF, regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 32. Typical consumption in Run mode and corresponding performance
versus code position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 33. Typical current consumption batch acquisition mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 34. Typical and maximum current consumption in Sleep mode, regulator ON. . . . . . . . . . . . 114
Table 35. Typical and maximum current consumption in Stop mode, regulator ON. . . . . . . . . . . . . 115
Table 36. Typical and maximum current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . 115
Table 37. Typical and maximum current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . 116
Table 38. Peripheral current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 39. Peripheral current consumption in Stop, Standby and VBAT mode . . . . . . . . . . . . . . . . . 123
Table 40. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 41. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 42. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 43. 4-48 MHz HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 44. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
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12
Table 45. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 46. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 47. CSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 48. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 49. PLL characteristics (wide VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 50. PLL characteristics (medium VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 51. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 52. Flash memory programming (single bank configuration nDBANK=1) . . . . . . . . . . . . . . . 134
Table 53. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 54. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 55. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 56. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 57. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 58. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 59. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 60. Output voltage characteristics for all I/Os except PC13, PC14, PC15 and PI8 . . . . . . . . 140
Table 61. Output voltage characteristics for PC13, PC14, PC15 and PI8 . . . . . . . . . . . . . . . . . . . . 141
Table 62. Output timing characteristics (HSLV OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 63. Output timing characteristics (HSLV ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 64. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 65. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 148
Table 66. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings . . . . . . . . . . 148
Table 67. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 149
Table 68. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings. . . . . . . . . . 150
Table 69. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 70. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 151
Table 71. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 72. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 153
Table 73. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 74. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 75. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 76. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 77. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 78. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 79. SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 80. LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 81. SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 82. LPSDR SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 83. QUADSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 84. QUADSPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 85. Dynamics characteristics: Delay Block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 86. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 87. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 88. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 89. DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 90. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Table 91. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Table 92. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Table 93. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Table 94. VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Table 95. Temperature monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Table 96. Voltage booster for analog switch characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
List of tables STM32H753xI
10/356 DS12117 Rev 7
Table 97. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 98. OPAMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 99. DFSDM measured timing 1.62-3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Table 100. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 101. LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Table 102. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Table 103. Minimum i2c_ker_ck frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Table 104. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Table 105. SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 106. I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Table 107. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Table 108. MDIO Slave timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 109. Dynamic characteristics: SD / MMC characteristics, VDD=2.7V to 3.6V . . . . . . . . . . . . . 200
Table 110. Dynamic characteristics: eMMC characteristics, VDD=1.71V to 1.9V . . . . . . . . . . . . . . . 201
Table 111. USB OTG_FS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Table 112. Dynamic characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Table 113. Dynamics characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . 204
Table 114. Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 115. Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 206
Table 116. Dynamics JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Table 117. Dynamics SWD characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Table 118. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Table 119. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 120. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 121. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Table 122. Supply voltage and maximum frequency configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 123. VCAP operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Table 124. Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . 216
Table 125. Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Table 126. Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Table 127. Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Table 128. Typical and maximum current consumption in Run mode, code with data processing
running from ITCM, LDO regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Table 129. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, cache ON,
LDO regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Table 130. Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory, cache OFF,
LDO regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Table 131. Typical and maximum current consumption batch acquisition mode,
LDO regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Table 132. Typical and maximum current consumption in Stop, LDO regulator ON . . . . . . . . . . . . . 222
Table 133. Typical and maximum current consumption in Sleep mode, LDO regulator. . . . . . . . . . . 223
Table 134. Typical and maximum current consumption in Standby . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Table 135. Typical and maximum current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . 224
Table 136. Peripheral current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Table 137. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Table 138. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Table 139. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Table 140. 4-48 MHz HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Table 141. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Table 142. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
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Table 143. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Table 144. CSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Table 145. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Table 146. PLL characteristics (wide VCO frequency range). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Table 147. PLL characteristics (medium VCO frequency range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Table 148. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Table 149. Flash memory programming (single bank configuration nDBANK=1) . . . . . . . . . . . . . . . 241
Table 150. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Table 151. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Table 152. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Table 153. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Table 154. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Table 155. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Table 156. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Table 157. Output voltage characteristics for all I/Os except PC13, PC14, PC15 and PI8 . . . . . . . . 248
Table 158. Output voltage characteristics for PC13, PC14, PC15 and PI8 . . . . . . . . . . . . . . . . . . . . 249
Table 159. Output timing characteristics (HSLV OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Table 160. Output timing characteristics (HSLV ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Table 161. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Table 162. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 255
Table 163. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 255
Table 164. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 257
Table 165. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 257
Table 166. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Table 167. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 259
Table 168. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Table 169. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 260
Table 170. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Table 171. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Table 172. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 266
Table 173. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Table 174. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Table 175. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Table 176. SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Table 177. LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Table 178. SDRAM Write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Table 179. LPSDR SDRAM Write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Table 180. QUADSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Table 181. QUADSPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Table 182. Delay Block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Table 183. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Table 184. Minimum sampling time vs RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Table 185. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Table 186. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Table 187. DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Table 188. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Table 189. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Table 190. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Table 191. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Table 192. VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Table 193. Temperature monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Table 194. Voltage booster for analog switch characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
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Table 195. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Table 196. Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Table 197. DFSDM measured timing 1.62-3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Table 198. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Table 199. LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
Table 200. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Table 201. Minimum i2c_ker_ck frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Table 202. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Table 203. USART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
Table 204. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Table 205. I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Table 206. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Table 207. MDIO Slave timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Table 208. Dynamics characteristics: SD / MMC characteristics, VDD=2.7 to 3.6 V . . . . . . . . . . . . . 314
Table 209. Dynamics characteristics: eMMC characteristics VDD=1.71V to 1.9V . . . . . . . . . . . . . . . 315
Table 210. Dynamics characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Table 211. Dynamics characteristics: Ethernet MAC signals for SMI . . . . . . . . . . . . . . . . . . . . . . . . 318
Table 212. Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 319
Table 213. Dynamics characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . 319
Table 214. Dynamics JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Table 215. Dynamics SWD characteristics: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Table 216. LQPF100 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
Table 217. TFBGA100 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Table 218. TFBGA100 recommended PCB design rules (0.8 mm pitch BGA). . . . . . . . . . . . . . . . . . 327
Table 219. LQFP144 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
Table 220. UFBGA169 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
Table 221. LQFP176 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
Table 222. LQFP208 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Table 223. UFBGA176+25 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Table 224. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . . 344
Table 225. TFBG240+25 ball package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Table 226. TFBGA240+25 recommended PCB design rules (0.8 mm pitch) . . . . . . . . . . . . . . . . . . . 348
Table 227. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
Table 228. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
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List of figures
Figure 1. STM32H753xI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 2. Power-up/power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 3. STM32H753xI bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 4. LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 5. TFBGA100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 6. LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 7. UFBGA169 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 8. LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 9. UFBGA176+25 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 10. LQFP208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 11. TFBGA240+25 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 12. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 13. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 14. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 15. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 16. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 17. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 18. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 19. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 20. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 21. VIL/VIH for all I/Os except BOOT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 22. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Figure 23. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 147
Figure 24. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 149
Figure 25. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 150
Figure 26. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 27. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 28. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 29. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 30. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 31. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 32. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 33. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 161
Figure 34. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 162
Figure 35. SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Figure 36. SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 37. Quad-SPI timing diagram - SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 38. Quad-SPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 39. ADC accuracy characteristics (12-bit resolution) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 40. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 41. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 173
Figure 42. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 173
Figure 43. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Figure 44. Channel transceiver timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 45. DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 46. LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Figure 47. LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Figure 48. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
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14/356 DS12117 Rev 7
Figure 49. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Figure 50. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Figure 51. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Figure 52. I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Figure 53. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Figure 54. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Figure 55. MDIO Slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 56. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 57. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 58. DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 59. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Figure 60. Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Figure 61. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Figure 62. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Figure 63. JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Figure 64. SWD timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Figure 65. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Figure 66. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Figure 67. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Figure 68. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Figure 69. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 70. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Figure 71. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Figure 72. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Figure 73. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Figure 74. VIL/VIH for all I/Os except BOOT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Figure 75. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Figure 76. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 254
Figure 77. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 256
Figure 78. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 258
Figure 79. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Figure 80. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Figure 81. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 265
Figure 82. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Figure 83. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Figure 84. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Figure 85. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 270
Figure 86. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 271
Figure 87. SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Figure 88. SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Figure 89. Quad-SPI timing diagram - SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Figure 90. Quad-SPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Figure 91. ADC accuracy characteristics (12-bit resolution) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Figure 92. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Figure 93. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 285
Figure 94. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 285
Figure 95. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Figure 96. Channel transceiver timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Figure 97. DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Figure 98. LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Figure 99. LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Figure 100. USART timing diagram in Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
DS12117 Rev 7 15/356
STM32H753xI List of figures
15
Figure 101. USART timing diagram in Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Figure 102. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Figure 103. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Figure 104. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
Figure 105. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Figure 106. I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Figure 107. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Figure 108. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Figure 109. MDIO Slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Figure 110. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
Figure 111. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
Figure 112. DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
Figure 113. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Figure 114. Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Figure 115. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
Figure 116. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Figure 117. JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Figure 118. SWD timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Figure 119. LQFP100 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
Figure 120. LQFP100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
Figure 121. LQFP100 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Figure 122. TFBGA100 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
Figure 123. TFBGA100 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Figure 124. TFBGA100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
Figure 125. LQFP144 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
Figure 126. LQFP144 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
Figure 127. LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Figure 128. UFBGA169 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
Figure 129. UFBGA169 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
Figure 130. LQFP176 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
Figure 131. LQFP176 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Figure 132. LQFP176 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
Figure 133. LQFP208 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
Figure 134. LQFP208 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
Figure 135. LQFP208 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
Figure 136. UFBGA176+25 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Figure 137. UFBGA176+25 package recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
Figure 138. UFBGA176+25 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Figure 139. TFBGA240+25 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Figure 140. TFBGA240+25 package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Figure 141. TFBGA240+25 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . 348
arm
Introduction STM32H753xI
16/356 DS12117 Rev 7
1 Introduction
This document provides information on STM32H53xI microcontrollers, such as description,
functional overview, pin assignment and definition, electrical characteristics, packaging, and
ordering information.
This document should be read in conjunction with the STM32H53xI reference manual
(RM0433), available from the STMicroelectronics website www.st.com.
For information on the Arm®(a) Cortex®-M7 core, please refer to the Cortex®-M7 Technical
Reference Manual, available from the http://www.arm.com website.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
DS12117 Rev 7 17/356
STM32H753xI Description
53
2 Description
STM32H753xI devices are based on the high-performance Arm® Cortex®-M7 32-bit RISC
core operating at up to 480 MHz. The Cortex® -M7 core features a floating point unit (FPU)
which supports Arm® double-precision (IEEE 754 compliant) and single-precision data-
processing instructions and data types. STM32H753xI devices support a full set of DSP
instructions and a memory protection unit (MPU) to enhance application security.
STM32H753xI devices incorporate high-speed embedded memories with a dual-bank Flash
memory of 2 Mbytes, up to 1 Mbyte of RAM (including 192 Kbytes of TCM RAM, up to
864 Kbytes of user SRAM and 4 Kbytes of backup SRAM), as well as an extensive range of
enhanced I/Os and peripherals connected to APB buses, AHB buses, 2x32-bit multi-AHB
bus matrix and a multi layer AXI interconnect supporting internal and external memory
access.
All the devices offer three ADCs, two DACs, two ultra-low power comparators, a low-power
RTC, a high-resolution timer, 12 general-purpose 16-bit timers, two PWM timers for motor
control, five low-power timers, a true random number generator (RNG), and a cryptographic
acceleration cell. The devices support four digital filters for external sigma-delta modulators
(DFSDM). They also feature standard and advanced communication interfaces.
Standard peripherals
–Four I
2Cs
Four USARTs, four UARTs and one LPUART
Six SPIs, three I2Ss in Half-duplex mode. To achieve audio class accuracy, the I2S
peripherals can be clocked by a dedicated internal audio PLL or by an external
clock to allow synchronization.
Four SAI serial audio interfaces
One SPDIFRX interface
One SWPMI (Single Wire Protocol Master Interface)
Management Data Input/Output (MDIO) slaves
Two SDMMC interfaces
A USB OTG full-speed and a USB OTG high-speed interface with full-speed
capability (with the ULPI)
One FDCAN plus one TT-FDCAN interface
An Ethernet interface
Chrom-ART Accelerator
– HDMI-CEC
Advanced peripherals including
A flexible memory control (FMC) interface
A Quad-SPI Flash memory interface
A camera interface for CMOS sensors
An LCD-TFT display controller
A JPEG hardware compressor/decompressor
Refer to Table 2: STM32H753xI features and peripheral counts for the list of peripherals
available on each part number.
Description STM32H753xI
18/356 DS12117 Rev 7
STM32H753xI devices operate in the –40 to +85 °C temperature range from a 1.62 to 3.6 V
power supply. The supply voltage can drop down to 1.62 V by using an external power
supervisor (see Section 3.5.2: Power supply supervisor) and connecting the PDR_ON pin to
VSS. Otherwise the supply voltage must stay above 1.71 V with the embedded power
voltage detector enabled.
Dedicated supply inputs for USB (OTG_FS and OTG_HS) are available on all packages
except LQFP100 to allow a greater power supply choice.
A comprehensive set of power-saving modes allows the design of low-power applications.
STM32H753xI devices are offered in 8 packages ranging from 100 pins to 240 pins/balls.
The set of included peripherals changes with the device chosen.
These features make STM32H753xI microcontrollers suitable for a wide range of
applications:
Motor drive and application control
Medical equipment
Industrial applications: PLC, inverters, circuit breakers
Printers, and scanners
Alarm systems, video intercom, and HVAC
Home audio appliances
Mobile applications, Internet of Things
Wearable devices: smart watches.
Figure 1 shows the device block diagram.
DS12117 Rev 7 19/356
STM32H753xI Description
53
Table 2. STM32H753xI features and peripheral counts
Peripherals STM32H753
VI
STM32H753
ZI
STM32H753
AI
STM32H753
II
STM32H753
BI
STM32H753
XI
Flash memory in Kbytes 2 x 1 Mbyte
SRAM in Kbytes
SRAM mapped
onto AXI bus 512
SRAM1 (D2
domain) 128
SRAM2 (D2
domain) 128
SRAM3 (D2
domain) 32
SRAM4 (D3
domain) 64
TCM RAM in Kbytes
ITCM RAM
(instruction) 64
DTCM RAM
(data) 128
Backup SRAM (Kbytes) 4
FMC Yes
GPIOs 82 114 131 140 168
Quad-SPI Yes
Ethernet Yes
Timers
High-resolution 1
General-
purpose 10
Advanced-
control (PWM) 2
Basic 2
Low-power 5
Random number generator Yes
Cryptographic accelerator Yes
(DMAZD)
Description STM32H753xI
20/356 DS12117 Rev 7
Communication
interfaces
SPI / I2S6/3
(1)
I2C4
USART/UART/
LPUART
4/4
/1
SAI 4
SPDIFRX 4 inputs
SWPMI Yes
MDIO Yes
SDMMC 2
FDCAN/TT-
FDCAN 1/1
USB OTG_FS Yes
USB OTG_HS Yes
Ethernet and camera interface Yes
LCD-TFT Yes
JPEG Codec Yes
Chrom-ART Accelerator™ (DMA2D) Yes
16-bit ADCs
Number of channels
3
Up to 36
12-bit DAC
Number of channels
Yes
2
Comparators 2
Operational amplifiers 2
DFSDM Yes
Maximum CPU frequency 480MHz(2)(3)/400 MHz
Operating voltage 1.71 to
3.6 V(4) 1.62 to 3.6 V(5)
Operating temperatures
Ambient temperatures: –40 up to +85 °C(6)
Junction temperature: –40 to + 125 °C
Package LQFP100
TFBGA100(7) LQFP144 UFBGA169
(7)
LQFP176
UFBGA176+
25
LQFP208 TFBGA240+
25
1. The SPI1, SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio
mode.
2. The maximum CPU frequency of 480 MHz can be obtained on devices revision V.
3. The product junction temperature must be kept within the –40 to +105 °C temperature range.
4. Since the LQFP100 package does not feature the PDR_ON pin (tied internally to VDD), the minimum VDD value for this
package is 1.71 V.
Table 2. STM32H753xI features and peripheral counts (continued)
Peripherals STM32H753
VI
STM32H753
ZI
STM32H753
AI
STM32H753
II
STM32H753
BI
STM32H753
XI
DS12117 Rev 7 21/356
STM32H753xI Description
53
5. VDD/VDDA can drop down to 1.62 V by using an external power supervisor (see Section 3.5.2: Power supply supervisor) and
connecting PDR_ON pin to VSS. Otherwise the supply voltage must stay above 1.71 V with the embedded power voltage
detector enabled.
6. The product junction temperature must be kept within the –40 to +125 °C temperature range.
7. This package is under development. Please contact STMicroelectronics for details.
mg? ‘ Mm] sn Sex Is mm Dam-M] 9‘ 5”“ ‘5 “Liiiu‘flfl 2W mmmgcmn TIM m.“ mums“ 2‘ mm :m m Lrvmrcmn um mm "mm m mm mm mm, :nervALcmn w, m." my mu m M; M ms m w m um) um um; 5m 5m sumnu J 5mm nemmm _ Dcm mum mum Sm 5sz sm 5% mm II II” \%_1 nmn mm 5m swzs‘ m sws m usARn mwm m waerM V, we: we pom J Emu pom _ 5m commz mm Lan mm mm UH swarms: quRn mm mm mmmzmmm _ mamsn - ma ; g [mmm g g g g [cmcswn‘ mmmm I mam mswmx \zcstaus m m 5mm um - m m swim-m: \zciarsmaus RCC at“. 5 mm was; svscrs mm mm? ++++ L @VDD awn upm swim/Isuzu if: i |:| W¢ |:|
Description STM32H753xI
22/356 DS12117 Rev 7
Figure 1. STM32H753xI block diagram
MSv40887V15
TT-FDCAN1
FDCAN2
I2C1/SMBUS
I2C2/SMBUS
I2C3/SMBUS
AXI/AHB12 (200MHz)
4 compl. chan. (TIM1_CH1[1:4]N),
4 chan. (TIM1_CH1[1:4]ETR, BKIN as AF
APB1 30MHz
TX, RX
SCL, SDA, SMBAL as AF
APB1 100 MHz (max)
MDMA
PK[7:0]
4 compl. chan.(TIM8_CH1[1:4]N),
4 chan. (TIM8_CH1[1:4], ETR, BKIN as
AF
RX, TX, SCK, CTS, RTS as AF
SCL, SDA, SMBAL as AF
SCL, SDA, SMBAL as AF
MOSI, MISO, SCK, NSS /
SDO, SDI, CK, WS, MCK, as AF
TX, RX
RX, TX as AF
RX, TX as AF
RX, TX, SCK
CTS, RTS as AF
RX, TX, SCK, CTS,
RTS as AF
1 channel as AF
smcard
irDA
1 channel as AF
2 channels as AF
4 channels
4 channels, ETR as AF
4 channels, ETR as AF
4 channels, ETR as AF
RX, TX as AF
FIFO
LCD-TFT
FIFO
CHROM-ART
(DMA2D)
SD, SCK, FS, MCLK, D/CK[4:1] as
AF
FIFO
LCD_R[7:0], LCD_G[7:0],
LCD_B[7:0], LCD_HSYNC,
LCD_VSYNC, LCD_DE, LCD_CLK
CLK, CS,D[7:0]
64-bit AXI BUS-MATRIX
CEC as AF
IN[1:4] as AF
MDC, MDIO
AXIM
AXIM
Arm CPU
Cortex-M7
400 MHz
AHBP
AHBS
TRACECK
TRACED[3:0]
JTRST, JTDI,
JTCK/SWCLK
JTDO/SWD, JTDO
JTAG/SW
ETM
I-Cache
16KB
D-Cache
16KB
I-TCM
64KB
D-TCM
64KB
16 Streams
FIFO
SDMMC1
SDMMC_D[7:0],SDMMC_D[7:3,1]Dir
SDMMC_D0dir, SDMMC_D2dir
CMD, CMDdir, CK, Ckin,
CKio as AF
FIFO
DMA1
FIFOs
8 Stream
DMA2
FIFOs
ETHER
MAC
FIFO
SDMMC2
FIFO
OTG_HS
FIFO
OTG_FS
FIFO
SRAM1
128 KB
8 Stream
FMC_signals
DMA/ DMA/ DMA/
PHY PHY
MII / RMII
MDIO
as AF
DP, DM, STP,
NXT,ULPI:CK
, D[7:0], DIR,
ID, VBUS
AHB1 (200MHz)
ADC1
DAC_OUT1, DAC_OUT2 as AF
16b
AXI/AHB34 (200MHz)
JPEGWWDG
AHB2 (200MHz)
AHB2 (200MHz)
PA..J[15:0]
HSYNC, VSYNC, PIXCLK, D[13:0]
SAI3
MOSI, MISO, SCK, NSS as AF
MOSI, MISO, SCK, NSS as AF
smcard
irDA 32-bit AHB BUS-MATRIX
AHB4 (200MHz)
BDMA
DMA
Mux2
Up to 20 analog inputs
common to ADC1 & 2
HSEM
AHB4 (200MHz)
AHB3
AHB4
AHB4
AHB4
AHB4
AHB4
VDDA, VSSA
NRESET
WKUP[5:0]
@VDD
RCC
Reset &
control
OSC32_IN
OSC32_OUT
VBAT = 1.8 to 3.6 V
AWU
VDD12 BBgen + POWER MNGT
LS LS
OSC_IN
OSC_OUT
RTC_TS
RTC_TAMP[1:3]
RTC_OUT
RTC_REFIN
VDDMMC33 = 1.8 to 3.6V
VDDUSB33 = 3.0 to 3.6 V
VDD = 1.8 to 3.6 V
VSS
VCAP
@VDD
@VDD33
@VSW
PWRCTRL
AHB4 (200MHz)
SUPPLY SUPERVISION
Int
POR
reset
@VDD
WDG_LS_D1
LPTIM1_IN1, LPTIM1_IN2,
LPTIM1_OUT as AF
OPAMPx_VINM
OPAMPx_VINP
OPAMPx_VOUT as AF
HRTIM1_CH[A..E]x
HRTIM1_FLT[5:1],
HRTIM1_FLT[5:1]_in, SYSFLT
DFSDM1_CKOUT,
DFSDM1_DATAIN[0:7],
DFSDM1_CKIN[0:7]
2 compl. chan.(TIM15_CH1[1:2]N),
2 chan. (TIM_CH15[1:2], BKIN as AF
1 compl. chan.(TIM16_CH1N),
1 chan. (TIM16_CH1, BKIN as AF
1 compl. chan.(TIM17_CH1N),
1 chan. (TIM17_CH1, BKIN as AF
SDMMC_
D[7:0],
CMD, CK as AF
Up to 17 analog inputs
common to ADC1 and 2
SD, SCK, FS, MCLK,
D[3;1], CK[2:1] as AF
SCL, SDA, SMBAL as AF
COMPx_INP, COMPx_INM,
COMPx_OUT as AF
LPTIM5_OUT as AF
D-TCM
64KB
AHB/APB
Quad-SPI
1 MB FLASH
1 MB FLASH
512 KB AXI
SRAM
FMC
Delay block
DCMI AHB/APB
HRTIM1
DFSDM1
SD, SCK, FS, MCLK, CK[2:1] as AF
FIFO
SAI2
SD, SCK, FS, MCLK, D[3:1],
CK[2:1] as AF
FIFO
SAI1
SPI5
TIM17
TIM16
TIM15
SPI4
MOSI, MISO, SCK, NSS /
SDO, SDI, CK, WS, MCK, as AF SPI1/I2S1
USART6
RX, TX, SCK, CTS, RTS as AF irDA USART1
TIM1/PWM 16b
TIM8/PWM 16b
APB2 100 MHz (max)
ADC3
GPIO PORTA.. J
GPIO PORTK
SAI4
COMP1&2
LPTIM5
LPTIM4_OUT as AF LPTIM4
LPTIM3_OUT as AF LPTIM3
I2C4
MOSI, MISO, SCK, NSS /
SDO, SDI, CK, WS, MCK, as AF SPI6/I2S6
RX, TX, CK, CTS, RTS as AF LPUART1
LPTIM2
VREF
SYSCFG
EXTI WKUP
CRC
DAP
RNG
DMA
Mux1
To APB1-2
peripherals
SRAM2
128 KB
SRAM3
32 KB
ADC2
AHB/APB
TIM6 16b
TIM7 16b
SWPMI
TIM2
32b
TIM3
16b
TIM4
16b
TIM5
32b
TIM12
16b
TIM13
16b
TIM14
16b
USART2
smcard
irDA
USART3
UART4
UART5
UART7
RX, TX as AF
UART8
SPI2/I2S2
MOSI, MISO, SCK, NSS /
SDO, SDI, CK, WS, MCK, as AF
SPI3/I2S3
Digital filter
MDIOs
FIFO
10 KB SRAM
RAM
I/F
USBCR
SPDIFRX1
HDMI-CEC
DAC
LPTIM1
OPAMP1&2
AHB/APB
XTAL 32 kHz
RTC
Backup registers
XTAL OSC
4- 48 MHz
HS RC
LS RC
PLL1+PLL2+PLL3
POR/PDR/BOR
PVD
smcard
Voltage
regulator
3.3 to 1.2V
LSI
HSI
CSI
HSI48
LPTIM2_IN1, LPTIM2_IN2 and
LPTIM2_OUT
AHB1 (200MHz)
DP, DM, ID,
VBUS
64 KB SRAM 4 KB BKP
RAM
AHB4
32-bit AHB BUS-MATRIX
APB4 100 MHz (max)
APB4 100 MHz (max)
APB4 100 MHz (max)
IWDG
Temperature
sensor
HASH
3DES/AES
DS12117 Rev 7 23/356
STM32H753xI Functional overview
53
3 Functional overview
3.1 Arm® Cortex®-M7 with FPU
The Arm® Cortex®-M7 with double-precision FPU processor is the latest generation of Arm
processors for embedded systems. It was developed to provide a low-cost platform that
meets the needs of MCU implementation, with a reduced pin count and optimized power
consumption, while delivering outstanding computational performance and low interrupt
latency.
The Cortex®-M7 processor is a highly efficient high-performance featuring:
Six-stage dual-issue pipeline
Dynamic branch prediction
Harvard architecture with L1 caches (16 Kbytes of I-cache and 16 Kbytes of D-cache)
64-bit AXI interface
64-bit ITCM interface
2x32-bit DTCM interfaces
The following memory interfaces are supported:
Separate Instruction and Data buses (Harvard Architecture) to optimize CPU latency
Tightly Coupled Memory (TCM) interface designed for fast and deterministic SRAM
accesses
AXI Bus interface to optimize Burst transfers
Dedicated low-latency AHB-Lite peripheral bus (AHBP) to connect to peripherals.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
It also supports single and double precision FPU (floating point unit) speeds up software
development by using metalanguage development tools, while avoiding saturation.
Figure 1 shows the general block diagram of the STM32H753xI family.
Note: Cortex®-M7 with FPU core is binary compatible with the Cortex®-M4 core.
3.2 Memory protection unit (MPU)
The memory protection unit (MPU) manages the CPU access rights and the attributes of the
system resources. It has to be programmed and enabled before use. Its main purposes are
to prevent an untrusted user program to accidentally corrupt data used by the OS and/or by
a privileged task, but also to protect data processes or read-protect memory regions.
The MPU defines access rules for privileged accesses and user program accesses. It
allows defining up to 16 protected regions that can in turn be divided into up to 8
independent subregions, where region address, size, and attributes can be configured. The
protection area ranges from 32 bytes to 4 Gbytes of addressable memory.
When an unauthorized access is performed, a memory management exception is
generated.
Functional overview STM32H753xI
24/356 DS12117 Rev 7
3.3 Memories
3.3.1 Embedded Flash memory
The STM32H753xI devices embed 2 Mbytes of Flash memory that can be used for storing
programs and data.
The Flash memory is organized as 266-bit Flash words memory that can be used for storing
both code and data constants. Each word consists of:
One Flash word (8 words, 32 bytes or 256 bits)
10 ECC bits.
The Flash memory is divided into two independent banks. Each bank is organized as
follows:
1 Mbyte of user Flash memory block containing eight user sectors of 128 Kbytes
(4 K Flash memory words)
128 Kbytes of System Flash memory from which the device can boot
2 Kbytes (64 Flash words) of user option bytes for user configuration
3.3.2 Secure access mode
In addition to other typical memory protection mechanism (RDP, PCROP), STM32H753xI
devices introduce the Secure access mode, a new enhanced security feature. This mode
allows developing user-defined secure services by ensuring, on the one hand code and
data protection and on the other hand code safe execution.
Two types of secure services are available:
STMicroelectronics Root Secure Services:
These services are embedded in System memory. They provide a secure solution for
firmware and third-party modules installation. These services rely on cryptographic
algorithms based on a device unique private key.
User-defined secure services:
These services are embedded in user Flash memory. Examples of user secure
services are proprietary user firmware update solution, secure Flash integrity check or
any other sensitive applications that require a high level of protection.
The secure firmware is embedded in specific user Flash memory areas configured
through option bytes.
Secure services are executed just after a reset and preempt all other applications to
guarantee protected and safe execution. Once executed, the corresponding code and data
are no more accessible.
The above secure services are available only for Cortex®-M7 core operating in Secure
access mode. The other masters cannot access the option bytes involved in Secure access
mode settings or the Flash secured areas.
DS12117 Rev 7 25/356
STM32H753xI Functional overview
53
3.3.3 Embedded SRAM
All devices feature:
512 Kbytes of AXI-SRAM mapped onto AXI bus on D1 domain.
SRAM1 mapped on D2 domain: 128 Kbytes
SRAM2 mapped on D2 domain: 128 Kbytes
SRAM3 mapped on D2 domain: 32 Kbytes
SRAM4 mapped on D3 domain: 64 Kbytes
4 Kbytes of backup SRAM
The content of this area is protected against possible unwanted write accesses,
and is retained in Standby or VBAT mode.
RAM mapped to TCM interface (ITCM and DTCM):
Both ITCM and DTCM RAMs are 0 wait state memories. either They can be accessed
either from the CPU or the MDMA (even in Sleep mode) through a specific AHB slave
of the CPU(AHBP):
64 Kbytes of ITCM-RAM (instruction RAM)
This RAM is connected to ITCM 64-bit interface designed for execution of critical
real-times routines by the CPU.
128 Kbytes of DTCM-RAM (2x 64-Kbyte DTCM-RAMs on 2x32-bit DTCM ports)
The DTCM-RAM could be used for critical real-time data, such as interrupt service
routines or stack/heap memory. Both DTCM-RAMs can be used in parallel (for
load/store operations) thanks to the Cortex®-M7 dual issue capability.
The MDMA can be used to load code or data in ITCM or DTCM RAMs.
Error code correction (ECC)
Over the product lifetime, and/or due to external events such as radiations, invalid bits in
memories may occur. They can be detected and corrected by ECC. This is an expected
behavior that has to be managed at final-application software level in order to ensure data
integrity through ECC algorithms implementation.
SRAM data are protected by ECC:
7 ECC bits are added per 32-bit word.
8 ECC bits are added per 64-bit word for AXI-SRAM and ITCM-RAM.
The ECC mechanism is based on the SECDED algorithm. It supports single-error correction
and double-error detection.
3.4 Boot modes
At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option
bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF
which includes:
All Flash address space
All RAM address space: ITCM, DTCM RAMs and SRAMs
The System memory bootloader
Functional overview STM32H753xI
26/356 DS12117 Rev 7
The boot loader is located in non-user System memory. It is used to reprogram the Flash
memory through a serial interface (USART, I2C, SPI, USB-DFU). Refer to STM32
microcontroller System memory Boot mode application note (AN2606) for details.
3.5 Power supply management
3.5.1 Power supply scheme
STM32H53xI power supply voltages are the following:
VDD = 1.62 to 3.6 V: external power supply for I/Os, provided externally through VDD
pins.
VDDLDO = 1.62 to 3.6 V: supply voltage for the internal regulator supplying VCORE
VDDA = 1.62 to 3.6 V: external analog power supplies for ADC, DAC, COMP and
OPAMP.
VDD33USB and VDD50USB:
VDD50USB can be supplied through the USB cable to generate the VDD33USB via the
USB internal regulator. This allows supporting a VDD supply different from 3.3 V.
The USB regulator can be bypassed to supply directly VDD33USB if VDD = 3.3 V.
VBAT = 1.2 to 3.6 V: power supply for the VSW domain when VDD is not present.
VCAP: VCORE supply voltage, which values depend on voltage scaling (1.0 V, 1.1 V,
1.2 V or 1.35 V). They are configured through VOS bits in PWR_D3CR register and
ODEN bit in the SYSCFG_PWRCR register. The VCORE domain is split into the
following power domains that can be independently switch off.
D1 domain containing some peripherals and the Cortex®-M7 core.
D2 domain containing a large part of the peripherals.
D3 domain containing some peripherals and the system control.
During power-up and power-down phases, the following power sequence requirements
must be respected (see Figure 2):
When VDD is below 1 V, other power supplies (VDDA, VDD33USB, VDD50USB) must
remain below VDD + 300 mV.
When VDD is above 1 V, all power supplies are independent.
During the power-down phase, VDD can temporarily become lower than other supplies only
if the energy provided to the microcontroller remains below 1 mJ. This allows external
decoupling capacitors to be discharged with different time constants during the power-down
transient phase.
,,,,,,,4, , ,,,,,,,,,,,,,,,,,,,,,,,,,
DS12117 Rev 7 27/356
STM32H753xI Functional overview
53
Figure 2. Power-up/power-down sequence
1. VDDx refers to any power supply among VDDA, VDD33USB, VDD50USB.
3.5.2 Power supply supervisor
The devices have an integrated power-on reset (POR)/ power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry:
Power-on reset (POR)
The POR supervisor monitors VDD power supply and compares it to a fixed threshold.
The devices remain in Reset mode when VDD is below this threshold,
Power-down reset (PDR)
The PDR supervisor monitors VDD power supply. A reset is generated when VDD drops
below a fixed threshold.
The PDR supervisor can be enabled/disabled through PDR_ON pin.
Brownout reset (BOR)
The BOR supervisor monitors VDD power supply. Three BOR thresholds (from 2.1 to
2.7 V) can be configured through option bytes. A reset is generated when VDD drops
below this threshold.
MSv47490V1
0.3
1
VBOR0
3.6
Operating modePower-on Power-down time
V
VDDX(1)
VDD
Invalid supply area VDDX < VDD + 300 mV VDDX independent from VDD
Functional overview STM32H753xI
28/356 DS12117 Rev 7
3.5.3 Voltage regulator
The same voltage regulator supplies the 3 power domains (D1, D2 and D3). D1 and D2 can
be independently switched off.
Voltage regulator output can be adjusted according to application needs through 6 power
supply levels:
Run mode (VOS0 to VOS3)
Scale 0: boosted performance (available only with LDO regulator)
Scale 1: high performance
Scale 2: medium performance and consumption
Scale 3: optimized performance and low-power consumption
Stop mode (SVOS3 to SVOS5)
Scale 3: peripheral with wakeup from Stop mode capabilities (UART, SPI, I2C,
LPTIM) are operational
Scale 4 and 5 where the peripheral with wakeup from Stop mode is disabled
The peripheral functionality is disabled but wakeup from Stop mode is possible
through GPIO or asynchronous interrupt.
3.6 Low-power strategy
There are several ways to reduce power consumption on STM32H753xI:
Decrease the dynamic power consumption by slowing down the system clocks even in
Run mode and by individually clock gating the peripherals that are not used.
Save power consumption when the CPU is idle, by selecting among the available low-
power mode according to the user application needs. This allows achieving the best
compromise between short startup time, low-power consumption, as well as available
wakeup sources.
The devices feature several low-power modes:
CSleep (CPU clock stopped)
CStop (CPU sub-system clock stopped)
DStop (Domain bus matrix clock stopped)
Stop (System clock stopped)
DStandby (Domain powered down)
Standby (System powered down)
CSleep and CStop low-power modes are entered by the MCU when executing the WFI
(Wait for Interrupt) or WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit of
the Cortex®-Mx core is set after returning from an interrupt service routine.
A domain can enter low-power mode (DStop or DStandby) when the processor, its
subsystem and the peripherals allocated in the domain enter low-power mode.
If part of the domain is not in low-power mode, the domain remains in the current mode.
Finally the system can enter Stop or Standby when all EXTI wakeup sources are cleared
and the power domains are in DStop or DStandby mode.
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STM32H753xI Functional overview
53
3.7 Reset and clock controller (RCC)
The clock and reset controller is located in D3 domain. The RCC manages the generation of
all the clocks, as well as the clock gating and the control of the system and peripheral
resets. It provides a high flexibility in the choice of clock sources and allows to apply clock
ratios to improve the power consumption. In addition, on some communication peripherals
that are capable to work with two different clock domains (either a bus interface clock or a
kernel peripheral clock), the system frequency can be changed without modifying the
baudrate.
3.7.1 Clock management
The devices embed four internal oscillators, two oscillators with external crystal or
resonator, two internal oscillators with fast startup time and three PLLs.
The RCC receives the following clock source inputs:
Internal oscillators:
64 MHz HSI clock
48 MHz RC oscillator
4 MHz CSI clock
32 kHz LSI clock
External oscillators:
HSE clock: 4-50 MHz (generated from an external source) or 4-48 MHz(generated
from a crystal/ceramic resonator)
LSE clock: 32.768 kHz
The RCC provides three PLLs: one for system clock, two for kernel clocks.
The system starts on the HSI clock. The user application can then select the clock
configuration.
Table 3. System vs domain low-power mode
System power mode D1 domain power
mode
D2 domain power
mode
D3 domain power
mode
Run DRun/DStop/DStandby DRun/DStop/DStandby DRun
Stop DStop/DStandby DStop/DStandby DStop
Standby DStandby DStandby DStandby
Functional overview STM32H753xI
30/356 DS12117 Rev 7
3.7.2 System reset sources
Power-on reset initializes all registers while system reset reinitializes the system except for
the debug, part of the RCC and power controller status registers, as well as the backup
power domain.
A system reset is generated in the following cases:
Power-on reset (pwr_por_rst)
Brownout reset
Low level on NRST pin (external reset)
Window watchdog
Independent watchdog
Software reset
Low-power mode security reset
Exit from Standby
3.8 General-purpose input/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
After reset, all GPIOs (except debug pins) are in Analog mode to reduce power
consumption (refer to GPIOs register reset values in the device reference manual).
The I/O configuration can be locked if needed by following a specific sequence in order to
avoid spurious writing to the I/Os registers.
3.9 Bus-interconnect matrix
The devices feature an AXI bus matrix, two AHB bus matrices and bus bridges that allow
interconnecting bus masters with bus slaves (see Figure 3).
mm ‘23 Kbyle ANEF‘ Ethernet DMM DMA2 MAC SDMMcz USEHS‘ USBHSZ SDMMC‘ MDMA ammo me 64-bnAXI bus malnx 01 7mm A ] N] ] ] DMALFEW mm MEM mm pawn HasnA Upln‘ the flash 3 Upln‘ the )— AX‘ saw 5‘ 2 Kbyle ‘ ‘ AMMMMHFLA gamma D1 domain DzrmrmAHE am Legend r h LE 327mm: ‘ AX‘ ‘ A mm; mm H 0 Bus mump‘exer ,-.=u:|1
STM32H753xI Functional overview
DS12117 Rev 7 31/356
Figure 3. STM32H753xI bus matrix
MSv46613V2
AXIM
DMA2 Ethernet
MAC SDMMC2DMA1 USBHS1 USBHS2
APB1
SDMMC1 MDMA DMA2D LTDC
BDMA
APB4
Cortex-M7
I$
16KB
D$
16KB
AHBP
DMA1_MEM
DMA1_PERIPH
DMA2_MEM
DMA2_PERIPH
APB3
32-bit AHB bus matrix
D2 domain
64-bit AXI bus matrix
D1 domain
32-bit AHB bus matrix
D3 domain
DTCM
128 Kbyte
ITCM
64 Kbyte
Flash A
Up to 1 Mbyte
Flash B
Up to 1 Mbyte
AXI SRAM
512 Kbyte
QSPI
FMC
SRAM1 128
Kbyte
SRAM2 128
Kbyte
SRAM3
32 Kbyte
AHB1
AHB2
AHB4
SRAM4
64 Kbyte
Backup
SRAM
4 Kbyte
AHBS
CPU
D2-to-D1 AHB
D2-to-D3 AHB
D1-to-D2 AHB
D1-to-D3 AHB
32-bit bus
64-bit bus
Bus multiplexer
Legend
Master interface
Slave interface
AHB3
AXI
AHB
APB
APB2
TCM
Functional overview STM32H753xI
32/356 DS12117 Rev 7
3.10 DMA controllers
The devices feature four DMA instances to unload CPU activity:
A master direct memory access (MDMA)
The MDMA is a high-speed DMA controller, which is in charge of all types of memory
transfers (peripheral to memory, memory to memory, memory to peripheral), without
any CPU action. It features a master AXI interface and a dedicated AHB interface to
access Cortex®-M7 TCM memories.
The MDMA is located in D1 domain. It is able to interface with the other DMA
controllers located in D2 domain to extend the standard DMA capabilities, or can
manage peripheral DMA requests directly.
Each of the 16 channels can perform single block transfers, repeated block transfers
and linked list transfers.
Two dual-port DMAs (DMA1, DMA2) located in D2 domain, with FIFO and request
router capabilities.
One basic DMA (BDMA) located in D3 domain, with request router capabilities.
The DMA request router could be considered as an extension of the DMA controller. It
routes the DMA peripheral requests to the DMA controller itself. This allowing managing the
DMA requests with a high flexibility, maximizing the number of DMA requests that run
concurrently, as well as generating DMA requests from peripheral output trigger or DMA
event.
3.11 Chrom-ART Accelerator™ (DMA2D)
The Chrom-Art Accelerator™ (DMA2D) is a graphical accelerator which offers advanced bit
blitting, row data copy and pixel format conversion. It supports the following functions:
Rectangle filling with a fixed color
Rectangle copy
Rectangle copy with pixel format conversion
Rectangle composition with blending and pixel format conversion
Various image format coding are supported, from indirect 4bpp color mode up to 32bpp
direct color. It embeds dedicated memory to store color lookup tables. The DMA2D also
supports block based YCbCr to handle JPEG decoder output.
An interrupt can be generated when an operation is complete or at a programmed
watermark.
All the operations are fully automatized and are running independently from the CPU or the
DMAs.
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STM32H753xI Functional overview
53
3.12 Nested vectored interrupt controller (NVIC)
The devices embed a nested vectored interrupt controller which is able to manage 16
priority levels, and handle up to 150 maskable interrupt channels plus the 16 interrupt lines
of the Cortex®-M7 with FPU core.
Closely coupled NVIC gives low-latency interrupt processing
Interrupt entry vector table address passed directly to the core
Allows early processing of interrupts
Processing of late arriving, higher-priority interrupts
Support tail chaining
Processor context automatically saved on interrupt entry, and restored on interrupt exit
with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.
3.13 Extended interrupt and event controller (EXTI)
The EXTI controller performs interrupt and event management. In addition, it can wake up
the processor, power domains and/or D3 domain from Stop mode.
The EXTI handles up to 89 independent event/interrupt lines split as 28 configurable events
and 61 direct events .
Configurable events have dedicated pending flags, active edge selection, and software
trigger capable.
Direct events provide interrupts or events from peripherals having a status flag.
3.14 Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
programmable polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
Functional overview STM32H753xI
34/356 DS12117 Rev 7
3.15 Flexible memory controller (FMC)
The FMC controller main features are the following:
Interface with static-memory mapped devices including:
Static random access memory (SRAM)
NOR Flash memory/OneNAND Flash memory
PSRAM (4 memory banks)
NAND Flash memory with ECC hardware to check up to 8 Kbytes of data
Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories
8-,16-,32-bit data bus width
Independent Chip Select control for each memory bank
Independent configuration for each memory bank
Write FIFO
Read FIFO for SDRAM controller
The maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is the
FMC kernel clock divided by 2.
3.16 Quad-SPI memory interface (QUADSPI)
All devices embed a Quad-SPI memory interface, which is a specialized communication
interface targeting Single, Dual or Quad-SPI Flash memories. It supports both single and
double datarate operations.
It can operate in any of the following modes:
Direct mode through registers
External Flash status register polling mode
Memory mapped mode.
Up to 256 Mbytes of external Flash memory can be mapped, and 8-, 16- and 32-bit data
accesses are supported as well as code execution.
The opcode and the frame format are fully programmable.
3.17 Analog-to-digital converters (ADCs)
The STM32H753xI devices embed three analog-to-digital converters, which resolution can
be configured to 16, 14, 12, 10 or 8 bits.
Each ADC shares up to 20 external channels, performing conversions in the Single-shot or
Scan mode. In Scan mode, automatic conversion is performed on a selected group of
analog inputs.
Additional logic functions embedded in the ADC interface allow:
Simultaneous sample and hold
Interleaved sample and hold
The ADC can be served by the DMA controller, thus allowing to automatically transfer ADC
converted values to a destination location without any software action.
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STM32H753xI Functional overview
53
In addition, an analog watchdog feature can accurately monitor the converted voltage of
one, some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1,
TIM2, TIM3, TIM4, TIM6, TIM8, TIM15, HRTIM1 and LPTIM1 timer.
3.18 Temperature sensor
STM32H753xI devices embed a temperature sensor that generates a voltage (VTS) that
varies linearly with the temperature. This temperature sensor is internally connected to
ADC3_IN18. The conversion range is between 1.7 V and 3.6 V. It can measure the device
junction temperature ranging from 40 up to +125 °C.
The temperature sensor have a good linearity, but it has to be calibrated to obtain a good
overall accuracy of the temperature measurement. As the temperature sensor offset varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only. To improve the accuracy of
the temperature sensor measurement, each device is individually factory-calibrated by ST.
The temperature sensor factory calibration data are stored by ST in the System memory
area, which is accessible in Read-only mode.
3.19 VBAT operation
The VBAT power domain contains the RTC, the backup registers and the backup SRAM.
To optimize battery duration, this power domain is supplied by VDD when available or by the
voltage applied on VBAT pin (when VDD supply is not present). VBAT power is switched
when the PDR detects that VDD dropped below the PDR level.
The voltage on the VBAT pin could be provided by an external battery, a supercapacitor or
directly by VDD, in which case, the VBAT mode is not functional.
VBAT operation is activated when VDD is not present.
The VBAT pin supplies the RTC, the backup registers and the backup SRAM.
Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events
do not exit it from VBAT operation.
When PDR_ON pin is connected to VSS (Internal Reset OFF), the VBAT functionality is no
more available and VBAT pin should be connected to VDD.
Functional overview STM32H753xI
36/356 DS12117 Rev 7
3.20 Digital-to-analog converters (DAC)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs.
This dual digital Interface supports the following features:
two DAC converters: one for each output channel
8-bit or 12-bit monotonic output
left or right data alignment in 12-bit mode
synchronized update capability
noise-wave generation
triangular-wave generation
dual DAC channel independent or simultaneous conversions
DMA capability for each channel including DMA underrun error detection
external triggers for conversion
input voltage reference VREF+ or internal VREFBUF reference.
The DAC channels are triggered through the timer update outputs that are also connected
to different DMA streams.
3.21 Ultra-low-power comparators (COMP)
STM32H753xI devices embed two rail-to-rail comparators (COMP1 and COMP2). They
feature programmable reference voltage (internal or external), hysteresis and speed (low
speed for low-power) as well as selectable output polarity.
The reference voltage can be one of the following:
An external I/O
A DAC output channel
An internal reference voltage or submultiple (1/4, 1/2, 3/4).
All comparators can wake up from Stop mode, generate interrupts and breaks for the timers,
and be combined into a window comparator.
3.22 Operational amplifiers (OPAMP)
STM32H753xI devices embed two rail-to-rail operational amplifiers (OPAMP1 and
OPAMP2) with external or internal follower routing and PGA capability.
The operational amplifier main features are:
PGA with a non-inverting gain ranging of 2, 4, 8 or 16 or inverting gain ranging of -1, -3,
-7 or -15
One positive input connected to DAC
Output connected to internal ADC
Low input bias current down to 1 nA
Low input offset voltage down to 1.5 mV
Gain bandwidth up to 7.3 MHz
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STM32H753xI Functional overview
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The devices embeds two operational amplifiers (OPAMP1 and OPAMP2) with two inputs
and one output each. These three I/Os can be connected to the external pins, thus enabling
any type of external interconnections. The operational amplifiers can be configured
internally as a follower, as an amplifier with a non-inverting gain ranging from 2 to 16 or with
inverting gain ranging from -1 to -15.
3.23 Digital filter for sigma-delta modulators (DFSDM)
The devices embed one DFSDM with 4 digital filters modules and 8 external input serial
channels (transceivers) or alternately 8 internal parallel inputs support.
The DFSDM peripheral is dedicated to interface the external  modulators to
microcontroller and then to perform digital filtering of the received data streams (which
represent analog value on  modulators inputs). DFSDM can also interface PDM (Pulse
Density Modulation) microphones and perform PDM to PCM conversion and filtering in
hardware. DFSDM features optional parallel data stream inputs from internal ADC
peripherals or microcontroller memory (through DMA/CPU transfers into DFSDM).
DFSDM transceivers support several serial interface formats (to support various 
modulators). DFSDM digital filter modules perform digital processing according user
selected filter parameters with up to 24-bit final ADC resolution.
The DFSDM peripheral supports:
8 multiplexed input digital serial channels:
configurable SPI interface to connect various SD modulator(s)
configurable Manchester coded 1 wire interface support
PDM (Pulse Density Modulation) microphone input support
maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding)
clock output for SD modulator(s): 0..20 MHz
alternative inputs from 8 internal digital parallel channels (up to 16 bit input resolution):
internal sources: ADC data or memory data streams (DMA)
4 digital filter modules with adjustable digital signal processing:
–Sinc
x filter: filter order/type (1..5), oversampling ratio (up to 1..1024)
integrator: oversampling ratio (1..256)
up to 24-bit output data resolution, signed output data format
automatic data offset correction (offset stored in register by user)
continuous or single conversion
start-of-conversion triggered by:
software trigger
internal timers
external events
start-of-conversion synchronously with first digital filter module (DFSDM0)
analog watchdog feature:
low value and high value data threshold registers
dedicated configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32)
input from final output data or from selected input digital serial channels
continuous monitoring independently from standard conversion
Functional overview STM32H753xI
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short circuit detector to detect saturated analog input values (bottom and top range):
up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on serial data stream
monitoring continuously each input serial channel
break signal generation on analog watchdog event or on short circuit detector event
extremes detector:
storage of minimum and maximum values of final conversion data
refreshed by software
DMA capability to read the final conversion data
interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial
channel clock absence
“regular” or “injected” conversions:
“regular” conversions can be requested at any time or even in Continuous mode
without having any impact on the timing of “injected” conversions
“injected” conversions for precise timing and with high conversion priority
3.24 Digital camera interface (DCMI)
The devices embed a camera interface that can connect with camera modules and CMOS
sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera
interface can achieve a data transfer rate up to 140 Mbyte/s using a 80 MHz pixel clock. It
features:
Programmable polarity for the input pixel clock and synchronization signals
Parallel data communication can be 8-, 10-, 12- or 14-bit
Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2
progressive video, RGB 565 progressive video or compressed data (like JPEG)
Supports Continuous mode or Snapshot (a single frame) mode
Capability to automatically crop the image
Table 4. DFSDM implementation
DFSDM features DFSDM1
Number of filters 4
Number of input
transceivers/channels 8
Internal ADC parallel input X
Number of external triggers 16
Regular channel information in
identification register X
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3.25 LCD-TFT controller
The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue)
and delivers all signals to interface directly to a broad range of LCD and TFT panels up to
XGA (1024x768) resolution with the following features:
2 display layers with dedicated FIFO (64x64-bit)
Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer
Up to 8 input color formats selectable per layer
Flexible blending between two layers using alpha value (per pixel or constant)
Flexible programmable parameters for each layer
Color keying (transparency color)
Up to 4 programmable interrupt events
AXI master interface with burst of 16 words
3.26 JPEG Codec (JPEG)
The JPEG Codec can encode and decode a JPEG stream as defined in the ISO/IEC 10918-
1 specification. It provides an fast and simple hardware compressor and decompressor of
JPEG images with full management of JPEG headers.
The JPEG codec main features are as follows:
8-bit/channel pixel depths
Single clock per pixel encoding and decoding
Support for JPEG header generation and parsing
Up to four programmable quantization tables
Fully programmable Huffman tables (two AC and two DC)
Fully programmable minimum coded unit (MCU)
Encode/decode support (non simultaneous)
Single clock Huffman coding and decoding
Two-channel interface: Pixel/Compress In, Pixel/Compressed Out
Support for single greyscale component
Ability to enable/disable header processing
Fully synchronous design
Configuration for High-speed decode mode
3.27 Random number generator (RNG)
All devices embed an RNG that delivers 32-bit random numbers generated by an integrated
analog circuit.
Functional overview STM32H753xI
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3.28 Cryptographic acceleration (CRYP and HASH)
The devices embed a cryptographic processor that supports the advanced cryptographic
algorithms usually required to ensure confidentiality, authentication, data integrity and non-
repudiation when exchanging messages with a peer:
Encryption/Decryption
DES/TDES (data encryption standard/triple data encryption standard): ECB
(electronic codebook) and CBC (cipher block chaining) chaining algorithms, 64-,
128- or 192-bit key
AES (advanced encryption standard): ECB, CBC, GCM, CCM, and CTR (Counter
mode) chaining algorithms, 128, 192 or 256-bit key
Universal HASH
SHA-1 and SHA-2 (secure HASH algorithms)
–MD5
–HMAC
The cryptographic accelerator supports DMA request generation.
3.29 Timers and watchdogs
The devices include one high-resolution timer, two advanced-control timers, ten general-
purpose timers, two basic timers, five low-power timers, two watchdogs and a SysTick timer.
All timer counters can be frozen in Debug mode.
Table 5 compares the features of the advanced-control, general-purpose and basic timers.
Table 5. Timer feature comparison
Timer
type Timer Counter
resolution
Counter
type
Prescaler
factor
DMA
request
generation
Capture/
compare
channels
Comple-
mentary
output
Max
interface
clock
(MHz)
Max
timer
clock
(MHz)
(1)
High-
resolution
timer
HRTIM1 16-bit Up
/1 /2 /4
(x2 x4 x8
x16 x32,
with DLL)
Yes 10 Yes 480 480
Advanced
-control
TIM1,
TIM8 16-bit
Up,
Down,
Up/down
Any
integer
between 1
and
65536
Yes 4 Yes 120 240
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General
purpose
TIM2,
TIM5 32-bit
Up,
Down,
Up/down
Any
integer
between 1
and
65536
Yes 4 No 120 240
TIM3,
TIM4 16-bit
Up,
Down,
Up/down
Any
integer
between 1
and
65536
Yes 4 No 120 240
TIM12 16-bit Up
Any
integer
between 1
and
65536
No 2 No 120 240
TIM13,
TIM14 16-bit Up
Any
integer
between 1
and
65536
No 1 No 120 240
TIM15 16-bit Up
Any
integer
between 1
and
65536
Yes 2 1 120 240
TIM16,
TIM17 16-bit Up
Any
integer
between 1
and
65536
Yes 1 1 120 240
Basic TIM6,
TIM7 16-bit Up
Any
integer
between 1
and
65536
Yes 0 No 120 240
Low-
power
timer
LPTIM1,
LPTIM2,
LPTIM3,
LPTIM4,
LPTIM5
16-bit Up
1, 2, 4, 8,
16, 32, 64,
128
No 0 No 120 240
1. The maximum timer clock is up to 480 MHz depending on TIMPRE bit in the RCC_CFGR register and D2PRE1/2 bits in
RCC_D2CFGR register.
Table 5. Timer feature comparison (continued)
Timer
type Timer Counter
resolution
Counter
type
Prescaler
factor
DMA
request
generation
Capture/
compare
channels
Comple-
mentary
output
Max
interface
clock
(MHz)
Max
timer
clock
(MHz)
(1)
Functional overview STM32H753xI
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3.29.1 High-resolution timer (HRTIM1)
The high-resolution timer (HRTIM1) allows generating digital signals with high-accuracy
timings, such as PWM or phase-shifted pulses.
It consists of 6 timers, 1 master and 5 slaves, totaling 10 high-resolution outputs, which can
be coupled by pairs for deadtime insertion. It also features 5 fault inputs for protection
purposes and 10 inputs to handle external events such as current limitation, zero voltage or
zero current switching.
The HRTIM1 timer is made of a digital kernel clocked at 480 MHz The high-resolution is
available on the 10 outputs in all operating modes: variable duty cycle, variable frequency,
and constant ON time.
The slave timers can be combined to control multiswitch complex converters or operate
independently to manage multiple independent converters.
The waveforms are defined by a combination of user-defined timings and external events
such as analog or digital feedbacks signals.
HRTIM1 timer includes options for blanking and filtering out spurious events or faults. It also
offers specific modes and features to offload the CPU: DMA requests, Burst mode
controller, Push-pull and Resonant mode.
It supports many topologies including LLC, Full bridge phase shifted, buck or boost
converters, either in voltage or current mode, as well as lighting application (fluorescent or
LED). It can also be used as a general purpose timer, for instance to achieve high-resolution
PWM-emulated DAC.
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3.29.2 Advanced-control timers (TIM1, TIM8)
The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators
multiplexed on 6 channels. They have complementary PWM outputs with programmable
inserted dead times. They can also be considered as complete general-purpose timers.
Their 4 independent channels can be used for:
Input capture
Output compare
PWM generation (Edge- or Center-aligned modes)
One-pulse mode output
If configured as standard 16-bit timers, they have the same features as the general-purpose
TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0-
100%).
The advanced-control timer can work together with the TIMx timers via the Timer Link
feature for synchronization or event chaining.
TIM1 and TIM8 support independent DMA request generation.
3.29.3 General-purpose timers (TIMx)
There are ten synchronizable general-purpose timers embedded in the STM32H753xI
devices (see Table 5 for differences).
TIM2, TIM3, TIM4, TIM5
The devices include 4 full-featured general-purpose timers: TIM2, TIM3, TIM4 and
TIM5. TIM2 and TIM5 are based on a 32-bit auto-reload up/downcounter and a 16-bit
prescaler while TIM3 and TIM4 are based on a 16-bit auto-reload up/downcounter and
a 16-bit prescaler. All timers feature 4 independent channels for input capture/output
compare, PWM or One-pulse mode output. This gives up to 16 input capture/output
compare/PWMs on the largest packages.
TIM2, TIM3, TIM4 and TIM5 general-purpose timers can work together, or with the
other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the
Timer Link feature for synchronization or event chaining.
Any of these general-purpose timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are
capable of handling quadrature (incremental) encoder signals and the digital outputs
from 1 to 4 hall-effect sensors.
TIM12, TIM13, TIM14, TIM15, TIM16, TIM17
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM13, TIM14, TIM16 and TIM17 feature one independent channel, whereas TIM12
and TIM15 have two independent channels for input capture/output compare, PWM or
One-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5
full-featured general-purpose timers or used as simple timebases.
Functional overview STM32H753xI
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3.29.4 Basic timers TIM6 and TIM7
These timers are mainly used for DAC trigger and waveform generation. They can also be
used as a generic 16-bit time base.
TIM6 and TIM7 support independent DMA request generation.
3.29.5 Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5)
The low-power timers have an independent clock and is running also in Stop mode if it is
clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode.
This low-power timer supports the following features:
16-bit up counter with 16-bit autoreload register
16-bit compare register
Configurable output: pulse, PWM
Continuous / One-shot mode
Selectable software / hardware input trigger
Selectable clock source:
Internal clock source: LSE, LSI, HSI or APB clock
External clock source over LPTIM input (working even with no internal clock source
running, used by the Pulse Counter Application)
Programmable digital glitch filter
Encoder mode
3.29.6 Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes.
3.29.7 Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
Debug mode.
3.29.8 SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
downcounter. It features:
A 24-bit downcounter
Autoreload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source.
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3.30 Real-time clock (RTC), backup SRAM and backup registers
The RTC is an independent BCD timer/counter. It supports the following features:
Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.
Two programmable alarms.
On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy.
Three anti-tamper detection pins with programmable filter.
Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
VBAT mode.
17-bit auto-reload wakeup timer (WUT) for periodic events with programmable
resolution and period.
The RTC and the 32 backup registers are supplied through a switch that takes power either
from the VDD supply when present or from the VBAT pin.
The backup registers are 32-bit registers used to store 128 bytes of user application data
when VDD power is not present. They are not reset by a system or power reset, or when the
device wakes up from Standby mode.
The RTC clock sources can be:
A 32.768 kHz external crystal (LSE)
An external resonator or oscillator (LSE)
The internal low-power RC oscillator (LSI, with typical frequency of 32 kHz)
The high-speed external clock (HSE) divided by 32.
The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the
LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in
all low-power modes.
All RTC events (Alarm, Wakeup Timer, Timestamp or Tamper) can generate an interrupt and
wakeup the device from the low-power modes.
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3.31 Inter-integrated circuit interface (I2C)
STM32H753xI devices embed four I2C interfaces.
The I2C bus interface handles communications between the microcontroller and the serial
I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
I2C-bus specification and user manual rev. 5 compatibility:
Slave and Master modes, multimaster capability
Standard-mode (Sm), with a bitrate up to 100 kbit/s
Fast-mode (Fm), with a bitrate up to 400 kbit/s
Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
Programmable setup and hold times
Optional clock stretching
System Management Bus (SMBus) specification rev 2.0 compatibility:
Hardware PEC (Packet Error Checking) generation and verification with ACK
control
Address resolution protocol (ARP) support
SMBus alert
Power System Management Protocol (PMBusTM) specification rev 1.1 compatibility
Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming.
Wakeup from Stop mode on address match
Programmable analog and digital noise filters
1-byte buffer with DMA capability
3.32 Universal synchronous/asynchronous receiver transmitter
(USART)
STM32H753xI devices have four embedded universal synchronous receiver transmitters
(USART1, USART2, USART3 and USART6) and four universal asynchronous receiver
transmitters (UART4, UART5, UART7 and UART8). Refer to Table 6 for a summary of
USARTx and UARTx features.
These interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire Half-duplex communication mode and
have LIN Master/Slave capability. They provide hardware management of the CTS and RTS
signals, and RS485 Driver Enable. They are able to communicate at speeds of up to
12.5 Mbit/s.
USART1, USART2, USART3 and USART6 also provide Smartcard mode (ISO 7816
compliant) and SPI-like communication capability.
The USARTs embed a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO mode
is enabled by software and is disabled by default.
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STM32H753xI Functional overview
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All USART have a clock domain independent from the CPU clock, allowing the USARTx to
wake up the MCU from Stop mode.The wakeup from Stop mode is programmable and can
be done on:
Start bit detection
Any received data frame
A specific programmed data frame
Specific TXFIFO/RXFIFO status when FIFO mode is enabled.
All USART interfaces can be served by the DMA controller.
3.33 Low-power universal asynchronous receiver transmitter
(LPUART)
The device embeds one Low-Power UART (LPUART1). The LPUART supports
asynchronous serial communication with minimum power consumption. It supports half
duplex single wire communication and modem operations (CTS/RTS). It allows
multiprocessor communication.
The LPUARTs embed a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). FIFO
mode is enabled by software and is disabled by default.
Table 6. USART features
USART modes/features(1)
1. X = supported.
USART1/2/3/6 UART4/5/7/8
Hardware flow control for modem X X
Continuous communication using DMA X X
Multiprocessor communication X X
Synchronous mode (Master/Slave) X -
Smartcard mode X -
Single-wire Half-duplex communication X X
IrDA SIR ENDEC block X X
LIN mode X X
Dual clock domain and wakeup from low power mode X X
Receiver timeout interrupt X X
Modbus communication X X
Auto baud rate detection X X
Driver Enable X X
USART data length 7, 8 and 9 bits
Tx/Rx FIFO X X
Tx/Rx FIFO size 16
Functional overview STM32H753xI
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The LPUART has a clock domain independent from the CPU clock, and can wakeup the
system from Stop mode. The wakeup from Stop mode are programmable and can be done
on:
Start bit detection
Any received data frame
A specific programmed data frame
Specific TXFIFO/RXFIFO status when FIFO mode is enabled.
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to
9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame
while having an extremely low energy consumption. Higher speed clock can be used to
reach higher baudrates.
LPUART interface can be served by the DMA controller.
3.34 Serial peripheral interface (SPI)/inter- integrated sound
interfaces (I2S)
The devices feature up to six SPIs (SPI2S1, SPI2S2, SPI2S3, SPI4, SPI5 and SPI6) that
allow communicating up to 150 Mbits/s in Master and Slave modes, in Half-duplex, Full-
duplex and Simplex modes. The 3-bit prescaler gives 8 master mode frequencies and the
frame is configurable from 4 to 16 bits. All SPI interfaces support NSS pulse mode, TI mode,
Hardware CRC calculation and 8x 8-bit embedded Rx and Tx FIFOs with DMA capability.
Three standard I2S interfaces (multiplexed with SPI1, SPI2 and SPI3) are available. They
can be operated in Master or Slave mode, in Simplex communication modes, and can be
configured to operate with a 16-/32-bit resolution as an input or output channel. Audio
sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the
I2S interfaces is/are configured in Master mode, the master clock can be output to the
external DAC/CODEC at 256 times the sampling frequency. All I2S interfaces support 16x 8-
bit embedded Rx and Tx FIFOs with DMA capability.
3.35 Serial audio interfaces (SAI)
The devices embed 4 SAIs (SAI1, SAI2, SAI3 and SAI4) that allow designing many stereo
or mono audio protocols such as I2S, LSB or MSB-justified, PCM/DSP, TDM or AC’97. An
SPDIF output is available when the audio block is configured as a transmitter. To bring this
level of flexibility and reconfigurability, the SAI contains two independent audio sub-blocks.
Each block has it own clock generator and I/O line controller.
Audio sampling frequencies up to 192 kHz are supported.
In addition, up to 8 microphones can be supported thanks to an embedded PDM interface.
The SAI can work in master or slave configuration. The audio sub-blocks can be either
receiver or transmitter and can work synchronously or asynchronously (with respect to the
other one). The SAI can be connected with other SAIs to work synchronously.
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3.36 SPDIFRX Receiver Interface (SPDIFRX)
The SPDIFRX peripheral is designed to receive an S/PDIF flow compliant with IEC-60958
and IEC-61937. These standards support simple stereo streams up to high sample rate,
and compressed multi-channel surround sound, such as those defined by Dolby or DTS (up
to 5.1).
The main SPDIFRX features are the following:
Up to 4 inputs available
Automatic symbol rate detection
Maximum symbol rate: 12.288 MHz
Stereo stream from 32 to 192 kHz supported
Supports Audio IEC-60958 and IEC-61937, consumer applications
Parity bit management
Communication using DMA for audio samples
Communication using DMA for control and user channel information
Interrupt capabilities
The SPDIFRX receiver provides all the necessary features to detect the symbol rate, and
decode the incoming data stream. The user can select the wanted SPDIF input, and when a
valid signal will be available, the SPDIFRX will re-sample the incoming signal, decode the
Manchester stream, recognize frames, sub-frames and blocks elements. It delivers to the
CPU decoded data, and associated status flags.
The SPDIFRX also offers a signal named spdif_frame_sync, which toggles at the S/PDIF
sub-frame rate that will be used to compute the exact sample rate for clock drift algorithms.
3.37 Single wire protocol master interface (SWPMI)
The Single wire protocol master interface (SWPMI) is the master interface corresponding to
the Contactless Frontend (CLF) defined in the ETSI TS 102 613 technical specification. The
main features are:
Full-duplex communication mode
automatic SWP bus state management (active, suspend, resume)
configurable bitrate up to 2 Mbit/s
automatic SOF, EOF and CRC handling
SWPMI can be served by the DMA controller.
Functional overview STM32H753xI
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3.38 Management Data Input/Output (MDIO) slaves
The devices embed an MDIO slave interface it includes the following features:
32 MDIO Registers addresses, each of which is managed using separate input and
output data registers:
32 x 16-bit firmware read/write, MDIO read-only output data registers
32 x 16-bit firmware read-only, MDIO write-only input data registers
Configurable slave (port) address
Independently maskable interrupts/events:
MDIO Register write
MDIO Register read
MDIO protocol error
Able to operate in and wake up from Stop mode
3.39 SD/SDIO/MMC card host interfaces (SDMMC)
Two SDMMC host interfaces are available. They support MultiMediaCard System
Specification Version 4.51 in three different databus modes: 1 bit (default), 4 bits and 8 bits.
Both interfaces support the SD memory card specifications version 4.1. and the SDIO card
specification version 4.0. in two different databus modes: 1 bit (default) and 4 bits.
Each SDMMC host interface supports only one SD/SDIO/MMC card at any one time and a
stack of MMC Version 4.51 or previous.
The SDMMC host interface embeds a dedicated DMA controller allowing high-speed
transfers between the interface and the SRAM.
3.40 Controller area network (FDCAN1, FDCAN2)
The controller area network (CAN) subsystem consists of two CAN modules, a shared
message RAM memory and a clock calibration unit.
Both CAN modules (FDCAN1 and FDCAN2) are compliant with ISO 11898-1 (CAN protocol
specification version 2.0 part A, B) and CAN FD protocol specification version 1.0.
FDCAN1 supports time triggered CAN (TT-FDCAN) specified in ISO 11898-4, including
event synchronized time-triggered communication, global system time, and clock drift
compensation. The FDCAN1 contains additional registers, specific to the time triggered
feature. The CAN FD option can be used together with event-triggered and time-triggered
CAN communication.
A 10-Kbyte message RAM memory implements filters, receive FIFOs, receive buffers,
transmit event FIFOs, transmit buffers (and triggers for TT-FDCAN). This message RAM is
shared between the two FDCAN1 and FDCAN2 modules.
The common clock calibration unit is optional. It can be used to generate a calibrated clock
for both FDCAN1 and FDCAN2 from the HSI internal RC oscillator and the PLL, by
evaluating CAN messages received by the FDCAN1.
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3.41 Universal serial bus on-the-go high-speed (OTG_HS)
The devices embed two USB OTG high-speed (up to 480 Mbit/s) device/host/OTG
peripheral. OTG-HS1 supports both full-speed and high-speed operations, while OTG-HS2
supports only full-speed operations. They both integrate the transceivers for full-speed
operation (12 Mbit/s) and are able to operate from the internal HSI48 oscillator. OTG-HS1
features a UTMI low-pin interface (ULPI) for high-speed operation (480 Mbit/s). When using
the USB OTG-HS1 in HS mode, an external PHY device connected to the ULPI is required.
The USB OTG HS peripherals are compliant with the USB 2.0 specification and with the
OTG 2.0 specification. They have software-configurable endpoint setting and supports
suspend/resume. The USB OTG controllers require a dedicated 48 MHz clock that is
generated by a PLL connected to the HSE oscillator.
The main features are:
Combined Rx and Tx FIFO size of 4 Kbytes with dynamic FIFO sizing
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
9 bidirectional endpoints (including EP0)
16 host channels with periodic OUT support
Software configurable to OTG1.3 and OTG2.0 modes of operation
USB 2.0 LPM (Link Power Management) support
Battery Charging Specification Revision 1.2 support
Internal FS OTG PHY support
External HS or HS OTG operation supporting ULPI in SDR mode (OTG_HS1 only)
The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can
be clocked using the 60 MHz output.
Internal USB DMA
HNP/SNP/IP inside (no need for any external resistor)
For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
3.42 Ethernet MAC interface with dedicated DMA controller (ETH)
The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for
ethernet LAN communications through an industry-standard medium-independent interface
(MII) or a reduced medium-independent interface (RMII). The microcontroller requires an
external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair,
fiber, etc.). The PHY is connected to the device MII port using 17 signals for MII or 9 signals
for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller.
Functional overview STM32H753xI
52/356 DS12117 Rev 7
The devices include the following features:
Supports 10 and 100 Mbit/s rates
Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM
and the descriptors
Tagged MAC frame support (VLAN support)
Half-duplex (CSMA/CD) and full-duplex operation
MAC control sublayer (control frames) support
32-bit CRC generation and removal
Several address filtering modes for physical and multicast address (multicast and
group addresses)
32-bit status code for each transmitted or received frame
Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the
receive FIFO are both 2 Kbytes.
Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008
(PTP V2) with the time stamp comparator connected to the TIM2 input
Triggers interrupt when system time becomes greater than target time
3.43 High-definition multimedia interface (HDMI)
- consumer electronics control (CEC)
The devices embed a HDMI-CEC controller that provides hardware support for the
Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard).
This protocol provides high-level control functions between all audiovisual products in an
environment. It is specified to operate at low speeds with minimum processing and memory
overhead. It has a clock domain independent from the CPU clock, allowing the HDMI-CEC
controller to wakeup the MCU from Stop mode on data reception.
3.44 Debug infrastructure
The devices offer a comprehensive set of debug and trace features to support software
development and system integration.
Breakpoint debugging
Code execution tracing
Software instrumentation
JTAG debug port
Serial-wire debug port
Trigger input and output
Serial-wire trace port
Trace port
Arm® CoreSight™ debug and trace components
The debug can be controlled via a JTAG/Serial-wire debug access port, using industry
standard debugging tools.
The trace port performs data capture for logging and analysis.
DS12117 Rev 7 53/356
STM32H753xI Memory mapping
53
4 Memory mapping
Refer to the product line reference manual for details on the memory mapping as well as the
boundary addresses for all peripherals.
2s 27 23 29 an 3‘ 32 33 34 35 as 37 as 39 40 m 42 as 44 45 w 47 43 as 50
Pin descriptions STM32H753xI
54/356 DS12117 Rev 7
5 Pin descriptions
Figure 4. LQFP100 pinout
1. The above figure shows the package top view.
MSv41918V4
VDD
VSS
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
PE2 1 75 VDD
PE3 2 74 VSS
PE4 3 73 VCAP
PE5 4 72 PA13
PE6 5 71 PA12
VBAT 6 70 PA11
PC13 7 69 PA10
PC14-OSC32_IN 8 68 PA9
PC15-OSC32_OUT 9 67 PA8
VSS 10 66 PC9
VDD 11 65 PC8
PH0-OSC_IN 12 64 PC7
PH1-OSC_OUT 13 100-pins 63 PC6
NRST 14 62 PD15
PC0 15 61 PD14
PC1 16 60 PD13
PC2_C 17 59 PD12
PC3_C 18 58 PD11
VSSA 19 57 PD10
VREF+ 20 56 PD9
VDDA 21 55 PD8
PA0 22 54 PB15
PA1 23 53 PB14
PA2 24 52 PB13
PA3 25 51 PB12
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
VSS
VDD
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VCAP
VSS
VDD
DS12117 Rev 7 55/356
STM32H753xI Pin descriptions
102
Figure 5. TFBGA100 pinout
1. The above figure shows the package top view.
MSv46177V2
PC14-
OSC32_IN PC13 PE2 PB9 PB7 PB4 PB3 PA15 PA14 PA13
12345678910
A
B
C
D
E
F
G
H
J
K
PC15-
OSC32_OUT VBAT PE3 PB8 PB6 PD5 PD2 PC11 PC10 PA12
PH0-OSC_IN VSS PE4 PE1 PB5 PC12 PA9 PA11
PH1-
OSC_OUT VDD PE5 PA10
NRST PC2_C PE6 PC7
PC0 PC1
VSSA PA0
VDDA PA1 PA5 PB14
VSS PA2 PA6 PD13
VDD PA3 PA7 PB1 PE9 PB12 PD8 PD12
PE0 BOOT0 PD7 PD4
PD6 PD3
PD0 PA8
VSS VSS VSS VCAP PD1 PC9
PC3_C VDDLDO VDD VDD33USB PDR_ON PC8
PA4 PC4 PB2 PE10 PE14 PD15 PD11
PC6
PB15
PC5 PE7 PE11 PE15 PD14 PD10
PB0 PE8 PE12 PB10 PB13 PD9
PE13 PB11
VCAP
vvvpppp
Pin descriptions STM32H753xI
56/356 DS12117 Rev 7
Figure 6. LQFP144 pinout
1. The above figure shows the package top view.
MSv41917V4
VDD
PDR_ON
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PG15
VDD
VSS
PG14
PG13
PG12
PG11
PG10
PG9
PD7
PD6
VDD
VSS
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
PE2 1 108 VDD
PE3 2 107 VSS
PE4 3 106 VCAP
PE5 4 105 PA13
PE6 5 104 PA12
VBAT 6 103 PA11
PC13 7 102 PA10
PC14-OSC32_IN 8 101 PA9
PC15-OSC32_OUT 9 100 PA8
PF0 10 99 PC9
PF1 11 98 PC8
PF2 12 97 PC7
PF3 13 96 PC6
PF4 14 95 VDD33USB
PF5 15 94 VSS
VSS 16 93 PG8
VDD 17 92 PG7
PF6 18 144-pins 91 PG6
PF7 19 90 PG5
PF8 20 89 PG4
PF9 21 88 PG3
PF10 22 87 PG2
PH0-OSC_IN 23 86 PD15
PH1-OSC_OUT 24 85 PD14
NRST 25 84 VDD
PC0 26 83 VSS
PC1 27 82 PD13
PC2_C 28 81 PD12
PC3_C 29 80 PD11
VDD 30 79 PD10
VSSA 31 78 PD9
VREF+ 32 77 PD8
VDDA 33 76 PB15
PA0 34 75 PB14
PA1 35 74 PB13
PA2 36 73 PB12
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
PA3
VSS
VDD
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PF11
PF12
VSS
VDD
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
VSS
VDD
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VCAP
VDD
our out
DS12117 Rev 7 57/356
STM32H753xI Pin descriptions
102
Figure 7. UFBGA169 ballout
1. The above figure shows the package top view.
MSv45339V4
A
B
C
D
E
F
G
H
J
K
L
M
N
12345678910111213
PE4 PE2 VDD PI6 PB6 PI2 VDD PG10 PD5 VDD PC12 PC10 PI0
PC15-
OSC32_
OUT
PE3 VSS VDDLDO PB8 PB4 PI3 PG11 PD6 VSS PC11 PA14 PI1
PC14-
OSC32_
IN
PE5 PDR_ON PB9 PB5 PG14 PG9 PD4 PD1 PA15 VSS VDD
VDD VSS PC13 PE0 PB7 PG13 PD7 PD3 PD0 PA13 VDDLDO VCAP
PI11 PI7 VBAT
PE1
PF3 BOOT0 PG15 PG12 PD2 PA10 PA9 PA8 PA12
PI13 PI12 PF0
PF1
PF5 PF7 PB3 PG4 PC6 PC7 PC9 PC8 PA11
VDD VSS PF4
PF2
PF9 NRST PF13 PE7 PG6 PG7 PG8 VDD50_
USB
VDD33_
USB
PH0-
OSC_
IN
PH1-
OSC_
OUT
PF10
PF6
PJ1 PA4 PF14 PE8 PG2 PG3 PG5 VSS VDD
PC1 VSSA
PF8
PA0 PA7 PF15 PE9 PE14 PD11 PD13 PD15 PD14
PC3_C PH4
PJ0
PA6 PC4 PG0 PE13 PH10 PH12 PD9 PD10 PD12
VDDA VREF+ PH5
PA1
PB1 PB2 PG1 PE12 PB10 PH11 PB13 VSS VDD
VDD VSS PH3
PA5
PB0 PF11 VSS PE10 PB11 VDDLDO VSS PD8 PB15
PA2 PH2 PA3 VDD PC5 PF12 VDD PE11 PE15 VCAP VDD PB12 PB14
PC0
PE6
PC2_C
VSS
Pin descriptions STM32H753xI
58/356 DS12117 Rev 7
Figure 8. LQFP176 pinout
1. The above figure shows the package top view.
PINOUT UNDER DEVELOPMENT
MSv41916V5
PI7
PI6
PI5
PI4
VDD
PDR_ON
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PG15
VDD
VSS
PG14
PG13
PG12
PG11
PG10
PG9
PD7
PD6
VDD
VSS
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
VDD
VSS
PI3
PI2
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
PE2 1132 PI1
PE3 2 131 PI0
PE4 3 130 PH15
PE5 4 129 PH14
PE6 5 128 PH13
VBAT 6 127 VDD
PI8 7 126 VSS
PC13 8 125 VCAP
PC14-OSC32_IN 9 124 PA13
PC15-OSC32_OUT 10 123 PA12
PI9 11 122 PA11
PI10 12 121 PA10
PI11 13 120 PA9
VSS 14 119 PA8
VDD 15 118 PC9
PF0 16 117 PC8
PF1 17 116 PC7
PF2 18 115 PC6
PF3 19 114 VDD33USB
PF4 20 113 VSS
PF5 21 112 PG8
VSS 22 176-pins 111 PG7
VDD 23 110 PG6
PF6 24 109 PG5
PF7 25 108 PG4
PF8 26 107 PG3
PF9 27 106 PG2
PF10 28 105 PD15
PH0-OSC_IN 29 104 PD14
PH1-OSC_OUT 30 103 VDD
NRST 31 102 VSS
PC0 32 101 PD13
PC1 33 100 PD12
PC2_C 34 99 PD11
PC3_C 35 98 PD10
VDD 36 97 PD9
VSSA 37 96 PD8
VREF+ 38 95 PB15
VDDA 39 94 PB14
PA0 40 93 PB13
PA1 41 92 PB12
PA2 42 91 VDD
PH2 43 90 VSS
PH3 44 89 PH12
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
PH4
PH5
PA3
VSS
VDD
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PF11
PF12
VSS
VDD
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
VSS
VDD
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VCAP
VDD
PH6
PH7
PH8
PH9
PH10
PH11
m ‘2 ‘3 out
DS12117 Rev 7 59/356
STM32H753xI Pin descriptions
102
Figure 9. UFBGA176+25 ballout
1. The above figure shows the package top view.
MSv41912V3
123456789101112131415
APE3 PE2 PE1 PE0 PB8 PB5 PG14 PG13 PB4 PB3 PD7 PC12 PA15 PA14 PA13
BPE4 PE5 PE6 PB9 PB7 PB6 PG15 PG12 PG11 PG10 PD6 PD0 PC11 PC10 PA12
CVBAT PI7 PI6 PI5 VDD PDR_ON VDD VDD VDD PG9 PD5 PD1 PI3 PI2 PA11
DPC13 PI8 PI9 PI4 VSS BOOT0 VSS VSS VSS PD4 PD3 PD2 PH15 PI1 PA10
E
PC14-
OSC32_
IN
PF0 PI10 PI11 PH13 PH14 PI0 PA9
F
PC15-
OSC32_
OUT
VSS VDD PH2 VSS VSS VSS VSS VSS VSS VCAP PC9 PA8
GPH0-
OSC_IN VSS VDD PH3 VSS VSS VSS VSS VSS VSS VDD PC8 PC7
H
PH1-
OSC_
OUT
PF2 PF1 PH4 VSS VSS VSS VSS VSS VSS VDD
33USB PG8 PC6
JNRST PF3 PF4 PH5 VSS VSS VSS VSS VSS VDD VDD PG7 PG6
KPF7 PF6 PF5 VDD VSS VSS VSS VSS VSS PH12 PG5 PG4 PG3
LPF10 PF9 PF8 PH11 PH10 PD15 PG2
MVSSA PC0 PC1 PC2_C PC3_C PB2 PG1 VSS VSS VCAP PH6 PH8 PH9 PD14 PD13
NVREF- PA1 PA0 PA4 PC4 PF13 PG0 VDD VDD VDD PE13 PH7 PD12 PD11 PD10
PVREF+ PA2 PA6 PA5 PC5 PF12 PF15 PE8 PE9 PE11 PE14 PB12 PB13 PD9 PD8
RVDDA PA3 PA7 PB1 PB0 PF11 PF14 PE7 PE10 PE12 PE15 PB10 PB11 PB14 PB15
VSS
Pin descriptions STM32H753xI
60/356 DS12117 Rev 7
Figure 10. LQFP208 pinout
1. The above figure shows the package top view.
MSv41915V3
PI7
PI6
PI5
PI4
VDD
PDR_ON
VSS
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PG15
PK7
PK6
PK5
PK4
PK3
VDD
VSS
PG14
PG13
PG12
PG11
PG10
PG9
PJ15
PJ14
PJ13
PJ12
PD7
PD6
VDD
VSS
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
VDD
PI3
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
PE2 1156 PI2
PE3 2 155 PI1
PE4 3 154 PI0
PE5 4 153 PH15
PE6 5 152 PH14
VBAT 6 151 PH13
PI8 7 150 VDD
PC13 8 149 VSS
PC14-OSC32_IN 9 148 VCAP
PC15-OSC32_OUT 10 147 PA13
PI9 11 146 PA12
PI10 12 145 PA11
PI11 13 144 PA10
VSS 14 143 PA9
VDD 15 142 PA8
PF0 16 141 PC9
PF1 17 140 PC8
PF2 18 139 PC7
PI12 19 138 PC6
PI13 20 137 VDD33USB
PI14 21 136 VSS
PF3 22 135 PG8
PF4 23 134 PG7
PF5 24 133 PG6
VSS 25 208-pins 132 PG5
VDD 26 131 PG4
PF6 27 130 PG3
28 129 PG2
PF8 29 128 PK2
PF9 30 127 PK1
PF10 31 126 PK0
PH0-OSC_IN 32 125 VSS
PH1-OSC_OUT 33 124 VDD
NRST 34 123 PJ11
PC0 35 122 PJ10
PC1 36 121 PJ9
PC2_C 37 120 PJ8
PC3_C 38 119 PJ7
VDD 39 118 PJ6
VSSA 40 117 PD15
VREF+ 41 116 PD14
VDDA 42 115 VDD
PA0 43 114 VSS
PA1 44 113 PD13
PA2 45 112 PD12
PH2 46 111 PD11
PH3 47 110 PD10
PH4 48 109 PD9
PH5 49 108 PD8
PA3 50 107 PB15
VSS 51 106 PB14
VDD 52 105 PB13
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
PA4
PA5
PA6
PA7
PC4
PC5
VDD
VSS
PB0
PB1
PB2
PI15
PJ0
PJ1
PJ2
PJ3
PJ4
PF11
PF12
VSS
VDD
PF13
PF14
PF15
PG0
PG1
PE7
PE8
PE9
VSS
VDD
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VCAP
VSS
VDD
PJ5
PH6
PH7
PH8
PH9
PH10
PH11
PH12
VDD
PB12
PF7
om
DS12117 Rev 7 61/356
STM32H753xI Pin descriptions
102
Figure 11. TFBGA240+25 ballout
1. The above figure shows the package top view.
MSv41911V2
VSS PI6 PI5 PI4 PB5 VDD
LDO VCAP PK5 PG10 PG9 PD5 PD4 PC10 PA15 PI1 PI0 VSS
VBAT VSS PI7 PE1 PB6 VSS PB4 PK4 PG11 PJ15 PD6 PD3 PC11 PA14 PI2 PH15 PH14
PC15-
OSC32_
OUT
PE2 PE0 PB7 PB3 PK6 PK3 PG12 VSS PD7 PC12 VSS PI3 PA13 VSS VDD
LDO
PE5 PE4 PE3 PB9 PB8 PG15 PK7 PG14 PG13 PJ14 PJ12 PD2 PD0 PA10 PA9 PH13 VCAP
NC PI9 PC13 PI8 PE6 VDD PDR_
ON
BOO
T0 VDD PJ13 VDD PD1 PC8 PC9 PA8 PA12 PA11
NC NC PI10 PI11 VDD PC7 PC6 PG8 PG7 VDD33
USB
PF2 NC PF1 PF0 VDD VSS VSS VSS VSS VSS VDD PG5 PG6 VSS VDD50
USB
PI12 PI13 PI14 PF3 VDD VDD PG4 PG3 PG2 PK2
PH0-
OSC_IN VSS PF5 PF4 VDD PK0 PK1 VSS VSS
NRST PF6 PF7 PF8 VDD VDD PJ11 VSS NC NC
VDDA PC0 PF10 PF9 VDD VDD PJ10 VSS NC NC
VREF+ PC1 PC2 PC3 VDD VDD PJ9 VSS NC NC
VREF- PH2 PA2 PA1 PA0 PJ0 VDD VDD PE10 VDD VDD VDD PJ8 PJ7 PJ6 VSS NC
VSSA PH3 PH4 PH5 PI15 PJ1 PF13 PF14 PE9 PE11 PB10 PB11 PH10 PH11 PD15 PD14 VDD
PC2_C PC3_C PA6 VSS PA7 PB2 PF12 VSS PF15 PE12 PE15 PJ5 PH9 PH12 PD11 PD12 PD13
PA0_C PA1_C PA5 PC4 PB1 PJ2 PF11 PG0 PE8 PE13 PH6 VSS PH8 PB12 PB15 PD10 PD9
VSS PA3 PA4 PC5 PB0 PJ3 PJ4 PG1 PE7 PE14 VCAP VDD
LDO PH7 PB13 PB14 PD8 VSS
PC14-
OSC32_
IN
VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS
PH0-
OSC_
OUT
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
1234567891011121314151617
Pin descriptions STM32H753xI
62/356 DS12117 Rev 7
Table 7. Legend/abbreviations used in the pinout table
Name Abbreviation Definition
Pin name Unless otherwise specified in brackets below the pin name, the pin function during
and after reset is the same as the actual pin name
Pin type
S Supply pin
I Input only pin
I/O Input / output pin
ANA Analog-only Input
I/O structure
FT 5 V tolerant I/O
TT 3.3 V tolerant I/O
B Dedicated BOOT0 pin
RST Bidirectional reset pin with embedded weak pull-up resistor
Option for TT and FT I/Os
_f I2C FM+ option
_a analog option (supplied by VDDA)
_u USB option (supplied by VDD33USB)
_h High-speed low-voltage I/O
Notes Unless otherwise specified by a note, all I/Os are set as floating inputs during and
after reset.
Pin functions
Alternate
functions Functions selected through GPIOx_AFR registers
Additional
functions Functions directly selected/enabled through peripheral registers
DS12117 Rev 7 63/356
STM32H753xI Pin descriptions
102
Table 8. Pin/ball definition
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
1 A3 1 A2 A2 1 1 C3 PE2 I/O FT_h -
TRACECLK, SAI1_CK1,
SPI4_SCK,
SAI1_MCLK_A,
SAI4_MCLK_A,
QUADSPI_BK1_IO2,
SAI4_CK1,
ETH_MII_TXD3,
FMC_A23, EVENTOUT
-
2 B3 2 B2 A1 2 2 D3 PE3 I/O FT_h -
TRACED0, TIM15_BKIN,
SAI1_SD_B, SAI4_SD_B,
FMC_A19, EVENTOUT
-
3 C3 3 A1 B1 3 3 D2 PE4 I/O FT_h -
TRACED1, SAI1_D2,
DFSDM1_DATIN3,
TIM15_CH1N,
SPI4_NSS, SAI1_FS_A,
SAI4_FS_A, SAI4_D2,
FMC_A20, DCMI_D4,
LCD_B0, EVENTOUT
-
4 D3 4 C3 B2 4 4 D1 PE5 I/O FT_h -
TRACED2, SAI1_CK2,
DFSDM1_CKIN3,
TIM15_CH1, SPI4_MISO,
SAI1_SCK_A,
SAI4_SCK_A, SAI4_CK2,
FMC_A21, DCMI_D6,
LCD_G0, EVENTOUT
-
5 E3 5 C2 B3 5 5 E5 PE6 I/O FT_h -
TRACED3, TIM1_BKIN2,
SAI1_D1, TIM15_CH2,
SPI4_MOSI, SAI1_SD_A,
SAI4_SD_A, SAI4_D1,
SAI2_MCLK_B,
TIM1_BKIN2_COMP12,
FMC_A22, DCMI_D7,
LCD_G1, EVENTOUT
-
- - - M4 H10 - - A1 VSS S - - - -
-- -A3- - - - VDD S -- - -
6 B2 6 E3 C1 6 6 B1 VBAT S - - - -
- - - - J6 - - B2 VSS S - - - -
- - - - D2 7 7 E4 PI8 I/O FT - EVENTOUT RTC_TAMP2/
WKUP3
7 A2 7 D3 D1 8 8 E3 PC13 I/O FT - EVENTOUT
RTC_TAMP1/
RTC_TS/
WKUP2
- - - - J7 - - B6 VSS S - - - -
Pin descriptions STM32H753xI
64/356 DS12117 Rev 7
8 A1 8 C1 E1 9 9 C2
PC14-
OSC32_
IN
(OSC32_
IN)(1)
I/O FT - EVENTOUT OSC32_IN
9 B1 9 B1 F1 10 10 C1
PC15-
OSC32_
OUT
(OSC32_
OUT)(1)
I/O FT - EVENTOUT OSC32_
OUT
- - - - D3 11 11 E2 PI9 I/O FT_h -
UART4_RX,
FDCAN1_RX, FMC_D30,
LCD_VSYNC,
EVENTOUT
-
- - - - E3 12 12 F3 PI10 I/O FT_h -
FDCAN1_RXFD_MODE,
ETH_MII_RX_ER,
FMC_D31, LCD_HSYNC,
EVENTOUT
- - - E1 E4 13 13 F4 PI11 I/O FT -
LCD_G6,
OTG_HS_ULPI_DIR,
EVENTOUT
WKUP4
- C2 - D2 F2 14 14 A17 VSS S - - - -
- D2 - D1 F3 15 15 E6 VDD S - - - -
-- - - - - -E1
(2) NC - - - - -
-- - - - - -F1
(3) NC - - - - -
-- - - - - -G2
(4) NC - - - - -
- - 10 F3 E2 16 16 G4 PF0 I/O FT_f - I2C2_SDA, FMC_A0,
EVENTOUT -
- - 11 E4 H3 17 17 G3 PF1 I/O FT_f - I2C2_SCL, FMC_A1,
EVENTOUT -
- - 12 F4 H2 18 18 G1 PF2 I/O FT - I2C2_SMBA, FMC_A2,
EVENTOUT -
- - - F2 - - 19 H1 PI12 I/O FT - LCD_HSYNC,
EVENTOUT -
- - - F1 - - 20 H2 PI13 I/O FT - LCD_VSYNC,
EVENTOUT -
- - - - - - 21 H3 PI14 I/O FT_h - LCD_CLK, EVENTOUT -
- - 13 E5 J2 19 22 H4 PF3 I/O FT_
ha - FMC_A3, EVENTOUT ADC3_INP5
Table 8. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
DS12117 Rev 7 65/356
STM32H753xI Pin descriptions
102
- - 14 G3 J3 20 23 J5 PF4 I/O FT_
ha - FMC_A4, EVENTOUT ADC3_INN5,
ADC3_INP9
- - 15 F5 K3 21 24 J4 PF5 I/O FT_
ha - FMC_A5, EVENTOUT ADC3_INP4
10 - 16 B10 G2 22 25 C10 VSS S - - - -
11 - 17 G1 G3 23 26 E9 VDD S - - - -
- - 18 G4 K2 24 27 K2 PF6 I/O FT_
ha -
TIM16_CH1, SPI5_NSS,
SAI1_SD_B, UART7_RX,
SAI4_SD_B,
QUADSPI_BK1_IO3,
EVENTOUT
ADC3_INN4,
ADC3_INP8
- - 19 F6 K1 25 28 K3 PF7 I/O FT_
ha -
TIM17_CH1, SPI5_SCK,
SAI1_MCLK_B,
UART7_TX,
SAI4_MCLK_B,
QUADSPI_BK1_IO2,
EVENTOUT
ADC3_INP3
- - 20 H4 L3 26 29 K4 PF8 I/O FT_
ha -
TIM16_CH1N,
SPI5_MISO,
SAI1_SCK_B,
UART7_RTS/UART7_DE
, SAI4_SCK_B,
TIM13_CH1,
QUADSPI_BK1_IO0,
EVENTOUT
ADC3_INN3,
ADC3_INP7
- - 21 G5 L2 27 30 L4 PF9 I/O FT_
ha -
TIM17_CH1N,
SPI5_MOSI, SAI1_FS_B,
UART7_CTS,
SAI4_FS_B, TIM14_CH1,
QUADSPI_BK1_IO1,
EVENTOUT
ADC3_INP2
- - 22 H3 L1 28 31 L3 PF10 I/O FT_
ha -
TIM16_BKIN, SAI1_D3,
QUADSPI_CLK,
SAI4_D3, DCMI_D11,
LCD_DE, EVENTOUT
ADC3_INN2,
ADC3_INP6
12 C1 23 H1 G1 29 32 J2
PH0-
OSC_IN
(PH0)
I/O FT - EVENTOUT OSC_IN
13 D1 24 H2 H1 30 33 J1
PH1-
OSC_OUT
(PH1)
I/O FT - EVENTOUT OSC_OUT
14 E1 25 G6 J1 31 34 K1 NRST I/O RST - - -
Table 8. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
Pin descriptions STM32H753xI
66/356 DS12117 Rev 7
15 F1 26 J1 M2 32 35 L2 PC0 I/O FT_a -
DFSDM1_CKIN0,
DFSDM1_DATIN4,
SAI2_FS_B,
OTG_HS_ULPI_STP,
FMC_SDNWE, LCD_R5,
EVENTOUT
ADC123_
INP10
16 F2 27 J2 M3 33 36 M2 PC1 I/O FT_
ha -
TRACED0, SAI1_D1,
DFSDM1_DATIN0,
DFSDM1_CKIN4,
SPI2_MOSI/I2S2_SDO,
SAI1_SD_A, SAI4_SD_A,
SDMMC2_CK, SAI4_D1,
ETH_MDC,
MDIOS_MDC,
EVENTOUT
ADC123_
INN10,
ADC123_
INP11,
RTC_TAMP3/W
KUP5
-- - - - - -M3
(5) PC2 I/O FT_a -
CDSLEEP,
DFSDM1_CKIN1,
SPI2_MISO/I2S2_SDI,
DFSDM1_CKOUT,
OTG_HS_ULPI_DIR,
ETH_MII_TXD2,
FMC_SDNE0,
EVENTOUT
ADC123_
INN11,
ADC123_
INP12
17
(6) E2(6) 28(6) K2(6) M4(6) 34(6) 37(6) R1(5) PC2_C ANA TT_a - ADC3_INN1,
ADC3_INP0
-- - - - - -M4
(5) PC3 I/O FT_a - CSLEEP,
DFSDM1_DATIN1,
SPI2_MOSI/I2S2_SDO,
OTG_HS_ULPI_NXT,
ETH_MII_TX_CLK,
FMC_SDCKE0,
EVENTOUT
ADC12_INN12,
ADC12_INP13
18
(6) F3(6) 29(6) K1(6) M5(6) 35(6) 38(6) R2(5) PC3_C ANA TT_a - ADC3_INP1
- F5 30 - G3 36 39 E11 VDD S - - - -
- E6 - B3 J10 - - C13 VSS S - - - -
19 G1 31 J3 M1 37 40 P1 VSSA S - - - -
- - - - N1 - - N1 VREF- S - - - -
20 -(7) 32 L2 P1 38 41 M1 VREF+ S - - - -
21 H1 33 L1 R1 39 42 L1 VDDA S - - - -
Table 8. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
DS12117 Rev 7 67/356
STM32H753xI Pin descriptions
102
22 G2 34 J5 N3 40 43 N5(5) PA0 I/O FT_a - TIM2_CH1/TIM2_ETR,
TIM5_CH1, TIM8_ETR,
TIM15_BKIN,
USART2_CTS/USART2_
NSS, UART4_TX,
SDMMC2_CMD,
SAI2_SD_B,
ETH_MII_CRS,
EVENTOUT
ADC1_INP16,
WKUP0
-- - - - - -T1
(5) PA0_C ANA TT_a - ADC12_INN1,
ADC12_INP0
23 H2 35 K4 N2 41 44 N4(5) PA1 I/O FT_
ha -TIM2_CH2, TIM5_CH2,
LPTIM3_OUT,
TIM15_CH1N,
USART2_RTS/USART2_
DE, UART4_RX,
QUADSPI_BK1_IO3,
SAI2_MCLK_B,
ETH_MII_RX_CLK/ETH_
RMII_REF_CLK,
LCD_R2, EVENTOUT
ADC1_INN16,
ADC1_INP17
-- - - - - -T2
(5) PA1_C ANA TT_a - ADC12_INP1
24 J2 36 N1 P2 42 45 N3 PA2 I/O FT_a -
TIM2_CH3, TIM5_CH3,
LPTIM4_OUT,
TIM15_CH1,
USART2_TX,
SAI2_SCK_B,
ETH_MDIO,
MDIOS_MDIO, LCD_R1,
EVENTOUT
ADC12_INP14,
WKUP1
- - - N2F44346 N2 PH2 I/O
FT_
ha -
LPTIM1_IN2,
QUADSPI_BK2_IO0,
SAI2_SCK_B,
ETH_MII_CRS,
FMC_SDCKE0, LCD_R0,
EVENTOUT
ADC3_INP13
-K1 - M1 - - - F5 VDD S - - - -
- J1 - M7 J8 - - C16 VSS S - - - -
-- -M3G44447P2 PH3 I/O
FT_
ha -
QUADSPI_BK2_IO1,
SAI2_MCLK_B,
ETH_MII_COL,
FMC_SDNE0, LCD_R1,
EVENTOUT
ADC3_INN13,
ADC3_INP14
- - - K3H44548 P3 PH4 I/OFT_fa-
I2C2_SCL, LCD_G5,
OTG_HS_ULPI_NXT,
LCD_G4, EVENTOUT
ADC3_INN14,
ADC3_INP15
-- -L3J44649P4 PH5 I/OFT_fa-
I2C2_SDA, SPI5_NSS,
FMC_SDNWE,
EVENTOUT
ADC3_INN15,
ADC3_INP16
Table 8. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
Pin descriptions STM32H753xI
68/356 DS12117 Rev 7
25 K2 37 N3 R2 47 50 U2 PA3 I/O FT_
ha -
TIM2_CH4, TIM5_CH4,
LPTIM5_OUT,
TIM15_CH2,
USART2_RX, LCD_B2,
OTG_HS_ULPI_D0,
ETH_MII_COL, LCD_B5,
EVENTOUT
ADC12_INP15
26 - 38 G2 K6 - 51 F2(4) VSS S - - - -
- - - - L4 48 - - VSS S - - - -
27 - 39 - K4 49 52 G5 VDD S - - - -
28 G3 40 H6 N4 50 53 U3 PA4 I/O TT_a -
D1PWREN, TIM5_ETR,
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
USART2_CK, SPI6_NSS,
OTG_HS_SOF,
DCMI_HSYNC,
LCD_VSYNC,
EVENTOUT
ADC12_INP18,
DAC1_OUT1
29 H3 41 L4 P4 51 54 T3 PA5 I/O TT_
ha -
D2PWREN,
TIM2_CH1/TIM2_ETR,
TIM8_CH1N,
SPI1_SCK/I2S1_CK,
SPI6_SCK,
OTG_HS_ULPI_CK,
LCD_R4, EVENTOUT
ADC12_INN18,
ADC12_INP19,
DAC1_OUT2
30 J3 42 K5 P3 52 55 R3 PA6 I/O FT_a -
TIM1_BKIN, TIM3_CH1,
TIM8_BKIN,
SPI1_MISO/I2S1_SDI,
SPI6_MISO, TIM13_CH1,
TIM8_BKIN_COMP12,
MDIOS_MDC,
TIM1_BKIN_COMP12,
DCMI_PIXCLK, LCD_G2,
EVENTOUT
ADC12_INP3
31 K3 43 J6 R3 53 56 R5 PA7 I/O TT_a -
TIM1_CH1N, TIM3_CH2,
TIM8_CH1N,
SPI1_MOSI/I2S1_SDO,
SPI6_MOSI, TIM14_CH1,
ETH_MII_RX_DV/ETH_R
MII_CRS_DV,
FMC_SDNWE,
EVENTOUT
ADC12_INN3,
ADC12_INP7,
OPAMP1_VINM
Table 8. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
DS12117 Rev 7 69/356
STM32H753xI Pin descriptions
102
32 G4 44 K6 N5 54 57 T4 PC4 I/O TT_a -
DFSDM1_CKIN2,
I2S1_MCK,
SPDIFRX1_IN3,
ETH_MII_RXD0/ETH_R
MII_RXD0, FMC_SDNE0,
EVENTOUT
ADC12_INP4,
OPAMP1_
VOUT,
COMP1_INM
33 H4 45 N5 P5 55 58 U4 PC5 I/O TT_a -
SAI1_D3,
DFSDM1_DATIN2,
SPDIFRX1_IN4,
SAI4_D3,
ETH_MII_RXD1/ETH_R
MII_RXD1,
FMC_SDCKE0,
COMP1_OUT,
EVENTOUT
ADC12_INN4,
ADC12_INP8,
OPAMP1_
VINM
-- -N4- -59G13VDD S -- - -
- - - H12 J9 - 60 R4 VSS S - - - -
34 J4 46 M5 R5 56 61 U5 PB0 I/O FT_a -
TIM1_CH2N, TIM3_CH3,
TIM8_CH2N,
DFSDM1_CKOUT,
UART4_CTS, LCD_R3,
OTG_HS_ULPI_D1,
ETH_MII_RXD2,
LCD_G1, EVENTOUT
ADC12_INN5,
ADC12_INP9,
OPAMP1_VINP,
COMP1_INP
35 K4 47 L5 R4 57 62 T5 PB1 I/O TT_u -
TIM1_CH3N, TIM3_CH4,
TIM8_CH3N,
DFSDM1_DATIN1,
LCD_R6,
OTG_HS_ULPI_D2,
ETH_MII_RXD3,
LCD_G0, EVENTOUT
ADC12_INP5,
COMP1_INM
36 G5 48 L6 M6 58 63 R6 PB2 I/O FT_
ha -
RTC_OUT, SAI1_D1,
DFSDM1_CKIN1,
SAI1_SD_A,
SPI3_MOSI/I2S3_SDO,
SAI4_SD_A,
QUADSPI_CLK,
SAI4_D1, EVENTOUT
COMP1_INP
-- - - - -64P5 PI15I/OFT-LCD_G2, LCD_R0,
EVENTOUT -
-- -J4- -65N6 PJ0 I/OFT- LCD_R7, LCD_R1,
EVENTOUT -
- - - H5 - - 66 P6 PJ1 I/O FT - LCD_R2, EVENTOUT -
- - - - - - 67 T6 PJ2 I/O FT - LCD_R3, EVENTOUT -
Table 8. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
Pin descriptions STM32H753xI
70/356 DS12117 Rev 7
- - - - - - 68 U6 PJ3 I/O FT - LCD_R4, EVENTOUT -
- - - - - - 69 U7 PJ4 I/O FT - LCD_R5, EVENTOUT -
- - 49 M6 R6 59 70 T7 PF11 I/O FT_a -
SPI5_MOSI, SAI2_SD_B,
FMC_SDNRAS,
DCMI_D12, EVENTOUT
ADC1_INP2
- - 50 N6 P6 60 71 R7 PF12 I/O FT_
ha - FMC_A6, EVENTOUT ADC1_INN2,
ADC1_INP6
- - 51 M11 M8 61 72 J3 VSS S - - - -
- - 52 - N86273 H5 VDD S - - - -
- - 53 G7 N6 63 74 P7 PF13 I/O FT_
ha -
DFSDM1_DATIN6,
I2C4_SMBA, FMC_A7,
EVENTOUT
ADC2_INP2
- - 54 H7 R7 64 75 P8 PF14 I/O FT_
fha -
DFSDM1_CKIN6,
I2C4_SCL, FMC_A8,
EVENTOUT
ADC2_INN2,
ADC2_INP6
- - 55 J7 P7 65 76 R9 PF15 I/O FT_fh - I2C4_SDA, FMC_A9,
EVENTOUT -
- - 56 K7 N7 66 77 T8 PG0 I/O FT_h - FMC_A10, EVENTOUT -
- - - M2 F6 - - J16 VSS S - - - -
- - - A10 - - - H13 VDD S - - - -
- - 57 L7 M7 67 78 U8 PG1 I/O TT_h - FMC_A11, EVENTOUT OPAMP2_
VINM
37 H5 58 G8 R8 68 79 U9 PE7 I/O TT_
ha -
TIM1_ETR,
DFSDM1_DATIN2,
UART7_RX,
QUADSPI_BK2_IO0,
FMC_D4/FMC_DA4,
EVENTOUT
OPAMP2_
VOUT,
COMP2_INM
38 J5 59 H8 P8 69 80 T9 PE8 I/O TT_
ha -
TIM1_CH1N,
DFSDM1_CKIN2,
UART7_TX,
QUADSPI_BK2_IO1,
FMC_D5/FMC_DA5,
COMP2_OUT,
EVENTOUT
OPAMP2_
VINM
39 K5 60 J8 P9 70 81 P9 PE9 I/O TT_
ha -
TIM1_CH1,
DFSDM1_CKOUT,
UART7_RTS/UART7_DE
, QUADSPI_BK2_IO2,
FMC_D6/FMC_DA6,
EVENTOUT
OPAMP2_VINP,
COMP2_INP
Table 8. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
DS12117 Rev 7 71/356
STM32H753xI Pin descriptions
102
- - 61 C12 M9 71 82 J17 VSS S - - - -
- - 62C13N97283J13 VDD S - - - -
40 G6 63 M8 R9 73 84 N9 PE10 I/O FT_
ha -
TIM1_CH2N,
DFSDM1_DATIN4,
UART7_CTS,
QUADSPI_BK2_IO3,
FMC_D7/FMC_DA7,
EVENTOUT
COMP2_INM
41 H6 64 N8 P10 74 85 P10 PE11 I/O FT_
ha -
TIM1_CH2,
DFSDM1_CKIN4,
SPI4_NSS, SAI2_SD_B,
FMC_D8/FMC_DA8,
LCD_G3, EVENTOUT
COMP2_INP
42 J6 65 L8 R10 75 86 R10 PE12 I/O FT_h -
TIM1_CH3N,
DFSDM1_DATIN5,
SPI4_SCK,
SAI2_SCK_B,
FMC_D9/FMC_DA9,
COMP1_OUT, LCD_B4,
EVENTOUT
-
43 K6 66 K8 N11 76 87 T10 PE13 I/O FT_h -
TIM1_CH3,
DFSDM1_CKIN5,
SPI4_MISO, SAI2_FS_B,
FMC_D10/FMC_DA10,
COMP2_OUT, LCD_DE,
EVENTOUT
-
- - - L12 F7 - - T12 VSS S - - - -
- - - H13 - - - K13 VDD S - - - -
44 G7 67 J9 P11 77 88 U10 PE14 I/O FT_h -
TIM1_CH4, SPI4_MOSI,
SAI2_MCLK_B,
FMC_D11/FMC_DA11,
LCD_CLK, EVENTOUT
-
45 H7 68 N9 R11 78 89 R11 PE15 I/O FT_h -
TIM1_BKIN,
FMC_D12/FMC_DA12,
TIM1_BKIN_COMP12/
COMP_TIM1_BKIN,
LCD_R7, EVENTOUT
-
Table 8. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
Pin descriptions STM32H753xI
72/356 DS12117 Rev 7
46 J7 69 L9 R12 79 90 P11 PB10 I/O FT_f -
TIM2_CH3,
HRTIM_SCOUT,
LPTIM2_IN1, I2C2_SCL,
SPI2_SCK/I2S2_CK,
DFSDM1_DATIN7,
USART3_TX,
QUADSPI_BK1_NCS,
OTG_HS_ULPI_D3,
ETH_MII_RX_ER,
LCD_G4, EVENTOUT
-
47 K7 70 M9 R13 80 91 P12 PB11 I/O FT_f -
TIM2_CH4,
HRTIM_SCIN,
LPTIM2_ETR,
I2C2_SDA,
DFSDM1_CKIN7,
USART3_RX,
OTG_HS_ULPI_D4,
ETH_MII_TX_EN/ETH_R
MII_TX_EN, LCD_G5,
EVENTOUT
-
48 F8 71 N10 M10 81 92 U11 VCAP S - - - -
49 E4 - - K7 - 93 - VSS S - - - -
- - - M10 - - - U12 VDDLDO
(8) S-- - -
50 - 72 M1 N10 82 94 L13 VDD S - - - -
- - - - - - 95 R12 PJ5 I/O FT - LCD_R6, EVENTOUT -
-- - -M118396T11 PH6 I/OFT-
TIM12_CH1,
I2C2_SMBA, SPI5_SCK,
ETH_MII_RXD2,
FMC_SDNE1, DCMI_D8,
EVENTOUT
-
- - - - N12 84 97 U13 PH7 I/O FT_fa -
I2C3_SCL, SPI5_MISO,
ETH_MII_RXD3,
FMC_SDCKE1,
DCMI_D9, EVENTOUT
-
-- - -M128598T13 PH8 I/O
FT_fh
a-
TIM5_ETR, I2C3_SDA,
FMC_D16,
DCMI_HSYNC, LCD_R2,
EVENTOUT
-
- - - - F8 - - - VSS S - - - -
- - - L13 - - - M13 VDD S - - - -
Table 8. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
DS12117 Rev 7 73/356
STM32H753xI Pin descriptions
102
- - - - M13 86 99 R13 PH9 I/O FT_h -
TIM12_CH2,
I2C3_SMBA, FMC_D17,
DCMI_D0, LCD_R3,
EVENTOUT
-
- - - K9 L13 87 100 P13 PH10 I/O FT_h -
TIM5_CH1, I2C4_SMBA,
FMC_D18, DCMI_D1,
LCD_R4, EVENTOUT
-
- - - L10 L12 88 101 P14 PH11 I/O FT_fh -
TIM5_CH2, I2C4_SCL,
FMC_D19, DCMI_D2,
LCD_R5, EVENTOUT
-
- - - K10 K12 89 102 R14 PH12 I/O FT_fh -
TIM5_CH3, I2C4_SDA,
FMC_D20, DCMI_D3,
LCD_R6, EVENTOUT
-
- - - - H12 90 - N16 VSS S - - - -
- - - N11 J12 91 103 P17 VDD S - - - -
51 K8 73 N12 P12 92 104 T14 PB12 I/O FT_u -
TIM1_BKIN, I2C2_SMBA,
SPI2_NSS/I2S2_WS,
DFSDM1_DATIN1,
USART3_CK,
FDCAN2_RX,
OTG_HS_ULPI_D5,
ETH_MII_TXD0/ETH_RM
II_TXD0, OTG_HS_ID,
TIM1_BKIN_COMP12,
UART5_RX, EVENTOUT
52 J8 74 L11 P13 93 105 U14 PB13 I/O FT_u -
TIM1_CH1N,
LPTIM2_OUT,
SPI2_SCK/I2S2_CK,
DFSDM1_CKIN1,
USART3_CTS/USART3_
NSS, FDCAN2_TX,
OTG_HS_ULPI_D6,
ETH_MII_TXD1/ETH_RM
II_TXD1, UART5_TX,
EVENTOUT
OTG_HS_
VBUS
Table 8. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
Pin descriptions STM32H753xI
74/356 DS12117 Rev 7
53 H10 75 N13 R14 94 106 U15 PB14 I/O FT_u -
TIM1_CH2N,
TIM12_CH1,
TIM8_CH2N,
USART1_TX,
SPI2_MISO/I2S2_SDI,
DFSDM1_DATIN2,
USART3_RTS/
USART3_DE,
UART4_RTS/UART4_DE
, SDMMC2_D0,
OTG_HS_DM,
EVENTOUT
-
54 G10 76 M13 R15 95 107 T15 PB15 I/O FT_u -
RTC_REFIN,
TIM1_CH3N,
TIM12_CH2,
TIM8_CH3N,
USART1_RX,
SPI2_MOSI/I2S2_SDO,
DFSDM1_CKIN2,
UART4_CTS,
SDMMC2_D1,
OTG_HS_DP,
EVENTOUT
-
55 K9 77 M12 P15 96 108 U16 PD8 I/O FT_h -
DFSDM1_CKIN3,
SAI3_SCK_B,
USART3_TX,
SPDIFRX1_IN2,
FMC_D13/FMC_DA13,
EVENTOUT
-
56 J9 78 K11 P14 97 109 T17 PD9 I/O FT_h -
DFSDM1_DATIN3,
SAI3_SD_B,
USART3_RX,
FDCAN2_RXFD_MODE,
FMC_D14/FMC_DA14,
EVENTOUT
-
57 H9 79 K12 N15 98 110 T16 PD10 I/O FT_h -
DFSDM1_CKOUT,
SAI3_FS_B,
USART3_CK,
FDCAN2_TXFD_MODE,
FMC_D15/FMC_DA15,
LCD_B3, EVENTOUT
-
- - - N7 - - - N12 VDD S - - - -
- - - - F9 - - U17 VSS S - - - -
Table 8. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
DS12117 Rev 7 75/356
STM32H753xI Pin descriptions
102
58 G9 80 J10 N14 99 111 R15 PD11 I/O FT_h -
LPTIM2_IN2,
I2C4_SMBA,
USART3_CTS/USART3_
NSS,
QUADSPI_BK1_IO0,
SAI2_SD_A, FMC_A16,
EVENTOUT
-
59 K10 81 K13 N13 100 112 R16 PD12 I/O FT_fh -
LPTIM1_IN1, TIM4_CH1,
LPTIM2_IN1, I2C4_SCL,
USART3_RTS/USART3_
DE, QUADSPI_BK1_IO1,
SAI2_FS_A, FMC_A17,
EVENTOUT
-
60 J10 82 J11 M15 101 113 R17 PD13 I/O FT_fh -
LPTIM1_OUT,
TIM4_CH2, I2C4_SDA,
QUADSPI_BK1_IO3,
SAI2_SCK_A, FMC_A18,
EVENTOUT
-
- - 83 - K8 102 114 - VSS S - - - -
- - 84 - J13 103 115 N11 VDD S - - - -
61 H8 85 J13 M14 104 116 P16 PD14 I/O FT_h -
TIM4_CH3,
SAI3_MCLK_B,
UART8_CTS,
FMC_D0/FMC_DA0,
EVENTOUT
-
62 G8 86 J12 L14 105 117 P15 PD15 I/O FT_h -
TIM4_CH4,
SAI3_MCLK_A,
UART8_RTS/UART8_DE
, FMC_D1/FMC_DA1,
EVENTOUT
-
-- - - - -118N15 PJ6 I/OFT-
TIM8_CH2, LCD_R7,
EVENTOUT -
-- - - - -119N14 PJ7 I/OFT-
TRGIN, TIM8_CH2N,
LCD_G0, EVENTOUT -
-- - - - - -N10VDD S - -
- - - - F10 - - R8 VSS S - -
- - - - - - 120 N13 PJ8 I/O FT -
TIM1_CH3N, TIM8_CH1,
UART8_TX, LCD_G1,
EVENTOUT
-
- - - - - - 121 M14 PJ9 I/O FT -
TIM1_CH3, TIM8_CH1N,
UART8_RX, LCD_G2,
EVENTOUT
-
Table 8. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
Pin descriptions STM32H753xI
76/356 DS12117 Rev 7
- - - - - - 122 L14 PJ10 I/O FT -
TIM1_CH2N, TIM8_CH2,
SPI5_MOSI, LCD_G3,
EVENTOUT
-
- - - - - - 123 K14 PJ11 I/O FT -
TIM1_CH2, TIM8_CH2N,
SPI5_MISO, LCD_G4,
EVENTOUT
-
- - - - - - 124 N8 VDD S - -
- - - - G6 - 125 U1 VSS S - - - -
-- - - - - -
N17
(2) NC - - - - -
-- - - - - -
M16
(2) NC - - - - -
-- - - - - -
M17
(2) NC - - - - -
- - - - - - - K15 VSS S - - - -
- - - - - - - L16(2) NC - - - - -
- - - - - - - L17(2) NC - - - - -
-- - - - - -
K16
(2) NC - - - - -
-- - - - - -
K17
(2) NC - - - - -
- - - - - - - L15 VSS S - - - -
- - - - - - 126 J14 PK0 I/O FT -
TIM1_CH1N, TIM8_CH3,
SPI5_SCK, LCD_G5,
EVENTOUT
-
- - - - - - 127 J15 PK1 I/O FT -
TIM1_CH1, TIM8_CH3N,
SPI5_NSS, LCD_G6,
EVENTOUT
-
- - - - - - 128 H17 PK2 I/O FT -
TIM1_BKIN, TIM8_BKIN,
TIM8_BKIN_COMP12,
TIM1_BKIN_COMP12,
LCD_G7, EVENTOUT
-
- - 87 H9 L15 106 129 H16 PG2 I/O FT_h -
TIM8_BKIN,
TIM8_BKIN_COMP12,
FMC_A12, EVENTOUT
-
- - 88 H10 K15 107 130 H15 PG3 I/O FT_h -
TIM8_BKIN2,
TIM8_BKIN2_COMP12,
FMC_A13, EVENTOUT
-
- - - - G7 - - - VSS S - - - -
Table 8. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
DS12117 Rev 7 77/356
STM32H753xI Pin descriptions
102
-- - - - - -N7 VDD S -- - -
- - 89 F8 K14 108 131 H14 PG4 I/O FT_h -
TIM1_BKIN2,
TIM1_BKIN2_COMP12,
FMC_A14/FMC_BA0,
EVENTOUT
-
- - 90 H11 K13 109 132 G14 PG5 I/O FT_h -
TIM1_ETR,
FMC_A15/FMC_BA1,
EVENTOUT
-
- - 91 G9 J15 110 133 G15 PG6 I/O FT_h -
TIM17_BKIN,
HRTIM_CHE1,
QUADSPI_BK1_NCS,
FMC_NE3, DCMI_D12,
LCD_R7, EVENTOUT
-
- - 92 G10 J14 111 134 F16 PG7 I/O FT_h -
HRTIM_CHE2,
SAI1_MCLK_A,
USART6_CK, FMC_INT,
DCMI_D13, LCD_CLK,
EVENTOUT
-
- - 93 G11 H14 112 135 F15 PG8 I/O FT_h -
TIM8_ETR, SPI6_NSS,
USART6_RTS/USART6_
DE, SPDIFRX1_IN3,
ETH_PPS_OUT,
FMC_SDCLK, LCD_G7,
EVENTOUT
-
- - 94 - G12 113 136 G16 VSS S - - - -
- - - G12 - - - G17 VDD50
USB S-- - -
- F6 95 G13 H13 114 137 F17 VDD33
USB S-- - -
-- - - - - -M5 VDD S -- - -
63 F10 96 F9 H15 115 138 F14 PC6 I/O FT_h -
HRTIM_CHA1,
TIM3_CH1, TIM8_CH1,
DFSDM1_CKIN3,
I2S2_MCK, USART6_TX,
SDMMC1_D0DIR,
FMC_NWAIT,
SDMMC2_D6,
SDMMC1_D6, DCMI_D0,
LCD_HSYNC,
EVENTOUT
SWPMI_IO
Table 8. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
Pin descriptions STM32H753xI
78/356 DS12117 Rev 7
64 E10 97 F10 G15 116 139 F13 PC7 I/O FT_h -
TRGIO, HRTIM_CHA2,
TIM3_CH2, TIM8_CH2,
DFSDM1_DATIN3,
I2S3_MCK,
USART6_RX,
SDMMC1_D123DIR,
FMC_NE1,
SDMMC2_D7,
SWPMI_TX,
SDMMC1_D7, DCMI_D1,
LCD_G6, EVENTOUT
-
65 F9 98 F12 G14 117 140 E13 PC8 I/O FT_h -
TRACED1,
HRTIM_CHB1,
TIM3_CH3, TIM8_CH3,
USART6_CK,
UART5_RTS/UART5_DE
, FMC_NE2/FMC_NCE,
SWPMI_RX,
SDMMC1_D0, DCMI_D2,
EVENTOUT
-
66 E9 99 F11 F14 118 141 E14 PC9 I/O FT_fh -
MCO2, TIM3_CH4,
TIM8_CH4, I2C3_SDA,
I2S_CKIN, UART5_CTS,
QUADSPI_BK1_IO0,
LCD_G3,
SWPMI_SUSPEND,
SDMMC1_D1, DCMI_D3,
LCD_B2, EVENTOUT
-
- - - - G8 - - - VSS S - - -
-- - - - - -L5 VDD S -- -
67 D9 100 E12 F15 119 142 E15 PA8 I/O FT_
fha -
MCO1, TIM1_CH1,
HRTIM_CHB2,
TIM8_BKIN2, I2C3_SCL,
USART1_CK,
OTG_FS_SOF,
UART7_RX,
TIM8_BKIN2_COMP12,
LCD_B3, LCD_R6,
EVENTOUT
-
Table 8. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
DS12117 Rev 7 79/356
STM32H753xI Pin descriptions
102
68 C9 101 E11 E15 120 143 D15 PA9 I/O FT_u -
TIM1_CH2,
HRTIM_CHC1,
LPUART1_TX,
I2C3_SMBA,
SPI2_SCK/I2S2_CK,
USART1_TX,
FDCAN1_RXFD_MODE,
DCMI_D0, LCD_R5,
EVENTOUT
OTG_FS_VBUS
69 D10 102 E10 D15 121 144 D14 PA10 I/O FT_u -
TIM1_CH3,
HRTIM_CHC2,
LPUART1_RX,
USART1_RX,
FDCAN1_TXFD_MODE,
OTG_FS_ID,
MDIOS_MDIO, LCD_B4,
DCMI_D1, LCD_B1,
EVENTOUT
-
70 C10 103 F13 C15 122 145 E17 PA11 I/O FT_u -
TIM1_CH4,
HRTIM_CHD1,
LPUART1_CTS,
SPI2_NSS/I2S2_WS,
UART4_RX,
USART1_CTS/USART1_
NSS, FDCAN1_RX,
OTG_FS_DM, LCD_R4,
EVENTOUT
-
71 B10 104 E13 B15 123 146 E16 PA12 I/O FT_u -
TIM1_ETR,
HRTIM_CHD2,
LPUART1_RTS/
LPUART1_DE,
SPI2_SCK/I2S2_CK,
UART4_TX,
USART1_RTS/USART1_
DE, SAI2_FS_B,
FDCAN1_TX,
OTG_FS_DP, LCD_R5,
EVENTOUT
-
72 A10 105 D11 A15 124 147 C15
PA13
(JTMS/SW
DIO)
I/O FT - JTMS-SWDIO,
EVENTOUT -
73 E7 106 D13 F13 125 148 D17 VCAP S - - - -
74 E5 107 - F12 126 149 - VSS S - - - -
- - - D12 - - - C17 VDDLDO
(8) -- - -
75 - 108 - G13 127 150 K5 VDD S - - - -
Table 8. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
Pin descriptions STM32H753xI
80/356 DS12117 Rev 7
- - - - E12 128 151 D16 PH13 I/O FT_h -
TIM8_CH1N, UART4_TX,
FDCAN1_TX, FMC_D21,
LCD_G2, EVENTOUT
-
- - - - E13 129 152 B17 PH14 I/O FT_h -
TIM8_CH2N,
UART4_RX,
FDCAN1_RX, FMC_D22,
DCMI_D4, LCD_G3,
EVENTOUT
-
- - - - D13 130 153 B16 PH15 I/O FT_h -
TIM8_CH3N,
FDCAN1_TXFD_MODE,
FMC_D23, DCMI_D11,
LCD_G4, EVENTOUT
-
- - - A13 E14 131 154 A16 PI0 I/O FT_h -
TIM5_CH4,
SPI2_NSS/I2S2_WS,
FDCAN1_RXFD_MODE,
FMC_D24, DCMI_D13,
LCD_G5, EVENTOUT
-
- - - - G9 - - - VSS S - - - -
- - - B13 D14 132 155 A15 PI1 I/O FT_h -
TIM8_BKIN2,
SPI2_SCK/I2S2_CK,
TIM8_BKIN2_COMP12,
FMC_D25, DCMI_D8,
LCD_G6, EVENTOUT
-
- - - A6 C14 133 156 B15 PI2 I/O FT_h -
TIM8_CH4,
SPI2_MISO/I2S2_SDI,
FMC_D26, DCMI_D9,
LCD_G7, EVENTOUT
-
- - - B7 C13 134 157 C14 PI3 I/O FT_h -
TIM8_ETR,
SPI2_MOSI/I2S2_SDO,
FMC_D27, DCMI_D10,
EVENTOUT
-
- - - - D9 135 - - VSS S - - - -
- - - - C9 136 158 - VDD S - - - -
76 A9 109 B12 A14 137 159 B14
PA14
(JTCK/SW
CLK)
I/O FT - JTCK-SWCLK,
EVENTOUT -
Table 8. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
DS12117 Rev 7 81/356
STM32H753xI Pin descriptions
102
77 A8 110 C11 A13 138 160 A14 PA15
(JTDI) I/O FT -
JTDI,
TIM2_CH1/TIM2_ETR,
HRTIM_FLT1, CEC,
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
SPI6_NSS,
UART4_RTS/UART4_DE
, UART7_TX,
EVENTOUT
-
78 B9 111 A12 B14 139 161 A13 PC10 I/O FT_
ha -
HRTIM_EEV1,
DFSDM1_CKIN5,
SPI3_SCK/I2S3_CK,
USART3_TX,
UART4_TX,
QUADSPI_BK1_IO1,
SDMMC1_D2, DCMI_D8,
LCD_R2, EVENTOUT
-
79 B8 112 B11 B13 140 162 B13 PC11 I/O FT_h -
HRTIM_FLT2,
DFSDM1_DATIN5,
SPI3_MISO/I2S3_SDI,
USART3_RX,
UART4_RX,
QUADSPI_BK2_NCS,
SDMMC1_D3, DCMI_D4,
EVENTOUT
-
80 C8 113 A11 A12 141 163 C12 PC12 I/O FT_h -
TRACED3,
HRTIM_EEV2,
SPI3_MOSI/I2S3_SDO,
USART3_CK,
UART5_TX,
SDMMC1_CK, DCMI_D9,
EVENTOUT
-
- - - - G10 - - - VSS S - - - -
81 D8 114 D10 B12 142 164 D13 PD0 I/O FT_h -
DFSDM1_CKIN6,
SAI3_SCK_A,
UART4_RX,
FDCAN1_RX,
FMC_D2/FMC_DA2,
EVENTOUT
-
82 E8 115 C10 C12 143 165 E12 PD1 I/O FT_h -
DFSDM1_DATIN6,
SAI3_SD_A, UART4_TX,
FDCAN1_TX,
FMC_D3/FMC_DA3,
EVENTOUT
-
Table 8. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
Pin descriptions STM32H753xI
82/356 DS12117 Rev 7
83 B7 116 E9 D12 144 166 D12 PD2 I/O FT_h -
TRACED2, TIM3_ETR,
UART5_RX,
SDMMC1_CMD,
DCMI_D11, EVENTOUT
-
84 C7 117 D9 D11 145 167 B12 PD3 I/O FT_h -
DFSDM1_CKOUT,
SPI2_SCK/I2S2_CK,
USART2_CTS/USART2_
NSS, FMC_CLK,
DCMI_D5, LCD_G7,
EVENTOUT
-
85 D7 118 C9 D10 146 168 A12 PD4 I/O FT_h -
HRTIM_FLT3,
SAI3_FS_A,
USART2_RTS/USART2_
DE,
FDCAN1_RXFD_MODE,
FMC_NOE, EVENTOUT
-
86 B6 119 A9 C11 147 169 A11 PD5 I/O FT_h -
HRTIM_EEV3,
USART2_TX,
FDCAN1_TXFD_MODE,
FMC_NWE, EVENTOUT
-
- - 120 - D8 148 170 - VSS S - - - -
- - 121 - C8 149 171 - VDD S - - - -
87 C6 122 B9 B11 150 172 B11 PD6 I/O FT_h -
SAI1_D1,
DFSDM1_CKIN4,
DFSDM1_DATIN1,
SPI3_MOSI/I2S3_SDO,
SAI1_SD_A,
USART2_RX,
SAI4_SD_A,
FDCAN2_RXFD_MODE,
SAI4_D1, SDMMC2_CK,
FMC_NWAIT,
DCMI_D10, LCD_B2,
EVENTOUT
-
88 D6 123 D8 A11 151 173 C11 PD7 I/O FT_h -
DFSDM1_DATIN4,
SPI1_MOSI/I2S1_SDO,
DFSDM1_CKIN1,
USART2_CK,
SPDIFRX1_IN1,
SDMMC2_CMD,
FMC_NE1, EVENTOUT
-
- - - - - - 174 D11 PJ12 I/O FT - TRGOUT, LCD_G3,
LCD_B0, EVENTOUT -
- - - - - - 175 E10 PJ13 I/O FT - LCD_B4, LCD_B1,
EVENTOUT -
Table 8. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
DS12117 Rev 7 83/356
STM32H753xI Pin descriptions
102
- - - - - - 176 D10 PJ14 I/O FT - LCD_B2, EVENTOUT -
- - - - - - 177 B10 PJ15 I/O FT - LCD_B3, EVENTOUT -
- - - - H6 - - - VSS S - - - -
-- -A7- - - - VDD S -- - -
- - 124 C8 C10 152 178 A10 PG9 I/O FT_h -
SPI1_MISO/I2S1_SDI,
USART6_RX,
SPDIFRX1_IN4,
QUADSPI_BK2_IO2,
SAI2_FS_B,
FMC_NE2/FMC_NCE,
DCMI_VSYNC,
EVENTOUT
-
- - 125 A8 B10 153 179 A9 PG10 I/O FT_h -
HRTIM_FLT5,
SPI1_NSS/I2S1_WS,
LCD_G3, SAI2_SD_B,
FMC_NE3, DCMI_D2,
LCD_B2, EVENTOUT
-
- - 126 B8 B9 154 180 B9 PG11 I/O FT_h -
LPTIM1_IN2,
HRTIM_EEV4,
SPI1_SCK/I2S1_CK,
SPDIFRX1_IN1,
SDMMC2_D2,
ETH_MII_TX_EN/ETH_R
MII_TX_EN, DCMI_D3,
LCD_B3, EVENTOUT
-
- - 127 E8 B8 155 181 C9 PG12 I/O FT_h -
LPTIM1_IN1,
HRTIM_EEV5,
SPI6_MISO,
USART6_RTS/USART6_
DE, SPDIFRX1_IN2,
LCD_B4,
ETH_MII_TXD1/ETH_RM
II_TXD1, FMC_NE4,
LCD_B1, EVENTOUT
-
- - 128 D7 A8 156 182 D9 PG13 I/O FT_h -
TRACED0,
LPTIM1_OUT,
HRTIM_EEV10,
SPI6_SCK,
USART6_CTS/USART6_
NSS,
ETH_MII_TXD0/ETH_RM
II_TXD0, FMC_A24,
LCD_R0, EVENTOUT
-
Table 8. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
Pin descriptions STM32H753xI
84/356 DS12117 Rev 7
- - 129 C7 A7 157 183 D8 PG14 I/O FT_h -
TRACED1,
LPTIM1_ETR,
SPI6_MOSI,
USART6_TX,
QUADSPI_BK2_IO3,
ETH_MII_TXD1/ETH_RM
II_TXD1, FMC_A25,
LCD_B0, EVENTOUT
-
- - 130 - D7 158 184 - VSS S - - - -
- - 131 - C7 159 185 - VDD S - - - -
- - - - - - 186 C8 PK3 I/O FT - LCD_B4, EVENTOUT -
- - - - - - 187 B8 PK4 I/O FT - LCD_B5, EVENTOUT -
- - - - - - 188 A8 PK5 I/O FT - LCD_B6, EVENTOUT -
- - - - - - 189 C7 PK6 I/O FT - LCD_B7, EVENTOUT -
- - - - - - 190 D7 PK7 I/O FT - LCD_DE, EVENTOUT -
- - - - H7 - - - VSS S - - - -
- - 132 E7 B7 160 191 D6 PG15 I/O FT_h -
USART6_CTS/USART6_
NSS, FMC_SDNCAS,
DCMI_D13, EVENTOUT
-
89 A7 133 F7 A10 161 192 C6
PB3(JTDO
/TRACES
WO)
I/O FT -
JTDO/TRACESWO,
TIM2_CH2,
HRTIM_FLT4,
SPI1_SCK/I2S1_CK,
SPI3_SCK/I2S3_CK,
SPI6_SCK,
SDMMC2_D2,
CRS_SYNC, UART7_RX,
EVENTOUT
-
90 A6 134 B6 A9 162 193 B7 PB4(NJTR
ST) I/O FT -
NJTRST, TIM16_BKIN,
TIM3_CH1,
HRTIM_EEV6,
SPI1_MISO/I2S1_SDI,
SPI3_MISO/I2S3_SDI,
SPI2_NSS/I2S2_WS,
SPI6_MISO,
SDMMC2_D3,
UART7_TX, EVENTOUT
-
Table 8. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
DS12117 Rev 7 85/356
STM32H753xI Pin descriptions
102
91 C5 135 C6 A6 163 194 A5 PB5 I/O FT -
TIM17_BKIN, TIM3_CH2,
HRTIM_EEV7,
I2C1_SMBA,
SPI1_MOSI/I2S1_SDO,
I2C4_SMBA,
SPI3_MOSI/I2S3_SDO,
SPI6_MOSI,
FDCAN2_RX,
OTG_HS_ULPI_D7,
ETH_PPS_OUT,
FMC_SDCKE1,
DCMI_D10, UART5_RX,
EVENTOUT
-
- - - - H8 - - - VSS S - - - -
92 B5 136 A5 B6 164 195 B5 PB6 I/O FT_f -
TIM16_CH1N,
TIM4_CH1,
HRTIM_EEV8,
I2C1_SCL, CEC,
I2C4_SCL, USART1_TX,
LPUART1_TX,
FDCAN2_TX,
QUADSPI_BK1_NCS,
DFSDM1_DATIN5,
FMC_SDNE1, DCMI_D5,
UART5_TX, EVENTOUT
-
93 A5 137 D6 B5 165 196 C5 PB7 I/O FT_fa -
TIM17_CH1N,
TIM4_CH2,
HRTIM_EEV9,
I2C1_SDA, I2C4_SDA,
USART1_RX,
LPUART1_RX,
FDCAN2_TXFD_MODE,
DFSDM1_CKIN5,
FMC_NL, DCMI_VSYNC,
EVENTOUT
PVD_IN
94 D5 138 E6 D6 166 197 E8 BOOT0 I B - - VPP
95 B4 139 B5 A5 167 198 D5 PB8 I/O FT_fh -
TIM16_CH1, TIM4_CH3,
DFSDM1_CKIN7,
I2C1_SCL, I2C4_SCL,
SDMMC1_CKIN,
UART4_RX,
FDCAN1_RX,
SDMMC2_D4,
ETH_MII_TXD3,
SDMMC1_D4, DCMI_D6,
LCD_B6, EVENTOUT
-
Table 8. Pin/ball definition (continued)
Pin/ball name
Pin name
(function
after
reset)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
LQFP100
TFBGA100
LQFP144
UFBGA169
UFBGA176+25
LQFP176
LQFP208
TFBGA240 +25
Pin descriptions STM32H753xI
86/356 DS12117 Rev 7
96 A4 140 C5 B4 168 199 D4 PB9 I/O FT_fh -
TIM17_CH1, TIM4_CH4,
DFSDM1_DATIN7,
I2C1_SDA,
SPI2_NSS/I2S2_WS,
I2C4_SDA,
SDMMC1_CDIR,
UART4_TX,
FDCAN1_TX,
SDMMC2_D5,
I2C4_SMBA,
SDMMC1_D5, DCMI_D7,
LCD_B7, EVENTOUT
-
97 D4 141 D5 A4 169 200 C4 PE0 I/O FT_h -
LPTIM1_ETR,
TIM4_ETR,
HRTIM_SCIN,
LPTIM2_ETR,
UART8_RX,
FDCAN1_RXFD_MODE,
SAI2_MCLK_A,
FMC_NBL0, DCMI_D2,
EVENTOUT
-
98 C4 142 D4 A3 170 201 B4 PE1 I/O FT_h -
LPTIM1_IN2,
HRTIM_SCOUT,
UART8_TX,
FDCAN1_TXFD_MODE,
FMC_NBL1, DCMI_D3,
EVENTOUT
-
-- - - - - -A7VCAPS -- - -
99 - - - D5 - 202 - VSS S - - - -
- F7 143 C4 C6 171 203 E7 PDR_ON I FT - - -
-F4 - B4 - - - A6
VDDLDO
(8)