MAX505,506 Datasheet by Maxim Integrated

View All Related Products | Download PDF Datasheet
rsmzrmvz r194 lVI/lXI/VI Quad B-Blt DACs with flail-to-llall Voltage Outputs donor-l Doscrlptlon The MAX505 and MAXSOG an; CMO'S, quad. B—bitvoltage— output dlgitaI-to-analog oorwensrs (DACst The parts operate with a single +5v supply or dual 15v supplies. Internal precision output butters swing rall-lo-reil, The relevance input range includes both supply rails. Offset, gain. and linearityan lactorycalibrated to provrde 1LSB total unaolusteo error (TUE) over the lull operating temperature range. The MAXSOS contains double-btmered logic inputs. which allowallanalog euueutstobeermunaneouery updated using the asynchronous load DAC (LDAC) oonlrol signal. The MAXSOS also has tour separate reference inputs, allowing each DAC'S fill-Scale range to be independenlly set. The W506 NS sspelate iron. latches lot each of its tour DACs. Dallas transferred tome Inptl latchsslroma amnion 8-bit input port. The more Individually selected flown address inputsAD and A1, and updated by bmgng WR low, All MAXSOS BAGS share a common reference input. All logic Inputs are TTL and +5v CMOS compatible. Application Minimum Componont Count Analog systems Digital Ollset/Galn Adjustment Arbitrary Functlon Generators Industrial Process Conlrol —— Futuros 0 Open. nun Shah .sv my" Dt-l asv Supp.- 0 Output Elmer Antplmou wing mll-to-fl-II o Rmnco up»: Hung. mum Boill supply nan- O Factory-callbrlud lot ‘ILSB TUE o honorarium Dlglhl Input: (MAxsos) O “momma! and TIL/cues compnlhlo 0 mqulro no Emma Minimum. 9 Plu-Colnputlblo llpgrldu to IIX7225IMX7226 9 Now Avlllnble In Tlny SSOP Pooling. Ordering information put-r Tarn tuna: annotate: (335.) MAXWSACNG o‘cm ac MNumHm‘oDlP :1 MAXWSBCNG Otto-$70 t, 24mm“)? 21% MAxsosAch o‘cm+ro'c 24wldeso 11 MAXWBCWG 0.010 670.0 24 Wide 50 t1 ‘4 MAXSOSACAG WC [0 +70'C 24 35°F it MAXSOSECAG 0.0 to +70‘C 24 SSOP 21 ‘a MAXSOSBCID 0'0 I0 070‘0 Dice' 11‘ V2 Odom: MW continuum lain-n ' Contact rectory/or aloe specifications Automatic Test Equipment . V V V prog'ammable Afienm‘ors ‘Conmct famryloravarlabrmyandplmsmgm MlL-STD-ass. Functional Pilgrims Pln Configuration: VIBE m “mm Mm .23” TUPVIEW u A3431 ler 3.th Vault ' gym —r/ A Vow E E um vet E El V.» MAXIM —-N mg a,“ LELJ. anI WERE W505 2| WEFC —l/ a vnm E El vim) I ‘6'“ E E to 2‘ 3 a” m 5%“ TE :4: C — um E E] M l (mm E El mum 4\ fig" fig vwm on E '3‘ m _‘/ '7 In E E m mxsas ”E El m . DIPISOISSDF JNJE Vii FEDDYDGM) WWWMNN MAXIM Mmmmpmm I Call toll fro. 1-800-998-8800 for lroo samples or lltornture. 9OSXVfl/909XVW
MAX505/MAX506 Quad B-Bit DAGs with Rail-to-Rail Voltage Outputs ABSOLUTE MAXIMUM FIATINGS VDD lo AGND . -n.3v1 +8V MAXSOS VDD m DGND . -0 av‘ +5v Plum; DIP(dema 11.1 1mwrc above +7o'c) . . . 389nm vss lo AGND , =N. 0.3V \Nlde so (damn 1ooomwrc lbwe not) . , sounw V5319 DGND .-7v. 0.3V CERDIP(delals 11111mwrcmeuo'cl .aeemw van to vss , 4) 3v nzv Owafmg Tenveraiuve Ranges. Digilal Iwm Vamge m DGND. , aoav (VDD v o 31/) MAX50_ c_ . . . to +7o‘c was ,. . lvss 0. 3V) (V90 0 0 3V) MAXSO _L . AUG 11: «use anmote 1) ,.,vss. VDD MAX50_ M_ . 55‘0 1o +1251: Continuous PowerDisalpallon (u - on) c) SlMaoeTenlpululva Range . . 651: la +1651: MAxsos Leadlempemuremldering 10sec) . , ., “430m: Plastic DIP (genie samuwrc above not» . 1067mw Wide so (dams 11.76mWI‘C abwe no‘c) , 1 , 94mm CERDIP meme 12 somw/‘c abwe am?) i. . looomw ssoP1deme 8"!wa above no'c) 1 . .MOMW «an: PeeNogmmaybesmmflbVw vss mAGNDInap-amepousrdwiememeedea Tymalsmnciwncmemw is 50m summ- MWWWWW'W mwmme rnosaaesuasuumsony mammal mum mmumamgommmmummmmdmmm mimdlflvwmmfismmplbd EXWIU MMMMIAMWW Wmmymwmmwm ELECTRICAL CHARACTERISTICS (an . +5v 21096. vss - av 10 -5,5v, AGND = DGND . av, VREF - 4v, nL - 10m. cl . wow. u - mm m IMAX, unlels amarwlse nmsd) PARAMETER I swam. | commons I ran TVP MAXI uurrs STATIC ACCURACY Mullen 8 Elli VREF I «Vi MAXSDA t1 VES-WuéVXIOK MAxso B *1. Total Unadjusted Emzr TUE ’ /2 L56 VREF = -4v, ' MAX-WA H vs: = 5V 110% W5 *1 1/2 Diflelsnlial Nonlineanly DNL Gummeaanmmmc 121 L55 MAXSCLC 14 cm . oo hex. V53 = w MAXSOj 16 Zeta-001.15 Em" ZCE M ‘M 20 mV MAXWJ: :14 Code - DO hex. VSS _ -SV :10“ MAX50_E 116 MAXWJJI :20 Code - 00 thv Zen-Code Em Supply Rsiecbon VDD . 5v goes. 1 2 mV Vss - W o! ~5V £1036 mocode Tempelmuve Coeflicievll Coda - W hex tID uV/‘C Fuilscaie Enor Code . FF hex m mV 00119 e F hex. WED-C ‘ ‘ Fun-Scale Errol Sunny Rsiamim VDD = +5V 110%, MAXEDj I 8 mV m- We! -5thu% MW‘M ‘2 Fullscala—EnorTampefaturu cmmm Code - FF hex 210 uV/‘C z MAXIM
Quad a-Bit DAcs with Rall-to-natl Voltage Outputs ELECTRICAL CHARACTERISTICS (contlnuod) {Von - *5v 11m, Vss -ovm A5.5V‘ AGND - DGND - 0v, VREF - 4v. RL - mm, CL - IDDpF, TA - Wm M wa, unless chemise ma) WWW/909"" PARAMETER I swam. | commons | um m MAX um: REFERENCE mans Inpuianmgo Range vss van v mxsos us 2¢ Inmaesxnmsmma 2} Code = 55 hex ‘ 6 kn _ mm 15 Input cmmnance (Note a) Code = on hex MW 40 pF Chm-Whannallwuiun mmmmeo) a: as ACFeedIhvough MAX505(Nule5) -70 as me ourwrs Full-Scale cumul Voltage Vss Von V vow = 4v. lead Iagulaflien s miss 2 Racism Load vow = 4‘1,th regulahm s um 2 m vow=vw MW_C/Ebldmgflanmsl,5l.sa 10 vM=VmMAxwhedmgumsase m mum“. mvurs Logic mgr. v.” 24 v Logic Law VIL as v lnpul Current Melsmed ale ma VIL it ”A Inpumapwmm a par lnpuiCoding Emmy nvumlc penronumos MAxso_c LU Vanaga-Oummslewfille mmmnegam muse; 0] Vin: MAxsom us ompmswmgnme To:ll2LSE.10KDIIImnFInad(Nme6) 5 us my“ mummy. mm: 595:? wn = Von. an digital mpuls 5 n“ VREF - 4v -p m lkHz, VDD - 5v, vss - .5v, 3, dB Signal |o (Noise . Distortion) nan» m = FF vnss = AVp-p a 2mm, vs; . évxms 44 as MulliplyingBandwidlh was; =osvw, mammmm 1 MHz Widebsnd AmpimarNoise so nVnMs MAXIM 5
MAX505/MAX506 Quad B-Blt DAGs with Rail-to-Rail Voltage Outputs ELECTRICAL CHARACTERIS'HCS (oomlnued) (Von . .5vg1oss. Vss = ovm 5.5V. AGND = DGND = ov, VREF = av‘ RL - mm, CL . IDDpF, n = TMIN to TMAX. unless otherwise norm) PARAMETER \ mm» | commons | MIN "F max] uurrs rowan suwss Posinve Supply Van-gs vm; Forspeoilied performance 45 55 v Negaiive Suppoy thaga vs; Fwspecilied pmomnce —5 s o v Posmve Supply Cunenl loo figmzm‘fi‘a‘r'bw mg]? g :2 MA _ vss 5v 210%.putpms MAstCIE 5 10 Negative 5‘le Curvem lss 95393ng dlgflal mmls MAxsnm 5 ‘2 mA swvrcume cummms’nes Address to W Setup us 5 -8 ns Address in m Ham 1m 5 -A ns Data to W Sewn ms 45 35 ns DmxofiHom mu 0 43 us fi Pu|se mam MR 40 20 us LDAC Pulse mum mo «2 20 n3 ma- 2: Inpul magma Duds depeudem. The Iwesl Inpm resistance occurs steeds - 55 by. man :: Wu: capamma is code mm. me mm in: “out: mm Irv-AI EF- IDKHzJV codeofallothevDA swoon“ ms: vnB== 1mm 4W9. DACcoda=mhex Now a: Ouuwlmling lime is measured by waking the code [mm co m In F ha, and cm FF hex to no hex. OIHPU' SINK CURRENT vl‘ (Vow-V55) n In Vm-VKFnGV mama-w mmm n12 a: ssllummz leH/ssM wmvcnmm 1m» ulcamlancaoccmaleodo-thx V Channsl—lochannel im‘alion Is measured by naming the code alone DAC to FF hex and sealing me Typléal Operating Characteristics SUPPLV CURRENT VLTEIIPERATURE a 5 a 3 Vm-dis‘l 2 .ssv =05 , mm ”av 0 «Ham 0 29 to m lummuo mmmm) m1 SUPPLV CURRENT 6 v3. REFERENCE VOLTAGE v$.W v "we "5v mam wuvsmv u ~54>3~2~Inl23|5 vnrrvomeem
TND ¢ NOISE AT DAG 0|!qu “I REFERENCE FREQUENCY AND ANPerUnE 4a 45 en ~56 can ga ; ,m E as -m .55 ~90 mm. m an In 2030 w 50 com” an In NEFERENCEAMPHNKNVII REFERENCE VOLYAGE INPUT FREQUENCY RESPONSE van-Isv mun nmuvs own! (a) Ik m m III «N mmummm OUTPUTSOURcEwRREN'I' "your '95 I 4 I I vm-vnEr-vsv Vss-wn -2o mammrumm a :45 5-‘0 -s n as u to 42 u do 4: sn VnulM Quad B-Bit DAGs with Hail-to-Rail Voltage Outputs Typical Oporaflng Characteristics (continued) 1RD o NOISE A1 DAG OUTPUT In. REFERENCE FREaIIEch AND AWLITUDE .20 m ,3n = .sv ' gilt § 4" cans. ma ‘* - .swm fl '50 5 «an I III 5 ~10 «w w"; u um an In 1w II «1 m mama minimum) REFERENCE voLYAaE INPUr FREauEncv RESRONSE anéV V3: ‘51] YA .m wry-25m. VNWEWAVE mm: mm" m III M Im IM m mmnm) DIGII’AL FEEmHRuuGR - uLll’cN Iqu (o m 1 mGrIAI. TRANsIrIoNI A- warm INPUIS,SVMIV a-VnmAme/nw mm: . 1,.5 am I mmmmunu an All. mmusmwummnn) vim-Nam m: § umsu nmnv: mum (my 2 REFERENCE VOIJAGE INPUT FREnuEch RESPONSE so 40 II mI Imk m m maumcmz! ZERDcODEERROH 5?. NEGATIVE SUPPLV VOLTAGE a van . .5v vkzr . «v u. we MMMmMIIWI u v . . - ; DIGIrAL FEEImIRouG aercN IMPULSE I 1 DIGITALsz A-nIeIm IMPUIS, swan s . vnum wmI/mv mime . IIIS I ma mmm mus m AU mums (Mm m1) vam- 1am MAXIM QOSXVW/SOSXVW
MAX505/MAX506 Quad B-Bit DAcs with Rail-to-Rail Voltage Outputs Typical Operating Ghanaian-Idle: (continued) nEFEn nErEnEucE FEED‘IHRDUGH POSWWE SEWING "ME 94le 5555mm” Al’ moan: (Vss - AGND) A. was? my ,, I. A mm mm my, a: m: ‘WNMV WLDADED E= VIN" m£lfl$wliv~ UNLWID Elms/gist: 21M" VIMKEASE. Ins/m VD“ _ ,W ' “5 Vm . .ev V55 ' 5" “Fail-5'3]; 10m ms nu CNS-£105 flL-VflvaHWvF Posmvs SEI'I'LING TIME NEGATIVE szrruue nuE NEGATIVE SE'I'I'LNG nu: (Vs: -'5V) (Vss MONK?) (Vss - 6V) GM] mm ‘ Mn END (BID 5 END A: DEIYAL \NPUI, fivldrv A uleALllHfl, 5V v A: MWM llfifl. swam B-VWM (Wm B sVrmA. Zvldiv 8: anAW MY "HEW - I»: Y MEW "HEW: 19$ um. .5»: anfi WEFA- 6V M «5‘! MFA; '6‘] MHVSOFrwmansuN mswswomsusw ALLawsaMmAuaIlsoFr RL-mmm-IW Amamuamr mama-1w 5 MAXIM
Quad B-Bil DAG: with Pin Dunn-1pm»! PIN MAE “X505 MAW I I VOU'E DAC 5 Ql‘pul Venice 2 2 un DAD A Output Vance a 3 Vss Necative Power Supply 4 VfiEFB Rah-lance Vduge Input lor DAG s 4 VHEF meme Vomge Input '0! DACAlo DAG D 5 WEEK Ramm‘lalmqe Infill I01 DAC A 8 5 AGND Analog Ground 7 6 DGND Dismal Gmund 8 m kg: 3:: mg! (wflvelw “gang“: asynaucmous lwul km Hillier: ma cameras 01 each 9 7 D7 Dita B“ 7 (M58) I0 8 D6 Dali Bu 6 ‘I 9 D5 Dan Bi! 5 12 10 DA Data BM 4 IS II Da Data Bil 3 M 12 DZ Dam Bil 2 I5 ‘3 m Data an 1 IS M DO Dale EM 0 (L35) '7 IS W erlB Input (ems ION). Used to load am im me DAG Input Illa! new WM) and A1. 18 18 Al DAG Addie” 56m bi!(MSB} ‘9 17 M) DAD Addvess 5646c! bl! (L38) 20 VEEFD Refievenoe leage Inpm I01 DAG D 2' VREFC Relevance Voilage Inpu tor DAG C 22 15 Van PosmveSuppty Vdmge 2:4 19 ann DAG DWleage 24 an Vourc DAC 0 Oman! Voltage MAXIM QOSXVfl/QOSXVW
MAX505/MAX506 Quad 8-Bit DAG: with Rail-to-Rail Voltage Outputs Del-ll“ Description Wm Won The MAX505/MAX506 conieln iour matched voltage“- put DACs. The DACs are inverted Ft~2R ladder networks lnal convert 8-bit digital words into equivalent analog output voimges In propordon to the applied reference vmtagels). Each DAC in the MAXSOE has a separate relererlce input. while all tour DACs in the MAXSOG share a common reierence Input. Figure 1 shows a simplified functional diagram ol one oi the DACs, mmullmm figure 1, DACSIMDWC/rcuii Divan hwmuumnmm The MAxsosmAxsos can be used tor multiplying applications. The reference accepts both DC and AC signals. The voltage at each VREF input sets the full-scale output voltage for its respective DAC, The VREF input impedance is code dependent. wlth the lowest value (16m for the MAX505 and am for the MAXSOS) occuring when the input code is 55 hex The maximum value. essentially Inilnlty, occurs when the input code is 00 hex. Since the VFIEF Input im- pedance is code dependent. the DACs' relerenoe sour- ces must have a low output impedance (no more than 320 for the MAX505 and an to! the MAXSOS) to maintain output linearity. The VFtEF input capacitance is also code dependent: ISpF maximum tor the MAXSOS and 40pF maximum tor the MAXSOG. The output voitagetor any DAG can be represented by a digitally programmable voltage source as: Vou'r = (Na x VREF) (256 where Na is the numeric value ol the DAC's binary Input code. will lunar Amplifier: All MAXSOSIMAX506 voltage outputs are Internally bui- tered by precision unity-gain followers that slew al1VIhs. \Mth a 0V to +4V (or «V to 0V) outpul transition. the amplifier outputs will settleto 1/2Lse in typicallyspswhen loaded with tom in parallel with 100pF. The butler amplifiers are stable with any combination oi resistive loads 2 2m and capacitive loads 5 300pF 0W mute and Inf-m Logic The digital inputs are compatible with both Ti]. and 5V CMOS logic. Howevert the powersuppty currenl (loo) depends on lhe input logic levels. Supply current is specified tor CMOS input levels (best case). Supply current increases by about ZrnA when driven with TTL logic levels. Address lines A0 and A1 select which DAC receives data irem the data bus as shown in Teoie 1, When W is lcm. the addrewed DAC‘s input latch is transparent Data is latched when WE ls highl Figure 2 shows the MAX5fl5/MAX506 MD“! control logic. The MAXSOB DAC outputs represent the data held in the tour 87bit input latches. The MAX505 has double» buttered inputs; in addition to the input registers, there are individual DAG latches (see Functional Dlagrarrrs).
Quad B-Bit DAcs with Hall-to-nall Voltage Outputs (W all“ V AI V w—D— Hymn Z WW5“ Imwf Como! Logic In lhe MAXSOS, date is translerred lrom the ingut Table 1a. MAXSOS DAG Addmulng (pant-I mt) Al Al) LATOOI STATE x input-m DAG am lemma DAG A mm latch Innsparent x L L X Mlm'nwlmnmmt fimi mumps-mm me a 1mm latch mutant H L H L DACClnpmlatohtrmmerw HLHH me 0 input Inch Inn-parent H=HighstmelL=LWSulaX=Don10ua Table 1b. W506 DAO Addresslng latches lo the DAC latches by pulllno the (pgrflgl ll“) control input low This operation sumultenoously updates all tour outputs. since LDAC is m M M ums‘rATE asynchronous with respect to , be sure that Incorrect data is not latched to the output‘ Table N X x Inputdataluched la is the write-cycle truth table for the MAXSOS. Table lb Is the write-cycle truth table lor the L '- l DACAVIW'WVWW' MAX5OSL Flgure 3 shows the MAX505/MAX506 t write-cycle tlmin , "simultaneous updellng is not L L H DACB'WWSMVWW‘ required, tie LDA low to keep the DAC latches L H L chlnpmlammtmwermt transparent. Eevold output glltches. insure that data is valid belareWR law MAXSOG). This also applies L N H DACD‘mputlelchtrmeperent tome W505i! and erelow slrnulleneously. 0n powthp. ell MAXSOS/MAXSOS latches are internally preset with all Os. MAXIM H.mgnsm,L-mwsure.x-Dmcare 909XVW905XVW
MAX505/MAX506 Quad B-Bit BAGS with Rail-to-flail Voltage Outputs r r ‘W was mmvwo av ._ m _.: _ m fl .sv ov um (ml-V} In 6V um w W “3—. .91 “fl‘ muvllun w mu: Aulllrlrlslamlllsuunrmrursmnmumrnmnmr,u...smmnmm mm mmmlnmrczmrs W IrmmmwmIsAcuwxlmmlollmfisnsmm,llulrslsmwllrofinrzlonmmlmfiaoesnm Figure 3, WWW wmcycls Timing Dr'lgmm Application: Information low» M and Nahum Opal-ting Rango- The MAxsosmAxsoe are lully specified to operate wilh VDD - 5V1IO% and V58 = 0V lo -5.5VV Mil pedomancs is guaranteed for bolh slngle- and dual-supply operan‘on. The zero
Quad B-Bl'f DAG: with sveruain o e e o e e e a e cmrmmmum maimismsrnwn) .5v srzimm m Vllo mantras l | mm NOD AIDLE vwm Vs mum MIXIM I: l 7 Mum «mm! |—.l. SOSXVWISOSXVW Haws 5, wmmauymbrmmm "MIDI-i Output. um: “WM In unipolar operation, the cuipui voltages arid lhe refer- ence Inpuus) are me same polarity. Figures 6 and 7 show (he MAXSOSIMAXSOS unipolar covrligurallons. If (he rel- erence Inputs are positive, both de~ices can beeperaled from a single supply. if dual supplies are used, [he relerarioe inpui can vary from Vss to VDD. Table 2 is ihe unlpolar code iabie, M 0m "ml ”Hulk-lion Bipolar output 2—quadranl mumplicalion is achieved by arisenlng AGND positively or negaiiveiy. my AGND Pulhlvlly - slngk or Dual supplie- AGND can be biased abcvva DGNDlo provide anarbilrary nonzero output voltage lor a 0 input code. as shown in Figure 5. The output voliage a! VOUTA is: VOUTA = VBIAS + (Na/256mm where Na represents the digilal lnpin word. Since AGND is common to all laur DADS. all outputs will be Ollsel by VEIAs in lhe same manner. AGND should not be biased more than +1V above DGND. MAXIM 5911!qu MAXMEUDWAIOWO‘ICM WEIGEINVSWSSID‘M) mi 4| “l Van um $1.3. vim. . WE J‘DL» vwr- mutants l ”mm N we _L[>i.-m l W“ I 13mm V§ END Mn |3 s mm mm", ‘l—fl W6 ‘ ’ = Hyursz msosuniooiaromcmi I1
MAXSOS/MAX506 Quad B-Blt BAGS with flail-to-nail Voltage Outputs Table 2. Unipolar Cod. Table Table 3. Bipolar Code Table mcoorrrems monomer": mmotrmrr urpur use us use LSI ANALOGO 355 127 1111 III! ’VREFizss] mi 1111 vnir[fi] louo ooot wasfl 1000 one! VREF‘— 25o rza man 0000 +VREF[‘§]=¢VR2EF WW 0”“ W I 01 It Illl —vaEF[— olll IIII ovnEF[%] ‘26 ‘ oooo ouot “erg—:3] 0000 cam .vner[fi) 121a 0000 0000 w 0000 0000 ~vnEF[fi].-VHEF Nob: use - (VHE‘F) (2‘) - was; ollutflng 1mm: Nagadvoly - D-nr Supplln An alternate method of gensraling blpolar outpum usss Figure 5's circuits In these circuils, AGND is biased negatively (up in ~2.5V with respect to DGND) to provide an arbitrary negative output vonage tor a 0 input code, The oulput voltage el VomA is: VOUTA = (IE/F") (25V) + (NE/256N290 (HZ/RI t- I) where Ns represents the dlgiial input word, Slnoe AGND is common to all tour DAGs. all outputs will be offset by VelAs in the same manner. Table 3,will1 VREF = 2.5V. shows the digllai code vs, output voilage tor figure 9‘s circuits with R1 = H2. WWW” Each DAG output may be configured tor “quadrant multiplication using Flgure 10's circuit. One op amp and two resistors are required per channel, With R1 : R2: VOUT = VREF [(ZXNEIZSG) -1], where Na represents the digital word in DAC regimer A. Recommended values tor resistors R1 and R2 are mm (mm). table 3 shows me dlgilal code vs. output vult— aue for Figure 10's circuit, 12 GI 5 [22 H van V" ~ 2 W A VW'A ”w m M Vs m It J! = aria-law) 7 .av t [in we? VI» VII - 2 w A Vain 5 . m ”3"” W505 me vs: new I3 J! 7 5leer 1 ‘ DWTM WW5 “Mm agma a, AGND Blue 0mm (Poa‘n‘ve Offset) Mm
Quad 8-Bit times with nail-to-Rail Voltage Outputs mum": 50m osv m "E w van Fame 9.. W505 AGND B's: D'rwil (Negative 0mm) figms 9b. Muses AGND Bias aim: (Negative Offset) MAXIM 13 SOSXVfl/SOSXVW
MAX505/MAX506 Quad B-Blt BAGS with flail-to-flall Voltage Outputs mm Iwmm SM mm": Vss nwf‘?‘ mama mm mmlmummm Fumwa. mmoumum mu. mm! m Mill) MID “Mlfi: 5' 5 mm»! ”are: mvlcuuumamm Fngmmb. MAXSOGWOMW 1‘ MAXIM
Quad B-Blt DAG: with Rail-to-Bail Voltage Outputs _Functlonal Diagram (continued) _ Mn Outflow-lions (continued) “I “3‘" mvzw Vuml E 5| mm vmm E 5] mm VS a 13 W“ W I E w mun E m M mm E ‘5 fi m7 E 31 mm 06 5 1! D1 m 0 12 DZ 0‘ [E n nu um ram. an»: PIPH’ACKAGE ”“5, MAXSOSAENG won: .851: ammo? :1 MAXSOSBENG we“: «35's mama-aim? 2w: MAXSOSAEWG 40m: .551: 24 was so :1 MMSNBEWG 40'0 la «85% 24 M60 90 “52 MAXSOSAEAG we to own 24 $0? *1 MAXBOSBEAG 40'0“: .ss'c 24 ssop 2w: MAxsosAMne we to “5'0 «mean?- *1 MAxsosaMne wow «so 24mm?- 1% MAXSCfiACPP US In +70'C 20 PImio DIP 1:1 WPP US In +70'C 20 HIM DIP 3:192 MAXWCWP 0'0 [0 970'0 20 WHO 50 fl MAxsosacwr mam +101: zowmso :1»: W506ch 0'0 to $7017 Dice' 1:1": MAX5OGAEPP we in owe zo Hm: DIP g: MAXSOGBEPP 4470 lo QBS'C an HMO DIP 21% MAXSOSAEWP 40'0 I0 {SS'C 20 W6. 50 $1 MAXWEEWP 40'0 In OSS'C 2D Mae SO fl'é MAXSOSAMJP 45cm uzs'c ZDCEHDIP“ :1 MAXWBMJP -55'C m +125'C 20 CERDIP" fl'fl - Cant-ct lam kw doe specifications» "Cor-rm Item Ior availabmanduocssing to MIL-Sm. MAXIM It MSXVWSOQXVW
MAX505/MAX506 2 gym Quad B-Bit DAG: with Ra -Io-Rail Voltage Outputs < h="" l="" in="" no="" no="" on="" mm="" on="" i'm="" m="" m="" in="" n_12r="" mar="" 4—azoomm)="" (32mm)="" ramslsvoa="" com!="" 1717.="" mms‘ron="" scum:="" 1m.="" subsyraye="" connecyed="" to="" vdd.="" subs’vraye="" weg'ed="" y0="" vdd.="" puck-go="" information="" m="" i‘cdei="" iijjiie'i'er!="" iii="" max="" in="" iiax="" a="" am="" 0078="" l75="" 1="" .00="" a1="" 0.00%="" 0.000="" 0.05="" 0.21="" b="" 0010="" 0.015="" 0.25="" 0.8="" c="" 0.006="" 0.000="" 0.18="" 0.22="" d="" 0278="" 0.328="" 7.07="" 3.5="" e="" 0205="" 0.212="" 5.20="" 5.3="" i="" 0.02!="" 39c="" 0.06="" i:="" h="" 0.301="" 0.3“="" 7.65="" 7.”="" l="" 0022="" 0.067="" 0.35="" a.="" 0'="" 8'="" 8‘="" mm="" 24-pin="" plastic="" shrink="" small-outline="" package="" mum.annoy-mmmmwmmdwmmamcmmnmmmmmmmmmmt.="" noctmn‘patemmmsminm‘ed="" www="" mrmmmgommmmwwm="" m‘mnamamm="" 1c="" __—mulmlmngmndhwm="" vzosanwmswmym="" ca="" mutm)m-ma="" @1994="" maxim="" imam="" products="" hunted="" usa="" wis="" nregistered="" wademark="" m="" maxim="" imagmsd="" ondu-m.="">

Products related to this Datasheet

IC DAC 8BIT V-OUT 24SOIC
IC DAC 8BIT V-OUT 24DIP
IC DAC 8BIT V-OUT 24DIP
IC DAC 8BIT V-OUT 20SOIC
IC DAC 8BIT V-OUT 20DIP
IC DAC 8BIT V-OUT 24SSOP
IC DAC 8BIT V-OUT 24SSOP
IC DAC 8BIT V-OUT 20DIP
IC DAC 8BIT V-OUT 24SSOP
IC DAC 8BIT V-OUT 20SOIC
IC DAC 8BIT V-OUT 24SOIC
IC DAC 8BIT V-OUT 20SOIC
IC DAC 8BIT V-OUT 20SOIC
IC DAC 8BIT V-OUT 20DIP
IC DAC 8BIT V-OUT 24DIP
IC DAC 8BIT V-OUT 24SOIC
IC DAC 8BIT V-OUT 24DIP
IC DAC 8BIT V-OUT 20DIP
IC DAC 8BIT V-OUT 24SOIC
IC DAC 8BIT V-OUT 24DIP
IC DAC 8BIT V-OUT 20DIP
IC DAC 8BIT V-OUT 24SOIC
IC DAC 8BIT V-OUT 20SOIC
IC DAC 8BIT V-OUT 24DIP
IC DAC 8BIT V-OUT 24SSOP
IC DAC 8BIT V-OUT 24SSOP
IC DAC 8BIT V-OUT 24DIP
IC DAC 8BIT V-OUT 24SOIC
IC DAC 8BIT V-OUT 24SSOP
IC DAC 8BIT V-OUT 24SOIC