PCA9952, PCA9955 Datasheet by NXP USA Inc.

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1. General description
The PCA9952 and PCA9955 are I2C-bus controlled 16-channel constant current LED
driver optimized for dimming and blinking 57 mA Red/Green/Blue/Amber (RGBA) LEDs in
amusement products. Each LEDn output has its own 8-bit resolution (256 steps) fixed
frequency individual PWM controller that operates at 31.25 kHz with a duty cycle that is
adjustable from 0 % to 99.6 % to allow the LED to be set to a specific brightness value. An
additional 8-bit resolution (256 steps) group PWM controller has both a fixed frequency of
122 Hz and an adjustable frequency between 15 Hz to once every 16.8 seconds with a
duty cycle that is adjustable from 0 % to 99.6 % that is used to either dim or blink all LEDs
with the same value.
Each LEDn output can be off, on (no PWM control), set at its individual PWM controller
value or at both individual and group PWM controller values. The PCA9952 and PCA9955
operate with a supply voltage range of 3 V to 5.5 V and the constant current sink LEDn
outputs allow up to 40 V for the LED supply. The output peak current is adjustable with an
8-bit linear DAC from 225 A to 57 mA.
These devices have built-in open, short load and overtemperature detection circuitry. The
error information from the corresponding register can be read via the I2C-bus. Additionally,
a thermal shutdown feature protects the device when internal junction temperature
exceeds the limit allowed for the process.
The PCA9952 and PCA9955 devices have Fast-mode Plus (Fm+) I2C-bus interface. Fm+
devices offer higher frequency (up to 1 MHz) or more densely populated bus operation
(up to 4000 pF).
The PCA9952 is identical to PCA9955 except for the following differences:
The PCA9952 has only three hardware address pins compared to four on PCA9955.
The PCA9952 has an output enable pin (OE) and the PCA9955 does not.
The active LOW output enable input pin (OE), available only on PCA9952, blinks all the
LEDn outputs and can be used to externally PWM the outputs, which is useful when
multiple devices need to be dimmed or blinked together without using software control.
Software programmable LED Group and three Sub Call I2C-bus addresses allow all or
defined groups of PCA9952/55 devices to respond to a common I2C-bus address,
allowing for example, all red LEDs to be turned on or off at the same time or marquee
chasing effect, thus minimizing I2C-bus commands. On power-up, PCA9952/55 will have
a unique Sub Call address to identify it as a 16-channel LED driver. This allows mixing of
devices with different channel widths. Four hardware address pins on PCA9955 allow up
to 16 devices on the same bus. In the case of PCA9952, three hardware address pins
allow up to 8 devices on the same bus.
PCA9952; PCA9955
16-channel Fm+ I2C-bus 57 mA constant current LED driver
Rev. 7.1 — 29 June 2015 Product data sheet
PCA9952_PCA9955 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 7.1 — 29 June 2015 2 of 48
NXP Semiconductors PCA9952; PCA9955
16-channel Fm+ I2C-bus 57 mA constant current LED driver
The Software Reset (SWRST) function allows the master to perform a reset of the
PCA9952/55 through the I2C-bus, identical to the Power-On Reset (POR) that initializes
the registers to their default state causing the output current switches to be OFF (LED off).
This allows an easy and quick way to reconfigure all device registers to the same
condition.
2. Features and benefits
16 LED drivers. Each output programmable at:
Off
On
Programmable LED brightness
Programmable group dimming/blinking mixed with individual LED brightness
Programmable LEDn output enable delay to reduce EMI and surge currents
16 constant current output channels can sink up to 57 mA, tolerate up to 40 V when
OFF
Output current adjusted through an external resistor
Output current accuracy
6 % between output channels
8 % between PCA9952/55 devices
Open/short load/overtemperature detection mode to detect individual LED errors
1 MHz Fast-mode Plus compatible I2C-bus interface with 30 mA high drive capability
on SDA output for driving high capacitive buses
256-step (8-bit) linear programmable brightness per LEDn output varying from fully off
(default) to maximum brightness using a 31.25 kHz PWM signal
256-step group brightness control allows general dimming (using a 122 Hz PWM
signal) from fully off to maximum brightness (default)
256-step group blinking with frequency programmable from 15 Hz to 16.8 s and duty
cycle from 0 % to 99.6 %
Output state change programmable on the Acknowledge or the STOP Command to
update outputs byte-by-byte or all at the same time (default to ‘Change on STOP’).
Active LOW Output Enable (OE) input pin (only on PCA9952) allows for hardware
blinking and dimming of the LEDs
Four hardware address pins allow 16 PCA9955 devices to be connected to the same
I2C-bus and to be individually programmed
Four software programmable I2C-bus addresses (one LED Group Call address and
three LED Sub Call addresses) allow groups of devices to be addressed at the same
time in any combination (for example, one register used for ‘All Call’ so that all the
PCA9952/55s on the I2C-bus can be addressed at the same time and the second
register used for three different addresses so that 13 of all devices on the bus can be
addressed at the same time in a group). Software enable and disable for each
programmable I2C-bus address.
Unique power-up default Sub Call address allows mixing of devices with different
channel widths
Software Reset feature (SWRST Call) allows the device to be reset through the
I2C-bus
8 MHz internal oscillator requires no external components
PCA9952_PCA9955 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 7.1 — 29 June 2015 3 of 48
NXP Semiconductors PCA9952; PCA9955
16-channel Fm+ I2C-bus 57 mA constant current LED driver
Internal power-on reset
Noise filter on SDA/SCL inputs
No glitch on LED on power-up
Low standby current
Operating power supply voltage (VDD) range of 3 V to 5.5 V
5.5 V tolerant inputs on non-LED pins
Operating temperature:
20 C to +85 C (PCA9952TW, PCA9955TW)
40 C to +85 C (PCA9952TW/Q900, PCA9955TW/Q900)
ESD protection exceeds 2000 V HBM per JESD22-A114, 750 V CDM (PCA9952TW,
PCA9955TW), and 500 V CDM (PCA9952TW/Q900, PCA9955TW/Q900) per
JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 Class II, Level B
Packages offered: HTSSOP28
3. Applications
Amusement products
RGB or RGBA LED drivers
LED status information
LED displays
LCD backlights
Keypad backlights for cellular phones or handheld devices
Automotive lighting (PCA9952TW/Q900, PCA9955TW/Q900)
@900,
PCA9952_PCA9955 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 7.1 — 29 June 2015 4 of 48
NXP Semiconductors PCA9952; PCA9955
16-channel Fm+ I2C-bus 57 mA constant current LED driver
4. Ordering information
[1] PCA9952TW/Q900 and PCA9955TW/Q900 are AEC-Q100 compliant.
4.1 Ordering options
Table 1. Ordering information
Type number Topside
marking Package
Name Description Version
PCA9952TW PCA9952 HTSSOP28 plastic thermal enhanced thin shrink small outline package;
28 leads; body width 4.4 mm; lead pitch 0.65 mm;
exposed die pad
SOT1172-2
PCA9952TW/Q900[1] PCA9952 HTSSOP28 plastic thermal enhanced thin shrink small outline package;
28 leads; body width 4.4 mm; lead pitch 0.65 mm;
exposed die pad
SOT1172-2
PCA9955TW PCA9955 HTSSOP28 plastic thermal enhanced thin shrink small outline package;
28 leads; body width 4.4 mm; lead pitch 0.65 mm;
exposed die pad
SOT1172-2
PCA9955TW/Q900[1] PCA9955 HTSSOP28 plastic thermal enhanced thin shrink small outline package;
28 leads; body width 4.4 mm; lead pitch 0.65 mm;
exposed die pad
SOT1172-2
Table 2. Ordering options
Type number Orderable
part number Package Packing method Minimum
order
quantity
Temperature
PCA9952TW PCA9952TW,118 HTSSOP28 Reel 13” Q1/T1
*standard mark SMD 2500 Tamb =20 Cto+85C
PCA9952TW/Q900 PCA9952TW/Q900,118 HTSSOP28 Reel 13” Q1/T1
*standard mark SMD 2500 Tamb =40 Cto+85C
PCA9955TW PCA9955TW,118 HTSSOP28 Reel 13” Q1/T1
*standard mark SMD 2500 Tamb =20 Cto+85C
PCA9955TW/Q900 PCA9955TW/Q900,118 HTSSOP28 Reel 13” Q1/T1
*standard mark SMD 2500 Tamb =40 Cto+85C
PCA9952_PCA9955 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 7.1 — 29 June 2015 5 of 48
NXP Semiconductors PCA9952; PCA9955
16-channel Fm+ I2C-bus 57 mA constant current LED driver
5. Block diagram
Dim repetition rate = 122 Hz.
Blink repetition rate = 15 Hz to every 16.8 seconds.
(1) On PCA9955 this pin is address pin A3. On PCA9952 this pin is OE.
Fig 1. Block diagram of PCA9952/55
A0 A1 A2 A3/OE
(1)
002aae909
I
2
C-BUS
CONTROL
INPUT FILTER
PCA9952/55
POWER-ON
RESET
SCL
SDA
V
DD
V
SS
LED STATE
SELECT
REGISTER
PWM
REGISTER X
BRIGHTNESS
CONTROL
GRPFREQ
REGISTER GRPPWM
REGISTER
(DUTY CYCLE
CONTROL)
MUX/
CONTROL
'0' – permanently OFF
'1' – permanently ON
DIM CLOCK
31.25 kHz
8 MHz
OSCILLATOR
RESET
REXT LED14 LED15
I/O
REGULATOR
OUTPUT DRIVER, DELAY CONTROL
AND ERROR DETECTION
INPUT
FILTER
÷ 256
200 kΩ
individual LED
current setting
8-bit DACs
DAC
15
LED1LED0
DAC
14
DAC1
DAC0
repetion rate 31.25 kHz
33333333333333 EEEEEEEEEEEEEE 33333333333333 EEEETEEEEEEEEE R
PCA9952_PCA9955 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 7.1 — 29 June 2015 6 of 48
NXP Semiconductors PCA9952; PCA9955
16-channel Fm+ I2C-bus 57 mA constant current LED driver
6. Pinning information
6.1 Pinning
a. PCA9952TW; PCA9952TW/Q900 b. PCA9955TW; PCA9955TW/Q900
(1) Thermal pad; connected to VSS.
Fig 2. Pin configuration for HTSSOP28
V
DD
SDA
SCL
RESET
V
SS
LED15
LED14
LED13
LED12
V
SS
LED11
LED10
LED9
LED8
REXT
A0
A1
A2
OE
LED0
LED1
LED2
LED3
V
SS
LED4
LED5
LED6
LED7
002aae911
1
2
3
4
5
6
7
8
9
10
20
19
11
12
18
17
22
21
13
14
16
15
24
23
26
25
28
27
PCA9952TW
PCA9952TW/Q900
(1)
002aae912
1
2
3
4
5
6
7
8
9
10
20
19
11
12
18
17
22
21
13
14
16
15
24
23
26
25
28
27
REXT V
DD
A0 SDA
A1 SCL
A2 RESET
A3 V
SS
LED0 LED15
LED1 LED14
LED2 LED13
LED3 LED12
V
SS
V
SS
LED4 LED11
LED5 LED10
LED6 LED9
LED7 LED8
(1)
PCA9955TW
PCA9955TW/Q900
PCA9952_PCA9955 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 7.1 — 29 June 2015 7 of 48
NXP Semiconductors PCA9952; PCA9955
16-channel Fm+ I2C-bus 57 mA constant current LED driver
6.2 Pin description
[1] In order to obtain the best system level ESD performance, a standard pull-up resistor (10 k typical) is
required for any address pin connecting to VDD. For additional information on system level ESD
performance, please refer to application notes AN10897 and AN11131.
[2] HTSSOP28 package supply ground is connected to both VSS pins and exposed center pad. VSS pins must
be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board
level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad
on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the
PCB in the thermal pad region.
Table 3. PCA9952 pin description
Symbol Pin Type Description
REXT 1 I current set resistor input; resistor to ground
A0 2 I address input 0[1]
A1 3 I address input 1[1]
A2 4 I address input 2[1]
OE 5 I active LOW output enable
LED0 6 O LED driver 0
LED1 7 O LED driver 1
LED2 8 O LED driver 2
LED3 9 O LED driver 3
LED4 11 O LED driver 4
LED5 12 O LED driver 5
LED6 13 O LED driver 6
LED7 14 O LED driver 7
LED8 15 O LED driver 8
LED9 16 O LED driver 9
LED10 17 O LED driver 10
LED11 18 O LED driver 11
LED12 20 O LED driver 12
LED13 21 O LED driver 13
LED14 22 O LED driver 14
LED15 23 O LED driver 15
RESET 25 I active LOW reset input
SCL 26 I serial clock line
SDA 27 I/O serial data line
VSS 10, 19, 24[2] ground supply ground
VDD 28 power supply supply voltage
PCA9952_PCA9955 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 7.1 — 29 June 2015 8 of 48
NXP Semiconductors PCA9952; PCA9955
16-channel Fm+ I2C-bus 57 mA constant current LED driver
[1] In order to obtain the best system level ESD performance, a standard pull-up resistor (10 k typical) is
required for any address pin connecting to VDD. For additional information on system level ESD
performance, please refer to application notes AN10897 and AN11131.
[2] HTSSOP28 package supply ground is connected to both VSS pins and exposed center pad. VSS pins must
be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board
level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad
on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the
PCB in the thermal pad region.
Table 4. PCA9955 pin description
Symbol Pin Type Description
REXT 1 I current set resistor input; resistor to ground
A0 2 I address input 0[1]
A1 3 I address input 1[1]
A2 4 I address input 2[1]
A3 5 I address input 3[1]
LED0 6 O LED driver 0
LED1 7 O LED driver 1
LED2 8 O LED driver 2
LED3 9 O LED driver 3
LED4 11 O LED driver 4
LED5 12 O LED driver 5
LED6 13 O LED driver 6
LED7 14 O LED driver 7
LED8 15 O LED driver 8
LED9 16 O LED driver 9
LED10 17 O LED driver 10
LED11 18 O LED driver 11
LED12 20 O LED driver 12
LED13 21 O LED driver 13
LED14 22 O LED driver 14
LED15 23 O LED driver 15
RESET 25 I active LOW reset input
SCL 26 I serial clock line
SDA 27 I/O serial data line
VSS 10, 19, 24[2] ground supply ground
VDD 28 power supply supply voltage
Figure 1 “Block diagram of PCA9952/55" Figure 3 Figure4 —A— —A— WW —(_,_V# Section 7.3.10 “ALLCALLADR, LED All Call LCrbus address"
PCA9952_PCA9955 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 7.1 — 29 June 2015 9 of 48
NXP Semiconductors PCA9952; PCA9955
16-channel Fm+ I2C-bus 57 mA constant current LED driver
7. Functional description
Refer to Figure 1 “Block diagram of PCA9952/55.
7.1 Device addresses
Following a START condition, the bus master must output the address of the slave it is
accessing.
For PCA9955 there are a maximum of 16 possible programmable addresses using the
4 hardware address pins.
For PCA9952 there are a maximum of 8 possible programmable addresses using the
3 hardware address pins.
7.1.1 Regular I2C-bus slave address
The I2C-bus slave address of the PCA9955 is shown in Figure 3. To conserve power, no
internal pull-up resistors are incorporated on the hardware selectable address pins and
they must be pulled HIGH or LOW externally. Figure 4 shows the I2C-bus slave address of
the PCA9952.
Remark: Reserved I2C-bus addresses must be used with caution since they can interfere
with:
‘reserved for future use’ I2C-bus addresses (0000 011, 1111 1XX)
slave devices that use the 10-bit addressing scheme (1111 0XX)
slave devices that are designed to respond to the General Call address (0000 000)
High-speed mode (Hs-mode) master code (0000 1XX)
The last bit of the address byte defines the operation to be performed. When set to logic 1
a read is selected, while a logic 0 selects a write operation.
7.1.2 LED All Call I2C-bus address
Default power-up value (ALLCALLADR register): E0h or 1110 000X
Programmable through I2C-bus (volatile programming)
At power-up, LED All Call I2C-bus address is enabled. PCA9952/55 sends an ACK
when E0h (R/W = 0) or E1h (R/W = 1) is sent by the master.
See Section 7.3.10 ALLCALLADR, LED All Call I2C-bus address for more detail.
Fig 3. PCA9955 slave address Fig 4. PCA9952 slave address
002aae914
1 1 0 A3 A2 A1 A0 R/W
fixed hardware
selectable
slave address
002aae915
1 1 0 0 A2 A1 A0 R/W
fixed hardware
selectable
slave address
Section 7.3.9 “LED bit Sub Call IZCrbus addresses for PCA9952/55"
PCA9952_PCA9955 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 7.1 — 29 June 2015 10 of 48
NXP Semiconductors PCA9952; PCA9955
16-channel Fm+ I2C-bus 57 mA constant current LED driver
Remark: The default LED All Call I2C-bus address (E0h or 1110 000X) must not be used
as a regular I2C-bus slave address since this address is enabled at power-up. All of the
PCA9952/55s on the I2C-bus will acknowledge the address if sent by the I2C-bus master.
7.1.3 LED bit Sub Call I2C-bus addresses
3 different I2C-bus addresses can be used
Default power-up values:
SUBADR1 register: ECh or 1110 110X
SUBADR2 register: ECh or 1110 110X
SUBADR3 register: ECh or 1110 110X
Programmable through I2C-bus (volatile programming)
At power-up, SUBADR1 is enabled while SUBADR2 and SUBADR3 I2C-bus
addresses are disabled.
Remark: At power-up SUBADR1 identifies this device as a 16-channel driver.
See Section 7.3.9 “LED bit Sub Call I2C-bus addresses for PCA9952/55 for more detail.
Remark: The default LED Sub Call I2C-bus addresses may be used as regular I2C-bus
slave addresses as long as they are disabled.
7.2 Control register
Following the successful acknowledgement of the slave address, LED All Call address or
LED Sub Call address, the bus master will send a byte to the PCA9952/55, which will be
stored in the Control register.
The lowest 7 bits are used as a pointer to determine which register will be accessed
(D[6:0]). The highest bit is used as Auto-Increment Flag (AIF). The AIF is active by default
at power-up.
This bit along with the MODE1 register bit 5 and bit 6 provide the Auto-Increment feature.
When the Auto-Increment Flag is set (AIF = logic 1), the seven low-order bits of the
Control register are automatically incremented after a read or write. This allows the user to
program the registers sequentially. Four different types of Auto-Increment are possible,
depending on AI1 and AI0 values of MODE1 register.
reset state = 80h
Remark: The Control register does not apply to the Software Reset I2C-bus address.
Fig 5. Control register
002aad850
AIF D6 D5 D4 D3 D2 D1 D0
Auto-Increment Flag
register address
n Table 5 Table 6 Table 5
PCA9952_PCA9955 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 7.1 — 29 June 2015 11 of 48
NXP Semiconductors PCA9952; PCA9955
16-channel Fm+ I2C-bus 57 mA constant current LED driver
[1] AI1 and AI0 come from MODE1 register.
Remark: Other combinations not shown in Table 5 (AIF + AI[1:0] = 001b, 010b and 011b)
are reserved and must not be used for proper device operation.
AIF + AI[1:0] = 000b is used when the same register must be accessed several times
during a single I2C-bus communication, for example, changes the brightness of a single
LED. Data is overwritten each time the register is accessed during a write operation.
AIF + AI[1:0] = 100b is used when all the registers must be sequentially accessed, for
example, power-up programming.
AIF + AI[1:0] = 101b is used when the 16 LED drivers must be individually programmed
with different values during the same I2C-bus communication, for example, changing color
setting to another color setting.
AIF + AI[1:0] = 110b is used when MODE1 to IREF15 registers must be programmed with
different settings during the same I2C-bus communication.
AIF + AI[1:0] = 111b is used when the 16 LED drivers must be individually programmed
with different values in addition to global programming.
Only the 7 least significant bits D[6:0] are affected by the AIF, AI1 and AI0 bits.
When the Control register is written, the register entry point determined by D[6:0] is the
first register that will be addressed (read or write operation), and can be anywhere
between 00h and 41h (as defined in Table 6). When AIF = 1, the Auto-Increment Flag is
set and the rollover value at which the register increment stops and goes to the next one
is determined by AIF, AI1 and AI0. See Table 5 for rollover values. For example, if MODE1
register bit AI1 = 0 and AI0 = 1 and if the Control register = 1001 0000, then the register
addressing sequence will be (in hexadecimal):
10 11 19 0A 0B 19 0A 0B … as long as the master
keeps sending or reading data.
If MODE1 register bit AI1 = 0 and AI0 = 0 and if the Control register = 1010 0010, then the
register addressing sequence will be (in hexadecimal):
22 23 41 00 01 19 0A 0B … as long as the master
keeps sending or reading data.
Table 5. Auto-Increment options
AIF AI1[1] AI0[1] Function
0 0 0 no Auto-Increment
1 0 0 Auto-Increment for registers (00h to 41h). D[6:0] roll over to 00h after the last
register 41h is accessed.
1 0 1 Auto-Increment for individual brightness registers only (0Ah to 19h). D[6:0] roll
over to 0Ah after the last register (19h) is accessed.
1 1 0 Auto-Increment for MODE1 to IREF15 control registers (00h to 31h).
D[6:0] roll over to 00h after the last register (31h) is accessed.
1 1 1 Auto-Increment for global control registers and individual brightness registers
(08h to 19h). D[6:0] roll over to 08h after the last register (19h) is accessed.
PCA9952_PCA9955 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 7.1 — 29 June 2015 12 of 48
NXP Semiconductors PCA9952; PCA9955
16-channel Fm+ I2C-bus 57 mA constant current LED driver
If MODE1 register bit AI1 = 0 and AI0 = 1 and if the Control register = 1000 0101, then the
register addressing sequence will be (in hexadecimal):
05 06 19 0A 0B 19 0A 0B … as long as the master
keeps sending or reading data.
Remark: Writing to registers marked ‘not used’ will return NACK.
7.3 Register definitions
Table 6. Register summary[1]
Register
number
(hexadecimal)
D6 D5 D4 D3 D2 D1 D0 Name Type Function
00h 0000000MODE1 read/write Mode register 1
01h 0000001MODE2 read/write Mode register 2
02h 0000010LEDOUT0 read/write LEDn output state 0
03h 0000011LEDOUT1 read/write LEDn output state 1
04h 0000100LEDOUT2 read/write LEDn output state 2
05h 0000101LEDOUT3 read/write LEDn output state 3
06h 0000110- read/write not used[1]
07h 0000111- read/write not used[1]
08h 0001000GRPPWM read/write group duty cycle control
09h 0001001GRPFREQ read/write group frequency
0Ah 0001010PWM0 read/write brightness control LED0
0Bh 0001011PWM1 read/write brightness control LED1
0Ch 0001100PWM2 read/write brightness control LED2
0Dh 0001101PWM3 read/write brightness control LED3
0Eh 0001110PWM4 read/write brightness control LED4
0Fh 0001111PWM5 read/write brightness control LED5
10h 0010000PWM6 read/write brightness control LED6
11h 0010001PWM7 read/write brightness control LED7
12h 0010010PWM8 read/write brightness control LED8
13h 0010011PWM9 read/write brightness control LED9
14h 0010100PWM10 read/write brightness control LED10
15h 0010101PWM11 read/write brightness control LED11
16h 0010110PWM12 read/write brightness control LED12
17h 0010111PWM13 read/write brightness control LED13
18h 0011000PWM14 read/write brightness control LED14
19h 0011001PWM15 read/write brightness control LED15
1Ah to 21h -------- read/write not used[1]
22h 0100010IREF0 read/write output gain control register 0
23h 0100011IREF1 read/write output gain control register 1
24h 0100100IREF2 read/write output gain control register 2
25h 0100101IREF3 read/write output gain control register 3
26h 0100110IREF4 read/write output gain control register 4
PCA9952_PCA9955 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 7.1 — 29 June 2015 13 of 48
NXP Semiconductors PCA9952; PCA9955
16-channel Fm+ I2C-bus 57 mA constant current LED driver
[1] Remark: Writing to registers marked ‘not used’ will return a NACK.
[2] Remark: Writing to registers marked ‘reserved’ will not change any functionality in the chip.
27h 0100111IREF5 read/write output gain control register 5
28h 0101000IREF6 read/write output gain control register 6
29h 0101001IREF7 read/write output gain control register 7
2Ah 0101010IREF8 read/write output gain control register 8
2Bh 0101011IREF9 read/write output gain control register 9
2Ch 0101100IREF10 read/write output gain control register 10
2Dh 0101101IREF11 read/write output gain control register 11
2Eh 0101110IREF12 read/write output gain control register 12
2Fh 0101111IREF13 read/write output gain control register 13
30h 0110000IREF14 read/write output gain control register 14
31h 0110001IREF15 read/write output gain control register 15
32h to 39h -------- read/write not used[1]
3Ah 0111010OFFSET read/write Offset/delay on LEDn outputs
3Bh 0111011SUBADR1 read/write I2C-bus subaddress 1
3Ch 0111100SUBADR2 read/write I2C-bus subaddress 2
3Dh 0111101SUBADR3 read/write I2C-bus subaddress 3
3Eh 0111110ALLCALLADRread/write All Call I2C-bus address
3Fh 0111111RESERVED1 read/write reserved[2]
40h 1000000RESERVED2 read only reserved[2]
41h 1000001RESERVED3 read only reserved[2]
42h 1000010PWMALL write only brightness control for all LEDn
43h 1000011IREFALL write only output gain control for all registers
IREF0 to IREF15
44h 1000100EFLAG0 read only output error flag 0
45h 1000101EFLAG1 read only output error flag 1
46h to 7Fh -------- read only not used[1]
Table 6. Register summary[1] …continued
Register
number
(hexadecimal)
D6 D5 D4 D3 D2 D1 D0 Name Type Function
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Product data sheet Rev. 7.1 — 29 June 2015 14 of 48
NXP Semiconductors PCA9952; PCA9955
16-channel Fm+ I2C-bus 57 mA constant current LED driver
7.3.1 MODE1 — Mode register 1
[1] It takes 500 s max. for the oscillator to be up and running once SLEEP bit has been set to logic 0. Timings on LEDn outputs are not
guaranteed if PWMx, GRPPWM or GRPFREQ registers are accessed within the 500 s window.
[2] No blinking or dimming is possible when the oscillator is off.
[3] The device must be reset if the LED driver output state is set to LDRx=11 after the device is set back to Normal mode.
7.3.2 MODE2 — Mode register 2
Table 7. MODE1 - Mode register 1 (address 00h) bit description
Legend: * default value.
Bit Symbol Access Value Description
7 AIF read only 0 Register Auto-Increment disabled.
1* Register Auto-Increment enabled.
6 AI1 R/W 0* Auto-Increment bit 1 = 0. Auto-increment range as defined in Table 5.
1 Auto-Increment bit 1 = 1. Auto-increment range as defined in Table 5.
5 AI0 R/W 0* Auto-Increment bit 0 = 0. Auto-increment range as defined in Table 5.
1 Auto-Increment bit 0 = 1. Auto-increment range as defined in Table 5.
4 SLEEP R/W 0* Normal mode[1].
1 Low-power mode. Oscillator off[2][3].
3 SUB1 R/W 0 PCA9952; PCA9955 does not respond to I2C-bus subaddress 1.
1* PCA9952; PCA9955 responds to I2C-bus subaddress 1.
2 SUB2 R/W 0* PCA9952; PCA9955 does not respond to I2C-bus subaddress 2.
1 PCA9952; PCA9955 responds to I2C-bus subaddress 2.
1 SUB3 R/W 0* PCA9952; PCA9955 does not respond to I2C-bus subaddress 3.
1 PCA9952; PCA9955 responds to I2C-bus subaddress 3.
0 ALLCALL R/W 0 PCA9952; PCA9955 does not respond to LED All Call I2C-bus address.
1* PCA9952; PCA9955 responds to LED All Call I2C-bus address.
Table 8. MODE2 - Mode register 2 (address 01h) bit description
Legend: * default value.
Bit Symbol Access Value Description
7 OVERTEMP read only 0* O.K.
1 overtemperature condition
6 FAULTTEST R/W 0* LED fault test complete
1 start fault test
5 DMBLNK R/W 0* group control = dimming.
1 group control = blinking.
4 - read only 0* reserved
3 OCH R/W 0* outputs change on STOP command
1 outputs change on ACK
2 - read only 1* reserved
1 - read only 0* reserved
0 - read only 1* reserved
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Product data sheet Rev. 7.1 — 29 June 2015 15 of 48
NXP Semiconductors PCA9952; PCA9955
16-channel Fm+ I2C-bus 57 mA constant current LED driver
7.3.3 LEDOUT0 to LEDOUT3, LED driver output state
LDRx = 00 — LED driver x is off (default power-up state).
LDRx = 01 — LED driver x is fully on (individual brightness and group dimming/blinking
not controlled).
LDRx = 10 — LED driver x individual brightness can be controlled through its PWMx
register.
LDRx = 11 — LED driver x individual brightness and group dimming/blinking can be
controlled through its PWMx register and the GRPPWM registers.
Remark: Setting the device in low power mode while being on group dimming/blinking
mode may cause the LED output state to be in an unknown state after the device is set
back to normal mode. The device must be reset and all register values reprogrammed.
7.3.4 GRPPWM, group duty cycle control
When DMBLNK bit (MODE2 register) is programmed with logic 0, a 122 Hz fixed
frequency signal is superimposed with the 31.25 kHz individual brightness control signal.
GRPPWM is then used as a global brightness control allowing the LEDn outputs to be
dimmed with the same value. The value in GRPFREQ is then a ‘Don’t care’.
Table 9. LEDOUT0 to LEDOUT3 - LED driver output state registers (address 02h to 05h)
bit description
Legend: * default value.
Address Register Bit Symbol Access Value Description
02h LEDOUT0 7:6 LDR3 R/W 00* LED3 output state control
5:4 LDR2 R/W 00* LED2 output state control
3:2 LDR1 R/W 00* LED1 output state control
1:0 LDR0 R/W 00* LED0 output state control
03h LEDOUT1 7:6 LDR7 R/W 00* LED7 output state control
5:4 LDR6 R/W 00* LED6 output state control
3:2 LDR5 R/W 00* LED5 output state control
1:0 LDR4 R/W 00* LED4 output state control
04h LEDOUT2 7:6 LDR11 R/W 00* LED11 output state control
5:4 LDR10 R/W 00* LED10 output state control
3:2 LDR9 R/W 00* LED9 output state control
1:0 LDR8 R/W 00* LED8 output state control
05h LEDOUT3 7:6 LDR15 R/W 00* LED15 output state control
5:4 LDR14 R/W 00* LED14 output state control
3:2 LDR13 R/W 00* LED13 output state control
1:0 LDR12 R/W 00* LED12 output state control
Table 10. GRPPWM - Group brightness control register (address 08h) bit description
Legend: * default value
Address Register Bit Symbol Access Value Description
08h GRPPWM 7:0 GDC[7:0] R/W 1111 1111* GRPPWM register
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Product data sheet Rev. 7.1 — 29 June 2015 16 of 48
NXP Semiconductors PCA9952; PCA9955
16-channel Fm+ I2C-bus 57 mA constant current LED driver
General brightness for the 16 outputs is controlled through 256 linear steps from 00h
(0 % duty cycle = LEDn output off) to FFh (99.6 % duty cycle = maximum brightness).
Applicable to LEDn outputs programmed with LDRx = 11 (LEDOUT0 to LEDOUT3
registers).
When DMBLNK bit is programmed with logic 1, GRPPWM and GRPFREQ registers
define a global blinking pattern, where GRPFREQ contains the blinking period (from
67 ms to 16.8 s) and GRPPWM the duty cycle (ON/OFF ratio in %).
(1)
7.3.5 GRPFREQ, group frequency
GRPFREQ is used to program the global blinking period when DMBLNK bit (MODE2
register) is equal to 1. Value in this register is a ‘Don’t care’ when DMBLNK = 0.
Applicable to LEDn outputs programmed with LDRx = 11 (LEDOUT0 to LEDOUT3
registers).
Blinking period is controlled through 256 linear steps from 00h (67 ms, frequency 15 Hz)
to FFh (16.8 s).
(2)
7.3.6 PWM0 to PWM15, individual brightness control
duty cycle GDC 7:0
256
--------------------------
=
Table 11. GRPFREQ - Group frequency register (address 09h) bit description
Legend: * default value.
Address Register Bit Symbol Access Value Description
09h GRPFREQ 7:0 GFRQ[7:0] R/W 0000 0000* GRPFREQ register
global blinking period GFRQ 7:01+
15.26
----------------------------------------s=
Table 12. PWM0 to PWM15 - PWM registers 0 to 15 (address 0Ah to 19h) bit description
Legend: * default value.
Address Register Bit Symbol Access Value Description
0Ah PWM0 7:0 IDC0[7:0] R/W 0000 0000* PWM0 Individual Duty Cycle
0Bh PWM1 7:0 IDC1[7:0] R/W 0000 0000* PWM1 Individual Duty Cycle
0Ch PWM2 7:0 IDC2[7:0] R/W 0000 0000* PWM2 Individual Duty Cycle
0Dh PWM3 7:0 IDC3[7:0] R/W 0000 0000* PWM3 Individual Duty Cycle
0Eh PWM4 7:0 IDC4[7:0] R/W 0000 0000* PWM4 Individual Duty Cycle
0Fh PWM5 7:0 IDC5[7:0] R/W 0000 0000* PWM5 Individual Duty Cycle
10h PWM6 7:0 IDC6[7:0] R/W 0000 0000* PWM6 Individual Duty Cycle
11h PWM7 7:0 IDC7[7:0] R/W 0000 0000* PWM7 Individual Duty Cycle
12h PWM8 7:0 IDC8[7:0] R/W 0000 0000* PWM8 Individual Duty Cycle
13h PWM9 7:0 IDC9[7:0] R/W 0000 0000* PWM9 Individual Duty Cycle
14h PWM10 7:0 IDC10[7:0] R/W 0000 0000* PWM10 Individual Duty Cycle
15h PWM11 7:0 IDC11[7:0] R/W 0000 0000* PWM11 Individual Duty Cycle
16h PWM12 7:0 IDC12[7:0] R/W 0000 0000* PWM12 Individual Duty Cycle
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Product data sheet Rev. 7.1 — 29 June 2015 17 of 48
NXP Semiconductors PCA9952; PCA9955
16-channel Fm+ I2C-bus 57 mA constant current LED driver
A 31.25 kHz fixed frequency signal is used for each output. Duty cycle is controlled
through 256 linear steps from 00h (0 % duty cycle = LEDn output off) to FFh
(99.6 % duty cycle = LEDn output at maximum brightness). Applicable to LEDn outputs
programmed with LDRx = 10 or 11 (LEDOUT0 to LEDOUT3 registers).
(3)
Remark: The first lower end 8 steps of PWM and the last (higher end) steps of PWM will
not have effective brightness control of LEDs due to edge rate control of LEDn output
pins.
7.3.7 IREF0 to IREF15, LEDn output current value registers
These registers reflect the gain settings for output current for LED0 to LED15.
17h PWM13 7:0 IDC13[7:0] R/W 0000 0000* PWM13 Individual Duty Cycle
18h PWM14 7:0 IDC14[7:0] R/W 0000 0000* PWM14 Individual Duty Cycle
19h PWM15 7:0 IDC15[7:0] R/W 0000 0000* PWM15 Individual Duty Cycle
Table 12. PWM0 to PWM15 - PWM registers 0 to 15 (address 0Ah to 19h) bit description
…continued
Address Register Bit Symbol Access Value Description
duty cycle IDCx 7:0
256
---------------------------
=
Table 13. IREF0 to IREF15 - LEDn output gain control registers (address 22h to 31h)
bit description
Legend: * default value.
Address Register Bit Access Value Description
22h IREF0 7:0 R/W 00h* LED0 output current setting
23h IREF1 7:0 R/W 00h* LED1 output current setting
24h IREF2 7:0 R/W 00h* LED2 output current setting
25h IREF3 7:0 R/W 00h* LED3 output current setting
26h IREF4 7:0 R/W 00h* LED4 output current setting
27h IREF5 7:0 R/W 00h* LED5 output current setting
28h IREF6 7:0 R/W 00h* LED6 output current setting
29h IREF7 7:0 R/W 00h* LED7 output current setting
2Ah IREF8 7:0 R/W 00h* LED8 output current setting
2Bh IREF9 7:0 R/W 00h* LED9 output current setting
2Ch IREF10 7:0 R/W 00h* LED10 output current setting
2Dh IREF11 7:0 R/W 00h* LED11 output current setting
2Eh IREF12 7:0 R/W 00h* LED12 output current setting
2Fh IREF13 7:0 R/W 00h* LED13 output current setting
30h IREF14 7:0 R/W 00h* LED14 output current setting
31h IREF15 7:0 R/W 00h* LED15 output current setting
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Product data sheet Rev. 7.1 — 29 June 2015 18 of 48
NXP Semiconductors PCA9952; PCA9955
16-channel Fm+ I2C-bus 57 mA constant current LED driver
7.3.8 OFFSET — LEDn output delay offset register
The OFFSET register should not be changed while the LEDn output is on and pulsing.
The PCA9955 can be programmed to have turn-on delay between LEDn outputs. This
helps to reduce peak current for the VDD supply and reduces EMI.
The order in which the LEDn outputs are enabled will always be the same (channel 0 will
enable first and channel 15 will enable last).
OFFSET control register bits [3:0] determine the delay used between the turn-on times as
follows:
0000 = no delay between outputs (all on, all off at the same time)
0001 = delay of 1 clock cycle (125 ns) between successive outputs
0010 = delay of 2 clock cycles (250 ns) between successive outputs
0011 = delay of 3 clock cycles (375 ns) between successive outputs
:
1111 = delay of 15 clock cycles (1.875 s) between successive outputs
Example: If the value in the OFFSET register is 1000 the corresponding delay =
8125 ns = 1 s delay between successive outputs.
channel 0 turns on at time 0 s
channel 1 turns on at time 1 s
channel 2 turns on at time 2 s
channel 3 turns on at time 3 s
channel 4 turns on at time 4 s
channel 5 turns on at time 5 s
channel 6 turns on at time 6 s
channel 7 turns on at time 7 s
channel 8 turns on at time 8 s
channel 9 turns on at time 9 s
channel 10 turns on at time 10 s
channel 11 turns on at time 11 s
channel 12 turns on at time 12 s
channel 13 turns on at time 13 s
channel 14 turns on at time 14 s
channel 15 turns on at time 15 s
Table 14. OFFSET - LEDn output delay offset register (address 3Ah) bit description
Legend: * default value.
Address Register Bit Access Value Description
3Ah OFFSET 7:4 read only 0000* not used
3:0 R/W 1000* LEDn output delay offset factor
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Product data sheet Rev. 7.1 — 29 June 2015 19 of 48
NXP Semiconductors PCA9952; PCA9955
16-channel Fm+ I2C-bus 57 mA constant current LED driver
7.3.9 LED bit Sub Call I2C-bus addresses for PCA9952/55
Default power-up values are ECh, ECh, ECh. At power-up, SUBADR1 is enabled while
SUBADR2 and SUBADR3 are disabled. The power-up default bit subaddress of ECh
indicates that this device is a 16-channel LED driver.
All three subaddresses are programmable. Once subaddresses have been programmed
to their right values, SUBx bits need to be set to logic 1 in order to have the device
acknowledging these addresses (MODE1 register) (0). When SUBx is set to logic 1, the
corresponding I2C-bus subaddress can be used during either an I2C-bus read or write
sequence.
7.3.10 ALLCALLADR, LED All Call I2C-bus address
The LED All Call I2C-bus address allows all the PCA9952/55s on the bus to be
programmed at the same time (ALLCALL bit in register MODE1 must be equal to logic 1
(power-up default state)). This address is programmable through the I2C-bus and can be
used during either an I2C-bus read or write sequence. The register address can also be
programmed as a Sub Call.
Only the 7 MSBs representing the All Call I2C-bus address are valid. The LSB in
ALLCALLADR register is a read-only bit (0).
If ALLCALL bit = 0, the device does not acknowledge the address programmed in register
ALLCALLADR.
7.3.11 RESERVED1
This register is reserved.
7.3.12 RESERVED2, RESERVED3
These registers are reserved.
Table 15. SUBADR1 to SUBADR3 - I2C-bus subaddress registers 1 to 3 (address 3Bh to
3Dh) bit description
Legend: * default value.
Address Register Bit Symbol Access Value Description
3Bh SUBADR1 7:1 A1[7:1] R/W 1110 110* I2C-bus subaddress 1
0 A1[0] R only 0* reserved
3Ch SUBADR2 7:1 A2[7:1] R/W 1110 110* I2C-bus subaddress 2
0 A2[0] R only 0* reserved
3Dh SUBADR3 7:1 A3[7:1] R/W 1110 110* I2C-bus subaddress 3
0 A3[0] R only 0* reserved
Table 16. ALLCALLADR - LED All Call I2C-bus address register (address 3Eh) bit
description
Legend: * default value.
Address Register Bit Symbol Access Value Description
3Eh ALLCALLADR 7:1 AC[7:1] R/W 1110 000* ALLCALL I2C-bus
address register
0 AC[0] R only 0* reserved
Eguation 4 Eguafion 5
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Product data sheet Rev. 7.1 — 29 June 2015 20 of 48
NXP Semiconductors PCA9952; PCA9955
16-channel Fm+ I2C-bus 57 mA constant current LED driver
7.3.13 PWMALL — brightness control for all LEDn outputs
When programmed, the value in this register will be used for PWM duty cycle for all the
LEDn outputs and will be reflected in PWM0 through PWM15 registers.
Write to any of the PWM0 to PWM15 registers will overwrite the value in corresponding
PWMn register programmed by PWMALL.
7.3.14 IREFALL register: output current value for all LEDn outputs
The output current setting for all outputs is held in this register. When this register is
written to or updated, all LEDn outputs will be set to a current corresponding to this
register value.
Write to IREF0 to IREF15 will overwrite the output current settings.
7.3.15 LED driver constant current outputs
In LED display applications, PCA9952/55 provides nearly no current variations from
channel to channel and from device to device. The maximum current skew between
channels is less than 6 % and less than 8 % between devices.
7.3.15.1 Adjusting output peak current
The PCA9952/55 scales up the reference current (Iref) set by the external resistor (Rext) to
sink the output current (IO) at each output port. The maximum output peak current for the
outputs can be set using Rext. In addition, the constant value for current drive at each of
the outputs is independently programmable using command registers IREF0 to IREF15.
Alternatively, programming the IREFALL register allows all outputs to be set at one current
value determined by the value in IREFALL register.
Equation 4 and Equation 5 can be used to calculate the minimum and maximum constant
current values that can be programmed for the outputs for a chosen Rext.
(4)
(5)
For a given IREFx setting, .
Table 17. PWMALL - brightness control for all LEDn outputs register (address 42h)
bit description
Legend: * default value.
Address Register Bit Access Value Description
42h PWMALL 7:0 write only 0000 0000* duty cycle for all LEDn outputs
Table 18. IREFALL - Output gain control for all LEDn outputs (address 43h) bit description
Legend: * default value.
Bit Symbol Access Value Description
7:0 IREFALL write only 00h* Current gain setting for all LEDn outputs.
IO_LED_LSB 900 mV
Rext
------------------- 1
4
---
=
IO_LED IREFx 900 mV
Rext
-------------------
1
4
---
=
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Product data sheet Rev. 7.1 — 29 June 2015 21 of 48
NXP Semiconductors PCA9952; PCA9955
16-channel Fm+ I2C-bus 57 mA constant current LED driver
Example 1: If Rext =1k, IO_LED_LSB = 225 A, IO_LED_MAX = 57.375 mA.
So each channel can be programmed with its individual IREFx in 256 steps and in 225 A
increments to a maximum output current of 57.375 mA independently.
Example 2: If Rext =2k, IO_LED_LSB = 112.5 A, IO_LED_MAX = 28.687 mA.
So each channel can be programmed with its individual IREFx in 256 steps and in
112.5 A increments to a maximum output channel of 28.687 mA independently.
IO(LEDn) (mA) = IREFx (0.9 / 4) / Rext (k)
maximum IO(LEDn) (mA) = 255 (0.9 / 4) / Rext (k)
Remark: Default IREFx at power-up = 0.
Fig 6. Maximum ILED versus Rext
(1) Assuming Rext = 1 k.
Fig 7. IO(target) versus IREFx value
R
ext
(kΩ)
1109482
002aag288
0
60
40
20
80
I
O(LEDn)
(mA)
56
IREFx = 255
3 7
IREFx[7:0] value
0 25519112763
002aaf396
20
30
10
40
57.375
(1)
I
O(target)
(mA)
0
31 95 159 223
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Product data sheet Rev. 7.1 — 29 June 2015 22 of 48
NXP Semiconductors PCA9952; PCA9955
16-channel Fm+ I2C-bus 57 mA constant current LED driver
7.3.16 LED error detection
The PCA9952/55 is capable of detecting an LED open or a short condition at its LEDn
output. To detect LED error status, user must initiate the LEDn output fault test. The
LEDout channel under test must be ON to conduct this test.
Setting MODE2[6] = 1 initiates the FAULTTEST. The entire test sequence takes up to
52 s. Once the test cycle begins, all outputs will be turned off (no matter where they are
in the group or individual PWM cycle) until entire test sequence is finished and next
register read or write is activated. Then each output will be enabled at its previously
defined output current level based on IREFx for 1.25 s. Only those channels with an
LEDOUT value other than 00h will be tested. If the output is selected to be fully on,
individual dim, or individual and group dim that channel will be tested; however, its
operation will be affected for one entire 32 s individual PWM cycle. At the end of the test
cycle PCA9952/55 writes out the 16 error flag bits to EFLAGn.
Before reading the error flag register EFLAGn, user should verify if the FAULTTEST is
complete by reading MODE2 register. MODE2[6] = 0 indicates that the test is complete
and the error status is ready in EFLAG0 and EFLAG1.
The error flags in registers EFLAG0 and EFLAG1 can now be read.
Remark: The LED open and short-circuit error status bits share the same error flag
registers (EFLAG0/EFLAG1). If both LED open and short-circuit conditions exist on
different LED outputs, the error status bits in error flag registers report only the
open-circuits first and disregards the short-circuits. If only one of the two conditions (that
is, LED open-circuits or short-circuits) exists, then the error status bits in error flag
registers will report all of those faulted channels. For all unused LED outputs, user must
program their LED outputs to the ‘OFF’ state (LDRx = 00) and IREFx value to 00h, and all
unused LED output pins must be pulled up to VDD with a recommended 100 k shared
resistor. The states of the unused LED channels have no effect upon the FAULTTEST and
always return 0s in EFLAG0/EFLAG1 registers.
7.3.16.1 Open-circuit detection principle
The PCA9952/55 LED open-circuit detection compares the effective current level IO with
the open load detection threshold current Ith(det). If IO is below the threshold Ith(det), the
PCA9952/55 detects an open load condition. This error status can be read out as an
error flag through the registers EFLAG0 and EFLAG1. For open-circuit error detection of
an output channel, that channel must be ON.
Table 19. EFLAG0, EFLAG1 - Error flag registers (address 44h, 45h) bit description
Legend: * default value.
Address Register Bit Access Value Description
44h EFLAG0 7:0 R only 00h* Error flag 0; lower 8-bit channel error status
45h EFLAG1 7:0 R only 00h* Error flag 1; upper 8-bit channel error status
Table 20. Open-circuit detection
State of
output port Condition of
output current Error status code Description
OFF IO= 0 mA 0 detection not possible
ON IO<I
th(det)[1] 1 open-circuit
IOIth(det)[1] channel n error status bit 0 normal
e Table 24 Table 24
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Product data sheet Rev. 7.1 — 29 June 2015 23 of 48
NXP Semiconductors PCA9952; PCA9955
16-channel Fm+ I2C-bus 57 mA constant current LED driver
[1] Ith(det) =0.5IO(target) (typical). This threshold may be different for each I/O and only depends on IREFx and
Rext.
7.3.16.2 Short-circuit detection principle
The LED short-circuit detection compares the effective voltage level (VO) with the
shorted-load detection threshold voltages Vth(trig). If VO is above the Vth(trig) threshold, the
PCA9952/55 detects a shorted-load condition. If VO is below the Vth(trig) threshold, no error
is detected or error bit is reset. This error status can be read out as an error flag through
the registers EFLAG0 and EFLAG1. For short-circuit error detection, a channel must be
on.
[1] Vth 2.5 V.
Remark: The error status does not distinguish between an LED short condition and an
LED open condition. When an LED fault condition is noted, the LEDn outputs should be
turned off to prevent heat dissipation in the chip and the repair should be done.
7.3.17 Overtemperature protection
If the PCA9952/55 chip temperature exceeds its limit (Tth(otp), see Table 24), all output
channels will be disabled until the temperature drops below its limit minus a small
hysteresis (Thys, see Table 24). When an overtemperature situation is encountered, the
OVERTEMP flag (bit 7) is set in the MODE2 register. Once the die temperature reduces
below the Tth(otp) Thys, the chip will return to the same condition it was prior to the
overtemperature event and the OVERTEMP flag will be cleared.
7.4 Active LOW output enable input
Remark: Only the PCA9952 has the OE pin.
The active LOW output enable (OE) pin on PCA9952 allows to enable or disable all the
LEDn outputs at the same time.
When a LOW level is applied to OE pin, all the LEDn outputs are enabled.
When a HIGH level is applied to OE pin, all the LEDn outputs are high-impedance.
The OE pin can be used as a synchronization signal to switch on/off several PCA9952
devices at the same time. This requires an external clock reference that provides blinking
period and the duty cycle.
The OE pin can also be used as an external dimming control signal. The frequency of the
external clock must be high enough not to be seen by the human eye, and the duty cycle
value determines the brightness of the LEDs.
Table 21. Shorted-load detection
State of
output port Condition of
output voltage Error status code Description
OFF - 0 detection not possible
ON VOVth(trig)[1] 1 short-circuit
VO<V
th(trig)[1] channel n error status bit 0 normal
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Product data sheet Rev. 7.1 — 29 June 2015 24 of 48
NXP Semiconductors PCA9952; PCA9955
16-channel Fm+ I2C-bus 57 mA constant current LED driver
Remark: Do not use OE as an external blinking control signal when internal global
blinking is selected (DMBLNK = 1, MODE2 register) since it will result in an undefined
blinking pattern. Do not use OE as an external dimming control signal when internal global
dimming is selected (DMBLNK = 0, MODE2 register) since it will result in an undefined
dimming pattern.
7.5 Power-on reset
When power is applied to VDD, an internal power-on reset holds the PCA9952/55 in a
reset condition until VDD has reached VPOR. At this point, the reset condition is released
and the PCA9952/55 registers and I2C-bus state machine are initialized to their default
states (all zeroes) causing all the channels to be deselected. Thereafter, VDD must be
pulled lower than 1 V and stay LOW for longer than 20 s. The device will reset itself, and
allow 2 ms for the device to fully wake up.
7.6 Hardware reset recovery
When a reset of PCA9952/55 is activated using an active LOW input on the RESET pin, a
reset pulse width of 2.5 s minimum is required. The maximum wait time after RESET pin
is released is 1.5 ms.
7.7 Software reset
The Software Reset Call (SWRST Call) allows all the devices in the I2C-bus to be reset to
the power-up state value through a specific formatted I2C-bus command. To be performed
correctly, it implies that the I2C-bus is functional and that there is no device hanging the
bus.
The maximum wait time after software reset is 1 ms.
The SWRST Call function is defined as the following:
1. A START command is sent by the I2C-bus master.
2. The reserved General Call address ‘0000 000’ with the R/W bit set to ‘0’ (write) is sent
by the I2C-bus master.
3. The PCA9952/55 device(s) acknowledge(s) after seeing the General Call address
‘0000 0000’ (00h) only. If the R/W bit is set to ‘1’ (read), no acknowledge is returned to
the I2C-bus master.
4. Once the General Call address has been sent and acknowledged, the master sends
1 byte with 1 specific value (SWRST data byte 1):
a. Byte 1 = 06h: the PCA9952/55 acknowledges this value only. If byte 1 is not equal
to 06h, the PCA9952/55 does not acknowledge it.
If more than 1 byte of data is sent, the PCA9952/55 does not acknowledge any more.
5. Once the correct byte (SWRST data byte 1) has been sent and correctly
acknowledged, the master sends a STOP command to end the SWRST function: the
PCA9952/55 then resets to the default value (power-up value) and is ready to be
addressed again within the specified bus free time (tBUF).
Vimtzans Fimn N . (o m 255) (FWMX Register L—J 256 x125 ns. 32 Ms {3125 kHz)
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Product data sheet Rev. 7.1 — 29 June 2015 25 of 48
NXP Semiconductors PCA9952; PCA9955
16-channel Fm+ I2C-bus 57 mA constant current LED driver
The I2C-bus master must interpret a non-acknowledge from the PCA9952/55 (at any time)
as a ‘SWRST Call Abort’. The PCA9952/55 does not initiate a reset of its registers. This
happens only when the format of the SWRST Call sequence is not correct.
7.8 Individual brightness control with group dimming/blinking
A 31.25 kHz fixed frequency signal with programmable duty cycle (8 bits, 256 steps) is
used to control individually the brightness for each LED.
On top of this signal, one of the following signals can be superimposed (this signal can be
applied to the 16 LEDn outputs control registers LEDOUT0 to LEDOUT3):
A lower 122 Hz fixed frequency signal with programmable duty cycle (8 bits,
256 steps) is used to provide a global brightness control.
A programmable frequency signal from 15 Hz to every 16.8 seconds (8 bits,
256 steps) with programmable duty cycle (8 bits, 256 steps) is used to provide a
global blinking control.
Fig 8. SWRST Call
0 0 0 0 0 0 0 AS 0
General Call address
START condition acknowledge
from slave
002aac900
SWRST data byte 1
A
acknowledge
from slave
P
STOP
condition
00001100
Minimum pulse width for LEDn Brightness Control is 125 ns.
Minimum pulse width for Group Dimming is 32 s.
When M = 1 (GRPPWM register value), the resulting LEDn Brightness Control + Group Dimming signal will have 1 pulse of the
LED Brightness Control signal (pulse width = N 125 ns, with ‘N’ defined in PWMx register).
This resulting Brightness + Group Dimming signal above shows a resulting Control signal with M = 8.
Fig 9. Brightness + Group Dimming signals
123456789101112 251252253254255256 1234567891011
Brightness Control signal (LEDn)
M × 256 × 125 ns
with M = (0 to 255)
(GRPPWM Register)
N × 125 ns
with N = (0 to 255)
(PWMx Register)
256 × 125 ns = 32 μs
(31.25 kHz)
1234567812345678
Group Dimming signal
resulting Brightness + Group Dimming signal
256 × 256 × 125 ns = 8.19 ms (122 Hz)
002aaf935
Fi ure10 6 Figure 11 6 Pi we 12
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Product data sheet Rev. 7.1 — 29 June 2015 26 of 48
NXP Semiconductors PCA9952; PCA9955
16-channel Fm+ I2C-bus 57 mA constant current LED driver
8. Characteristics of the I2C-bus
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 10).
8.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 11).
8.2 System configuration
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 12).
Fig 10. Bit transfer
mba607
data line
stable;
data valid
change
of data
allowed
SDA
SCL
Fig 11. Definition of START and STOP conditions
mba608
SDA
SCL P
STOP condition
S
START condition
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Product data sheet Rev. 7.1 — 29 June 2015 27 of 48
NXP Semiconductors PCA9952; PCA9955
16-channel Fm+ I2C-bus 57 mA constant current LED driver
8.3 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up time and hold
time must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Fig 12. System configuration
002aaa966
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
SDA
SCL
I2C-BUS
MULTIPLEXER
SLAVE
Fig 13. Acknowledgement on the I2C-bus
002aaa987
S
START
condition
9821
clock pulse for
acknowledgement
not acknowledge
acknowledge
data output
by transmitter
data output
by receiver
SCL from master
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Product data sheet Rev. 7.1 — 29 June 2015 28 of 48
NXP Semiconductors PCA9952; PCA9955
16-channel Fm+ I2C-bus 57 mA constant current LED driver
9. Bus transactions
(1) Slave address shown for PCA9955.
(2) See Table 6 for register definition.
Fig 14. Write to a specific register
1 0 A3 A2 A1 A0 0 AS 1
slave address
(1)
START condition R/W
acknowledge
from slave
002aae918
data for register D[7:0]
(2)
D6 D5 D4 D3 D2 D1 D0X
control register
Auto-Increment flag
A
acknowledge
from slave
A
acknowledge
from slave
P
STOP
condition
(1) Slave address shown for PCA9955.
(2) AI1, AI0 = 00. See Table 5 for Auto-Increment options.
Remark: Care should be taken to load the appropriate value here in the AI1 and AI0 bits of the MODE1 register for
programming the part with the required Auto-Increment options.
Fig 15. Write to all registers using the Auto-Increment feature
1 0 A3 A2 A1 A0 0 AS 1
slave address(1)
START condition R/W
acknowledge
from slave
002aae919
MODE1 register data(2)
0 0 0 0 0 0 01
control register
Auto-Increment on
A
acknowledge
from slave
A
acknowledge
from slave
P
STOP
condition
(cont.)
(cont.)
MODE1
register selection
MODE2 register data
A
acknowledge
from slave
ALLCALLADR register data
A
acknowledge
from slave
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
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Product data sheet Rev. 7.1 — 29 June 2015 29 of 48
NXP Semiconductors PCA9952; PCA9955
16-channel Fm+ I2C-bus 57 mA constant current LED driver
This example assumes that AIF + AI[1:0] = 101b.
(1) Slave address shown for PCA9955.
Fig 16. Multiple writes to Individual Brightness registers only using the Auto-Increment feature
1 0 A3 A2 A1 A0 0 AS 1
slave address
(1)
START condition R/W
acknowledge
from slave
002aae920
PWM0 register data
0 0 0 1 0 1 01
control register
Auto-Increment on
A
acknowledge
from slave
A
acknowledge
from slave
P
STOP
condition
(cont.)
(cont.)
PWM0
register selection
PWM1 register data
A
acknowledge
from slave
PWM14 register data
A
acknowledge
from slave
PWM15 register data
A
acknowledge
from slave
PWM0 register data
A
acknowledge
from slave
register rollover
PWM14 register data
A
acknowledge
from slave
PWM15 register data
A
acknowledge
from slave
T 1
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Product data sheet Rev. 7.1 — 29 June 2015 30 of 48
NXP Semiconductors PCA9952; PCA9955
16-channel Fm+ I2C-bus 57 mA constant current LED driver
This example assumes that the MODE1[5] = 0 and MODE1[6] = 0.
(1) Slave address shown for PCA9955.
Fig 17. Read all registers using the Auto-Increment feature
1 0 A3 A2 A1 A0 0 AS 1
slave address
(1)
START condition R/W
acknowledge
from slave
002aae921
0 0 0 0 0 0 01
control register
Auto-Increment on
A
acknowledge
from slave
(cont.)
(cont.)
MODE1
register selection
data from MODE1 register
A
acknowledge
from master
Sr
ReSTART
condition
1 0 A3 A2 A1 A0 1 A1
slave address
(1)
R/W
acknowledge
from slave
data from MODE2 register
A
acknowledge
from master
data from LEDOUT0
A
acknowledge
from master
data from
EFLAG1 register
A
acknowledge
from master
data from
MODE1 register
A
acknowledge
from master
(cont.)
(cont.)
data from last read byte
A
not acknowledge
from master
P
STOP
condition
Remark: A read operation can be done without doing a write operation before it. In this case, the data sent out is from the
register pointed to by the control register (written to during the last write operation) with the Auto-Increment options in the
MODE1 register (written to during the last write operation).
(1) Slave address shown for PCA9955.
Fig 18. Read of registers
1 0 A3 A2 A1 A0 1 AS 1
slave address
(1)
START condition R/W
002aae922
data from register
A
acknowledge
from master
data from register
A
no acknowledge
from master
data from register
acknowledge
from slave
P
STOP
condition
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Product data sheet Rev. 7.1 — 29 June 2015 31 of 48
NXP Semiconductors PCA9952; PCA9955
16-channel Fm+ I2C-bus 57 mA constant current LED driver
(1) Slave address shown for PCA9955.
(2) In this example, several PCA9955s are used and the same sequence (A) (above) is sent to each of them.
(3) ALLCALL bit in MODE1 register is previously set to 1 for this example.
(4) OCH bit in MODE2 register is previously set to 1 for this example.
Fig 19. LED All Call I2C-bus address programming and LED All Call sequence example
1 0 A3 A2 A1 A0 0 AS 1
slave address(1)(2)
START condition R/W
acknowledge
from slave
002aae923
0 1 1 1 1 1 01
control register
Auto-Increment on
A
acknowledge
from slave
ALLCALLADR
register selection
0 1 0 1 0 1 X1
new LED All Call I2C address(3)
P
STOP condition
A
acknowledge
from slave
0 1 0 1 0 1 0 AS 1
LED All Call I2C address
START condition R/W
acknowledge
from the 4 devices
0 0 0 0 0 1 01
control register
A
acknowledge
from the 4 devices
LEDOUT0
register selection
1 0 1 0 1 0 10
LEDOUT0 register (LED fully ON)
P
STOP condition
A
the 16 LEDs are on at the acknowledge(4)
sequence (A)
sequence (B) (cont.)
(cont.) 1 0 1 0 1 0 10
LEDOUT1 register (LED fully ON)
A
the 16 LEDs are on
at the acknowledge(4)
1 0 1 0 1 0 10
LEDOUT2 register (LED fully ON)
A
the 16 LEDs are on
at the acknowledge(4)
acknowledge
from the 4 devices
acknowledge
from the 4 devices
acknowledge
from the 4 devices
1 0 1 0 1 0 10
LEDOUT3 register (LED fully ON)
A
the 16 LEDs are on
at the acknowledge(4)
acknowledge
from the 4 devices
Auto-Increment on
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Product data sheet Rev. 7.1 — 29 June 2015 32 of 48
NXP Semiconductors PCA9952; PCA9955
16-channel Fm+ I2C-bus 57 mA constant current LED driver
10. Application design-in information
10.1 Thermal considerations
Since the PCA9952/55 device integrates 16 linear current sources, thermal
considerations should be taken into account to prevent overheating, which can cause the
device to go into thermal shutdown.
Perhaps the major contributor for device’s overheating is the LED forward voltage
mismatch. This is because it can cause significant voltage differences between the LED
strings of the same type (e.g., 2 V to 3 V), which ultimately translates into higher power
dissipation in the device. The voltage drop across the LED channels of the device is given
by the difference between the supply voltage and the LED forward voltage of each LED
(1) A standard 10 k pull-up resistor is required to obtain the best system level ESD performance.
Fig 20. Typical application (PCA9955)
PCA9955
LED0SDA
SCL
VDD = 3.3 V or 5.0 V
I2C-BUS/SMBus
MASTER
SDA
SCL
1.6 kΩ 1.6 kΩ
A0
A1
A2
VDD
A3
VSS
002aae924
VSS
RESETRESET
REXT
ISET
up to 40 V
LED1
LED2
LED3
LED4
LED5
LED6
LED7
LED8
LED9
LED10
LED11
LED12
LED13
LED14
LED15
C
10 μF
1.1 kΩ
(optional)
10 kΩ(1)
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Product data sheet Rev. 7.1 — 29 June 2015 33 of 48
NXP Semiconductors PCA9952; PCA9955
16-channel Fm+ I2C-bus 57 mA constant current LED driver
string. Reducing this to a minimum (e.g., 0.8 V) helps to keep the power dissipation down.
Therefore LEDs binning is recommended to minimize LED voltage forward variation and
reduce power dissipation in the device.
In order to ensure that the device will not go into thermal shutdown when operating under
certain application conditions, its junction temperature (Tj) should be calculated to ensure
that is below the overtemperature threshold limit (125 C). The Tj of the device depends
on the ambient temperature (Tamb), device’s total power dissipation (Ptot), and thermal
resistance.
The device junction temperature can be calculated by using the following equation:
(6)
where:
Tj = junction temperature
Tamb = ambient temperature
Rth(j-a) = junction to ambient thermal resistance
Ptot = (device) total power dissipation
An example of this calculation is show below:
Conditions:
Tamb = 50 C
Rth(j-a) = 31 C/W (per JEDEC 51 standard for multilayer PCB)
ILED = 50 mA / channel
IDD(max) = 12 mA
VDD = 5 V
LEDs per channel = 10 LEDs / channel
LED VF(typ) = 3 V per LED (30 V total for 10 LEDs in series)
LED VF mismatch = 0.2 V per LED (2 V total for 10 LEDs in series)
Vreg(drv) = 0.8 V (This will be present only in the LED string with the highest LED forward
voltage.)
Vsup = LED VF(typ) + LED VF mismatch + Vreg(drv) = 30 V + 2 V + 0.8 V = 32.8 V
Ptot calculation:
Ptot = IC_power + LED drivers_power;
IC_power = (IDD VDD) + [(SCL_VOL IOL) + (SDA_VOL IOL)]
IC_power = (0.012 A 5V) + [(0.4V0.03 A) + (0.4 V 0.03 A)] = 0.084 W
LED drivers_power = [(16 1) (ILED)(LED VF mismatch + Vreg(drv))] +
(ILED Vreg(drv))
LED drivers_power = [15 0.05 A (2 V + 0.8 V)] + (0.05 A 0.8 V) = 2.14 W
Ptot = 0.084 W + 2.14 W = 2.224 W
TjTamb Rth j-aPtot
+=
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Product data sheet Rev. 7.1 — 29 June 2015 34 of 48
NXP Semiconductors PCA9952; PCA9955
16-channel Fm+ I2C-bus 57 mA constant current LED driver
Tj calculation:
Tj = Tamb + Rth(j-a) Ptot
Tj = 50 C + (31 C/W 2.224 W) = 118.94 C
This confirms that the junction temperature is below the minimum overtemperature
threshold of 125 C, which ensures the device will not go into thermal shutdown under
these conditions.
It is important to mention that the value of the thermal resistance junction-to-ambient
(Rth(j-a)) strongly depends in the PCB design. Therefore, the thermal pad of the device
should be attached to a big enough PCB copper area to ensure proper thermal dissipation
(similar to JEDEC 51 standard). Several thermal vias in the PCB thermal pad should be
used as well to increase the effectiveness of the heat dissipation (e.g., 15 thermal vias).
The thermal vias should be distributed evenly in the PCB thermal pad.
Finally it is important to point out that this calculation should be taken as a reference only
and therefore evaluations should still be performed under the application environment and
conditions to confirm proper system operation.
11. Limiting values
[1] Class II, Level B for A1 (pin 3), A2 (pin 4). All other pins are Class II, Level A (100 mA).
12. Thermal characteristics
[1] Per JEDEC 51 standard for multilayer PCB.
Table 22. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDD supply voltage 0.5 +6.0 V
VI/O voltage on an input/output pin VSS 0.5 5.5 V
Vdrv(LED) LED driver voltage VSS 0.5 40 V
IO(LEDn) output current on pin LEDn - 65 mA
ISS ground supply current - 1.0 A
Ilu latch-up current JESD [1] -90mA
Ptot total power dissipation Tamb =25C-3.2W
Tamb =85C-1.3W
Tstg storage temperature 65 +150 C
Tamb ambient temperature operating
PCA9952TW, PCA9955TW 20 +85 C
PCA9952TW/Q900, PCA9955TW/Q900 40 +85 C
Tjjunction temperature 20 +125 C
Table 23. Thermal characteristics
Symbol Parameter Conditions Typ Unit
Rth(j-a) thermal resistance from junction to ambient HTSSOP28 [1] 31 C/W
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Product data sheet Rev. 7.1 — 29 June 2015 35 of 48
NXP Semiconductors PCA9952; PCA9955
16-channel Fm+ I2C-bus 57 mA constant current LED driver
13. Static characteristics
Table 24. Static characteristics
VDD = 3 V to 5.5 V; VSS =0V; T
amb =
20
Cto+85
C (PCA9952TW, PCA9955TW);
Tamb =
40
Cto+85
C (PCA9952TW/Q900, PCA9955TW/Q900); unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Supply
VDD supply voltage 3 - 5.5 V
IDD supply current on pin VDD; operating mode; no load;
fSCL =1MHz
VDD =3.3V - 6.5 14 mA
VDD =5.5V - 7.0 15 mA
IDD supply current Rext = open; LED[15:0] = off - 0.7 14 mA
Rext =2k; LED[15:0] = off - 2 14 mA
Rext =1k; LED[15:0] = off - 3 15 mA
Rext =2k; LED[15:0] = on - 2 15 mA
Rext =1k; LED[15:0] = on - 3 16 mA
Istb standby current on pin VDD; no load; fSCL =0Hz;
MODE1[4] = 1; VI=V
DD
VDD = 3.3 V - 100 600 A
VDD = 5.5 V - 100 700 A
VPOR power-on reset voltage no load; VI=V
DD or VSS - 2.65 2.8 V
VPDR power-down reset voltage no load; VI=V
DD or VSS [1] 0.8 1.25 - V
Input SCL; input/output SDA
VIL LOW-level input voltage 0.5 - +0.3VDD V
VIH HIGH-level input voltage 0.7VDD -5.5V
IOL LOW-level output current VOL =0.4V; V
DD =3V 20 - - mA
VOL =0.4V; V
DD =5.0V 30 - - mA
ILleakage current VI=V
DD or VSS 1- +1 A
Ciinput capacitance VI=V
SS - 6 10 pF
Current controlled outputs (LED[15:0])
IOoutput current VO= 0.8 V; IREFx = FFh
Rext =1k52 57.5 62 mA
Rext =2k25.5 28.5 31.5 mA
IOoutput current variation VO= 0.8 V; IREFx = FFh
between bits (different ICs,
same channel); Rext =1k
-2.5 8%
between bits (2 channels, same IC);
Rext =2k
-1.7 5.8 %
Vreg(drv) driver regulation voltage minimum regulation voltage;
IREFx = FFh; Rext =1k
0.8 1.0 40 V
IL(off) off-state leakage current VO=40V 1.0 - +1 A
Vth(L) LOW-level threshold voltage open LED protection; Error flag will trip
during verification test if VOVth(L)
-0.35- V
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Product data sheet Rev. 7.1 — 29 June 2015 36 of 48
NXP Semiconductors PCA9952; PCA9955
16-channel Fm+ I2C-bus 57 mA constant current LED driver
[1] VDD must be lowered to 0.8 V in order to reset part.
14. Dynamic characteristics
Vth(H) HIGH-level threshold voltage short LED protection; Error flag will trip
during verification test if VOVth(H)
-2.5- V
Address inputs, OE input (PCA9952 only), RESET input
VIL LOW-level input voltage 0.5 - +0.3VDD V
VIH HIGH-level input voltage 0.7VDD -5.5V
ILI input leakage current 1- +1 A
Ciinput capacitance - 3.7 5 pF
Overtemperature protection
Tth(otp) overtemperature protection
threshold temperature rising 125 145 160 C
hysteresis - 20 - C
Table 24. Static characteristics …continued
VDD = 3 V to 5.5 V; VSS =0V; T
amb =
20
Cto+85
C (PCA9952TW, PCA9955TW);
Tamb =
40
Cto+85
C (PCA9952TW/Q900, PCA9955TW/Q900); unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Table 25. Dynamic characteristics
Symbol Parameter Conditions Standard-mode
I2C-bus Fast-mode
I2C-bus Fast-mode
Plus I2C-bus Unit
Min Max Min Max Min Max
fSCL SCL clock frequency 0 100 0 400 0 1000 kHz
tBUF bus free time between a STOP
and START condition 4.7 - 1.3 - 0.5 - s
tHD;STA hold time (repeated) START
condition 4.0 - 0.6 - 0.26 - s
tSU;STA set-up time for a repeated
START condition 4.7 - 0.6 - 0.26 - s
tSU;STO set-up time for STOP condition 4.0 - 0.6 - 0.26 - s
tHD;DAT data hold time 0 - 0 - 0 - ns
tVD;ACK data valid acknowledge time [1] 0.3 3.45 0.1 0.9 0.05 0.45 s
tVD;DAT data valid time [2] 0.3 3.45 0.1 0.9 0.05 0.45 s
tSU;DAT data set-up time 250 - 100 - 50 - ns
tLOW LOW period of the SCL clock 4.7 - 1.3 - 0.5 - s
tHIGH HIGH period of the SCL clock 4.0 - 0.6 - 0.26 - s
tffall time of both SDA and SCL
signals
[3][4] -30020+0.1C
b[5] 300 - 120 ns
trrise time of both SDA and SCL
signals - 1000 20 + 0.1Cb[5] 300 - 120 ns
tSP pulse width of spikes that must
be suppressed by the input filter
[6] -50 - 50-50ns
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16-channel Fm+ I2C-bus 57 mA constant current LED driver
[1] tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
[2] tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.
[3] A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to
bridge the undefined region of SCL’s falling edge.
[4] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time (tf) for the SDA output stage is specified at
250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without
exceeding the maximum specified tf.
[5] Cb= total capacitance of one bus line in pF.
[6] Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
[7] Load resistor (RL) for LEDn is 100 pull-up to VDD.
tw(rst) reset pulse width 2.5 - 2.5 - 2.5 - s
tPLH LOW to HIGH propagation
delay OE to LEDn
disable
[7] - 1.2 - 1.2 - 1.2 s
tPHL HIGH to LOW propagation
delay OE to LEDn
enable
[7] - 1.2 - 1.2 - 1.2 s
Table 25. Dynamic characteristics …continued
Symbol Parameter Conditions Standard-mode
I2C-bus Fast-mode
I2C-bus Fast-mode
Plus I2C-bus Unit
Min Max Min Max Min Max
Fig 21. Definition of timing
t
SP
t
BUF
t
HD;STA
PP S
t
LOW
t
r
t
HD;DAT
t
f
t
HIGH
t
SU;DAT
t
SU;STA
Sr
t
HD;STA
t
SU;STO
SDA
SCL
002aaa986
0.7 × V
DD
0.3 × V
DD
0.7 × V
DD
0.3 × V
DD
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Product data sheet Rev. 7.1 — 29 June 2015 38 of 48
NXP Semiconductors PCA9952; PCA9955
16-channel Fm+ I2C-bus 57 mA constant current LED driver
15. Test information
Rise and fall times refer to VIL and VIH.
Fig 22. I2C-bus timing diagram
SCL
SDA
t
HD;STA
t
SU;DAT
t
HD;DAT
t
f
t
BUF
t
SU;STA
t
LOW
t
HIGH
t
VD;ACK
002aab285
t
SU;STO
protocol
START
condition
(S)
bit 7
MSB
(A7)
bit 6
(A6)
bit 1
(D1)
bit 0
(D0)
1
/ f
SCL
t
r
t
VD;DAT
acknowledge
(A)
STOP
condition
(P)
0.3 × V
DD
0.7 × V
DD
0.3 × V
DD
0.7 × V
DD
Fig 23. Output propagation delay
002aag604
OE
tPLH
output data
tPHL
RL = Load resistor for LEDn. RL for SDA = 165 (30 mA or less current).
CL = Load capacitance includes jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generators.
Fig 24. Test circuitry for switching times
PULSE
GENERATOR
V
O
CL
50 pF
RL
50 Ω
002aag289
RT
V
I
V
DD
DUT
V
LED
open
V
SS
,,,,,,,,,,, U‘ m HHHHHHWHHHHHHH JDL - |:I g© We
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Product data sheet Rev. 7.1 — 29 June 2015 39 of 48
NXP Semiconductors PCA9952; PCA9955
16-channel Fm+ I2C-bus 57 mA constant current LED driver
16. Package outline
Fig 25. Package outline SOT1172-2 (HTSSOP28)
References
Outline
version European
projection Issue date
IEC JEDEC JEITA
SOT1172-2 - - -
MO-153
- - -
sot1172-2_po
Unit
mm max
nom
min
1.1 0.15
0.10
0.05 0.25 0.30
0.22
0.19
9.8
9.7
9.6
5.6
5.5
5.4
A
Dimensions
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
HTSSOP28: plastic thermal enhanced thin shrink small outline package; 28 leads;
body width 4.4 mm; lead pitch 0.65 mm; exposed die pad SOT1172-2
A1A2
0.95
0.90
0.85
A3bp
0.75
0.62
0.50
0.40
0.37
0.3 0.2
LpQvc
0.20
0.15
0.10
D(1) DhE(2)
4.5
4.4
4.3
Eh
2.3
2.2
2.1
e
0.65 1.0
6.6
6.4
6.2
HEL
0.1
0.80
0.63
0.50
8°
4°
0°
yZθ
0.13
w
0 2.5 5 mm
scale
yexposed die pad side
D
Dh
Z
bpw
Eh
e
pin 1 index
141
28 15
detail X
Q
A
A3
θ
A1
A2
Lp
L
c
X
HEvA
EA
10-07-06
10-07-13
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16-channel Fm+ I2C-bus 57 mA constant current LED driver
17. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling ensure that the appropriate precautions are taken as
described in JESD625-A or equivalent standards.
18. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
18.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
18.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
Through-hole components
Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
18.3 Wave soldering
Key characteristics in wave soldering are:
Figure 26 Table 26 g Figure 26
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Product data sheet Rev. 7.1 — 29 June 2015 41 of 48
NXP Semiconductors PCA9952; PCA9955
16-channel Fm+ I2C-bus 57 mA constant current LED driver
Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
Solder bath specifications, including temperature and impurities
18.4 Reflow soldering
Key characteristics in reflow soldering are:
Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 26) than a SnPb process, thus
reducing the process window
Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 26 and 27
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 26.
Table 26. SnPb eutectic process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350 350
< 2.5 235 220
2.5 220 220
Table 27. Lead-free process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350 350 to 2000 > 2000
< 1.6 260 260 260
1.6 to 2.5 260 250 245
> 2.5 250 245 245
mamum peak hamperature = MSL hymn damage \eve\ mmmum peak |emperature = mwmmum soldenng |emperamre
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Product data sheet Rev. 7.1 — 29 June 2015 42 of 48
NXP Semiconductors PCA9952; PCA9955
16-channel Fm+ I2C-bus 57 mA constant current LED driver
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
MSL: Moisture Sensitivity Level
Fig 26. Temperature profiles for large and small components
001aac844
temperature
time
minimum peak temperature
= minimum soldering temperature
maximum peak temperature
= MSL limit, damage level
peak
temperature
i %
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Product data sheet Rev. 7.1 — 29 June 2015 43 of 48
NXP Semiconductors PCA9952; PCA9955
16-channel Fm+ I2C-bus 57 mA constant current LED driver
19. Soldering: PCB footprints
Fig 27. PCB footprint for SOT1172-2 (HTSSOP28); reflow soldering
',0(16,216LQPP
$\ %\ ' ' *\ +\3
   
&
  
*[

+[

627)RRWSULQWLQIRUPDWLRQIRUUHIORZVROGHULQJRI+76623SDFNDJH
3

6/\

Q63\
Q63[
636\

636[

6/[

63[WRW

63\WRW

63[

63\

RFFXSLHGDUHD
VROGHUODQGSOXVVROGHUSDVWH
VROGHUODQG
VRWBIU
,VVXHGDWH 


*\ $\
&
6/\ 63\WRW
%\+\
3
6/[
'
'
[
63\
63[
Q63[
63[WRW
636[
3
*[
+[

636\
Q63\
*HQHULFIRRWSULQWSDWWHUQ
5HIHUWRWKHSDFNDJHRXWOLQHGUDZLQJIRUDFWXDOOD\RXW
PCA9952_PCA9955 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 7.1 — 29 June 2015 44 of 48
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16-channel Fm+ I2C-bus 57 mA constant current LED driver
20. Abbreviations
21. References
[1] AN10897, “A guide to designing for ESD and EMC” — NXP Semiconductors
[2] AN11131, “How to improve system level ESD performance”
NXP Semiconductors
Table 28. Abbreviations
Acronym Description
ACK Acknowledge
CDM Charged-Device Model
DAC Digital-to-Analog Converter
DUT Device Under Test
EMI ElectroMagnetic Interference
ESD ElectroStatic Discharge
HBM Human Body Model
I2C-bus Inter-Integrated Circuit bus
LED Light Emitting Diode
LSB Least Significant Bit
MSB Most Significant Bit
PCB Printed-Circuit Board
PWM Pulse Width Modulation
RGB Red/Green/Blue
RGBA Red/Green/Blue/Amber
SMBus System Management Bus
Section 7.3.3 “LEDOUTO lo LEDOUTS, LED driver output slate" Table 7 “MODEI - Mode register1 (address 00h) bll description" d Table note 3 Section 2 “Features and benefits" Section 3 “Agglications" Table 1 “Ordering information" Table 2 “Ordering ogtions" Fi ure 2 “Pin confi uration for HTSSOP28“ Table 22 “Limiting values" Table 24 “Static characteristics"
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Product data sheet Rev. 7.1 — 29 June 2015 45 of 48
NXP Semiconductors PCA9952; PCA9955
16-channel Fm+ I2C-bus 57 mA constant current LED driver
22. Revision history
Table 29. Revision history
Document ID Release date Data sheet status Change
notice Supersedes
PCA9952_PCA9955 v.7.1 20150629 Product data sheet - PCA9952_PCA9955 v.7
Modifications: Section 7.3.3 “LEDOUT0 to LEDOUT3, LED driver output state: added remark.
Table 7 MODE1 - Mode register 1 (address 00h) bit description: added Table
note [3].
PCA9952_PCA9955 v.7 20130527 Product data sheet - PCA9952_PCA9955 v.6
PCA9952Q900_PCA9955Q900 v.1
Modifications: Section 2 “Features and benefits:
bullet item for operating temperature re-written to indicate different temperature
ranges for PCA9952/55 and PCA9952/55/Q900
bullet item for ESD protection re-written to indicate different CDM voltages for
PCA9952/55 and PCA9952/55/Q900
Section 3 “Applications: added (new) seventh bullet item
Table 1 Ordering information: added type numbers PCA9952TW/Q900 and
PCA9955TW/Q900
Table 2 Ordering options: added type numbers PCA9952TW/Q900 and
PCA9955TW/Q900
Figure 2 “Pin configuration for HTSSOP28: added type numbers
PCA9952TW/Q900 and PCA9955TW/Q900
Table 22 “Limiting values: added ambient temperature range for type numbers
PCA9952TW/Q900 and PCA9955TW/Q900
Table 24 “Static characteristics:
appended “(PCA9952TW, PCA9955TW)” to phrase “Tamb =20 Cto+85C”
in descriptive line below table title
added phrase “Tamb =40 Cto+85C (PCA9952TW/Q900,
PCA9955TW/Q900)” to descriptive line below table title
PCA9952Q900_PCA9955Q900 v.1 20130426 Product data sheet - -
PCA9952_PCA9955 v.6 20130422 Product data sheet - PCA9952_PCA9955 v.5
PCA9952_PCA9955 v.5 20121001 Product data sheet - PCA9952_PCA9955 v.4
PCA9952_PCA9955 v.4 20120813 Product data sheet - PCA9952_PCA9955 v.3
PCA9952_PCA9955 v.3 20120418 Product data sheet - PCA9952_PCA9955 v.2
PCA9952_PCA9955 v.2 20120312 Product data sheet - PCA9952_PCA9955 v.1
PCA9952_PCA9955 v.1 20111202 Product data sheet - -
PCA9952_PCA9955 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 7.1 — 29 June 2015 46 of 48
NXP Semiconductors PCA9952; PCA9955
16-channel Fm+ I2C-bus 57 mA constant current LED driver
23. Legal information
23.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
23.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
23.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
hug :l/www. nxgcom salesaddresses®nx9£0m
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Product data sheet Rev. 7.1 — 29 June 2015 47 of 48
NXP Semiconductors PCA9952; PCA9955
16-channel Fm+ I2C-bus 57 mA constant current LED driver
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
23.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP Semiconductors N.V.
24. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors PCA9952; PCA9955
16-channel Fm+ I2C-bus 57 mA constant current LED driver
© NXP Semiconductors N.V. 2015. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 29 June 2015
Document identifier: PCA9952_PCA9955
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
25. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 2
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 4
4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4
5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 6
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7
7 Functional description . . . . . . . . . . . . . . . . . . . 9
7.1 Device addresses . . . . . . . . . . . . . . . . . . . . . . . 9
7.1.1 Regular I2C-bus slave address. . . . . . . . . . . . . 9
7.1.2 LED All Call I2C-bus address . . . . . . . . . . . . . . 9
7.1.3 LED bit Sub Call I2C-bus addresses. . . . . . . . 10
7.2 Control register. . . . . . . . . . . . . . . . . . . . . . . . 10
7.3 Register definitions . . . . . . . . . . . . . . . . . . . . . 12
7.3.1 MODE1 — Mode register 1 . . . . . . . . . . . . . . 14
7.3.2 MODE2 — Mode register 2 . . . . . . . . . . . . . . 14
7.3.3 LEDOUT0 to LEDOUT3, LED driver output
state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.3.4 GRPPWM, group duty cycle control . . . . . . . . 15
7.3.5 GRPFREQ, group frequency . . . . . . . . . . . . . 16
7.3.6 PWM0 to PWM15, individual brightness
control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.3.7 IREF0 to IREF15, LEDn output current
value registers . . . . . . . . . . . . . . . . . . . . . . . . 17
7.3.8 OFFSET — LEDn output delay offset register 18
7.3.9 LED bit Sub Call I2C-bus addresses for
PCA9952/55 . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.3.10 ALLCALLADR, LED All Call I2C-bus address. 19
7.3.11 RESERVED1 . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.3.12 RESERVED2, RESERVED3 . . . . . . . . . . . . . 19
7.3.13 PWMALL — brightness control for all LEDn
outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.3.14 IREFALL register: output current value for
all LEDn outputs . . . . . . . . . . . . . . . . . . . . . . . 20
7.3.15 LED driver constant current outputs . . . . . . . . 20
7.3.15.1 Adjusting output peak current. . . . . . . . . . . . . 20
7.3.16 LED error detection . . . . . . . . . . . . . . . . . . . . 22
7.3.16.1 Open-circuit detection principle . . . . . . . . . . . 22
7.3.16.2 Short-circuit detection principle. . . . . . . . . . . . 23
7.3.17 Overtemperature protection . . . . . . . . . . . . . . 23
7.4 Active LOW output enable input . . . . . . . . . . . 23
7.5 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 24
7.6 Hardware reset recovery . . . . . . . . . . . . . . . . 24
7.7 Software reset. . . . . . . . . . . . . . . . . . . . . . . . . 24
7.8 Individual brightness control with group
dimming/blinking . . . . . . . . . . . . . . . . . . . . . . 25
8 Characteristics of the I2C-bus . . . . . . . . . . . . 26
8.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.1.1 START and STOP conditions. . . . . . . . . . . . . 26
8.2 System configuration . . . . . . . . . . . . . . . . . . . 26
8.3 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 27
9 Bus transactions. . . . . . . . . . . . . . . . . . . . . . . 28
10 Application design-in information. . . . . . . . . 32
10.1 Thermal considerations . . . . . . . . . . . . . . . . . 32
11 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 34
12 Thermal characteristics . . . . . . . . . . . . . . . . . 34
13 Static characteristics . . . . . . . . . . . . . . . . . . . 35
14 Dynamic characteristics. . . . . . . . . . . . . . . . . 36
15 Test information . . . . . . . . . . . . . . . . . . . . . . . 38
16 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 39
17 Handling information . . . . . . . . . . . . . . . . . . . 40
18 Soldering of SMD packages. . . . . . . . . . . . . . 40
18.1 Introduction to soldering. . . . . . . . . . . . . . . . . 40
18.2 Wave and reflow soldering. . . . . . . . . . . . . . . 40
18.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 40
18.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 41
19 Soldering: PCB footprints . . . . . . . . . . . . . . . 43
20 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 44
21 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
22 Revision history . . . . . . . . . . . . . . . . . . . . . . . 45
23 Legal information . . . . . . . . . . . . . . . . . . . . . . 46
23.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 46
23.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
23.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 46
23.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 47
24 Contact information . . . . . . . . . . . . . . . . . . . . 47
25 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

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