ATF16V8CZ Datasheet by Microchip Technology

View All Related Products | Download PDF Datasheet
A IIIEI. 41m
Features
Industry-standard Architecture
Emulates Many 20-pin PALs
Low-cost Easy-to-use Software Tools
High-speed Electrically-erasable Programmable Logic Devices
12 ns Maximum Pin-to-pin Delay
Low-power - 5 µA (Typ) Standby Current
CMOS and TTL Compatible Inputs and Outputs
Input and I/O Pin Keeper Circuits
Advanced Flash Technology
– Reprogrammable
100% Tested
High-reliability CMOS Process
20 Year Data Retention
100 Erase/Write Cycles
2,000V ESD Protection
200 mA Latchup Immunity
Commercial and Industrial Temperature Ranges
Dual-in-line and Surface Mount Packages in Standard Pinouts
PCI-compliant
Green (Pb/Halide-free/RoHS Compliant) Package Options Available
1. Description
The ATF16V8CZ is a high-performance EECMOS programmable logic device that uti-
lizes Atmel’s proven electrically-erasable Flash memory technology. Speeds down to
12 ns and a 5 µA (Typ) edge-sensing power-down mode are offered. All speed ranges
are specified over the full 5V ±10% range for industrial temperature ranges; 5V ±5%
for commercial range 5-volt devices.
The ATF16V8CZ incorporates a superset of the generic architectures, which allows
direct replacement of the 16R8 family and most 20-pin combinatorial PLDs. Eight out-
puts are each allocated eight product terms. Three different modes of operation,
configured automatically with software, allow highly complex logic functions to be
realized.
The ATF16V8CZ can significantly reduce total system power, thereby enhancing sys-
tem reliability and reducing power supply costs. When all the inputs and internal
nodes are not switching, supply current drops to less than 5 µA typically. This auto-
matic power-down feature (or sleep mode) allows for power savings in slow clock
systems and asynchronous applications. Also, the pin-keeper circuits eliminate the
need for internal pull-up resistors along with their attendant power consumption.
High-
performance
EE PLD
ATF16V8CZ
0453H–PLD–7/05
1n \NPuT P‘NS PROGRAMMABLE \NTERCONNECT AND COMBWATOR‘AL LOG‘C ARRAY LOG‘C oPfloN w” m a mumps, _; Figure 2-2. DIP/SOIC wcm:< an:="" hi:2o="" w:="" \2|:3="" m:="" m:4="" w:="" m:5="" us:="" 5:5="" ‘5:="" \gl:7="" w:="" m:a="" ‘3:="" m:g="" ‘2:="" endi:m="" h:|="" _="" \,/="" [i="" 20]="" :2="" 193="" :3="" m:="" up="" 17]="" mm="" 153="" 5:5="" 153="" mm="" m]="" web=""><3] mm="" 123="" gndeio="" h3="" 7="" a="" v0="" p‘ns="">
2
0453H–PLD–7/05
ATF16V8CZ
Figure 1-1. Block Diagram
2. Pin Configuration and Pinouts
Figure 2-1. TSSOP
Figure 2-2. DIP/SOIC
Table 2-1. Pinouts - All Pinouts Top View
Pin Name Function
CLK Clock
I Logic Inputs
I/O Bi-directional Buffers
OE Output Enable
VCC +5V Supply
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
I/CLK
I1
I2
I3
I4
I5
I6
I7
I8
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I9/OE
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
I/CLK
I1
I2
I3
I4
I5
I6
I7
I8
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I9/OE
o: 9 W99 nzo E A IIIEI. uAsaHJLDJ/os
3
0453H–PLD–7/05
ATF16V8CZ
Figure 2-3. PLCC
4
5
6
7
8
18
17
16
15
14
I3
I4
I5
I6
I7
I/O
I/O
I/O
I/O
I/O
3
2
1
20
19
9
10
11
12
13
I8
GND
I9/OE
I/O
I/O
I2
I1
I/CLK
VCC
I/O
3. Absolute Maximum Ratings*
Temperature Under Bias.................................. -40°C to +85°C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Note: 1. Minimum voltage is -0.6V DC, which may under-
shoot to -2.0V for pulses of less than 20 ns.
Maximum output pin voltage is VCC +0.75VDC,
which may overshoot to 7.0V for pulses of less
than 20 ns.
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V(1)
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
4. DC and AC Operating Conditions
Commercial Industrial
Operating Temperature (Ambient) 0°C - 70°C -40°C - 85°C
VCC Power Supply 5V ±5% 5V ±10%
4.1 DC Characteristics
Symbol Parameter Condition Min Typ Max Units
IIL Input or I/O Low Leakage Current 0 VIN VIL(Max) -10 µA
IIH Input or I/O High Leakage Current 3.5 VIN VCC 10 µA
ICC1 Power Supply Current 15 MHz, VCC = Max,
VIN = 0, VCC, Outputs Open
Com 95 mA
Ind. 105 mA
ICC(1) Power Supply Current,
Standby Mode
0 MHz, VCC = Max,
VIN = 0, VCC, Outputs Open
Com. 5 µA
Ind 5 µA
IOS Output Short Circuit Current VOUT = 0.5V;
VCC= 5V; TA = 25°C -150 mA
VIL Input Low Voltage Min < VCC < Max -0.5 0.8 V
VIH Input High Voltage 2.0 VCC+1 V
VOL Output Low Voltage VCC = Min, All Outputs
IOL = -16 mA Com, Ind. 0.5 V
Jill—EL
4
0453H–PLD–7/05
ATF16V8CZ
Note: 1. All ICC parameters measured with outputs open. Data is based on Atmel test patterns. Reading may vary with pattern.
VOH Output High Voltage VCC = Min
IOL = -3.2 mA 2.4 V
IOL Output Low Current VCC = Min Com. 24 mA
Ind. 12
IOH Output High Current VCC = Min Com., Ind. 4 mA
4.1 DC Characteristics
Symbol Parameter Condition Min Typ Max Units
\NPUTS‘ l/O REG FEEDBACK CLK REG‘STERED OUTPUTS COMB‘NATOFHAL OUTPUTS ‘tPD ‘ H‘GHZ OUTPUT VALH: VAUD .7 IER, 4. LEA, * TH ' \w «00 ' , OUTPUT OUTPUT OUTPUT VAUD VAUD E |PXZ HIGHZ xPZX OUTPUT VALID
5
0453H–PLD–7/05
ATF16V8CZ
4.2 AC Waveforms(1)
Note: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
4.3 AC Characteristics
Symbol Parameter
-12 -15
UnitsMin Max Min Max
tPD Input or Feedback to Non-registered Output 3 12 3 15 ns
tCF Clock to Feedback 6 8 ns
tCO Clock to Output 2 8 2 10 ns
tSInput or Feedback Setup Time 10 12 ns
tHInput Hold Time 0 0 ns
tPClock Period 12 16 ns
tWClock Width 6 8 ns
fMAX
External Feedback 1/(tS + tCO)5545MHz
Internal Feedback 1/(tS + tCF)6250MHz
No Feedback 1/(tP)8362MHz
tEA Input to Output Enable – Product Term 3 12 3 15 ns
tER Input to Output Disable – Product Term 2 15 2 15 ns
tPZX OE pin to Output Enable 2 12 2 15 ns
tPXZ OE pin to Output Disable 1.5 12 1.5 15 ns
E 3.0V AC AC DRIV‘NG 1 5V , MEASUREMENT LEVELs \ LEVEL u.ov \ 5.0V R‘ = 300 OUTPUT PIN R2 : 390 CL = 50pF
6
0453H–PLD–7/05
ATF16V8CZ
4.4 Input Test Waveforms
4.4.1 Input Test Waveforms and Measurement Levels
tR, tF < 1.5 ns (10% to 90%)
4.4.2 Output Test Loads
Note: Similar devices are tested with slightly different loads. These load differences may affect output
signals' delay and slew rate. Atmel devices are tested with sufficient margins to meet compatible
devices.
4.4.3 Pin Capacitance
Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100%
tested.
Table 4-1. Pin Capacitance (f = 1 MHz, T = 25°C(1))
Typ Max Units Conditions
CIN 58 pF V
IN = 0V
COUT 68 pF V
OUT = 0V
POWER REG‘STERED OUTPUTS CLOCK VRST ‘7 ‘FR «‘5 PM E
7
0453H–PLD–7/05
ATF16V8CZ
4.5 Power-up Reset
The ATF16V8CZ’s registers are designed to reset during power-up. At a point delayed slightly
from VCC crossing VRST, all registers will be reset to the low state. As a result, the registered out-
put state will always be high on power-up.
This feature is critical for state machine initialization. However, due to the asynchronous nature
of reset and the uncertainty of how VCC actually rises in the system, the following conditions are
required:
1. The VCC rise must be monotonic, from below 0.7V,
2. After reset occurs, all input and feedback setup times must be met before driving the
clock term high, and
3. The signals from which the clock is derived must remain stable during tPR.
4.6 Preload of Registered Outputs
The ATF16V8CZ’s registers are provided with circuitry to allow loading of each register with
either a high or a low. This feature will simplify testing since any state can be forced into the reg-
isters to control test sequencing. A JEDEC file with preload is generated when a source file with
vectors is compiled. Once downloaded, the JEDEC file preload sequence will be done automati-
cally by approved programmers.
5. Security Fuse Usage
A single fuse is provided to prevent unauthorized copying of the ATF16V8CZ fuse patterns.
Once programmed, fuse verify and preload are inhibited. However, the 64-bit User Signature
remains accessible.
The security fuse should be programmed last, as its effect is immediate.
Parameter Description Typ Max Units
tPR Power-up Reset Time 600 1,000 ns
VRST Power-up Reset Voltage 3.8 4.5 V
E mnK \NPUT - H/Fo/ ._> 4< esd="" pnmmm="" 6chqu="" van="" 0e="" 4.="" a="" 1an="" \nput="" 4—0="" \e—ih="" ,7="">
8
0453H–PLD–7/05
ATF16V8CZ
6. Input and I/O Pin-keeper Circuits
The ATF16V8CZ contains internal input and I/O pin-keeper circuits. These circuits allow each
ATF16V8CZ pin to hold its previous value even when it is not being driven by an external source
or by the device’s output buffer. This helps insure that all logic array inputs are at known, valid
logic levels. This reduces system power by preventing pins from floating to indeterminate levels.
By using pin-keeper circuits rather than pull-up resistors, there is no DC current required to hold
the pins in either logic state (high or low).
These pin-keeper circuits are implemented as weak feedback inverters, as shown in the Input
Diagram below. These keeper circuits can easily be overdriven by standard TTL- or CMOS-com-
patible drivers. The typical overdrive current required is 40 µA.
Figure 6-1. Input Diagram
Figure 6-2. I/O Diagram
41m
9
0453H–PLD–7/05
ATF16V8CZ
7. Functional Logic Diagram Description
The Logic Option and Functional Diagrams describe the ATF16V8CZ architecture. Eight config-
urable macrocells can be configured as a registered output, combinatorial I/O, combinatorial
output, or dedicated input.
The ATF16V8CZ can be configured in one of three different modes. Each mode makes the
ATF16V8CZ look like a different device. Most PLD compilers can choose the right mode auto-
matically. The user can also force the selection by supplying the compiler with a mode selection.
The determining factors would be the usage of register versus combinatorial outputs and dedi-
cated outputs versus outputs with output enable control.
The ATF16V8CZ universal architecture can be programmed to emulate many 20-pin PAL
devices. These architectural subsets can be found in each of the configuration modes described
in the following pages. The user can download the listed subset device JEDEC programming file
to the PLD programmer, and the ATF16V8CZ can be configured to act like the chosen device.
Check with your programmer manufacturer for this capability.
Unused product terms are automatically disabled by the compiler to decrease power consump-
tion. A security fuse, when programmed, protects the content of the ATF16V8CZ. Eight bytes
(64 fuses) of User Signature are accessible to the user for purposes such as storing project
name, part number, revision, or date. The User Signature is accessible regardless of the state of
the security fuse.
Notes: 1. Only applicable for version 3.4 or lower.
Table 7-1. Compiler Mode Selection
Registered Complex Simple Auto Select
ABEL, Atmel-ABEL P16C8R P16V8C P16V8AS P16V8
CUPL G16V8MS G16V8MA G16V8AS G16V8A
LOG/iC GAL16V8_R(1) GAL16V8_C7(1) GAL16V8_C8(1) GAL16V8
OrCAD-PLD “Registered” “Complex” “Simple” GAL16V8A
PLDesigner P16V8R P16V8C P16V8C P16V8A
Tango-PLD G16V8R G16V8C G16V8AS G16V8
Jill—EL
10
0453H–PLD–7/05
ATF16V8CZ
8. Macrocell Configuration
Software compilers support the three different OMC modes as different device types. These
device types are listed in the table below. Most compilers have the ability to automatically select
the device type, generally based on the register usage and output enable (OE) usage. Register
usage on the device forces the software to choose the registered mode. All combinatorial out-
puts with OE controlled by the product term will force the software to choose the complex mode.
The software will choose the simple mode only when all outputs are dedicated combinatorial
without OE control. The different device types listed in the table can be used to override the
automatic device selection by the software. For further details, refer to the compiler software
manuals.
When using compiler software to configure the device, the user must pay special attention to the
following restrictions in each mode.
In registered mode pin 1 and pin 11 are permanently configured as clock and output enable,
respectively. These pins cannot be configured as dedicated inputs in the registered mode.
In complex mode pin 1 and pin 11 become dedicated inputs and use the feedback paths of pin
19 and pin 12 respectively. Because of this feedback path usage, pin 19 and pin 12 do not have
the feedback option in this mode.
In simple mode all feedback paths of the output pins are routed via the adjacent pins. In doing
so, the two inner most pins (pins 15 and 16) will not have the feedback option as these pins are
always configured as dedicated combinatorial output.
8.1 ATF16V8CZ Registered Mode
PAL Device Emulation/PAL Replacement. The registered mode is used if one or more regis-
ters are required. Each macrocell can be configured as either a registered or combinatorial
output or I/O, or as an input. For a registered output or I/O, the output is enabled by the OE pin,
and the register is clocked by the CLK pin. Eight product terms are allocated to the sum term.
For a combinatorial output or I/O, the output enable is controlled by a product term, and seven
product terms are allocated to the sum term. When the macrocell is configured as an input, the
output enable is permanently disabled.
Any register usage will make the compiler select this mode. The following registered devices can
be emulated using this mode:
16R8 16RP8
16R6 16RP6
16R4 16RP4
A lllEl
11
0453H–PLD–7/05
ATF16V8CZ
Figure 8-1. Registered Configuration for Registered Mode(1)(2)
Notes: 1. Pin 1 controls common CLK for the registered outputs.
Pin 11 controls common OE for the registered outputs.
Pin 1 and Pin 11 are permanently configured as CLK and OE.
2. The development software configures all the architecture control bits and checks for proper pin
usage automatically.
Figure 8-2. Combinatorial Configuration for Registered Mode(1)(2)
Notes: 1. Pin 1 and Pin 11 are permanently configured as CLK and OE.
2. The development software configures all the architecture control bits and checks for proper pin
usage automatically.
CLK 1 T )4? 9 r’»—L;r 12 INPUT LINES 16 20 24 25 OUTPUT LOGW OUTPUT LOGW OUTPUT LOGD OUTPUT LOGD OUTPUT LOGW OUTPUT LOGW OUTPUT LOGW OUTPUT LOGW 19 1B 17 16 15 14 12 H
12
0453H–PLD–7/05
ATF16V8CZ
Figure 8-3. Registered Mode Logic Diagram
Pm: ‘2 and w do m have tms muck Dam E
13
0453H–PLD–7/05
ATF16V8CZ
8.2 ATF16V8CZ Complex Mode
PAL Device Emulation/PAL Replacement. In the complex mode, combinatorial output and I/O
functions are possible. Pins 1 and 11 are regular inputs to the array. Pins 13 through 18 have pin
feedback paths back to the AND-array, which makes full I/O capability possible. Pins 12 and 19
(outermost macrocells) are outputs only. They do not have input capability. In this mode, each
macrocell has seven product terms going to the sum term and one product term enabling the
output.
Combinatorial applications with an OE requirement will make the compiler select this mode. The
following devices can be emulated using this mode:
16L8
16H8
16P8
Figure 8-4. Complex Mode Option
9. ATF16V8CZ Simple Mode
PAL Device Emulation/PAL Replacement. In the Simple Mode, 8 product terms are allocated
to the sum term. Pins 15 and 16 (center macrocells) are permanently configured as combinato-
rial outputs. Other macrocells can be either inputs or combinatorial outputs with pin feedback to
the AND-array. Pins 1 and 11 are regular inputs.
The compiler selects this mode when all outputs are combinatorial without OE control. The fol-
lowing simple PALs can be emulated using this mode:
10L8 10H8 10P8
12L6 12H6 12P6
14L4 14H4 14P4
16L2 16H2 16P2
sv XOR K m ‘5 m vs 4» m m“ m amm pm ‘ , Plus 15 and ‘e ave a‘ways enab‘ed E
14
0453H–PLD–7/05
ATF16V8CZ
Figure 9-1. Simple Mode Option
0
1
INPUTLWES 12 16 A1IlI—EI. III-I-I-W OUTPUT LOGW OUTPUT LOGB OUTPUT LOGW OUTPUT LOGE OUTPUT LOGW OUTPUT LOGW OUTPUT LOGW OUTPUT LOGW I9 13 17 16 15 14 I3 12 H
15
0453H–PLD–7/05
ATF16V8CZ
Figure 9-2. Complex Mode Logic Diagram
\NPUTUNES 12 T5 20 OUTPUT LOGm OUTPUT LOSE OUTPUT LOGm OUTPUT LOGm OUTPUT LOSE OUTPUT LOSE OUTPUT LOGm OUTPUT LOGm
16
0453H–PLD–7/05
ATF16V8CZ
Figure 9-3. Simple Mode Logic Diagram
TCC mA NORM ICC mA IOL mA so 75 so 45 so «5 o SUPPLY CURRENT VS. INPUT FREQUENCY ATEIsvacz (vcc : 5V. TA : 25"C) 0 To 20 an m so so 70 m an ma 1 1 105 T mas as 0.85 05 33 31 30 FREQUENCY (MHZ) NORMALIZED SUPPLY CURRENT vs AMBTENT TEMPERATURE (VCC : 5V STANDBY) a" 25' 75‘ AMBT ENT TEMPERATURE (C) OUTPUT SINK CURRENT VS. SUPPLY VOLTAGE (TA : 25°C. VOL : 0 45V) / / 4 5 4.75 5 5 25 5 5 SUPPLY VOLTAGE (v) E NORMALIZED SUPPLY CURRENT VS SUPPLY VOLTAGE (TA : 25%: STANDBY) T T 105 NORM m m T 0 95 0.9 0 85 A75 5 5 25 SUPPLY VOLTAGE (V) OUTPUT SOURCE CURRENT vs. SUPPLY VOLTAGE (VOH : 2.4V. TA : 25°C) 40 720 IOH mA 730 .40 '50 4.5 4 75 5 5.25 5.5 SUPPLY VOLTAGE (V) OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE TVOH : 2.4V, TA : 25°C) 0 40 -20 -30 TOH mA .40 -50 rec .70 Vac 790 4 no 0051152253354455 OUTPUT VOLTAGE (V) «n
17
0453H–PLD–7/05
ATF16V8CZ
9.1 Test Characterization Data
TOL mA NORM ‘Pn NORM ‘co E OUTPUT SINK CURRENT VS OUTPUT VOLTAGE (vcc : 5V TA : 25$) so so 70 so 50 40 so 20 T u o a 0TD2030405060JOEDQ T T.TT2(3T4T§ OUTPUT VOLTAGE (v) NORMALIZED (PD VS. AMBTENT TEMPERATURE (TA : 25°C) T 2 TT 0 9 0 8 a” 25w 75' AMBTENT TEMPERATURE (C) NORMALTZED :60 VS AMBIENT TEMPERATURE (VCC : SVT 1 2 T.T ( 0 9 O B o~ 25~ 75v AMBT ENT TEMPERATURE (C) NORM Two NORM (co NORM NORMALIZED 1PD VS SUPPLV VOLTAGE (TA : 25”C) T 06 T 04 I 02 T 0 53 0 SE 4.5 n5 5 525 5 s SUPPLY VOLTAGE (V) NORMALIZED Tm VS SUPPLV VOLTAGE (TA : 25"C) 1 m I 02 T \ 0 98 0 96 4 5 4 75 5 5 25 5 5 SUPPLY VOLTAGE (v) NORMALIZED 15 VS SUPPLV VOLTAGE (TA : 25C) T 05 T 04 T 02 T 0.98 O 96 O 54 o 92 4.75 5 5 25 SUPPLY VOLTAGE (v)
18
0453H–PLD–7/05
ATF16V8CZ
NORMALIZED ‘5 VS AMBIENT TEMPERATURE (TA : 25°C) I 2 I 1 NORM l5 1 o 9 o s o~ 25~ 75~ AMB‘ENT TEMPERATURE (C) NORMALIZED ‘H Vs AMBIENT TEMPERATURE (VCC : 5V) 1 I5 1 I I 05 NORM L4 1 o 95 o s o as 0” 25° 75' AMBIENT TEMPERATURE (C) INPUT CURRENT vs INPUT VOLTAGE (VCC : 5M TA : 25‘0) mo 75 5o INPUT 25 CURRENT 0 “A -25 750 -75 4 co o I 2 a A 5 6 INPUT VOLTAGE (V) E NORMALIZED TH VS suPPLv VOLTAGE (TA : 25$) ‘18 L09 NORM ‘H 1 0.91 0.82 4 7S 5 5.25 SUPPLY VOLTAGE (V) INPUT CLAMP CURRENT vs INPUT VOLTAGE (TA : 25°C, vcc : 5V) 0 45 INPUT '30 CURRENT ,45 mA 760 ,75 790 o -.I -2 73 -4 75 is -7 re VS -1 \NPUT VOLTAGE (V) JV
19
0453H–PLD–7/05
ATF16V8CZ
Jill—EL
20
0453H–PLD–7/05
ATF16V8CZ
10. Ordering Information
Note: Shaded parts are being obsoleted in Q3-05 and being replaced by Green parts.
10.2 Using “C” Product for Industrial
To use commercial product for Industrial temperature ranges, down-grade one speed grade
from the “I” to the “C” device (7 ns “C” = 10 ns “I”) and de-rate power by 30%.
10.1 Standard Package Options
tPD
(ns)
tS
(ns)
tCO
(ns) Ordering Code Package Operation Range
12 10 8
ATF16V8CZ-12JC
ATF16V8CZ-12PC
ATF16V8CZ-12SC
ATF16V8CZ-12XC
20J
20P3
20S
20X
Commercial
(0°C to 70°C)
15
12 10
ATF16V8CZ-15JC
ATF16V8CZ-15PC
20J
20P3
20S
20X
Commercial
(0°C to 70°C)
ATF16V8CZ-15SC
ATF16V8CZ-15XC
12 10
ATF16V8CZ-15JI
ATF16V8CZ-15PI
20J
20P3
20S
20X
Industrial
(-40°C to 85°C)
ATF16V8CZ-15SI
ATF16V8CZ-15XI
10.3 Green Package Options (Pb/Halide-free/RoHS Compliant)
tPD
(ns)
tS
(ns)
tCO
(ns) Ordering Code Package Operation Range
15 12 10
ATF16V8CZ-15JU
ATF16V8CZ-15PU
ATF16V8CZ-15SU
ATF16V8CZ-15XU
20J
20P3
20S
20X
Industrial
(-40°C to 85°C)
Package Type
20J 20-lead, Plastic J-leaded Chip Carrier (PLCC)
20P3 20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
20S 20-lead, 0.300" Wide, Plastic Gull-wing Small Outline (SOIC)
20X 20-lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP)
JJJJJJ ”W \H m LJUJL i d g 3:] LL NHL T am ATE;
21
0453H–PLD–7/05
ATF16V8CZ
11. Package Information
11.1 20J – PLCC
2325 Orchard Parkway
San Jose, CA 95131
R
TITLE DRAWING NO. REV.
Notes: 1. This package conforms to JEDEC reference MS-018, Variation AA.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
A 4.191 – 4.572
A1 2.286 3.048
A2 0.508
D 9.779 – 10.033
D1 8.890 9.042 Note 2
E 9.779 – 10.033
E1 8.890 9.042 Note 2
D2/E2 7.366 8.382
B 0.660 – 0.813
B1 0.330 0.533
e 1.270 TYP
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
1.14(0.045) X 45˚ PIN NO. 1
IDENTIFIER
1.14(0.045) X 45˚
0.51(0.020)MAX
0.318(0.0125)
0.191(0.0075)
A2
45˚ MAX (3X)
A
A1
B1 D2/E2
B
e
E1 E
D1
D
20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC) B
20J
10/04/01
m
22
0453H–PLD–7/05
ATF16V8CZ
11.2 20P3 – PDIP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
20P3, 20-lead (0.300"/7.62 mm Wide) Plastic Dual
Inline Package (PDIP) D
20P3
1/23/04
PIN
1
E1
A1
B
E
B1
C
L
SEATING PLANE
A
D
e
eB
eC
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A – 5.334
A1 0.381
D 24.892 – 26.924 Note 2
E 7.620 8.255
E1 6.096 7.112 Note 2
B 0.356 – 0.559
B1 1.270 1.551
L 2.921 – 3.810
C 0.203 0.356
eB – 10.922
eC 0.000 1.524
e 2.540 TYP
Notes: 1. This package conforms to JEDEC reference MS-001, Variation AD.
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
HHHHHHHHHH 41m ATE;
23
0453H–PLD–7/05
ATF16V8CZ
11.3 20S – SOIC
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
20S, 20-lead, 0.300" Body, Plastic Gull Wing Small Outline (SOIC) B
20S
10/23/03
7.60 (0.2992)
7.40 (0.2914)
0.51(0.020)
0.33(0.013)
10.65 (0.419)
10.00 (0.394)
PIN 1 ID
1.27 (0.050) BSC
13.00 (0.5118)
12.60 (0.4961)
0.30(0.0118)
0.10 (0.0040)
2.65 (0.1043)
2.35 (0.0926)
0º ~ 8º
1.27 (0.050)
0.40 (0.016)
0.32 (0.0125)
0.23 (0.0091)
PIN 1
Dimensions in Millimeters and (Inches).
Controlling dimension: Inches.
JEDEC Standard MS-013
s so (0 255 s 60 (.260) 6 40 (252) 1 20 (o 047) M 7 O 65 ( 0256) 550 o 15 (c. 006) \ SEAT‘NG u. so (u. 012) o 05 (c. 002) PLANE 0.19 (0.007) o. 20 (o. 003) ,—_ o. 09 (o. 004) o..75(o osoL‘ L 1 0450013) 10/23/ TITLE DRAWING NO. RE 2325 Orchard Parkway . A MEL San Jose, CA 95131 20X, V(Forrvnerly gOT), 20-lead,v4.4 mm Body Wldlh, 20X C — Plasllc Thin Shrunk Small Oulllne Package (TSSOP)
24
0453H–PLD–7/05
ATF16V8CZ
11.4 20X – TSSOP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
20X, (Formerly 20T), 20-lead, 4.4 mm Body Width,
Plastic Thin Shrink Small Outline Package (TSSOP) C
20X
10/23/03
6.60 (.260)
6.40 (.252) 1.20 (0.047) MAX
0.65 (.0256) BSC
0.20 (0.008)
0.09 (0.004)
0.15 (0.006)
0.05 (0.002)
INDEX MARK
6.50 (0.256)
6.25 (0.246)
SEATING
PLANE
4.50 (0.177)
4.30 (0.169)
PIN
1
0.75 (0.030)
0.45 (0.018)
0º ~ 8º
0.30 (0.012)
0.19 (0.007)
Dimensions in Millimeters and (Inches).
Controlling dimension: Millimeters.
JEDEC Standard MO-153 AC
41m
25
0453H–PLD–7/05
ATF16V8CZ
12. Revision History
12.1 0453H
1. Green Package options added in 2005.
41m —@
Printed on recycled paper.
0453H–PLD–7/05
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any
intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-
TIONS OF SALE LOCATED ON ATMELS WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY
WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-
TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT
OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no
representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications
and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided
otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use
as components in applications intended to support or sustain life.
Atmel Corporation Atmel Operations
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Regional Headquarters
Europe
Atmel Sarl
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
Tel: (41) 26-426-5555
Fax: (41) 26-426-5500
Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimshatsui
East Kowloon
Hong Kong
Tel: (852) 2721-9778
Fax: (852) 2722-1369
Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Memory
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
Microcontrollers
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
Tel: (33) 2-40-18-18-18
Fax: (33) 2-40-18-19-60
ASIC/ASSP/Smart Cards
Zone Industrielle
13106 Rousset Cedex, France
Tel: (33) 4-42-53-60-00
Fax: (33) 4-42-53-60-01
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Fax: 1(719) 540-1759
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
Tel: (44) 1355-803-000
Fax: (44) 1355-242-743
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Fax: 1(719) 540-1759
Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom
Avenue de Rochepleine
BP 123
38521 Saint-Egreve Cedex, France
Tel: (33) 4-76-58-30-00
Fax: (33) 4-76-58-34-80
Literature Requests
www.atmel.com/literature
© Atmel Corporation 2005. All rights reserved. Atmel®, logo and combinations thereof, Everywhere You Are® and others, are registered trade-
marks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.

Products related to this Datasheet

IC PLD 8MC 15NS 20DIP
IC PLD 8MC 15NS 20SOIC
IC PLD 8MC 15NS 20TSSOP
IC PLD 8MC 15NS 20PLCC