LT3507 Datasheet by Analog Devices Inc.

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L7L|nt “I2 LT3507 TECHNOLOGY
LT3507
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Features
applications
Description
Triple Monolithic Step-Down
Regulator with LDO
The LT
®
3507 is a triple, current mode, DC/DC converter
with internal power switches and a low dropout regulator.
The switching converters are step-down converters capable
of generating one 2.4A output and two 1.5A outputs. All
three converters are synchronized to a single oscillator.
The 2.4A output runs with opposite phase to the other two
converters, reducing input ripple current. Each regulator
has independent shutdown and soft-start circuits, and
generates a power good signal when its output is in regu-
lation, easing power supply sequencing and interfacing
with microcontrollers and DSPs.
The switching frequency is set with a single resistor yielding
a range of 250kHz to 2.5MHz. The high switching frequency
allows the use of small inductors and capacitors resulting
in a very small triple output supply. The constant switching
frequency, combined with low impedance ceramic capaci-
tors, results in low, predictable output ripple. With its wide
input voltage range of 4V to 36V, the LT3507 regulates
a broad array of power sources including 5V logic rails,
unregulated wall transformers, lead acid batteries and
distributed power supplies.
n Wide Input Range: 4V to 36V
n One 2.4A and Two 1.5A Output Switching
Regulators with Internal Power Switches
n Low Dropout Linear Regulator with External
Transistor
n Antiphase Switching Reduces Ripple
n Independent Run, Tracking/Soft-Start, and Power
Good Indicators Ease Supply Sequencing
n Uses Small Inductors and Ceramic Capacitors
n Adjustable, 250kHz to 2.5MHz Switching Frequency,
Synchronizable Over the Full Range
n User Programmable Overvoltage and Undervoltage
Lockouts
n Thermally Enhanced, 38-Lead 5mm × 7mm QFN
Package
n DSL and Cable Modems
n Distributed Power Regulation
n DSP Power
n Automotive
typical application
VIN1
BOOST1
BOOST3
SW3
FB3
VC3
BIAS
DRIVE
FB4
SW1
FB1
VC1
BOOST2
0.22µF
10.2k
53.6k
VIN
6V TO 36V
VOUT3
5V
1.5A
VIN2 VIN3
SW2
FB2
VC2
GND
LT3507
22µF
24.3k
3507 TA01a
107k 11.5k
VOUT2
3.3V
1.3A
VOUT4
2.5V
0.2A
RT/SYNC
680pF
15µH
2.2µF
22µF
fSW = 450kHz
0.22µF
0.22µF
15k
18.7k
VOUT1
1.8V
2.4A
100µF
18.7k 680pF
4.7µH
24.3k
1000pF 16.2k 11.5k
35.7k
10µH
22µF
VOUT2
Start-Up Waveforms—Coincident Tracking5V, 3.3V, 2.5V and 1.8V Step-Down Regulator
1V/DIV
VOUT1
VOUT2
VOUT3
VOUT4
1ms/DIV 3507 TA01b
L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered trademarks of
Linear Technology Corporation. All other trademarks are the property of their respective owners.
wwwwwwwwwwwwwwwwwwwwwwwwwwwww LT3507
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pin conFiGurationabsolute MaxiMuM ratinGs
VIN Pins ...................................................... 0.3V to 36V
BOOST Pins ..............................................................55V
BOOST Above SW .....................................................25V
PGOOD Pins .............................................................. 36V
BIAS Pin ....................................................................16V
TRK/SS, VC, FB, RT/SYNC Pins ...................................6V
RUN, OVLO, UVLO Pins ........................................... VIN1
DRIVE Pin ...................................................................5V
Operating Junction Temperature Range (Notes 2, 5)
LT3507E, LT3507I .............................. 40°C to 125°C
LT3507H ............................................ 40°C to 150°C
Storage Temperature Range .................. 65°C to 150°C
(Note 1)
13 14 15 16
TOP VIEW
39
UHF PACKAGE
38-LEAD (5mm × 7mm) PLASTIC QFN
17 18 19
38 37 36 35 34 33 32
24
25
26
27
28
29
30
31
8
7
6
5
4
3
2
1BOOST1
VIN1
VIN1
VINSW
OVLO
UVLO
VC1
TRK/SS1
FB1
PGOOD1
PGOOD2
PGOOD3
VIN2
VIN2
SW2
SW2
BOOST2
TRK/SS4
FB4
DRIVE
VC2
FB2
TRK/SS2
FB3
SW1
SW1
VIN3
VIN3
SW3
SW3
BOOST3
RT/SYNC
RUN1
RUN2
RUN3
BIAS
TRK/SS3
VC3
23
22
21
20
9
10
11
12
θJA = 34°C/W
EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB
PARAMETER CONDITIONS MIN TYP MAX UNITS
Minimum Operating Voltage Internal UVLO on VIN1 l3.8 4 V
Input Quiescent Current Not Switching, VBIAS = 3.3V 2 3.5 mA
Bias Quiescent Current Not Switching, VBIAS = 3.3V 5 7.5 mA
Shutdown Current VRUN1,2,3 = 0V 1 µA
Reference Voltage Line Regulation 5V < VIN1 < 36V 0.01 %/V
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN1, VIN2, VIN3 = 12V, VBOOST1, VBOOST2, VBOOST3 = 17V, unless
otherwise noted. (Note 2)
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT3507EUHF#PBF
LT3507IUHF#PBF
LT3507HUHF#PBF
LT3507EUHF#TRPBF
LT3507IUHF#TRPBF
LT3507HUHF#TRPBF
3507
3507
3507
38-Lead (5mm × 7mm) Plastic QFN
38-Lead (5mm × 7mm) Plastic QFN
38-Lead (5mm × 7mm) Plastic QFN
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
orDer inForMation
electrical characteristics
LT3507
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electrical characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN1, VIN2, VIN3 = 12V, VBOOST1, VBOOST2, VBOOST3 = 17V, unless
otherwise noted. (Note 2)
PARAMETER CONDITIONS MIN TYP MAX UNITS
VC Source Current VC = 0.6V 20 µA
VC Sink Current VC = 0.6V 30 µA
VC Clamp Voltage 1.7 V
Switching Frequency RT = 40.2k l0.9 1.1 MHz
Switching Phase SW1 to SW2,3, RT = 40.2k 180 Deg
Foldback Frequency VFB = 0V, RT = 40.2k 120 kHz
Frequency Shift Threshold on FB 0.4 V
RUN Threshold 1 1.5 V
PGOOD Output Voltage Low IPGOOD = 200µA 0.2 0.4 V
PGOOD Pin Leakage VPGOOD = 2V 10 400 nA
PGOOD Threshold Offset VFB Rising 58 80 105 mV
Feedback Pin Voltage l788 800 812 mV
Feedback Pin Bias Current l–50 –500 nA
Error Amplifier Transconductance 330 µS
Error Amplifier Voltage Gain 500 V/V
VC Switching Threshold 0.9 V
Switch Leakage Current 0.01 10 µA
Minimum Boost Voltage Above Switch (Note 4) 1.8 2.5 V
Converter 1
VC1 to Switch Current Gain 5 A/V
Switch 1 Current Limit (Note 3) Duty Cycle = 15% l3 4.3 6 A
Switch 1 VCESAT ISW1 = 2A 400 600 mV
BOOST1 Operating Current ISW1 = 2A 40 60 mA
Converter 2
VC2 to Switch Current Gain 3.6 A/V
Switch 2 Current Limit (Note 3) Duty Cycle = 15% l2 2.9 4 A
Switch 2 VCESAT ISW2 = 1.5A 350 500 mV
BOOST2 Operating Current ISW2 = 1.5A 40 60 mA
Converter 3
VC3 to Switch Current Gain 3.6 A/V
Switch 3 Current Limit (Note 3) Duty Cycle = 15% l2 2.9 4 A
Switch 3 VCESAT ISW3 = 1.5A 350 500 mV
BOOST3 Operating Current ISW3 = 1.5A 40 60 mA
LDO Regulator
Feedback Pin Voltage l788 800 812 mV
Feedback Pin Bias Current –150 –500 nA
Error Amplifier Voltage Gain 1100 V/V
Line Regulation VIN from 5V to 36V 0.05 %/V
LT3507
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electrical characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN1, VIN2, VIN3 = 12V, VBOOST1, VBOOST2, VBOOST3 = 17V, unless
otherwise noted (Note 2)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Load Regulation IDRIVE from 0.1mA to 10mA 0.005 %/mA
DRIVE Output Current Limit l10 15 22.5 mA
Dropout Voltage, VIN1 to DRIVE IDRIVE = 10mA, VIN1 = 5V 1.7 2.0 V
Dropout Voltage, BIAS to DRIVE IDRIVE = 10mA, VIN1 = 5V 0.5 0.8 V
Over/Undervoltage Lockout
Undervoltage Lockout Threshold 1.15 1.20 1.25 V
Overvoltage Lockout Threshold 1.15 1.20 1.25 V
Undervoltage Lockout Hysteresis Current V(UVLO) < 1.2V 7 10 13 µA
Overvoltage Lockout Hysteresis Current V(OVLO) > 1.2V –7 –10 –13 µA
Input Bias Current (OVLO and UVLO) V(OVLO) = 1.0V, V(UVLO) = 1.5V –100 –200 nA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3507E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT3507I is guaranteed to meet performance specifications from –40°C
to 125°C junction temperature. The LT3507H is guaranteed over the full
–40°C to 150°C operating junction temperature range. High junction
temperatures degrade operating lifetimes. Operating lifetime is derated at
junction temperatures greater than 125°C.
Note 3: Current limit is guaranteed by design and/or correlation to static
test. Slope compensation reduces current limit at higher duty cycles.
Note 4: This is the minimum voltage across the boost capacitor needed to
guarantee full saturation of the internal power switch.
Note 5: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions.
Junction temperature will exceed the maximum operating range when
overtemperature protection is active. Continuous operation above the
specified maximum operating junction temperature may impair device
reliability.
Note 6: Positive currents flow into pins, negative currents flow out of pins.
Minimum and maximum specifications refer to absolute values.
LT3507 L7HEWEAR 5
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typical perForMance characteristics
VFB vs Temperature Frequency vs RT
Frequency vs Temperature Frequency vs VFB (Foldback) ITRK/SS vs Temperature
Efficiency vs Load Current,
Channel 1, VOUT = 1.8V
Switch VCESAT vs Switch Current,
Channels 1, 2 and 3
BOOST Pin Current vs Switch
Current, Channels 1, 2 and 3
Efficiency vs Load Current,
Channels 2 and 3, VOUT = 3.3V
IOUT (A)
0
EFFICIENCY (%)
90
80
60
70
50
40 21
3507 G01
2.51.50.5
VIN = 6V
VIN = 12V
VIN = 36V
TA = 25°C
fSW = 450kHz
IOUT (A)
0
EFFICIENCY (%)
100
80
90
60
70
50
40 1.20.6
3507 G02
1.50.90.3
VIN = 6V
VIN = 12V
VIN = 36V
TA = 25°C
fSW = 450kHz
ISW (A)
0
V
SW
(V)
0.6
0.4
0.5
0.2
0.3
0.1
02.51
3507 G03
31.5 20.5
CHANNELS 2 & 3
CHANNEL 1
TA = 25°C
ISW (A)
0
IBOOST (mA)
100
80
70
60
50
40
90
20
30
10
02.51
3507 G04
31.5 20.5
CHANNELS 2 & 3
CHANNEL 1
TA = 25°C
TEMPERATURE (°C)
–50
VFB (mV)
805
803
802
801
800
799
804
797
798
796
795 130–10
3507 G05
15090705030 110–30
RT (kΩ)
FREQUENCY (MHz)
3507 G06
2.5
0.2510 100
TA = 25°C
TEMPERATURE (°C)
–50
FREQUENCY DEVIATION (%)
0.5
–0.5
–1.0
–1.5
0.0
–2.0 130–10
3507 G07
15090705030 110–30
VFB (V)
0
FRERQUENCY (kHz)
1200
800
600
400
200
1000
00.80.4
3507 G08
10.60.2
RT = 40.2k
TA = 25°C
TEMPERATURE (°C)
–50
ITRK/SS (µA)
1.30
1.26
1.24
1.22
1.28
1.20 130–10
3507 G09
15090705030 110–30
LT3507 6 L7ELUW
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typical perForMance characteristics
VIN1-VINSW Voltage Drop vs IVINSW
Current Limit vs Duty Cycle
Minimum On-Time vs ISW
RUN Threshold vs Temperature
Minimum Off-Time vs ISW
TEMPERATURE (°C)
–50
RUN THRESHOLD (V)
1.2
1.0
0.6
0.4
0.2
0.8
0.0 130–10
3507 G10
15090705030 110–30
IVINSW (mA)
0
VIN–VINSW (V)
0.40
0.20
0.30
0.35
0.25
0.15
0.05
0.10
0.00 0.80.4
3507 G11
1.00.60.2
TA = 25°C
DUTY CYCLE (%)
0
ILIM (A)
4.5
2.0
3.0
3.5
4.0
2.5
1.5
0.5
1.0
0.0 8040
3507 G12
1006020
CHANNEL 1
CHANNELS 2 & 3
TA = 25°C
ISW (A)
0
MINIMUM ON-TIME (ns)
250
150
200
50
100
0
3507 G13
321
150°C
25°C
–40°C
ISW (A)
0
MINIMUM OFF-TIME (ns)
200
150
50
100
02 2.51
3507 G14
31.50.5
150°C
25°C
–40°C
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pin Functions
BOOST1, BOOST2, BOOST3 (Pins 1, 27, 32): The BOOST
pins are used to provide drive voltages, higher than the
input voltage, to the internal bipolar NPN power switches.
These pins must be tied through a diode from VOUT, VIN
or another supply greater than 2.5V.
VIN1 (Pins 2, 3): The VIN1 pins supply power to the internal
switch of the 2.4A regulator and to the LT3507’s internal
reference and start-up circuitry. VIN1 must be above the
internal UVLO threshold of 3.8V (typical) for any of the
four channels to operate. These pins must be locally
bypassed (Note 6).
VINSW (Pin 4): The VINSW pin is a switched VIN1 for the
user programmable undervoltage and overvoltage detec-
tion. It is connected to VIN1 when any of the RUN pins
are pulled high, and high impedance when all RUN pins
are low or open.
OVLO (Pin 5): The LT3507 goes into overvoltage shutdown
when this pin goes above 1.2V. If unused, the OVLO pin
should be tied to GND.
UVLO (Pin 6): The LT3507 goes into undervoltage shut-
down when this pin drops below 1.2V. If unused, the UVLO
pin should be tied to VINSW.
VC1, VC2, VC3 (Pins 7, 23, 19): The VC pins are the outputs
of the internal error amps. The voltages on these pins
control the peak switch currents. These pins are normally
used to compensate the control loops. Each switching
regulator can be shut down by pulling its respective VC
pin to ground with an NMOS or NPN transistor.
TRK/SS1, TRK/SS2, TRK/SS3, TRK/SS4 (Pins 8, 21, 18,
26): The TRK/SS pins allow a regulator to track the output
of another regulator. When the TRK/SS pin is below 0.8V,
the FB pin regulates to the TRK/SS voltage. This pin can
also be used as a soft-start by connecting a capacitor from
TRK/SS to ground. The TRK/SS pins should be left open
if neither feature is used.
FB1, FB2, FB3 (Pins 9, 22, 20): The FB pins are the nega-
tive inputs of the error amplifiers. The LT3507 regulates
each feedback pin to the lesser of 0.8V or the TRK/SS
pin voltage. Connect the feedback resistor divider taps
to these pins. Note 6: VINX pins that are connected together may share a bypass capacitor.
PGOOD1, PGOOD2, PGOOD3 (Pins 10, 11, 12): The
PGOOD pins are the open-collector outputs of an internal
comparator. PGOOD remains low until the FB pin is within
10% of the final regulation voltage. As well as indicating
output regulation, the PGOOD pins can sequence the
switching regulators. These pins must be left unconnected
if unused. The PGOOD outputs are valid when VIN is greater
than 3.8V and any of the RUN pins are high. They are not
valid when all RUN pins are low.
RT/SYNC (Pin 13): The RT/SYNC pin requires a resistor
to ground or a clock signal to set the operating frequency
of the LT3507.
RUN1, RUN2, RUN3 (Pins 14, 15, 16): The RUN pins are
used to shut down the individual switching regulators.
When all three RUN pins are low, the LT3507 shuts down
and draws less than 1µA from VIN1.
BIAS (Pin 17): The BIAS pin supplies the current to the
LT3507’s internal regulator. This pin should be tied to the
lowest available voltage source above 3V (either VIN, VOUT
or any other available supply). The LDO pass transistor’s
base current is supplied from the BIAS pin if it is at least
0.8V above the LDO DRIVE output.
DRIVE (Pin 24): The DRIVE pin provides the base drive
for an external NPN transistor used for the LDO regulator.
FB4 (Pin 25): The FB4 pin is the negative input to the LDO
error amplifier. It is regulated to 0.8V through the LDO
feedback resistor divider.
VIN2 (Pins 30, 31)/VIN3 (Pins 35, 36 ): The VIN2 and VIN3
pins supply power to the internal switches of the 1.5A
converters. These pins must be locally bypassed (Note 6).
SW1 (Pins 37, 38)/SW2 (Pins 28, 29)/SW3 (Pins 33, 34):
The SW pins are the outputs of the internal power switches.
Connect these pins to the inductors and switching diodes.
Exposed Pad (Pin 39): Ground. The underside Exposed
Pad metal of the package provides both electrical contact
to ground and good thermal contact to the printed circuit
board. The Exposed Pad must be soldered to a grounded
pad on the circuit board for proper operation.
LT3507 L7LJCUEN2
LT3507
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block DiaGraM
Figure 1. LT3507 Block Diagram with Typical External Components
+
+
+
+
+
+
+
+
+
+
1.2V
OVLO
VINSW
UVLO
DRIVE
VIN4
VOUT4
0.8V
TRK/SS4
FB4
BOOST
SW
FB
TRK/SS
3507 F01
VIN
SHDN
VINX
CIN
C3
VOUTX
C1
D2
D1
0.8V
80mV
ONE OF THREE STEP-DOWN REGULATORS
ERROR
AMP
ILIMIT
CLAMP
1.25µA
L1
R1
R2
UNDERVOLTAGE
DETECTION
THERMAL
SHUTDOWN
CHANNEL
SHUTDOWN
0.9V C1
0.4V
VC
RC
CC
CF
PGOOD 1.7V
SLOPE
CLK
SQ
R
+
SLAVE
OSC
+
+
RUN1
BIAS
VIN1
RUN2
RUN3
RT/SYNC
GND
MASTER
OSC
INT REG
AND REF
CLK1
CLK2
CLK3
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operation
The LT3507 contains three independent, constant fre-
quency, current mode, switching regulators with internal
power switches plus a low dropout linear regulator. The
three regulators share common circuitry including input
source, voltage reference and oscillator, but are otherwise
independent. Operation can be best understood by refer-
ring to the Block Diagram (Figure 1).
If the RUN pins are tied to ground, the LT3507 is shut
down and draws <1µA from the input source tied to VIN1. If
any of the RUN pins are driven above 1V, the internal bias
circuits turn on, including the internal regulator, reference,
and master oscillator. Each switching regulator will only
begin to operate when its corresponding RUN pin reaches
>1.25V. The master oscillator generates three clock signals,
with the signal for Channel 1 out of phase by 180°.
The three switchers are current mode regulators. Instead
of directly modulating the duty cycle of the power switch,
the feedback loop controls the peak current in the switch
during each cycle. Compared to voltage mode control, cur-
rent mode control improves loop dynamics and provides
cycle-by-cycle current limit.
The Block Diagram shows only one of the three step-down
switching regulators. A pulse from the slave oscillator
sets the RS flip-flop and turns on the internal NPN bipo-
lar power switch. Current in the switch and the external
inductor begins to increase. When this current exceeds a
level determined by the voltage at VC, current comparator
C1 resets the flip-flop, turning off the switch. The current
in the inductor flows through the external Schottky diode
and begins to decrease. The cycle begins again at the next
pulse from the oscillator. In this way, the voltage on the VC
pin controls the current through the inductor to the output.
The internal error amplifier regulates the output voltage
by continually adjusting the VC pin voltage. The threshold
for switching on the VC pin is >0.9V and an active clamp
of 1.8V limits the output current.
Each switcher contains an extra, independent oscillator to
perform frequency foldback during overload conditions.
This slave oscillator is normally synchronized to the master
oscillator. A comparator senses when VFB is less than 50%
of its regulated value and switches the regulator from the
master oscillator to a slower slave oscillator. VFB is less than
50% of its regulated value during start-up, short-circuit
and overload conditions. Frequency foldback helps limit
switch current under these conditions.
The TRK/SS pins override the 0.8V reference for the FB
pins when the TRK/SS pins are below 0.8V. This allows
either coincident or ratiometric supply tracking on start-up
as well as a soft-start capability.
The switch drivers operate either from VIN or from the
BOOST pin. An external capacitor and diode are used to
generate a voltage at the BOOST pin that is higher than
the input supply. This allows the driver to saturate the
internal bipolar NPN power switch for efficient operation.
The BIAS pin allows the internal circuitry to draw its current
from a lower voltage supply than the input, also reducing
power dissipation and increasing efficiency. If the voltage
on the BIAS pin falls below 3V, then its quiescent current
will flow from VIN.
A power good comparator trips when the FB pin is at
90% of its regulated value. The PGOOD output is an
open-collector transistor that is off when the output is in
regulation, allowing an external resistor to pull the PGOOD
pin high. Power good is valid when the LT3507 is enabled
and VIN > 3.5V.
The LDO regulator uses an external NPN pass transistor to
form a linear regulator. The loop is internally compensated
to be stable with a load capacitance of 2.2µF or greater.
The LDO is disabled when all three of the RUN pins are low.
The overvoltage and undervoltage detection shuts down
the LT3507 if the OVLO pin>1.2V or the UVLO pin<1.2V.
Input overvoltage and undervoltage values are set by re-
sistor dividers to VINSW. Hysteresis is provided by 10µA
currents activated when either pin trips. The hysteresis
voltage at VIN is the top resistor times 10µA.
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applications inForMation
STEP-DOWN CONSIDERATIONS
FB Resistor Network
The output voltage is programmed with a resistor divider
(refer to the Block Diagram) between the output and the
FB pin. Choose the resistors according to:
R1=R2 VOUT
800mV 1
The parallel combination of R1 and R2 should be 10k or
less to avoid bias current errors.
Input Voltage Range
The minimum operating voltage is determined either by
the LT3507’s internal undervoltage lockout (4V) or by
its maximum duty cycle. The duty cycle is the fraction of
time that the internal switch is on and is determined by
the input and output voltages:
DC =
V
OUT +
V
F
V
IN
– V
SW
+V
F
where VF is the forward voltage drop of the catch diode
(~0.4V) and VSW is the voltage drop of the internal switch
(~0.3V at maximum load). This leads to a minimum input
voltage of:
VIN(MIN) =
V
OUT +
V
F
DCMAX
– VF+VSW
The duty cycle is the fraction of time that the internal switch
is on during a clock cycle. The maximum duty cycle is
generally given by DCMAX=1 tOFF(MIN) fSW. However,
unlike most fixed frequency regulators, the LT3507 will not
switch off at the end of each clock cycle if there is sufficient
voltage across the boost capacitor (C3 in Figure 1) to fully
saturate the output switch. Forced switch off for a minimum
time will only occur at the end of a clock cycle when the
boost capacitor needs to be recharged. This operation
has the same effect as lowering the clock frequency for a
fixed off time, resulting in a higher duty cycle and lower
minimum input voltage. The resultant duty cycle depends
on the charging times of the boost capacitor and can be
approximated by the following equation:
DCMAX =1
1+1
B
where B is the output current capacity divided by the typi-
cal boost current from the BOOST pin current vs switch
current in the Typical Performance Characteristics section.
The maximum operating voltage without pulse-skipping
is determined by the minimum duty cycle DCMIN:
VIN(PS) =
V
OUT +
V
F
DCMIN
– VF+VSW
with DCMIN = tON(MIN) fSW.
Thus both the maximum and minimum input voltages are
a function of the switching frequency and output voltages.
Therefore the maximum switching frequency must be set
to a value that accommodates all the input and output
voltage parameters and must meet both of the following
criteria for each channel:
fMAX1 =VOUT +VF
VIN(PS) – VSW +VF
1
tON(MIN)
fMAX2 =1VOUT +VF
VIN(MIN) – VSW +VF
1
tOFF(MIN)
The values of tON(MIN) and tOFF(MIN) are functions of ISW
and temperature (see chart in the Typical Performance
Characteristics section). Worst-case values for switch cur-
rents greater than 0.5A are tON(MIN)=130ns (for TJ>125°C
tON(MIN)=155ns) and tOFF(MIN)=170ns.
fMAX1 is the frequency at which the minimum duty cycle
is exceeded. The regulator will skip ON pulses in order to
reduce the overall duty cycle at frequencies above fMAX1.
It will continue to regulate but with increased inductor
current and greatly increased output ripple. The increased
peak inductor current in pulse-skipping will also stress
the switch transistor at high voltages and high switching
frequency. If the LT3507 is allowed to pulse-skip and
LT3507 Vom VF L'f AIL DCNHN Vom VF L7HEWEAR 1 1
LT3507
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the input voltage is greater than 20V, then the switching
frequency must be kept below 1.1MHz to prevent damage
to the LT3507.
fMAX2 is the frequency at which the maximum duty cycle
is exceeded. If there is sufficient charge on the BOOST
capacitor, the regulator will skip OFF periods to increase
the overall duty cycle at frequencies about fMAX2. It will
continue to regulate but with increased inductor current
and greatly increased output ripple.
Note that the restriction on the operating input voltage
refers to steady-state limits to keep the output in regula-
tion; the circuit will tolerate input voltage transients up to
the absolute maximum rating.
Switching Frequency
Once the upper and lower bounds for the switching
frequency are found from the duty cycle requirements,
the frequency may be set within those bounds. Lower
frequencies result in lower switching losses, but require
larger inductors and capacitors. The user must decide
the best trade-off.
The switching frequency is set by a resistor connected
from the RT/SYNC pin to ground, or by forcing a clock
signal into RT/SYNC. The LT3507 applies a voltage of
~1.25V across this resistor and uses the current to set
the oscillator speed. The switching frequency is given by
the following formula:
fSW =55
R
T
+12
where fSW is in MHz and RT is in kΩ.
The frequency sync signal will support VH logic levels from
1.8V to 5V CMOS or TTL. The duty cycle is not important,
but it needs a minimum on time of 100ns and a minimum
off time of 100ns. If the sync circuit is to be powered from
one of the LT3507 outputs there may be start-up problems
if the driving gate is high impedance without a supply or
pulls high or low at some intermediate supply voltage.
The circuit shown in Figure 2 prevents these problems by
isolating the clock sync circuit until the clock is operating.
The Schottky diode should be a low leakage type such as
the BAS70 from On Semi or CMOD6263 from Central Semi.
RT should be set to provide a frequency within ±25% of
the final sync frequency.
Inductor Selection and Maximum Output Current
The current in the inductor is a triangle wave with an
average value equal to the load current. The peak switch
current is equal to the output current plus half the peak-to-
peak inductor ripple current. The LT3507 limits its switch
current in order to protect itself and the system from
overload faults. Therefore, the maximum output current
that the LT3507 will deliver depends on the switch current
limit, the inductor value and the input and output voltages.
When the switch is off, the potential across the inductor
is the output voltage plus the catch diode drop. This gives
the peak-to-peak ripple current in the inductor:
ΔIL=1– DC
( )
V
OUT +
V
F
Lf
where f is the switching frequency of the LT3507 and L
is the value of the inductor. The peak inductor and switch
current is:
ISWPK =ILPK =IOUT +Δ
I
L
2
To maintain output regulation, this peak current must
be less than the LT3507’s switch current limit, ILIM. For
SW1, ILIM is at least 3A at low duty cycles and decreases
linearly to 2.4A at DC = 0.8. For SW2 and SW3, ILIM is at
least 2A for at low duty cycles and decreases linearly to
1.6A at DC=0.8.
The minimum inductance can now be calculated as:
LMIN =
1
DC
MIN
2f
V
OUT +
V
F
I
LIM
I
OUT
applications inForMation
Figure 2. Clock Powered from LT3507 Output
RT/SYNC VOUT1
3507 F02
LT3507
SW1
CLK
CLOCK
SYNC
VCC
RT
BAS70
1k 470pF
LT3507 fsw AIL AIL 31‘ 12
LT3507
12
3507fb
For more information www.linear.com/LT3507
applications inForMation
However, it’s generally better to use an inductor larger
than the minimum value. The minimum inductor has large
ripple currents which increase core losses and require
large output capacitors to keep output voltage ripple low.
Select an inductor greater than LMIN that keeps the ripple
current below 30% of ILIM.
The inductors RMS current rating must be greater than the
maximum load current and its saturation current should
be greater than ILPK. For highest efficiency, the series
resistance (DCR) should be less than 0.1Ω. Table 1 lists
several vendors and types that are suitable.
Table 1. Inductors
PART NUMBER
VALUE
(µH)
ISAT
(A)
DCR
(Ω)
HEIGHT
(mm)
Sumida
CDC5D23-2R2 2.2 2.16 0.030 2.5
CDRH5D28-2R6 2.6 2.60 0.013 3.0
CDRH6D26-5R6 5.6 2.00 0.027 2.8
CDH113-100 10 2.00 0.047 3.7
Coilcraft
DO1606T-152 1.5 2.10 0.060 2.0
LPS6225-222ML 2.2 4.00 0.045 2.4
DO1608C-332 3.3 2.00 0.080 2.9
MSS6132-472ML 4.7 2.60 0.056 3.2
DO1813P-682HC 6.8 2.20 0.080 5.0
Cooper
SD414-2R2 2.2 2.73 0.061 1.35
DRA73-6R8-R 6.8 2.96 0.041 3.55
UP1B-100 10 1.90 0.111 5.0
Toko
(D62F)847FY-2R4M 2.4 2.5 0.037 2.7
(D73LF)817FY-2R2M 2.2 2.7 0.03 3.0
This analysis is valid for continuous mode operation
(IOUT > ILIM/2). For details of maximum output current in
discontinuous mode operation, see Linear Technology’s
Application Note AN44. Finally, for duty cycles greater
than 50% (VOUT/VIN > 0.5), a minimum inductance is
required to avoid subharmonic oscillations. This minimum
inductance is:
SW1:LMIN =VOUT +VF
( )
0.45
fSW
SW2, SW3:LMIN =VOUT +VF
( )
0.9
f
SW
with LMIN in µH and fSW in MHz.
Output Capacitor Selection
The output capacitor filters the inductor current to generate
an output with low voltage ripple. It also stores energy in
order to satisfy transient loads and stabilize the LT3507’s
control loop. Because the LT3507 operates at a high
frequency, minimal output capacitance is necessary. In
addition, the control loop operates well with or without
the presence of output capacitor series resistance (ESR).
Ceramic capacitors, which achieve very low output ripple
and small circuit size, are therefore an option.
You can estimate output ripple with the following
equations:
VRIPPLE =Δ
I
L
8fCOUT
for ceramic capacitors
and
VRIPPLE = ΔILESR for electrolytic capacitors
(tantalum and aluminum)
where ΔIL is the peak-to-peak ripple current in the inductor.
The RMS content of this ripple is very low so the RMS
current rating of the output capacitor is usually not of
concern. It can be estimated with the formula:
IC(RMS) =Δ
I
L
12
LT3507 IOUT(VW VOUT) IUM 13
LT3507
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Another constraint on the output capacitor is that it must
have greater energy storage than the inductor; if the stored
energy in the inductor transfers to the output, the resulting
voltage step should be small compared to the regulation
voltage. For a 5% overshoot, this requirement indicates:
COUT >10 LILIM
VOUT
2
The low ESR and small size of ceramic capacitors make them
the preferred type for LT3507 applications. Not all ceramic
capacitors are the same, however. Many of the higher value
capacitors use poor dielectrics with high temperature and
voltage coefficients. In particular, Y5V and Z5U types lose
a large fraction of their capacitance with applied voltage
and at temperature extremes. Because loop stability and
transient response depend on the value of COUT, this loss
may be unacceptable. Use X7R and X5R types.
Electrolytic capacitors are also an option. The ESRs of
most aluminum electrolytic capacitors are too large to
deliver low output ripple. Tantalum, as well as newer,
lower-ESR organic electrolytic capacitors intended for
power supply use are suitable. Chose a capacitor with a
low enough ESR for the required output ripple. Because
the volume of the capacitor determines its ESR, both the
size and the value will be larger than a ceramic capacitor
that would give similar ripple performance. One benefit
is that the larger capacitance may give better transient
response for large changes in load current. Table 2 lists
several capacitor vendors.
Table 2. Low ESR Surface Mount Capacitors
VENDOR TYPE SERIES
Taiyo-Yuden Ceramic
AVX Ceramic
Tantalum TPS
Kemet Tantalum
Tantalum Organic
Aluminum Organic
T491,T494,T495
T520
A700
Sanyo Tantalum or
Aluminum Organic POSCAP
Panasonic Aluminum Organic SP CAP
TDK Ceramic
Diode Selection
The catch diode (D1 from Figure 2) conducts current only
during switch off time. Average forward current in normal
operation can be calculated from:
ID(AVG) =IOUT VIN VOUT
( )
V
IN
The only reason to consider a diode with a larger current
rating than necessary for nominal operation is for the
worst-case condition of shorted output. The diode current
will then increase to the typical peak switch current. Peak
reverse voltage is equal to the regulator input voltage. Use
a diode with a reverse voltage rating greater than the input
voltage, but not higher than 40V. Using higher breakdown
Schottky diodes may result in undesirable behavior. The
programmable OVLO can protect the diode from excessive
reverse voltage by shutting down the regulator if the input
voltage exceeds the maximum rating of the diode. Table
3 lists several Schottky diodes and their manufacturers.
Table 3. Schottky Diodes
PART NUMBER
VR
(V)
IAVE
(A)
VF AT 1A
(mV)
VF AT 2A
(mV)
On Semiconductor
MBRM120E 20 1 530 595
MBRM140 40 1 550
Diodes Inc
B120 20 1 500
B140 40 1 500
B220 20 2 500
B240 40 2 500
DFLS140L 40 1 550
DFLS240L 40 2 550
Boost Pin Considerations
The capacitor and diode tied to the BOOST pin generate a
voltage that is higher than the input voltage. In most cases,
a small ceramic capacitor and fast switching diode (such
as the CMDSH-3 or MMSD914LT1) will work well. The
capacitor value is a function of the switching frequency,
applications inForMation
LT3507 14 T J. Jf’it —>I—T—_L{W: 3% L7 LJU
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peak current, duty cycle and boost voltage; in general a
value of (0.1µF 1MHz/fSW) works well. Figure 3 shows
three ways to arrange the boost circuit. The BOOST pin
must be more than 2.5V above the SW pin for full ef-
ficiency. For outputs of 3.3V and higher, the standard
circuit (Figure 3a) is best. For outputs between 2.8V and
3.3V, use a small Schottky diode (such as the BAT54).
For lower output voltages, the boost diode can be tied
to the input (Figure 3b). The circuit in Figure 3a is more
efficient because the BOOST pin current comes from a
lower voltage source. Finally, as shown in Figure 3c, the
anode of the boost diode can be tied to another source
that is at least 3V. For example, if you are generating 3.3V
and 1.8V and the 3.3V is on whenever the 1.8V is on, the
1.8V boost diode can be connected to the 3.3V output. In
this case, the 3.3V output cannot be set to track the 1.8V
output (see Output Voltage Tracking).
In any case, be sure that the maximum voltage at the
BOOST pin is less than 55V and the voltage difference
between the BOOST and SW pins is less than 25V.
The minimum operating voltage of an LT3507 applica-
tion is limited by the internal undervoltage lockout (4V
for Channel 1, 3V for Channels 2 and 3) and by the
maximum duty cycle. The boost circuit also limits the
minimum input voltage for proper start-up. If the input
voltage ramps slowly, or the LT3507 turns on when the
output is already in regulation, the boost capacitor may
not be fully charged. Because the boost capacitor charges
with the energy stored in the inductor, the circuit will rely
on some minimum load current to get the boost circuit
running properly. This minimum load will depend on
input and output voltages, and on the arrangement of
the boost circuit. The minimum load current generally
goes to zero once the circuit has started. Figure 4 shows
a plot of minimum load to start and to run as a function
of input voltage. Even without an output load current, in
many cases the discharged output capacitor will present
a load to the switcher that will allow it to start.
The boost current is generally small but can become sig-
nificant at high duty cycles. The required boost current is:
IBOOST =VOUT
VIN
IOUT
40
applications inForMation
Figure 3. Generating the Boost Voltage
VIN
BOOST
GND
SW
VIN
LT3507
(3a)
D2
VOUT
C3
VBOOST – VSW VOUT
MAX VBOOST VIN + VOUT
VIN
BOOST
GND
SW
VIN
LT3507
(3b)
D2
VOUT
C3
VBOOST – VSW VIN
MAX VBOOST 2VIN
3507 F03
D2
VIN
BOOST
GND
SW
VIN
LT3507
(3c)
VOUT
VBOOST – VSW VINB
MAX VBOOST VINB + VIN
MINIMUM VALUE FOR VINB = 3V
VINB > 3V
C3
LT3507 Vom(Vw ’VUUT) IDA VIN L7HEWEAR 1 5
LT3507
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Converter with Backup Output Regulator
There is another situation to consider in systems where
the output will be held high when the input to the LT3507
is absent. If the VIN and one of the RUN pins are allowed
to float, then the LT3507’s internal circuitry will pull its
quiescent current through its SW pin. This is acceptable if
the system can tolerate a few mA of load in this state. With
all three RUN pins grounded, the LT3507 enters shutdown
mode and the SW pin current drops to <50µA. However, if
the VIN pin is grounded while the output is held high, then
parasitic diodes inside the LT3507 can pull large currents
from the output through the SW pin and the VIN pin. A
Schottky diode in series with the input to the LT3507, as
shown in Figure 5, will protect the LT3507 and the system
from a shorted or reversed input.
Input Capacitor Selection
Bypass the input of the LT3507 circuit with a 10µF or higher
ceramic capacitor of X7R or X5R type. A lower value or
a less expensive Y5V type will work if there is additional
bypassing provided by bulk electrolytic capacitors, or if the
input source impedance is low. The following paragraphs
describe the input capacitor considerations in more detail.
Step-down regulators draw current from the input sup-
ply in pulses with very fast rise and fall times. The input
capacitor is required to reduce the resulting voltage ripple
at the LT3507 input and to force this switching current
into a tight local loop, minimizing EMI. The input capaci-
tor must have low impedance at the switching frequency
to do this effectively and it must have an adequate ripple
current rating. With three switchers operating at the same
frequency but with different phases and duty cycles, cal-
culating the input capacitor RMS current is not simple;
however, a conservative value is the RMS input current
for the phase delivering the most power (VOUT IOUT):
IIN(RMS) =IOUT VOUT VIN VOUT
( )
V
IN
<IOUT
2
applications inForMation
Figure 4. The Minimum Input Voltage Depends on Output Voltage, Load Current and Boost Circuit
LOAD CURRENT (A)
0.001
INPUT VOLTAGE (V)
5.5
5.0
4.0
3.0
4.5
3.5
2.5
3507 F04b
1.0000.010 0.100
TA = 25°C
VOUT = 3.3V
TO START
TO RUN
LOAD CURRENT (A)
0.001
INPUT VOLTAGE (V)
8.0
7.5
6.5
5.5
4.5
7.0
6.0
5.0
4.0
3507 F04a
1.0000.010 0.100
TA = 25°C
VOUT = 5V
TO START
TO RUN
Figure 5. Diode D4 Prevents a Shorted Input from
Discharging a Backup Battery Tied to the Output
VIN
VIN VOUT
SW
LT3507
D4
PARASITIC DIODE
3507 F05
LT3507
LT3507
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and is largest when VIN=2VOUT (50% duty cycle). As
the second, lower power channel draws input current,
the input capacitor’s RMS current actually decreases as
the out-of-phase current cancels the current drawn by the
higher power channel. Considering that the maximum load
current from a single phase (if SW2 and SW3 are both at
maximum current) is ~3A, RMS ripple current will always
be less than 1.5A.
The high frequency of the LT3507 reduces the energy
storage requirements of the input capacitor, so that the
capacitance required is often less than 10µF. The combi-
nation of small size and low impedance (low equivalent
series resistance or ESR) of ceramic capacitors makes
them the preferred choice. The low ESR results in very
low voltage ripple. Ceramic capacitors can handle larger
magnitudes of ripple current than other capacitor types
of the same value. Use X5R and X7R types.
An alternative to a high value ceramic capacitor is a lower
value along with a larger electrolytic capacitor, for example
a 1µF ceramic capacitor in parallel with a low ESR tantalum
capacitor. For the electrolytic capacitor, a value larger than
10µF will be required to meet the ESR and ripple current
requirements. Because the input capacitor is likely to see
high surge currents when the input source is applied, tan-
talum capacitors should be surge rated. The manufacturer
may also recommend operation below the rated voltage
of the capacitor. Be sure to place the 1µF ceramic as close
as possible to the VIN and GND pins on the IC for optimal
noise immunity.
A final caution is in order regarding the use of ceramic
capacitors at the input. A ceramic input capacitor can
combine with stray inductance to form a resonant tank
circuit. If power is applied quickly (for example by plugging
the circuit into a live power source), this tank can ring,
doubling the input voltage and damaging the LT3507. The
solution is to either clamp the input voltage or dampen the
tank circuit by adding a lossy capacitor in parallel with the
ceramic capacitor. For details, see Application Note 88.
Frequency Compensation
The LT3507 uses current mode control to regulate the
output. This simplifies loop compensation. In particular, the
LT3507 does not depend on the ESR of the output capacitor
for stability so you are free to use ceramic capacitors to
achieve low output ripple and small circuit size.
The components tied to the VC pin provide frequency
compensation. Generally, a capacitor and a resistor in
series to ground determine loop gain. In addition, there
is a lower value capacitor in parallel. This capacitor filters
noise at the switching frequency and is not part of the
loop compensation.
Loop compensation determines the stability and transient
performance. Designing the compensation network is a bit
complicated and the best values depend on the application
and the type of output capacitor. A practical approach is to
start with one of the circuits in this data sheet that is similar
to your application and tune the compensation network
to optimize the performance. Check stability across all
operating conditions, including load current, input voltage
and temperature. The LT1375 data sheet contains a more
thorough discussion of loop compensation and describes
how to test the stability using a transient load. Application
Note 76 is an excellent source as well.
Figure 6 shows an equivalent circuit for the LT3507 control
loop. The error amp is a transconductance amplifier with
finite output impedance. The power section, consisting of
the modulator, power switch and inductor is modeled as a
transconductance amplifier generating an output current
proportional to the voltage at the VC pin. The gain of the
power stage (gmp) is 5S for Channel 1 and 3.6S for Chan-
nels 2 and 3. Note that the output capacitor integrates this
applications inForMation
LT3507 LTLJHSGB 1 7
LT3507
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current and that the capacitor on the VC pin (CC) integrates
the error amplifier output current, resulting in two poles
in the loop. In most cases, a zero is required and comes
either from the output capacitor ESR or from a resistor
in series with CC. This model works well as long as the
inductor current ripple is not too low (ΔIRIPPLE > 5% IOUT)
and the loop crossover frequency is less than fSW/5. A
phase lead capacitor (CPL) across the feedback divider
may improve the transient response.
SHUTDOWN
The RUN pins are used to place the individual switching
regulators and the internal bias circuits in shutdown mode.
When all three RUN pins are pulled low, the LT3507 is in
shutdown mode and draws less than 1µA from the input
supply. When any RUN pin is pulled high (>1.25V) the
internal reference, the LDO and selected channel are all
turned on.
The RUN pins draw a small amount of current to power
the reference. The current is less than 3µA at 1.8V, so the
RUN pin can be driven directly from 1.8V logic. The RUN
pins are rated up to 36V and can be connected directly to
the input voltage.
A RUN pin cannot be pulled up by logic powered by its
own output, i.e., RUN1 can’t be pulled up by logic powered
by OUT1.
POWER GOOD INDICATORS
The PGOOD pin is the open-collector output of an internal
comparator. PGOOD remains low until the FB pin is within
10% of the final regulation voltage. Tie the PGOOD to any
supply with a pull-up resistor that will supply less than
200µA. Note that this pin will be open when the LT3507
is in shutdown mode (all three RUN pins at ground) re-
gardless of the voltage at the FB pin. PGOOD is valid when
the LT3507 is enabled (any RUN pin is high) and VIN is
greater than ~3.5V.
OUTPUT SEQUENCING
The LT3507 outputs can be sequenced in several ways.
The circuits in Figure 7 show some examples of these. In
each case channel 1 starts first, followed by channel 2,
then channel 3. The sequence shown is not a requirement;
the LT3507 can sequence the channels in any order. Note
that these circuits sequence the outputs during start-up.
When shut down the three channels turn off simultaneously.
applications inForMation
Figure 6. Loop Response Model
+
VFB
800mV
VSW
VC
LT3507
GND
3507 F06
R1
OUTPUT
ESR
CF
CC
RC
500k
ERROR
AMPLIFIER
FB
R2
C1
C1
CURRENT MODE
POWER STAGE
gmp
330µS
+
POLYMER
OR
TANTALUM
CERAMIC
CPL
LT3507 | 1—H _I__L—|— TTT
LT3507
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The most obvious method is to bring the RUN pins up
individually in the sequence desired (Figure 7a). This is
the ideal solution if full independent control of all three
channels is needed. This is also a simple solution, but it
does require three logic inputs.
Another possibility is to use the soft-start feature to slow
the start-up of specific channels (Figure 7b). All three RUN
pins are tied together and the difference in soft-start ca-
pacitance will determine the start-up sequence. The larger
capacitor on channel 2 slows its start-up with respect to
channel 1, and channel 3 is even slower
. The capacitor on
the delayed channel should be at least twice the value of
the capacitor on the faster channel. A larger ratio may be
required, depending on the output capacitance and load on
each channel. Make sure to test the circuit in the system
before deciding on final values for these capacitors. Also
remember that the delayed channels will start rising right
away, just at a slower rate than the faster channels.
The PG pins can be also used to sequence the three out-
puts. In Figure 7c, the PG pins drive the RUN pins directly.
Channel 2 will be held off until channel 1 is in regulation
and channel 3 is held off until channel 2 is in regulation.
The resistors pull up to VINSW so that there is no current
draw in shutdown. They should be sized to provide at least
1µA into the RUN pin. The capacitors keep channels 2 and 3
off until the power good comparators are functioning (the
power good comparators are disabled in shutdown). The
FETs are necessary to insure the RUN2 and RUN3 pins
are held low during shutdown.
In Figure 7d, the PG pins pull down the TRK/SS pins of
the delayed channels. This is a simple solution requiring
no extra components. Channel 2 is held off by the PG1
output pulling TRK/SS2 down until channel 1 is at 90% of
its final value. PG1 then goes high impedance and allows
the channel 2 soft-start circuit to charge the soft-start
capacitor bringing channel 2 up. Similarly, channel 3 is
held off by PG2.
The circuits in Figure 7a and 7b leave the power good
indicators free. However, the circuits in Figures 7c and
7d have another advantage. As well as sequencing the
outputs at start-up, they also disable the slaved channels
if the master channel falls out of regulation (due to a short
circuit or a collapsing input voltage).
Finally, be aware that the circuit in Figure 7e does not
work, because the power good comparators are disabled
in shutdown.
applications inForMation
Figure 7. Output Sequencing
RUN1
RUN2
RUN3
TRK/SS1
TRK/SS2
TRK/SS3
LT3507 C
2C
4C
(7b)
RUN1
RUN2
RUN3
RUN1
RUN2
RUN3
LT3507
(7a)
RUN2
PG1
LT3507
VIN
(7e)
Doesn’t Work!
RUN1RUNRUN
VINSW
PG1
RUN2
RUN3
PG2
3507 F07
LT3507
(7c)
RUN1
RUN2
RUN3
TRK/SS1
PG1
TRK/SS2
PG2
TRK/SS3
LT3507
(7d)
RUN
LT3507 EE R5 , R3 m m Voun Vomz L7HEWEAR 1 9
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applications inForMation
Figure 8. Two Different Modes of Output Voltage Tracking
Figure 9. Setup for Coincident and Ratiometric Tracking
Figure 10. Equivalent Input Circuit of Error Amplifier
OUTPUT VOLTAGE TRACKING
The LT3507 allows the user to program how the output
ramps up by means of the TRK/SS pins. Through these
pins, any channel output can be set up to either coinci-
dently or ratiometrically track any other channel output.
This example will show the channel 2 output tracking the
channel 1 output, as shown in Figure 8. The TRK/SS2 pin
acts as a clamp on channel 2’s reference voltage. VOUT2
is referenced to the TRK/SS2 voltage when the TRK/SS2
< 0.8V and to the internal precision reference when TRK/
SS2 > 0.8V.
To implement the coincident tracking in Figure 8a, connect
an extra resistive divider to the output of channel 1 and
connect its midpoint to the TRK/SS2 pin (Figure 9). The
ratio of this divider should be selected the same as that
of channel 2’s feedback divider (R5=R3 and R6=R4). In
this tracking mode, VOUT1 must be set higher than VOUT2.
To implement the ratiometric tracking in Figure 8b, change
the extra divider ratio to R5=R1 and R6=R2 + ΔR. The
extra resistance on R6 should be set so that the TRK/SS2
voltage is ≥1V when VOUT1 is at its final value.
The need for this extra resistance is best understood with
the help of the equivalent input circuit shown in Figure 10.
At the input stage of the error amplifier, two common anode
diodes are used to clamp the equivalent reference volt-
age and an additional diode is used to match the shifted
common mode voltage. The top two current sources are
of the same amplitude. In the coincident mode, the TRK/
SS2 voltage is substantially higher than 0.8V at steady
state and effectively turns off D1. D2 and D3 will there-
fore conduct the same current and offer tight matching
between VFB2 and the internal precision 0.8V reference. In
the ratiometric mode with R6=R2, TRK/SS2 equals 0.8V
at steady state. D1 will divert part of the bias current and
make VFB2 slightly lower than 0.8V. Although this error
R1
R2 =VOUT1
0.8 1, R3
R4 =VOUT2
0.8 – 1
R5 R1
R6 R2
VOUT2
R4
R3
Tracking Setup
TO
VFB1
PIN
TO
TRK/SS2
PIN
TO
VFB2
PIN
VOUT1
COINCIDENT
R3
R4
R5 =
R6 =
RATIOMETRIC
R1
R1
VOUT1/1V – 1
SELECTING VALUES FOR R5 AND R6
TIME
(8a) Coincident Tracking
VOUT1
VOUT2
OUTPUT VOLTAGE
TIME 3507 F08
(8b) Ratiometric Tracking
VOUT1
VOUT2
OUTPUT VOLTAGE
1.25µA
+
I I
D1
TRK/SS
0.8V
FB
D2
D3
3507 F10
EA2
LT3507
LT3507
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3507fb
For more information www.linear.com/LT3507
is minimized by the exponential I-V characteristic of the
diodes, it does impose a finite amount of output voltage
deviation. Further, when channel 1’s output experiences
dynamic excursions (under load transient, for example),
channel 2 will be affected as well. Setting R6 to a value
that pushes the TRK/SS2 voltage to 1V at steady state will
eliminate these problems while providing near ratiometric
tracking.
The example shows channel 2 tracking channel 1, however
any channel may be set up to track any other channel.
If a capacitor is tied from the TRK/SS pin to ground, then
the internal pull-up current will generate a voltage ramp on
this pin. This results in a ramp at the output, limiting the
inductor current and therefore input current during start-up.
A good value for the soft-start capacitor is COUT/10,000,
where COUT is the value of the output capacitor.
MULTIPLE INPUT SUPPLIES
VIN1, VIN2 and VIN3 are independent and can be powered
with different voltages provided VIN1 is present when VIN2
or VIN3 is present. Each supply must be bypassed as close
to the VIN pins as possible.
For applications requiring large inductors due to high VIN
to VOUT ratios, a 2-stage step-down approach may reduce
inductor size by allowing an increase in frequency. A dual
step-down application steps down the input voltage (VIN1)
to the highest output voltage, then uses that voltage to
power the other outputs (VIN2 and VIN3). VOUT1 must be
able to provide enough current for its output plus the
input current at VIN2 and VIN3 when VOUT2 and VOUT3 are
at maximum load. The Typical Applications section shows
a 36V to 15V, 1.8V and 1.2V 2-stage converter using this
approach.
For applications with multiple voltages, the LT3507 can
accommodate input voltages as low as 3V on VIN2 and
VIN3. This can be useful in applications regulating outputs
from a PCI Express bus, where the 12V input is power
applications inForMation
limited and the 3.3V input has power available to drive
other outputs. In this case, tie the 12V input to VIN1 and
the 3.3V input to VIN2 and VIN3.
LOW DROPOUT REGULATOR
The low dropout regulator comprises an error amp, loop
compensation and a base drive amp. It uses the same 0.8V
reference as the switching regulators. It requires an external
NPN pass transistor and 2.2µF of output capacitance for
stability. The internal compensation is stable with loads
up to 300mA.
The dropout characteristics will be determined by the pass
transistor. The collector-emitter saturation characteristics
will limit the dropout voltage. Table 4 lists some suitable
NPN transistors with their saturation specifications.
The base drive voltage has a maximum voltage of 5V.
This will limit the maximum output of the regulator to
5V – VBESAT where VBESAT is the base-emitter saturation
voltage of the pass transistor.
Table 4. NPN Pass Transistors and Saturation Characteristics
PART NUMBER VCESAT VBESAT IC (mA) IB (mA)
On Semiconductor
NSS30071 0.25 0.85 500 5
NSS30101 0.2 0.85 1000 10
Fairchild
KSC3265 0.4 500 20
The LDO is always on when any of the switcher channels
is on. The LDO may be shut down if it is unused by pull-
ing the FB4 pin up with a 30µA current source. The FB4
pin will clamp at about 1.25V and the LDO will shut off
reducing power consumption. This pull-up can be sourced
from one of the LT3507 outputs provided that channel is
always on when the other channels are on.
The output stage of the LDO will drive the NPN base from
the BIAS voltage if it is at least 0.8V above the LDO DRIVE
voltage.
LT3507 Venn E] ifi. L7HEWEAR 21
LT3507
21
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For more information www.linear.com/LT3507
applications inForMation
FB Resistor Network
The output voltage of the LDO regulator is programmed
with a resistor divider (Refer to Block Diagram) between the
emitter of the external NPN pass resistor and the feedback
pin, FB4. Choose the resistors according to
R1=R2 VOUT4
800mV 1
The parallel combination of R1 and R2 should be 10k or
less to avoid bias current errors.
PROGRAMMABLE OVERVOLTAGE AND
UNDERVOLTAGE LOCKOUT
The LT3507 provides two input pins that allow user-
programmable overvoltage and undervoltage lockout. Both
the trip levels and hysteresis can be set by resistor values.
VINSW provides a switched VIN1 to minimize power con-
sumption in shutdown. VINSW is connected to VIN1 when
the LT3507 is operating, with a saturation voltage of about
0.3V. It is high impedance when the LT3507 is in shutdown
(all three RUN pins low).
The programmable lockout is a pair of comparators with
the trip level set at 1.2V. The OVLO comparator trips when
the OVLO pin exceeds 1.2V while the UVLO compara-
tor trips when the UVLO pin drops below 1.2V. These
comparators shut down all four regulators until the input
voltage recovers.
The comparators also activate current sources that gener-
ate hysteresis to eliminate chatter
. The UVLO comparator
activates a 10µA current sink on the UVLO pin. The OVLO
comparator activates a 10µA current source on the OVLO
pin. These currents generate hysteresis voltage through
the resistance of the divider string.
Figure 11. Undervoltage and Overvoltage Lockout Circuit
+
+
1.2V
UVLO
UVLO
V
INSW
R3
R4
R1
R2
OVLO
10µA
10µA
OVLO
3507 F11
Figure 11 shows a typical connection. The threshold
voltages are:
VOVTH =0.3V+1.2V 1+R3
R4
VUVTH =0.3V+1.2V 1+R1
R2
The hysteresis voltages are:
VOVHYST = 10µA R3
VUVHYST = 10µA R1
If the overvoltage lockout is not used, the OVLO pin must
be tied to ground. If the undervoltage lockout is not used,
the UVLO pin must be tied to VINSW.
LT3507 T—H—i - -l: + H— T |__ _E “F. .m 'H Ill L7LJCUEN2
LT3507
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Figure 12. Subtracting the Current When the Switch is ON (12a) From the Current When the Switch is OFF (12b) Reveals the Path of
the High Frequency Switching Current (12c) Keep this Loop Small. The Voltage on the SW and Boost Nodes Will Also be Switched;
Keep These Nodes as Small as Possible. Finally, Make Sure the Circuit is Shielded with a Local Ground Plane
applications inForMation
Figure 13. Power Path Components and Topside Layout
VIN SW
GND
(12a)
VIN
VSW
C1 D1 C2
3507 F12
L1
SW
GND
(12c)
VIN SW
GND
(12b)
IC1
PCB LAYOUT
For proper operation and minimum EMI, care must be
taken during printed circuit board (PCB) layout. Figure 12
shows the high current paths in the step-down regula-
tor circuit. Note that in the step-down regulators large,
switched currents flow in the power switch, the catch
diode and the input capacitor. The loop formed by these
components should be as small as possible. Place these
components, along with the inductor and output capacitor
,
on the same side of the circuit board and connect them
on that layer. Place a local, unbroken ground plane below
these components and tie this ground plane to system
ground at one location, ideally at the ground terminal of
the output capacitor C2. Additionally, keep the SW and
BOOST nodes as small as possible. Figure 13 shows an
example of proper PCB layout.
L7 LJUW LT3507 sw|('oum) Voum loun 23
LT3507
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THERMAL CONSIDERATIONS
The high output current capability of the LT3507 will require
careful attention to power dissipation of all the components
to insure a safe thermal design. The PCB must provide
heat sinking to keep the LT3507 cool. The Exposed Pad on
the bottom of the package must be soldered to a ground
plane. This ground should be tied to other copper layers
below with thermal vias; these layers will spread the heat
dissipated by the LT3507. Place additional vias near the
catch diodes. Adding more copper to the top and bottom
layers and tying this copper to the internal planes with vias
can reduce thermal resistance further. With these steps,
the thermal resistance from die (or junction) to ambient
can be reduced to θJA=34°C/W or less. With 100 LFPM
airflow, this resistance can fall by another 25%. Further
increases in airflow will lead to lower thermal resistance.
The maximum allowed power dissipation by the LT3507
can be determined by:
P
DISS(MAX) =TJ(MAX) – TA
θ
JA
where TJMAX is the maximum die temperature of 125°C
(150°C for H-grade).
However, take care in determining TA since the catch
diodes also dissipate power and must be located close
to the LT3507. Another potential heat source is the LDO
pass transistor. In a compact layout the pass transistor
will be located close to the LT3507. The inductors will
also dissipate some power due to their series resistance
and they must be close to the LT3507. All of these heat
sources will increase the effective ambient temperature
seen by the LT3507.
A thorough analysis of eight heat sources in a small PCB
area is beyond the scope of this data sheet, however a
number of thermal analysis programs are available to
calculate the temperature rise in each component (such
as PCAnalyze from K&K Associates or BETAsoft from
Mentor). The power dissipation of each component will be
needed to accurately calculate the thermal characteristics
of the system.
applications inForMation
The contributors to power dissipation inside the LT3507
are switch DC loss, switch AC loss, boost current, quies-
cent current and LDO drive current. The total dissipation
within the LT3507 can be expressed as:
P
DISS =PSWDCi +PSWACi +P
BSTi
( )
+PQ+P
LDO
i=1
3
The switch DC and AC losses in channel i are:
PSWDCi =RSWi IOUTi
( )
2VOUTi
VINi
PSWACi =17ns IOUTi
( )
VINi
( )
f
( )
where RSWi is the equivalent switch resistance (0.18Ω for
channel 1 and 0.22Ω for channels 2 and 3) and f is the
operating frequency.
The boost loss in channel i is:
P
BSTi =
VOUTi VBOOSTi
( )
I
OUTi
50 +0.02A
V
INi
The quiescent loss is:
PQ = VIN1(IQ(VIN1)) + VBIAS(IQ(BIAS))
If the BIAS pin does not have a voltage of at least 3V ap-
plied, then VIN1 must replace VBIAS in the equation. Also,
IQ(VIN1) can be reduced by 0.2mA (typ) if the LDO is shut
off (see the LDO section).
The LDO drive loss is:
P
LDO =(VBIAS VLDO(OUT) 0.7V) IOUT(LDO)
βPASS
,
if VBIAS VLDO(OUT) +1.5V
or
P
LDO =(VIN1 VLDO(OUT) 0.7V) IOUT(LDO)
βPASS
,
if VBIAS <VLDO(OUT) +1.5V
where βPASS is the current gain of the external pass
transistor.
LT3507 VF (Vw Vom VF)|0UT L7LJCUEN2
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Next, the power in the external components must be taken
into account. The diode power is given by:
P
DIODE =VFVIN VOUT VF
( )
IOUT
V
IN
where VF is the forward drop of the diode at IOUT.
The inductor power is:
PIND = (IOUT)2 ESRIND
where ESRIND is the inductor equivalent series resistance.
The LDO pass transistor power is:
PNPN = IOUTLDO(VC – VOUTLDO)
where VC is the collector voltage on the NPN pass tran-
sistor.
Example: An LT3507 design requirements are:
VIN = 8V, f=500kHz
V1 = 2.5V at I1 = 1.6A
V2 = 3.3V at I2 = 0.8A (used for boost, bias and V4)
V3 = 1.2V at I3 = 1A
V4 = 3V at I4 = 0.2A (from 3.3V output)
TA = 50°C, TJMAX = 125°C
θJA = 34°C/W
Schottky VF = 0.45V and Inductor ESR = 0.05Ω
P
DISS(MAX) =
125
°
C – 50
°
C
34°C/W =2.2W
PSWDC1 =0.18Ω1.6A
( )
22.5V
8V =0.14W
PSWAC1 =17ns 1.6A
( )
8V
( )
500k
( )
=0.11W
P
BST1 =
2.5V 3.3V
( )
1.6A
50 +0.02A
8V
=0.06W
applications inForMation
Similarly, PSWDC2=0.09W, PSWAC2=0.07W, PBST2=0.06W,
PSWDC3=0.03W, PSWAC3=0.07W and PBST2=0.03W.
Remember, the total current from channel 2 is I2 + I4 since
the LDO pass transistor draws from V2. Ignore bias and
boost currents.
PQ=8V 3.5mA
( )
+3.3V 7.5mA
( )
=0.05W
P
LDO =8V 0.2A
100
=0.02W
The total dissipation on the LT3507 is the sum of all these
and is equal to 0.73W. Note that this is less than half of
PDISS(MAX). Next, the power dissipation of the external
components are:
P
DIODE1 =0.45V 8V – 2.5V – 0.45
( )
1.6A
8V =0.46W
P
IND1 =1.6A
( )
20.05Ω = 0.13W
Similarly, PDIODE2=0.24W, PIND2=0.05W, PDIODE3=0.36W
and PIND3=0.05W. And finally:
PNPN=0.2A(3.3V – 3V)=0.06W
Thus the total power dissipated by the LT3507 and external
components is 2.08W. The thermal analysis will use these
power dissipations to calculate the internal component
temperatures. Make sure that none of the components
exceed their rated temperature limits.
RELATED LINEAR TECHNOLOGY PUBLICATIONS
Application Notes 19, 35, 44, 76 and 88 contain more
detailed descriptions and design information for buck
regulators and other switching regulators. The LT1375
data sheet has a more extensive discussion of output
ripple, loop compensation, and stability testing. Design
Note 318 shows how to generate a dual polarity output
supply using a buck regulator.
LT3507 _ :20; 453k J— T I | | 1E 49 Bk 4 32k '71,?% Li vi . ..J”:sé L7Hfl§0g 25
LT3507
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For more information www.linear.com/LT3507
typical applications
3.3V, 5V and 12V from a 24V Input with Ratiometric Tracking
VIN1
BOOST1 UVLO
OVLO
BOOST3
SW3
FB3
VC3
BIAS
DRIVE
FB4
PGOOD1
PGOOD2
PGOOD3
PGOOD1
PGOOD2
PGOOD3
SW1
FB1
VC1
TRK/SS1
TRK/SS2
TRK/SS3
BOOST2
0.1µF
10µF
50V
22µF D1
16.2k
1000pF
1.5nF
41.2k
L1 3.3µH
VOUT1
3.3V
2A
VIN
21V TO 27V
VOUT2
5V
1.2A
L2 6.8µH
L3 10µH
BAT54
VIN2 VIN3 VINSW
100k
49.9k
4.53k
OVLO = 29V
UVLO = 16V
100k
4.32k
VOUT1
13.3k
41.2k
BAT54
BAT54
18.2k
SW2
FB2
VC2
RT/SYNC TRK/SS4
GND
LT3507
RUN1
RUN2
RUN3
0.1µF
0.1µF
22µF
10µF
D2
D3
24.3k
26.7k
SHDN
470nF
470pF
61.9k
68.1kNC
VOUT1
D1: ON SEMI MBRS230LT3
D2, D3: ON SEMI MBRA130LT3
L1: COILCRAFT DO1813H-332ML
L1: COILCRAFT DO1813H-682ML
L1: COILCRAFT DO1813H-103ML
10.7k
3507 TA02
54.9k
fSW = 800kHz
11.8k
100k 100k
VOUT3
12V
1A
150k
VOUT1
LT3507 ‘BZK E T T I I M ”“1 —>J‘1—_L 1 £5“ 1: {$2 I % “A“ F 1 f —_t_—I<— -="">h.— T "m w
LT3507
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For more information www.linear.com/LT3507
typical applications
5V, 3.3V, 2.5V and 1.8V with Coincident Tracking
VIN1
BOOST1 UVLO
OVLO
BOOST2
SW2
FB2
VC2
BIAS
DRIVE
FB4
PGOOD1
PGOOD2
PGOOD3
PGOOD1
PGOOD2
PGOOD3
SW1
FB1
VC1
TRK/SS1
BOOST3
0.22µF
22µF
100µF D1
18.7k
680pF
18.7k
4.7µH
VOUT1
1.8V
2.4A
VIN
6V TO 36V
VOUT3
5V
1.5A
15µH
10µH
VIN2 VIN3 VINSW
49.9k 18.2k
100k
VOUT1
15k
SW3
FB3
VC3
RT/SYNC TRK/SS4
GND
LT3507
RUN1
RUN2
RUN3
0.22µF
0.22µF
22µF
22µF
D2
D3
24.3k
16.2k
SHDN
680pF
0.01µF
1000pF
53.6k
L1: WÜRTH WE-PD 744 778 9004
L2: WÜRTH WE-PD 744 778 9115
L3: WÜRTH WE-PD 744 778 910
D1, D2, D3: DIODES, INC. B240A
Q1: ON SEMICONDUCTOR NSS30101LT1G
11.5k
11.5k
24.3k
3507 TA03
105k
fSW = 450kHz
10.2k
2.2nF
2.2µF
100k 100k
VOUT2
3.3V
1.3A
VOUT4
2.5V
0.2A
35.7k
TRK/SS3
TRK/SS2 TRK/SS2
VOUT2
VOUT2
15k
18.7k
35.7k
11.5k
TRK/SS2
Q1
L7 LJUW LT3507 .H— 27
LT3507
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typical applications
15V, 1.8V and 1.2V 2-Stage Step Down
VIN1
BOOST1 UVLO
OVLO
PGOOD2
PGOOD3
BOOST 2
SW2
FB2
VC2
BOOST3
SW3
FB3
TRK/SS2
TRK/SS3
PGOOD1
SW1
FB1
VC1
TRK/SS1
BIAS
0.1µF
22µF
D1
68.1k
31.6k
220pF
0.01µF
187k
L1 10µH
VOUT1
15V
0.4A
VBST
3V
V
IN
21V TO 36V
L2 3.3µH
VIN2 VIN3 VINSW
49.9k 3.4k
UVLO = 19V
11.5k
10.5k
10µF
DRIVE
FB4
TRK/SS4
RT/SYNC VC3
GND
LT3507
RUN1
RUN2
RUN3
0.1µF
33µF
PGOOD
VBST
D2
13.3k
SHDN
1000pF
D1: DIODES, INC. B140A
D2, D3: DIODES, INC. B240A
L1: TDK LTF5022T-100M1R4
L2: TDK VLCF5020T-3R3N2R0-1
L3: TDK VLCF5020T-2R2N1R7
Q1: DIODES INC. BC817-16
18.2k
100k
3507 TA04
54.9k
fSW = 800kHz
VOUT2
1.8V
1.5A
22.6k
VOUT2
L3 2.2µH
0.1µF
47µF
VBST
D3
12.7k
1000pF
30.1k
270pF
2.2µF
Q1
VOUT3
1.2V
1.5A
15.0k
LT3507 UHUWUWHU]; T \fififlflflflfl‘flwfl; meflfllllL flflflflflflr\\ UUUUU J i 4_4,4 UUJUU \ A /flfl1flfl \\: \‘ Mflhmmflf: ‘ »« fit“ w 28 L7LJ11W
LT3507
28
3507fb
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Please refer to http://www.linear.com/product/LT3507#packaging for the most recent package drawings.
packaGe Description
5.00 ±0.10
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE
OUTLINE M0-220 VARIATION WHKD
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
PIN 1
TOP MARK
(SEE NOTE 6)
37
1
2
38
BOTTOM VIEW—EXPOSED PAD
5.50 REF 5.15 ±0.10
7.00 ±0.10
0.75 ±0.05
R = 0.125
TYP R = 0.10
TYP
0.25 ±0.05
(UH) QFN REF C 1107
0.50 BSC
0.200 REF
0.00 – 0.05
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
3.00 REF
3.15 ±0.10
0.40 ±0.10
0.70 ±0.05
0.50 BSC
5.5 REF
3.00 REF 3.15 ±0.05
4.10 ±0.05
5.50 ±0.05 5.15 ±0.05
6.10 ±0.05
7.50 ±0.05
0.25 ±0.05
PACKAGE
OUTLINE
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45° CHAMFER
UHF Package
38-Lead Plastic QFN (5mm × 7mm)
(Reference LTC DWG # 05-08-1701 Rev C)
LT3507 L7Hߤ0g 29
LT3507
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For more information www.linear.com/LT3507
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
revision history
REV DATE DESCRIPTION PAGE NUMBER
B 01/16 Added Clarifications to Conditions on Electrical Characteristics.
Added Note 6.
Clarified VIN1 Pin Function description.
Clarified PGOOD1, PGOOD2, PGOOD3 Pin Function description, 3.5V becomes 3.8V.
Clarified Operation VC pin >1V becomes VC pin >0.9V.
Clarified last paragraph in Operation description.
Clarified first paragraph of Input Voltage Range.
Added clarification in second paragraph of Diode Selection.
Replaced >1.5V with >1.25V in Shutdown description.
Clarified Figure 10.
Clarified Low Dropout Regulator first paragraph.
Clarified Typical Application Schematic.
Clarified Typical Application Schematic.
4
4
7
7
9
9
10
13
17
19
20
26
30
(Revision history begins at Rev B)
LT3507 hi _' up ”EL {I F 4:? % T w — _E 30 L7 LINE/“2
LT3507
30
3507fb
For more information www.linear.com/LT3507
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
LINEAR TECHNOLOGY CORPORATION 2008
LT 0116 REV B • PRINTED IN USA
(408) 432-1900 FAX: (408) 434-0507 www.linear.com/LT3507
typical applications
PART NUMBER DESCRIPTION COMMENTS
LT1939 25V, 2A, 2.5MHz High Efficiency DC/DC Converter and LDO Controller VIN(MIN) = 3.6V, VIN(MAX) = 25V, VOUT(MIN) = 0.8V,
IQ = 2.5mA, ISD < 10µA, 3 × 3 DFN-10 Package
LT1940 Dual 25V, 1.4A (IOUT), 1.1MHz, High Efficiency Step-Down DC/DC
Converter VIN(MIN) = 3.3V, VIN(MAX) = 25V, VOUT(MIN) = 1.20V,
IQ = 3.8mA, ISD < 30µA, TSSOP16E Package
LT3480 36V with Transient Protection to 60V, 2A (IOUT), 2.4MHz, High Efficiency
Step-Down DC/DC Converter with Burst Mode
®
Operation VIN(MIN) = 3.6V, VIN(MAX) = 38V, VOUT(MIN) = 0.78V,
IQ = 70µA, ISD < 1µA, 3 × 3 DFN-10, MSOP-10E Package
LT3481 34V with Transient Protection to 36V, 2A (IOUT), 2.8MHz, High Efficiency
Step-Down DC/DC Converter with Burst Mode Operation VIN(MIN) = 3.6V, VIN(MAX) = 34V, VOUT(MIN) = 1.26V,
IQ = 50µA, ISD < 1µA, 3 × 3 DFN-10, MSOP-10E Package
LT3493 36V, 1.4A (IOUT), 750kHz High Efficiency Step-Down DC/DC Converter VIN(MIN) = 3.6V, VIN(MAX) = 36V, VOUT(MIN) = 0.8V,
IQ = 1.9mA, ISD < 1µA, 2 × 3 DFN-6 Package
LT3500 36V, 40Vmax, 2A, 2.5MHz High Efficiency DC/DC Converter and LDO
Controller VIN(MIN) = 3.6V, VIN(MAX) = 36V, VOUT(MIN) = 0.8V,
IQ = 2.5mA, ISD < 10µA, 3 × 3 DFN-10 Package
LT3501/
LT3510 25V, Dual 3A/2A (IOUT), 1.5MHz High Efficiency Step-Down DC/DC
Converter VIN(MIN) = 3.3V, VIN(MAX) = 25V, VOUT(MIN) = 0.8V,
IQ = 3.7mA, ISD = 10µA, TSSOP-20E Package
LT3505 36V with Transient Protection to 40V, 1.4A (IOUT), 3MHz, High Efficiency
Step-Down DC/DC Converter VIN(MIN) = 3.6V, VIN(MAX) = 34V, VOUT(MIN) = 0.78V,
IQ = 2mA, ISD = 2µA, 3 × 3 DFN-8, MSOP-8E Package
LT3506/
LT3506A 25V, Dual 1.6A (IOUT), 575kHz/1.1MHz High Efficiency Step-Down DC/
DC Converter VIN(MIN) = 3.6V, VIN(MAX) = 25V, VOUT(MIN) = 0.8V,
IQ = 3.8mA, ISD = 30µA, TSSOP-16E, 5 × 4 DFN-16 Package
LT3508 36V with Transient Protection to 40V, Dual 1.4A (IOUT), 3MHz, High
Efficiency Step-Down DC/DC Converter VIN(MIN) = 3.7V, VIN(MAX) = 37V, VOUT(MIN) = 0.8V,
IQ = 4.6mA, ISD = 1µA, 4 × 4 QFN-24, TSSOP-16E Package
LT3684 34V with Transient Protection to 36V, 2A (IOUT), 2.8MHz, High Efficiency
Step-Down DC/DC Converter VIN(MIN) = 3.6V, VIN(MAX) = 34V, VOUT(MIN) = 1.26V,
IQ = 850µA, ISD < 1µA, 3 × 3 DFN-10, MSOP-10E Package
LT3685 36V with Transient Protection to 60V, 2A (IOUT), 2.4MHz, High Efficiency
Step-Down DC/DC Converter VIN(MIN) = 3.6V, VIN(MAX) = 38V, VOUT(MIN) = 0.78V,
IQ = 70µA, ISD < 1µA, 3 × 3 DFN-10, MSOP-10E Package
12V to 5V, 3.3V, 1.8V and 1.6V with 1.5mm Maximum Height
relateD parts
VIN1
BOOST1 UVLO
OVLO
BOOST3
SW3
FB3
VC3
TRK/SS3
BIAS
DRIVE
FB4
PGOOD1
PGOOD2
PGOOD3
PGOOD1
PGOOD2
PGOOD3
SW1
FB1
VC1
TRK/SS1
BOOST2
0.1µF
10µF
33µF D1
13.3k
1000pF
1.5nF
22.6k
L1 2µH
VOUT1
1.8V
2A
VIN
8V TO 16V
VOUT2
3.3V
1.5A
D1: DIODES, INC. DFLS220L
D2, D3: DIODES, INC. DFLS120L
L1: COOPER SD14-2R0-R
L2, L3: COOPER SD14-4R5-R
Q1: ON SEMI NSS30071MR6T1G
L2 4.5µH
L3 4.5µH
VIN2 VIN3 VINSW
49.9k
49.9k
4.02k OVLO = 17V
UVLO = 7V
100k
11.3k
VOUT1
VOUT2
18.2k
SW2
FB2
VC2
TRK/SS2
RT/SYNC TRK/SS4
GND
LT3507
RUN1
RUN2
RUN3
0.1µF
0.1µF
10µF D2
D3
7.32k
11.3k
SHDN
2000pF
1200pF
1.5nF
1.5nF
41.2k
11.8k
VOUT2
VOUT2
VOUT1
20.0k
20.0k
3507 TA03
31.6k
fSW = 1.25MHz
2.2nF
13.3k
100k 100k
VOUT3
5V
1.4A
VOUT4
1.6V
0.2A
2.2µF
10µF
61.9k
Q1

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