PM6675S Datasheet by STMicroelectronics

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February 2008 Rev 1 1/53
PM6675S
High efficiency step-down controller
with embedded 2 A LDO regulator
Features
Switching section
4.5 V to 28 V input voltage range
0.6 V, ±1 % voltage reference
Selectable 1.5 V fixed output voltage
Adjustable 0.6 V to 3.3 V output voltage
1.237 V ±1 % reference voltage available
Very fast load transient response using
constant on-time control loop
–No R
SENSE current sensing using low side
MOSFETs' RDS(ON)
Negative current limit
Latched OVP and UVP
Soft-start internally fixed at 3 ms
Selectable pulse skipping at light load
Selectable No-Audible (33 kHz) pulse skip
mode
Ceramic output capacitors supported
Output voltage ripple compensation
Output soft-end
LDO regulator section
Adjustable 0.6 V to 3.3 V output voltage
Selectable ±1 Apk or ±2 Apk current limit
Dedicated power-good signal
Ceramic output capacitors supported
Output soft-end
Applications
Notebook computers
Graphic cards
Embedded computers
Description
The PM6675S device consists of a single high
efficiency step-down controller and an
independent Low Drop-Out (LDO) linear
regulator.
The Constant On-Time (COT) architecture
assures fast transient response supporting both
electrolytic and ceramic output capacitors. An
embedded integrator control loop compensates
the DC voltage error due to the output ripple.
A selectable low-consumption mode allows the
highest efficiency over a wide range of load
conditions. The low-noise mode sets the minimum
switching frequency to 33 kHz for audio-sensitive
applications.
The LDO linear regulator can sink and source up
to 2 Apk. Two fixed current limits (±1 A-±2 A) can
be chosen.
An active soft-end is independently performed on
both the switching and the linear regulators
outputs when disabled.
VFQFPN-24 4x4
www.st.com
Table 1. Device summary
Order codes Package Packaging
PM6675S VFQFPN-24 4x4 (exposed pad) Tu b e
PM6675STR Tape and reel
Contents PM6675S
2/53
Contents
1 Typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1 Switching section - constant on-time PWM controller . . . . . . . . . . . . . . . 20
7.1.1 Constant-On-Time architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.1.2 Output ripple compensation and loop stability . . . . . . . . . . . . . . . . . . . . 23
7.1.3 Pulse-skip and no-audible pulse-skip modes . . . . . . . . . . . . . . . . . . . . . 27
7.1.4 Mode-of-operation selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.1.5 Current sensing and current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.1.6 POR, UVLO and Soft Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.1.7 Switching section power good signal . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.1.8 Switching section output discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.1.9 Gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.1.10 Reference voltage and bandgap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.1.11 Switching section OV and UV protections . . . . . . . . . . . . . . . . . . . . . . . 33
7.1.12 Device thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
PM6675S Contents
3/53
7.2 LDO linear regulator section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.2.1 LDO section current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.2.2 LDO section Soft-Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.2.3 LDO section power good signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.2.4 LDO section output discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8.1 External components selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8.1.1 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.1.2 Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.1.3 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.1.4 MOSFETs selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.1.5 Diode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.1.6 VOUT current limit setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.1.7 All ceramic capacitors application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
VLDOIN T stL3 E 2 § I mm mm VLDO 2 ma C on” L 4/53
Typical application circuit PM6675S
4/53
1 Typical application circuit
Figure 1. Application circuit
V
LDO
V
SMPS
+5V
R
LP
V
LDOIN
HGATE
PHASE
LGATE
CSNS
PGND
VSNS
VSEL
LIN
LPG
LOUT
LFB
LGND
LILIM
AVCC
VCC
VOSC
B
O
O
T
NOSKIP
SPG
LEN
SWEN
VREF
COMP
SGND
V
BATT
L
R
1
C
IN
C
INT
C
IN4
C
OUT
C
BYP
C
OUT2
C
IN2
C
IN3
1
2
24
4
23
10
9
16
19
17
20
21
312618822
5151413 711
R
2
C
BOOT
R
LIM
LDO PG
SMPS PG
PM6675
PM6675S
5/53
PM6675S Pin settings
5/53
2 Pin settings
2.1 Connections
Figure 2. Pin connection (through top view)
PM6675
1
6
712
13
18
19
24
VREF
VOSC
VSNS
VSEL
COMP
LILIM CSNS
PHASE
HGATE
BOOT
LIN
LOUT
SWEN
LEN
SPG
PGND
LGATE
VCC
LGND
LFB
LPG
NOSKIP
SGND
AVCC
PM6675S
Pin settings PM6675S
6/53
2.2 Pin description
Table 2. Pin functions
N° Pin Function
1LGND
LDO power ground. Connect to the negative terminal of VTT output
capacitor.
2LFB
LDO remote sensing. Connect as close as possible to the load via a low
noise PCB trace.
3NOSKIP
Pulse-Skip/No-Audible Pulse-Skip Modes selector.
See Section 7.1.4: Mode-of-operation selection on page 30
4LPG
LDO section power-good signal (open drain output). High when LDO output
voltage is within ±10 % of nominal value.
5SGND
Ground reference for analog circuitry, control logic and VTTREF buffer.
Connect together with the thermal pad and VTTGND to a low impedance
ground plane. See the Application Note for details.
6AVCC
+5 V supply for internal logic. Connect to +5 V rail through a simple RC
filtering network.
7VREF
High accuracy output voltage reference (1.237 V) for multilevel pins setting.
It can deliver up to 50 µA. Connect a 100 nF capacitor between VREF and
SGND in order to enhance noise rejection.
8VOSC
Frequency selection. Connect to the central tap of a resistor divider to set
the desired switching frequency. The pin cannot be left floating. See
Section 7: Device description on page 19 for details.
9 VSNS
Switching section output remote sensing and discharge path during output
soft-end. Connect as close as possible to the load via a low noise PCB
trace.
10 VSEL
Fixed output selector and feedback input for the switching controller.
If VSEL pin voltage is higher than 4 V, the fixed 1.5 V output is selected. If
VSEL pin voltage is lower than 4 V, it is used as negative input of the error
amplifier. See Section 7.1.4: Mode-of-operation selection on page 30 for
details.
11 COMP DC voltage error compensation input pin for the switching section. Refer to
Section 7.1.4: Mode-of-operation selection on page 30 for more details.
12 LILIM Current limit selector for the LDO. Connect to SGND for ±1 A current limit or
to +5 V for ±2 A current limit.
13 SWEN Switching controller enable. When tied to ground, the switching output is
turned off and a soft-end is performed.
14 LEN Linear regulator enable. When tied to ground, the LDO output is turned off
and a soft-end is performed.
15 SPG Switching section power good signal (open drain output). High when the
switching regulator output voltage is within ±10 % of nominal value.
16 PGND Power ground for the switching section.
17 LGATE Low-side gate driver output.
18 VCC +5 V low-side gate driver supply. Bypass with a 100 nF capacitor to PGND.
PM6675S Electrical data
7/53
3 Electrical data
3.1 Maximum rating
19 CSNS
Current sense input for the switching section. This pin must be connected
through a resistor to the drain of the synchronous rectifier (RDS(ON) sensing)
to set the current limit threshold.
20 PHASE Switch node connection and return path for the high side gate driver.
21 HGATE High-Side Gate Driver Output
22 BOOT Bootstrap capacitor connection. Input for the supply voltage of the high-side
gate driver.
23 LIN Linear Regulator Input. Bypass to LGND by a 10µF ceramic capacitor for
noise rejection enhancement.
24 LOUT LDO linear regulator output. Bypass with a 20µF (2 x 10 µF MLCC) filter
capacitor.
Table 2. Pin functions (continued)
N° Pin Function
Table 3. Absolute maximum ratings (1)
1. Free air operating conditions unless otherwise specified. Stresses beyond those listed under "absolute
maximum ratings" may cause permanent damage to the device. Exposure to absolute maximum rated
conditions for extended periods may affect device reliability.
Symbol Parameter Value Unit
VAVCC AVCC to SGND -0.3 to 6
V
VVCC VCC to SGND -0.3 to 6
PGND, LGND to SGND -0.3 to 0.3
HGATE and BOOT to PHASE -0.3 to 6
HGATE and BOOT to PGND -0.3 to 44
VPHASE PHASE to SGND -0.3 to 38
LGATE to PGND -0.3 to VCC +0.3
CSNS, SPG, LEN, SWEN, LILIM, COMP, VSEL,
VSNS, VOSC, VREF, NOSKIP to SGND -0.3 to VAVCC + 0.3
LPG,VREF, LOUT, LFB to SGND -0.3 to VAVCC + 0.3
LIN, LOUT, LPG, LIN to LGND -0.3 to VAVCC + 0.3
Maximum withstanding Voltage range test
condition: CDF-AEC-Q100-002- “Human Body
Model” acceptance criteria: “Normal
Performance”
± 1250 V
Electrical data PM6675S
8/53
3.2 Thermal data
3.3 Recommended operating conditions
Table 4. Thermal data
Symbol Parameter Value Unit
R
thJA
Thermal resistance junction to ambient 42 °C/W
T
STG
Storage temperature range - 50 to 150 °C
TAOperating ambient temperature range - 40 to 85 °C
T
J
Junction operating temperature range - 40 to 125 °C
Table 5. Recommended operating conditions
Symbol Parameter
Values
Unit
Min Typ Max
VIN Input voltage range 4.5 28
VVAVCC IC supply voltage 4.5 5.5
VVCC IC supply voltage 4.5 5.5
PM6675S Electrical characteristics
9/53
4 Electrical characteristics
Table 6. Electrical characteristics
TA = 0 °C to 85 °C, VCC = AVCC = +5 V, LIN = 1.5 V and LOUT = 0.6 V, if not otherwise
specified (1)
Symbol Parameter Test condition
Values
Unit
Min Typ Max
Supply section
IIN
Operating current
(Switching + LDO)
SWEN, LEN, VSEL and
NOSKIP connected to AVCC,
No load on LOUT output.
2
mA
ISW Operating current (Switching)
SWEN, VSEL and NOSKIP
connected to AVCC, LEN
connected to SGND.
1
ISHDN Shutdown operating current SWEN and LEN tied to SGND. 10 µA
UVLO
AVCC under voltage lockout
upper threshold 4.1 4.25 4.4
V
AVCC under voltage lockout
upper threshold 3.85 4.0 4.1
UVLO hysteresis 70 mV
ON-time (SMPS)
tON On-time duration
VSEL low,
NOSKIP low,
VVSNS = 2V
VOSC=300 mV 530 630 730
ns
VOSC=500 mV 320 380 440
OFF-time (SMPS)
tOFFMIN Minimum OFF-time 300 350 ns
Voltage reference
Voltage accuracy 4.5 V< VIN < 25 V 1.224 1.237 1.249 V
Load regulation -50 µA< IVREF < 50 µA -4 4
mV
Undervoltage Lockout Fault
Threshold 800
Electrical characteristics PM6675S
10/53
Symbol Parameter Test condition
Values
Unit
Min Typ Max
SMPS output
VOUT
SMPS fixed output voltage VSEL connected to AVCC,
NOSKIP tied to SGND, No Load
1.5 V
Feedback output voltage
accuracy -1.5 1.5 %
Current limit and zero crossing comparator
ICSNS CSNS input bias current 90 100 110 µA
Comparator offset -6 6
mV
Positive current limit threshold VPGND - VCSNS 100
Fixed negative current limit
threshold 110
VZC,OFFS
Zero crossing comparator
offset -11 -5 1
High and low side gate drivers
HGATE driver on-resistance HGATE high state (pull-up) 2.0 3
HGATE low state (pull-down) 1.8 2.7
LGATE driver on-resistance LGATE high state (pull-up) 1.4 2.1
LGATE low state (pull-down) 0.6 0.9
UVP/OVP protections and PGOOD signals
OVP Over voltage threshold 112 115 118
%
UVP Under voltage threshold 67 70 73
PGOOD
SMPS upper threshold 107 110 113
SMPS lower threshold 86 90 93
LDO upper threshold 107 110 113
LDO lower threshold 86 90 93
IPG,LEAK
SPG and LPG Leakage
Current SPG and LPG forced to 5.5 V 1 µA
VPG,LOW
SPG and LPG Low Level
Voltage ILPG,SINK = ISPG,SINK = 4 mA 150 250 mV
Soft-start section (SMPS)
Soft-start ramp time
(4 steps current limit) 234ms
Soft-start current limit step 25 µA
Table 6. Electrical characteristics (continued)
TA = 0 °C to 85 °C, VCC = AVCC = +5 V, LIN = 1.5 V and LOUT = 0.6 V, if not otherwise
specified (1)
PM6675S Electrical characteristics
11/53
Symbol Parameter Test condition
Values
Unit
Min Typ Max
Soft-end section
Switching section discharge
resistance 15 25 35
LDO section discharge
resistance 15 25 35
LDO section
VLREF LDO reference voltage 600
mV
LDO output accuracy respect
to VREF
-1 mA < ILDO < 1 mA -20 20
-1 A < ILDO < 1 A -25 25
ILDO,CL
LDO sink current limit VLFB > VLREF , LILIM = 5 V -3 -2.3 -2
A
VLFB > VLREF
, LILIM = 0 V -1.6 -1.3 -1
LDO source current limit
0.9 VLREF < VLFB < VLREF
,
LILIM = 5V 22.43
0.9 VLREF < VLFB < VLREF
,
LILIM = 0V 11.31.6
VLFB < 0.9 VLREF
, LILIM = 5 V 1 1.3 1.6
VLFB < 0.9 VLREF
, LILIM = 0 V 0.5 0.8 1.1
ILIN,BIAS
LDO input bias current, ON LEN connected to AVCC, no
load 110
µA
LDO input bias current, OFF LEN = 0 V, no load 1
ILFB,BIAS LFB input bias current LEN connected to AVCC
VLFB = 0.6 V -1 1
ILFB,LEAK LFB leakage current LEN = 0 V, VLFB = 0.6 V -1 1
Table 6. Electrical characteristics (continued)
TA = 0 °C to 85 °C, VCC = AVCC = +5 V, LIN = 1.5 V and LOUT = 0.6 V, if not otherwise
specified (1)
Electrical characteristics PM6675S
12/53
Symbol Parameter Test condition
Values
Unit
Min Typ Max
Power management section
VVTHVSEL VSEL pin thresholds
Fixed mode VAVCC
-0.7
V
Adjustable mode VAVCC
-1.3
VVTHNOSKIP NOSKIP pin thresholds
Forced-PWM mode VAVCC
-0.8
No-audible mode 1.0 VAVCC
-1.5
Pulse-skip mode 0.5
VVTHLEN,
VVTHSWEN
LEN, SWEN turn off level 0.4
LEN, SWEN turn on level 1.6
VVTHLILIM LILIM pin thresholds ±2 A LDO current limit VAVCC
-0.8
±1 A LDO current limit 0.5
IIN,LEAK Logic input leakage current LEN, SWEN and LILIM = 5 V 10
µAIIN3,LEAK
Multilevel input leakage
current VSEL and NOSKIP = 5 V 10
IOSC,LEAK VOSC pin leakage current VOSC = 1 V 1
Thermal shutdown
TSHDN Shutdown temperature (2) 150 °C
1. TA = TJ. All parameters at operating temperature extremes are guaranteed by design and statistical analysis
(not production tested)
2. Guaranteed by design. Not production tested.
Table 6. Electrical characteristics (continued)
TA = 0 °C to 85 °C, VCC = AVCC = +5 V, LIN = 1.5 V and LOUT = 0.6 V, if not otherwise
specified (1)
3.. $5.33
PM6675S Typical operating characteristics
13/53
5 Typical operating characteristics
Figure 3. VOUT efficiency vs load, 1.5 V,
SW frequency = 400 kHz
Figure 4. VOUT efficiency vs load, 1.25 V,
SW frequency = 400 kHz
Figure 5. VOUT load regulation, 1.5 V,
Vin = 12 V
Figure 6. VOUT load regulation, 1.25 V,
Vin = 12 V
Figure 7. VOUT load regulation, 2.5 V,
Vin = 12 V
Figure 8. LOUT load regulation, LOUT = 0.9 V,
LIN = 1.5 V
0
10
20
30
40
50
60
70
80
90
100
0.01 0.10 1.00 10.00
Output Current [A]
Efficiency [%]
SKIP @ 8V
SKIP @ 12V
SKIP @ 16V
No Aud. SKIP @ 8V
No Aud. SKIP @ 12V
No Aud. SKIP @ 16V
PWM @ 8V
PWM @ 12V
PWM @16V
0
10
20
30
40
50
60
70
80
90
100
0.01 0.10 1.00 10.00
Output Current [A]
Efficiency [%]
SKIP @ 8V
SKIP @ 12V
SKIP @ 16V
No Aud. SKIP @ 8V
No Aud. SKIP @ 12V
No Aud. SKIP @ 16V
PWM @ 8V
PWM @ 12V
PWM @ 16V
1.48
1.49
1.50
1.51
1.52
1.53
1.54
0.01 0.10 1.00 10.00
Output Current [A]
Output Voltage [V]
PWM
No Aud. SKIP
SKIP
1.240
1.245
1.250
1.255
1.260
1.265
1.270
1.275
1.280
0.01 0.10 1.00 10.00
Output Current [A]
Output Voltage [V]
PWM
No Aud. SKIP
SKIP
2.48
2.49
2.50
2.51
2.52
2.53
2.54
2.55
2.56
0.01 0.1 1 10
Output Current [A]
Output Voltage [V]
PWM
No Aud . SKIP
SKIP
0.87
0.88
0.89
0.90
0.91
0.92
0.93
0.94
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0
Output Current [A]
LOUT [V]
Typical operating characteristics PM6675S
14/53
Figure 9. VOUT line regulation, 1.5 V, 0 A Figure 10. VOUT line regulation, 1.25 V, 0 A
1.510
1.515
1.520
1.525
1.530
1.535
1.540
0 102030
Input Voltage [V]
Output Voltage [V]
SKIP @ 0A
No Aud. SKIP @ 0A
PWM @ 0 A
1.260
1.265
1.270
1.275
1.280
1.285
0 102030
Input Voltage [V]
Output Voltage [V]
SKIP @ 0A
No Aud. SKIP @ 0A
PWM @ 0 A
Figure 11. VOUT line regulation, 1.5 V Figure 12. VOUT line regulation, 1.25 V
1.5130
1.5135
1.5140
1.5145
1.5150
1.5155
1.5160
1.5165
1.5170
0 5 10 15 20 25 30
Input Voltage [V]
Output Voltage [V]
PWM @ 0A
PWM @ 7A
1.2625
1.2630
1.2635
1.2640
1.2645
1.2650
1.2655
1.2660
0 5 10 15 20 25 30
Input Voltage [V]
Output Voltage [V]
PWM @ 0 A
PWM @ 7 A
Figure 13. Switching frequency vs input
voltage, 1.5 V
Figure 14. Switching frequency vs input
voltage, 1.25 V
250
300
350
400
450
500
550
600
0 5 10 15 20 25 30
Input Voltage [V]
fsw [kHz]
PWM @ 0A
PWM @ 7A
200
250
300
350
400
450
500
550
600
0 5 10 15 20 25 30
Input Voltage [V]
fsw [kHz]
PWM @ 0 A
PWM @ 7 A
PM6675S Typical operating characteristics
15/53
Figure 15. Switching frequency vs load - 1.5 V Figure 16. PWM waveforms
0
100
200
300
400
500
600
0.01 0.1 1 10
Output Current [A]
fsw [kHz]
Pulse SKIP
No Aud. SKIP
PWM
Figure 17. No-audible pulse-skip waveforms Figure 18. Pulse-skip waveforms
Figure 19. Power-up sequence
VCC above UVLO
Figure 20. VOUT soft-start, 1.5 V, heavy load
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Typical operating characteristics PM6675S
16/53
Figure 21. Switching section output soft-end Figure 22. LDO section output soft-end
Figure 23. -1.8 A to 1.8 A LOUT
load transient, 0.9 V
Figure 24. -1 A to 1 A LOUT
load transient, 0.9 V
Figure 25. 0 A to 8 A VOUT
load transient, PWM
Figure 26. 8 A to 0 A VOUT
load transient, PWM
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PM6675S Typical operating characteristics
17/53
Figure 27. 0 A to 5 A VOUT load transient,
Pulse-Skip
Figure 28. 5 A to 0 A VOUT load transient,
Pulse-Skip
Figure 29. Over-voltage protection,
VOUT = 1.5 V
Figure 30. Under-voltage protection,
VOUT = 1.5 V
w . an ’77 5007 LFE 47 _ 7 4. >—( HGATE LIN 7°" PHASE mm vcc LOUT um 2;: "m“ LGATE l PGND luv Zevn Cmumg LGND um... csus me mum mar — coup LPG 4 (’4: swan Wm vr.m% 4: V- }' ' spa SGND Q7 uvP/ovP v. . mm Avcc 7 uvm swEN LDS Lns LEN 1 I I ' VSNS L'L'M — CDNTROLLDGIC sns NOSKIP —— J “" W LEM SWEN VSEL 18/53 ‘7
Block diagram PM6675S
18/53
6 Block diagram
Figure 31. Functional and block diagram
LOUT
LIN
LPG
VCC
AVCC
SGND
VSEL
LEN SWEN
CSNS
HGATE
LGATE
PHASE
BOOT
PGND
NOSKIP
VREF
VSNS
LFB
VOSC
COMP
CONTROL LOGIC
Zero Crossing
& Current
Limit
SPG
Vr -10
%
Vr +10
%
+
-
+
-
g
m
+
_Vr
+
_VREF
Level
shifter
1.236V
Bandgap
Vr = 0.6V
SDS
LDS
LEN
LEN
LILIM
UVLO
SWEN
SWEN
Vr
Ton
Toff
1-shot
1-shot
1-shot
fixadj
UVP/OVP
Thermal Shutdown
min
min
+
-
+
-
Vr +10
%
Vr -10
%
0.6V
+
_
Ton
Anti Cross
Conduction
LILIM
LGND
LDS
LDS
LOUT
LIN
LPG
VCC
AVCC
SGND
VSEL
LEN SWEN
CSNS
HGATE
LGATE
PHASE
BOOT
PGND
NOSKIP
VREF
VSNS
LFB
VOSC
COMP
CONTROL LOGIC
Zero Crossing
& Current
Limit
SPG
Vr -10
%
Vr +10
%
+
-
+
-
g
m
+
_Vr
+
_VREF
Level
shifter
1.236V
Bandgap
Vr = 0.6V
SDS
LDS
LEN
LEN
LILIM
UVLO
SWEN
SWEN
Vr
Ton
Toff
1-shot
1-shot
1-shot
fixadj
UVP/OVP
Thermal Shutdown
min
min
+
-
+
-
Vr +10
%
Vr -10
%
0.6V
+
_
Ton
Anti Cross
Conduction
LOUT
LIN
LPG
VCC
AVCC
SGND
VSEL
LEN SWEN
CSNS
HGATE
LGATE
PHASE
BOOT
PGND
NOSKIP
VREF
VSNS
LFB
VOSC
COMP
CONTROL LOGIC
Zero Crossing
& Current
Limit
SPG
Vr -10
%
Vr +10
%
+
-
+
-
g
m
+
_Vr
+
_VREF
Level
shifter
1.236V
Bandgap
Vr = 0.6V
SDS
LDS
LEN
LEN
LILIM
UVLO
SWEN
SWEN
Vr
Ton
Toff
1-shot
1-shot
1-shot
fixadj
UVP/OVP
Thermal Shutdown
min
min
+
-
+
-
Vr +10
%
Vr -10
%
0.6V
+
_
Ton
Anti Cross
Conduction
LILIM
LGND
LDS
LDS
Table 7. Legend
SWEN Switching controller enable
LEN LDO regulator enable
LDS LDO output discharge enable
SDS Switching output discharge enable
LILIM LDO regulator current limit
PM6675S Device description
19/53
7 Device description
The PM6675S combines a single high efficiency step-down controller and an independent
Low Drop-Out (LDO) linear regulator in the same package.
The switching controller section is a high-performance, pseudo-fixed frequency, Constant-
On-Time (COT) based regulator specifically designed for handling fast load transient over a
wide range of input voltages.
The switching section output can be easily set to a fixed 1.5 V voltage without additional
components or adjusted in the 0.6 V to 3.3 V range using an external resistor divider. The
Switching Mode Power Supply (SMPS) can handle different modes of operation in order to
minimize noise or power consumption, depending on the application needs. Selectable low-
consumption and low-noise modes allow the highest efficiency and a 33 kHz minimum
switching frequency respectively at light loads.
A lossless current sensing scheme, based on the Low-Side MOSFET turn-on resistance,
avoids the need for an external sensing resistor.
The input of the LDO can be either the switching section output or a lower voltage rail in
order to reduce the total power dissipation. Linear regulator stability is achieved by filtering
its output with a ceramic capacitor (20 µF or greater). The LDO linear regulator can sink and
source up to 2 Apk.
Two fixed current limit (±1 A-±2 A) can be chosen.
An active soft-end is independently performed on both the switching and the linear
regulators outputs when disabled.
Device description PM6675S
20/53
7.1 Switching section - constant on-time PWM controller
The PM6675S employes a pseudo-fixed frequency, Constant On-Time (COT) controller as
the core of the switching section. It is well known that the COT controller uses a relatively
simple algorithm and uses the ripple voltage derived across the output capacitor ESR to
trigger the On-Time one-shot generator. In this way, the output capacitor ESR acts as a
current sense resistor providing the appropriate ramp signal to the PWM comparator.
Nearly constant switching frequency is achieved by the system loop in steady-state
operating conditions by varying the On-Time duration, avoiding thus the need for a clock
generator. The On-Time one shot duration is directly proportional to the output voltage,
detected by theVSNS pin, and inversely proportional to the input voltage, detected by the
the VOSC pin, as follows:
Equation 1
where KOSC is a constant value (130 ns typ.) and τ is the internal propagation delay
(40ns typ.). The one-shot generator directly drives the high-side MOSFET at the beginning
of each switching cycle allowing the inductor current to increase; after the On-Time has
expired, an Off-Time phase, in which the low-side MOSFET is turned on, follows. The Off-
Time duration is solely determined by the output voltage: when lower than the set value (i.e.
the voltage at VSNS pin is lower than the internal reference VR = 0.6 V), the synchronous
rectifier is turned off and a new cycle begins (Figure 32).
Figure 32. Inductor current and output voltage in steady state conditions
τ+=
OSC
SNS
OSCON V
V
KT
Ton Toff
Inductor
current
t
Output
voltage
V
reg
PM6675S Device description
21/53
The duty-cycle of the buck converter is, in steady-state conditions, given by
Equation 2
The switching frequency is thus calculated as
Equation 3
where
Equation 4a
Equation 4b
Referring to the typical application schematic (figures on cover page and Figure 33), the
final expression is then:
Equation 5
Even if the switching frequency is theoretically independent from battery and output
voltages, parasitic parameters involved in the power path (like MOSFET on-resistance and
inductor DCR) introduce voltage drops responsible for a slight dependence on load current.
In addition, the internal delay is due to a small dependence on input voltage.
The PM6675S switching frequency can be set by an external divider connected to the
VOSC pin.
DVOUT
VIN
--------------=
OSCOUT
OSC
OSC
SNS
OSC
IN
OUT
ON
SW K
1
V
V
K
V
V
T
D
f
α
α
===
αOSC
VOSC
VIN
---------------=
αOUT
VSNS
VOUT
--------------=
OSC21
2
OSC
OSC
SW K
1
RR
R
K
f
+
=
α
=
7.1.1 22/53 mu m The voltage seen at this pin must be greater than 0.8 V and lower than 2 V in order to ensure the system linearity. Constant-On-Time architecture Figure 34 shows the simplified block diagram of the Constant»On-Time controller. The switching regulator of the PM667SS controls a one»shot generator that turns on the high-side MOSFET when the lolloWing conditions are simultaneously satisfied: the PWM comparator is high (i.e. output voltage is lower than Vr = 0.6 V), the synchronous rectifier current is below the current limit threshold and the minimum of‘Hime has expired. A minimum Off»Time contraint (300ns typ.) is introduced to assure the boot capacitor charge and allow inductor valley current sensing on low-side MOSFET. A minimum On»Time is also introduced to assure the start-up switching sequence. Once the On»Time has timed out, the high side switch is turned olf, while the synchronous rectifier is ignited according to the anti-cross conduction management circuitry. When the output voltage reaches the valley limit (determined by internal reference Vr = 0.6 V), the low»side MOSFET is turned ofl according to the anti-cross conduction logic once again, and a new cycle begins.
Device description PM6675S
22/53
Figure 33. Switching frequency selection and VOSC pin
The voltage seen at this pin must be greater than 0.8 V and lower than 2 V in order to
ensure the system linearity.
7.1.1 Constant-On-Time architecture
Figure 34 shows the simplified block diagram of the Constant-On-Time controller.
The switching regulator of the PM6675S controls a one-shot generator that turns on the
high-side MOSFET when the following conditions are simultaneously satisfied: the PWM
comparator is high (i.e. output voltage is lower than Vr = 0.6 V), the synchronous rectifier
current is below the current limit threshold and the minimum off-time has expired.
A minimum Off-Time contraint (300ns typ.) is introduced to assure the boot capacitor charge
and allow inductor valley current sensing on low-side MOSFET. A minimum On-Time is also
introduced to assure the start-up switching sequence.
Once the On-Time has timed out, the high side switch is turned off, while the synchronous
rectifier is ignited according to the anti-cross conduction management circuitry.
When the output voltage reaches the valley limit (determined by internal reference
Vr = 0.6 V), the low-side MOSFET is turned off according to the anti-cross conduction logic
once again, and a new cycle begins.
PM6675
VOSC
R1
R2
VIN
PM6675
VOSC
R1
R2
VIN
PM6675S
CSNS 4 HGATE F +— PHASE 4 S Q _ COMP ' Anllcmu. pm. Comm...” _ n 6 2225712” VCC ' l— VSEL Hum.“ 1°" — 2.5V VSNS LGATE ._ s O M: is“ E R PGND 2:23: R 6 -| — 4 1mm... Complain! T Puls: - SKIP ‘ SGND VREF 7.1.2 Output ripple compensation and loop stability The loop is closed conneciing ihe center tap of ihe output divider (lnfernally, when the fixed ouipui voltage lS chosen, or exiernally, using the VSEL pin in ihe adjusiable output voltage mode). The feedback node is the negaiive inpui ol the error comparaior, while the positive inpui is internally connected to ihe reference voltage (Vr = 0.6 V). When ihe feedback vollage becomes lower ihan the reference voltage, ihe PWM comparator goes lo high and seis the conirol logic, iurning on ihe highrslde MOSFET Alier ihe Oanlme (calculated as previously described), ihe syslem releases ihe highrside MOSFET and turns on ihe synchronous rectifier. The voltage drop along ground and supply PCB paths, used lo connect ihe outpui capacitor lo ihe load, is a source of DC error. Furthermore the syslem regulaies the ouipui vollage valley, not the average, as shown in Figure 37. Thus, the voltage ripple on the outpui capaciior is an additional source ol DC error. To compensaie lhls error, a network lS lniroduced in the conirol loop, by conneciing ihe outpui voltage ihrough a capaciior (CINT) as shown in Figure 35.
PM6675S Device description
23/53
7.1.2 Output ripple compensation and loop stability
The loop is closed connecting the center tap of the output divider (internally, when the fixed
output voltage is chosen, or externally, using the VSEL pin in the adjustable output voltage
mode). The feedback node is the negative input of the error comparator, while the positive
input is internally connected to the reference voltage (Vr = 0.6 V). When the feedback
voltage becomes lower than the reference voltage, the PWM comparator goes to high and
sets the control logic, turning on the high-side MOSFET. After the On-Time (calculated as
previously described), the system releases the high-side MOSFET and turns on the
synchronous rectifier.
The voltage drop along ground and supply PCB paths, used to connect the output capacitor
to the load, is a source of DC error. Furthermore the system regulates the output voltage
valley, not the average, as shown in Figure 37. Thus, the voltage ripple on the output
capacitor is an additional source of DC error. To compensate this error, an integrative
network is introduced in the control loop, by connecting the output voltage to the COMP pin
through a capacitor (CINT) as shown in Figure 35.
Figure 34. Switching section simplified block diagram
+
-
HS
HS
driver
driver
Level
Level
shifter
shifter
LS
LS
driver
driver
Q
Q
R
S
Ton
Ton-
-min
min
Anti cross-
conduction
circuitry
Toff
Toff-
-min
min
Q
R
S
+
-
PWM Comparator
PWM Comparator
Positive Current Limit comparator
Positive Current Limit comparator
0.6V
0.6V
Q
Q
R
S
+
_
Min
Min fsw
fsw
counter
counter
Zero
Zero-
-crossing
crossing
Comparator
Comparator
bandgap
bandgap
1.236V
1.236V
PHASE
PHASE
PGND
PGND
LGATE
LGATE
BOOT
BOOT
CSNS
CSNS
+
-
COMP
COMP
gm
gm
Integrator
Integrator
VSNS
VSNS
VBG
VBG
VBG
VBG
PULSE
PULSE -
-SKIP
SKIP
VSEL
VSEL
VSEL<4V
1-Shot generator
Ton
Ton
VSNS
VSNS
VOSC
VOSC
0.6V
0.6V
100uA
100uA
500mV
2.5V
2.5V
+
-
-
-
+
+
HGATE
HGATE
VREF
VREF
SGND
SGND
VOSC
VOSC
VOSC
VOSC
VCC
VCC
+
-
HS
HS
driver
driver
Level
Level
shifter
shifter
LS
LS
driver
driver
Q
Q
R
S
Ton
Ton-
-min
min
Anti cross-
conduction
circuitry
Toff
Toff-
-min
min
Q
R
S
+
-
PWM Comparator
PWM Comparator
Positive Current Limit comparator
Positive Current Limit comparator
0.6V
0.6V
Q
Q
R
S
+
_
Min
Min fsw
fsw
counter
counter
Zero
Zero-
-crossing
crossing
Comparator
Comparator
bandgap
bandgap
1.236V
1.236V
PHASE
PHASE
PGND
PGND
LGATE
LGATE
BOOT
BOOT
CSNS
CSNS
+
-
COMP
COMP
gm
gm
Integrator
Integrator
VSNS
VSNS
VBG
VBG
VBG
VBG
PULSE
PULSE -
-SKIP
SKIP
VSEL
VSEL
VSEL<4V
1-Shot generator
Ton
Ton
VSNS
VSNS
VOSC
VOSC
0.6V
0.6V
100uA
100uA
500mV
2.5V
2.5V
+
-
-
-
+
+
HGATE
HGATE
VREF
VREF
SGND
SGND
VOSC
VOSC
VOSC
VOSC
VCC
VCC
24/53 ESR COUT I _ _____ The additional capacitor is used to reduce the voltage on the COMP pin when higherthan 300 mVpp and is unnecessary for most of applications. The trans conductance amplifier (gm) generates a current, proportional to the DC error, used to charge the Gim- capacitor. The voltage across the CWT capacitor feeds the negative input of the PWM comparator, forcing the loop to compensate the total static error. An internal voltage clamp forces the COMP pin voltage range to :150 mV respect to VRE; This is useful to avoid or smooth output voltage overshoot during a load transient. When the Pulse»Skip Mode is entered, the clamping range is automatically reduced to 60 mV in order to enhance the recovering capability. If the ripple amplitude is larger than 150 mV, an additional capacitor CFILT can be connected between the COMP pin and ground to reduce ripple amplitude, otherWise the integrator will operate out of its linearity range. This capacitor is unnecessary for most of applications and can be omitted. The design of the external feedback network depends on the output voltage ripple. If the ripple is higher than approximately 20 mV, the correct CINT capacitor is usually enough to keep the loop stable. The stability of the system depends firstly on the output capacitor zero frequency. The following condition must be satisfied: Equation 6 where k is a fixed design parameter (k > 3). It determinates the m capacitor value:
Device description PM6675S
24/53
Figure 35. Circuitry for output ripple compensation
The additional capacitor is used to reduce the voltage on the COMP pin when higher than
300 mVpp and is unnecessary for most of applications. The trans conductance amplifier
(gm) generates a current, proportional to the DC error, used to charge the CINT capacitor.
The voltage across the CINT capacitor feeds the negative input of the PWM comparator,
forcing the loop to compensate the total static error. An internal voltage clamp forces the
COMP pin voltage range to ±150 mV respect to VREF
. This is useful to avoid or smooth
output voltage overshoot during a load transient. When the Pulse-Skip Mode is entered, the
clamping range is automatically reduced to 60 mV in order to enhance the recovering
capability. If the ripple amplitude is larger than 150 mV, an additional capacitor CFILT can be
connected between the COMP pin and ground to reduce ripple amplitude, otherwise the
integrator will operate out of its linearity range. This capacitor is unnecessary for most of
applications and can be omitted.
The design of the external feedback network depends on the output voltage ripple. If the
ripple is higher than approximately 20 mV, the correct CINT capacitor is usually enough to
keep the loop stable. The stability of the system depends firstly on the output capacitor zero
frequency.
The following condition must be satisfied:
Equation 6
where k is a fixed design parameter (k > 3). It determinates the minimum integrator
capacitor value:
+
-
V
V
REF
REF
COMP
COMP
g
g
m
m
VSNS
VSNS
R
R
Fb1
Fb1
R
R
Fb2
Fb2
Vr
Vr
+
PWM
PWM
Comparator
Comparator
C
C
INT
INT
R
R
INT
INT
C
C
FILT
FILT
t
Vr
C
C
OUT
OUT
COMP PIN
VOLTAGE
OUTPUT
VOLTAGE
I=g
m
(V
1
-Vr)
V
V
1
1
t
V
V
V
V
C
C
INT
INT
ESR
ESR
ESRC2
k
fkf
out
ZoutSW π
=>
PM6675S Device description
25/53
Equation 7
where gm = 50 µs is the integrator trans conductance.
If the ripple on the COMP pin is greater than 150 mV, the auxiliary capacitor CFILT can be
added. If q is the desired attenuation factor of the output ripple, CFILT is given by:
Equation 8
In order to reduce the noise on the COMP pin, it is possible to add a resistor RINT that,
together with CINT and CFILT
, becomes a low pass filter. The cutoff frequency fCUT must be
much greater (10 or more times) than the switching frequency:
Equation 9
If the ripple is very small (lower than approximately 20mV), a different compensation
network, called "Virtual-ESR" Network, is needed. This additional circuit generates a
triangular ripple that is added to the output voltage ripple at the input of the integrator. The
complete control scheme is shown in Figure 36.
Vout
Vr
f
k
f
2
g
C
Zout
SW
m
INT
π
>
q
)q1(C
CINT
FILT
=
FILTINT
FILTINT
CUT
INT
CC
CC
f2
1
R
+
π
=
on the COMP pin is the sum of the output voltage ripple a by the VirtualrESR Network. In fact the VirtualrESR Netw quivaient series resistor RVESR. derof‘f is to design the network in orderto achieve an RVE 10 is the inductor current ripple and VRIPPLE is1he total rippie n approximateiy 20 mV. usedrloop gain depends on CWT. 11
Device description PM6675S
26/53
Figure 36. "Virtual-ESR" network
The ripple on the COMP pin is the sum of the output voltage ripple and the triangular ripple
generated by the Virtual-ESR Network. In fact the Virtual-ESR Network behaves like a
another equivalent series resistor RVESR.
A good trade-off is to design the network in order to achieve an RVESR given by:
Equation 10
where IL is the inductor current ripple and VRIPPLE is the total ripple at the T node, chosen
greater than approximately 20 mV.
The new closed-loop gain depends on CINT
. In order to ensure stability it must be verified
that:
Equation 11
where:
Equation 12
and:
COMP
COMP
VSNS
VSNS
C
C
INT
INT
R
R
INT
INT
C
C
FILT
FILT
t
V
REF
C
C
OUT
OUT
COMP PIN
VOLTAGE
OUTPUT
VOLTAGE
C
C
R
R
R
R
1
1
t
t
T
T NODE
VOLTAGE
V
V
2
ESR
ESR
V
1
+
-
V
V
REF
REF
-
g
g
m
m
R
R
Fb1
Fb1
R
R
Fb2
Fb2
Vr
Vr
+
PWM
PWM
Comparator
Comparator
I=g
m
(V
1
-Vr)
V
V
1
1
ESR
I
V
R
L
RIPPLE
VESR
=
Vout
Vr
f2
g
C
Z
m
INT
π
>
TOTout
ZRC2
1
fπ
=
PM6675S Device description
27/53
Equation 13
Moreover, the CINT capacitor must meet the following condition:
Equation 14
where RTOT is the sum of the ESR of the output capacitor and the equivalent ESR given by
the Virtual-ESR Network (RVESR). The k parameter must be greater than unity (k > 3) and
determines the minimum integrator capacitor value CINT:
Equation 15
The capacitor of the Virtual-ESR Network, C, is chosen as follow
Equation 16
and R is calculated to provide the desired triangular ripple voltage:
Equation 17
Finally the R1 resistor is calculated according to Equation 18:
Equation 18
RTOT = ESR + RVESR
TOTout
ZSW RC2
k
fkf π
=>
Vout
Vr
f
k
f
2
g
C
Z
SW
m
INT
π
>
INT
C5C
>
CR
L
R
VESR
=
Cf
1
R
Cf
1
R
1R
Z
Z
π
π
=
Device description PM6675S
28/53
7.1.3 Pulse-skip and no-audible pulse-skip modes
High efficiency at light load conditions is achieved by PM6675S by entering the Pulse-Skip
Mode (if enabled). At light load conditions the zero-crossing comparator truncates the low-
side switch On-Time as soon as the inductor current becomes negative; in this way the
comparator determines the On-Time duration instead of the output ripple.
(see Figure 37).
Figure 37. Inductor current and output voltage at light load with Pulse-Skip
As a consequence, the output capacitor is left floating and its discharge depends solely on
the current drained from the load. When the output ripple on the pin COMP falls under the
reference, a new shot is triggered and the next cycle begins. The Pulse-Skip mode is
naturally obtained enabling the zero-crossing comparator and automatically takes part in the
COT algorithm when the inductor current is about half the ripple current amount, i.e.
migrating from continuous conduction mode (C.C.M.) to discontinuous conduction mode
(D.C.M.).
The output current threshold related to the transition between PWM Mode and Pulse-Skip
Mode can be approximately calculated as:
Equation 19
At higher loads, the inductor current never crosses the zero and the device works in pure
PWM mode with a switching frequency around the nominal value.
A physiological consequence of Pulse-Skip Mode is a more noisy and asynchronous (than
normal conditions) output, mainly due to very low load. If the Pulse-Skip is not compatible
with the application, the PM6675S allows the user to choose between forced-PWM and No-
Audible Pulse-Skip alternative modes (see Section 7.1.4: Mode-of-operation selection on
page 30 for details).
Output
voltage
Inductor
current
V
reg
T
ON
T
OFF
T
IDLE
t
ON
OUTIN
LOAD T
L2
VV
)Skip2PWM(I
=
PM6675S Device description
29/53
No-audible pulse-skip mode
Some audio-noise sensitive applications cannot accept the switching frequency to enter the
audible range as it is possible in Pulse-Skip mode with very light loads. For this reason, the
PM6675S implements an additional feature to maintain a minimum switching frequency of
33kHz despite a slight efficiency loss. At very light load conditions, if any switching cycle has
taken place within 30µs (typ.) since the last one (because of the output voltage is still higher
than the reference), a No-Audible Pulse-Skip cycle begins. The low-side MOSFET is turned
on and the output is driven to fall until the reference point has been crossed. Then, the high-
side switch is turned on for a TON period and, once it has expired, the synchronous rectifier
is enabled until the inductor current reaches the zero-crossing threshold (see Figure 38).
Figure 38. Inductor current and output voltage at light load with non-audible pulse-skip
For frequencies higher than 33 kHz (due to heavier loads) the device works in the same way
as in Pulse-Skip mode. It is important to notice that in both Pulse-Skip and No-Audible
Pulse-Skip modes, the switching frequency changes not only with the load but also with the
input voltage.
Output
voltage
Inductor
current
V
reg
t
T
MAX
T
ON
T
OFF
T
IDLE
30/53 R5 R8 \—o F/— NOSKIP The PM667SS has been designed to satisfy the widest range of applications. The device is provided with some multilevel pins which allow the user to choose the appropriate configuration. The VSEL pin is used to firstly decide between fixed preset or adjustable (user defined) output voltages. When the VSEL pin is connected to +5 V, the PM667SS sets the switching section output voltage to 1.5 V without the need of an external divider. Applications requiring different output voltages can be managed by PM667SS simply setting the ad)ustaple mode. Consider that if the VSEL pin voltage is higher than 4 V, the fixed output mode is selected. When connecting an external divider to the VSEL pin, it is used as negative input of the error amplifier and the output voltage is given by expression (20). Equation 20 The output voltage can be set in the range from 0.6 V to 3.3 V. The NOSKIP is the power saving algorithm selector: if tied to +5 V, the lorced»PWM (fixed frequency) control is performed. It grounded or connected to VREF pin (1.237 V reference voltage), the Pulse»Skip or Non»Audible Pulse-Skip Modes are respectively selected.
Device description PM6675S
30/53
7.1.4 Mode-of-operation selection
Figure 39. VSEL and NOSKIP multifunction pin configurations
The PM6675S has been designed to satisfy the widest range of applications. The device is
provided with some multilevel pins which allow the user to choose the appropriate
configuration. The VSEL pin is used to firstly decide between fixed preset or adjustable
(user defined) output voltages.
When the VSEL pin is connected to +5 V, the PM6675S sets the switching section output
voltage to 1.5 V without the need of an external divider.
Applications requiring different output voltages can be managed by PM6675S simply setting
the adjustable mode. Consider that if the VSEL pin voltage is higher than 4 V, the fixed
output mode is selected. When connecting an external divider to the VSEL pin, it is used as
negative input of the error amplifier and the output voltage is given by expression (20).
Equation 20
The output voltage can be set in the range from 0.6 V to 3.3 V.
The NOSKIP is the power saving algorithm selector: if tied to +5 V, the forced-PWM (fixed
frequency) control is performed. If grounded or connected to VREF pin (1.237 V reference
voltage), the Pulse-Skip or Non-Audible Pulse-Skip Modes are respectively selected.
PM6675
NOSKIP
VSEL
R9
R8
VOUT
+5V
VREF
PM6675S
8R
9R8R
6.0VOUTADJ
+
=
41 ill rWVN PHASE 100% Rm A csms >—l:|—- lvttt __ LGATE —|E> '- PGND J. An internal tOO uA current source is connected to CSNS pin that is input of the positive current limit comparator. When the voltage dro sensing parameter equals the voltage drop across the programmin controller skips subsequent cycles until the overcurrent condition is UV protection latches off the device (see Section 7.1.11: Switching protections on page 34). Referring to Figure 40, the RDSW‘) sensing technique allows high e without the need tor an external sensing resistor. The onrresistanc affected by temperature drift and nominal value spread of the para considered during the RNA setting resistor design.
PM6675S Device description
31/53
7.1.5 Current sensing and current limit
The PM6675S switching controller uses a valley current sensing algorithm to properly
handle the current limit protection and the inductor current zero-crossing information. The
current is detected during the conduction time of the low-side MOSFET. The current sensing
element is the on-resistance of the low-side switch. The sensing scheme is visible in
Figure 40.
Figure 40. Current sensing scheme
An internal 100 µA current source is connected to CSNS pin that is also the non-inverting
input of the positive current limit comparator. When the voltage drop developed across the
sensing parameter equals the voltage drop across the programming resistor RILIM, the
controller skips subsequent cycles until the overcurrent condition is detected or the output
UV protection latches off the device (see Section 7.1.11: Switching section OV and UV
protections on page 34 ).
Referring to Figure 40, the RDS(on) sensing technique allows high efficiency performance
without the need for an external sensing resistor. The on-resistance of the MOSFET is
affected by temperature drift and nominal value spread of the parameter itself; this must be
considered during the RILIM setting resistor design.
Table 8. Mode-of-operation settings summary
VSEL NOSKIP VOUT Operating mode
VVSEL > 4.3 V
VNOSKIP > 4.2 V
1.5 V
Forced-PWM
1V <VNOSKIP < 3.5 V Non-audible pulse-skip
< 0.5 V Pulse-skip
VVSEL < 3.7 V
VNOSKIP > 4.2 V
ADJ
Forced-PWM
1V <VNOSKIP < 3.5 V Non-audible pulse-skip
VNOSKIP < 0.5 V Pulse-skip
HGATE
PHASE
CSNS
LGATE
PGND
PM6675
100µA·
R
ILIM
V
IN
V
OUT
I
VALLEY
·
R
DSon
HGATE
PHASE
CSNS
LGATE
PGND
PM6675
100µA·
R
ILIM
V
IN
V
OUT
I
VALLEY
·
R
DSon
PM6675S
Device description PM6675S
32/53
It must be taken into account that the current limit circuit actually regulates the inductor
valley current. This means that RILIM must be calculated to set a limit threshold given by the
maximum DC output current plus half of the inductor ripple current:
Equation 21
The PM6675S provides also a fixed negative current limit to prevent excessive reverse
inductor current when the switching section sinks current from the load in forced-PWM (3rd
quadrant working conditions). This negative current limit threshold is measured between
PHASE and PGND pins, comparing the drop magnitude on PHASE pin with an internal
110 mV fixed threshold.
7.1.6 POR, UVLO and soft-start
The PM6675S automatically performs an internal startup sequence during the rising phase
of the analog supply of the device (AVCC). The switching controller remains in a stand-by
state until AVCC crosses the upper UVLO threshold (4.25 V typ.), keeping active the internal
discharge MOSFETs (only if AVCC > 1V).
The soft-start allows a gradual increase of the internal current limit threshold during startup
reducing the input/output surge currents. At the beginning of start-up, the PM6675S current
limit is set to 25 % of nominal value and the Under Voltage Protection is disabled. Then, the
current limit threshold is sequentially brought to 100 % in four steps of approximately 750 µs
(Figure 41).
Figure 41. Soft-start waveforms
After a fixed 3ms total time, the soft-start finishes and UVP is released: if the output voltage
doesn't reach the under voltage threshold within soft-start duration, the UVP condition is
detected and the device performs a soft-end and latches off. Depending on the load
conditions, the inductor current may or may not reach the nominal value of the current limit
during the soft-start (Figure 42 shows two examples).
DSon
ILIM
CL R
R
A100I µ=
SWEN
Current limit threshold
Switching output
Time
VOUT VOUT
PM6675S Device description
33/53
7.1.7 Switching section power good signal
The SPG pin is an open drain output used to monitor output voltage through VSNS (in fixed
output voltage mode) or VSEL (in adjustable output voltage mode) pins and is enabled after
the soft-start timer has expired. The SPG signal is held low if the output voltage drops 10%
below or rises 10 % above the nominal regulated value. The SPG output can sink current up
to 4 mA.
7.1.8 Switching section output discharge
Active soft-end of the output occurs when the SWEN (SWitching ENable) is forced low.
When the switching section is turned off, an internal 25 resistor discharges the output
through the VSNS pin.
Figure 43. Switching section soft-end
Figure 42. Soft-start at heavy load (a) and short-circuit (b) conditions, Pulse-Skip enabled
(a)
(b)
SWEN
VOUT
Resistive Discharge
Device description PM6675S
34/53
7.1.9 Gate drivers
The integrated high-current gate drivers allow using different power MOSFETs. The high-
side driver uses a bootstrap circuit which is supplied by the +5 V rail. The BOOT and
PHASE pins work respectively as supply and return path for the high-side driver, while the
low-side driver is directly fed through VCC and PGND pins.
An important feature of the PM6675S gate drivers is the Adaptive Anti-Cross-Conduction
circuitry, which prevents high-side and low-side MOSFETs from being turned on at the same
time. When the high-side MOSFET is turned off, the voltage at the PHASE node begins to
fall. The low-side MOSFET is turned on only when the voltage at the PHASE node reaches
an internal threshold (2.5 V typ.). Similarly, when the low-side MOSFET is turned off, the
high-side one remains off until the LGATE pin voltage is above 1 V.
The power dissipation of the drivers is a function of the total gate charge of the external
power MOSFETs and the switching frequency, as shown in the following equation:
Equation 22
The low-side driver has been designed to have a low-resistance pull-down transistor
(0.6 typ.) in order to prevent undesired start-up of the low-side MOSFET due to the Miller
effect.
7.1.10 Reference voltage and bandgap
The 1.237 V internal bandgap reference has a granted accuracy of ±1 % over the 0 °C to
85 °C temperature range. The VREF pin is a buffered replica of the bandgap voltage. It can
supply up to ±100 µA and is suitable to set the intermediate level of NOSKIP multifunction
pin. A 100 nF (min.) bypass capacitor toward SGND is required to enhance noise rejection.
If VREF falls below 0.8 V (typ.), the system detects a fault condition and all the circuitry is
turned off.
An internal divider derives a 0.6 V ± 1 % voltage (Vr) from the bandgap. This voltage is used
as reference for both the switching and the linear sections. The Over-Voltage Protection, the
Under-Voltage Protection and the power-good signals are also referred to Vr.
7.1.11 Switching section OV and UV protections
When the switching output voltage is about 115 % of its nominal value, a latched Over-
Voltage Protection (OVP) occurs. In this case the synchronous rectifier immediately turns on
while the high-side MOSFET turns off. The output capacitor is rapidly discharged and the
load is preserved from being damaged. The OVP is also active during the soft-start. Once
an OVP has taken part, a toggle on SWEN pin or a Power-On-Reset is necessary to exit
from the latched state.
When the switching output voltage is below 70 % of its nominal value, a latched Under-
Voltage Protection occurs. This event causes the switching section to be immediately
disabled and both switches to be opened. The controller performs a soft-end and the output
is eventually kept to ground, turning the low side MOSFET on when the voltage is lower than
400 mV.
The Under-Voltage Protection circuit is enabled only at the end of the soft-start. Once an
UVP has taken part, a toggle on SWEN pin or a Power-On-Reset is necessary to clear the
fault state and restart the section.
SWgDRVD fQV)driver(P =
PM6675S Device description
35/53
7.1.12 Device thermal protection
The internal control circuitry of the PM6675S self-monitors the junction temperature and
turns all outputs off when the 150 °C limit has been overrun. This event causes the switching
section to be immediately disabled and both switches to be opened. The controller performs
a soft-end and both the outputs are eventually kept to ground, then the low side MOSFET is
turned on when the voltage of the switching section is lower than 400 mV.
The thermal fault is a latched protection and, in normal operating conditions it is restored by
a Power-On Reset or toggling SWEN and LEN pins at the same time.
7.2 LDO linear regulator section
The independent Low-Drop-Out (LDO) linear regulator has been designed to sink and
source up to 2 A peak current and 1 A continuously. The LDO output voltage can be
adjusted in the range 0.6 V to 3.3 V simply connecting a resistor divider as shown in
Figure 44.
Equation 23
Figure 44. LDO output voltage selection
Table 9. Switching section OV, UV and OT Faults management
Fault Conditions Action
Over voltage VOUT > 115 % of the
nominal value
LGATE pin is forced high and the device latches off.
Exit by a Power-On Reset or toggling SWEN
Under voltage VOUT < 70 % of the
nominal value
LGATE pin is forced high after the soft-end, then the
device latches off. Exit by a Power-On Reset or
toggling SWEN.
Junction over
temperature TJ > +150 °C
LGATE pin is forced high after the soft-end, then the
device latches off. Exit by a Power-On Reset or
toggling SWEN and LEN after 15°C temperature
drop.
20R
20R19R
6.0VLDOADJ
+
=
PM6675
LFB
LOUT
R19
R20
V
LOUT
LGND
Cc
C
OUT
PM6675S
36/53 L Ff The maximum currem ihai 1he LDO can some voiiages. Due 10 the high Side MOSFET of me currem ax high ouiput voliages. In Figure 46 ii can source as funciion of me inpui and ouipui me maximum omput curreni is limited as repo
Device description PM6675S
36/53
A compensation capacitor Cc must be added to adjust the dynamic response of the loop.
The value of Cc is calculated according to the desired bandwidth of the LDO regulator and
depends on the value of the feedback resistors. In most of applications the pole due to the
compensation capacitor is placed at 100-200 kHz (equation 24).
Equation 24
The LIN input can be connected to the switching section output for compact solutions or to a
lower supply, if available in the system, in order to reduce the power dissipation of the LDO.
A minimum output capacitance of 20 µF (2x10 µF MLCC capacitors) is enough to assure
stability and fast load transient response.
7.2.1 LDO section current limit
The LDO regulator can handle up to ±2 Apk, depending on the LDO input voltage and the
LILIM pin setting. The output current is limited to ±1 A or ±2 A if the LILIM pin is connected
to SGND or AVCC respectively (Figure 45).
Figure 45. LDO current limit setting
The maximum current that the LDO can source depends also on the input and output
voltages. Due to the high side MOSFET of the output stage, the LDO cannot source the limit
current at high output voltages. In Figure 46 it is shown the maximum current that the LDO
can source as function of the input and output voltages. For output voltages higher than 2 V,
the maximum output current is limited as reported.
kHz200
C)20R19R(2
1
f
C
p=
π
=
PM6675
LILIM
+5V
±2A CL
±1A CL
PM6675S
7.2.2 7.2.3 7.2.4 Illlllll ILOUT [A] 2,0 1,8 1,6 1,4 1,2 1,0 0,8 0,6 0,4 0,2 0,0 2 5 3 0 3 0.0 0.5 1.0 15 2 0 . . 5 4,0 4 5 5.0 VLIN [V] LDO section soft-start The LDO section soft-start is performed by clamping the current limit. During startup, the LDC current limit voltage is set to 1A and the output voltage increases linearly. When the output voltage rises above 90 % of the nominal value, the current limit is released to 2 A according to the LILIM pin setting. At the end of the ramp-up phase of the soft-start, the LPG signal is masked for about 100 its in order to ignore dynamic overshoot on the feedback pin. LDO section power good signal The LPG pin is an open drain output used to monitorthe LDO output voltage through LFB pin. The LPG signal is held low it the output voltage drops 10 % below or rises 10 % above the nominal regulated value. The LPG output can sink current up to 4 mA. LDO section output discharge Active soft»end of the LDC output occurs when the LEN (Linear ENable) is lorced low. When the LDC section is turned oft, an internal 25 Q resistor, directly connected to the LOUT pin, discharges the output. Figure 47. LDO section soft-end 37/53
PM6675S Device description
37/53
Figure 46. Maximum LDO source able output current vs input voltage
7.2.2 LDO section soft-start
The LDO section soft-start is performed by clamping the current limit. During startup, the
LDO current limit voltage is set to 1A and the output voltage increases linearly. When the
output voltage rises above 90 % of the nominal value, the current limit is released to 2 A
according to the LILIM pin setting. At the end of the ramp-up phase of the soft-start, the LPG
signal is masked for about 100 µs in order to ignore dynamic overshoot on the feedback pin.
7.2.3 LDO section power good signal
The LPG pin is an open drain output used to monitor the LDO output voltage through LFB
pin.
The LPG signal is held low if the output voltage drops 10 % below or rises 10 % above the
nominal regulated value. The LPG output can sink current up to 4 mA.
7.2.4 LDO section output discharge
Active soft-end of the LDO output occurs when the LEN (Linear ENable) is forced low. When
the LDO section is turned off, an internal 25 resistor, directly connected to the LOUT pin,
discharges the output.
Figure 47. LDO section soft-end
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VLIN [V]
ILOUT [A]
VOUT=1.05V
VOUT=1.2V
VOUT=1.5V
VOUT=1.8V
VOUT=2.0V
VOUT=2.2V
VOUT=2.5V
VOUT=3.3V
LEN
VLDO
Resistive Discharge
Application information PM6675S
38/53
8 Application information
The purpose of this chapter is showing the design procedure of the switching section.
The design starts from three main specifications:
The input voltage range, provided by the battery or the external supply. The two
extreme values (VINMAX and VINmin ) are important for the design.
The maximum load current, indicated with ILOAD,MAX.
The maximum allowed output voltage ripple VRIPPLE,MAX.
It's also possible that specific designs should involve other specifications.
The following paragraphs will guide the user into a step-by-step design.
8.1 External components selection
The PM6675S uses a pseudo-fixed frequency, Constant On-Time (COT) controller as the
core of the switching section. The switching frequency can be set by connecting an external
divider to the VOSC pin. The voltage seen at this pin must be greater than 0.8V and lower
than 2 V in order to ensure system linearity.
Nearly constant switching frequency is achieved by the system loop in steady-state
operating conditions by varying the On-Time duration, avoiding thus the need for a clock
generator. The On-Time one shot duration is directly proportional to the output voltage,
sensed at VSNS pin, and inversely proportional to the input voltage, sensed at the VOSC
pin, as follows:
Equation 25
where KOSC is a constant value (130 ns typ.) and τ is the internal propagation delay
(40 ns typ.).
The duty cycle of the buck converter is, in under steady state conditions, given by
Equation 26
The switching frequency is thus calculated as
Equation 27
τ+=
OSC
SNS
OSCON V
V
KT
IN
OUT
V
V
D=
OSCOUT
OSC
OSC
SNS
OSC
IN
OUT
ON
SW K
1
V
V
K
V
V
T
D
f
α
α
=
==
PM6675S Application information
39/53
where
Equation 28a
Equation 28b
Referring to the typical application schematic (figure in cover page and Figure 33), the final
expression is then:
Equation 29
The switching frequency directly affects two parameters:
Inductor size: greater frequencies mean smaller inductances. In notebook applications,
real estate solutions (i.e. low-profile power inductors) are mandatory also with high
saturation and r.m.s. currents.
Efficiency: switching losses are proportional to the frequency. Generally, higher
frequencies imply lower efficiency.
Even if the switching frequency is theoretically independent from battery and output
voltages, parasitic parameters involved in power path (like MOSFETs on-resistance and
inductor DCR) introduce voltage drops responsible for a slight dependence on load current.
In addition, the internal delay is cause of a light dependence from input voltage.
IN
OSC
OSC V
V
=α
OUT
SNS
OUT V
V
=α
OSC21
2
OSC
OSC
SW K
1
RR
R
K
f
+
=
α
=
Table 10. Typical values for switching frequency selection
R1 (k)R2 (k) Approx switching frequency (kHz)
330 11 250
330 13 300
330 15 350
330 18 400
330 20 450
330 22 500
Application information PM6675S
40/53
8.1.1 Inductor selection
Once the switching frequency has been defined, the inductance value depends on the
desired inductor ripple current. Low inductance value means great ripple current that brings
poor efficiency and great output noise. On the other hand a great current ripple is desirable
for fast transient response when a load step is applied.
High inductance brings to good efficiency but the transient response is critical, especially if
VINmin - VOUT is little. Moreover a minimum output ripple voltage is necessary to assure
system stability and jitter-free operations (see Section 8.1.3: Output capacitor selection on
page 42). The product of the output capacitor ESR multiplied by the inductor ripple current
must be taken in consideration. A good trade-off between the transient response time, the
efficiency, the cost and the size is choosing the inductance value in order to maintain the
inductor ripple current between 20 % and 50 % (usually 40 %) of the maximum output
current.
The maximum inductor ripple current, IL,MAX , occurs at the maximum input voltage.
Given these considerations, the inductance value can be calculated using the following
expression:
Equation 30
where fSW is the switching frequency, VIN is the input voltage, VOUT is the output voltage and
IL is the inductor ripple current.
Once the inductor value is determined, the inductor ripple current is then recalculated:
Equation 31
The next step is the calculation of the maximum r.m.s. inductor current:
Equation 32
The inductor must have an r.m.s. current greater than IL,RMS in order to assure thermal
stability.
Then the calculation of the maximum inductor peak current follows:
Equation 33
IL,PEAK is important when choosing the inductor, in term of its saturation current.
IN
OUT
L
OUTIN
V
V
Ifsw
VV
L
=
MAX,IN
OUT
OUTMAX,IN
MAX,L V
V
Lfsw
VV
I
=
12
)I(
)I(I
2
MAX,L
2
MAX,LOADRMS,L
+=
2
I
II MAX,L
MAX,LOADPEAK,L
+=
PM6675S Application information
41/53
The saturation current of the inductor should be greater than IL,PEAK as well as for case of
hard saturation core inductors. Using soft-ferrite cores is possible (but not advisable) to push
the inductor working near its saturation current.
In Ta bl e 1 1 some inductors suitable for notebook applications are listed.
In Pulse-Skip Mode, low inductance values produce a better efficiency versus load curve,
while higher values result in higher full-load efficiency because of the smaller current ripple.
8.1.2 Input capacitor selection
In a buck topology converter the current that flows through the input capacitor is pulsed and
with zero average value. The RMS input current can be calculated as follows:
Equation 34
Neglecting the second term, the equation 10 is reduced to:
Equation 35
The losses due to the input capacitor are thus maximized when the duty-cycle is 0.5:
Equation 36
The input capacitor should be selected with a RMS rated current higher than ICINRMS(max).
Tantalum capacitors are good in terms of low ESR and small size, but they occasionally can
burn out if subjected to very high current during operation. Multi-Layers-Ceramic-Capacitors
(MLCC) have usually a higher RMS current rating with smaller size and they remain the best
choice. The drawback is their quite high cost.
Table 11. Evaluated inductors (@fsw = 400 kHz)
Manufacturer Series Inductance (µH) +40 °C RMS
current (A)
-30 % saturation
current (A)
COILCRAFT MLC1538-102 1 13.4 21.0
COILCRAFT MLC1240-901 0.9 12.4 24.5
COILCRAFT MVR1261C-112 1.1 20 20
WURTH 7443552100 1 16 20
COILTRONICS HC8-1R2 1.2 16.0 25.4
2
L
2
LOAD
RMS
Cin )I(D
12
1
)D1(DII +=
)D1(DII LOAD
RMS
Cin =
2
LOADCin
2
CinRMSCinloss (max))I5.0(ESR(max)IESRP ==
Application information PM6675S
42/53
It must be taken into account that in some MLCC the capacitance decreases when the
operating voltage is near the rated voltage. In Ta bl e 1 2 some MLCC suitable for most of
applications are listed.
8.1.3 Output capacitor selection
Using tantalum or electrolytic capacitors, the selection is made referring to ESR and voltage
rating rather than by a specific capacitance value.
The output capacitor has to satisfy the output voltage ripple requirements. At a given
switching frequency, small inductor values are useful to reduce the size of the choke but
increase the inductor current ripple. Thus, to reduce the output voltage ripple a low ESR
capacitor is required.
To reduce jitter noise between different switching regulators in the system, it is preferable to
work with an output voltage ripple greater than 25 mV.
Concerning the load transient requirements, the Equivalent Series Resistance (ESR) of the
output capacitor must satisfy the following relationship:
Equation 37
where VRIPPLE is the maximum tolerable ripple voltage.
In addition, the ESR must be high enough to meet stability requirements. The output
capacitor zero must be lower than the switching frequency:
Equation 38
Table 12. Evaluated MLCC for input filtering
Manufacturer Series Capacitance (µF) Rated voltage (V) Maximum Irms
@100 kHz (A)
TAIYO YUDEN UMK325BJ106KM-T 10 50 2
TAIYO YUDEN GMK316F106ZL-T 10 35 2.2
TAIYO YUDEN GMK325F106ZH-T 10 35 2.2
TAIYO YUDEN GMK325BJ106KN 10 35 2.5
TDK C3225X5R1E106M 10 25
MAX,L
MAX,RIPPLE
I
V
ESR
out
ZSW CESR2
1
ff π
=>
PM6675S Application information
43/53
If ceramic capacitors are used, the output voltage ripple due to inductor current ripple is
negligible. Then the inductance should be smaller, reducing the size of the choke. In this
case it is important that output capacitor can adsorb the inductor energy without generating
an over-voltage condition when the system changes from a full load to a no load condition.
The minimum output capacitance can be chosen by the following equation:
Equation 39
where Vf is the output capacitor voltage after the load transient, while Vi is the output
capacitor voltage before the load transient.
In Ta bl e 1 3 are listed some tested polymer capacitors.
8.1.4 MOSFETs selection
In a notebook application, power management efficiency is a high level requirement.
The power dissipation on the power switches becomes an important factor in the selection
of switches. Losses of high-side and low-side MOSFETs depend on their working condition.
Considering the high-side MOSFET, the power dissipation is calculated as:
Equation 40
Maximum conduction losses are approximately given by:
Equation 41
Table 13. Evaluated output capacitors
Manufacturer Series Capacitance
(µF)
Rated voltage
(V)
ESR max @100 kHz
(m)
SANYO
4TPE220MF 220 4 V 15 to 25
4TPE150MI 220 4 V 18
4TPC220M 220 4 V 40
HITACHI TNCB OE227MTRYF 220 2.5 V 25
22
MAX,LOAD
min,OUT ViVf
IL
C
=2
switchingconductionDHighSide PPP +=
2
MAX,LOAD
min.IN
OUT
DSonconduction I
V
V
RP =
‘ I) m
Application information PM6675S
44/53
where RDS(on) is the drain-source on-resistance of the control MOSFET.
Switching losses are approximately given by:
Equation 42
where tON and tOFF are the turn-on and turn-off times of the MOSFET and depend on the
gate-driver current capability and the gate charge Qgate. A greater efficiency is achieved with
low RDSon. Unfortunately low RDSon MOSFETs have a great gate charge.
As general rule, the RDS(on) x Qgate product should be minimized to find the suitable
MOSFET.
Logic-level MOSFETs are recommended, as long as low-side and high-side gate drivers are
powered by VVCC = +5 V. The breakdown voltage of the MOSFETs (VBRDSS) must be
greater than the maximum input voltage VINmax.
Below some tested high-side MOSFETs are listed.
In buck converters the power dissipation of the synchronous MOSFET is mainly due to
conduction losses:
Equation 43
Maximum conduction losses occur at the maximum input voltage:
Equation 44
The synchronous rectifier should have the lowest RDS(on) as possible. When the high-side
MOSFET turns on, high dV/dt of the phase node can bring up even the low-side gate
through its gate-drain capacitance CRRS, causing a cross-conduction problem. Once again,
the choice of the low-side MOSFET is a trade-off between on resistance and gate charge; a
good selection should minimizes the ratio CRSS / CGS where
Equation 45
Below some tested low-side MOSFETs are listed.
Table 14. Evaluated high-side MOSFETs
Manufacturer Type RDS(on)
(m)
Gate charge
(nC)
Rated reverse
voltage (V)
ST STS12NH3LL 10.5 12 30
IR IRF7811 9 18 30
2
ft)
2
I
(max)I(V
2
ft)
2
I
(max)I(V
P
swoff
L
LOADINswon
L
LOADIN
switching
+
+
=
conductionDLowSide PP
2
MAX,LOAD
MAX,IN
OUT
DSonconduction I
V
V
1RP
=
RSSISSGS CCC
=
PM6675S Application information
45/53
Dual N-MOS can be used in applications with lower output current.
Ta bl e 1 6 shows some suitable dual MOSFETs for applications requiring about 3 A.
8.1.5 Diode selection
A rectifier across the synchronous switch is recommended. The rectifier works as a voltage
clamp across the synchronous rectifier and reduces the negative inductor swing during the
dead time between turning the high-side MOSFET off and the synchronous rectifier on.
Moreover it increases the efficiency of the system.
Choose a schottky diode as long as its forward voltage drop is very little (0.3 V). The reverse
voltage should be greater than the maximum input voltage VINmax and a minimum recovery
reverse charge is preferable. Ta b le 1 7 shows some evaluated diodes.
Table 15. Evaluated low-side MOSFETs
Manufacturer Type RDS(on) (m)CGD \ CGS Rated reverse voltage (V)
ST STS12NH3LL 13.5 0.069 30
ST STS25NH3LL 4.0 0.011 30
IR IRF7811 24 0.054 30
Table 16. Suitable dual MOSFETs
Manufacturer Type RDSon (m)Gate charge (nC) Rated reverse voltage (V)
ST STS8DNH3LL 25 10 30
IR IRF7313 46 33 30
Table 17. Evaluated recirculation rectifiers
Manufacturer Type Forward
voltage (V)
Rated reverse
voltage (V) Reverse current (µA)
ST STPS1L30M 0.34 30 0.00039
ST STPS1L30A 0.34 30 0.00039
Application information PM6675S
46/53
8.1.6 VOUT current limit setting
The valley current limit is set by RCSNS and must be chosen to support the maximum load
current. The valley of the inductor current ILvalley is:
Equation 46
The output current limit depends on the current ripple as shown in Figure 48:
Figure 48. Valley current limit waveforms
As the valley threshold is fixed, the greater the current ripple, the greater the DC output
current will be. If an output current limit greater than ILOAD(max) over all the input voltage
range is required, the minimum current ripple must be considered in the previous formula.
Then the resistor RCSNS is:
Equation 47
where RDSon is the drain-source on-resistance of the low-side switch. Consider the
temperature effect and the worst case value in RDSon calculation (typically +0.4 % / °C).
The accuracy of the valley current also depends on the offset of the internal comparator (±5
mV).
The negative valley-current limit (if the device works in forced-PWM mode) is given by:
Equation 48
2
I
(max)II L
LOADLvalley
=
Inductor current
Valley current limit
MAX LOAD 1
MAX LOAD 2
Inductor current
Current
Time
uA100
IR
RLvalleyDSon
CSNS
=
DSon
NEG R
mV110
I=
Tan One-sum generator + PW Comparalo comp f The stability of me syslem firstly depends on me oulpm capacllor verifled mat Equation 49 where k lS a lree deslgn parameler grealer man unlly (K > 3) . l1 imegrator capacitor value CWT: Equation 50 If Ihe ripple on Ihe COMP pln ls grealer than me imegramr oulpu addilional capacllor CM could be added in order lo reduce ils am anenuation lactor cl Ihe ompul ripple, select
PM6675S Application information
47/53
8.1.7 All ceramic capacitors application
Design of external feedback network depends on the output voltage ripple across the output
capacitors ESR. If the ripple is great enough (at least 20 mV), the compensation network
simply consists of a CINT capacitor.
Figure 49. Integrative compensation
The stability of the system firstly depends on the output capacitor zero frequency. It must be
verified that:
Equation 49
where k is a free design parameter greater than unity (k > 3) . It determines the minimum
integrator capacitor value CINT:
Equation 50
If the ripple on the COMP pin is greater than the integrator output dynamic (150 mV), an
additional capacitor Cfilt could be added in order to reduce its amplitude. If q is the desired
attenuation factor of the output ripple, select:
C
FILT
C
INT
R
INT
g
m
+
-
VREF
VSNS
Ton One-shot
generator
Vr=0.9
V
PWM
Comparator
+
-
COMP
VOUT
Integrator
VREF
0.6V
outout
ZoutSW CR2
k
fkf π
=>
Vo
Vref
f
k
f
2
g
C
Zout
SW
m
INT
π
>
48/53 Ton Block Generalion ' pwm Campmamv Selecx C as shown: Equation 53
Application information PM6675S
48/53
Equation 51
In order to reduce noise on the COMP pin, it's possible to introduce a resistor RINT that,
together with CINT and Cfilt, becomes a low pass filter. The cutoff frequency fCUT must be
much greater (10 or more times) than the switching frequency:
Equation 52
For most applications both RINT and Cfilt are unnecessary.
If the ripple is very small (e.g. such as with ceramic capacitors), a further compensation
network, called "Virtual ESR" network, is needed. This additional part generates a triangular
ripple that substitutes the ESR output voltage ripple. The complete compensation scheme is
represented in Figure 50.
Figure 50. Virtual ESR network
Select C as shown:
Equation 53
q
)q1(C
CINT
filt
=
FILTINT
FILTINT
CUT
INT
CC
CC
f2
1
R
+
π
=
Vr C
FILT
C
INT
R
INT
PWM Comparator
g
m
+
-
+
-
1.237V
VOUT
Ton
Generation
Block
C
RR1
L
Integrator
VREF
0.6V
INT
C5C
>
PM6675S Application information
49/53
Then calculate R in order to have enough ripple voltage on the integrator input:
Equation 54
Where RVESR is the new virtual output capacitor ESR. A good trade-off is to consider an
equivalent ESR of 30-50 m , even though the choice depends on inductor current ripple.
Then choose R1 as follows:
Equation 55
CR
L
R
VESR
=
Cf
1
R
Cf
1
R
1R
Z
Z
π
π
=
Package mechanical data PM6675S
50/53
9 Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Table 18. VFQFPN-24 4 mm x 4 mm mechanical data
Dim.
mm.
Min Typ Max
A 0.80 0.90 1.00
A1 0.0 0.05
A2 0.65 0.80
D 4.00
D1 3.75
E4.00
E1 3.75
θ12°
P 0.240.420.60
e0.50
N 24.00
Nd 6.00
Ne 6.00
L 0.300.400.50
b 0.18 0.30
D2 1.95 2.10 2.25
E2 1.95 2.10 2.25
SEAT‘NG PLANE : Q g l ‘9 G - D > VPIN #1 \D ’ e ‘ 0:0.35 19 24 U LIJ [U U U U ‘ 183 I" C 1 x D E 0‘ “4 § 3 + C ‘ 3‘ D C ' ”3 C a 3 H H H H H H 4‘ ' 12 7 t 44;) “LP < dz="" ,="" b@="" bowom="" v‘ew="">
PM6675S Package mechanical data
51/53
Figure 51. Package dimensions
Revision history PM6675S
52/53
10 Revision history
Table 19. Document revision history
Date Revision Changes
14-Feb-2008 1 Initial release
PM6675S
53/53
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