PIC32MM0256GPM064 Family Errata Datasheet by Microchip Technology

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6‘ MICRDCHIP Programmer > Reconnect andow > Dashr board
2017-2019 Microchip Technology Inc. DS80000729E-page 1
PIC32MM0256GPM064 FAMILY
The PIC32MM0256GPM064 family devices that you
have received conform functionally to the current
Device Data Sheet (DS60001387C), except for the
anomalies described in this document.
The silicon issues discussed in the following pages are
for silicon revisions with the Device and Revision IDs
listed in Table 1. The silicon issues are summarized in
Table 2.
The errata described in this document will be addressed
in future revisions of the PIC32MM0256GPM064 silicon.
Data Sheet clarifications and corrections start on page
10, following the discussion of silicon issues.
The silicon revision level can be identified using the
current version of MPLAB® IDE and Microchip’s
programmers, debuggers and emulation tools, which
are available at the Microchip corporate website
(www.microchip.com).
For example, to identify the silicon revision level
using MPLAB IDE in conjunction with a hardware
debugger:
1. Using the appropriate interface, connect the
device to the hardware debugger.
2. Open an MPLAB IDE project.
3. Configure the MPLAB IDE project for the
appropriate device and hardware debugger.
4. Based on the version of MPLAB IDE you are
using, do one of the following:
a) For MPLAB IDE 8, select Programmer >
Reconnect.
b) For MPLAB X IDE, select Window > Dash-
board and click the Refresh Debug Tool
Status icon ( ).
5. Depending on the development tool used, the
part number and Device Revision ID value
appear in the Output window.
The DEVREV values for the various
PIC32MM0256GPM064 silicon revisions are shown in
Table 1.
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated in the last column of
Table 2 apply to the current silicon
revision (A3).
Note: If you are unable to extract the silicon
revision level, please contact your local
Microchip sales office for assistance.
TABLE 1: SILICON DEVREV VALUES
Part Number Device
ID(1)
Revision ID for
Silicon Revision(2)Part Number Device
ID(1)
Revision ID for Silicon
Revision(2)
A1 A2 A3 A1 A2 A3
PIC32MM0064GPM028 0x7708
01h 02h 03h
PIC32MM0064GPM048 0x772C
01h 02h 03h
PIC32MM0128GPM028 0x7710 PIC32MM0128GPM048 0x7734
PIC32MM0256GPM028 0x7718 PIC32MM0256GPM048 0x773C
PIC32MM0064GPM036 0x770A PIC32MM0064GPM064 0x770E
PIC32MM0128GPM036 0x7712 PIC32MM0128GPM064 0x7716
PIC32MM0256GPM036 0x771A PIC32MM0256GPM064 0x771E
Note 1: The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses of configuration
memory space. They are shown in hexadecimal in the format “DEVID DEVREV”.
2: Refer to the “PIC32MM Families Flash Programming Specification” (DS60001364) for detailed information on
Device and Revision IDs for your specific device.
PIC32MM0256GPM064 Family
Silicon Errata and Data Sheet Clarification
PIC32MM0256GPM064
DS80000729E-page 2 2017-2019 Microchip Technology Inc.
TABLE 2: SILICON ISSUE SUMMARY
Module Feature Item
Number Issue Summary
Affected
Revisions
A1 A2 A3
ADC 12-Bit Conversion 1. The ADC may miss one or more of the
following codes in 12-bit mode: 1023, 2046,
2047, 3070 and 3071.
XXX
ADC Format Options 2. 32-bit signed format option is the same as the
16-bit signed format option.
XXX
UART Receive Buffer
Overflow Disable
3. Overflow disable feature controlled by the
OVFDIS bit is not functional.
X
MCCP OCM3A Output 4. The OCM3A output for MCCP3 is not
functional.
XXX
Primary Oscillator Primary Oscillator
Start-up Timer (OST)
5. The Primary Oscillator Start-up Timer (OST)
may indicate the oscillator is ready for use
and set the POSCRDY (CLKSTAT<2>) bit
too early.
XXX
Reset Reset 6. Current consumption in Reset is high. X X X
Timer1 External Clock Mode 7. Timer1 does not overflow in External Clock
mode when PR1 = 1 and the prescaler is 1:1.
XXX
Timer1 External Clock Mode 8. The first increment value is not visible when
using External Clock mode and a
1:1 prescaler.
XXX
I2C Slave I2C Slave 9. I2C line does not return to Idle after receiving
a NACK from the Master. Writes to I2CxTRN
are not ignored in this condition.
XXX
I2C Slave I2C Slave 10. Slave reports a Bus Collision (BLC) for every
transaction when SBCDE is enabled.
XXX
I2C Slave I2C Slave 11. When BOEN = 0, RBF = 0 and I2COV = 1, a
NACK is generated but the address is not
received.
XXX
I2C Slave I2C Slave 12. The Slave may ACK subsequent data after it
has gone Idle after a NACK.
XXX
I2C Slave I2C Slave 13. The Slave will not Acknowledge reserved
addresses in the111_10xx’ range,
regardless of the STRICT setting.
XXX
Power Retention Sleep 14. When the device wakes up from Retention
Sleep mode, a device Reset may occur. The
BOR, POR and EXTR bits in the RCON
register are set erroneously for this Reset.
X
Programming Programming 15. The JTAG TDO (RC9) pin toggles during
programming when using the PGEC1/PGED1
or PGEC2/PGED2 pairs.
X
Oscillator Secondary Oscillator
(SOSC)
16. Enabling POSC in XT or HS mode may inhibit
SOSC operation.
X
ADC ADC Performance 17. Enabling POSC in XT or HS mode may
degrade ADC performance.
X
Power BOR 18. BOR: The main BOR may not function. X X
I/O Schmitt Trigger Inputs 19. Schmitt Trigger inputs may have glitches with
slow signal rise/fall times.
XX
SPI SRMT Bit 20. In SPI Slave mode, the SRMT bit may be set
if the FIFO or Shift register is not empty.
XXX
MCLR
2017-2019 Microchip Technology Inc. DS80000729E-page 3
PIC32MM0256GPM064
ICSP™
Programming
Programming 21. Programming in Retention Sleep. X X
ICSP Programming Programming 22. Self-programming after a POR or MCLR
Reset.
XX
MCCP Single Edge Compare
Mode
23. The Single Edge Compare mode does not
work when the Timebase Prescaler is not 1:1.
XX
Reset Configuration Mismatch 24. The CMR bit in RCON may be erroneously
set after a POR, BOR or when exiting
Retention Sleep.
XX
ADC Current 25. ADC draws additional current when enabled. X X X
TABLE 2: SILICON ISSUE SUMMARY (CONTINUED)
Module Feature Item
Number Issue Summary
Affected
Revisions
A1 A2 A3
Work around Affected S Work around Work around Affected S Work around Affected con Revisions Work around
PIC32MM0256GPM064
DS80000729E-page 4 2017-2019 Microchip Technology Inc.
Silicon Errata Issues
1. Module: ADC
The ADC may miss one or more of the following
codes in 12-bit mode: 1023, 2046, 2047, 3070
and 3071.
Work around
There is no work around in 12-bit mode. If all
codes are desired in the application, use 10-Bit
Operating mode.
Affected Silicon Revisions
2. Module: ADC
The 32-bit signed format option is the same as
the 16-bit signed format option.
Work around
Use software to correct the output format. Sign-
extend the ADC module’s 16-bit signed integer
output to a 32-bit signed integer. Using the
MPLAB® XC32 C compiler, this can be accom-
plished by casting the ADC1BUFx SFR contents
to a volatile short type, followed by a cast to a
volatile int type.
Affected Silicon Revisions
3. Module: UART
The overflow disable feature controlled by the
OVFDIS bit is not functional.
Work around
None.
Affected Silicon Revisions
4. Module: MCCP
The OCM3A output for MCCP3 is not functional.
Work around
Select the OCM3B, OCM3C, OCM3D output, or
use MCCP1 OCM1A or MCCP2 OCM2A output.
Affected Silicon Revisions
5. Module: Primary Oscillator
The Primary Oscillator Start-up Timer (OST) may
indicate the oscillator is ready for use and set the
POSCRDY (CLKSTAT<2>) bit too early. Clocking
the device before the oscillator is ready may
result in incorrect execution and exceptions.
Work around
Make sure that the Primary Oscillator clock is
ready before using it by following these steps:
1. Running on non-POSC source, request the
POSC clock using a peripheral such as
REFO.
2. Provide a delay to stabilize POSC.
3. Switch to the POSC source.
Example 1 shows a work around for the device
power-on and Example 2 shows the work
around when the device wakes from Sleep.
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A3).
A1 A2 A3
XXX
A1 A2 A3
XXX
A1 A2 A3
X
A1 A2 A3
XXX
Affected con Revisions
2017-2019 Microchip Technology Inc. DS80000729E-page 5
PIC32MM0256GPM064
EXAMPLE 1: USING POSC AT POWER-ON
EXAMPLE 2: USING POSC WHEN AWAKENED FROM SLEEP
Affected Silicon Revisions
#pragma config FNOSC = FRCDIV // Oscillator Selection bits (Fast RC oscillator (FRC))
// Clock Switching Enabled (Failsafe Clock Monitor can be enabled or disabled)
#pragma config FCKSM = CSECMD
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
void main()
{
// configure REFO to request POSC
REFO1CONbits.ROSEL = 2; // POSC = 2
REFO1CONbits.OE = 0; // disable output
REFO1CONbits.ON = 1; // enable module
// wait for POSC stable clock
// this delay may vary depending on different application conditions
// such as voltage, temperature, layout, XT or HS mode and components
{ // delay for 9 ms
unsigned
int start = __builtin_mfc0(_CP0_COUNT, _CP0_COUNT_SELECT);
while((__builtin_mfc0(_CP0_COUNT, _CP0_COUNT_SELECT)) - start < (unsigned int)(0.009*8000000/2));
}
// unlock OSCCON
SYSKEY = 0;
SYSKEY = 0xAA996655;
SYSKEY = 0x556699AA;
// switch to POSC = 2
OSCCONCLR = _OSCCON_NOSC_MASK | _OSCCON_CLKLOCK_MASK | _OSCCON_OSWEN_MASK;
OSCCONSET = (2<<_OSCCON_NOSC_POSITION) | _OSCCON_OSWEN_MASK;
while(OSCCONbits.OSWEN == 1); // wait for switch
// Clock Switching Enabled (Failsafe Clock Monitor can be enabled or disabled)
#pragma config FCKSM = CSECMD
// unlock OSCCON
SYSKEY = 0;
SYSKEY = 0xAA996655;
SYSKEY = 0x556699AA;
// switch to FRC = 0 before entering to sleep
OSCCONCLR = _OSCCON_NOSC_MASK | _OSCCON_CLKLOCK_MASK | _OSCCON_OSWEN_MASK;
OSCCONSET = (0<<_OSCCON_NOSC_POSITION) | _OSCCON_OSWEN_MASK;
while(OSCCONbits.OSWEN == 1); // wait for switch
// enter sleep mode
asm volatile("wait");
// configure REFO to request POSC
REFO1CONbits.ROSEL = 2; // POSC = 2
REFO1CONbits.OE = 0; // disable output
REFO1CONbits.ON = 1; // enable module
// wait for POSC stable clock
// this delay may vary depending on different application conditions
// such as voltage, temperature, layout, XT or HS mode and components
{ // delay for 9 ms
unsigned
int start = __builtin_mfc0(_CP0_COUNT, _CP0_COUNT_SELECT);
while((__builtin_mfc0(_CP0_COUNT, _CP0_COUNT_SELECT)) - start < (unsigned int)(0.009*8000000/2));
}
// switch to POSC = 2
OSCCONCLR = _OSCCON_NOSC_MASK | _OSCCON_CLKLOCK_MASK | _OSCCON_OSWEN_MASK;
OSCCONSET = (2<<_OSCCON_NOSC_POSITION) | _OSCCON_OSWEN_MASK;
while(OSCCONbits.OSWEN == 1); // wait for switch
A1 A2 A3
XXX
Work around MCLR Affected con Revisions Work around Affected con Revisions Work around Affected S Work around Affected S Work around Affected con Revisions Work around Affected con Revisions Work around Affected S Work around Affected S
PIC32MM0256GPM064
DS80000729E-page 6 2017-2019 Microchip Technology Inc.
6. Module: Reset
Current consumption in Master Clear Reset is
high.
Work around
Do not use MCLR to hold device in Reset to
save power.
Affected Silicon Revisions
7. Module: Timer1
Timer1 does not overflow in External Clock
mode when PR1 = 1 and the prescaler is 1:1.
Work around
Use a PR1 value greater than one.
Affected Silicon Revisions
8. Module: Timer1
The first increment value is not visible when
using External Clock mode and a 1:1 prescaler.
Work around
None.
Affected Silicon Revisions
9. Module: I2C Slave
The I2C line does not return to Idle after receiving
a NACK from the Master. Writes to I2CxTRN are
not ignored in this condition.
Work around
Do not write to the I2CxTRN register after a
NACK has been received.
Affected Silicon Revisions
10. Module: I2C Slave
Slave reports a Bus Collision (BLC) for every
transaction when SBCDE is enabled.
Work around
Do not enable SBCDE.
Affected Silicon Revisions
11. Module: I2C Slave
When BOEN = 0, RBF = 0 and I2COV = 1, a
NACK is generated but the address is not
received.
Work around
Service the receive buffer to prevent an overflow.
Affected Silicon Revisions
12. Module: I2C Slave
The Slave may ACK subsequent data after it
has gone Idle after a NACK.
Work around
The Master should not send data following a
NACK without generating a Start condition
Affected Silicon Revisions
13. Module: I2C Slave
The Slave will not Acknowledge reserved
addresses in the ‘111_10xx’ range, regardless
of the STRICT bit setting.
Work around
None.
Affected Silicon Revisions
A1 A2 A3
XXX
A1 A2 A3
XXX
A1 A2 A3
XXX
A1 A2 A3
XXX
A1 A2 A3
XXX
A1 A2 A3
XXX
A1 A2 A3
XXX
A1 A2 A3
XXX
Work around Affected con Revisions Work around Affected con Revisions Work around Work around Affected S Work around Affected S Work around Affected Silicon Revisions
2017-2019 Microchip Technology Inc. DS80000729E-page 7
PIC32MM0256GPM064
14. Module: Power
When the device wakes up from Retention
Sleep mode, a device Reset may occur. The
BOR, POR and EXTR bits in RCON register are
set erroneously for this Reset.
Work around
To provide a consistent behavior when the
device wakes up from the Retention Sleep
mode, the software sequence should be per-
formed following the SLEEP instruction. In this
case, a Reset will always be generated when
the device wakes up from Retention Sleep.
Affected Silicon Revisions
15. Module: Programming
The JTAG TDO (RC9) pin toggles during
programming when using the PGEC1/PGED1
or PGEC2/PGED2 pairs.
Work around
Do not connect external circuitry to the TDO pin
that cannot tolerate toggling when programming
using the PGEC1/PGED1 or PGEC2/PGED2
pins.
Affected Silicon Revisions
16. Module: Oscillator
Enabling POSC in XT or HS mode may inhibit
SOSC operation.
Work around
If SOSC operation is required, use FRC or
FRCPLL instead of POSC.
Affected Silicon Revisions
17. Module: ADC
Enabling POSC in XT or HS mode may degrade
ADC performance in 10-bit and 12-bit mode.
Work around
If ADC operation that meets the data sheet
specification is required, use FRC or FRCPLL
instead of POSC.
Affected Silicon Revisions
18. Module: Power
The main BOR may not occur when the operating
voltage drops below the BOR trip voltage.
Work around
Ensure the device operating voltage does not
violate the specified values.
Use an external supervisor circuit to reset the
device if the operating voltage can be outside
the specified values.
Affected Silicon Revisions
19. Module: I/O
If the input signal rise or fall time is more than
500 nS, the I/O Schmitt Trigger output may have
glitches.
Work around
The rise/fall time of the input signal must be less
than 500 nS.
Affected Silicon Revisions
A1 A2 A3
X
A1 A2 A3
X
A1 A2 A3
X
A1 A2 A3
X
A1 A2 A3
XX
A1 A2 A3
XX
Work around Affected con Revisions MCLR Work around MCLR Affected S on Re MCLR Work around of 3 FOR or MCLR Affected S on Re Work around Affected S
PIC32MM0256GPM064
DS80000729E-page 8 2017-2019 Microchip Technology Inc.
20. Module: SPI
In SPI Slave mode, the SRMT bit may be set if the
FIFO or Shift register is not empty.
Work around
The following work arounds can be imple-
mented in the application to detect when the
FIFO and Shift register are empty:
1. Check the SPITBF bit before checking the
SRMT bit. If the SPITBF flag is cleared and
the SRMT flag is set, then all data was
transmitted. Example 3 demonstrates the
SPITBF and SRMT bits polling.
2. Read the SRMT bit twice, back-to-back. If
the SRMT bit is set two reads in a row, then
the FIFO and Shift register are empty.
Example 4 demonstrates the SRMT bit
polling using double read.
EXAMPLE 3: EMPTY STATUS DETECTION
USING SPITBF AND SRMT
BITS POLLING
EXAMPLE 4:
EMPTY STATUS DETECTION
USING SRMT BIT POLLING
WITH BACK-TO-BACK READS
Affected Silicon Revisions
21. Module: ICSP™ Programming
After a POR or MCLR Reset, the device may fail
to program if Retention Sleep is invoked within
40 ms.
Work around
Provide a delay in firmware to ensure the device
does not enter Retention Sleep within 40 ms of
a POR or MCLR Reset.
Affected Silicon Revisions
22. Module: ICSP Programming
After a POR or MCLR Reset, the device may fail
to program using ICSP if user firmware performs
self-programming within 40 ms.
Work around
Provide a delay in firmware to ensure the device
does not perform self-programming within 40 ms
of a POR or MCLR Reset.
Affected Silicon Revisions
23. Module: MCCP
The Single Edge Compare mode does not work
when the Timebase Prescaler is not 1:1.
Work around
Use 1:1 Prescaler value.
Affected Silicon Revisions
A1 A2 A3
XXX
// Both flags must indicate empty status.
while(SPI1STATLbits.SPITBF);
while(!SPI1STATLbits.SRMT);
// If SRMT bit is set two reads in a row
then it set correctly.
asm volatile("\n\
la $t0, SPI1STAT;\
loop:;\
lw $t1, 0($t0);\
lw $t2, 0($t0);\
and $t1, $t1, $t2;\
andi $t1, $t2, 0x80;\
beqz $t1, loop;");
A1 A2 A3
XX
A1 A2 A3
XX
A1 A2 A3
XX
Work around Work around Affected Silicon Revisions
2017-2019 Microchip Technology Inc. DS80000729E-page 9
PIC32MM0256GPM064
24. Module: Reset
The CMR bit in RCON may be erroneously set
after a POR, BOR or when exiting Retention
Sleep.
Work around
Clear the CMR bit following a POR, BOR or exit
from Retention Sleep.
Affected Silicon Revisions
25. Module: ADC
On some devices, the current draw may
increase by up to 12 mA when the ADC is
enabled. This current draw is not affected by the
device Power Save modes or ADC configura-
tion. This additional current does not affect the
ADC or device performance.
Work around
Disable the ADC when it is not converting or not
used in the application.
Affected Silicon Revisions
A1 A2 A3
XX
A1 A2 A3
XXX
PIC32MM0256GPM064
DS80000729E-page 10 2017-2019 Microchip Technology Inc.
Data Sheet Clarifications
The following typographic corrections and clarifications
are to be noted for the latest version of the device data
sheet (DS60001387C):
None.
Note: Corrections are shown in bold. Where
possible, the original bold text formatting
has been removed for clarity.
Rev A Document (3/2017) Rev B Documenl 5/2017 Rev (2 Document 6/2017 Rev D Document 7/2018 Rev E Documenl 1/2019
2017-2019 Microchip Technology Inc. DS80000729E-page 11
PIC32MM0256GPM064
APPENDIX A: DOCUMENT
REVISION HISTORY
Rev A Document (3/2017)
Initial release of this document; issued for revision A1.
Rev B Document (5/2017)
Adds silicon revision A2.
Updates Ta b l e 1 and Ta b l e 2 .
Adds new silicon issues 18 (Power), 19 (I/O), 20 (SPI)
and 21 (ICSP™ Programming).
Rev C Document (6/2017)
Updates Ta b l e 2 .
Adds new silicon issues 22 (ICSP Programming).
Adds new data sheet clarification 1 (Electrical
Characteristics).
Rev D Document (7/2018)
Adds silicon revision A3.
Adds new silicon issues 23 (MCCP) and 24 (Reset).
Removes data sheet clarification 1 (Electrical Character-
istics) since this issue was corrected in the latest data
sheet revision DS60001387C.
Rev E Document (1/2019)
Adds silicon issue 25 (ADC).
PIC32MM0256GPM064
DS80000729E-page 12 2017-2019 Microchip Technology Inc.
NOTES:
YSTEM
2017-2019 Microchip Technology Inc. DS80000729E-page 13
Information contained in this publication regarding device
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and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
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© 2019, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-4086-4
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
6‘ MICROCHIP AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE
DS80000729E-page 14 2017-2019 Microchip Technology Inc.
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Tel: 630-285-0071
Fax: 630-285-0075
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Novi, MI
Tel: 248-848-4000
Houston, TX
Tel: 281-894-5983
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Tel: 317-536-2380
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Tel: 951-273-7800
Raleigh, NC
Tel: 919-844-7510
New York, NY
Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
Tel: 408-436-4270
Canada - Toronto
Tel: 905-695-1980
Fax: 905-695-2078
ASIA/PACIFIC
Australia - Sydney
Tel: 61-2-9868-6733
China - Beijing
Tel: 86-10-8569-7000
China - Chengdu
Tel: 86-28-8665-5511
China - Chongqing
Tel: 86-23-8980-9588
China - Dongguan
Tel: 86-769-8702-9880
China - Guangzhou
Tel: 86-20-8755-8029
China - Hangzhou
Tel: 86-571-8792-8115
China - Hong Kong SAR
Tel: 852-2943-5100
China - Nanjing
Tel: 86-25-8473-2460
China - Qingdao
Tel: 86-532-8502-7355
China - Shanghai
Tel: 86-21-3326-8000
China - Shenyang
Tel: 86-24-2334-2829
China - Shenzhen
Tel: 86-755-8864-2200
China - Suzhou
Tel: 86-186-6233-1526
China - Wuhan
Tel: 86-27-5980-5300
China - Xian
Tel: 86-29-8833-7252
China - Xiamen
Tel: 86-592-2388138
China - Zhuhai
Tel: 86-756-3210040
ASIA/PACIFIC
India - Bangalore
Tel: 91-80-3090-4444
India - New Delhi
Tel: 91-11-4160-8631
India - Pune
Tel: 91-20-4121-0141
Japan - Osaka
Tel: 81-6-6152-7160
Japan - Tokyo
Tel: 81-3-6880- 3770
Korea - Daegu
Tel: 82-53-744-4301
Korea - Seoul
Tel: 82-2-554-7200
Malaysia - Kuala Lumpur
Tel: 60-3-7651-7906
Malaysia - Penang
Tel: 60-4-227-8870
Philippines - Manila
Tel: 63-2-634-9065
Singapore
Tel: 65-6334-8870
Taiwan - Hsin Chu
Tel: 886-3-577-8366
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Taiwan - Taipei
Tel: 886-2-2508-8600
Thailand - Bangkok
Tel: 66-2-694-1351
Vietnam - Ho Chi Minh
Tel: 84-28-5448-2100
EUROPE
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
Finland - Espoo
Tel: 358-9-4520-820
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Garching
Tel: 49-8931-9700
Germany - Haan
Tel: 49-2129-3766400
Germany - Heilbronn
Tel: 49-7131-67-3636
Germany - Karlsruhe
Tel: 49-721-625370
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Germany - Rosenheim
Tel: 49-8031-354-560
Israel - Ra’anana
Tel: 972-9-744-7705
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Italy - Padova
Tel: 39-049-7625286
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Norway - Trondheim
Tel: 47-7288-4388
Poland - Warsaw
Tel: 48-22-3325737
Romania - Bucharest
Tel: 40-21-407-87-50
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Gothenberg
Tel: 46-31-704-60-40
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Worldwide Sales and Service
08/15/18

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IC MCU 32BIT 64KB FLASH 64TQFP
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IC MCU 32BIT 128KB FLASH 40UQFN
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IC MCU 32BIT 128KB FLASH 64TQFP
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IC MCU 32BIT 256KB FLASH 28SSOP
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IC MCU 32BIT 64KB FLASH 28SSOP
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IC MCU 32BIT 64KB FLASH 48TQFP
IC MCU 32BIT 64KB FLASH 64TQFP
IC MCU 32BIT 128KB FLASH 28QFN
IC MCU 32BIT 128KB FLASH 28SSOP
IC MCU 32BIT 128KB FLASH 36VQFN
IC MCU 32BIT 128KB FLASH 40UQFN
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IC MCU 32BIT 128KB FLASH 48TQFP
IC MCU 32BIT 128KB FLASH 64TQFP
IC MCU 32BIT 256KB FLASH 28QFN
IC MCU 32BIT 256KB FLASH 28SSOP
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IC MCU 32BIT 256KB FLASH 48TQFP
IC MCU 32BIT 256KB FLASH 64TQFP
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IC MCU 32BIT 64KB FLASH 40UQFN
IC MCU 32BIT 64KB FLASH 48UQFN
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IC MCU 32BIT 256KB FLASH 28UQFN
IC MCU 32BIT 64KB FLASH 28UQFN
IC MCU 32BIT 128KB FLASH 28UQFN
IC MCU 32BIT 256KB FLASH 28UQFN
IC MCU 32BIT 64KB FLASH 28UQFN
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128KB FLASH, 16KB RAM, 79 COREMA
128KB FLASH, 16KB RAM, 79 COREMA
128KB FLASH, 16KB RAM, 79 COREMA
128KB FLASH, 16KB RAM, 79 COREMA
256KB FLASH, 32KB RAM, 79 COREMA
256KB FLASH, 32KB RAM, 79 COREMA
256KB FLASH, 32KB RAM, 79 COREMA
256KB FLASH, 32KB RAM, 79 COREMA
128KB FLASH 16KB RAM 79 COREMARK
256KB FLASH 32KB RAM 79 COREMARK
128KB FLASH 16KB RAM 79 COREMARK
256KB FLASH 32KB RAM 79 COREMARK
128KB FLASH 16KB RAM 79 COREMARK
256KB FLASH 32KB RAM 79 COREMARK
128KB FLASH 16KB RAM 79 COREMARK
256KB FLASH 32KB RAM 79 COREMARK