ICM-20948 Datasheet by TDK InvenSense

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ICM-20948
World’s Lowest Power 9-Axis MEMS MotionTracking™ Device
InvenSense reserves the right to change the detail
specifications as may be required to permit
improvements in the design of its products.
TDK Corporation
1745 Technology Drive, San Jose, CA 95110 U.S.A
+1(408) 9887339
www.invensense.com
Document Number: DS-000189
Revision: 1.3
Release Date: 06/02/2017
GENERAL DESCRIPTION
The ICM-20948 is the world’s lowest power 9-axis
MotionTracking device that is ideally suited for Smartphones,
Tablets, Wearable Sensors, and IoT applications.
3-axis gyroscope, 3-axis accelerometer, 3-axis
compass, and a Digital Motion Processor™ (DMPTM)
in a 3 mm x 3 mm x 1 mm (24-pin QFN) package
DMP offloads computation of motion processing
algorithms from the host processor, improving
system power performance
Software drivers are fully compliant with Google’s
latest Android release
EIS FSYNC support
ICM-20948 supports an auxiliary I2C interface to external
sensors, on-chip 16-bit ADCs, programmable digital filters, an
embedded temperature sensor, and programmable
interrupts. The device features an operating voltage range
down to 1.71V. Communication ports include I2C and high
speed SPI at 7 MHz.
Note: ICM-20948 VDDIO range is 1.71V to 1.95V, different
than the MPU-9250 9-axis device.
ORDERING INFORMATION
PART
TEMP RANGE
PACKAGE
ICM-20948† −40°C to +85°C 24-Pin QFN
Denotes RoHS and Green-Compliant Package
BLOCK DIAGRAM
APPLICATIONS
Smartphones and Tablets
Wearable Sensors
IoT Applications
FEATURES
Lowest Power 9-Axis Device at 2.5 mW
3-Axis Gyroscope with Programmable FSR of
±250 dps, ±500 dps, ±1000 dps, and ±2000 dps
3-Axis Accelerometer with Programmable FSR of
±2g, ±4g, ±8g, and ±16g
3-Axis Compass with a wide range to ±4900 µT
Onboard Digital Motion Processor (DMP)
Android support
Auxiliary I2C interface for external sensors
On-Chip 16-bit ADCs and Programmable Filters
7 MHz SPI or 400 kHz Fast Mode I²C
Digital-output temperature sensor
VDD operating range of 1.71V to 3.6V
MEMS structure hermetically sealed and bonded at
wafer level
RoHS and Green compliant
TYPICAL OPERATING CIRCUIT
AUX_CL
VDDIO
SDO
/ AD0
REGOUT
FSYNC
INT1
GND
SCL / SCLK
nCS
RESV
VDD
SDA / SDI
NC
1.71 – 3.6VDC
C2, 0.1 µF
C3, 0.1 µ F
1.71 – 1.95VDC
SCLK
SDI
AUX_DA
SDO
C1, 0.1 µF
RESV
NC
NC
NC
NC
NC
NC
NC
NC
NC
ICM-20948
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nCS
@TDK InvenSense
Document Number: DS-000189 Page 2 of 89
Revision: 1.3
TABLE OF CONTENTS
GENERAL DESCRIPTION ......................................................................................................................................................... 1
ORDERING INFORMATION ..................................................................................................................................................... 1
BLOCK DIAGRAM ................................................................................................................................................................. 1
APPLICATIONS ..................................................................................................................................................................... 1
FEATURES .......................................................................................................................................................................... 1
TYPICAL OPERATING CIRCUIT ................................................................................................................................................. 1
1 GENERAL DESCRIPTION ........................................................................................................................................ 9
1.1 PURPOSE AND SCOPE ............................................................................................................................................... 9
1.2 PRODUCT OVERVIEW ............................................................................................................................................... 9
1.3 APPLICATIONS ......................................................................................................................................................... 9
2 FEATURES .......................................................................................................................................................... 10
2.1 GYROSCOPE FEATURES ........................................................................................................................................... 10
2.2 ACCELEROMETER FEATURES ..................................................................................................................................... 10
2.3 MAGNETOMETER FEATURES .................................................................................................................................... 10
2.4 DMP FEATURES .................................................................................................................................................... 10
2.5 ADDITIONAL FEATURES ........................................................................................................................................... 10
3 ELECTRICAL CHARACTERISTICS ........................................................................................................................... 11
3.1 GYROSCOPE SPECIFICATIONS .................................................................................................................................... 11
3.2 ACCELEROMETER SPECIFICATIONS ............................................................................................................................. 12
3.3 MAGNETOMETER SPECIFICATIONS ............................................................................................................................ 13
3.4 ELECTRICAL SPECIFICATIONS..................................................................................................................................... 13
D.C. Electrical Characteristics ................................................................................................................................... 13
A.C. Electrical Characteristics ................................................................................................................................... 14
Other Electrical Specifications .................................................................................................................................. 15
3.5 I2C TIMING CHARACTERIZATION ............................................................................................................................... 16
3.6 SPI TIMING CHARACTERIZATION ............................................................................................................................... 17
3.7 ABSOLUTE MAXIMUM RATINGS ............................................................................................................................... 18
4 APPLICATIONS INFORMATION ........................................................................................................................... 19
4.1 PIN OUT DIAGRAM AND SIGNAL DESCRIPTION ............................................................................................................ 19
4.2 TYPICAL OPERATING CIRCUIT ................................................................................................................................... 20
4.3 BILL OF MATERIALS FOR EXTERNAL COMPONENTS ....................................................................................................... 20
4.4 EXPOSED DIE PAD PRECAUTIONS .............................................................................................................................. 20
4.5 BLOCK DIAGRAM ................................................................................................................................................... 21
4.6 OVERVIEW ........................................................................................................................................................... 21
4.7 THREE-AXIS MEMS GYROSCOPE WITH 16-BIT ADCS AND SIGNAL CONDITIONING ............................................................ 22
4.8 THREE-AXIS MEMS ACCELEROMETER WITH 16-BIT ADCS AND SIGNAL CONDITIONING ...................................................... 22
4.9 THREE-AXIS MEMS MAGNETOMETER WITH 16-BIT ADCS AND SIGNAL CONDITIONING ..................................................... 22
4.10 DIGITAL MOTION PROCESSOR .................................................................................................................................. 22
4.11 PRIMARY I2C AND SPI SERIAL COMMUNICATIONS INTERFACES ....................................................................................... 22
ICM-20948 Solution Using I2C Interface.................................................................................................................... 22
ICM-20948 Solution Using SPI Interface ................................................................................................................... 23
4.12 AUXILIARY I2C SERIAL INTERFACE .............................................................................................................................. 24
4.13 SELF-TEST ............................................................................................................................................................ 24
4.14 CLOCKING ............................................................................................................................................................ 25
4.15 SENSOR DATA REGISTERS ........................................................................................................................................ 25
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Document Number: DS-000189 Page 3 of 89
Revision: 1.3
4.16 FIFO ................................................................................................................................................................... 25
4.17 FSYNC ................................................................................................................................................................ 25
4.18 INTERRUPTS .......................................................................................................................................................... 25
4.19 DIGITAL-OUTPUT TEMPERATURE SENSOR ................................................................................................................... 26
4.20 BIAS AND LDOS .................................................................................................................................................... 26
4.21 CHARGE PUMP ...................................................................................................................................................... 26
4.22 POWER MODES..................................................................................................................................................... 26
5 PROGRAMMABLE INTERRUPTS .......................................................................................................................... 27
6 DIGITAL INTERFACE ............................................................................................................................................ 28
6.1 I2C AND SPI SERIAL INTERFACES ............................................................................................................................... 28
6.2 I2C INTERFACE ...................................................................................................................................................... 28
6.3 I2C COMMUNICATIONS PROTOCOL ........................................................................................................................... 28
6.4 I2C TERMS ........................................................................................................................................................... 30
6.5 SPI INTERFACE ...................................................................................................................................................... 31
7 REGISTER MAP FOR GYROSCOPE AND ACCELEROMETER ................................................................................... 32
7.1 USER BANK 0 REGISTER MAP .................................................................................................................................. 32
7.2 USER BANK 1 REGISTER MAP .................................................................................................................................. 33
7.3 USER BANK 2 REGISTER MAP .................................................................................................................................. 34
7.4 USER BANK 3 REGISTER MAP .................................................................................................................................. 34
8 USER BANK 0 REGISTER DESCRIPTIONS .............................................................................................................. 36
8.1 WHO_AM_I ....................................................................................................................................................... 36
8.2 USER_CTRL ........................................................................................................................................................ 36
8.3 LP_CONFIG ........................................................................................................................................................ 37
8.4 PWR_MGMT_1 ................................................................................................................................................. 37
8.5 PWR_MGMT_2 ................................................................................................................................................. 38
8.6 INT_PIN_CFG .................................................................................................................................................... 38
8.7 INT_ENABLE ...................................................................................................................................................... 39
8.8 INT_ENABLE_1 .................................................................................................................................................. 39
8.9 INT_ENABLE_2 .................................................................................................................................................. 39
8.10 INT_ENABLE_3 .................................................................................................................................................. 40
8.11 I2C_MST_STATUS ............................................................................................................................................. 40
8.12 INT_STATUS ...................................................................................................................................................... 40
8.13 INT_STATUS_1 .................................................................................................................................................. 41
8.14 INT_STATUS_2 .................................................................................................................................................. 41
8.15 INT_STATUS_3 .................................................................................................................................................. 41
8.16 DELAY_TIMEH ................................................................................................................................................... 41
8.17 DELAY_TIMEL .................................................................................................................................................... 42
8.18 ACCEL_XOUT_H ................................................................................................................................................ 42
8.19 ACCEL_XOUT_L ................................................................................................................................................. 42
8.20 ACCEL_YOUT_H ................................................................................................................................................ 42
8.21 ACCEL_YOUT_L ................................................................................................................................................. 43
8.22 ACCEL_ZOUT_H ................................................................................................................................................ 43
8.23 ACCEL_ZOUT_L ................................................................................................................................................. 43
8.24 GYRO_XOUT_H ................................................................................................................................................. 43
8.25 GYRO_XOUT_L .................................................................................................................................................. 44
8.26 GYRO_YOUT_H ................................................................................................................................................. 44
8.27 GYRO_YOUT_L .................................................................................................................................................. 44
8.28 GYRO_ZOUT_H ................................................................................................................................................. 44
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Document Number: DS-000189 Page 4 of 89
Revision: 1.3
8.29 GYRO_ZOUT_L .................................................................................................................................................. 45
8.30 TEMP_OUT_H ................................................................................................................................................... 45
8.31 TEMP_OUT_L .................................................................................................................................................... 45
8.32 EXT_SLV_SENS_DATA_00 ................................................................................................................................. 45
8.33 EXT_SLV_SENS_DATA_01 ................................................................................................................................. 46
8.34 EXT_SLV_SENS_DATA_02 ................................................................................................................................. 46
8.35 EXT_SLV_SENS_DATA_03 ................................................................................................................................. 46
8.36 EXT_SLV_SENS_DATA_04 ................................................................................................................................. 46
8.37 EXT_SLV_SENS_DATA_05 ................................................................................................................................. 47
8.38 EXT_SLV_SENS_DATA_06 ................................................................................................................................. 47
8.39 EXT_SLV_SENS_DATA_07 ................................................................................................................................. 47
8.40 EXT_SLV_SENS_DATA_08 ................................................................................................................................. 47
8.41 EXT_SLV_SENS_DATA_09 ................................................................................................................................. 48
8.42 EXT_SLV_SENS_DATA_10 ................................................................................................................................. 48
8.43 EXT_SLV_SENS_DATA_11 ................................................................................................................................. 48
8.44 EXT_SLV_SENS_DATA_12 ................................................................................................................................. 48
8.45 EXT_SLV_SENS_DATA_13 ................................................................................................................................. 49
8.46 EXT_SLV_SENS_DATA_14 ................................................................................................................................. 49
8.47 EXT_SLV_SENS_DATA_15 ................................................................................................................................. 49
8.48 EXT_SLV_SENS_DATA_16 ................................................................................................................................. 49
8.49 EXT_SLV_SENS_DATA_17 ................................................................................................................................. 50
8.50 EXT_SLV_SENS_DATA_18 ................................................................................................................................. 50
8.51 EXT_SLV_SENS_DATA_19 ................................................................................................................................. 50
8.52 EXT_SLV_SENS_DATA_20 ................................................................................................................................. 50
8.53 EXT_SLV_SENS_DATA_21 ................................................................................................................................. 51
8.54 EXT_SLV_SENS_DATA_22 ................................................................................................................................. 51
8.55 EXT_SLV_SENS_DATA_23 ................................................................................................................................. 51
8.56 FIFO_EN_1 ........................................................................................................................................................ 52
8.57 FIFO_EN_2 ........................................................................................................................................................ 52
8.58 FIFO_RST ........................................................................................................................................................... 53
8.59 FIFO_MODE ...................................................................................................................................................... 53
8.60 FIFO_COUNTH .................................................................................................................................................. 53
8.61 FIFO_COUNTL ................................................................................................................................................... 53
8.62 FIFO_R_W ......................................................................................................................................................... 54
8.63 DATA_RDY_STATUS .......................................................................................................................................... 54
8.64 FIFO_CFG .......................................................................................................................................................... 54
8.65 REG_BANK_SEL ................................................................................................................................................. 54
9 USR BANK 1 REGISTER DESCRIPTIONS ................................................................................................................ 55
9.1 SELF_TEST_X_GYRO .......................................................................................................................................... 55
9.2 SELF_TEST_Y_GYRO .......................................................................................................................................... 55
9.3 SELF_TEST_Z_GYRO .......................................................................................................................................... 55
9.4 SELF_TEST_X_ACCEL ......................................................................................................................................... 55
9.5 SELF_TEST_Y_ACCEL ......................................................................................................................................... 56
9.6 SELF_TEST_Z_ACCEL ......................................................................................................................................... 56
9.7 XA_OFFS_H ....................................................................................................................................................... 56
9.8 XA_OFFS_L ........................................................................................................................................................ 56
9.9 YA_OFFS_H ....................................................................................................................................................... 56
9.10 YA_OFFS_L ........................................................................................................................................................ 57
9.11 ZA_OFFS_H ....................................................................................................................................................... 57
9.12 ZA_OFFS_L ........................................................................................................................................................ 57
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Document Number: DS-000189 Page 5 of 89
Revision: 1.3
9.13 TIMEBASE_CORRECTION_PLL ........................................................................................................................... 57
9.14 REG_BANK_SEL ................................................................................................................................................. 58
10 USR BANK 2 REGISTER MAP ........................................................................................................................... 59
10.1 GYRO_SMPLRT_DIV .......................................................................................................................................... 59
10.2 GYRO_CONFIG_1 .............................................................................................................................................. 59
10.3 GYRO_CONFIG_2 .............................................................................................................................................. 60
10.4 XG_OFFS_USRH ................................................................................................................................................ 61
10.5 XG_OFFS_USRL ................................................................................................................................................. 62
10.6 YG_OFFS_USRH ................................................................................................................................................ 62
10.7 YG_OFFS_USRL ................................................................................................................................................. 62
10.8 ZG_OFFS_USRH................................................................................................................................................. 62
10.9 ZG_OFFS_USRL ................................................................................................................................................. 62
10.10 ODR_ALIGN_EN ............................................................................................................................................ 63
10.11 ACCEL_SMPLRT_DIV_1 ................................................................................................................................. 63
10.12 ACCEL_SMPLRT_DIV_2 ................................................................................................................................. 63
10.13 ACCEL_INTEL_CTRL ....................................................................................................................................... 63
10.14 ACCEL_WOM_THR ........................................................................................................................................ 64
10.15 ACCEL_CONFIG ............................................................................................................................................. 64
10.16 ACCEL_CONFIG_2 ......................................................................................................................................... 65
10.17 FSYNC_CONFIG ............................................................................................................................................. 66
10.18 TEMP_CONFIG .............................................................................................................................................. 67
10.19 MOD_CTRL_USR ........................................................................................................................................... 67
10.20 REG_BANK_SEL ............................................................................................................................................. 67
11 USR BANK 3 REGISTER MAP ........................................................................................................................... 68
11.1 I2C_MST_ODR_CONFIG .................................................................................................................................... 68
11.2 I2C_MST_CTRL .................................................................................................................................................. 68
11.3 I2C_MST_DELAY_CTRL ...................................................................................................................................... 69
11.4 I2C_SLV0_ADDR ................................................................................................................................................ 69
11.5 I2C_SLV0_REG................................................................................................................................................... 69
11.6 I2C_SLV0_CTRL ................................................................................................................................................. 70
11.7 I2C_SLV0_DO .................................................................................................................................................... 70
11.8 I2C_SLV1_ADDR ................................................................................................................................................ 70
11.9 I2C_SLV1_REG................................................................................................................................................... 71
11.10 I2C_SLV1_CTRL ............................................................................................................................................. 71
11.11 I2C_SLV1_DO ................................................................................................................................................ 72
11.12 I2C_SLV2_ADDR ............................................................................................................................................ 72
11.13 I2C_SLV2_REG............................................................................................................................................... 72
11.14 I2C_SLV2_CTRL ............................................................................................................................................. 73
11.15 I2C_SLV2_DO ................................................................................................................................................ 73
11.16 I2C_SLV3_ADDR ............................................................................................................................................ 73
11.17 I2C_SLV3_REG............................................................................................................................................... 74
11.18 I2C_SLV3_CTRL ............................................................................................................................................. 74
11.19 I2C_SLV3_DO ................................................................................................................................................ 74
11.20 I2C_SLV4_ADDR ............................................................................................................................................ 75
11.21 I2C_SLV4_REG............................................................................................................................................... 75
11.22 I2C_SLV4_CTRL ............................................................................................................................................. 75
11.23 I2C_SLV4_DO ................................................................................................................................................ 75
11.24 I2C_SLV4_DI .................................................................................................................................................. 76
11.25 REG_BANK_SEL ............................................................................................................................................. 76
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Document Number: DS-000189 Page 6 of 89
Revision: 1.3
12 REGISTER MAP FOR MAGNETOMETER ........................................................................................................... 77
12.1 REGISTER MAP DESCRIPTION ................................................................................................................................... 77
13 DETAILED DESCRIPTIONS FOR MAGNETOMETER REGISTERS .......................................................................... 78
13.1 WIA: DEVICE ID ................................................................................................................................................... 78
13.2 ST1: STATUS 1 ..................................................................................................................................................... 78
13.3 HXL TO HZH: MEASUREMENT DATA ........................................................................................................................ 78
13.4 ST2: STATUS 2 ..................................................................................................................................................... 79
13.5 CNTL2: CONTROL 2 .............................................................................................................................................. 79
13.6 CNTL3: CONTROL 3 .............................................................................................................................................. 80
13.7 TS1, TS2: TEST 1, 2 .............................................................................................................................................. 80
14 USE NOTES ..................................................................................................................................................... 81
14.1 GYROSCOPE MODE TRANSITION ............................................................................................................................... 81
14.2 POWER MANAGEMENT 1 REGISTER SETTING .............................................................................................................. 81
14.3 DMP MEMORY ACCESS ......................................................................................................................................... 81
14.4 TIME BASE CORRECTION ......................................................................................................................................... 81
14.5 I2C MASTER CLOCK FREQUENCY ............................................................................................................................... 81
14.6 CLOCKING ............................................................................................................................................................ 82
14.7 LP_EN BIT-FIELD USAGE ........................................................................................................................................ 82
14.8 REGISTER ACCESS USING SPI INTERFACE .................................................................................................................... 82
15 ORIENTATION OF AXES .................................................................................................................................. 83
16 PACKAGE DIMENSIONS .................................................................................................................................. 84
17 PART NUMBER PART MARKINGS.................................................................................................................... 86
18 REFERENCES ................................................................................................................................................... 87
19 DOCUMENT INFORMATION ........................................................................................................................... 88
19.1 REVISION HISTORY ................................................................................................................................................. 88
COMPLIANCE DECLARATION DISCLAIMER ............................................................................................................................... 89
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Document Number: DS-000189 Page 7 of 89
Revision: 1.3
LIST OF FIGURES
Figure 1. I2C Bus Timing Diagram ...................................................................................................................................... 16
Figure 2. SPI Bus Timing Diagram ..................................................................................................................................... 17
Figure 3. Pin out Diagram for ICM-20948 3 mm x 3 mm x 1 mm QFN ............................................................................. 19
Figure 4. ICM-20948 Application Schematic (a) I2C operation (b) SPI operation ............................................................. 20
Figure 5. ICM-20948 Block Diagram ................................................................................................................................. 21
Figure 6. ICM-20948 Solution Using I2C Interface ............................................................................................................ 23
Figure 7. ICM-20948 Solution Using SPI Interface ............................................................................................................ 24
Figure 8. START and STOP Conditions .............................................................................................................................. 28
Figure 9. Acknowledge on the I2C Bus .............................................................................................................................. 29
Figure 10. Complete I2C Data Transfer ............................................................................................................................. 29
Figure 11. Typical SPI Master / Slave Configuration ......................................................................................................... 31
Figure 12. Orientation of Axes of Sensitivity and Polarity of Rotation ............................................................................. 83
Figure 13. Orientation of Axes of Sensitivity for Magnetometer ..................................................................................... 83
Figure 14. Package Dimensions ........................................................................................................................................ 84
Figure 15. Part Number Part Markings ............................................................................................................................. 86
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Document Number: DS-000189 Page 8 of 89
Revision: 1.3
LIST OF TABLES
Table 1. Gyroscope Specifications .................................................................................................................................... 11
Table 2. Accelerometer Specifications ............................................................................................................................. 12
Table 3. Magnetometer Specifications ............................................................................................................................. 13
Table 4. D.C. Electrical Characteristics.............................................................................................................................. 13
Table 5. A.C. Electrical Characteristics .............................................................................................................................. 15
Table 6. Other Electrical Specifications ............................................................................................................................ 15
Table 7. I2C Timing Characteristics ................................................................................................................................... 16
Table 8. SPI Timing Characteristics (7 MHz) ..................................................................................................................... 17
Table 9. Absolute Maximum Ratings ................................................................................................................................ 18
Table 10. Signal Descriptions ............................................................................................................................................ 19
Table 11. Bill of Materials ................................................................................................................................................. 20
Table 12. Power Modes for ICM-20948 ............................................................................................................................ 26
Table 13. Interrupt Sources .............................................................................................................................................. 27
Table 14. Serial Interface .................................................................................................................................................. 28
Table 15. I2C Terms ........................................................................................................................................................... 30
Table 16. Gyroscope Configuration 1 ............................................................................................................................... 60
Table 17. Gyroscope Configuration 2 ............................................................................................................................... 61
Table 18. Accelerator Configuration ................................................................................................................................. 64
Table 19. Accelerator Configuration 2 .............................................................................................................................. 66
Table 20. Register Table for Magnetometer .................................................................................................................... 77
Table 21. Register Map for Magnetometer ...................................................................................................................... 77
Table 22. Magnetometer Measurement Data Format ..................................................................................................... 79
Table 23. I2C Master Clock Frequency .............................................................................................................................. 82
Table 24. Package Dimensions ......................................................................................................................................... 85
Table 26. Part Number Part Markings .............................................................................................................................. 86
@TDK InvenSense
Document Number: DS-000189 Page 9 of 89
Revision: 1.3
1 GENERAL DESCRIPTION
1.1 PURPOSE AND SCOPE
This document is a preliminary data sheet, providing a description, specifications, and design related information on
the ICM-20948 MotionTracking device.
For references to register map and descriptions of individual registers, please refer to the ICM-20948 Register Map
and Register Descriptions document.
1.2 PRODUCT OVERVIEW
The ICM-20948 is a multi-chip module (MCM) consisting of two dies integrated into a single QFN package. One die
houses a 3-axis gyroscope, a 3-axis accelerometer, and a Digital Motion Processor™ (DMP). The other die houses the
AK09916 3-axis magnetometer from Asahi Kasei Microdevices Corporation. The ICM-20948 is a 9-axis MotionTracking
device all in a small 3x3x1mm QFN package. The device supports the following features:
FIFO of size 512 bytes (FIFO size will vary depending on DMP feature-set)
Runtime Calibration
Enhanced FSYNC functionality to improve timing for applications like EIS
ICM-20948 devices, with their 9-axis integration, on-chip DMP, and run-time calibration firmware, enable
manufacturers to eliminate the costly and complex selection, qualification, and system level integration of discrete
devices, guaranteeing optimal motion performance for consumers.
The gyroscope has a programmable full-scale range of ±250 dps, ±500 dps, ±1000 dps, and ±2000 dps. The
accelerometer has a user-programmable accelerometer full-scale range of ±2g, ±4g, ±8g, and ±16g. Factory-calibrated
initial sensitivity of both sensors reduces production-line calibration requirements.
Other key features include on-chip 16-bit ADCs, programmable digital filters, an embedded temperature sensor, and
programmable interrupts. The device features I2C and SPI serial interfaces, a VDD operating range of 1.71V to 3.6V,
and a separate digital IO supply, VDDIO from 1.71V to 1.95V.
Communication with all registers of the device is performed using I2C at up to 100 kHz (standard-mode) or up to
400 kHz (fast-mode), or SPI at up to 7 MHz.
By leveraging its patented and volume-proven CMOS-MEMS fabrication platform, which integrates MEMS wafers with
companion CMOS electronics through wafer-level bonding, InvenSense has driven the package size down to a
footprint and thickness of 3 mm x 3 mm x 1 mm (24-pin QFN), to provide a very small yet high-performance, low-cost
package. The device provides high robustness by supporting 20,000g shock reliability.
1.3 APPLICATIONS
Smartphones and Tablets
Wearable Sensors
IoT Applications
Drones
@TDK InvenSense
Document Number: DS-000189 Page 10 of 89
Revision: 1.3
2 FEATURES
2.1 GYROSCOPE FEATURES
The triple-axis MEMS gyroscope in the ICM-20948 includes the following features:
Digital-output X-, Y-, and Z-axis angular rate sensors (gyroscopes) with a user-programmable full-scale range
of ±250 dps, ±500 dps, ±1000 dps, and ±2000 dps, and integrated 16-bit ADCs
User-selectable ODR; User-selectable low pass filters
Self-test
2.2 ACCELEROMETER FEATURES
The triple-axis MEMS accelerometer in ICM-20948 includes the following features:
Digital-output X-, Y-, and Z-axis accelerometer with a programmable full scale range of ±2g, ±4g, ±8g, and
±16g, and integrated 16-bit ADCs
User-selectable ODR; User-selectable low pass filters
Wake-on-motion interrupt for low power operation of applications processor
Self-test
2.3 MAGNETOMETER FEATURES
The triple-axis MEMS magnetometer in ICM-20948 includes a wide range of features:
3-axis silicon monolithic Hall-effect magnetic sensor with magnetic concentrator
Wide dynamic measurement range and high resolution with lower current consumption.
Output data resolution of 16-bits
Full scale measurement range is ±4900 µT
Self-test function with internal magnetic source to confirm magnetic sensor operation on end products
2.4 DMP FEATURES
The DMP in ICM-20948 includes the following capabilities:
Offloads computation of motion processing algorithms from the host processor. The DMP can be used to
minimize power, simplify timing, simplify the software architecture, and save valuable MIPS on the host
processor for use in applications.
The DMP enables ultra-low power run-time and background calibration of the accelerometer, gyroscope, and
compass, maintaining optimal performance of the sensor data for both physical and virtual sensors generated
through sensor fusion. This enables the best user experience for all sensor enabled applications for the
lifetime of the device.
DMP features simplify the software architecture resulting in quicker time to market.
DMP features are OS, Platform, and Architecture independent, supporting virtually any AP, MCU, or other
embedded architecture.
2.5 ADDITIONAL FEATURES
The ICM-20948 includes the following additional features:
I2C at up to 100 kHz (standard-mode) or up to 400 kHz (fast-mode) or SPI at up to 7 MHz for communication
with registers
Auxiliary master I2C bus for reading data from external sensors (e.g. magnetometer)
Digital-output temperature sensor
20,000g shock tolerant
MEMS structure hermetically sealed and bonded at wafer level
RoHS and Green compliant
@TDK InvenSense FuIIVSCaIe Range GYRO,FS,SEL:O 1250 1105 1 GVR07F575E 1500 1105 1 GYRO,FS,SEL:2 11000 1105 1 GYRO,FS,SEL:3 12000 1105 1 Gyroscope ADC Word Length 15 bits 1 SensIt‘wuy ScaIe Facmr GYRO,FS,SEL:O 131 LSB/IdpsI 1 GVR07F575E 65 5 LSB/Idps) 1 GVR07F575E 32 8 LSB/Idps) 1 GYRO,FS,SEL:3 16 4 LSB/Idps) 1 SensIt‘wuy ScaIe FacmrToIerance z5‘c 11.5 % z SensIt‘wuy ScaIe FecmrvarIaIion Over 740T m +s5‘c 13 % 2 Temperature NonIIneemy aesI m StraIghl Iine; z5“c 10.1 % 2,3 CrossVAxIs Sensnivin 12 % 2,3 lmtIaI ZRO ToIemce z5‘c (ComponenHeveIl 15 1105 2 ZRO Variation OverTemperamre 740T m +s5‘c 10.05 dps/‘C 2 Noise SpecIraI Densny Based on NcIse Bandedm : 0.015 dpS/VHZ z 10 Hz GVROSCOPE MECHANICAL FREQUENCIES 25 27 29 kHz 2 Low PASS FILTER RESPONSE ProgrammabIe Range 5 7 197 Hz 1, 3 GVROSCOPE START-UP TIME From FuHrChip Sleep mode 35 ms 2,3 LowVPower Mode 4 4 562.5 Hz LowVNcise Mode GVROJCHOICEH; GVRCLDLPFCFGq LowVNcise Mode GVROJCHOIC GVRCLDLPFCF
Document Number: DS-000189 Page 11 of 89
Revision: 1.3
3 ELECTRICAL CHARACTERISTICS
3.1 GYROSCOPE SPECIFICATIONS
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
NOTE: All specifications apply to Low-Power Mode and Low-Noise Mode, unless noted otherwise
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
GYROSCOPE SENSITIVITY
Full-Scale Range
GYRO_FS_SEL=0
±250
dps
1
GYRO_FS_SEL=1
±500
dps
1
GYRO_FS_SEL=2
±1000
dps
1
GYRO_FS_SEL=3
±2000
dps
1
Gyroscope ADC Word Length
16
bits
1
Sensitivity Scale Factor
GYRO_FS_SEL=0
131
LSB/(dps)
1
GYRO_FS_SEL=1
65.5
LSB/(dps)
1
GYRO_FS_SEL=2
32.8
LSB/(dps)
1
GYRO_FS_SEL=3
16.4
LSB/(dps)
1
Sensitivity Scale Factor Tolerance
25°C
±1.5
%
2
Sensitivity Scale Factor Variation Over
Temperature
-40°C to +85°C
±3
%
2
Nonlinearity
Best fit straight line; 25°C
±0.1
%
2, 3
Cross-Axis Sensitivity
±2
%
2, 3
ZERO-RATE OUTPUT (ZRO)
Initial ZRO Tolerance
25°C (Component-level)
±5
dps
2
ZRO Variation Over Temperature
-40°C to +85°C
±0.05
dps/°C
2
GYROSCOPE NOISE PERFORMANCE (GYRO_FS_SEL=0)
Noise Spectral Density
Based on Noise Bandwidth =
10 Hz
0.015
dps/√Hz
2
GYROSCOPE MECHANICAL FREQUENCIES
25
27
29
kHz
2
LOW PASS FILTER RESPONSE
Programmable Range
5.7
197
Hz
1, 3
GYROSCOPE START-UP TIME
From Full-Chip Sleep mode
35
ms
2, 3
OUTPUT DATA RATE
Low-Power Mode
4.4
562.5
Hz
1
Low-Noise Mode
GYRO_FCHOICE=1;
GYRO_DLPFCFG=x
4.4 1.125k Hz
Low-Noise Mode
GYRO_FCHOICE=0;
GYRO_DLPFCFG=x
9k Hz
Table 1. Gyroscope Specifications
NOTES:
1. Guaranteed by design.
2. Derived from validation or characterization of parts, not guaranteed in production.
3. Low-noise mode specification.
@TDK InvenSense ACCELJSAJ :2 G 1 ACCEL,FS:1 :4 G 1 ACCEL,FS:2 :8 G 1 ACCEL,FS:3 :15 G 1 ADC Word Length Output in two's complement format 16 Blls 1 ACCEL,FS:0 16,384 LSB/g 1 ACCEL,FS:1 8,192 LSB/g 1 ACCEL,FS:2 4,096 LSB/g 1 ACCEL,FS:3 2,048 LSB/g 1 Initial Tolerance Componentrlevel :0.5 % 2 Nonlinearity Best Flt Straight Line :05 % 2, 3 CrcSS'AXlS SerlSlliv‘ltv :2 % 2, 3 Initial Tolerance Componentrlevel, all axes :25 mg 2 Initial Tolerance Boardrlevel, all axes :50 mg 2 Zeer Level Change vs Temperature at to +85“C :080 mg/‘C 2 Noise Spectral Density Based on Nulse Bandwidth : 10 Hz 230 W/‘IHZ 2 Low PASS FILTER RESPONSE Programmable Range 5.7 245 Hz 1, 3 From Sleep mode 20 ms 2, 3 From Cold Start, 1 ms van ramp 30 ms 2, 3 LowVPower Mode 0.27 552.5 Hz LOWVNO‘lSe Mode ACCELJCHOICE - ACCELDLPFCFGH LOWVNO‘lSe Mode ACCELFCHOICFD; ACCELDLPFCFGH
Document Number: DS-000189 Page 12 of 89
Revision: 1.3
3.2 ACCELEROMETER SPECIFICATIONS
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
NOTES: All specifications apply to Low-Power Mode and Low-Noise Mode, unless noted otherwise
PARAMETER CONDITIONS MIN TYP MAX UNITS NOTES
ACCELEROMETER SENSITIVITY
Full-Scale Range
ACCEL_FS=0
±2
G
1
ACCEL_FS=1
±4
G
1
ACCEL_FS=2
±8
G
1
ACCEL_FS=3
±16
G
1
ADC Word Length
Output in twos complement format
16
Bits
1
Sensitivity Scale Factor
ACCEL_FS=0
16,384
LSB/g
1
ACCEL_FS=1
8,192
LSB/g
1
ACCEL_FS=2
4,096
LSB/g
1
ACCEL_FS=3
2,048
LSB/g
1
Initial Tolerance
Component-level
±0.5
%
2
Sensitivity Change vs. Temperature -40°C to +85°C ACCEL_FS=0 ±0.026 %/ºC 2
Nonlinearity
Best Fit Straight Line
±0.5
%
2, 3
Cross-Axis Sensitivity
±2
%
2, 3
ZERO-G OUTPUT
Initial Tolerance
Component-level, all axes
±25
mg
2
Initial Tolerance
Board-level, all axes
±50
mg
2
Zero-G Level Change vs. Temperature
C to +85°C
±0.80
mg/°C
2
ACCELEROMETER NOISE PERFORMANCE
Noise Spectral Density
Based on Noise Bandwidth = 10 Hz
230
µg/√Hz
2
LOW PASS FILTER RESPONSE
Programmable Range
5.7
246
Hz
1, 3
ACCELEROMETER STARTUP TIME
From Sleep mode
20
ms
2, 3
From Cold Start, 1 ms VDD ramp
30
ms
2, 3
OUTPUT DATA RATE
Low-Power Mode
0.27
562.5
Hz
1
Low-Noise Mode
ACCEL_FCHOICE=1;
ACCEL_DLPFCFG=x
4.5 1.125k Hz
Low-Noise Mode
ACCEL_FCHOICE=0;
ACCEL_DLPFCFG=x
4.5k Hz
Table 2. Accelerometer Specifications
NOTES:
1. Guaranteed by design.
2. Derived from validation or characterization of parts, not guaranteed in production.
3. Low-noise mode specification.
@TDK InvenSense Fullr$cale Range Output Resolutlan Sensiliy‘ny Scale Facmr ln'lllal Calibration Tolerance VDD 1.71 1.8 3 6 < ,_.="" vddio="" 1.71="" 1.8="" 1.95="" v="" 1="" lchnoise="" mode,="" compass="" m="" contlnucus="" mode="" gyroscope="" only="" (dmp,="" bar="" disabledl="" accelerometer="" only="" (dmp,="" bar="" disabledl="" magnetometer="" only="" (dmp,="" acc="" disabledl="" fullrchip="" sleep="" mode="" a="" m="" 2="" specilred="" temperature="" range="" performance="" pararnelers="" are="" npl="" applicable="" beyond="" specified="" temperature="" range="">
Document Number: DS-000189 Page 13 of 89
Revision: 1.3
3.3 MAGNETOMETER SPECIFICATIONS
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS NOTES
MAGNETOMETER SENSITIVITY
Full-Scale Range
±4900
µT
1
Output Resolution
16
bits
1
Sensitivity Scale Factor
0.15
µT / LSB
1
ZERO-FIELD OUTPUT
Initial Calibration Tolerance
-2000
+2000
LSB
2
OTHER
Output Data Rate 100 Hz 1
Table 3. Magnetometer Specifications
NOTES:
1. Guaranteed by design.
2. Derived from validation or characterization of parts, not guaranteed in production.
3.4 ELECTRICAL SPECIFICATIONS
D.C. Electrical Characteristics
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
SUPPLY VOLTAGES
VDD
1.71
1.8
3.6
V
1
VDDIO
1.71
1.8
1.95
V
1
SUPPLY CURRENTS
9-Axis (DMP disabled)
Low-Noise Mode; Compass in Continuous
Mode
3.11 mA 2
Gyroscope Only
(DMP, Barometer & Accelerometer
disabled)
Low-Power Mode, 102.3 Hz update rate, 1x
averaging filter
1.23 mA 2
Accelerometer Only
(DMP, Barometer & Gyroscope
disabled)
Low-Power Mode, 102.3 Hz update rate, 1x
averaging filter
68.9 µA 2
Magnetometer Only
(DMP, Accelerometer & Gyroscope
disabled)
8 Hz update rate
90 µA 2
Full-Chip Sleep Mode
8
µA
2
TEMPERATURE RANGE
Specified Temperature Range
Performance parameters are not applicable
beyond Specified Temperature Range
-40 +85 °C 1
Table 4. D.C. Electrical Characteristics
NOTES:
1. Guaranteed by design.
2. Derived from validation or characterization of parts, not guaranteed in production.
@TDK InvenSense Supply RampTime (T l MonotOniC ramp Ramp 0.01 20 100 ms rate is 10%t final value. Operating Range Ambient 4:0 35 ‘C Sensitivity untrimmeo 333 37 LSB/“C Room Temp Offset 21“c 0 LSE Supply Ramp Time (Trkuel Valio powerrorl RESET 0.01 20 100 ms Startrup time for register read/write From powerrup 11 100 ms A00 : 0 1101000 A00 : 1 1101001 VlH, ngh Level Input Voltage 0.7*VODIO v Vit, Low Level Input Voltage 0.3‘VDDIO V Cr, Input Capacitance < 10="" pf="" vuu,="" high="" level="" output="" voltage="" mama="" mo;="" 0.9*vodio="" v="" von,="" lowrlevel="" output="" voltage="" mama="" mo;="" 0.1‘vddio="" v="" v="" n“,="" int="" lowvlevel="" output="" voltage="" open:1,="" 0="" 3="" ma="" sink="" 0.1="" v="" current="" output="" leakage="" current="" open:1="" 100="" na="" twr,="" int="" pulse="" widtn="" latch,int,en:0="" 50="" ps="" vit,="" low="" level="" input="" voltage="" 0.5v="" 0.3‘vddio="" v="" v="" p,="" highrlevel="" input="" voltage="" 0.7*vodio="" vooio="" +="" v="" 0.5v="" vm,="" hysteresis="" 0.1"vdd|o="" v="" vm,="" lowrlevel="" output="" voltage="" 3="" ma="" sink="" current="" 0="" 0.4="" v="" i="" ,lowrlevel="" output="" current="" v="" :0.4v="" 3="" ma="" vol:d.6v="" 5="" ma="" output="" leakage="" current="" 100="" na="" (or,="" output="" fall="" time="" from="" v="" to="" vleax="" vit,="" lowrlevel="" input="" voltage="" 0.5v="" 0.3‘vddio="" v="" v="" p,="" highrlevel="" input="" voltage="" 07*="" vddio="" vooio="" +="" v="" 0.5v="" vm,="" hysteresis="" 0.1x="" vooio="" v="" v="" 1,="" lowrlevel="" output="" voltage="" vooio=""> 2v; 1 mA sink 0 0.4 v Current V 3, LOWrLevel Output Voltage VOOIO < 2v;="" 1="" ma="" sink="" 0="" 0.2x="" vooio="" v="" current="" i="" ,lowrlevel="" output="" current="" v="" :="" 0="" 4v="" 3="" ma="" vol="" :="" 0="" 5v="" 5="" ma="" output="" leakage="" current="" 100="" na="" (or,="" output="" fall="" time="" from="" v="" to="" cl.="" bus="" capacltance="" in="" pf="" 20+d.1c="" 250="" ns="" vleax="">
Document Number: DS-000189 Page 14 of 89
Revision: 1.3
A.C. Electrical Characteristics
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS NOTES
SUPPLIES
Supply Ramp Time (T
RAMP
)
Monotonic ramp. Ramp
rate is 10% to 90% of the
final value.
0.01
20
100
ms
1
TEMPERATURE SENSOR
Operating Range
Ambient
-40
85
°C
1
Sensitivity
Untrimmed
333.87
LSB/°C
Room Temp Offset
21°C
0
LSB
POWER-ON RESET
Supply Ramp Time (TRAMP)
Valid power-on RESET
0.01
20
100
ms
1
Start-up time for register read/write
From power-up
11
100
ms
1
I2C ADDRESS
AD0 = 0
AD0 = 1
1101000
1101001
DIGITAL INPUTS (FSYNC, AD0, SCLK, SDI, CS)
VIH, High Level Input Voltage
0.7*VDDIO
V
1
VIL, Low Level Input Voltage
0.3*VDDIO
V
CI, Input Capacitance
< 10
pF
DIGITAL OUTPUT (SDO, INT)
VOH, High Level Output Voltage
RLOAD=1 MΩ;
0.9*VDDIO
V
1
VOL1, LOW-Level Output Voltage
RLOAD=1 MΩ;
0.1*VDDIO
V
V
OL.INT1
, INT Low-Level Output Voltage
OPEN=1, 0.3 mA sink
Current
0.1
V
Output Leakage Current
OPEN=1
100
nA
tINT, INT Pulse Width
LATCH_INT_EN=0
50
µs
I
2
C I/O (SCL, SDA)
VIL, LOW Level Input Voltage
-0.5V
0.3*VDDIO
V
1
V
IH
, HIGH-Level Input Voltage
0.7*VDDIO
VDDIO +
0.5V
V
Vhys, Hysteresis
0.1*VDDIO
V
VOL, LOW-Level Output Voltage
3 mA sink current
0
0.4
V
I
OL
, LOW-Level Output Current
V
OL
=0.4V
VOL=0.6V
3
6
mA
mA
Output Leakage Current
100
nA
t
of
, Output Fall Time from V
IHmax
to
VILmax
Cb bus capacitance in pf 20+0.1Cb 250 ns
AUXILLIARY I/O (AUX_CL, AUX_DA)
VIL, LOW-Level Input Voltage
-0.5V
0.3*VDDIO
V
1
V
IH
, HIGH-Level Input Voltage
0.7* VDDIO
VDDIO +
0.5V
V
Vhys, Hysteresis
0.1* VDDIO
V
V
OL1
, LOW-Level Output Voltage
VDDIO > 2V; 1 mA sink
current
0
0.4
V
V
OL3
, LOW-Level Output Voltage
VDDIO < 2V; 1 mA sink
current
0
0.2* VDDIO
V
I
OL
, LOW-Level Output Current
V
OL
= 0.4V
VOL = 0.6V
3
6
mA
mA
Output Leakage Current
100
nA
t
of
, Output Fall Time from V
IHmax
to
VILmax
C
b
bus capacitance in pF
20+0.1C
b
250
ns
@TDK InvenSense Acce‘ercmeter Only Mode 75 +5 % Gyroscope or GrAx‘xs Mode WITHOUT T Corredion Gyroscope or GrAx‘xs Mode WITH Timebase Corremion Frequency Var Temperamre Acce‘ercmeter Only Mode 710 +10 % Gyroscope or GrAx‘xs Mode % 100 :10% High Speed cnarmenzanon 7 110% MHz All regis‘ers, rasmoue 400 kHz All regis‘ers, S‘andardrmode 100 kHz
Document Number: DS-000189 Page 15 of 89
Revision: 1.3
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
INTERNAL CLOCK SOURCE
Clock Frequency Initial Tolerance
Accelerometer Only Mode
-5
+5
%
1
Gyroscope or 6-Axis Mode
WITHOUT Timebase
Correction
-9 +9 %
1
Gyroscope or 6-Axis Mode
WITH Timebase Correction
-1 +1
Frequency Variation over
Temperature
Accelerometer Only Mode
-10
+10
%
1
Gyroscope or 6-Axis Mode
±1
%
1
Table 5. A.C. Electrical Characteristics
NOTES:
1. Derived from validation or characterization of parts, not guaranteed in production.
Other Electrical Specifications
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
SERIAL INTERFACE
SPI Operating Frequency, All
Registers Read/Write
Low Speed Characterization
100
±10%
kHz
High Speed Characterization
7 ±10%
MHz
I2C Operating Frequency
All registers, Fast-mode
400
kHz
All registers, Standard-mode
100
kHz
Table 6. Other Electrical Specifications
NOTES:
1. Derived from validation or characterization of parts, not guaranteed in production.
@TDK InvenSense (m, SCL Clock Frequency 400 kHz 1, z tuosm (Repeated! START Condition Hold 0.5 us 1,2 Time now, SCL Low Period 1.3 us 1, z tum, SCL Hign Period 0.5 us 1,2 (W 5”, Repeated START Condition Setup 0.5 us 1, 2 Time (my my, SDA Data Huid Time 0 us 1,2 [30 w, SDA Data Setup Time 100 nS 1, 2 ti, SDA and SCL Rise Time ci. bus cap. from 10 to 400 pF 20+0 10. 300 nS 1,2 t., SDA and SCL FaH Time ci. bus cap. from 10 to 400 pF 20+0 1Q. 300 nS 1,2 t m, STOP Condition Setup Time 0.5 us 1,2 lam, Bus Free Time Between STOP and 1.3 us 1,2 START Condition ca, Capacitive Load for each Bus Line < 400="" pf="" 1,2="" (vd="" on,="" data="" valid="" time="" 0.9="" us="" 1,="" z="" (w="" w,="" data="" vaiid="" acknuwiedge="" time="" 0.9="" us="" 1,2="">
Document Number: DS-000189 Page 16 of 89
Revision: 1.3
3.5 I2C TIMING CHARACTERIZATION
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETERS CONDITIONS MIN TYPICAL MAX UNITS NOTES
I2C TIMING I2C FAST-MODE
fSCL, SCL Clock Frequency
400
kHz
1, 2
t
HD.STA
, (Repeated) START Condition Hold
Time
0.6
µs
1, 2
tLOW, SCL Low Period
1.3
µs
1, 2
tHIGH, SCL High Period
0.6
µs
1, 2
t
SU.STA
, Repeated START Condition Setup
Time
0.6
µs
1, 2
tHD.DAT, SDA Data Hold Time
0
µs
1, 2
tSU.DAT, SDA Data Setup Time
100
ns
1, 2
tr, SDA and SCL Rise Time
Cb bus cap. from 10 to 400 pF
20+0.1Cb
300
ns
1, 2
tf, SDA and SCL Fall Time
Cb bus cap. from 10 to 400 pF
20+0.1Cb
300
ns
1, 2
t
SU.STO
, STOP Condition Setup Time
0.6
µs
1, 2
t
BUF
, Bus Free Time Between STOP and
START Condition
1.3
µs
1, 2
Cb, Capacitive Load for each Bus Line
< 400
pF
1, 2
tVD.DAT, Data Valid Time
0.9
µs
1, 2
tVD.ACK, Data Valid Acknowledge Time
0.9
µs
1, 2
Table 7. I2C Timing Characteristics
NOTES:
1. Timing Characteristics apply to both Primary and Auxiliary I2C Bus.
2. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets.
SDA
SCL
SDA
SCL
70%
30%
t
f
S
70%
30%
t
r
tSU.DAT
t
r
tHD.DAT
70%
30%
tHD.STA 1/fSCL
1st clock cycle
70%
30%
tLOW tHIGH
tVD.DAT
9th clock cycle
continued below at A
A
Sr PS
70%
30%
tSU.STA tHD.STA tVD.ACK tSU.STO
tBUF
70%
30%
9th clock cycle
t
f
Figure 1. I2C Bus Timing Diagram
@TDK InvenSense
Document Number: DS-000189 Page 17 of 89
Revision: 1.3
3.6 SPI TIMING CHARACTERIZATION
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA=25°C, unless otherwise noted.
PARAMETERS CONDITIONS MIN TYPICAL MAX UNITS NOTES
SPI TIMING
fSCLK, SCLK Clock Frequency
7 MHz
tLOW, SCLK Low Period
64
ns
tHIGH, SCLK High Period
64
ns
tSU.CS, CS Setup Time
8
ns
tHD.CS, CS Hold Time
500
ns
tSU.SDI, SDI Setup Time
5
ns
tHD.SDI, SDI Hold Time
7
ns
tVD.SDO, SDO Valid Time Cload = 20 pF
59 ns
tHD.SDO, SDO Hold Time Cload = 20 pF 6
ns
tDIS.SDO, SDO Output Disable Time
50
ns
Table 8. SPI Timing Characteristics (7 MHz)
NOTES:
1. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets
t
HIGH
70%
30%
1/f
CLK
t
HD;CS
CS
SCLK
SDI
SDO MSB OUT
MSB IN LSB IN
LSB OUT
t
DIS;SDO
70%
30%
t
SU;CS
t
SU;SDI
t
HD;SDI
70%
30%
t
HD;SDO
70%
30%
t
VD;SDO
t
LOW
Figure 2. SPI Bus Timing Diagram
@TDK InvenSense Supp‘y Voltage, VDD 70 5v to +4v Supp‘y Voltage, vnmo 70.3v to +2 5v REGOUT 70.5v m 2v Input Vo‘tage Leve‘ (AUX7DA, ADD, FSVNC, INT, SCL, SDA) 70.5V to VDD + 0.5V Acce‘erat‘xcn (Any Ax‘s, unpcwered) zumug for 0.2 ms Operating Temperature Range 740T m +105”C Storage Temperature Range 740T m +125”C 2kv(HsMp; zuuwMM) JEDEC Class H 12p,125“c :100 mA
Document Number: DS-000189 Page 18 of 89
Revision: 1.3
3.7 ABSOLUTE MAXIMUM RATINGS
Stress above those listed as “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these conditions is not implied. Exposure to the absolute
maximum ratings conditions for extended periods may affect device reliability.
PARAMETER
RATING
Supply Voltage, VDD
-0.5V to +4V
Supply Voltage, VDDIO
-0.3V to +2.5V
REGOUT
-0.5V to 2V
Input Voltage Level (AUX_DA, AD0, FSYNC, INT, SCL, SDA)
-0.5V to VDD + 0.5V
Acceleration (Any Axis, unpowered)
20,000g for 0.2 ms
Operating Temperature Range
-40°C to +105°C
Storage Temperature Range
-40°C to +125°C
Electrostatic Discharge (ESD) Protection
2kV (HBM);
200V (MM)
Latch-up
JEDEC Class II (2),125°C
±100 mA
Table 9. Absolute Maximum Ratings
@TDK InvenSense 7 AUX7CL I c Master serial clock, for connecting to external sensors 8 VDDIO Digital we supply voltage 9 ADC / SDO | c slave Address LSB (Anal, SPI serial data output 1500) 10 REGOUT Regulatorfllter capacitor connection 11 FSVNC Frame svnchron‘lzaiion digital input. Connect to GND if unused 12 INTI Interrupt 1 13 VDD Power supply voltage 13 GND Power supply ground 19 RESV Reserved. Do not connect ZO RESV Reserved. Connect to GND. 21 AUX7DA | c master serial data, for connecting to external sensors 22 ncs cnip select lspl mode only) 23 SCL / scu< |="" c="" serial="" clock="" lscu;="" spl="" serial="" clock="" (saw="" 24="" sda/="" sdi="" ic="" serial="" data="" lsna);="" spl="" serial="" data="" input="" (le}="">
Document Number: DS-000189 Page 19 of 89
Revision: 1.3
4 APPLICATIONS INFORMATION
4.1 PIN OUT DIAGRAM AND SIGNAL DESCRIPTION
PIN NUMBER PIN NAME PIN DESCRIPTION
7
AUX_CL
I2C Master serial clock, for connecting to external sensors
8
VDDIO
Digital I/O supply voltage
9
AD0 / SDO
I
2
C Slave Address LSB (AD0); SPI serial data output (SDO)
10
REGOUT
Regulator filter capacitor connection
11
FSYNC
Frame synchronization digital input. Connect to GND if unused
12
INT1
Interrupt 1
13
VDD
Power supply voltage
18
GND
Power supply ground
19
RESV
Reserved. Do not connect.
20
RESV
Reserved. Connect to GND.
21
AUX_DA
I2C master serial data, for connecting to external sensors
22
nCS
Chip select (SPI mode only)
23
SCL / SCLK
I2C serial clock (SCL); SPI serial clock (SCLK)
24
SDA / SDI
I2C serial data (SDA); SPI serial data input (SDI)
1 – 6, 14 - 17 NC Do not connect
Table 10. Signal Descriptions
NOTE: Power up with SCL/SCLK and nCS pins held low is not a supported use case. In case this power up approach is used, software
reset is required using the PWR_MGMT_1 register, prior to initialization.
AUX_CL
VDDIO
SDO / AD0
REGOUT
FSYNC
INT1
GND
SCL / SCLK
nCS
RESV
VDD
SDA / SDI
NC
AUX_DA
RESV
NC
NC
NC
NC
NC
NC
NC
NC
NC
ICM-20948
1
2
3
4
5
613
18
17
16
15
14
7
8
9
10
11
12
24
23
22
21
20
19
Figure 3. Pin out Diagram for ICM-20948 3 mm x 3 mm x 1 mm QFN
@TDK InvenSense [ W W UUUUUU H }7>7 3—{ H W7 3—4
Document Number: DS-000189 Page 20 of 89
Revision: 1.3
4.2 TYPICAL OPERATING CIRCUIT
AUX_CL
VDDIO
SDO
/ AD0
REGOUT
FSYNC
INT1
GND
SCL / SCLK
nCS
RESV
VDD
SDA / SDI
NC
1.71 – 3.6VDC
C2, 0.1 µF
C3, 0.1 µ F
1.71 – 1.95VDC
SCL VDDIO
SDA
AUX_DA
AD0
C1, 0.1 µF
RESV
NC
NC
NC
NC
NC
NC
NC
NC
NC
ICM-20948
1
2
3
4
5
613
18
17
16
15
14
7
8
9
10
11
12
24
23
22
21
20
19
AUX_CL
VDDIO
SDO
/ AD0
REGOUT
FSYNC
INT1
GND
SCL / SCLK
nCS
RESV
VDD
SDA / SDI
NC
1.71 – 3.6VDC
C2, 0.1 µF
C3, 0.1 µ F
1.71 – 1.95VDC
SCLK
SDI
AUX_DA
SDO
C1, 0.1 µF
RESV
NC
NC
NC
NC
NC
NC
NC
NC
NC
ICM-20948
1
2
3
4
5
613
18
17
16
15
14
7
8
9
10
11
12
24
23
22
21
20
19
nCS
(a) (b)
Figure 4. ICM-20948 Application Schematic (a) I2C operation (b) SPI operation
Note that the INT pin should be connected to a GPIO pin on the system processor that is capable of waking the system
processor from suspend mode.
I2C lines are open drain and pullup resistors (e.g. 10 kΩ) are required.
4.3 BILL OF MATERIALS FOR EXTERNAL COMPONENTS
COMPONENT LABEL SPECIFICATION QUANTITY
Regulator Filter Capacitor C1 Ceramic, X7R, 0.1 µF ±10%, 2V 1
VDD Bypass Capacitor C2 Ceramic, X7R, 0.1 µF ±10%, 4V 1
VDDIO Bypass Capacitor C3 Ceramic, X7R, 0.1 µF ±10%, 4V 1
Table 11. Bill of Materials
4.4 EXPOSED DIE PAD PRECAUTIONS
InvenSense products have very low active and standby current consumption. The exposed die pad is not required for
heat sinking, and should not be soldered to the PCB. Failure to adhere to this rule can induce performance changes
due to package thermo-mechanical stress. There is no electrical connection between the pad and the CMOS.
@TDK InvenSense E E E E E E
Document Number: DS-000189 Page 21 of 89
Revision: 1.3
4.5 BLOCK DIAGRAM
ICM-20948
Charge
Pump
nCS
AD0 / SDO
SCL / SCLK
SDA / SDI
Temp Sensor ADC
ADC
Z Gyro
ADC
Y Gyro
Digital Motion
Processor
(DMP)
FSYNC
Slave I2C and
SPI Serial
Interface
Master I2C
Serial
Interface
Serial
Interface
Bypass
Mux
AUX_CL
AUX_DA
INT1
Interrupt
Status
Register
VDD
Bias & LDOs
GND REGOUT
Z Accel
Y Accel
X Accel ADC
ADC
ADC
ADC
X Gyro
Signal Conditioning
FIFO
User & Config
Registers
Sensor
Registers
Self
test
Self
test
Self
test
Self
test
Self
test
Self
test
X
Compass Y
Compass Z
Compass
ADC ADC ADC
Signal Conditioning
Figure 5. ICM-20948 Block Diagram
4.6 OVERVIEW
The ICM-20948 is comprised of the following key blocks and functions:
Three-axis MEMS rate gyroscope sensor with 16-bit ADCs and signal conditioning
Three-axis MEMS accelerometer sensor with 16-bit ADCs and signal conditioning
Three-axis MEMS magnetometer sensor with 16-bit ADCs and signal conditioning
Digital Motion Processor (DMP) engine
Primary I2C and SPI serial communications interfaces
Auxiliary I2C serial interface
Gyroscope, Accelerometer, and Magnetometer Self-Test
Clocking
Sensor Data Registers
FIFO
FSYNC
Interrupts
Digital-Output Temperature Sensor
Bias and LDOs
Charge Pump
Power Modes
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Document Number: DS-000189 Page 22 of 89
Revision: 1.3
4.7 THREE-AXIS MEMS GYROSCOPE WITH 16-BIT ADCS AND SIGNAL CONDITIONING
The ICM-20948 consists of three independent vibratory MEMS rate gyroscopes, which detect rotation about the X-, Y-,
and Z-Axes. When the gyros are rotated about any of the sense axes, the Coriolis Effect causes a vibration that is
detected by a capacitive pickoff. The resulting signal is amplified, demodulated, and filtered to produce a voltage that
is proportional to the angular rate. This voltage is digitized using individual on-chip 16-bit Analog-to-Digital Converters
(ADCs) to sample each axis. The full-scale range of the gyro sensors may be digitally programmed to ±250, ±500,
±1000, or ±2000 degrees per second (dps).
4.8 THREE-AXIS MEMS ACCELEROMETER WITH 16-BIT ADCS AND SIGNAL CONDITIONING
The ICM-20948’s 3-Axis accelerometer uses separate proof masses for each axis. Acceleration along a particular axis
induces displacement on the corresponding proof mass, and capacitive sensors detect the displacement differentially.
The ICM-20948’s architecture reduces the accelerometers’ susceptibility to fabrication variations as well as to thermal
drift. When the device is placed on a flat surface, it will measure 0g on the X- and Y-axes and +1g on the Z-axis. The
accelerometers’ scale factor is calibrated at the factory and is nominally independent of supply voltage. Each sensor
has a dedicated sigma-delta ADC for providing digital outputs. The full scale range of the digital output can be adjusted
to ±2g, ±4g, ±8g, or ±16g.
4.9 THREE-AXIS MEMS MAGNETOMETER WITH 16-BIT ADCS AND SIGNAL CONDITIONING
The 3-axis magnetometer uses highly sensitive Hall sensor technology. The magnetometer portion of the IC
incorporates magnetic sensors for detecting terrestrial magnetism in the X-, Y-, and Z-Axes, a sensor driving circuit, a
signal amplifier chain, and an arithmetic circuit for processing the signal from each sensor. Each ADC has a 16-bit
resolution and a full scale range of ±4900 µT.
4.10 DIGITAL MOTION PROCESSOR
The embedded Digital Motion Processor (DMP) within the ICM-20948 offloads computation of motion processing
algorithms from the host processor. The DMP acquires data from accelerometers, gyroscopes, and additional third
party sensors such as magnetometers, and processes the data. The resulting data can be read from the FIFO. The DMP
has access to the external pins, which can be used for generating interrupts.
The purpose of the DMP is to offload both timing requirements and processing power from the host processor.
Typically, motion processing algorithms should be run at a high rate, often around 200 Hz, in order to provide accurate
results with low latency. This is required even if the application updates at a much lower rate; for example, a low
power user interface may update as slowly as 5 Hz, but the motion processing should still run at 200 Hz. The DMP can
be used to minimize power, simplify timing, simplify the software architecture, and save valuable MIPS on the host
processor for use in applications.
4.11 PRIMARY I2C AND SPI SERIAL COMMUNICATIONS INTERFACES
The ICM-20948 communicates to a system processor using either a SPI or an I2C serial interface. The ICM-20948
always acts as a slave when communicating to the system processor. The LSB of the of the I2C slave address is set by
pin 1 (AD0).
ICM-20948 Solution Using I2C Interface
In Figure 6, the system processor is an I2C master to the ICM-20948. In addition, the ICM-20948 is an I2C master to the
optional external sensor. The ICM-20948 has limited capabilities as an I2C Master, and depends on the system
processor to manage the initial configuration of any auxiliary sensors. The ICM-20948 has an interface bypass
multiplexer, which connects the system processor I2C bus pins 23 and 24 (SCL and SDA) directly to the auxiliary sensor
I2C bus pins 7 and 21 (AUX_CL and AUX_DA).
@TDK InvenSense
Document Number: DS-000189 Page 23 of 89
Revision: 1.3
Once the auxiliary sensors have been configured by the system processor, the interface bypass multiplexer should be
disabled so that the ICM-20948 auxiliary I2C master can take control of the sensor I2C bus and gather data from the
auxiliary sensors.
ICM-20948
AD0
SCL
SDA/SDI
Digital
Motion
Processor
(DMP)
Sensor
Master I
2
C
Serial
Interface
AUX_CL
AUX_DA
Interrupt
Status
Register
VDD
Bias & LDOs
GND REGOUT
FIFO
User & Config
Registers
Sensor
Register
Factory
Calibration
Slave I
2
C
or SPI
Serial
Interface
External
Sensor
SCL
SDA
System
Processor
Interface
Bypass
Mux
SCL
SDA
VDD or GND
I
2
C Processor Bus: for reading all
sensor data from MPU and for
configuring external sensors (i.e.
compass in this example)
Interface bypass mux allows
direct configuration of
compass by system processor
Optional
Sensor I
2
C Bus: for
configuring and reading
from external sensors
INT1
Figure 6. ICM-20948 Solution Using I2C Interface
ICM-20948 Solution Using SPI Interface
In Figure 7, the system processor is an SPI master to the ICM-20948. Pins 9, 22, 23, and 24 are used to support the
SDO, nCS, SCLK, and SDI signals for SPI communications. Because these SPI pins are shared with the I2C slave pins (9,
23 and 24), the system processor cannot access the auxiliary I2C bus through the interface bypass multiplexer, which
connects the processor I2C interface pins to the sensor I2C interface pins. Since the ICM-20948 has limited capabilities
as an I2C Master, and depends on the system processor to manage the initial configuration of any auxiliary sensors,
another method must be used for programming the sensors on the auxiliary sensor I2C bus pins 7 and 21 (AUX_CL and
AUX_DA).
When using SPI communications between the ICM-20948 and the system processor, configuration of devices on the
auxiliary I2C sensor bus can be achieved by using I2C Slaves 0-4 to perform read and write transactions on any device
and register on the auxiliary I2C bus. The I2C Slave 4 interface can be used to perform only single byte read and write
transactions. Once the external sensors have been configured, the ICM-20948 can perform single or multi-byte reads
using the sensor I2C bus. The read results from the Slave 0-3 controllers can be written to the FIFO buffer as well as to
the external sensor registers.
@TDK InvenSense IZC Master Mode: Pass-Through Made: IZC Master Mode: Pass-Through Made:
Document Number: DS-000189 Page 24 of 89
Revision: 1.3
ICM-20948 SDO
SCLK
SDI
Digital
Motion
Processor
(DMP)
Sensor
Master I
2
C
Serial
Interface
Interrupt
Status
Register
FIFO
Config
Register
Sensor
Register
Factory
Calibration
nCS
Slave I
2
C
or SPI
Serial
Interface
System
Processor
Interface
Bypass
Mux
SDI
SCLK
SDO
nCS
Processor SPI Bus: for reading all
data from MPU and for configuring
MPU and external sensors
AUX_CL
AUX_DA
External
Sensor
SCL
SDA
Optional
I
2
C Master performs
read and write
transactions on
Sensor I
2
C bus.
Sensor I
2
C Bus: for
configuring and
reading data from
external sensors
VDD
Bias & LDOs
GND REGOUT
INT1
Figure 7. ICM-20948 Solution Using SPI Interface
4.12 AUXILIARY I2C SERIAL INTERFACE
The ICM-20948 has an auxiliary I2C bus for communicating to external sensors. This bus has two operating modes:
I2C Master Mode: The ICM-20948 acts as a master to any external sensors connected to the auxiliary I2C bus
Pass-Through Mode: The ICM-20948 directly connects the primary and auxiliary I2C buses together, allowing
the system processor to directly communicate with any external sensors.
Auxiliary I2C Bus Modes of Operation:
I2C Master Mode: Allows the ICM-20948 to directly access the data registers of external sensors. In this
mode, the ICM-20948 directly obtains data from auxiliary sensors without intervention from the system
applications processor. The I2C Master can be configured to read up to 24 bytes from up to 4 auxiliary
sensors. A fifth sensor can be configured to work single byte read/write mode.
Pass-Through Mode: Allows an external system processor to act as master and directly communicate to the
external sensors connected to the auxiliary I2C bus pins (AUX_DA and AUX_CL). In this mode, the auxiliary I2C
bus control logic of the ICM-20948 is disabled, and the auxiliary I2C pins AUX_CL and AUX_DA (pins 7 and 21)
are connected to the main I2C bus (Pins 23 and 24) through analog switches internally. Pass-Through mode is
useful for configuring the external sensors.
4.13 SELF-TEST
Self-test allows for the testing of the mechanical and electrical portions of the sensors. The self-test for each
measurement axis can be activated by means of the gyroscope and accelerometer self-test registers.
When the self-test is activated, the electronics cause the sensors to be actuated and produce an output signal. The
output signal is used to observe the self-test response.
The self-test response is defined as follows:
SELF-TEST RESPONSE = SENSOR OUTPUT WITH SELF-TEST ENABLED SENSOR OUTPUT WITHOUT SELF-TEST ENABLED
@TDK InvenSense
Document Number: DS-000189 Page 25 of 89
Revision: 1.3
The self-test response for each gyroscope axis is defined in the gyroscope specification table, while that for each
accelerometer axis is defined in the accelerometer specification table.
When the value of the self-test response is within the specified min/max limits, the part has passed self-test. When
the self-test response exceeds the min/max values, the part is deemed to have failed self-test. It is recommended to
use InvenSense MotionApps software for executing self-test.
4.14 CLOCKING
The internal system clock sources include: (1) an internal relaxation oscillator, and (2) a PLL with MEMS gyroscope
oscillator as the reference clock. With the recommended clock selection setting (CLKSEL = 1), the best clock source for
optimum sensor performance and power consumption will be automatically selected based on the power mode.
Specifically, the internal relaxation oscillator will be selected when operating in accelerometer only mode, while the
PLL will be selected whenever gyroscope is on, which includes gyroscope and 6-axis modes.
As clock accuracy is critical to the preciseness of distance and angle calculations performed by DMP, it should be noted
that the internal relaxation oscillator and PLL show different performances in some aspects. The internal relaxation
oscillator is trimmed to have a consistent operating frequency at room temperature, while the PLL clock frequency
varies from part to part. The PLL frequency deviation from the nominal value in percentage is captured in register
TIMEBASE_CORRECTION_PLL (detailed in section 12.5), and users can factor it in during distance and angle
calculations to not sacrifice accuracy. Other than that, PLL has better frequency stability and lower frequency variation
over temperature than the internal relaxation oscillator.
4.15 SENSOR DATA REGISTERS
The sensor data registers contain the latest gyro, accelerometer, auxiliary sensor, and temperature measurement
data. They are read-only registers, and are accessed via the serial interface. Data from these registers may be read
anytime.
4.16 FIFO
The ICM-20948 contains a FIFO of size 512 bytes (FIFO size will vary depending on DMP feature-set) that is accessible
via the Serial Interface. The FIFO configuration register determines which data is written into the FIFO. Possible
choices include gyro data, accelerometer data, temperature readings, auxiliary sensor readings, and FSYNC input.
A FIFO counter keeps track of how many bytes of valid data are contained in the FIFO. The FIFO register supports burst
reads. The interrupt function may be used to determine when new data is available.
For further information regarding the FIFO, please refer to the Section 7.
4.17 FSYNC
The FSYNC pin can be used from an external interrupt source to wake up the device from sleep. It is particularly useful
in EIS applications to synchronize the gyroscope ODR with external inputs from an imaging sensor. Connecting the
VSYNC or HSYNC pin of the image sensor subsystem to FSYNC on ICM-20948 allows timing synchronization between
the two otherwise unconnected subsystems.
An FSYNC_ODR delay time register is used to capture the delay between an FSYNC pulse and the very next gyroscope
data ready pulse.
4.18 INTERRUPTS
Interrupt functionality is configured via the Interrupt Configuration register. Items that are configurable include the
INT pin configuration, the interrupt latching and clearing method, and triggers for the interrupt. Section 5 provides a
summary of interrupt sources. The interrupt status can be read from the Interrupt Status register.
For further information regarding interrupts, please refer to Section 7.
@TDK InvenSense 1 Sleep Mode Off Off Off Off 2 LowVPower Accelerometer Mode Off Dulerycled Off On or Off 3 LowVNmse Accelerometer Mode Off On Off On or Off 4 Gyroscope Mode on Off Off On or Off 5 Magnetomefer Mode Off Off On On or Off 6 Accel + Gyro Mode on On Off On or Off 7 Accel + Magnetomefer Mode Off On On On or Off 8 QiAxls Mode on On On On or Off
Document Number: DS-000189 Page 26 of 89
Revision: 1.3
4.19 DIGITAL-OUTPUT TEMPERATURE SENSOR
An on-chip temperature sensor and ADC are used to measure the ICM-20948 die temperature. The readings from the
ADC can be read from the FIFO or the Sensor Data registers.
4.20 BIAS AND LDOS
The bias and LDO section generates the internal supply and the reference voltages and currents required by the ICM-
20948. Its two inputs are an unregulated VDD and a VDDIO logic reference supply voltage. The LDO output is bypassed
by a capacitor at REGOUT. For further details on the capacitor, please refer to the Bill of Materials for External
Components.
4.21 CHARGE PUMP
An on-chip charge pump generates the high voltage required for the MEMS oscillators.
4.22 POWER MODES
Table 12 lists the user-accessible power modes for ICM-20948.
MODE
NAME
GYRO
ACCEL
MAGNETOMETER
DMP
1
Sleep Mode
Off
Off
Off
Off
2
Low-Power Accelerometer Mode
Off
Duty-Cycled
Off
On or Off
3
Low-Noise Accelerometer Mode
Off
On
Off
On or Off
4
Gyroscope Mode
On
Off
Off
On or Off
5
Magnetometer Mode
Off
Off
On
On or Off
6
Accel + Gyro Mode
On
On
Off
On or Off
7
Accel + Magnetometer Mode
Off
On
On
On or Off
8
9-Axis Mode
On
On
On
On or Off
Table 12. Power Modes for ICM-20948
@TDK InvenSense DMP Interrupt Wake on Motion Interrupt PLL RDV Interrupt IZC Master Interrupt
Document Number: DS-000189 Page 27 of 89
Revision: 1.3
5 PROGRAMMABLE INTERRUPTS
The ICM-20948 has a programmable interrupt system which can generate an interrupt signal on the INT pin. Status
flags indicate the source of an interrupt. Interrupt sources may be enabled and disabled individually. Table 13 lists the
interrupt sources.
INTERRUPT SOURCE
DMP Interrupt
Wake on Motion Interrupt
PLL RDY Interrupt
I2C Master Interrupt
Raw Data Ready Interrupt
FIFO Overflow Interrupt
FIFO Watermark Interrupt
Table 13. Interrupt Sources
@TDK InvenSense 23 SCL/ SCLK \ c seria‘ dock 15cm; sm serm clock 15cm 24 SDA / SDI \ c seria‘ data (sDAp, sm serm data mpm 15m)
Document Number: DS-000189 Page 28 of 89
Revision: 1.3
6 DIGITAL INTERFACE
6.1 I2C AND SPI SERIAL INTERFACES
The internal registers and memory of the ICM-20948 can be accessed using either I2C at 400 kHz or SPI at 7 MHz. SPI
operates in four-wire mode.
PIN NUMBER PIN NAME PIN DESCRIPTION
9 AD0 / SDO I2C Slave Address LSB (AD0); SPI serial data output (SDO)
22 nCS Chip select (SPI mode only)
23
SCL / SCLK
I
2
C serial clock (SCL); SPI serial clock (SCLK)
24
SDA / SDI
I2C serial data (SDA); SPI serial data input (SDI)
Table 14. Serial Interface
NOTE: To prevent switching into I2C mode when using SPI, the I2C interface should be disabled by setting the I2C_IF_DIS configuration bit. Setting
this bit should be performed immediately after waiting for the time specified by the “Start-Up Time for Register Read/Write” in Section 6.3.
For further information regarding the I2C_IF_DIS bit, please refer to Section 7.
6.2 I2C INTERFACE
I2C is a two-wire interface comprised of the signals serial data (SDA) and serial clock (SCL). In general, the lines are
open-drain and bi-directional. In a generalized I2C interface implementation, attached devices can be a master or a
slave. The master device puts the slave address on the bus, and the slave device with the matching address
acknowledges the master.
The ICM-20948 always operates as a slave device when communicating to the system processor, which thus acts as
the master. SDA and SCL lines typically need pull-up resistors to VDD. The maximum bus speed is 400 kHz.
The slave address of the ICM-20948 is b110100X which is 7 bits long. The LSB bit of the 7-bit address is determined by
the logic level on pin AD0. This allows two ICM-20948s to be connected to the same I2C bus. When used in this
configuration, the address of the one of the devices should be b1101000 (pin AD0 is logic low) and the address of the
other should be b1101001 (pin AD0 is logic high).
6.3 I2C COMMUNICATIONS PROTOCOL
START (S) and STOP (P) Conditions
Communication on the I2C bus starts when the master puts the START condition (S) on the bus, which is defined as a
HIGH-to-LOW transition of the SDA line while SCL line is HIGH (see figure below). The bus is considered to be busy until
the master puts a STOP condition (P) on the bus, which is defined as a LOW to HIGH transition on the SDA line while
SCL is HIGH (see figure below).
Additionally, the bus remains busy if a repeated START (Sr) is generated instead of a STOP condition.
SDA
SCL
S
START condition STOP condition
P
Figure 8. START and STOP Conditions
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Document Number: DS-000189 Page 29 of 89
Revision: 1.3
Data Format / Acknowledge
I2C data bytes are defined to be 8-bits long. There is no restriction to the number of bytes transmitted per data
transfer. Each byte transferred must be followed by an acknowledge (ACK) signal. The clock for the acknowledge
signal is generated by the master, while the receiver generates the actual acknowledge signal by pulling down SDA and
holding it low during the HIGH portion of the acknowledge clock pulse.
If a slave is busy and cannot transmit or receive another byte of data until some other task has been performed, it can
hold SCL LOW, thus forcing the master into a wait state. Normal data transfer resumes when the slave is ready, and
releases the clock line (refer to the following figure).
DATA OUTPUT BY
TRANSMITTER (SDA)
DATA OUTPUT BY
RECEIVER (SDA)
SCL FROM
MASTER
START
condition
clock pulse for
acknowledgement
acknowledge
not acknowledge
1 2 8 9
Figure 9. Acknowledge on the I2C Bus
Communications
After beginning communications with the START condition (S), the master sends a 7-bit slave address followed by an
8th bit, the read/write bit. The read/write bit indicates whether the master is receiving data from or is writing to the
slave device. Then, the master releases the SDA line and waits for the acknowledge signal (ACK) from the slave device.
Each byte transferred must be followed by an acknowledge bit. To acknowledge, the slave device pulls the SDA line
LOW and keeps it LOW for the high period of the SCL line. Data transmission is always terminated by the master with
a STOP condition (P), thus freeing the communications line. However, the master can generate a repeated START
condition (Sr), and address another slave without first generating a STOP condition (P). A LOW to HIGH transition on
the SDA line while SCL is HIGH defines the stop condition. All SDA changes should take place when SCL is low, with the
exception of start and stop conditions.
SDA
START
condition
SCL
ADDRESS R/W ACK DATA ACK DATA ACK STOP
condition
S P
1 – 7 8 9 1 – 7 8 9 1 – 7 8 9
Figure 10. Complete I2C Data Transfer
@TDK InvenSense 5 sun Condition: SDA goes from high to iow while 5a is high AD Sieve |2C address w Write b‘it (a) R Read bit in ACK Acknowiedge SDA line is low whiie the SCL hne is high at the s h deck cycle NACK NobAckncw‘edge: SDA line stays high at the s h dock cycie RA ICMVZUQAS ihiemal regisier address DATA Transmii or received data P Step condition: SDA gomg from iow m high while SCL is high
Document Number: DS-000189 Page 30 of 89
Revision: 1.3
To write the internal ICM-20948 registers, the master transmits the start condition (S), followed by the I2C address and
the write bit (0). At the 9th clock cycle (when the clock is high), the ICM-20948 acknowledges the transfer. Then the
master puts the register address (RA) on the bus. After the ICM-20948 acknowledges the reception of the register
address, the master puts the register data onto the bus. This is followed by the ACK signal, and data transfer may be
concluded by the stop condition (P). To write multiple bytes after the last ACK signal, the master can continue
outputting data rather than transmitting a stop signal. In this case, the ICM-20948 automatically increments the
register address and loads the data to the appropriate register. The following figures show single and two-byte write
sequences.
Single-Byte Write Sequence
Burst Write Sequence
To read the internal ICM-20948 registers, the master sends a start condition, followed by the I2C address and a write
bit, and then the register address that is going to be read. Upon receiving the ACK signal from the ICM-20948, the
master transmits a start signal followed by the slave address and read bit. As a result, the ICM-20948 sends an ACK
signal and the data. The communication ends with a not acknowledge (NACK) signal and a stop bit from master. The
NACK condition is defined such that the SDA line remains high at the 9th clock cycle. The following figures show single
and two-byte read sequences.
Single-Byte Read Sequence
Burst Read Sequence
6.4 I2C TERMS
SIGNAL DESCRIPTION
S
Start Condition: SDA goes from high to low while SCL is high
AD
Slave I
2
C address
W
Write bit (0)
R
Read bit (1)
ACK
Acknowledge: SDA line is low while the SCL line is high at the 9th clock cycle
NACK
Not-Acknowledge: SDA line stays high at the 9
th
clock cycle
RA
ICM-20948 internal register address
DATA
Transmit or received data
P
Stop condition: SDA going from low to high while SCL is high
Table 15. I2C Terms
Master S AD+W RA DATA P
Slave ACK ACK ACK
Master S AD+W RA DATA DATA P
Slave ACK ACK ACK ACK
Master S AD+W RA S AD+R NACK P
Slave ACK ACK ACK DATA
Master S AD+W RA S AD+R ACK NACK P
Slave ACK ACK ACK DATA DATA
@TDK InvenSense R/W A6 A5 A4 A3 AZ A1 A0 D7 D6 D5 D4 D3 D2 D1 DD
Document Number: DS-000189 Page 31 of 89
Revision: 1.3
6.5 SPI INTERFACE
SPI is a 4-wire synchronous serial interface that uses two control lines and two data lines. The ICM-20948 always
operates as a Slave device during standard Master-Slave SPI operation.
With respect to the Master, the Serial Clock output (SCLK), the Serial Data Output (SDO) and the Serial Data Input (SDI)
are shared among the Slave devices. Each SPI slave device requires its own Chip Select (CS) line from the master.
CS goes low (active) at the start of transmission and goes back high (inactive) at the end. Only one CS line is active at a
time, ensuring that only one slave is selected at any given time. The CS lines of the non-selected slave devices are held
high, causing their SDO lines to remain in a high-impedance (high-z) state so that they do not interfere with any active
devices.
SPI Operational Features
1. Data is delivered MSB first and LSB last
2. Data is latched on the rising edge of SCLK
3. Data should be transitioned on the falling edge of SCLK
4. The maximum frequency of SCLK is 7MHz
5. SPI read and write operations are completed in 16 or more clock cycles (two or more bytes). The first byte
contains the SPI Address, and the following byte(s) contain(s) the SPI data. The first bit of the first byte
contains the Read/Write bit and indicates the Read (1) or Write (0) operation. The following 7 bits contain the
Register Address. In cases of multiple-byte Read/Writes, data is two or more bytes:
SPI Address format
MSB
LSB
R/W
A6
A5
A4
A3
A2
A1
A0
SPI Data format
MSB LSB
D7
D6
D5
D4
D3
D2
D1
D0
6. Supports Single or Burst Read/Writes.
SPI Master SPI Slave 1
SPI Slave 2
/CS1
/CS2
SCLK
SDI
SDO
/CS
SCLK
SDI
SDO
/CS
Figure 11. Typical SPI Master / Slave Configuration
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Document Number: DS-000189 Page 32 of 89
Revision: 1.3
7 REGISTER MAP FOR GYROSCOPE AND ACCELEROMETER
The following table lists the register map for the ICM-20948, for user banks 0, 1, 2, 3.
7.1 USER BANK 0 REGISTER MAP
ADDR
(HEX)
ADDR
(DEC.) REGISTER NAME SERIAL
I/F BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
00
0
WHO_AM_I
R
WHO_AM_I[7:0]
03
3
USER_CTRL
R/W
DMP_EN
FIFO_EN
I2C_MST_EN
I2C_IF_DIS
DMP_RST
SRAM_RST
I2C_MST_RST
-
05 5 LP_CONFIG R/W
I2C_MST_CY
CLE
ACCEL_CYCLE GYRO_CYCLE -
06 6 PWR_MGMT_1 R/W
DEVICE_RESE
T
SLEEP LP_EN - TEMP_DIS CLKSEL[2:0]
07
7
PWR_MGMT_2
R/W
-
DISABLE_ACCEL
DISABLE_GYRO
0F 15 INT_PIN_CFG R/W INT1_ACTL INT1_OPEN
INT1_LATCH_
INT_EN
INT_ANYRD_
2CLEAR
ACTL_FSYNC
FSYNC_INT_
MODE_EN
BYPASS_EN -
10 16 INT_ENABLE R/W
REG_WOF_E
N
-
WOM_INT_E
N
PLL_RDY_EN
DMP_INT1_E
N
I2C_MST_INT
_EN
11 17 INT_ENABLE_1 R/W -
RAW_DATA_
0_RDY_EN
12
18
INT_ENABLE_2
R/W
-
FIFO_OVERFLOW_EN[4:0]
13
19
INT_ENABLE_3
R/W
-
FIFO_WM_EN[4:0]
17 23 I2C_MST_STATUS R/C
PASS_THROU
GH
I2C_SLV4_DO
NE
I2C_LOST_AR
B
I2C_SLV4_NA
CK
I2C_SLV3_NA
CK
I2C_SLV2_NA
CK
I2C_SLV1_NA
CK
I2C_SLV0_NA
CK
19
25
INT_STATUS
R/C
-
WOM_INT
PLL_RDY_INT
DMP_INT1
I2C_MST_INT
1A 26 INT_STATUS_1 R/C -
RAW_DATA_
0_RDY_INT
1B
27
INT_STATUS_2
R/C
-
FIFO_OVERFLOW_INT[4:0]
1C
28
INT_STATUS_3
R/C
-
FIFO_WM_INT[4:0]
28
40
DELAY_TIMEH
R
DELAY_TIMEH[7:0]
29
41
DELAY_TIMEL
R
DELAY_TIMEL[7:0]
2D
45
ACCEL_XOUT_H
R
ACCEL_XOUT_H[7:0]
2E
46
ACCEL_XOUT_L
R
ACCEL_XOUT_L[7:0]
2F
47
ACCEL_YOUT_H
R
ACCEL_YOUT_H[7:0]
30
48
ACCEL_YOUT_L
R
ACCEL_YOUT_L[7:0]
31
49
ACCEL_ZOUT_H
R
ACCEL_ZOUT_H[7:0]
32
50
ACCEL_ZOUT_L
R
ACCEL_ZOUT_L[7:0]
33
51
GYRO_XOUT_H
R
GYRO_XOUT_H[7:0]
34
52
GYRO_XOUT_L
R
GYRO_XOUT_L[7:0]
35
53
GYRO_YOUT_H
R
GYRO_YOUT_H[7:0]
36
54
GYRO_YOUT_L
R
GYRO_YOUT_L[7:0]
37
55
GYRO_ZOUT_H
R
GYRO_ZOUT_H[7:0]
38
56
GYRO_ZOUT_L
R
GYRO_ZOUT_L[7:0]
39
57
TEMP_OUT_H
R
TEMP_OUT_H[7:0]
3A
58
TEMP_OUT_L
R
TEMP_OUT_L[7:0]
3B
59
EXT_SLV_SENS_DATA_00
R
EXT_SLV_SENS_DATA_00[7:0]
3C
60
EXT_SLV_SENS_DATA_01
R
EXT_SLV_SENS_DATA_01[7:0]
3D
61
EXT_SLV_SENS_DATA_02
R
EXT_SLV_SENS_DATA_02[7:0]
3E
62
EXT_SLV_SENS_DATA_03
R
EXT_SLV_SENS_DATA_03[7:0]
3F
63
EXT_SLV_SENS_DATA_04
R
EXT_SLV_SENS_DATA_04[7:0]
40
64
EXT_SLV_SENS_DATA_05
R
EXT_SLV_SENS_DATA_05[7:0]
41
65
EXT_SLV_SENS_DATA_06
R
EXT_SLV_SENS_DATA_06[7:0]
42
66
EXT_SLV_SENS_DATA_07
R
EXT_SLV_SENS_DATA_07[7:0]
43
67
EXT_SLV_SENS_DATA_08
R
EXT_SLV_SENS_DATA_08[7:0]
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Document Number: DS-000189 Page 33 of 89
Revision: 1.3
ADDR
(HEX)
ADDR
(DEC.) REGISTER NAME SERIAL
I/F BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
44
68
EXT_SLV_SENS_DATA_09
R
EXT_SLV_SENS_DATA_09[7:0]
45
69
EXT_SLV_SENS_DATA_10
R
EXT_SLV_SENS_DATA_10[7:0]
46
70
EXT_SLV_SENS_DATA_11
R
EXT_SLV_SENS_DATA_11[7:0]
47
71
EXT_SLV_SENS_DATA_12
R
EXT_SLV_SENS_DATA_12[7:0]
48
72
EXT_SLV_SENS_DATA_13
R
EXT_SLV_SENS_DATA_13[7:0]
49
73
EXT_SLV_SENS_DATA_14
R
EXT_SLV_SENS_DATA_14[7:0]
4A
74
EXT_SLV_SENS_DATA_15
R
EXT_SLV_SENS_DATA_15[7:0]
4B
75
EXT_SLV_SENS_DATA_16
R
EXT_SLV_SENS_DATA_16[7:0]
4C
76
EXT_SLV_SENS_DATA_17
R
EXT_SLV_SENS_DATA_17[7:0]
4D
77
EXT_SLV_SENS_DATA_18
R
EXT_SLV_SENS_DATA_18[7:0]
4E
78
EXT_SLV_SENS_DATA_19
R
EXT_SLV_SENS_DATA_19[7:0]
4F
79
EXT_SLV_SENS_DATA_20
R
EXT_SLV_SENS_DATA_20[7:0]
50
80
EXT_SLV_SENS_DATA_21
R
EXT_SLV_SENS_DATA_21[7:0]
51
81
EXT_SLV_SENS_DATA_22
R
EXT_SLV_SENS_DATA_22[7:0]
52
82
EXT_SLV_SENS_DATA_23
R
EXT_SLV_SENS_DATA_23[7:0]
66 102 FIFO_EN_1 R/W -
SLV_3_FIFO_
EN
SLV_2_FIFO_
EN
SLV_1_FIFO_
EN
SLV_0_FIFO_
EN
67 103 FIFO_EN_2 R/W -
ACCEL_FIFO_
EN
GYRO_Z_FIF
O_EN
GYRO_Y_FIF
O_EN
GYRO_X_FIF
O_EN
TEMP_FIFO_
EN
68
104
FIFO_RST
R/W
-
FIFO_RESET[4:0]
69
105
FIFO_MODE
R/W
-
FIFO_MODE[4:0]
70
112
FIFO_COUNTH
R
-
FIFO_CNT[12:8]
71
113
FIFO_COUNTL
R
FIFO_CNT[7:0]
72
114
FIFO_R_W
R/W
FIFO_R_W[7:0]
74 116 DATA_RDY_STATUS R/C
WOF_STATU
S
- RAW_DATA_RDY[3:0]
76
118
FIFO_CFG
R/W
-
FIFO_CFG
7F
127
REG_BANK_SEL
R/W
-
USER_BANK[1:0]
-
7.2 USER BANK 1 REGISTER MAP
Addr
(Hex)
Addr
(Dec.) Register Name
Serial
I/F Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
02
2
SELF_TEST_X_GYRO
R/W
XG_ST_DATA[7:0]
03
3
SELF_TEST_Y_GYRO
R/W
YG_ST_DATA[7:0]
04
4
SELF_TEST_Z_GYRO
R/W
ZG_ST_DATA[7:0]
0E
14
SELF_TEST_X_ACCEL
R/W
XA_ST_DATA[7:0]
0F
15
SELF_TEST_Y_ACCEL
R/W
YA_ST_DATA[7:0]
10
16
SELF_TEST_Z_ACCEL
R/W
ZA_ST_DATA[7:0]
14
20
XA_OFFS_H
R/W
XA_OFFS[14:7]
15
21
XA_OFFS_L
R/W
XA_OFFS[6:0]
-
17
23
YA_OFFS_H
R/W
YA_OFFS[14:7]
18
24
YA_OFFS_L
R/W
YA_OFFS[6:0]
-
1A
26
ZA_OFFS_H
R/W
ZA_OFFS[14:7]
1B
27
ZA_OFFS_L
R/W
ZA_OFFS[6:0]
-
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Document Number: DS-000189 Page 34 of 89
Revision: 1.3
Addr
(Hex)
Addr
(Dec.) Register Name
Serial
I/F Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
28 40
TIMEBASE_CORRECTIO
N_PLL R/W TBC_PLL[7:0]
7F
127
REG_BANK_SEL
R/W
-
USER_BANK[1:0]
-
7.3 USER BANK 2 REGISTER MAP
ADDR
(HEX)
ADDR
(DEC.) REGISTER NAME SERIAL
I/F BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
00
0
GYRO_SMPLRT_DIV
R/W
GYRO_SMPLRT_DIV[7:0]
01 1 GYRO_CONFIG_1 R/W - GYRO_DLPFCFG[2:0] GYRO_FS_SEL[1:0]
GYRO_FCHOI
CE
02
2
GYRO_CONFIG_2
R/W
-
XGYRO_CTEN
YGYRO_CTEN
ZGYRO_CTEN
GYRO_AVGCFG[2:0]
03
3
XG_OFFS_USRH
R/W
X_OFFS_USER[15:8]
04
4
XG_OFFS_USRL
R/W
X_OFFS_USER[7:0]
05
5
YG_OFFS_USRH
R/W
Y_OFFS_USER[15:8]
06
6
YG_OFFS_USRL
R/W
Y_OFFS_USER[7:0]
07
7
ZG_OFFS_USRH
R/W
Z_OFFS_USER[15:8]
08
8
ZG_OFFS_USRL
R/W
Z_OFFS_USER[7:0]
09 9 ODR_ALIGN_EN R/W -
ODR_ALIGN_
EN
10
16
ACCEL_SMPLRT_DIV_1
R/W
-
ACCEL_SMPLRT_DIV[11:8]
11
17
ACCEL_SMPLRT_DIV_2
R/W
ACCEL_SMPLRT_DIV[7:0]
12 18 ACCEL_INTEL_CTRL R/W -
ACCEL_INTEL
_EN
ACCEL_INTEL
_MODE_INT
13
19
ACCEL_WOM_THR
R/W
WOM_THRESHOLD[7:0]
14 20 ACCEL_CONFIG R/W - ACCEL_DLPFCFG[2:0] ACCEL_FS_SEL[1:0]
ACCEL_FCHOI
CE
15 21 ACCEL_CONFIG_2 R/W -
AX_ST_EN_R
EG
AY_ST_EN_R
EG
AZ_ST_EN_R
EG
DEC3_CFG[1:0]
52 82 FSYNC_CONFIG R/W
DELAY_TIME
_EN
-
WOF_DEGLIT
CH_EN
WOF_EDGE_I
NT
EXT_SYNC_SET[3:0]
53
83
TEMP_CONFIG
R/W
-
TEMP_DLPFCFG[2:0]
54 84 MOD_CTRL_USR R/W -
REG_LP_DMP
_EN
7F
127
REG_BANK_SEL
R/W
-
USER_BANK[1:0]
-
7.4 USER BANK 3 REGISTER MAP
ADDR
(HEX)
ADDR
(DEC.) REGISTER NAME SERIAL
I/F BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
00
0
I2C_MST_ODR_CONFIG
R/W
-
I2C_MST_ODR_CONFIG[3:0]
01 1 I2C_MST_CTRL R/W
MULT_MST_
EN
-
I2C_MST_P_
NSR
I2C_MST_CLK[3:0]
02 2 I2C_MST_DELAY_CTRL R/W
DELAY_ES_S
HADOW
-
I2C_SLV4_DE
LAY_EN
I2C_SLV3_DE
LAY_EN
I2C_SLV2_DE
LAY_EN
I2C_SLV1_DE
LAY_EN
I2C_SLV0_DE
LAY_EN
03 3 I2C_SLV0_ADDR R/W
I2C_SLV0_RN
W
I2C_ID_0[6:0]
04
4
I2C_SLV0_REG
R/W
I2C_SLV0_REG[7:0]
05 5 I2C_SLV0_CTRL R/W I2C_SLV0_EN
I2C_SLV0_BY
TE_SW
I2C_SLV0_RE
G_DIS
I2C_SLV0_GR
P
I2C_SLV0_LENG[3:0]
06
6
I2C_SLV0_DO
R/W
I2C_SLV0_DO[7:0]
07 7 I2C_SLV1_ADDR R/W
I2C_SLV1_RN
W
I2C_ID_1[6:0]
08
8
I2C_SLV1_REG
R/W
I2C_SLV1_REG[7:0]
09 9 I2C_SLV1_CTRL R/W I2C_SLV1_EN
I2C_SLV1_BY
TE_SW
I2C_SLV1_RE
G_DIS
I2C_SLV1_GR
P
I2C_SLV1_LENG[3:0]
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Document Number: DS-000189 Page 35 of 89
Revision: 1.3
ADDR
(HEX)
ADDR
(DEC.) REGISTER NAME SERIAL
I/F BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
0A
10
I2C_SLV1_DO
R/W
I2C_SLV1_DO[7:0]
0B 11 I2C_SLV2_ADDR R/W
I2C_SLV2_RN
W
I2C_ID_2[6:0]
0C
12
I2C_SLV2_REG
R/W
I2C_SLV2_REG[7:0]
0D 13 I2C_SLV2_CTRL R/W I2C_SLV2_EN
I2C_SLV2_BY
TE_SW
I2C_SLV2_RE
G_DIS
I2C_SLV2_GR
P
I2C_SLV2_LENG[3:0]
0E
14
I2C_SLV2_DO
R/W
I2C_SLV2_DO[7:0]
0F 15 I2C_SLV3_ADDR R/W
I2C_SLV3_RN
W
I2C_ID_3[6:0]
10
16
I2C_SLV3_REG
R/W
I2C_SLV3_REG[7:0]
11 17 I2C_SLV3_CTRL R/W I2C_SLV3_EN
I2C_SLV3_BY
TE_SW
I2C_SLV3_RE
G_DIS
I2C_SLV3_GR
P
I2C_SLV3_LENG[3:0]
12
18
I2C_SLV3_DO
R/W
I2C_SLV3_DO[7:0]
13 19 I2C_SLV4_ADDR R/W
I2C_SLV4_RN
W
I2C_ID_4[6:0]
14
20
I2C_SLV4_REG
R/W
I2C_SLV4_REG[7:0]
15 21 I2C_SLV4_CTRL R/W I2C_SLV4_EN
I2C_SLV4_BY
TE_SW
I2C_SLV4_RE
G_DIS
I2C_SLV4_DLY[4:0]
16
22
I2C_SLV4_DO
R/W
I2C_SLV4_DO[7:0]
17
23
I2C_SLV4_DI
R
I2C_SL