74CBTLV3245 Datasheet by NXP USA Inc.

View All Related Products | Download PDF Datasheet
nexpefla http://www.nxD.com http://www.DhiliDs.com/ httD://www.semiconductors.philips.com/ htt : www.nex eria.com salesaddressesQneer com
Important notice
Dear Customer,
On 7 February 2017 the former NXP Standard Product business became a new company with the
tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS
semiconductors with its focus on the automotive, industrial, computing, consumer and wearable
application markets
In data sheets and application notes which still contain NXP or Philips Semiconductors references, use
the references to Nexperia, as shown below.
Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/,
use http://www.nexperia.com
Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use
salesaddresses@nexperia.com (email)
Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on
the version, as shown below:
- © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights
reserved
Should be replaced with:
- © Nexperia B.V. (year). All rights reserved.
If you have any questions related to the data sheet, please contact our nearest sales office via e-mail
or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and
understanding,
Kind regards,
Team Nexperia
1. General description
The 74CBTLV3245 is an 8-pole, single-throw bus switch. The device features a single
output enable input (OE) that controls eight switch channels. The switches are disabled
when OE is HIGH. Schmitt-trigger action at control inputs makes the circuit tolerant of
slower input rise and fall times. This device is fully specified for partial power-down
applications using IOFF. The IOFF circuitry disables the output, preventing the damaging
backflow current through the device when it is powered down.
2. Features and benefits
Supply voltage range from 2.3 V to 3.6 V
High noise immunity
Complies with JEDEC standard:
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM AEC-Q100-011 revision B exceeds 1000 V
5 switch connection between two ports
Rail to rail switching on data I/O ports
CMOS low power consumption
Latch-up performance exceeds 250 mA per JESD78B Class I level A
IOFF circuitry provides partial Power-down mode operation
Multiple package options
Specified from 40 Cto+85C and 40 Cto+125C
74CBTLV3245
8-bit bus switch with output enable
Rev. 3 — 11 November 2016 Product data sheet
SSOPZO,
74CBTLV3245 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 3 — 11 November 2016 2 of 19
NXP Semiconductors 74CBTLV3245
8-bit bus switch with output enable
3. Ordering information
[1] Also known as QSOP20 package
4. Functional diagram
Table 1. Ordering information
Type number Package
Temperature
range Name Description Version
74CBTLV3245DS 40 C to +125 C SSOP20[1] plastic shrink small outline package; 20 leads; body
width 3.9 mm; lead pitch 0.635 mm SOT724-1
74CBTLV3245PW 40 C to +125 C TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm SOT360-1
74CBTLV3245BQ 40 C to +125 C DHVQFN20 plastic dual-in-line compatible thermal enhanced very
thin quad flat package; no leads; 20 terminals; body
2.5 4.5 0.85 mm
SOT764-1
Fig 1. Logic symbol
DDQ


%
$
2(

%
$

%
$

%
$

%
$

%
$

%
$

%
$
Fig 2. Logic diagram (one switch)
DDQ
2(
Q$ Q%
7 333333333: O EEEEEEEEEE W188n325 7 3333333333 O EEEEEEEEEE 0915311325 7 agaaaqag ® @ U @ EEEEEDEE Transparem mp mew
74CBTLV3245 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 3 — 11 November 2016 3 of 19
NXP Semiconductors 74CBTLV3245
8-bit bus switch with output enable
5. Pinning information
5.1 Pinning
Fig 3. Pin configuration for TSSOP20 (SOT360-1) Fig 4. Pin configuration for SSOP20 (SOT724-1)
&%7/9
QF 9&&
$ 2(
$ %
$ %
$ %
$ %
$ %
$ %
$ %
*1' %
DDQ











&%7/9
QF 9&&
$ 2(
$ %
$ %
$ %
$ %
$ %
$ %
$ %
*1' %
DDQ











(1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or
mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to
GND.
Fig 5. Pin configuration for DHVQFN20 (SOT764-1)
74CBTLV3245 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 3 — 11 November 2016 4 of 19
NXP Semiconductors 74CBTLV3245
8-bit bus switch with output enable
5.2 Pin description
6. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state.
7. Limiting values
[1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SSOP20 and TSSOP20 packages: above 60 C the value of Ptot derates linearly at 5.5 mW/K.
For DHVQFN20 packages: above 60 C the value of Ptot derates linearly at 4.5 mW/K.
Table 2. Pin description
Symbol Pin Description
nc 1 not connected
A1 to A8 2, 3, 4, 5, 6, 7, 8, 9 data input/output (A port)
GND 10 ground (0 V)
B1 to B8 18, 17, 16, 15, 14, 13, 12, 11 data input/output (B port)
OE 19 output enable input (active LOW)
VCC 20 positive supply voltage
Table 3. Function selection[1]
Input Input/output
OE An, Bn
LAn = Bn
HZ
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +4.6 V
VIinput voltage [1] 0.5 +4.6 V
VSW switch voltage enable and disable mode [1] 0.5 VCC + 0.5 V
IIK input clamping current VI<0.5 V 50 - mA
ISK switch clamping current VI<0.5 V 50 - mA
ISW switch current VSW = 0 V to VCC -128 mA
ICC supply current - +100 mA
IGND ground current 100 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb =40 Cto+125C[2] - 500 mW
Typ, Figure 6 Figure 7
74CBTLV3245 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 3 — 11 November 2016 5 of 19
NXP Semiconductors 74CBTLV3245
8-bit bus switch with output enable
8. Recommended operating conditions
[1] Applies to control signal levels.
9. Static characteristics
[1] All typical values are measured at Tamb =25C.
[2] One input at 3 V, other inputs at VCC or GND.
Table 5. Recommended operating conditions
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 2.3 3.6 V
VIinput voltage 03.6V
VSW switch voltage enable and disable mode 0 VCC V
Tamb ambient temperature 40 +125 C
t/V input transition rise and fall rate VCC = 2.3 V to 3.6 V [1] -200ns/V
Table 6. Static characteristics
At recommended operating conditions voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Tamb =40 C to +85 C Tamb =40 C to +125 CUnit
Min Typ[1] Max Min Max
VIH HIGH-level
input voltage VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V
VCC = 3.0 V to 3.6 V 2.0 - - 2.0 - V
VIL LOW-level input
voltage VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V
VCC = 3.0 V to 3.6 V - - 0.9 - 0.9 V
IIinput leakage
current pin OE; VI = GND to VCC;
VCC =3.6V --1- 20 A
IS(OFF) OFF-state
leakage current VCC = 3.6 V; see Figure 6 --1- 20 A
IS(ON) ON-state
leakage current VCC = 3.6 V; see Figure 7 --1- 20 A
IOFF power-off
leakage current VI or VO = 0 V to 3.6 V;
VCC =0V --10 - 50 A
ICC supply current VI = GND or VCC; IO = 0 A;
VSW =GNDorV
CC;
VCC =3.6V
--10- 50A
ICC additional
supply current pin OE; VI=V
CC 0.6 V;
VSW =GNDorV
CC;
VCC =3.6V
[2] - - 300 - 2000 A
CIinput
capacitance pin OE; VCC = 3.3 V;
VI=0Vto3.3 V -0.9- - -pF
CS(OFF) OFF-state
capacitance VCC = 3.3 V; VI=0Vto3.3 V - 5.2 - - - pF
CS(ON) ON-state
capacitance VCC = 3.3 V; VI= 0 V to 3.3 V - 14.3 - - - pF
0mm ,4, 0mm; Figure 8 Figure 9 Figure 11 Figure 12 Figure 14
74CBTLV3245 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 3 — 11 November 2016 6 of 19
NXP Semiconductors 74CBTLV3245
8-bit bus switch with output enable
9.1 Test circuits
9.2 ON resistance
[1] Typical values are measured at Tamb =25C and nominal VCC.
[2] Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is
determined by the lower of the voltages of the two (A or B) terminals.
VI = VCC or GND and VO = GND or VCC.V
I = VCC or GND and VO = open circuit.
Fig 6. Test circuit for measuring OFF-state leakage
current (one switch) Fig 7. Test circuit for measuring ON-state leakage
current (one switch)
$$
DDQ
*1'
2(
%Q
9,+
9,
,6,6
92
9&&
$Q
$
DDQ
*1'
2(
$Q
9,/
9,
,6
92
9&&
%Q
Table 7. Resistance RON
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.
Symbol Parameter Conditions Tamb =40 C to +85 C Tamb =40 C to +125 CUnit
Min Typ[1] Max Min Max
RON ON resistance VCC = 2.3 V to 2.7 V;
see Figure 9 to Figure 11
[2]
ISW =64mA; V
I= 0 V - 4.2 8.0 - 15.0
ISW =24 mA; V
I= 0 V - 4.2 8.0 - 15.0
ISW = 15 mA; VI= 1.7 V - 8.4 40 - 60.0
VCC = 3.0 V to 3.6 V;
see Figure 12 to Figure 14
ISW =64mA; V
I=0V - 4.0 7.0 - 11.0
ISW =24 mA; V
I=0V - 4.0 7.0 - 11.0
ISW = 15 mA; VI= 2.4 V - 6.2 15 - 25.5
sssssssss 777 iiigi r\ // /\ 2A i: ’\ /// //\/ . AJ/
74CBTLV3245 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 3 — 11 November 2016 7 of 19
NXP Semiconductors 74CBTLV3245
8-bit bus switch with output enable
9.3 ON resistance test circuit and graphs
RON =V
SW / ISW.(1)T
amb = 125 C.
(2) Tamb = 85 C.
(3) Tamb = 25 C.
(4) Tamb =40 C.
Fig 8. Test circuit for measuring ON resistance
(one switch) Fig 9. ON resistance as a function of input voltage;
VCC = 2.5 V; ISW = 15 mA
DDQ
*1'
2(
$Q
9,/
9,
96:
9&&
%Q
9
,6:
9,9
 
DDL

521
ȍ




(1) Tamb = 125 C.
(2) Tamb = 85 C.
(3) Tamb = 25 C.
(4) Tamb =40 C.
(1) Tamb = 125 C.
(2) Tamb = 85 C.
(3) Tamb = 25 C.
(4) Tamb =40 C.
Fig 10. ON resistance as a function of input voltage;
VCC = 2.5 V; ISW = 24 mA Fig 11. ON resistance as a function of input voltage;
VCC = 2.5 V; ISW = 64 mA
9,9
 
DDL

521
ȍ




9,9
 
DDL

521
ȍ




(21 7m
74CBTLV3245 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 3 — 11 November 2016 8 of 19
NXP Semiconductors 74CBTLV3245
8-bit bus switch with output enable
(1) Tamb = 125 C.
(2) Tamb = 85 C.
(3) Tamb = 25 C.
(4) Tamb =40 C.
(1) Tamb = 125 C.
(2) Tamb = 85 C.
(3) Tamb = 25 C.
(4) Tamb =40 C.
Fig 12. ON resistance as a function of input voltage;
VCC = 3.3 V; ISW = 15 mA Fig 13. ON resistance as a function of input voltage;
VCC = 3.3 V; ISW = 24 mA
9,9

DDL
521
ȍ




9,9

DDL
521
ȍ




(1) Tamb = 125 C.
(2) Tamb = 85 C.
(3) Tamb = 25 C.
(4) Tamb =40 C.
Fig 14. ON resistance as a function of input voltage; VCC = 3.3 V; ISW = 64 mA
9,9

DDL





521
ȍ





s Figure 17 Figure 15 Figure 16 Figure 16 0171351367
74CBTLV3245 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 3 — 11 November 2016 9 of 19
NXP Semiconductors 74CBTLV3245
8-bit bus switch with output enable
10. Dynamic characteristics
[1] All typical values are measured at Tamb =25C and at nominal VCC.
[2] The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the load capacitance, when
driven by an ideal voltage source (zero output impedance).
[3] tpd is the same as tPLH and tPHL.
[4] ten is the same as tPZH and tPZL.
[5] tdis is the same as tPHZ and tPLZ.
11. Waveforms
Table 8. Dynamic characteristics
GND = 0 V; for test circuit see Figure 17
Symbol Parameter Conditions Tamb =40 C to +85 C Tamb =40 C to +125 CUnit
Min Typ[1] Max Min Max
tpd propagation delay An to Bn or Bn to An;
see Figure 15
[2][3]
VCC = 2.3 V to 2.7 V - - 0.13 - 0.20 ns
VCC = 3.0 V to 3.6 V - - 0.20 - 0.31 ns
ten enable time OE to An or Bn;
see Figure 16
[4]
VCC = 2.3 V to 2.7 V 1.0 3.4 5.5 1.0 8.0 ns
VCC = 3.0 V to 3.6 V 1.0 3.0 4.9 1.0 7.0 ns
tdis disable time OE to An or Bn;
see Figure 16
[5]
VCC = 2.3 V to 2.7 V 1.0 3.0 5.5 1.0 8.0 ns
VCC = 3.0 V to 3.6 V 1.0 3.4 5.8 1.0 8.5 ns
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 15. The data input (An, Bn) to output (Bn, An) propagation delay times
DDL
9090
9090
9,
LQSXW
9
92+
RXWSXW
92/
W3+/ W3/+
Table 9. Measurement points
Supply voltage Input Output
VCC VMVItr = tfVMVXVY
2.3 V to 2.7 V 0.5VCC VCC 2.0 ns 0.5VCC VOL +0.15V V
OH 0.15 V
3.0 V to 3.6 V 0.5VCC VCC 2.0 ns 0.5VCC VOL +0.3V V
OH 0.3 V
74CBTLV3245 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 3 — 11 November 2016 10 of 19
NXP Semiconductors 74CBTLV3245
8-bit bus switch with output enable
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 16. Enable and disable times
DDQ
*1'
*1'
9&&
92/
92+
9,
9090
90
9<
9;
W3/= W3=/
W3+= W3=+
VZLWFK
GLVDEOHG
VZLWFK
HQDEOHG
VZLWFK
HQDEOHG
90
RXWSXW
/2:WR2))
2))WR/2:
RXWSXW
+,*+WR2))
2))WR+,*+
2(LQSXW
H i if E
74CBTLV3245 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 3 — 11 November 2016 11 of 19
NXP Semiconductors 74CBTLV3245
8-bit bus switch with output enable
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 17. Test circuit for measuring switching times
9090
W:
W:


9
9,
9,
QHJDWLYH
SXOVH
SRVLWLYH
SXOVH
9
9090


WI
WU
WU
WI
DDH
9(;7
9&&
9,92
'87
&/
57
5/
5/
*
Table 10. Test data
Supply voltage Load VEXT
VCC CLRLtPLH, tPHL tPZH, tPHZ tPZL, tPLZ
2.3 V to 2.7 V 30 pF 500 open GND 2VCC
3.0 V to 3.6 V 50 pF 500 open GND 2VCC
figure 18 oommss
74CBTLV3245 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 3 — 11 November 2016 12 of 19
NXP Semiconductors 74CBTLV3245
8-bit bus switch with output enable
11.1 Additional dynamic characteristics
[1] fi is biased at 0.5VCC.
11.2 Test circuit
Table 11. Additional dynamic characteristics
GND = 0 V.
Symbol Parameter Conditions Tamb = 25 CUnit
Min Typ Max
f(3dB) 3 dB frequency response VCC = 3.3 V; RL=50; see Figure 18 [1] - 406 - MHz
Adjust fi voltage to obtain 0 dBm level at output. Increase fi frequency until dB meter reads 3dB.
Fig 18. Test circuit for measuring the frequency response when channel is in ON-state
DDQ
*1'
2(
%Q $Q
9
&&
9
&&
9
,/
IL
5/
G%
74CBTLV3245 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 3 — 11 November 2016 13 of 19
NXP Semiconductors 74CBTLV3245
8-bit bus switch with output enable
12. Package outline
Fig 19. Package outline SOT724-1 (SSOP20)
81,7 $ $ $ +( /S
ES F ' ( =
H / \ZY ș
5()(5(1&(6
287/,1(
9(56,21
(8523($1
352-(&7,21 ,668('$7(
,(& -('(& -(,7$
PP 


  






  








R
R
 
',0(16,216PLOOLPHWUHGLPHQVLRQVDUHGHULYHGIURPWKHRULJLQDOLQFKGLPHQVLRQV
1RWH
3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG
627 

Z 0
ES
'
+(
(
=
H
F
Y 0 $
;
$
\
 
 
ș
$
$
$
/S
GHWDLO;
/
$
02
  PP
VFDOH
6623SODVWLFVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPPOHDGSLWFKPP 627
$
PD[

H
74CBTLV3245 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 3 — 11 November 2016 14 of 19
NXP Semiconductors 74CBTLV3245
8-bit bus switch with output enable
Fig 20. Package outline SOT360-1 (TSSOP20)
81,7 $
 $
 $
 E
S F ' ( 
H +
( / /
S 4 =\ZY ș
5()(5(1&(6
287/,1(
9(56,21
(8523($1
352-(&7,21 ,668('$7(
,(& -('(& -(,7$
PP 










  







R
R
 
',0(16,216PPDUHWKHRULJLQDOGLPHQVLRQV
1RWHV
3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG
3ODVWLFLQWHUOHDGSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG


627 02 

Z 0
E
S
'
=
H

 
 
SLQLQGH[
ș
$
$

$

/
S
4
GHWDLO;
/
$

+
(
(
F
Y 0 $
;
$
\
  PP
VFDOH
76623SODVWLFWKLQVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP 627
$
PD[

1 ? W 1 W ,,,,,,, 4 ,,,,,,,, , ‘ l \ D (M) 4* *DF ‘ ’H (“3 fij [U U U€U U U U I: ‘ 67‘ «5* ****** reg 0 H H mm fl 0 fl E}@ W
74CBTLV3245 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 3 — 11 November 2016 15 of 19
NXP Semiconductors 74CBTLV3245
8-bit bus switch with output enable
Fig 21. Package outline SOT764-1 (DHVQFN20)
5HIHUHQFHV
2XWOLQH
YHUVLRQ
(XURSHDQ
SURMHFWLRQ ,VVXHGDWH
,(& -('(& -(,7$
627 
02

VRWBSR


8QLW
PP
PD[
QRP
PLQ
    
  
$
'LPHQVLRQVPPDUHWKHRULJLQDOGLPHQVLRQV
1RWH
3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG
$E

F'
 'K( (K

HH
/

YZ

\\
       
     
 
GHWDLO;
% $
H
H
H
&
\
&
\
;
$&%
Y
&
Z
VFDOH
$
$
F
/
(K
'K
E

 



'
(
WHUPLQDO
LQGH[DUHD
WHUPLQDO
LQGH[DUHD
PP
'+94)1SODVWLFGXDOLQOLQHFRPSDWLEOHWKHUPDOHQKDQFHGYHU\WKLQTXDGIODWSDFNDJHQROHDGV
WHUPLQDOVERG\[[PP 627
Section 11.1 Section 11.2
74CBTLV3245 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 3 — 11 November 2016 16 of 19
NXP Semiconductors 74CBTLV3245
8-bit bus switch with output enable
13. Abbreviations
14. Revision history
Table 12. Abbreviations
Acronym Description
CDM Charged Device Model
CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
Table 13. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74CBTLV3245 v.3 20161111 Product data sheet - 74CBTLV3245 v.2
Modifications: Section 11.1 and Section 11.2 added.
74CBTLV3245 v.2 20111215 Product data sheet - 74CBTLV3245 v.1
Modifications: Legal pages updated.
74CBTLV3245 v.1 20101230 Product data sheet - -
74CBTLV3245 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 3 — 11 November 2016 17 of 19
NXP Semiconductors 74CBTLV3245
8-bit bus switch with output enable
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
hug :l/www. nxgcom salesaddresses®nx9£0m
74CBTLV3245 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 3 — 11 November 2016 18 of 19
NXP Semiconductors 74CBTLV3245
8-bit bus switch with output enable
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74CBTLV3245
8-bit bus switch with output enable
© NXP Semiconductors N.V. 2016. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 11 November 2016
Document identifier: 74CBTLV3245
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Functional description . . . . . . . . . . . . . . . . . . . 4
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
8 Recommended operating conditions. . . . . . . . 5
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
9.1 Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
9.2 ON resistance. . . . . . . . . . . . . . . . . . . . . . . . . . 6
9.3 ON resistance test circuit and graphs. . . . . . . . 7
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
11.1 Additional dynamic characteristics . . . . . . . . . 12
11.2 Test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
16 Contact information. . . . . . . . . . . . . . . . . . . . . 18
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Products related to this Datasheet

IC BUS SWITCH 8BIT 20-SSOP