CYW20702 Datasheet by Cypress Semiconductor Corp

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CYW20702
Single-Chip Bluetooth Transceiver and
Baseband Processor
Cypress Semiconductor Corporation 198 Champion Court San Jose,CA 95134-1709 408-943-2600
Document Number: 002-14773 Rev. *M Revised Wednesday, November 15, 2017
The CYW20702 is a monolithic, single-chip, Bluetooth 4.0 compliant, stand-alone baseband processor with an integrated 2.4 GHz
transceiver. Manufactured using the industry's most advanced 65 nm CMOS low-power process, the CYW20702 employs the highest
level of integration, eliminating all critical external components, and thereby minimizing the device’s footprint and costs associated
with the implementation of Bluetooth solutions.
The CYW20702 is the optimal solution for voice and data applications that require a Bluetooth SIG standard Host Controller Interface
(HCI) via USB, UART H4 or H5, and PCM audio interface support. The CYW20702 radio transceiver’s enhanced radio performance
meets the most stringent industrial temperature application requirements for compact integration into mobile handset and portable
devices. The CYW20702 is fully compatible with all standard TCXO frequencies and provides full radio compatibility, enabling it to
operate simultaneously with GPS and cellular radios.
This document provides engineering design information for the CYW20702, a single-chip Bluetooth transceiver and baseband
processor that provides a complete lower layer Bluetooth protocol stack. The CYW20702 supports Bluetooth 4.0, which includes
support for Enhanced Data Rates (2 Mbps and 3 Mbps) and Low Energy (LE) connections.
The information provided is intended for hardware design engineers who will be incorporating the CYW20702 into their designs.
Cypress Part Numbering Scheme
Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion,
there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides
Cypress ordering part number that matches an existing IoT part number.
Features
Bluetooth 4.0 + EDR and Low Energy compliant
Class 1 capable with built-in PA
Programmable output power control meets Class 1, Class 2,
or Class 3 requirements
Use supply voltages up to 5.5V
Supports Broadcom SmartAudio™, wide-band speech, SBC
codec, and packet loss concealment.
Fractional-N synthesizer supports frequency references from
12 MHz to 52 MHz
Automatic frequency detection for standard crystal and TCXO
values when an external 32.768 kHz reference clock is
provided.
Ultra-low power consumption
Supports serial flash interfaces
Available in a 50-ball FPBGA package.
ARM7TDMI-S™–based microprocessor with integrated ROM
and RAM
Supports mobile and PC applications without external memory
A USB hub
Table 1. Mapping Table for Part Number between Broadcom and Cypress
Broadcom Part Number Cypress Part Number
BCM4325 CYW4325
BCM4329 CYW4329
BCM4330 CYW4330
BCM20702 CYW20702
BCM20702A1KWFBG CYW20702A1KWFBG
BCM20702B0KWFBG CYW20702B0KWFBG
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CYW20702
Applications
Desktop and laptop personal computers
Computer peripheral devices (PCMCIA cards, CF cards, and
USB dongles)
Personal digital assistants
Automotive telematic systems
Figure 1. System Block Diagram
Microprocessorand
MemoryUnit(uPU)
BluetoothBasebandCore
(BBC)
HighSpeedPeripheral
TransportUnit(PTU) RadioTransceiver
TCXO
LPO
PCM/I2S
USB
UART/SPI
GPIO
SPIMaster
BSC
CYW20702
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CYW20702
Contents
1. Overview ........................................................................4
1.1 Major Features ...................................................... 4
1.2 Block Diagram .......................................................6
1.3 Usage Model .........................................................7
2. Integrated Radio Transceiver ......................................8
2.1 Transmitter Path .................................................... 8
2.2 Receiver Path ........................................................8
2.3 Local Oscillator Generation ...................................8
2.4 Calibration ............................................................. 8
2.5 Internal LDO .......................................................... 9
3. Bluetooth Baseband Core ......................................... 10
3.1 Transmit and Receive Functions .........................10
3.2 Bluetooth 4.0 + EDR Features ............................ 10
3.3 Frequency Hopping Generator ............................ 10
3.4 Link Control Layer ...............................................10
3.5 Test Mode Support .............................................. 11
3.6 Power Management Unit .....................................11
3.7 Adaptive Frequency Hopping .............................. 13
3.8 Collaborative Coexistence ................................... 13
3.9 Serial Enhanced Coexistence Interface .............. 14
4. Microprocessor Unit ................................................... 15
4.1 Overview .............................................................15
4.2 NVRAM Configuration Data and Storage ............ 15
4.3 EEPROM ............................................................. 15
4.4 External Reset .....................................................15
4.5 One-Time Programmable Memory ...................... 16
5. Peripheral Transport Unit .......................................... 17
5.1 PCM Interface ..................................................... 17
5.2 HCI Transport Detection Configuration ............... 19
5.3 USB Interface ...................................................... 19
5.4 UART Interface .................................................... 21
5.5 SPI ....................................................................... 22
5.6 Simultaneous UART Transport and Bridging ...... 22
6. Frequency References ............................................... 23
6.1 Crystal Interface and Clock Generation .............. 23
6.2 Crystal Oscillator...................................................... 24
6.3 External Frequency Reference ............................ 24
6.4 Frequency Selection ............................................ 25
6.5 Frequency Trimming ........................................... 25
6.6 LPO Clock Interface ............................................ 26
7. Pin-out and Signal Descriptions ............................... 27
7.1 Pin Descriptions .................................................. 27
8. Ball Grid Arrays .......................................................... 29
9. Electrical Characteristics ........................................... 30
9.1 RF Specifications ................................................ 36
9.2 Timing and AC Characteristics ............................ 39
9.3 Electrostatic Discharge ........................................ 48
10. Mechanical Information ........................................... 50
10.1 Tape, Reel, and Packing Specification .............. 51
11. Ordering Information ................................................ 52
12. Acronyms and Abbreviations .................................. 52
13. IoT Resources ........................................................... 52
Document History ........................................................... 53
Sales, Solutions, and Legal Information ...................... 55
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CYW20702
1. Overview
The CYW20702 complies with Bluetooth Core Specification, version 4.0 and is designed for use in standard Host Controller Interface
(HCI) UART and HCI USB applications. The combination of the Bluetooth Baseband Core (BBC), a Peripheral Transport Unit (PTU),
and an ARM®-based microprocessor with on-chip ROM provides a complete lower layer Bluetooth protocol stack, including the Link
Controller (LC), Link Manager (LM), and HCI.
1.1 Major Features
Major features of the CYW20702 include:
Support for Bluetooth 4.0 + EDR and Low Energy (LE), including the following options:
A whitelist size of 25.
Enhanced Power Control
HCI Read Encryption Key Size command
Full support for Bluetooth 2.1 + EDR additional features:
Secure Simple Pairing (SSP)
Encryption Pause Resume (EPR)
Enhance Inquiry Response (EIR)
Link Supervision Time Out (LSTO)
Sniff SubRating (SSR)
Erroneous Data (ED)
Packet Boundary Flag (PBF)
Built-in Low Drop-Out (LDO) regulators (2)
1.63 to 5.5V input voltage range
1.8 to 3.3V intermediate programmable output voltage
Integrated RF section
Single-ended, 50 ohm RF interface
Built-in TX/RX switch functionality
TX Class 1 output power capability
RX sensitivity basic rate of –88 dBm
RX sensitivity for Low Energy of –92 dBm
Supports maximum Bluetooth data rates over HCI UART, USB, and SPI interfaces
Multipoint operation, with up to 7 active slaves
Maximum of 7 simultaneous active ACL links
Maximum of 3 simultaneous active SCO and eSCO links, with Scatternet support
Scatternet operation, with up to 4 active piconets (with background scan and support for ScatterMode)
High-speed HCI UART transport support
H4 five-wire UART (four signal wires, one ground wire)
H5 three-wire UART (two signal wires, one ground wire)
Maximum UART baud rates of 4 Mbps
Low-power out-of-band BT_WAKE and HOST_WAKE signaling
VSC from host transport to UART
Proprietary compressing scheme (allows more than 2 simultaneous A2DP packets and up to 5 devices at a time)
HCI USB transport support
USB version 2.0 full-speed compliant interface
Full USB hub
UHE (proprietary method for emulating a Human Interface Device (HID) at system bootup)
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CYW20702
Channel Quality-Driven Data Rate (CQDDR) and packet type selection
Standard Bluetooth test modes
Extended radio and production test mode features
Full support for power savings modes:
Bluetooth standard sniff
Deep sleep modes and regulator shutdown
Supports Wide-Band Speech (WBS) over PCM and Packet Loss Concealment (PLC) for better audio quality
2-, 3-, and 4-wire coexistence
Power Amplifier (PA) shutdown for externally controlled coexistence, such as WIMAX
Built-in LPO clock or operation using an external LPO clock
TCXO input and auto-detection of all standard handset clock frequencies (supports low-power crystal, which can be used during
Power Saving mode with better timing accuracy)
OR gate for combining a host clock request with a Bluetooth clock request (operates even when the Bluetooth core logic is powered
off)
Larger patch RAM space to support future enhancements
Serial flash Interface with native support for devices from several manufacturers
One-Time Programmable (OTP) memory
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CYW20702
1.2 Block Diagram
Figure 2 shows the interconnect of the major CYW20702 physical blocks and associated external interfaces.
Figure 2. Functional Block Diagram
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CYW20702
1.3 Usage Model
This section contains information on the “PC Product Usage Model”.
1.3.1 PC Product Usage Model
The CYW20702 can be directly interfaced using the HCI USB interface, providing full support for embedded USB applications like
laptops and PC motherboards. The CYW20702 also supports PC applications as an external USB dongle peripheral device.
Figure 3 shows an example of a PC product usage model.
Figure 3. PC Product Usage Model
Host PC
Flash Memory
CYW20702
IEEE 802.11™
WLAN
USB
OPTIONAL/STATUS
BT_BUSY/TX_REQ
WIFI_BUSY/TX_CONFIRM
LINK_IND
20 MHz Crystal Oscillator
Serial Interface
VDD_USB
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CYW20702
2. Integrated Radio Transceiver
The CYW20702 has an integrated radio transceiver that has been optimized for use in 2.4 GHz Bluetooth wireless systems. It has
been designed to provide low-power, low-cost, robust communications for applications operating in the globally available 2.4 GHz
unlicensed ISM band. The CYW20702 is fully compliant with the Bluetooth Radio Specification and enhanced data rate specification
and meets or exceeds the requirements to provide the highest communication link quality of service.
2.1 Transmitter Path
The CYW20702 features a fully integrated zero IF transmitter. The baseband transmitted data is digitally modulated in the modem
block and up-converted to the 2.4 GHz ISM band in the transmitter path. The transmitter path consists of signal filtering, I/Q up-
conversion, a high-output power amplifier (PA), and RF filtering.
The CYW20702 also incorporates modulation schemes to support enhanced data rates.
P/4-DQPSK for 2 Mbps
8-DPSK for 3 Mbps
2.1.1 Digital Modulator
The digital modulator performs the data modulation and filtering required for the GFSK, /4DQPSK, and 8-DPSK signals. The fully
digital modulator minimizes any frequency drift or anomalies in the modulation characteristics of the transmitted signal and is much
more stable than direct VCO modulation schemes.
2.1.2 Power Amplifier
The CYW20702 integrated PA can be configured for Class 2 operation, transmitting up to +4 dBm. The PA can also be configured for
Class 1 operation, transmitting up +10 dBm at the chip in gFSK mode, when a minimum supply voltage of 2.5V is applied to VDDTF.
Because of the linear nature of the PA, combined with integrated filtering, minimal external filtering is required to meet Bluetooth and
regulatory harmonic and spurious requirements.
Using a highly linearized, temperature compensated design, the PA can transmit +10 dBm for basic rate and +8 dBm for enhanced
data rates (2 to 3 Mbps). A flexible supply voltage range allows the PA to operate from 1.2V to 3.3V. A minimum supply voltage of
2.5V is required at VDDTF to achieve +10 dBm of transmit power.
2.2 Receiver Path
The receiver path uses a low IF scheme to downconvert the received signal for demodulation in the digital demodulator and bit
synchronizer. The receiver path provides a high degree of linearity, an extended dynamic range, and high order on-chip channel
filtering to ensure reliable operation in the noisy 2.4 GHz ISM band. The front-end topology, with built-in out-of-band attenuation,
enables the device to be used in most applications without off-chip filtering. For integrated handset operation where the Bluetooth
function is integrated close to the cellular transmitter, minimal external filtering is required to eliminate the desensitization of the
receiver by the cellular transmit signal.
2.2.1 Digital Demodulator and Bit Synchronizer
The digital demodulator and bit synchronizer uses the low IF received signal to perform an optimal frequency tracking and bit synchro-
nization algorithm.
2.2.2 Receiver Signal Strength Indicator
The CYW20702 radio provides a Receiver Signal Strength Indicator (RSSI) signal to the baseband so that the controller can take part
in a Bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine whether the transmitter
should increase or decrease its output power.
2.3 Local Oscillator Generation
Local Oscillator (LO) generation provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels.
The LO generation subblock employs an architecture for high immunity to LO pulling during PA operation. The device uses fully-
integrated PLL loop filters.
2.4 Calibration
The radio transceiver features an automated calibration scheme that is fully self-contained in the radio. User interaction is not required
during normal operation or during manufacturing to provide the optimal performance. Calibration optimizes the performance of all
major blocks in the radio, including gain and phase characteristics of filters, matching between key components, and key gain blocks.
Calibration, which takes process and temperature variations into account, occurs transparently during the settling time of the hops,
adjusting for temperature variations as the device cools and heats during normal operation.
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2.5 Internal LDO
Two internal Low Drop-Out (LDO) voltage regulators eliminate the need for external voltage regulators and therefore reduce the BOM.
The first LDO is a preregulator (HV LDO). The second LDO (Main LDO) supplies the main power to the CYW20702 (see Figure 4).
The HV LDO has an input voltage range of 2.3V to 5.5V. The input VBAT is ideal for batteries. The VREGHV output is programmable
from 1.8V to 3.3V, in 100 mV steps. The dropout voltage is 200 mV. The HV LDO can supply up to 95 mA, which leaves spare power
for external circuitry such as an RF power amp for higher transmit power. If the HV LDO is not used, to turn off the HV LDO and
minimize current consumption, connect the VBAT input to the VREGHV output. Firmware can then disable the HV LDO, saving the
quiescent current.
The HV LDO default output voltage is 2.9V, allowing this regulator to be used to power external NV memory devices, as well as the
VDDO rail. The firmware can then adjust this output to as low as 1.8V, if desired, to power VDDTF.
The main LDO has a 1.22V output (VREG) and is used to supply main power to the CYW20702. The input of this LDO (VREGHV)
has an input voltage range of from 1.63V to 3.63V. The output of the HV LDO is internally connected to the input to the main LDO.
Power can be applied to VREGHV when the HV LDO is not used. The main LDO supplies power to the entire device for Class 2
operation. The main LDO can drive up to 60 mA, which leaves spare power for external circuitry. The main LDO is bypassed by not
connecting anything to its output (VREG) and driving 1.12V–1.32V directly to VDDC and VDDRF.
REG_EN provides a control signal for the host to control power to the CYW20702. When power is enabled, the CYW20702 will require
complete initialization.
Figure 4. LDO Functional Block Diagram
HV LDO Main LDO
VREGHVVBAT VREG
REG_EN
CYW20702
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3. Bluetooth Baseband Core
The Bluetooth Baseband Core (BBC) implements the time critical functions required for high-performance Bluetooth and Low Energy
operation. The BBC manages buffering, segmentation, and data routing for all connections. It also buffers data that passes through
it, handles data flow control, schedules SCO/ACL Tx/Rx transactions, monitors Bluetooth slot usage, optimally segments and
packages data into baseband packets, manages connection status indicators, and composes and decodes HCI packets. In addition
to these functions, it independently handles HCI event types and HCI command types.
3.1 Transmit and Receive Functions
The following transmit and receive functions are implemented in the BBC hardware to increase the reliability and security of the
Tx/Rx data before sending the data over the air:
In the transmitter:
Data framing
Forward Error Correction (FEC) generation
Header Error Control (HEC) generation
Cyclic Redundancy Check (CRC) generation
Key generation
Data encryption
Data whitening
In the receiver:
Symbol timing recovery
Data deframing
FEC
HEC
CRC
Data decryption
Data dewhitening
3.2 Bluetooth 4.0 + EDR Features
The CYW20702 supports Bluetooth 4.0 + EDR and Low Energy, including the following options:
A whitelist size of 25
Enhanced Power Control
HCI Read Encryption Key Size command
The CYW20702 provides full support for Bluetooth 2.1 + EDR additional features:
Secure Simple Pairing (SSP)
Encryption Pause Resume (EPR)
Enhance Inquiry Response (EIR)
Link Supervision Time Out (LSTO)
Sniff SubRating (SSR)
Erroneous Data (ED)
Packet Boundary Flag (PBF)
3.3 Frequency Hopping Generator
The frequency hopping sequence generator selects the correct hopping channel number, based on the link controller state, Bluetooth
clock, and device address.
3.4 Link Control Layer
The Link Control layer is part of the Bluetooth link control functions implemented in dedicated logic in the Link Control Unit (LCU).
This layer consists of the Command Controller that takes commands from the software and other controllers that are activated or
configured by the Command Controller to perform the link control tasks.
There are two major states–Standby and Connection. Each task establishes a different state in the Bluetooth Link Controller. In
addition, there are eight substates—Page, Page Scan, Inquiry, Inquiry Scan, Sniff, and Sniff SubRating.
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3.5 Test Mode Support
The CYW20702 fully supports Bluetooth Test Mode.
In addition to the standard Bluetooth Test mode, the device supports enhanced testing features to simplify RF debugging and quali-
fication and type approval testing.
These test features include:
Fixed frequency carrier wave (unmodulated) transmission
Simplifies some type approval measurements (Japan)
Aids in transmitter performance analysis
Fixed frequency constant receiver mode
Directs receiver output to I/O pin
Allows for direct BER measurements using standard RF test equipment
Facilitates spurious emissions testing for receive mode
Fixed frequency constant bit stream transmission
Unmodulated, 8-bit fixed pattern, PRBS-9, or PRBS-15
Enables modulated signal measurements with standard RF test equipment
Packetized connectionless transmitter test
Hopping or fixed frequency
Multiple packet types supported
Multiple data patterns supported
Packetized connectionless receiver test
Fixed frequency
Multiple packet types supported
Multiple data patterns supported
3.6 Power Management Unit
The Power Management Unit (PMU) provides power management features that can be invoked through power management registers
or packet handling in the baseband core. This section contains descriptions of the PMU features.
3.6.1 RF Power Management
The BBC generates power-down control signals for the transmit path, receive path, PLL, and power amplifier to the 2.4 GHz trans-
ceiver. The transceiver then processes the power-down functions, accordingly.
3.6.2 Host Controller Power Management
The host can place the device in a sleep state, in which all nonessential blocks are powered off and all nonessential clocks are
disabled. Power to the digital core is maintained so that the state of the registers and RAM is not lost. In addition, the LPO clock is
applied to the internal sleep controller so that the chip can wake automatically at a specified time or based on signaling from the host.
The goal is to limit the current consumption to a minimum, while maintaining the ability to wake up and resume a connection with
minimal latency.
If a scan or sniff session is enabled while the device is in Sleep mode, the device automatically will wake up for the scan/sniff event,
then go back to sleep when the event is done. In this case, the device uses its internal LPO-based timers to trigger the periodic wake
up. While in Sleep mode, the transports are idle. However, the host can signal the device to wake up at any time. If signaled to wake
up while a scan or sniff session is in progress, the session continues but the device will not sleep between scan/sniff events. Once
Sleep mode is enabled, the wake signaling mechanism can also be thought of as a sleep signaling mechanism, since removing the
wake status will often cause the device to sleep.
In addition to a Bluetooth device wake signaling mechanism, there is a host wake signaling mechanism. This feature provides a way
for the Bluetooth device to wake up a host that is in a reduced power state.
There are three mechanisms for the device and the host to signal wake status to each other:
USB: When running in USB mode, the device supports the USB version 2.0 full-speed specification, suspend/resume signaling,
as well as remote wake-up signaling for power control.
Bluetooth WAKE (BT_WAKE) and Host WAKE (and HOST_WAKE) signaling: The BT_WAKE pin (GPIO_0) allows the host to
wake the BT device, and HOST_WAKE (GPIO_1) is an output that allows the BT device to wake the host.
In-band UART signaling: The CTS and RTS signals of the UART interface are used for BT wake (CTS) and Host wake (RTS)
functions in addition to their normal function on the UART interface. Note that this applies for both H4 and H5 protocols.
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CYW20702
When running in SPI mode, the CYW20702 has a mode where it enters Sleep mode when there is no activity on the SPI interface for
a specified (programmable) amount of time. Idle mode is detected when the SPI_CSN is left deasserted. Whether to sleep on an idle
interface and the amount of time to wait before entering Sleep mode can be programed by the host. Once the CYW20702 enters
sleep, the host can wake it by asserting SPI_CSN. If the host decides to sleep, the CYW20702 will wake up the host by asserting
SPI_INT when it has data for it.
Note: Successful operation of the power management handshaking signals requires coordinated support between the device
firmware and the host software.
3.6.3 BBC Power Management
The device provides the following low-power operations for the BBC:
Physical layer packet handling turns RF on and off dynamically within packet TX and RX.
Bluetooth specified low-power connection mode (Sniff). While in this low-power connection mode, the device runs on the Low
Power Oscillator and wakes up after a predefined time period.
Table 2. Power Control Pin Summary
Pin Direction Description
BT_WAKE
(GPIO_0)
Host output
BT input
Bluetooth device wake-up: Signal from the host to the Bluetooth device that the host requires
attention.
Asserted = Bluetooth device must wake up or remain awake.
Deasserted = Bluetooth device may sleep when sleep criteria are met.
The polarity of this signal is software configurable and can be asserted high or low. By default,
BT_WAKE is active-low (if BT-WAKE is low it requires the device to wake up or remain awake).
For USB applications, this can be used for setting Airport mode (radio disable mode).
HOST_WAKE
(GPIO_1)
BT output
Host input
Host wake-up. Signal from the Bluetooth device to the host indicating that Bluetooth device
requires attention.
Asserted = Host device must wake up or remain awake.
Deasserted = Host device may sleep when sleep criteria are met.
The polarity of this signal is software configurable and can be asserted high or low.
CLK_REQ
(GPIO_5)
BT output Clock request
Asserted = External clock reference required
Deasserted = External clock reference may be powered down
For the CYW20702A1KWFBG, the polarity of CLK_REQ is active low.
REG_EN BT input Enables the internal preregulator and main regulator outputs. REG_EN is active-high.
1 = Enabled
0 = Disabled
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3.6.4 Backdrive Protection
The CYW20702 provides a backdrive protection feature that allows the device to be turned off while the host and other devices in the
system remain operational. When the device is not needed in the system, VDD_RF and VDDC are shut down and VDDO remains
powered. This allows the device to be effectively off, while keeping the I/O pins powered so that they do not draw extra current from
other devices connected to the I/O.
Note: VDD_RF collectively refers to the VDDTF, VDDIF, VDDLNA, VDDPX, and VDDRF RF power supplies.
Note: Never apply voltage to I/O pins if VDDO is not applied.
During the low power shutdown state and as long as VDDO remains applied to the device, all outputs are tristated and all digital and
analog clocks are disabled. Input voltages must remain within the limits defined for normal operation. This is done to either prevent
current draw and back loading on digital signals in the system. It also enables the device to be fully integrated in an embedded device
and take full advantage of the lowest power savings modes. If VDDC is powered up externally (not connected to VREG), VDDC
requires 750K ohms to ground during low-power shutdown. If VDDC is powered up by VREG, VDDC does not require 750K ohms to
ground because the internal main LDO has about 750 K ohms to ground when turned off.
Several signals, including the frequency reference input (XTAL_IN) and external LPO input (LPO_IN), are designed to be high-
impedance inputs that will not load down the driving signal, even if VDDO power is not applied to the chip. The other signals with back
drive prevention are RST_N, COEX_IN, PCM_SYNC, PCM_CLK, PCM_OUT, PCM_IN, UART_RTS_N, UART_CTS_N, UART_RXD,
UART_TXD, GPIO_0, GPIO_1, GPIO_4, GPIO_7, HUSB_DP, HUSB_DN, CFG_SEL, and OTP_DIS.
All other I/O signals must remain at VSS until VDDO is applied. Failing to do this can result in unreliable startup behavior.
When powered on, using REG_EN is the same as applying power to the CYW20702. The device does not have information about its
state before being powered-down.
3.7 Adaptive Frequency Hopping
The CYW20702 supports host channel classification and dynamic channel classification Adaptive Frequency Hopping (AFH)
schemes, as defined in the Bluetooth specification.
Host channel classification enables the host to set a predefined hopping map for the device to follow.
If dynamic channel classification is enabled, the device gathers link quality statistics on a channel-by-channel basis to facilitate channel
assessment and channel map selection. To provide a more accurate frequency hop map, link quality is determined using both RF and
baseband signal processing.
3.8 Collaborative Coexistence
The CYW20702 provides extensions and collaborative coexistence to the standard Bluetooth AFH for direct communication with
WLAN devices. Collaborative coexistence enables WLAN and Bluetooth to operate simultaneously in a single device. The device
supports industry-standard coexistence signaling, including 802.15.2, and supports Broadcom and third-party WLAN solutions.
Using a multitiered prioritization approach, relative priorities between data types and applications can be set. This approach maximizes
the performance-WLAN data throughput vs. voice quality vs. link performance.
A PA shutdown pin is available to allow full external control of the RF output for other types of coexistence, such as WIMAX.
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3.9 Serial Enhanced Coexistence Interface
The Serial Enhanced Coexistence Interface (Serial ECI or SECI) is a proprietary Cypress interface between Cypress WLAN devices
and Bluetooth devices. It is an optional replacement to the legacy 3- or 4-wire coexistence feature, which is also available.
The following key features are associated with the interface:
Enhanced coexistence data can be exchanged over a two-wire interface, one serial input (SECI_IN), and one serial output
(SECI_OUT). The pad configuration registers must be programmed to choose the digital I/O pins that serve the SECI_IN and
SECI_OUT function.
It supports generic UART communication between WLAN and Bluetooth devices.
To conserve power, it is disabled when inactive.
It supports automatic resynchronizaton upon waking from sleep mode.
It supports a baud rate of up to 4 Mbps.
3.9.1 SECI Advantages
The advantages of the SECI over the legacy 3-wire coexistence interface are:
Only two wires are required: SECI_IN and SECI_OUT.
Up to 48-bits of coexistence data can be exchanged.
Previous Cypress standalone Bluetooth devices such as the BCM2070 supported only a 3-wire or 4-wire coexistence interface.
Previous Cypress WLAN and Bluetooth combination devices such as the CYW4325, CYW4329, and CYW4330 support an internal
parallel enhanced coexistence interface for more efficient WLAN and Bluetooth information exchange. The SECI allows enhanced
coexistence information to be passed to a companion Cypress WLAN chip through a serial interface using fewer I/O than the 3-wire
coexistence scheme.
The 48-bits of the SECI significantly enhance WLAN and Bluetooth coexistence by sharing such information as frequencies used and
radio usage times. The exact contents of the SECI are Cypress confidential.
3.9.2 SECI I/O
The CYW20702 does not have dedicated SECI_IN or SECI_OUT pins, but the two pin functions can be mapped to the following digital
I/O: the UART, GPIO, SPI Master (or BSC), PCM, and COEX pins. Pin function mapping is controlled by the config file that is either
stored in NVRAM or downloaded directly into on-chip RAM from the host.
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CYW20702
4. Microprocessor Unit
4.1 Overview
The CYW20702 microprocessor unit runs software from the Link Control (LC) layer up to the Host Controller Interface (HCI). The
microprocessor is based on the ARM7TDMIS 32-bit RISC processor with embedded ICE-RT debug and JTAG interface units. The
microprocessor also includes 384 KB of ROM memory for program storage and boot ROM, 112 KB of RAM for data scratch-pad, and
patch RAM code.
The internal boot ROM provides flexibility during power-on reset to enable the same device to be used in various configurations,
including automatic host transport selection from SPI, USB, or UART, with or without external NVRAM. At power-up, the lower layer
protocol stack is executed from the internal ROM.
External patches can be applied to the ROM-based firmware to provide flexibility for bug fixes and features additions. These patches
can be downloaded from the host to the device through the SPI, USB, or UART transports, or using external NVRAM. The device can
also support the integration of user applications and profiles using an external serial flash memory.
4.2 NVRAM Configuration Data and Storage
4.2.1 Serial Interface
The CYW20702 includes an SPI master controller that can be used to access serial flash memory. The SPI master contains an AHB
slave interface, transmit and receive FIFOs, and the SPI core PHY logic. Data is transferred to and from the module by the system
CPU. DMA operation is not supported.
The CYW20702 supports serial flash vendors Atmel®, MXIC, and Numonyx™. The most commonly used parts from two of these
vendors are:
AT25BCM512B, manufactured by Atmel
MX25V512ZUI-20G, manufactured by MXIC
4.3 EEPROM
The CYW20702 includes a Broadcom Serial Control (BSC) master interface. The BSC interface supports low-speed and fast mode
devices and is compatible with I2C slave devices. Multiple I2C master devices and flexible wait state insertion by the master interface
or slave devices are not supported. The CYW20702 provides 400 kHz, full speed clock support.
The BSC interface is programmed by the CPU to generate the following BSC transfer types on the bus:
Read-only
Write-only
Combined read/write
Combined write-read
NVRAM may contain configuration information about the customer application, including the following:
Fractional-N information
BD_ADDR
UART baud rate
USB enumeration information
SDP service record
File system information used for code, code patches, or data
4.4 External Reset
The CYW20702 has an integrated power-on reset circuit which completely resets all circuits to a known power on state. This action
can also be driven by an external reset signal, which can be used to externally control the device, forcing it into a power-on reset state.
The RST_N signal input is an active-low signal for all versions of the CYW20702. The CYW20702 requires an external pull-up resistor
on the RST_N input. Alternatively, the RST_N input can be connected to REG_EN or driven directly by a host GPIO.
um
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CYW20702
4.5 One-Time Programmable Memory
The CYW20702 includes a One-Time Programmable (OTP) memory, allowing manufacturing customization and avoiding the need
for an on-board NVRAM.If customization is not required, then the OTP does not need to be programmed. Whether the OTP is
programmed or not, it is disabled after the boot process completes to save power.
The OTP size is 128 bytes.
The OTP is designed to store a minimal amount of information. Aside from OTP data, most user configuration information will be
downloaded into RAM after the CYW20702 boots up and is ready for host transport communication. The OTP contents are limited to:
Parameters required prior to downloading user configuration to RAM.
Parameters unique to each part and each customer (i.e., the BD_ADDR, software license key, and USB PID/VID).
The OTP memory is particularly useful in a PC design with USB transport capability because:
Some customer-specific information must be configured before enumerating the part on the USB transport.
Part or customer unique information (BD_ADDR, software license key, and USB PID/VID) do not need to be stored on the host
system.
4.5.1 Contents
The following are typical parameters programmed into the OTP memory:
BD_ADDR
Software license key
USB PID/VID
USB bus/self-powered status
Output power calibration
Frequency trimming
Initial status LED drive configuration
The OTP contents also include a static error correction table to improve yield during the programming process as well as forward error
correction codes to eliminate any long-term reliability problems. The OTP contents associated with error correction are not visible by
customers.
4.5.2 Programming
OTP memory programming takes place through a combination of Cypress software integrated with the manufacturing test software
and code embedded in CYW20702 firmware.
Programming the OTP requires a 3.3V supply. The OTP programming supply comes from the VDD_USB pin. For applications where
the OTP is most useful, such as the USB transport application for the PC market, the 3.3V is already required for USB operation from
the VDD_USB pin. The OTP power supply is allowed to be as low as 1.8 V to be able to read the contents. See Table 3 for the OTP
memory programming supply voltage requirements.
The OTP is enabled by default by setting OTP_DIS to low using an internal pull-down resistor. Leave this pin floating for a default
configuration. To disable the OTP, set the OTP_DIS pin to active high. This pin can be configured from the HW to enable or disable
OTP.
Typically it won’t be necessary to disable the OTP memory, even if it is not programmed during manufacturing. The OTP_DIS package
ball only needs to be tied to high if recommended by Cypress.
Table 3. OTP Programming Supply Voltage Requirementsa
a. The average and peak current consumptions during OTP memory programming are 20 mA and 70 mA, respectively.
Supply Minimumb
b. Contact your Cypress representative for recommended minimum and maximum supply voltages.
Typical MaximumbUnit
VDD_USB TBD TBD TBD V
:iCYPRESS' ' manna: mmmw PCM Interface S‘ave Mode ,BCLK PCM Interface Master Mode ,BCLK PCM Interface Hybr‘d Mode
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CYW20702
5. Peripheral Transport Unit
This section discusses the PCM, USB, UART, and SPI peripheral interfaces. The CYW20702 has a 1040 byte transmit and receive
fifo, which is large enough to hold the entire payload of the largest EDR BT packet (3-DH5).
5.1 PCM Interface
The CYW20702 PCM interface can connect to linear PCM codec devices in master or slave mode. In master mode, the device
generates the PCM_BCLK and PCM_SYNC signals. In slave mode, these signals are provided by another master on the PCM
interface as inputs to the device.
The device supports up to three SCO or eSCO channels through the PCM interface and each channel can be independently mapped
to any available slot in a frame.
The host can adjust the PCM interface configuration using vendor-specific HCI commands or it can be setup in the configuration file.
5.1.1 System Diagram
Figure 5 shows options for connecting the device to a PCM codec device as a master or a slave.
Figure 5. PCM Interface with Linear PCM Codec
PCM Interface Slave Mode
PCM Codec
(Master)
CYW20702
(Slave)
PCM_IN
PCM_BCLK
PCM_SYNC
PCM_OUT
PCM Interface Master Mode
PCM Codec
(Slave)
CYW20702
(Master)
PCM_IN
PCM_BCLK
PCM_SYNC
PCM_OUT
PCM Interface Hybrid Mode
PCM Codec
(Hybrid)
CYW20702
(Hybrid)
PCM_IN
PCM_BCLK
PCM_SYNC
PCM_OUT
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CYW20702
5.1.2 Slot Mapping
The device supports up to three simultaneous, full-duplex SCO or eSCO channels. These channels are time-multiplexed onto the
PCM interface using a time slotting scheme based on the audio sampling rate, as described in Ta b l e 4 .
Transmit and receive PCM data from an SCO channel is always mapped to the same slot. The PCM data output driver tri-states its
output on unused slots to allow other devices to share the same PCM interface signals. The data output driver tri-states its output
after the falling edge of the PCM clock during the last bit of the slot.
5.1.3 Wideband Speech
The CYW20702 provides support for Wideband Speech (WBS) in two ways:
Transparent mode: The host encodes WBS packets and the encoded packets are transferred over the PCM bus for SCO or eSCO
voice connections. In Transparent mode, the PCM bus is typically configured in master mode for a 4 kHz sync rate with 16-bit
samples, resulting in a 64 kbps bit rate.
On-chip SmartAudio® technology: The CYW20702 can perform Subband-Codec (SBC) encoding and decoding of linear 16 bits
at 16 kHz (256 kbps rate) transferred over the PCM bus.
5.1.4 Frame Synchronization
The device supports both short and long frame synchronization types in both master and slave configurations. In short frame synchro-
nization mode, the frame synchronization signal is an active-high pulse at the 8 kHz audio frame rate (which is a single bit period in
width) and synchronized to the rising edge of the bit clock. The PCM slave expects PCM_SYNC to be high on the falling edge of the
bit clock and the first bit of the first slot to start at the next rising edge of the clock. In the long frame synchronization mode, the frame
synchronization signal is an active-high pulse at the 8 kHz audio frame rate. However, the duration is 3-bit periods and the pulse starts
coincident with the first bit of the first slot.
5.1.5 Data Formatting
The device can be configured to generate and accept several different data formats. The device uses 13 of the 16 bits in each PCM
frame. The location and order of these 13 bits is configurable to support various data formats on the PCM interface. The remaining
three bits are ignored on the input, and may be filled with zeros, ones, a sign bit, or a programmed value on the output. The default
format is 13-bit two’s complement data, left justified, and clocked most significant bit first.
Table 4. PCM Interface Time Slotting Scheme
Audio Sample Rate Time Slotting Scheme
8 kHz The number of slots depends on the selected interface rate, as follows:
Interface rate
128
256
512
1024
2048
Slot
1
2
4
8
16
16 kHz The number of slots depends on the selected interface rate, as follows:
Interface rate
256
512
1024
2048
Slot
1
2
4
8
amass:
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CYW20702
5.2 HCI Transport Detection Configuration
The CYW20702 supports the following interface types for the HCI transport from the host:
UART (H4 and H5)
USB
SPI
Only one host interface can be active at a time. The firmware performs a transport detect function at boot-time to determine which
host is the active transport. It can auto-detect UART and USB interfaces, but the SPI interface must be selected by strapping the SCL
pin to 0.
The complete algorithm is summarized as follows:
1. Determine if SCL is pulled low. If it is, select SPI as HCI host transport.
2. Determine if any local NVRAM contains a valid configuration file. If it does and a transport configuration entry is present, select the
active transport according to entry, and then exit the transport detection routine.
3. Look for start-of-frame (SOF) on the USB interface. If it is present, select USB.
4. Look for CTS_N = 0 on the UART interface. If it is present, select UART.
5. Repeat Step 3 and Step 4 until transport is determined.
5.3 USB Interface
5.3.1 Features
The following USB interface features are supported:
USB Protocol, Revision 2.0, full-speed compliant including the hub
Optional hub compound device with up to three device cores internal to device.
Bus or self-power, dynamic configuration for the hub
Global and selective suspend and resume with remote wakeup
Bluetooth HCI
HID, DFU, UHE (proprietary method to emulate an HID device at system bootup)
Integrated detach resistor
5.3.2 Operation
Note: The USB and HCI UART interfaces cannot be used simultaneously. For designs that do not use the USB interface, VDD_USB,
HUSB_DP and HUSB_DN must be connected to ground.
The CYW20702 can be configured to boot up as either a single USB peripheral or a USB hub with several USB peripherals attached.
As a single peripheral, the host detects a single USB Bluetooth device. In Hub mode, the host detects a hub with one to three of the
ports already connected to USB devices (see Figure 6).
Figure 6. USB Compounded Device Configuration
USB Compounded Device
Hub Controller
USB Device 1
HID Keyboard
USB Device 2
HID Mouse
USB Device 3
Bluetooth
Host
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CYW20702
Depending on the desired hub mode configuration, the CYW20702 can boot up showing the three ports connected to logical USB
devices internal to the CYW20702—a generic Bluetooth device, a mouse, and a keyboard. In this mode, the mouse and keyboard
are emulated devices, since they connect to real HID devices via a Bluetooth link. The Bluetooth link to these HID devices is hidden
from the USB host. To the host, the mouse and/or keyboard appear to be directly connected to the USB port. This Cypress proprietary
architecture is called USB HID Emulation (UHE).
The USB device, configuration, and string descriptors are fully programmable, allowing manufacturers to customize the descriptors,
including vendor and product IDs, the CYW20702 uses to identify itself on the USB port. To make custom USB descriptor information
available at boot time, stored it in external NVRAM.
Despite the mode of operation (Single Peripheral or Hub), the Bluetooth device is configured to include the following interfaces:
5.3.3 USB Hub and UHE Support
The CYW20702 supports the USB hub and device model (USB, Revision 2.0, full-speed compliant). Optional mouse and keyboard
devices utilize Broadcom’s proprietary USB HID Emulation (UHE) architecture, which allows these devices appear as standalone HID
devices even though connected through a Bluetooth link.
The presence of UHE devices requires the hub to be enabled. The CYW20702 cannot appear as a single keyboard or a single mouse
device without the hub. Once either mouse or keyboard UHE device is enabled, the hub must also be enabled.
When the hub is enabled, the CYW20702 handles all standard USB functions for the following devices:
HID keyboard
HID mouse
Bluetooth
All hub and device descriptors are firmware-programmable. This USB compound device configuration (see Figure 6) supports up to
three downstream ports. This configuration can also be programmed to a single USB device core. The device automatically detects
activity on the USB interface when connected. Therefore, no special configuration is needed to select HCI as the transport.
The hub’s downstream port definition is as follows:
Port 1 USB lite device core (for HID applications)
Port 2 USB lite device core (for HID applications)
Port 3 USB full device core (for Bluetooth applications)
When operating in Hub mode, all three internal devices do not have to be enabled. Each internal USB device can be optionally enabled.
The configuration record in NVRAM determines which devices are present.
Interface 0 Contains a Control endpoint (Endpoint 0x00) for HCI commands, a Bulk In Endpoint (Endpoint 0x82) for
receiving ACL data, a Bulk Out Endpoint (Endpoint 0x02) for transmitting ACL data, and an Interrupt Endpoint
(Endpoint 0x81) for HCI events.
Interface 1 Contains Isochronous In and Out endpoints (Endpoints 0x83 and 0x03) for SCO traffic. Several alternate
Interface 1 settings are available for reserving the proper bandwidth of isochronous data (depending on the
application).
Interface 2 Contains Bulk In and Bulk Out endpoints (Endpoints 0x84 and 0x04) used for proprietary testing and
debugging purposes. These endpoints can be ignored during normal operation.
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5.4 UART Interface
The UART physical interface is a standard, 4-wire interface (RX, TX, RTS, CTS) with adjustable baud rates from 9600 bps to 4.0
Mbps. The interface features an automatic baud rate detection capability that returns a baud rate selection. Alternatively, the baud
rate can be selected via a vendor-specific UART HCI command. The interface supports Bluetooth UART HCI (H4) specifications. The
default baud rate for H4 is 115.2 Kbaud.
The following baud rates are supported:
9600
14400
19200
28800
38400
57600
115200
230400
460800
921600
144444
150000
2000000
3000000
3250000
3692000
4000000
Normally, the UART baud rate is set by a configuration record downloaded after reset or by automatic baud rate detection. The host
does not need to adjust the baud rate. Support for changing the baud rate during normal HCI UART operation is provided through a
vendor-specific command.
The CYW20702 UART operates with the host UART correctly, provided the combined baud rate error of the two devices is within ±2%.
5.4.1 HCI 3-Wire Transport (UART H5)
The CYW20702 supports H5 UART transport for serial UART communications. H5 reduces the number of signal lines required by
eliminating CTS and RTS, when compared to H4.
H5 requires the use of an external LPO. CTS must be pulled low.
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5.5 SPI
The CYW20702 supports a slave SPI HCI transport with an input clock range of up to 16 MHz. Higher clock rates may be possible.
The physical interface between the SPI master and the CYW20702 consists of the four SPI signals (SPI_CSB, SPI_CLK, SPI_SI,
and SPI_SO) and one interrupt signal (SPI_INT). The 20702 internal SPI transport signals are multiplexed to the UART pins as fol-
lows: 20702-pin F6 --> UART_TXD (MISO); 20702-pin G7 --> UART_CTS (SPI_CLK); 20702-pin E5 --> UART_RTS (CS); and
20702-pin D7 --> UART_RXD (MOSI). The GPIO_1 is used for the SPI interrupt signal (SPI_INT). The CYW20702 can be config-
ured to accept active-low or active-high polarity on the SPI_CSB chip select signal. It can also be configured to drive an active-low or
active-high SPI_INT interrupt signal. Bit ordering on the SPI_SI and SPI_SO data lines can be configured as either little-endian or
big-endian. Additionally, proprietary sleep mode, half-duplex handshaking is implemented between the SPI master and the
CYW20702.
SPI_INT is required to negotiate the start of a transaction. The SPI interface does not require flow control in the middle of a payload.
The FIFO is large enough to handle the largest packet size. Only the SPI master can stop the flow of bytes on the data lines, since it
controls SPI_CSB and SPI_CLK. Flow control should be implemented in higher layer protocols.
Note: The 20702 pins E7, F7, G8, and E8 are used for SPI serial flash access. When the SPI transport detection is used, the serial
flash interface may not be used because SCL must be tied low.
5.6 Simultaneous UART Transport and Bridging
The CYW20702 supports UART or USB interfaces that can function as the host controller interface (HCI). Typically, a customer
application would choose one of the two interfaces and the other would be idle. The CYW20702 allows the UART transport to operate
simultaneously with the USB. To operate this way, the assumption is that the USB would function as the primary host transport, while
the UART would function as a secondary communication channel that can operate at the same time. This can enable the following
applications:
Bridging primary HCI transport traffic to another device via the UART
Generic communication to an external device for a vendor-supported application via the UART
Simultaneous UART transport and bridging is enabled by including:
Two dedicated 64-byte FIFOs, one for the input and one for the output
Additional DMA channels
Additional vendor-supported commands over the HCI transport
aCYPRESS' ' manna: mlanRRaw
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CYW20702
6. Frequency References
The CYW20702 uses two different frequency references for normal and low-power operational modes. An external crystal or
frequency reference driven by a Temperature Compensated Crystal Oscillator (TCXO) signal is used to generate the radio frequencies
and normal operation clocking. Either an external 32.768 kHz or fully integrated internal Low-Power Oscillator (LPO) is used for low-
power mode timing.
6.1 Crystal Interface and Clock Generation
The CYW20702 uses a fractional-N synthesizer to generate the radio frequencies, clocks, and data/packet timing, enabling it to
operate from any of a multitude of frequency sources. The source can be external, such as a TCXO, or a crystal interfaced directly to
the device.
The default frequency reference setting is for a 20 MHz crystal or TCXO. The signal characteristics for the crystal interface are listed
in Tab l e 5.
Table 5. Crystal Interface Signal Characteristics
Parameter Crystal External Frequency Reference Units
Acceptable frequencies 12–52 MHz in 2 ppma steps
a. The frequency step size is approximately 80 Hz resolution.
12–52 MHz in 2 ppma steps
Crystal load capacitance 12 (typical) N/A pF
ESR 60 (max)
Power dissipation 200 (max) μW
Input signal amplitude N/A 400 to 2000
2000 to 3300 (requires a 10 pF DC
blocking capacitor to attenuate the
signal)
mVp-p
Signal type N/A Square-wave or sine-wave
Input impedance N/A 1
2
M
pF
Phase noise
@ 1 kHz
@ 10 kHz
@ 100 kHz
@ 1 MHz
N/A
N/A
N/A
N/A
N/A
< –120b
< –131b
< –136b
< –136b
b. With a 26 MHz reference clock. For a 13 MHz clock, subtract 6 dB. For a 52 MHz clock, add 6 dB.
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Auto-detection frequencies when
using external LPOc
c. Auto-detection of the frequency requires the crystal or external frequency reference to have less than ±50 ppm of variation and also requires
an external LPO frequency which has less than ±250 ppm of variation at the time of detection.
12, 13, 14.4, 15.36, 16.2, 16.8, 18,
19.2, 19.44, 19.68, 19.8, 20, 24, 26,
33.6, 37.4, and 38.4
12, 13, 14.4, 15.36, 16.2, 16.8, 18,
19.2, 19.44, 19.68, 19.8, 20, 24, 26,
33.6, 37.4, and 38.4
MHz
Tolerance without frequency trimmingd
d. AT-Cut crystal or TXCO recommended.
±20 ±20 ppm
Initial frequency tolerance trimming
range
±50 ±50 ppm
-%I| ' 4H—
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CYW20702
6.2 Crystal Oscillator
The CYW20702 can use an external crystal to provide a frequency reference. The recommended configuration for the crystal oscillator,
including all external components, is shown in Figure 7.
Figure 7. Recommended Oscillator Configuration
6.3 External Frequency Reference
An external frequency reference, such as VDD_RF, collectively refers to several RF power supplies generated by a TCXO signal that
may be directly connected to the crystal input pin on the CYW20702, as shown in Figure 8. The external frequency reference input is
designed to not change loading on the TCXO when the CYW20702 is powered up or powered down.
When using the CYW20702 with the TXCO OR gate option, GPIO 6 must be driven active high or active low. Excessive leakage
current results if GPIO6 is allowed to float.
Figure 8. Recommended TCXO Connection
6.3.1 TCXO Clock Request Support
If the application utilizes an external TCXO as a clock reference, the CYW20702 provides a clock request output to allow the system
to power off the TCXO when not in use.
0 ~ 18 pF*
0 ~ 18 pF*
XIN
XOUT
Crystal
Oscillator
*Capacitor value range depends
on the manufacturer of the XTAL
as well as board layout.
No Connection
TCXO XIN
XOUT
10–1000 pF*
* Recommended value is 100 pF.
Higher values produce a longer startup time.
Lower values have greater isolation.
Larger values help small signal swings.
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6.4 Frequency Selection
Any frequency within the range specified for the crystal and TCXO reference can be used. These frequencies include standard handset
reference frequencies (12, 13, 14.4, 15.36, 16.2, 16.8, 18, 19.2, 19.44, 19.68, 19.8, 20, 24, 26, 33.6, 37.4, and 38.4 MHz) and any
frequency between these reference frequencies, as desired by the system designer. Since bit timing is derived from the reference
frequency, the CYW20702 must have the reference frequency set correctly in order for any of the USB, UART, and PCM interfaces
to function properly.
The CYW20702 reference frequency can be set in one of the following ways.
Use the default 20 MHz frequency by leaving the CFG_SEL pin unconnected or by strapping it high. The CFG_SEL pin is internally
pulled up in the CYW20702.
Use the 26 MHz option by setting CFG_SEL low.
Designate the reference frequency in external NVRAM
Auto-detect the standard handset reference frequencies using an external LPO clock
For PC and embedded applications where there typically won’t be an LPO clock, if autobaud is enabled, the CYW20702 will use XTAL
to sync up with the UART, thus allowing a user to download a firmware configuration without having to make a crystal frequency
assumption. Alternatively, the CYW20702 will upload the firmware configuration from an attached NVRAM (if one is attached) and
use it to make a crystal frequency assumption. Finally, if neither of the above is true, then the CYW20702 will look at the status of the
CFG_SEL pin and decide whether to choose 20 or 26 MHz. Autobaud is only valid for UART applications.
The 20 MHz choice is only a default in the sense that if the pin is left floating, it will be pulled up internally to support the 20 MHz option.
If the application requires a frequency other than the default, the value can be stored in an external NVRAM. Programming the
reference frequency in NVRAM provides the maximum flexibility in the selection of the reference frequency, since any frequency within
the specified range for crystal and external frequency reference can be used. During power-on reset (POR), the device downloads
the parameter settings stored in NVRAM, which can be programmed to include the reference frequency and frequency trim values.
Typically, this is how a PC Bluetooth application is configured.
For applications such as handsets and portable smart communication devices, where the reference frequency is one of the standard
frequencies commonly used, the CYW20702 automatically detects the reference frequency and programs itself to the correct
reference frequency. In order for auto-frequency detection to work properly, the CYW20702 must have a valid and stable 32.768 kHz
external LPO clock present during POR. This eliminates the need for NVRAM in applications where the external LPO clock is available
and an external NVRAM is typically not used.
6.5 Frequency Trimming
The CYW20702 uses a fractional-N synthesizer to digitally fine-tune the frequency reference input to within ±2 ppm tuning accuracy.
This trimming function can be applied to either the crystal or an external frequency source such as a TCXO. Unlike the typical crystal-
trimming methods used, the CYW20702 changes the frequency using a fully digital implementation and is much more stable and
unaffected by crystal characteristics or temperature. Input impedance and loading characteristics remain unchanged on the TCXO or
crystal during the trimming process and are unaffected by process and temperature variations.
The option to use or not use frequency trimming is based on the system designer’s cost trade-off between bill-of-materials (BOM) cost
of the crystal and the added manufacturing cost associated with frequency trimming. The frequency trimming value can either be
stored in the host and written to the CYW20702 as a vendor-specific HCI command or stored in NVRAM and subsequently recalled
during POR.
Frequency trimming is not a substitute for the poor use of tuning capacitors at an crystal oscillator (XTAL). Occasionally, trimming can
help alleviate hardware changes.
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CYW20702
6.6 LPO Clock Interface
The LPO clock is the second frequency reference that the CYW20702 uses to provide low-power mode timing for sniff. The LPO clock
can be provided to the device externally, from a 32.768 kHz source or the CYW20702 can operate using the internal LPO clock.
The LPO can be internally driven from the main clock. However, sleep current will be impacted.
The accuracy of the internal LPO limits the maximum sniff intervals.
Table 6. External LPO Signal Requirements
Parameter External LPO Clock Units
Nominal input frequency 32.768 kHz
Frequency accuracy ±250 ppm
Input signal amplitude 200 to 3600 mVp-p
Signal type Square-wave or sine-wave
Input impedance (when power is applied or power is off) >100
<5
k
pF
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7. Pin-out and Signal Descriptions
7.1 Pin Descriptions
Table 7. CYW20702 Signal Descriptions
Signal WFBGA Pin
(50-Ball) I/O Power
Domain Description
Radio
RES F3 O VDD_RF External calibration resistor,
15 k @ 1%
RFP D1 I/O VDD_RF RF I/O antenna port
XIN G2 I VDD_RF Crystal or reference input
XOUT G3 O VDD_RF Crystal oscillator output
Analog
LPO_IN B4 I VDDRF External LPO input
Voltage Regulators
REG_EN B2 I VDDO HV LDO and main enable
VBAT A3 I N/A HV LDO input
VREGHV A2 I/O N/A HV LDO output: main LDO input
VREG A1 O N/A Main LDO output
Straps
CFG_SEL B8 I/O VDDO This pin is floating for the 20 MHz XTAL option and tied to
ground for the 26 MHz XTAL option.
OTP_DIS B7 I/O VDDO OTP disable pin. By default, leave this pin floating.
RST_N A4 I VDDO Active-low reset input
TM0 I VDDO Clock request polarity select
TM1 I VDDO Internally connected to ground
TM2 E3 I VDDO Reserved: connect to ground.
Digital I/O
GPIO_0 B5 I/O VDDO GPIO/BT_WAKE
GPIO_1 B3 I/O VDDO GPIO/HOST_WAKE. It is also used for the SPI interrupt
signal (SPI_INT) when used as SPI transport.
GPIO_3 D8 I/O VDDO GPIO/LINK_IND
Can be configured for active high or low as well as open
drain.
GPIO_4 I/O VDDO GPIO
GPIO_5 F4 I/O VDDO GPIO/CLK_REQ
TCXO-OR Function Out available on some packages.
See Section 11. Ordering Information.
GPIO_6 E4 I/O VDDO GPIO
TCXO-OR Function In available on some packages. See
Section 11. Ordering Information.
GPIO_7 C7 I/O VDDO DETATCH/CARD_DETECT
UART_RXD D7 I/O VDDO UART receive data. Also mapped to the SPI signal MOSI.
UART_TXD F6 I/O VDDO UART transmit data. Also mapped to the SPI signal MISO.
GPIO_0 B5 I/O VDDO GPIO/BT_WAKE
GPIO_1 B3 I/O VDDO GPIO/HOST_WAKE. It is also used for the SPI interrupt
signal (SPI_INT) when used as SPI transport.
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CYW20702
UART_RTS_N E5 I/O VDDO UART request to send output. Also mapped to the SPI
signal CS.
UART_CTS_N G7 I/O VDDO UART clear to send input. Also mapped to the SPI signal
SPI_CLK.
SCL F7 I/O VDDO BSC clock. Also used for serial flash access (MISO).
SDA E7 I/O VDDO BSC data. Also used for serial flash access (MOSI).
SPIM_CLK E8 I/O VDDO Serial flash SPI clock
SPIM_CS_N G8 I/O VDDO Serial flash active-low chip select
PCM_IN G6 I/O VDDO PCM/I2S data input
PCM_OUT F5 I/O VDDO PCM/I2S data output
PCM_CLK G5 I/O VDDO PCM/I2S clock
PCM_SYNC C4 I/O VDDO PCM sync/I2S word select
COEX_IN B6 I/O VDDO Coexistence input
USB
HUSB_DP A8 I/O VDD_USB USB hub. If not used, connect to GND.
HUSB_DN A7 I/O VDD_USB If not used, connect to GND.
Supplies
VDDIF B1 I N/A Radio IF PLL supply
VDDTF C1 I N/A Radio PA supply
VDDLNA E1 I N/A Radio LNA supply
VDDRF F1 I N/A Radio supply
VDDPX G1 I N/A Radio RF PLL supply
VDDC A6 I N/A Core logic supply
VDDC F8 I N/A Core logic supply
VDDC I N/A Core logic supply
VDDO G4 I N/A Digital I/O supply voltage
VDDO A5 I N/A Digital I/O supply voltage
VDDO E6 I N/A Digital I/O supply voltage
VDD_USB C8 I N/A USB transceiver supply voltage. If not used, connect to
GND.
VSS C2 – N/A Ground
VSS D2 – N/A Ground
VSS F2 – N/A Ground
VSS D3 – N/A Ground
Table 7. CYW20702 Signal Descriptions (Cont.)
Signal WFBGA Pin
(50-Ball) I/O Power
Domain Description
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8. Ball Grid Arrays
Figure 9 shows the top view of the following array:
50-ball 4.5 x 4 x 0.8 mm (WFBGA)
Figure 9. 4.5 x 4 x 0.8 mm (WFBGA) Arra
y
Table 8. Ball-Out for the 50-Ball WFBGA
12345678
AVREG VREGHV VBAT RST_N VDDO VDDC HUSB_DN HUSB_DP
BVDDIF REG_EN GPIO_1 LPO_IN GPIO_0 COEX_IN OTP_DIS CFG_SEL
CVDDTF VSS – PCM_SYNC – VSS GPIO_7 VDD_USB
DRFP VSS VSS – UART_RXD GPIO_3
EVDDLNA – TM2 GPIO_6 UART_RTS_
N
VDDO SDA SPIM_CLK
FVDDRF VSS RES GPIO_5 PCM_OUT UART_TXD SCL VDDC
GVDDPX XIN XOUT VDDO PCM_CLK PCM_IN UART_CTS_
N
SPIM_CS_N
G
F
E
D
C
B
A
12345678
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9. Electrical Characteristics
Note: All voltages listed in Table 9 are referenced to VDD.
Table 9. Absolute Maximum Voltages
Rating Symbol Minimum Typical Maximum Unit
DC supply voltage for RF VDD_RF a
a. VDD_RF collectively refers to the VDDIF, VDDLNA, VDDPX, and VDDRF RF power supplies.
– 1.221.32V
DC supply voltage for core VDDC 1.22 1.32 V
DC supply voltage for I/O VDDO b
b. If VDDO is not applied, voltage should never be applied to any digital I/O pins (I/O pins should never be driven or pulled high). The list of digital
I/O pins includes the following (these pins are listed in Section 7. Pin-out and Signal Descriptions with VDDO shown as their power
domain):
GPIO[3], GPIO[5], GPIO[6]
SCL, SDA
N_MODE
SPIM_CS_N, SPIM_CLK
–1.83.6V
DC supply VDDTF 1.12 3.3 c
c. VDDTF for Class 2 must be connected to VREG (main LDO output). VDDTF for Class 1 must be connected to VREGHV (HV LDO output) or
an external voltage source. Refer to the Cypress compatibility guide for configuration details.
V
Voltage on input or output pin VIMAX, VIMIN VSS – 0.3 VDDO + 0.3 V
Storage temperature range TSTG 40 125 °C
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Table 10. Power Supply
Parameter Symbol Minimum Typical Maximum Unit
DC supply voltage for RF VDD_RF a
a. VDD_RF collectively refers to the VDDIF, VDDLNA, VDDPX, VDDLNA, VDDRF RF power supplies.
1.159 1.22 1.281 V
DC supply noise for RF, from 100 kHz to 1 MHz VDD_RF b
b. Overall performance defined using integrated regulation.
150 μV rms
DC supply voltage for core VDDC 1.159 1.22 1.281 V
DC supply voltage for I/O VDDO 1.7 3.6 V
DC supply voltage for USB VDD_USB 3.0 3.3 3.6 V
DC supply VDDTF c
c. VDDTF for Class 2 must be connected to VREG (main LDO output). VDDTF for Class 1 must be connected to VREGHV (HV LDO output) or
an external voltage source. Refer to the Cypress compatibility guide for configuration details. VDDTF requires a capacitor to ground. The value
of the capacitor must be tuned to ensure optimal RF RX sensitivity. Typical 10 pF for BGA packages and 6.2 pF for wafer package. The value
may depend on board layout.
1.12 – 3.0d
d. Can be 3.3V if the output power is limited to 9 dBm.
V
Table 11. High-Voltage Regulator (HV LDO) Electrical Specifications
Parameter Minimum Typical Maximum Unit
Input voltage 2.3 5.5 V
Output voltage 1.8 3.3 V
Max current load 95 mA
Load capacitance 1 10 μF
Load capacitor ESR 0.01 2
PSRR 20 – 40 dB
Turn-on time (Cload = 2.2 μF) 200 μs
Dropout voltage 200 mV
Table 12. Main Regulator (Main LDO) Electrical Specifications
Parameter Minimum Typical Maximum Unit
Input voltage 1.63 3.63 V
Output voltage 1.159 1.22 1.281 V
Load current 60 mA
Load capacitance 1 2.2 μF
ESR 0.1 0.5
Turn-on time 300 μs
PSRR 15 – dB
Dropout voltage 200 mV
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Note: By default, the drive strength settings specified in Table 1 3 are for 3.3V. To achieve the required drive strength for a VDDIO of
2.5V or 1.8V, contact a Cypress technical support representative (see “IoT Resources” for contact information).
Table 13. Digital I/O Characteristics
Characteristics Symbol Minimum Typical Maximum Unit
Input low voltage (VDDO = 3.3V) VIL ––0.8V
Input high voltage (VDDO = 3.3V) VIH 2.0 – V
Input low voltage (VDDO = 1.8V) VIL ––0.6V
Input high voltage (VDDO = 1.8V) VIH 1.1 – V
Output low voltage VOL ––0.4V
Output high voltage VOH VDDO – 0.4V V
Input low current IIL ––1.0μA
Input high current IIH ––1.0μA
Output low current (VDDO = 3.3V, VOL = 0.4V) IOL ––3.0mA
Output high current (VDDO = 3.3V, VOH = 2.9V) IOH ––3.0mA
Output low current (VDDO = 1.8V, VOL = 0.4V) IOL ––3.0mA
Output high current (VDDO = 1.8V, VOH = 1.4V) IOH ––3.0mA
Input capacitance CIN ––0.4pF
Note: GPIO_3/LINK_IND has a 10 mA IOH or IOL driver current that can be used for an LED.
Table 14. Pad I/O Characteristicsa
a. All digital I/O internal pull-up or pull-down values are around 60 k. This does not include the USB signals.
Pad Name Pull-Up/Pull-Down Fail-Safe
COEX_IN Y Y
PCM_CLK Y Y
PCM_OUT Y Y
PCM_IN Y Y
PCM_SYNC Y Y
UART_RTS_N Y Y
UART_CTS_N Y Y
UART_RXD Y Y
UART_TXD Y Y
GPIO_0 Y Y
GPIO_1 Y Y
GPIO_4 Y Y
GPIO_7 Y Y
RST_N N/A Y
USB D+ N/A Y
USB D- N/A Y
CFG_SEL Y N
OTP_DIS Y N
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Table 15. USB Interface Level
Parameter Symbol Minimum Typical Maximum Unit
I/O supply voltage VDD_USB 3.0 3.6 V
Supply current Icchpf 500 mA
Input high voltage (driven) Vih 2.0 V
Input high voltage (floating) Vihz 2.7 3.6 V
Input low voltage Vil 0.8 V
Differential input sensitivity Vdi 0.2 V
Differential common-mode range Vcm 0.8 2.5 V
Output low voltage Vol 0.0 0.3 V
Output high voltage (driven) Voh 2.8 3.6 V
Output signal crossover voltage Vcrs 1.3 2.0 V
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Table 16. Current ConsumptionClass 1(10 dBm)
Operational Mode Conditions Typical Units
Receive (1 Mbps) Current level during receive of a basic rate packet 31 mA
Transmit (1 Mbps) Current level during transmit of a basic rate packet, GFSK output power =
10 dBm
65 mA
Receive (EDR) Current level during receive of a 2 or 3 Mbps rate packet 32 mA
Transmit (EDR) Current level during transmit of a 2 or 3 Mbps rate packet, GFSK output
power = 10 dBm
59 mA
DM1/DH1 Average current during basic rate max throughput connection
which includes only this packet type.
45 mA
DM3/DH3 Average current during basic rate max throughput connection
which includes only this packet type.
46 mA
DM5/DH5 Average current during max basic rate throughput connection
which includes only this packet type.
48 mA
HV1 Average current during SCO voice connection consisting of only
this packet type. ACL channel is in 500 ms sniff.
38 mA
HV2 Average current during SCO voice connection consisting of only
this packet type. ACL channel is in 500 ms sniff.
23 mA
HV3 Average current during SCO voice connection consisting of only
this packet type. ACL channel is in 500 ms sniff.
17 mA
HCI only active Average current when waiting for HCI command UART, USB, or SPI trans-
ports.
4.8 mA
Sleep UART transport active, external LPO clock available. 55 μA
Sleep, HV Reg Bypass UART transport active, external LPO clock available, HV LDO
disabled and in bypass mode.
45 μA
Inquiry Scan (1.28 sec) Periodic scan rate is 1.28 sec. 350 μA
Page Scan (R1) Periodic scan rate is R1 (1.28 sec). 350 μA
Inquiry Scan + Page Scan
(R1)
Both inquiry and page scans are interlaced together at 1.28 sec periodic scan
rate.
630 μA
Sniff master (500 ms) Attempt and timeout parameters set to 4. Quality connection
which rarely requires more than minimum packet exchange.
175 μA
Sniff slave (500 ms) Attempt and timeout parameters set to 4. Quality connection
which rarely requires more than minimum packet exchange. Sniff master
follows optimal sniff protocol of CYW20702 master.
160 μA
Sniff (500 ms) + Inquiry/
Page Scan (R1)
Same conditions as Sniff master and Page Scan (R1). Scan maybe either
Inquiry Scan or Page Scan at 1.28 sec periodic scan rate.
455 μA
Sniff (500ms) + Inquiry Scan
+ Page Scan (R1)
Same conditions as Sniff master and Inquiry Scan + Page Scan. 760 μA
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Table 17. Current ConsumptionClass 2 (3 dBm)
Operational Mode Conditions Typical Units
Receive (1 Mbps) Current level during receive of a basic rate packet 31 mA
Transmit (1 Mbps) Current level during transmit of a basic rate packet, GFSK output power = 3
dBm
44 mA
Receive (EDR) Current level during receive of a 2 or 3 Mbps rate packet 32 mA
Transmit (EDR) Current level during transmit of a 2 or 3 Mbps rate packet, GFSK output power
= 3 dBm
41 mA
DM1/DH1 Average current during basic rate max throughput connection
which includes only this packet type.
35 mA
DM3/DH3 Average current during basic rate max throughput connection
which includes only this packet type.
36 mA
DM5/DH5 Average current during max basic rate throughput connection
which includes only this packet type.
37 mA
HV1 Average current during SCO voice connection consisting of only
this packet type. ACL channel is in 500 ms sniff.
28 mA
HV2 Average current during SCO voice connection consisting of only
this packet type. ACL channel is in 500 ms sniff.
17 mA
HV3 Average current during SCO voice connection consisting of only
this packet type. ACL channel is in 500 ms sniff.
13 mA
HCI only active Average current when waiting for HCI command UART, USB, or SPI trans-
ports.
4.8 mA
Sleep UART transport active, external LPO clock available. 55 μA
Sleep, HV Reg Bypass UART transport active, external LPO clock available, HV LDO
disabled and in bypass mode.
45 μA
Inquiry Scan (1.28 sec) Periodic scan rate is 1.28 sec. 350 μA
Page Scan (R1) Periodic scan rate is R1 (1.28 sec). 350 μA
Inquiry Scan + Page Scan
(R1)
Both inquiry and page scans are interlaced together at 1.28 sec periodic scan
rate.
630 μA
Sniff master (500 ms) Attempt and timeout parameters set to 4. Quality connection
which rarely requires more than minimum packet exchange.
145 μA
Sniff slave (500 ms) Attempt and timeout parameters set to 4. Quality connection
which rarely requires more than minimum packet exchange. Sniff master
follows optimal sniff protocol of CYW20702 master.
135 μA
Sniff (500 ms) + Inquiry/
Page Scan (R1)
Same conditions as Sniff master and Page Scan (R1). Scan maybe either
Inquiry Scan or Page Scan at 1.28 sec periodic scan rate.
425 μA
Sniff (500 ms) + Inquiry
Scan + Page Scan (R1)
Same conditions as Sniff master and Inquiry Scan + Page Scan. 730 μA
Table 18. Operating Conditions
Parameter Conditions Minimum Typical Maximum Unit
Temperature Commercial –30.0 – 85 °C
Power supply RF, Core 1.14 1.22 1.32 V
PA supply (VDDTF) Reduced power level 1.14 3.0 3.3 V
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9.1 RF Specifications
Table 19. Receiver RF Specificationsa, b
Parameter Conditions Minimum Typical cMaximum Unit
General
Frequency range 2402 2480 MHz
RX sensitivity dGFSK, 0.1% BER, 1 Mbps –89 –85 dBm
LE GFSK, 0.1% BER, 1 Mbps –92 –88 dBm
/4-DQPSK, 0.01% BER, 2 Mbps –91 –85 dBm
8-DPSK, 0.01% BER, 3 Mbps –86 –81 dBm
Maximum input GFSK, 1 Mbps –20 dBm
Maximum input /4-DQPSK, 8-DPSK, 2/3 Mbps –20 dBm
Interference Performance
C/I cochannel GFSK, 0.1% BER 11 dB
C/I 1 MHz adjacent channel GFSK, 0.1% BER 0 dB
C/I 2 MHz adjacent channel GFSK, 0.1% BER –30.0 dB
C/I > 3 MHz adjacent channel GFSK, 0.1% BER –40.0 dB
C/I image channel GFSK, 0.1% BER –9.0 dB
C/I 1 MHz adjacent to image channel GFSK, 0.1% BER –20.0 dB
C/I cochannel /4-DQPSK, 0.1% BER 13 dB
C/I 1 MHz adjacent channel /4-DQPSK, 0.1% BER 0 dB
C/I 2 MHz adjacent channel /4-DQPSK, 0.1% BER –30.0 dB
C/I > 3 MHz adjacent channel 8-DPSK, 0.1% BER –40.0 dB
C/I image channel /4-DQPSK, 0.1% BER –7.0 dB
C/I 1 MHz adjacent to image channel /4-DQPSK, 0.1% BER –20.0 dB
C/I cochannel 8-DPSK, 0.1% BER 21 dB
C/I 1 MHz adjacent channel 8-DPSK, 0.1% BER 5 dB
C/I 2 MHz adjacent channel 8-DPSK, 0.1% BER –25.0 dB
C/I > 3 MHz adjacent channel 8-DPSK, 0.1% BER –33.0 dB
C/I Image channel 8-DPSK, 0.1% BER 0 dB
C/I 1 MHz adjacent to image channel 8-DPSK, 0.1% BER –13.0 dB
Out-of-Band Blocking Performance (CW) e
30 MHz–2000 MHz 0.1% BER –10.0 dBm
2000–2399 MHz 0.1% BER –27 dBm
2498–3000 MHz 0.1% BER –27 dBm
3000 MHz–12.75 GHz 0.1% BER –10.0 dBm
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Out-of-Band Blocking Performance, Modulated Interferer
776–764 MHz CDMA –15 dBm
824–849 MHz CDMA –15 dBm
1850–1910 MHz CDMA –20 dBm
824–849 MHz EDGE/GSM –10 dBm
880–915 MHz EDGE/GSM –10 dBm
1710–1785 MHz EDGE/GSM –15 dBm
1850–1910 MHz EDGE/GSM –15 dBm
1850–1910 MHz WCDMA –25 dBm
1920–1980 MHz WCDMA –25 dBm
Intermodulation Performance f
BT, Df = 5 MHz –39.0 dBm
Spurious Emissions g
30 MHz to 1 GHz –57 dBm
1 GHz to 12.75 GHz –47 dBm
65 MHz to 108 MHz FM Rx –145 dBm/Hz
746 MHz to 764 MHz CDMA –145 dBm/Hz
851–894 MHz CDMA –145 dBm/Hz
925–960 MHz EDGE/GSM –145 dBm/Hz
1805–1880 MHz EDGE/GSM –145 dBm/Hz
1930–1990 MHz PCS –145 dBm/Hz
2110–2170 MHz WCDMA –145 dBm/Hz
a. All specifications are single ended. Unused inputs are left open.
b. All specifications, except typical, are for industrial temperatures. For details see Ta b le 18 .
c. Typical operating conditions are 1.22V operating voltage and 25°C ambient temperature.
d. The receiver sensitivity is measured at BER of 0.1% on the device interface.
e. Meets this specification using front-end band pass filter.
f. f0 = -64 dBm Bluetooth-modulated signal, f1 = –39 dBm sine wave, f2 = –39 dBm Bluetooth-modulated signal, f0 = 2f1 – f2, and |f2 –
f1| = n*1 MHz, where n is 3, 4, or 5. For the typical case, n = 5.
g. Includes baseband radiated emissions.
Table 19. Receiver RF Specificationsa, b (Cont.)
Parameter Conditions Minimum Typical cMaximum Unit
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Table 20. Transmitter RF Specifications a, b
Parameter Conditions Minimum Typical Maximum Unit
General
Frequency range 2402 2480 MHz
Class1: GFSK Tx power c–6.510dBm
Class1: EDR Tx power d– 4.58–dBm
Class 2: GFSK Tx power –1.5 2 dBm
Power control step 246dB
Modulation Accuracy
/4-DQPSK Frequency Stability –10 10 kHz
/4-DQPSK RMS DEVM 20 %
/4-QPSK Peak DEVM 35 %
/4-DQPSK 99% DEVM 30 %
8-DPSK frequency stability –10 10 kHz
8-DPSK RMS DEVM 13 %
8-DPSK Peak DEVM 25 %
8-DPSK 99% DEVM 20 %
In-Band Spurious Emissions
+500 kHz –20 dBc
1.0 MHz < |M – N| < 1.5 MHz –26 dBc
1.5 MHz < |M – N| < 2.5 MHz –20 dBm
|M – N| > 2.5 MHz –40 dBm
Out-of-Band Spurious Emissions
30 MHz to 1 GHz –36.0 edBm
1 GHz to 12.75 GHz –30.0 e, f dBm
1.8 GHz to 1.9 GHz –47.0 dBm
5.15 GHz to 5.3 GHz –47.0 dBm
GPS Band Noise Emission (without a front-end band pass filter)
1572.92 MHz to 1577.92 MHz –150 –127 dBm/Hz
Out-of-Band Noise Emissions (without a front-end band pass filter)
65 MHz to 108 MHz FM Rx –145 dBm/Hz
746 MHz to 764 MHz CDMA –145 dBm/Hz
869 MHz to 960 MHz CDMA –145 dBm/Hz
925 MHz to 960 MHz EDGE/GSM –145 dBm/Hz
1805 MHz to 1880 MHz EDGE/GSM –145 dBm/Hz
1930 MHz to 1990 MHz PCS –145 dBm/Hz
2110 MHz to 2170 MHz WCDMA –145 dBm/Hz
a. All specifications are for industrial temperatures. For details, see Table 18.
b. All specifications are single-ended. Unused input are left open.
c. +10 dBm output for GFSK measured with VDDTF = 2.9 V.
d. +8 dBm output for EDR measured with VDDTF = 2.9 V.
e. Maximum value is the value required for Bluetooth qualification.
f. Meets this spec using a front-end bandpass filter.
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CYW20702
9.2 Timing and AC Characteristics
In this section, use the numbers listed in the reference column to interpret the timing diagrams.
9.2.1 Startup Timing
There are two basic startup scenarios. In one scenario, the chip startup and firmware boot is held off while the RST_N pin is asserted.
In the second scenario, the chip startup and firmware boot is directly triggered by the chip power-up. In this case, an internal power-
on reset (POR) is held for a few ms, after which the chip commences startup.
The global reset signal in the CYW20702 is a logical OR (actually a wired AND, since the signals are active low) of the RST_N input
and the internal POR signals. The last signal to be released determines the time at which the chip is released from reset. The POR
is typically asserted for 3 ms after VDDC crosses the 0.8V threshold, but it may be as soon as 1.5 ms after this event.
After the chip is released from reset, both startup scenarios follow the same sequence, as follows:
1. For the CYW20702A1KWFBG part: After approximately 120 μs, the CLK_REQ (GPIO_5) signal is asserted.
2. The chip remains in sleep state for a minimum of 4.2 ms.
3. If present, the crystal (or TCXO) and LPO clocks must be oscillating by the end of the 4.2 ms period.
If a TCXO clock is not in the system, a crystal is assumed to be present at the XIN and XOUT pins. If an LPO clock is not used, the
firmware will detect the absence of a clock at the LPO_IN lead and use the internal LPO clock instead.
The following two figures illustrate two startup timing scenarios.
Figure 10. Startup Timing from RST_N
VDDIO, VBAT,REG_EN
VDDC > 0.8V
tmax = 4.2 ms
VREG
RST_N
GPIO5 (CLK_REQ)
XTAL/TCXO
LPO
t =64 to 171
μs
t = 800
μs
trampmax = 200
μs
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Figure 11. Startup Timing from Power-on Reset
9.2.2 USB Full-Speed Timing
Tab l e 2 1 through Table 26 shows timing specifications for VDD_USB = 3.3V, VSS = 0V, and TA = 0 to 85oC operating temperature
range.
Figure 12. USB Full-Speed Timing
Table 21. USB Full-Speed Timing Specifications
Reference Characteristics Minimum Maximum Unit
1 Transition rise time 4 20 ns
2 Transition fall time 4 20 ns
3 Rise/fall timing matching 90 111 %
4 Full-speed data rate 12 – 0.25% 12 + 0.25% Mb/s
VDDIO, VBAT,REG_EN
VDDC > 0.8V
tmax = 4.2 ms
GPIO5 (CLK_REQ)
tmin= 1.5 ms
VREG
XTAL/TCXO
LPO
Internal POR
trampmax = 200
μs
t = 800
μs
t = 64 to 171
μs
D+
D-
VCRS
90% 90%
10%10%
12
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9.2.3 UART Timing
Figure 13. UART Timing
9.2.4 PCM Interface Timing
Table 22. UART Timing Specifications
Reference Characteristics Minimum Maximum Unit
1 Delay time, UART_CTS_N low to UART_TXD valid 24 Baudout
cycles
2 Setup time, UART_CTS_N high before midpoint of stop bit 10 ns
3 Delay time, midpoint of stop bit to UART_RTS_N high 2 Baudout
cycles
Table 23. PCM Interface Timing Specifications (Short Frame Synchronization, Master Mode)
Reference Characteristics Minimum Maximum Unit
1 PCM bit clock frequency 128 2048 kHz
2 PCM bit clock HIGH time 128 ns
3 PCM bit clock LOW time 209 ns
4 Delay from PCM_BCLK rising edge to PCM_SYNC high 50 ns
5 Delay from PCM_BCLK rising edge to PCM_SYNC low 50 ns
6 Delay from PCM_BCLK rising edge to data valid on PCM_OUT 50 ns
7 Setup time for PCM_IN before PCM_BCLK falling edge 50 ns
8 Hold time for PCM_IN after PCM_BCLK falling edge 10 ns
9 Delay from falling edge of PCM_BCLK during last bit period to
PCM_OUT becoming high impedance
–50ns
1
3
2
UART_CTS_N
UART_TXD
UART_RXD
UART_RTS_N
Midpoint of STOP
bit
Midpoint of STOP
bit
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Figure 14. PCM Interface Timing (Short Frame Synchronization, Master Mode)
123
45
6
7
8
PCM_BCLK
PCM_SYNC
PCM_OUT
PCM_IN
Bit 15 (Previous Frame)
Bit 15 (Previous Frame)
Bit 0
Bit 0
Bit 15
Bit 15
9
HIGH
IMPEDENCE
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Figure 15. PCM Interface Timing (Short Frame Synchronization, Slave Mode)
Table 24. PCM Interface Timing Specifications (Short Frame Synchronization, Slave Mode)
Reference Characteristics Minimum Maximum Unit
1 PCM bit clock frequency 128 2048 kHz
2 PCM bit clock HIGH time 209 ns
3 PCM bit clock LOW time 209 ns
4 Setup time for PCM_SYNC before falling edge of PCM_BCLK 50 ns
5 Hold time for PCM_SYNC after falling edge of PCM_BCLK 10 ns
6 Hold time of PCM_OUT after PCM_BCLK falling edge 175 ns
7 Setup time for PCM_IN before PCM_BCLK falling edge 50 ns
8 Hold time for PCM_IN after PCM_BCLK falling edge 10 ns
9 Delay from falling edge of PCM_BCLK during last bit period
to PCM_OUT becoming high impedance
100 ns
123
4
5
6
7
8
PCM_BCLK
PCM_SYNC
PCM_OUT
PCM_IN
Bit 0
Bit 0
Bit 15
Bit 15
Bit 15 (Previous Frame)
Bit 15 (Previous Frame)
HIGH
IMPEDENCE
9
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CYW20702
Figure 16. PCM Interface Timing (Long Frame Synchronization, Master Mode)
Table 25. PCM Interface Timing Specifications (Long Frame Synchronization, Master Mode)
Reference Characteristics Minimum Maximum Unit
1 PCM bit clock frequency 128 2048 kHz
2 PCM bit clock HIGH time 209 ns
3 PCM bit clock LOW time 209 ns
4 Delay from PCM_BCLK rising edge to PCM_SYNC HIGH during
first bit time
–50ns
5 Delay from PCM_BCLK rising edge to PCM_SYNC LOW during
third bit time
–50ns
6 Delay from PCM_BCLK rising edge to data valid on PCM_OUT 50 ns
7 Setup time for PCM_IN before PCM_BCLK falling edge 50 ns
8 Hold time for PCM_IN after PCM_BCLK falling edge 10 ns
9 Delay from falling edge of PCM_BCLK during last bit period to
PCM_OUT becoming high impedance
–50ns
1
2
3
45
6
7
8
PCM_BCLK
PCM_SYNC
PCM_OUT
PCM_IN
Bit 0
Bit 0
Bit 1
Bit 1
Bit 2
Bit 2
Bit 15
Bit 15
HIGH
IMPEDENCE
9
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Figure 17. PCM Interface Timing (Long Frame Synchronization, Slave Mode)
Table 26. PCM Interface Timing Specifications (Long Frame Synchronization, Slave Mode)
Reference Characteristics Minimum Maximum Unit
1 PCM bit clock frequency. 128 2048 kHz
2 PCM bit clock HIGH time. 209 ns
3 PCM bit clock LOW time. 209 ns
4 Setup time for PCM_SYNC before falling edge of PCM_BCLK
during first bit time.
50 – ns
5 Hold time for PCM_SYNC after falling edge of PCM_BCLK during
second bit period. (PCM_SYNC may go low any time from second
bit period to last bit period).
10 – ns
6 Delay from rising edge of PCM_BCLK or PCM_SYNC
(whichever is later) to data valid for first bit on PCM_OUT.
–50ns
7 Hold time of PCM_OUT after PCM_BCLK falling edge. 175 ns
8 Setup time for PCM_IN before PCM_BCLK falling edge. 50 ns
9 Hold time for PCM_IN after PCM_BCLK falling edge. 10 ns
10 Delay from falling edge of PCM_BCLK or PCM_SYNC
(whichever is later) during last bit in slot to PCM_OUT becoming
high impedance.
–100ns
12
3
45
7
8
9
PCM_BCLK
PCM_SYNC
PCM_OUT
PCM_IN
Bit 0 Bit 1
Bit 0 Bit 1
Bit 15
Bit 15
6
HIGH
IMPEDENCE
10
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9.2.5 BSC Interface Timing
Figure 18. BSC Interface Timing Diagram
Table 27. BSC Interface Timing Specifications
Reference Characteristics Minimum Maximum Unit
1 Clock frequency 100
400
800
1000
kHz
2 START condition setup time 650 ns
3 START condition hold time 280 ns
4 Clock low time 650 ns
5 Clock high time 280 ns
6 Data input hold timea
a. As a transmitter, 300 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START
or STOP conditions
0–ns
7 Data input setup time 100 ns
8 STOP condition setup time 280 ns
9 Output valid from clock 400 ns
10 Bus free timeb
b. Time that the cbus must be free before a new transaction can start.
650 – ns
2
34
5
678
9
10
SCL
SDA
IN
SDA
OUT
1
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9.2.6 SPI Timing
The SPI interface can be clocked up to 12 MHz.
Tab l e 2 8 and Figure 20 show the timing requirements when operating in SPI Mode 0 and 2.
Figure 19. SPI Timing, Mode 0 and 2
Table 28. SPI Mode 0 and 2
Reference Characteristics Minimum Maximum Unit
1 Time from slave assert SPI_INT to master assert SPI_CSN
(DirectRead)
0ns
2 Time from master assert SPI_CSN to slave assert SPI_INT
(DirectWrite)
0ns
3 Time from master assert SPI_CSN to first clock edge 20 ns
4 Setup time for MOSI data lines 8 ½ SCK ns
5 Hold time for MOSI data lines 8 ½ SCK ns
6 Time from last sample on MOSI/MISO to slave deassert SPI_INT 0 100 ns
7 Time from slave deassert SPI_INT to master deassert SPI_CSN 0 ns
8 Idle time between subsequent SPI transactions 1 SCK ns
5
SPI_CSN
SPI_INT
(DirectWrite)
SPI_CLK
(Mode0)
SPI_MOSI FirstBit
SPI_MISO NotDriven FirstBit
SecondBit
SecondBit
Lastbit
Lastbit
3
4
6
7
8
SPI_CLK
(Mode2)
SPI_INT
(DirectRead) 1
2
NotDriven
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CYW20702
Tab l e 2 9 and Figure 20 show the timing requirements when operating in SPI Mode 0 and 2.
Figure 20. SPI Timing, Mode 1 and 3
Table 29. SPI Mode 1 and 3
Reference Characteristics Minimum Maximum Unit
1 Time from slave assert SPI_INT to master assert
SPI_CSN (DirectRead)
0ns
2 Time from master assert SPI_CSN to slave assert
SPI_INT (DirectWrite)
0ns
3 Time from master assert SPI_CSN to first clock edge 20 ns
4 Setup time for MOSI data lines 8 ½ SCK ns
5 Hold time for MOSI data lines 8 ½ SCK ns
6 Time from last sample on MOSI/MISO to slave
deassert SPI_INT
0100ns
7 Time from slave deassert SPI_INT to master
deassert SPI_CSN
0ns
8 Idle time between subsequent SPI transactions 1 SCK ns
5
SPI_CSN
SPI_INT
(DirectWrite)
SPI_CLK
(Mode1)
SPI_MOSI Invalidbit
SPI_MISO NotDriven Invalidbit
Firstbit
Firstbit
Lastbit
Lastbit
3
4
6
7
8
NotDriven
SPI_CLK
(Mode3)
SPI_INT
(DirectRead) 1
2
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CYW20702
9.3 Electrostatic Discharge
Table 30. Electrostatic Discharge Classification – Human Body Model (ESD – HBM)a
a. JESD22-A114 is used as reference.
Title Description
CLASS 0 < 250V
CLASS 1A 250V to < 500V
CLASS 1B 500V to < 1000V
CLASS 1C 1000V to < 2000V
CLASS 2 2000V to < 4000V
CLASS 3A 4000V to < 8000V
CLASS 3B 8000V
Procedures (HBM) For every pin, a positive and negative pulse is applied between (1) the pin and ground, (2)
the pin and VCC, and (3) the pin and all other pins tied together.
Test Electrostatic Discharge (ESD)
Conditions Human Body Model (HBM) JESD22-A114
Purpose To establish the ESD sensitivity.
Failure A failure is any device that fails to meet data sheet electrical requirements after ESD testing.
Pass/Fail Goal is >1000V on all I/O Pins (HBM)
Table 31. Electrostatic Discharge – Machine Model (ESD – MM)a
a. JESD22-A115, latest revision, is used as reference.
Title Description
CLASS A 200V
CLASS B > 200V to 400V
CLASS C > 400V
Procedures (MM) Each sample is stressed at one voltage level using 1 positive and 1 negative pulse with a
minimum of 0.5 second between pulses per pin for all pin combinations.
Test Electrostatic Discharge – Charged-Device Model (ESD - MM)
Conditions Machine Model (MM) JESD22-A115
Purpose To establish the ESD sensitivity.
Failure A failure is any device that fails to meet data sheet electrical requirements after ESD testing.
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Document Number: 002-14773 Rev. *M Page 50 of 55
CYW20702
10. Mechanical Information
Figure 21. 50-Ball WFBGA Mechanical Drawing
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Document Number: 002-14773 Rev. *M Page 51 of 55
CYW20702
10.1 Tape, Reel, and Packing Specification
Figure 22. Reel, Labeling, and Packing Specification
   
Cypress Barcode
ESD Warning
Device Orientation/Mix Lot Number
Each reel may contain up to three lot numbers, independent of the date code.
Individual lots must be labeled on the box, moisture barrier bag, and the reel.
Moisture Barrier Bag Contents/Label
Desiccant pouch (minimum 1)
Humidity indicator (minimum 1)
Reel (maximum 1)
Pin 1
Top-right corner toward sprocket holes.
Document Number: 002-14773 Rev. *M Page 52 of 55
CYW20702
11. Ordering Information
The following table lists available part numbers and describes differences in package type, available I/O, and functional configuration.
See the referenced figures and tables for mechanical drawings and package I/O information.
All packages are rated from –30°C to +85°C.
12. Acronyms and Abbreviations
In most cases, acronyms and abbreviations are defined on first use.
For a comprehensive list of acronyms and other terms used in Cypress documents, go to:
http://www.cypress.com/glossary
13. IoT Resources
Cypress provides a wealth of data at http://www.cypress.com/internet-things-iot to help you to select the right IoT device for your
design, and quickly and effectively integrate the device into your design. Cypress provides customer access to a wide range of
information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software
updates. Customers can acquire technical documentation and software from the Cypress Support Community website
(http://community.cypress.com/).
Part Number Package Type
CYW20702A1KWFBG Commercial 50-ball WFBGA, 4.5 mm x 4.0 mm x 0.8 mm
CYW20702B0KWFBG Commercial 50-ball WFBGA, 4.5 mm x 4.0 mm x 0.8 mm
Note: See Figure 21.
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Document History
Document Title: CYW20702 Single-Chip Bluetooth Transceiver and Baseband Processor
Document Number: 002-14773
Revision ECN Orig. of
Change
Submission
Date Description of Change
** 04/20/2010 20702-DS100-RI
Initial release
*A 06/11/2010 20702-DS101-RI
Updated:
Power Amplifier
Programming
Package Options and TCXO Mode
Frequency Selection
Table 6. CYW20702 Signal Description
Section 8. Ball Grid Arrays
Figure 9. Startup Timing from RST_N
Figure 10. Startup Timing from Power-on Reset
Section 10. Mechanical Information
Section 11. Ordering Information
Removed:
Mobile handsets and smart phones from the chips relevant applications.
The 42-bump WLBGA package from the features list.
Mobile Phone Usage Model
Clock Request Output and TXCO OR Option
*B 08/16/2010 20702-DS102-RI
Updated:
Table 6. CYW20702 Signal Descriptions
Table 8. Absolute Maximum Voltages
Table 9. Power Supply
Table 11. Main Regulator (Main LDO) Electrical Specifications
*C 09/13/2010 20702-DS103-R
Updated:
The document number to show that the document is for external use.
*D 02/23/2011 20702-DS104-R
Updated:
Section 11. Ordering Information
*E 08/01/2011 20702-DS105-R
Updated:
Simultaneous UART Transport and Bridging
*F 08/15/2011 20702-DS106-R
Added:
SPI Timing
Electrostatic Discharge
*G 12/02/2011 20702-DS107-R
Updated:
Table 27. SPI Mode 0 and 2
*H 12/09/2011 20702-DS108-R
Updated:
Table 27. SPI Mode 0 and 2
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CYW20702
*I UTSV 05/11/2012 20702-DS109-R
Updated:
Added compliance support for Low Energy (LE).
Figure 1. System Block Diagram
Figure 2. Functional Block Diagram
Table 2. Power Control Pin Summary
Microprocessor Unit “Overview
Microprocessor ROM and RAM value in “Overview
One-Time Programmable Memory
TCXO Clock Request Support
LPO Clock Interface
Table 7. CYW20702 Signal Descriptions
Table 8. Ball-Out for the 50-Ball WFBGA
Table 14. Pad I/O Characteristics
Table 19. Receiver RF Specifications,
Startup Timing
Section 11. Ordering Information
*J 02/25/2013 Updated:
Host Controller Power Management
HCI 3-Wire Transport (UART H5)
*K 03/04/2014 Updated:
SPI
Table 7. CYW20702 Signal Descriptions
Table 13. Digital I/O Characteristics
*L 5520447 UTSV 11/23/2016 Updated to Cypress Template.
Added Cypress Part Numbering Scheme.
*M 5967848 AESATP12 11/15/2017 Updated logo and copyright.
Document Title: CYW20702 Single-Chip Bluetooth Transceiver and Baseband Processor
Document Number: 002-14773
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Document Number: 002-14773 Rev. *M Revised November 15, 2017 Page 55 of 55
© Cypress Semiconductor Corporation, 2010-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
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device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
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damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
CYW20702
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Cypress maintains a worldwide network of offices, solution centers, manufacturers representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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