ST7565R Datasheet by Displaytech

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ST
Sitronix ST7565R
65 x 132 Dot Matrix LCD Controller/Driver
Ver 1.7 1/72 2007/06/01
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z Directly display RAM data through Display Data RAM.
z RAM capacity : 65 x 132 = 8580 bits
z Display duty selectable by select pin
1/65 duty : 65 common x 132 segment
1/49 duty : 49 common x 132 segment
1/33 duty : 33 common x 132 segment
1/55 duty : 55 common x 132 segment
1/53 duty : 53 common x 132 segment
z High-speed 8-bit MPU interface:
ST7565R can be connected directly to both the 80x86
series MPUs and the 6800 series MPUs.
Serial interface (SPI-4) is also supported.
z Abundant command functions
Display data Read/Write, display ON/OFF, Normal/
Reverse display mode, page address set, display start
line set, column address set, status read, display all
points ON/OFF, LCD bias set, electronic volume,
read/modify/write, segment driver direction selects,
power saver, common output status select, V0 voltage
regulation internal resistor ratio set.
z Embedded analog power supply circuits for Liquid
Crystal driving: Booster, Regulator and Follower.
z Embedded Booster circuit:
2X,3X,4X,5X and 6X boost ratios are supported.
Independent input (VDD2) for boost reference voltage.
z High-accuracy Regulator circuit:
Build-in Electronic volume function for the contrast
control. Thermal gradient = –0.05%/°C.
z Embedded voltage Follower circuit for LCD driving.
z Embedded R-C oscillator circuit.
The external clock is also supported.
z Extremely low power consumption: 60uA, bare dice
(using the internal power). Settings:
VDD – VSS = VDD2 – VSS =3.0 V, Booster Ratio=4,
V0 – VSS = 11.0 V. Display OFF and the normal mode is
selected.
z Logic power supply : VDD – VSS = 2.4V to 3.3 V
Analog Power (Boost reference voltage):
VDD2 – VSS = 2.4V to 3.3V
Booster maximum voltage limited
VOUT= 13.5V
Liquid crystal drive power supply:
V0 – VSS = 3.0V to 12.0 V
z Wide range of operating temperatures: –30 to 85°C
z Package type: COG only.
z The chip is not designed to resist the light or to resist
the radiation.
z Support LCD Module Size up to 2"
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The ST7565R is a single-chip dot matrix LCD driver that can
be connected directly to a microprocessor bus. 8-bit parallel
or 4-line SPI display data sent from the microprocessor is
stored in the internal display data RAM and the chip
generates a LCD drive signal independent of the
microprocessor. Because the chips in the ST7565R contain
65x132 bits of display data RAM and there is a 1-to-1
correspondence between the LCD panel pixels and the
internal RAM bits, these chips enable displays with a high
degree of freedom.
The ST7565R chips contain 65 common output circuits and
132 segment output circuits, so that a single chip can drive a
65x132 dot display (capable of displaying 8 columns x4 rows
of a 16x16 dot kanji font).
The ST7565R chips are able to minimize power consumption
because no external operating clock is necessary for the
display data RAM read/write operation. Furthermore,
because each chip is equipped internally with a low-power
LCD driver power supply, resistors for LCD driver power
voltage adjustment and a display clock CR oscillator circuit,
the ST7565R can be used to create the lowest power display
system with the fewest components for high-performance
portable devices.
PART NO. VRS temperature gradient VRS range
ST7565R -0.05%/°C 2.1V ±0.03V
ST7565R :53: fiifl: (-2562265) (2574 254) 84f mzovnzm 1f 65 334D ----- DDDDDDDDDDDDDDDDDDDD-m Dizzm E ST7565R '[ : PAD DIAGRAM ‘°'°’ E 107 E HUD" "HUBHHHHHHHHHHHHHHHHHHHHHHHHDHHHHHHH "WEE 260 108 259
ST7565R
Ver 1.7 2/72 2007/06/01
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Chip Size: 5900µm x 1000µm
Bump Pitch: 34µm(Min.)
Bump Size: PAD No. 001067 42µm x 54µm
PAD No. 068073 56µm x 54µm
PAD No. 074084 42µm x 54µm
PAD No. 085282 17µm x 118µm
Bump Height: 15µm
Chip Thickness: 480µm
z Recommend panel size is small than 1.8” (A.A.).
ST7565F1‘
ST7565R
Ver 1.7 3/72 2007/06/01
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Units: µm
PAD No. PIN Name X Y
1 TEST[6] 2575 392
2 FR 2515 392
3 CL 2455 392
4 DOF 2395 392
5 VSS 2335 392
6 CS1B 2275 392
7 CS2 2215 392
8 VDD 2155 392
9 RST 2095 392
10 A0 2035 392
11 VSS 1975 392
12 /WR(R/W) 1915 392
13 /RD(E) 1855 392
14 VDD 1795 392
15 D0 1735 392
16 D1 1675 392
17 D2 1615 392
18 D3 1555 392
19 D4 1495 392
20 D5 1435 392
21 D6 1375 392
22 D7 1315 392
23 VDD 1255 392
24 VDD2 1195 392
25 VDD2 1135 392
26 VSS 1075 392
27 VSS 1015 392
28 VSS 955 392
29 VSS 895 392
30 VOUT 821 392
31 VOUT 761 392
32 CAP5P 701 392
33 CAP5P 641 392
34 CAP1N 581 392
35 CAP1N 521 392
36 CAP3P 461 392
37 CAP3P 401 392
38 CAP1N 341 392
39 CAP1N 281 392
40 CAP1P 221 392
41 CAP1P 161 392
42 CAP2P 101 392
43 CAP2P 41 392
44 CAP2N -19 392
45 CAP2N -79 392
46 CAP4P -139 392
47 CAP4P -199 392
48 VSS -273 392
PAD No. PIN Name X Y
49 VSS -333 392
50 VRS -408 392
51 VRS -468 392
52 VDD2 -542 392
53 VDD -602 392
54 V4 -676 392
55 V4 -736 392
56 V3 -796 392
57 V3 -856 392
58 V2 -916 392
59 V2 -976 392
60 V1 -1036 392
61 V1 -1096 392
62 V0 -1156 392
63 V0 -1216 392
64 VR -1276 392
65 VR -1336 392
66 VDD -1410 392
67 VDD2 -1470 392
68 TEST[0] -1537 392
69 TEST[1] -1611 392
70 TEST[2] -1685 392
71 TEST[3] -1759 392
72 TEST[4] -1833 392
73 TEST[5] -1907 392
74 VDD -1974 392
75 TEST[7] -2034 392
76 CLS -2094 392
77 C86 -2154 392
78 PSB -2214 392
79 HPMB -2274 392
80 IRS -2334 392
81 SEL1 -2394 392
82 SEL2 -2454 392
83 SEL3 -2514 392
84 VSS -2574 392
85 COM[31] -2810 373
86 COM[30] -2810 339
87 COM[29] -2810 305
88 COM[28] -2810 271
89 COM[27] -2810 237
90 COM[26] -2810 203
91 COM[25] -2810 169
92 COM[24] -2810 135
93 COM[23] -2810 101
94 COM[22] -2810 67
95 COM[21] -2810 33
96 COM[20] -2810 -1
ST7565F1‘
ST7565R
Ver 1.7 4/72 2007/06/01
PAD No. PIN Name X Y
97 COM[19] -2810 -35
98 COM[18] -2810 -69
99 COM[17] -2810 -103
100 COM[16] -2810 -137
101 COM[15] -2810 -171
102 COM[14] -2810 -205
103 COM[13] -2810 -239
104 COM[12] -2810 -273
105 COM[11] -2810 -307
106 COM[10] -2810 -341
107 COM[9] -2810 -375
108 COM[8] -2573 -360
109 COM[7] -2539 -360
110 COM[6] -2505 -360
111 COM[5] -2471 -360
112 COM[4] -2437 -360
113 COM[3] -2403 -360
114 COM[2] -2369 -360
115 COM[1] -2335 -360
116 COM[0] -2301 -360
117 COMS2 -2267 -360
118 SEG[0] -2227 -360
119 SEG[1] -2193 -360
120 SEG[2] -2159 -360
121 SEG[3] -2125 -360
122 SEG[4] -2091 -360
123 SEG[5] -2057 -360
124 SEG[6] -2023 -360
125 SEG[7] -1989 -360
126 SEG[8] -1955 -360
127 SEG[9] -1921 -360
128 SEG[10] -1887 -360
129 SEG[11] -1853 -360
130 SEG[12] -1819 -360
131 SEG[13] -1785 -360
132 SEG[14] -1751 -360
133 SEG[15] -1717 -360
134 SEG[16] -1683 -360
135 SEG[17] -1649 -360
136 SEG[18] -1615 -360
137 SEG[19] -1581 -360
138 SEG[20] -1547 -360
139 SEG[21] -1513 -360
140 SEG[22] -1479 -360
141 SEG[23] -1445 -360
142 SEG[24] -1411 -360
143 SEG[25] -1377 -360
144 SEG[26] -1343 -360
145 SEG[27] -1309 -360
146 SEG[28] -1275 -360
147 SEG[29] -1241 -360
148 SEG[30] -1207 -360
PAD No. PIN Name X Y
149 SEG[31] -1173 -360
150 SEG[32] -1139 -360
151 SEG[33] -1105 -360
152 SEG[34] -1071 -360
153 SEG[35] -1037 -360
154 SEG[36] -1003 -360
155 SEG[37] -969 -360
156 SEG[38] -935 -360
157 SEG[39] -901 -360
158 SEG[40] -867 -360
159 SEG[41] -833 -360
160 SEG[42] -799 -360
161 SEG[43] -765 -360
162 SEG[44] -731 -360
163 SEG[45] -697 -360
164 SEG[46] -663 -360
165 SEG[47] -629 -360
166 SEG[48] -595 -360
167 SEG[49] -561 -360
168 SEG[50] -527 -360
169 SEG[51] -493 -360
170 SEG[52] -459 -360
171 SEG[53] -425 -360
172 SEG[54] -391 -360
173 SEG[55] -357 -360
174 SEG[56] -323 -360
175 SEG[57] -289 -360
176 SEG[58] -255 -360
177 SEG[59] -221 -360
178 SEG[60] -187 -360
179 SEG[61] -153 -360
180 SEG[62] -119 -360
181 SEG[63] -85 -360
182 SEG[64] -51 -360
183 SEG[65] -17 -360
184 SEG[66] 17 -360
185 SEG[67] 51 -360
186 SEG[68] 85 -360
187 SEG[69] 119 -360
188 SEG[70] 153 -360
189 SEG[71] 187 -360
190 SEG[72] 221 -360
191 SEG[73] 255 -360
192 SEG[74] 289 -360
193 SEG[75] 323 -360
194 SEG[76] 357 -360
195 SEG[77] 391 -360
196 SEG[78] 425 -360
197 SEG[79] 459 -360
198 SEG[80] 493 -360
199 SEG[81] 527 -360
200 SEG[82] 561 -360
ST7565F1‘
ST7565R
Ver 1.7 5/72 2007/06/01
PAD No. PIN Name X Y
201 SEG[83] 595 -360
202 SEG[84] 629 -360
203 SEG[85] 663 -360
204 SEG[86] 697 -360
205 SEG[87] 731 -360
206 SEG[88] 765 -360
207 SEG[89] 799 -360
208 SEG[90] 833 -360
209 SEG[91] 867 -360
210 SEG[92] 901 -360
211 SEG[93] 935 -360
212 SEG[94] 969 -360
213 SEG[95] 1003 -360
214 SEG[96] 1037 -360
215 SEG[97] 1071 -360
216 SEG[98] 1105 -360
217 SEG[99] 1139 -360
218 SEG[100] 1173 -360
219 SEG[101] 1207 -360
220 SEG[102] 1241 -360
221 SEG[103] 1275 -360
222 SEG[104] 1309 -360
223 SEG[105] 1343 -360
224 SEG[106] 1377 -360
225 SEG[107] 1411 -360
226 SEG[108] 1445 -360
227 SEG[109] 1479 -360
228 SEG[110] 1513 -360
229 SEG[111] 1547 -360
230 SEG[112] 1581 -360
231 SEG[113] 1615 -360
232 SEG[114] 1649 -360
233 SEG[115] 1683 -360
234 SEG[116] 1717 -360
235 SEG[117] 1751 -360
236 SEG[118] 1785 -360
237 SEG[119] 1819 -360
238 SEG[120] 1853 -360
239 SEG[121] 1887 -360
240 SEG[122] 1921 -360
241 SEG[123] 1955 -360
242 SEG[124] 1989 -360
243 SEG[125] 2023 -360
244 SEG[126] 2057 -360
245 SEG[127] 2091 -360
PAD No. PIN Name X Y
246 SEG[128] 2125 -360
247 SEG[129] 2159 -360
248 SEG[130] 2193 -360
249 SEG[131] 2227 -360
250 COM[32] 2267 -360
251 COM[33] 2301 -360
252 COM[34] 2335 -360
253 COM[35] 2369 -360
254 COM[36] 2403 -360
255 COM[37] 2437 -360
256 COM[38] 2471 -360
257 COM[39] 2505 -360
258 COM[40] 2539 -360
259 COM[41] 2573 -360
260 COM[42] 2810 -375
261 COM[43] 2810 -341
262 COM[44] 2810 -307
263 COM[45] 2810 -273
264 COM[46] 2810 -239
265 COM[47] 2810 -205
266 COM[48] 2810 -171
267 COM[49] 2810 -137
268 COM[50] 2810 -103
269 COM[51] 2810 -69
270 COM[52] 2810 -35
271 COM[53] 2810 -1
272 COM[54] 2810 33
273 COM[55] 2810 67
274 COM[56] 2810 101
275 COM[57] 2810 135
276 COM[58] 2810 169
277 COM[59] 2810 203
278 COM[60] 2810 237
279 COM[61] 2810 271
280 COM[62] 2810 305
281 COM[63] 2810 339
282 COMS1 2810 373
ST7565F1‘ 0‘234567890‘234567890‘234567890‘234567890‘2345678
ST7565R
Ver 1.7 6/72 2007/06/01
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U
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µ
µm
m
PAD No. PIN Name X Y
1 TEST[6] 2575 392
2 FR 2515 392
3 CL 2455 392
4 DOF 2395 392
5 VSS 2335 392
6 CS1B 2275 392
7 CS2 2215 392
8 VDD 2155 392
9 RST 2095 392
10 A0 2035 392
11 VSS 1975 392
12 /WR(R/W) 1915 392
13 /RD(E) 1855 392
14 VDD 1795 392
15 D0 1735 392
16 D1 1675 392
17 D2 1615 392
18 D3 1555 392
19 D4 1495 392
20 D5 1435 392
21 D6 1375 392
22 D7 1315 392
23 VDD 1255 392
24 VDD2 1195 392
25 VDD2 1135 392
26 VSS 1075 392
27 VSS 1015 392
28 VSS 955 392
29 VSS 895 392
30 VOUT 821 392
31 VOUT 761 392
32 CAP5P 701 392
33 CAP5P 641 392
34 CAP1N 581 392
35 CAP1N 521 392
36 CAP3P 461 392
37 CAP3P 401 392
38 CAP1N 341 392
39 CAP1N 281 392
40 CAP1P 221 392
41 CAP1P 161 392
42 CAP2P 101 392
43 CAP2P 41 392
44 CAP2N -19 392
45 CAP2N -79 392
46 CAP4P -139 392
47 CAP4P -199 392
48 VSS -273 392
49 VSS -333 392
PAD No. PIN Name X Y
50 VRS -408 392
51 VRS -468 392
52 VDD2 -542 392
53 VDD -602 392
54 V4 -676 392
55 V4 -736 392
56 V3 -796 392
57 V3 -856 392
58 V2 -916 392
59 V2 -976 392
60 V1 -1036 392
61 V1 -1096 392
62 V0 -1156 392
63 V0 -1216 392
64 VR -1276 392
65 VR -1336 392
66 VDD -1410 392
67 VDD2 -1470 392
68 TEST[0] -1537 392
69 TEST[1] -1611 392
70 TEST[2] -1685 392
71 TEST[3] -1759 392
72 TEST[4] -1833 392
73 TEST[5] -1907 392
74 VDD -1974 392
75 TEST[7] -2034 392
76 CLS -2094 392
77 C86 -2154 392
78 PSB -2214 392
79 HPMB -2274 392
80 IRS -2334 392
81 SEL1 -2394 392
82 SEL2 -2454 392
83 SEL3 -2514 392
84 VSS -2574 392
85 Reserve -2810 373
86 Reserve -2810 339
87 Reserve -2810 305
88 Reserve -2810 271
89 Reserve -2810 237
90 Reserve -2810 203
91 Reserve -2810 169
92 Reserve -2810 135
93 COM[23] -2810 101
94 COM[22] -2810 67
95 COM[21] -2810 33
96 COM[20] -2810 -1
97 COM[19] -2810 -35
98 COM[18] -2810 -69
ST7565F1‘
ST7565R
Ver 1.7 7/72 2007/06/01
PAD No. PIN Name X Y
99 COM[17] -2810 -103
100 COM[16] -2810 -137
101 COM[15] -2810 -171
102 COM[14] -2810 -205
103 COM[13] -2810 -239
104 COM[12] -2810 -273
105 COM[11] -2810 -307
106 COM[10] -2810 -341
107 COM[9] -2810 -375
108 COM[8] -2573 -360
109 COM[7] -2539 -360
110 COM[6] -2505 -360
111 COM[5] -2471 -360
112 COM[4] -2437 -360
113 COM[3] -2403 -360
114 COM[2] -2369 -360
115 COM[1] -2335 -360
116 COM[0] -2301 -360
117 COMS2 -2267 -360
118 SEG[0] -2227 -360
119 SEG[1] -2193 -360
120 SEG[2] -2159 -360
121 SEG[3] -2125 -360
122 SEG[4] -2091 -360
123 SEG[5] -2057 -360
124 SEG[6] -2023 -360
125 SEG[7] -1989 -360
126 SEG[8] -1955 -360
127 SEG[9] -1921 -360
128 SEG[10] -1887 -360
129 SEG[11] -1853 -360
130 SEG[12] -1819 -360
131 SEG[13] -1785 -360
132 SEG[14] -1751 -360
133 SEG[15] -1717 -360
134 SEG[16] -1683 -360
135 SEG[17] -1649 -360
136 SEG[18] -1615 -360
137 SEG[19] -1581 -360
138 SEG[20] -1547 -360
139 SEG[21] -1513 -360
140 SEG[22] -1479 -360
141 SEG[23] -1445 -360
142 SEG[24] -1411 -360
143 SEG[25] -1377 -360
144 SEG[26] -1343 -360
145 SEG[27] -1309 -360
146 SEG[28] -1275 -360
147 SEG[29] -1241 -360
148 SEG[30] -1207 -360
149 SEG[31] -1173 -360
150 SEG[32] -1139 -360
PAD No. PIN Name X Y
151 SEG[33] -1105 -360
152 SEG[34] -1071 -360
153 SEG[35] -1037 -360
154 SEG[36] -1003 -360
155 SEG[37] -969 -360
156 SEG[38] -935 -360
157 SEG[39] -901 -360
158 SEG[40] -867 -360
159 SEG[41] -833 -360
160 SEG[42] -799 -360
161 SEG[43] -765 -360
162 SEG[44] -731 -360
163 SEG[45] -697 -360
164 SEG[46] -663 -360
165 SEG[47] -629 -360
166 SEG[48] -595 -360
167 SEG[49] -561 -360
168 SEG[50] -527 -360
169 SEG[51] -493 -360
170 SEG[52] -459 -360
171 SEG[53] -425 -360
172 SEG[54] -391 -360
173 SEG[55] -357 -360
174 SEG[56] -323 -360
175 SEG[57] -289 -360
176 SEG[58] -255 -360
177 SEG[59] -221 -360
178 SEG[60] -187 -360
179 SEG[61] -153 -360
180 SEG[62] -119 -360
181 SEG[63] -85 -360
182 SEG[64] -51 -360
183 SEG[65] -17 -360
184 SEG[66] 17 -360
185 SEG[67] 51 -360
186 SEG[68] 85 -360
187 SEG[69] 119 -360
188 SEG[70] 153 -360
189 SEG[71] 187 -360
190 SEG[72] 221 -360
191 SEG[73] 255 -360
192 SEG[74] 289 -360
193 SEG[75] 323 -360
194 SEG[76] 357 -360
195 SEG[77] 391 -360
196 SEG[78] 425 -360
197 SEG[79] 459 -360
198 SEG[80] 493 -360
199 SEG[81] 527 -360
200 SEG[82] 561 -360
201 SEG[83] 595 -360
202 SEG[84] 629 -360
ST7565F1‘ 5957715957159500000000000000000000000 5456789012545678901254567890125456789012545
ST7565R
Ver 1.7 8/72 2007/06/01
PAD No. PIN Name X Y
203 SEG[85] 663 -360
204 SEG[86] 697 -360
205 SEG[87] 731 -360
206 SEG[88] 765 -360
207 SEG[89] 799 -360
208 SEG[90] 833 -360
209 SEG[91] 867 -360
210 SEG[92] 901 -360
211 SEG[93] 935 -360
212 SEG[94] 969 -360
213 SEG[95] 1003 -360
214 SEG[96] 1037 -360
215 SEG[97] 1071 -360
216 SEG[98] 1105 -360
217 SEG[99] 1139 -360
218 SEG[100] 1173 -360
219 SEG[101] 1207 -360
220 SEG[102] 1241 -360
221 SEG[103] 1275 -360
222 SEG[104] 1309 -360
223 SEG[105] 1343 -360
224 SEG[106] 1377 -360
225 SEG[107] 1411 -360
226 SEG[108] 1445 -360
227 SEG[109] 1479 -360
228 SEG[110] 1513 -360
229 SEG[111] 1547 -360
230 SEG[112] 1581 -360
231 SEG[113] 1615 -360
232 SEG[114] 1649 -360
233 SEG[115] 1683 -360
234 SEG[116] 1717 -360
235 SEG[117] 1751 -360
236 SEG[118] 1785 -360
237 SEG[119] 1819 -360
238 SEG[120] 1853 -360
239 SEG[121] 1887 -360
240 SEG[122] 1921 -360
241 SEG[123] 1955 -360
242 SEG[124] 1989 -360
243 SEG[125] 2023 -360
244 SEG[126] 2057 -360
245 SEG[127] 2091 -360
PAD No. PIN Name X Y
246 SEG[128] 2125 -360
247 SEG[129] 2159 -360
248 SEG[130] 2193 -360
249 SEG[131] 2227 -360
250 Reserve 2267 -360
251 Reserve 2301 -360
252 Reserve 2335 -360
253 Reserve 2369 -360
254 Reserve 2403 -360
255 Reserve 2437 -360
256 Reserve 2471 -360
257 Reserve 2505 -360
258 COM[24] 2539 -360
259 COM[25] 2573 -360
260 COM[26] 2810 -375
261 COM[27] 2810 -341
262 COM[28] 2810 -307
263 COM[29] 2810 -273
264 COM[30] 2810 -239
265 COM[31] 2810 -205
266 COM[32] 2810 -171
267 COM[33] 2810 -137
268 COM[34] 2810 -103
269 COM[35] 2810 -69
270 COM[36] 2810 -35
271 COM[37] 2810 -1
272 COM[38] 2810 33
273 COM[39] 2810 67
274 COM[40] 2810 101
275 COM[41] 2810 135
276 COM[42] 2810 169
277 COM[43] 2810 203
278 COM[44] 2810 237
279 COM[45] 2810 271
280 COM[46] 2810 305
281 COM[47] 2810 339
282 COMS1 2810 373
ST7565F1‘
ST7565R
Ver 1.7 9/72 2007/06/01
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at
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s
(
(1
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/3
33
3
D
Du
ut
ty
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)
U
Un
ni
it
ts
s:
:
µ
µm
m
PAD No. PIN Name X Y
1 TEST[6] 2575 392
2 FR 2515 392
3 CL 2455 392
4 DOF 2395 392
5 VSS 2335 392
6 CS1B 2275 392
7 CS2 2215 392
8 VDD 2155 392
9 RST 2095 392
10 A0 2035 392
11 VSS 1975 392
12 /WR(R/W) 1915 392
13 /RD(E) 1855 392
14 VDD 1795 392
15 D0 1735 392
16 D1 1675 392
17 D2 1615 392
18 D3 1555 392
19 D4 1495 392
20 D5 1435 392
21 D6 1375 392
22 D7 1315 392
23 VDD 1255 392
24 VDD2 1195 392
25 VDD2 1135 392
26 VSS 1075 392
27 VSS 1015 392
28 VSS 955 392
29 VSS 895 392
30 VOUT 821 392
31 VOUT 761 392
32 CAP5P 701 392
33 CAP5P 641 392
34 CAP1N 581 392
35 CAP1N 521 392
36 CAP3P 461 392
37 CAP3P 401 392
38 CAP1N 341 392
39 CAP1N 281 392
40 CAP1P 221 392
41 CAP1P 161 392
42 CAP2P 101 392
43 CAP2P 41 392
44 CAP2N -19 392
45 CAP2N -79 392
46 CAP4P -139 392
47 CAP4P -199 392
48 VSS -273 392
49 VSS -333 392
PAD No. PIN Name X Y
50 VRS -408 392
51 VRS -468 392
52 VDD2 -542 392
53 VDD -602 392
54 V4 -676 392
55 V4 -736 392
56 V3 -796 392
57 V3 -856 392
58 V2 -916 392
59 V2 -976 392
60 V1 -1036 392
61 V1 -1096 392
62 V0 -1156 392
63 V0 -1216 392
64 VR -1276 392
65 VR -1336 392
66 VDD -1410 392
67 VDD2 -1470 392
68 TEST[0] -1537 392
69 TEST[1] -1611 392
70 TEST[2] -1685 392
71 TEST[3] -1759 392
72 TEST[4] -1833 392
73 TEST[5] -1907 392
74 VDD -1974 392
75 TEST[7] -2034 392
76 CLS -2094 392
77 C86 -2154 392
78 PSB -2214 392
79 HPMB -2274 392
80 IRS -2334 392
81 SEL1 -2394 392
82 SEL2 -2454 392
83 SEL3 -2514 392
84 VSS -2574 392
85 Reserve -2810 373
86 Reserve -2810 339
87 Reserve -2810 305
88 Reserve -2810 271
89 Reserve -2810 237
90 Reserve -2810 203
91 Reserve -2810 169
92 Reserve -2810 135
93 Reserve -2810 101
94 Reserve -2810 67
95 RESERVED -2810 33
96 RESERVED -2810 -1
97 RESERVED -2810 -35
98 RESERVED -2810 -69
ST7565F1‘ 012545678901254567890125456789012545678901254567890
ST7565R
Ver 1.7 10/72 2007/06/01
PAD No. PIN Name X Y
99 RESERVED -2810 -103
100 RESERVED -2810 -137
101 COM[15] -2810 -171
102 COM[14] -2810 -205
103 COM[13] -2810 -239
104 COM[12] -2810 -273
105 COM[11] -2810 -307
106 COM[10] -2810 -341
107 COM[9] -2810 -375
108 COM[8] -2573 -360
109 COM[7] -2539 -360
110 COM[6] -2505 -360
111 COM[5] -2471 -360
112 COM[4] -2437 -360
113 COM[3] -2403 -360
114 COM[2] -2369 -360
115 COM[1] -2335 -360
116 COM[0] -2301 -360
117 COMS2 -2267 -360
118 SEG[0] -2227 -360
119 SEG[1] -2193 -360
120 SEG[2] -2159 -360
121 SEG[3] -2125 -360
122 SEG[4] -2091 -360
123 SEG[5] -2057 -360
124 SEG[6] -2023 -360
125 SEG[7] -1989 -360
126 SEG[8] -1955 -360
127 SEG[9] -1921 -360
128 SEG[10] -1887 -360
129 SEG[11] -1853 -360
130 SEG[12] -1819 -360
131 SEG[13] -1785 -360
132 SEG[14] -1751 -360
133 SEG[15] -1717 -360
134 SEG[16] -1683 -360
135 SEG[17] -1649 -360
136 SEG[18] -1615 -360
137 SEG[19] -1581 -360
138 SEG[20] -1547 -360
139 SEG[21] -1513 -360
140 SEG[22] -1479 -360
141 SEG[23] -1445 -360
142 SEG[24] -1411 -360
143 SEG[25] -1377 -360
144 SEG[26] -1343 -360
145 SEG[27] -1309 -360
146 SEG[28] -1275 -360
147 SEG[29] -1241 -360
148 SEG[30] -1207 -360
149 SEG[31] -1173 -360
150 SEG[32] -1139 -360
PAD No. PIN Name X Y
151 SEG[33] -1105 -360
152 SEG[34] -1071 -360
153 SEG[35] -1037 -360
154 SEG[36] -1003 -360
155 SEG[37] -969 -360
156 SEG[38] -935 -360
157 SEG[39] -901 -360
158 SEG[40] -867 -360
159 SEG[41] -833 -360
160 SEG[42] -799 -360
161 SEG[43] -765 -360
162 SEG[44] -731 -360
163 SEG[45] -697 -360
164 SEG[46] -663 -360
165 SEG[47] -629 -360
166 SEG[48] -595 -360
167 SEG[49] -561 -360
168 SEG[50] -527 -360
169 SEG[51] -493 -360
170 SEG[52] -459 -360
171 SEG[53] -425 -360
172 SEG[54] -391 -360
173 SEG[55] -357 -360
174 SEG[56] -323 -360
175 SEG[57] -289 -360
176 SEG[58] -255 -360
177 SEG[59] -221 -360
178 SEG[60] -187 -360
179 SEG[61] -153 -360
180 SEG[62] -119 -360
181 SEG[63] -85 -360
182 SEG[64] -51 -360
183 SEG[65] -17 -360
184 SEG[66] 17 -360
185 SEG[67] 51 -360
186 SEG[68] 85 -360
187 SEG[69] 119 -360
188 SEG[70] 153 -360
189 SEG[71] 187 -360
190 SEG[72] 221 -360
191 SEG[73] 255 -360
192 SEG[74] 289 -360
193 SEG[75] 323 -360
194 SEG[76] 357 -360
195 SEG[77] 391 -360
196 SEG[78] 425 -360
197 SEG[79] 459 -360
198 SEG[80] 493 -360
199 SEG[81] 527 -360
200 SEG[82] 561 -360
201 SEG[83] 595 -360
202 SEG[84] 629 -360
ST7565F1‘ 5957715957159500000000000000000000000 5456789012545678901254567890125456789012545
ST7565R
Ver 1.7 11/72 2007/06/01
PAD No. PIN Name X Y
203 SEG[85] 663 -360
204 SEG[86] 697 -360
205 SEG[87] 731 -360
206 SEG[88] 765 -360
207 SEG[89] 799 -360
208 SEG[90] 833 -360
209 SEG[91] 867 -360
210 SEG[92] 901 -360
211 SEG[93] 935 -360
212 SEG[94] 969 -360
213 SEG[95] 1003 -360
214 SEG[96] 1037 -360
215 SEG[97] 1071 -360
216 SEG[98] 1105 -360
217 SEG[99] 1139 -360
218 SEG[100] 1173 -360
219 SEG[101] 1207 -360
220 SEG[102] 1241 -360
221 SEG[103] 1275 -360
222 SEG[104] 1309 -360
223 SEG[105] 1343 -360
224 SEG[106] 1377 -360
225 SEG[107] 1411 -360
226 SEG[108] 1445 -360
227 SEG[109] 1479 -360
228 SEG[110] 1513 -360
229 SEG[111] 1547 -360
230 SEG[112] 1581 -360
231 SEG[113] 1615 -360
232 SEG[114] 1649 -360
233 SEG[115] 1683 -360
234 SEG[116] 1717 -360
235 SEG[117] 1751 -360
236 SEG[118] 1785 -360
237 SEG[119] 1819 -360
238 SEG[120] 1853 -360
239 SEG[121] 1887 -360
240 SEG[122] 1921 -360
241 SEG[123] 1955 -360
242 SEG[124] 1989 -360
243 SEG[125] 2023 -360
244 SEG[126] 2057 -360
245 SEG[127] 2091 -360
PAD No. PIN Name X Y
246 SEG[128] 2125 -360
247 SEG[129] 2159 -360
248 SEG[130] 2193 -360
249 SEG[131] 2227 -360
250 Reserve 2267 -360
251 Reserve 2301 -360
252 Reserve 2335 -360
253 Reserve 2369 -360
254 Reserve 2403 -360
255 Reserve 2437 -360
256 Reserve 2471 -360
257 Reserve 2505 -360
258 Reserve 2539 -360
259 Reserve 2573 -360
260 Reserve 2810 -375
261 Reserve 2810 -341
262 Reserve 2810 -307
263 Reserve 2810 -273
264 Reserve 2810 -239
265 Reserve 2810 -205
266 COM[16] 2810 -171
267 COM[17] 2810 -137
268 COM[18] 2810 -103
269 COM[19] 2810 -69
270 COM[20] 2810 -35
271 COM[21] 2810 -1
272 COM[22] 2810 33
273 COM[23] 2810 67
274 COM[24] 2810 101
275 COM[25] 2810 135
276 COM[26] 2810 169
277 COM[27] 2810 203
278 COM[28] 2810 237
279 COM[29] 2810 271
280 COM[30] 2810 305
281 COM[31] 2810 339
282 COMS1 2810 373
ST7565F1‘
ST7565R
Ver 1.7 12/72 2007/06/01
P
Pa
ad
d
C
Ce
en
nt
te
er
r
C
Co
oo
or
rd
di
in
na
at
te
es
s
(
(1
1/
/5
55
5
D
Du
ut
ty
y)
)
U
Un
ni
it
ts
s:
:
µ
µm
m
PAD No. PIN Name X Y
1 TEST[6] 2575 392
2 FR 2515 392
3 CL 2455 392
4 DOF 2395 392
5 VSS 2335 392
6 CS1B 2275 392
7 CS2 2215 392
8 VDD 2155 392
9 RST 2095 392
10 A0 2035 392
11 VSS 1975 392
12 /WR(R/W) 1915 392
13 /RD(E) 1855 392
14 VDD 1795 392
15 D0 1735 392
16 D1 1675 392
17 D2 1615 392
18 D3 1555 392
19 D4 1495 392
20 D5 1435 392
21 D6 1375 392
22 D7 1315 392
23 VDD 1255 392
24 VDD2 1195 392
25 VDD2 1135 392
26 VSS 1075 392
27 VSS 1015 392
28 VSS 955 392
29 VSS 895 392
30 VOUT 821 392
31 VOUT 761 392
32 CAP5P 701 392
33 CAP5P 641 392
34 CAP1N 581 392
35 CAP1N 521 392
36 CAP3P 461 392
37 CAP3P 401 392
38 CAP1N 341 392
39 CAP1N 281 392
40 CAP1P 221 392
41 CAP1P 161 392
42 CAP2P 101 392
43 CAP2P 41 392
44 CAP2N -19 392
45 CAP2N -79 392
46 CAP4P -139 392
47 CAP4P -199 392
48 VSS -273 392
49 VSS -333 392
PAD No. PIN Name X Y
50 VRS -408 392
51 VRS -468 392
52 VDD2 -542 392
53 VDD -602 392
54 V4 -676 392
55 V4 -736 392
56 V3 -796 392
57 V3 -856 392
58 V2 -916 392
59 V2 -976 392
60 V1 -1036 392
61 V1 -1096 392
62 V0 -1156 392
63 V0 -1216 392
64 VR -1276 392
65 VR -1336 392
66 VDD -1410 392
67 VDD2 -1470 392
68 TEST[0] -1537 392
69 TEST[1] -1611 392
70 TEST[2] -1685 392
71 TEST[3] -1759 392
72 TEST[4] -1833 392
73 TEST[5] -1907 392
74 VDD -1974 392
75 TEST[7] -2034 392
76 CLS -2094 392
77 C86 -2154 392
78 PSB -2214 392
79 HPMB -2274 392
80 IRS -2334 392
81 SEL1 -2394 392
82 SEL2 -2454 392
83 SEL3 -2514 392
84 VSS -2574 392
85 Reserve -2810 373
86 Reserve -2810 339
87 Reserve -2810 305
88 Reserve -2810 271
89 Reserve -2810 237
90 COM[26] -2810 203
91 COM[25] -2810 169
92 COM[24] -2810 135
93 COM[23] -2810 101
94 COM[22] -2810 67
95 COM[21] -2810 33
96 COM[20] -2810 -1
97 COM[19] -2810 -35
98 COM[18] -2810 -69
ST7565F1‘ 012545678901254567890125456789012545678901254567890
ST7565R
Ver 1.7 13/72 2007/06/01
PAD No. PIN Name X Y
99 COM[17] -2810 -103
100 COM[16] -2810 -137
101 COM[15] -2810 -171
102 COM[14] -2810 -205
103 COM[13] -2810 -239
104 COM[12] -2810 -273
105 COM[11] -2810 -307
106 COM[10] -2810 -341
107 COM[9] -2810 -375
108 COM[8] -2573 -360
109 COM[7] -2539 -360
110 COM[6] -2505 -360
111 COM[5] -2471 -360
112 COM[4] -2437 -360
113 COM[3] -2403 -360
114 COM[2] -2369 -360
115 COM[1] -2335 -360
116 COM[0] -2301 -360
117 COMS2 -2267 -360
118 SEG[0] -2227 -360
119 SEG[1] -2193 -360
120 SEG[2] -2159 -360
121 SEG[3] -2125 -360
122 SEG[4] -2091 -360
123 SEG[5] -2057 -360
124 SEG[6] -2023 -360
125 SEG[7] -1989 -360
126 SEG[8] -1955 -360
127 SEG[9] -1921 -360
128 SEG[10] -1887 -360
129 SEG[11] -1853 -360
130 SEG[12] -1819 -360
131 SEG[13] -1785 -360
132 SEG[14] -1751 -360
133 SEG[15] -1717 -360
134 SEG[16] -1683 -360
135 SEG[17] -1649 -360
136 SEG[18] -1615 -360
137 SEG[19] -1581 -360
138 SEG[20] -1547 -360
139 SEG[21] -1513 -360
140 SEG[22] -1479 -360
141 SEG[23] -1445 -360
142 SEG[24] -1411 -360
143 SEG[25] -1377 -360
144 SEG[26] -1343 -360
145 SEG[27] -1309 -360
146 SEG[28] -1275 -360
147 SEG[29] -1241 -360
148 SEG[30] -1207 -360
149 SEG[31] -1173 -360
150 SEG[32] -1139 -360
PAD No. PIN Name X Y
151 SEG[33] -1105 -360
152 SEG[34] -1071 -360
153 SEG[35] -1037 -360
154 SEG[36] -1003 -360
155 SEG[37] -969 -360
156 SEG[38] -935 -360
157 SEG[39] -901 -360
158 SEG[40] -867 -360
159 SEG[41] -833 -360
160 SEG[42] -799 -360
161 SEG[43] -765 -360
162 SEG[44] -731 -360
163 SEG[45] -697 -360
164 SEG[46] -663 -360
165 SEG[47] -629 -360
166 SEG[48] -595 -360
167 SEG[49] -561 -360
168 SEG[50] -527 -360
169 SEG[51] -493 -360
170 SEG[52] -459 -360
171 SEG[53] -425 -360
172 SEG[54] -391 -360
173 SEG[55] -357 -360
174 SEG[56] -323 -360
175 SEG[57] -289 -360
176 SEG[58] -255 -360
177 SEG[59] -221 -360
178 SEG[60] -187 -360
179 SEG[61] -153 -360
180 SEG[62] -119 -360
181 SEG[63] -85 -360
182 SEG[64] -51 -360
183 SEG[65] -17 -360
184 SEG[66] 17 -360
185 SEG[67] 51 -360
186 SEG[68] 85 -360
187 SEG[69] 119 -360
188 SEG[70] 153 -360
189 SEG[71] 187 -360
190 SEG[72] 221 -360
191 SEG[73] 255 -360
192 SEG[74] 289 -360
193 SEG[75] 323 -360
194 SEG[76] 357 -360
195 SEG[77] 391 -360
196 SEG[78] 425 -360
197 SEG[79] 459 -360
198 SEG[80] 493 -360
199 SEG[81] 527 -360
200 SEG[82] 561 -360
201 SEG[83] 595 -360
202 SEG[84] 629 -360
ST7565F1‘ 5957715957159500000000000000000000000 5456789012545678901254567890125456789012545
ST7565R
Ver 1.7 14/72 2007/06/01
PAD No. PIN Name X Y
203 SEG[85] 663 -360
204 SEG[86] 697 -360
205 SEG[87] 731 -360
206 SEG[88] 765 -360
207 SEG[89] 799 -360
208 SEG[90] 833 -360
209 SEG[91] 867 -360
210 SEG[92] 901 -360
211 SEG[93] 935 -360
212 SEG[94] 969 -360
213 SEG[95] 1003 -360
214 SEG[96] 1037 -360
215 SEG[97] 1071 -360
216 SEG[98] 1105 -360
217 SEG[99] 1139 -360
218 SEG[100] 1173 -360
219 SEG[101] 1207 -360
220 SEG[102] 1241 -360
221 SEG[103] 1275 -360
222 SEG[104] 1309 -360
223 SEG[105] 1343 -360
224 SEG[106] 1377 -360
225 SEG[107] 1411 -360
226 SEG[108] 1445 -360
227 SEG[109] 1479 -360
228 SEG[110] 1513 -360
229 SEG[111] 1547 -360
230 SEG[112] 1581 -360
231 SEG[113] 1615 -360
232 SEG[114] 1649 -360
233 SEG[115] 1683 -360
234 SEG[116] 1717 -360
235 SEG[117] 1751 -360
236 SEG[118] 1785 -360
237 SEG[119] 1819 -360
238 SEG[120] 1853 -360
239 SEG[121] 1887 -360
240 SEG[122] 1921 -360
241 SEG[123] 1955 -360
242 SEG[124] 1989 -360
243 SEG[125] 2023 -360
244 SEG[126] 2057 -360
245 SEG[127] 2091 -360
PAD No. PIN Name X Y
246 SEG[128] 2125 -360
247 SEG[129] 2159 -360
248 SEG[130] 2193 -360
249 SEG[131] 2227 -360
250 Reserve 2267 -360
251 Reserve 2301 -360
252 Reserve 2335 -360
253 Reserve 2369 -360
254 Reserve 2403 -360
255 COM[27] 2437 -360
256 COM[28] 2471 -360
257 COM[29] 2505 -360
258 COM[30] 2539 -360
259 COM[31] 2573 -360
260 COM[32] 2810 -375
261 COM[33] 2810 -341
262 COM[34] 2810 -307
263 COM[35] 2810 -273
264 COM[36] 2810 -239
265 COM[37] 2810 -205
266 COM[38] 2810 -171
267 COM[39] 2810 -137
268 COM[40] 2810 -103
269 COM[41] 2810 -69
270 COM[42] 2810 -35
271 COM[43] 2810 -1
272 COM[44] 2810 33
273 COM[45] 2810 67
274 COM[46] 2810 101
275 COM[47] 2810 135
276 COM[48] 2810 169
277 COM[49] 2810 203
278 COM[50] 2810 237
279 COM[51] 2810 271
280 COM[52] 2810 305
281 COM[53] 2810 339
282 COMS1 2810 373
ST7565F1‘
ST7565R
Ver 1.7 15/72 2007/06/01
P
Pa
ad
d
C
Ce
en
nt
te
er
r
C
Co
oo
or
rd
di
in
na
at
te
es
s
(
(1
1/
/5
53
3
D
Du
ut
ty
y)
)
U
Un
ni
it
ts
s:
:
µ
µm
m
PAD No. PIN Name X Y
1 TEST[6] 2575 392
2 FR 2515 392
3 CL 2455 392
4 DOF 2395 392
5 VSS 2335 392
6 CS1B 2275 392
7 CS2 2215 392
8 VDD 2155 392
9 RST 2095 392
10 A0 2035 392
11 VSS 1975 392
12 /WR(R/W) 1915 392
13 /RD(E) 1855 392
14 VDD 1795 392
15 D0 1735 392
16 D1 1675 392
17 D2 1615 392
18 D3 1555 392
19 D4 1495 392
20 D5 1435 392
21 D6 1375 392
22 D7 1315 392
23 VDD 1255 392
24 VDD2 1195 392
25 VDD2 1135 392
26 VSS 1075 392
27 VSS 1015 392
28 VSS 955 392
29 VSS 895 392
30 VOUT 821 392
31 VOUT 761 392
32 CAP5P 701 392
33 CAP5P 641 392
34 CAP1N 581 392
35 CAP1N 521 392
36 CAP3P 461 392
37 CAP3P 401 392
38 CAP1N 341 392
39 CAP1N 281 392
40 CAP1P 221 392
41 CAP1P 161 392
42 CAP2P 101 392
43 CAP2P 41 392
44 CAP2N -19 392
45 CAP2N -79 392
46 CAP4P -139 392
47 CAP4P -199 392
48 VSS -273 392
49 VSS -333 392
PAD No. PIN Name X Y
50 VRS -408 392
51 VRS -468 392
52 VDD2 -542 392
53 VDD -602 392
54 V4 -676 392
55 V4 -736 392
56 V3 -796 392
57 V3 -856 392
58 V2 -916 392
59 V2 -976 392
60 V1 -1036 392
61 V1 -1096 392
62 V0 -1156 392
63 V0 -1216 392
64 VR -1276 392
65 VR -1336 392
66 VDD -1410 392
67 VDD2 -1470 392
68 TEST[0] -1537 392
69 TEST[1] -1611 392
70 TEST[2] -1685 392
71 TEST[3] -1759 392
72 TEST[4] -1833 392
73 TEST[5] -1907 392
74 VDD -1974 392
75 TEST[7] -2034 392
76 CLS -2094 392
77 C86 -2154 392
78 PSB -2214 392
79 HPMB -2274 392
80 IRS -2334 392
81 SEL1 -2394 392
82 SEL2 -2454 392
83 SEL3 -2514 392
84 VSS -2574 392
85 Reserve -2810 373
86 Reserve -2810 339
87 Reserve -2810 305
88 Reserve -2810 271
89 Reserve -2810 237
90 Reserve -2810 203
91 COM[25] -2810 169
92 COM[24] -2810 135
93 COM[23] -2810 101
94 COM[22] -2810 67
95 COM[21] -2810 33
96 COM[20] -2810 -1
97 COM[19] -2810 -35
98 COM[18] -2810 -69
ST7565F1‘ 012545678901254567890125456789012545678901254567890
ST7565R
Ver 1.7 16/72 2007/06/01
PAD No. PIN Name X Y
99 COM[17] -2810 -103
100 COM[16] -2810 -137
101 COM[15] -2810 -171
102 COM[14] -2810 -205
103 COM[13] -2810 -239
104 COM[12] -2810 -273
105 COM[11] -2810 -307
106 COM[10] -2810 -341
107 COM[9] -2810 -375
108 COM[8] -2573 -360
109 COM[7] -2539 -360
110 COM[6] -2505 -360
111 COM[5] -2471 -360
112 COM[4] -2437 -360
113 COM[3] -2403 -360
114 COM[2] -2369 -360
115 COM[1] -2335 -360
116 COM[0] -2301 -360
117 COMS2 -2267 -360
118 SEG[0] -2227 -360
119 SEG[1] -2193 -360
120 SEG[2] -2159 -360
121 SEG[3] -2125 -360
122 SEG[4] -2091 -360
123 SEG[5] -2057 -360
124 SEG[6] -2023 -360
125 SEG[7] -1989 -360
126 SEG[8] -1955 -360
127 SEG[9] -1921 -360
128 SEG[10] -1887 -360
129 SEG[11] -1853 -360
130 SEG[12] -1819 -360
131 SEG[13] -1785 -360
132 SEG[14] -1751 -360
133 SEG[15] -1717 -360
134 SEG[16] -1683 -360
135 SEG[17] -1649 -360
136 SEG[18] -1615 -360
137 SEG[19] -1581 -360
138 SEG[20] -1547 -360
139 SEG[21] -1513 -360
140 SEG[22] -1479 -360
141 SEG[23] -1445 -360
142 SEG[24] -1411 -360
143 SEG[25] -1377 -360
144 SEG[26] -1343 -360
145 SEG[27] -1309 -360
146 SEG[28] -1275 -360
147 SEG[29] -1241 -360
148 SEG[30] -1207 -360
149 SEG[31] -1173 -360
150 SEG[32] -1139 -360
PAD No. PIN Name X Y
151 SEG[33] -1105 -360
152 SEG[34] -1071 -360
153 SEG[35] -1037 -360
154 SEG[36] -1003 -360
155 SEG[37] -969 -360
156 SEG[38] -935 -360
157 SEG[39] -901 -360
158 SEG[40] -867 -360
159 SEG[41] -833 -360
160 SEG[42] -799 -360
161 SEG[43] -765 -360
162 SEG[44] -731 -360
163 SEG[45] -697 -360
164 SEG[46] -663 -360
165 SEG[47] -629 -360
166 SEG[48] -595 -360
167 SEG[49] -561 -360
168 SEG[50] -527 -360
169 SEG[51] -493 -360
170 SEG[52] -459 -360
171 SEG[53] -425 -360
172 SEG[54] -391 -360
173 SEG[55] -357 -360
174 SEG[56] -323 -360
175 SEG[57] -289 -360
176 SEG[58] -255 -360
177 SEG[59] -221 -360
178 SEG[60] -187 -360
179 SEG[61] -153 -360
180 SEG[62] -119 -360
181 SEG[63] -85 -360
182 SEG[64] -51 -360
183 SEG[65] -17 -360
184 SEG[66] 17 -360
185 SEG[67] 51 -360
186 SEG[68] 85 -360
187 SEG[69] 119 -360
188 SEG[70] 153 -360
189 SEG[71] 187 -360
190 SEG[72] 221 -360
191 SEG[73] 255 -360
192 SEG[74] 289 -360
193 SEG[75] 323 -360
194 SEG[76] 357 -360
195 SEG[77] 391 -360
196 SEG[78] 425 -360
197 SEG[79] 459 -360
198 SEG[80] 493 -360
199 SEG[81] -207 -374
200 SEG[82] -149 -374
201 SEG[83] -91 -374
202 SEG[84] -33 -374
ST7565F1‘ 5456789012545678901254567890125456789012545
ST7565R
Ver 1.7 17/72 2007/06/01
PAD No. PIN Name X Y
203 SEG[85] 25 -374
204 SEG[86] 83 -374
205 SEG[87] 141 -374
206 SEG[88] 199 -374
207 SEG[89] 257 -374
208 SEG[90] 315 -374
209 SEG[91] 373 -374
210 SEG[92] 431 -374
211 SEG[93] 489 -374
212 SEG[94] 547 -374
213 SEG[95] 605 -374
214 SEG[96] 663 -374
215 SEG[97] 721 -374
216 SEG[98] 779 -374
217 SEG[99] 837 -374
218 SEG[100] 895 -374
219 SEG[101] 953 -374
220 SEG[102] 1011 -374
221 SEG[103] 1069 -374
222 SEG[104] 1127 -374
223 SEG[105] 1185 -374
224 SEG[106] 1243 -374
225 SEG[107] 1301 -374
226 SEG[108] 1359 -374
227 SEG[109] 1417 -374
228 SEG[110] 1475 -374
229 SEG[111] 1533 -374
230 SEG[112] 1591 -374
231 SEG[113] 1649 -374
232 SEG[114] 1707 -374
233 SEG[115] 1765 -374
234 SEG[116] 1823 -374
235 SEG[117] 1881 -374
236 SEG[118] 1939 -374
237 SEG[119] 1997 -374
238 SEG[120] 2055 -374
239 SEG[121] 2113 -374
240 SEG[122] 2171 -374
241 SEG[123] 2229 -374
242 SEG[124] 2287 -374
243 SEG[125] 2345 -374
244 SEG[126] 2403 -374
245 SEG[127] 2461 -374
PAD No. PIN Name X Y
246 SEG[128] 2519 -374
247 SEG[129] 2577 -374
248 SEG[130] 2635 -374
249 SEG[131] 2693 -374
250 Reserve 2751 -374
251 Reserve 2809 -374
252 Reserve 2867 -374
253 Reserve 2925 -374
254 Reserve 2983 -374
255 Reserve 3041 -374
256 COM[26] 3099 -374
257 COM[27] 3157 -374
258 COM[28] 3215 -374
259 COM[29] 3273 -374
260 COM[30] 3331 -374
261 COM[31] 3389 -374
262 COM[32] 3447 -374
263 COM[33] 3505 -374
264 COM[34] 3563 -374
265 COM[35] 3621 -374
266 COM[36] 3679 -374
267 COM[37] 3737 -374
268 COM[38] 3795 -374
269 COM[39] 3853 -374
270 COM[40] 3911 -374
271 COM[41] 3969 -374
272 COM[42] 4027 -374
273 COM[43] 4085 -374
274 COM[44] 4143 -374
275 COM[45] 4201 -374
276 COM[46] 4259 -374
277 COM[47] 4542 -345
278 COM[48] 4542 -287
279 COM[49] 4542 -229
280 COM[50] 4542 -171
281 COM[51] 4542 -113
282 COMS1 4542 -55
ST7565F1‘
ST7565R
Ver 1.7 18/72 2007/06/01
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MPU INTERFACE ( Parallel and Serial )
Command
decoder
Status Bus holder
DISPLAY DATA RAM
65 X 132 = 8580 Bits
Column address circuit
I/O buffer
Page address
circuit
Line address circuit
Display data latch
circuit
Oscillator
circuit
Display timing generator circuit
132 SEGMENT
DRIVERS
64 COMMON
DRIVERS
COM output control circuit
COMS
VSS
V0
V1
V2
V3
V4
V0
VR
VRS
IRS
VOUT
HPM
CAP1N
CAP1P
CAP2N
CAP2P
CAP3N
CAP4P
CAP5P Power Supply
Circuit
VDD2
VSS
Voltage
booster
circuit
Voltage
Regulator
circuit
Voltage
follower
circuit
SEG0
SEG131
COM0
COM63
COMS
CL
DOF
FR
CLS
D7(SI)
D6(SCL)
D5
D4
D3
D2
D1
D0
P/S
C86
CS2
/RES
CS1
A0
RW(/WR)
E(/RD)
SEL3
SEL2
SEL1
VDD
ST7565F1‘ Vo Vo
ST7565R
Ver 1.7 19/72 2007/06/01
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Power Supply Pins
Pin Name I/O Function No. of Pins
VDD Power
Supply Power supply 13
VDD2 Power
Supply Power supply 10
VSS Power
Supply Ground 2
VRS Power
Supply
This is the internal-output VREG power supply for the LCD power supply voltage
regulator. 2
V0, V1,
V2, V3,
V4,Vss
Power
Supply
This is a multi-level power supply for the liquid crystal drive. The voltage Supply applied is
determined by the liquid crystal cell, and is changed through the use of a resistive voltage
divided or through changing the impedance using an op. amp. Voltage levels are
determined based on Vss, and must maintain the relative magnitudes shown below.
V0 V1 V2 V3 V4 Vss
When the power supply turns ON, the internal power supply circuits produce the V1 to V4
voltages shown below. The voltage settings are selected using the LCD bias set
command.
1/65 DUTY 1/49 DUTY 1/33 DUTY 1/55 DUTY 1/53 DUTY
V1
V2
V3
V4
8/9*V0,6/7*V0
7/9*V0,5/7*V0
2/9*V0,2/7*V0
1/9*V0,1/7*V0
7/8*V0,5/6*V0
6/8*V0,4/6*V0
2/8*V0,2/6*V0
1/8*V0,1/6*V0
5/6*V0,4/5*V0
4/6*V0,3/5*V0
2/6*V0,2/5*V0
1/6*V0,1/5*V0
7/8*V0,5/6*V0
6/8*V0,4/6*V0
2/8*V0,2/6*V0
1/8*V0,1/6*V0
7/8*V0,5/6*V0
6/8*V0,4/6*V0
2/8*V0,2/6*V0
1/8*V0,1/6*V0
10
LCD Power Supply Pins
Pin Name I/O Function No. of Pins
CAP1P O DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1N
terminal. 4
CAP1N O DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1P
terminal. 2
CAP2P O DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2N
terminal. 2
CAP2N O DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2P
terminal. 2
CAP3P O DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1N
terminal. 2
CAP4P O
DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2N
terminal. 2
CAP5P O
DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1N
terminal. 2
VOUT O DC/DC voltage converter. Connect a capacitor between this terminal and VSS or VDD
terminal. 2
VR I
Output voltage regulator terminal. Provides the voltage between VSS and V0 through a
resistive voltage divider.
IRS = “L” : the V0 voltage regulator internal resistors are not used.
IRS = “H” : the V0 voltage regulator internal resistors are used.
2
ST7565F1’ A0 : “L": Indwcates Ihat DU :0 D7 are comra‘ data. Tms is the enab‘e clack mputlevmina‘ loB 6800 Series MPU.
ST7565R
Ver 1.7 20/72 2007/06/01
System Bus Connection Pins
Pin Name I/O Function No. of Pins
D5 to D0
D6 (SCL)
D7 (SI)
I/O
This is an 8-bit bi-directional data bus that connects to an 8-bit or 16-bit standard MPU
data bus.
When the serial interface (SPI-4) is selected (P/S = “L”) :
D7 : serial data input (SI) ; D6 : the serial clock input (SCL).
D0 to D5 should be connected to VDD or floating.
When the chip select is not active, D0 to D7 are set to high impedance.
8
A0 I
This is connect to the least significant bit of the normal MPU address bus, and it
determines whether the data bits are data or command.
A0 = “H”: Indicates that D0 to D7 are display data.
A0 = L”: Indicates that D0 to D7 are control data.
1
/RES I When /RES is set to “L”, the register settings are initialized (cleared).
The reset operation is performed by the /RES signal level. 1
CS1B
CS2 I This is the chip select signal. When CS1B = “L” and CS2 = “H”, then the chip select
becomes active, and data/command I/O is enabled. 2
/RD
(E) I
• When connected to 8080 series MPU, this pin is treated as the “/RD” signal of the 8080
MPU and is LOW-active.
The data bus is in an output status when this signal is “L”.
• When connected to 6800 series MPU, this pin is treated as the “E” signal of the 6800
MPU and is HIGH-active.
This is the enable clock input terminal of the 6800 Series MPU.
1
/WR
(R/W) I
• When connected to 8080 series MPU, this pin is treated as the “/WR” signal of the 8080
MPU and is LOW-active.
The signals on the data bus are latched at the rising edge of the /WR signal.
• When connected to 6800 series MPU, this pin is treated as the “R/W” signal of the 6800
MPU and decides the access type :
When R/W = “H”: Read.
When R/W = “L”: Write.
1
C86 I
This is the MPU interface selection pin.
C86 = “H”: 6800 Series MPU interface.
C86 = “L”: 8080 Series MPU interface.
1
P/S I
This pin configures the interface to be parallel mode or serial mode.
P/S = “H”: Parallel data input/output.
P/S = “L”: Serial data input.
The following applies depending on the P/S status:
P/S Data/Command Data Read/Write 4-line SPI Clock
“H” A0 D0 to D7 /RD, /WR X
“L” A0 SI (D7) Write only SCL (D6)
When P/S = “L”, D0 to D5 must be fixed to “H”.
/RD (E) and /WR (R/W) are fixed to either “H” or “L”.
The serial access mode does NOT support read operation.
1
ST7565F1’ “L" Input vegulaled b an ex‘erna‘ resislwe vokage dwidev attached to Ihe VR ‘ermmal /HPM : “L“: ngh powev made (suggested)
ST7565R
Ver 1.7 21/72 2007/06/01
Pin Name I/O Function No. of Pins
CLS I
Selection pin to enable or disable the internal display clock oscillator circuit.
CLS = “H” : use internal oscillator circuit .
CLS = “L” : use external clock input (internal oscillator is disabled).
When CLS = “L”, input the external display clock through the CL terminal.
1
CL I/O
This is the display clock input terminal
The following is true depending on the CLS status.
CLS CL
“H”
“L Output
Input
1
FR O This is the liquid crystal alternating current signal terminal. 1
/DOF O This is the LCD blanking control terminal. 1
IRS I
This terminal selects the resistors for the V0 voltage level adjustment.
IRS = “H”: Use the internal resistors
IRS = “L”: Do not use the internal resistors. The V0 voltage level is
regulated by an external resistive voltage divider attached to the VR terminal
1
/HPM I
This is the power control terminal for the power supply circuit for liquid crystal drive.
/HPM = “H”: Normal mode
/HPM = L”: High power mode (suggested)
1
SEL3
SEL2
SEL1 I
These pins are DUTY selection.
SEL 3, 2, 1 DUTY BIAS
0, 0, 0 1/65 1/9 or 1/7
0, 0, 1 1/49 1/8 or 1/6
0, 1, 0 1/33 1/6 or 1/5
0, 1, 1 1/55 1/8 or 1/6
1, 0, 0 1/53 1/8 or 1/6
1, X, X ----- -----
3
TEST0 ~ 7 I These are terminals for IC testing.
TEST0 ~ 6: left them open.
TEST7 must connected to VDD. 6
ST7565F1‘ dis \a RAM and with Ihe FR si na‘, 3 sin \e \eve‘ \s selec‘edf
ST7565R
Ver 1.7 22/72 2007/06/01
LCD Driver Pins
Pin Name I/O Function No. of Pins
SEG0
to
SEG131
O
These are the LCD segment drive outputs. Through a combination of the contents of the
display RAM and with the FR signal, a single level is selected from VSS, V3, V2, and V0.
Output Voltage
RAM DATA FR Normal Display Reverse Display
H H V0 V2
H L VSS V3
L H V2 V
0
L L V3 Vss
Power save VSS
132
COM0
to
COMn
O
Through a combination of the contents of the scan data and with the FR signal, a single
level is selected from VSS, V4, V1, and V0.
Scan Data FR Output Voltage
H H VSS
H L V0
L H V1
L L V4
Power save VSS
67
COMS O
These are the COM output terminals for the indicator. Both terminals output the same
signal.
Leave these open if they are not used.
2
ST7565R I/O PIN ITO Resister Limitation
PIN Name ITO Resister
CL, FR, /DOF, C86, PSB, HPMB, SEL1…SEL3, CLS, IRS, TEST7 No Limitation
TEST0 ~6, VRS Floating
VDD, VDD2, VSS, VOUT, VR <100
V0, V1, V2, V3, V4, CAP1P, CAP1N, CAP2P, CAP2N, CAP3P, CAP4P, CAP5P <300
CS1B, CS2, /RD, /WR, A0, D0 …D7 <1K
RST <10K
ST7565F1‘
ST7565R
Ver 1.7 23/72 2007/06/01
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Selecting the Interface Type
With the ST7565R chips, data transfers are done through an
8-bit parallel data bus (D7 to D0) or through a 4-line SPI
data input (SI). Through selecting the P/ S terminal polarity
to the “H” or “L” it is possible to select either parallel
data input or 4-line SPI data input as shown in Table 1.
Table 1
P/S /CS1 CS2 A0 /RD /WR C86 D7 D6 D5~D0
H: Parallel Input /CS1 CS2 A0 /RD /WR C86 D7 D6 D5~D0
L: 4-line SPI Input /CS1 CS2 A0 SI SCL (HZ)
“—” indicates fixed to “H”
The Parallel Interface
When the parallel interface has been selected (P/S =“H”),
then it is possible to connect directly to either an 8080-system MPU or a 6800 Series MPU (shown in Table 2)
by selecting the C86 terminal to either “H” or to “L”.
Table 2
C86 (P/S=H) /CS1 CS2 A0 E(/RD) R/W(/WR) D7~D0
H: 6800 Series /CS1 CS2 A0 E R/W D7~D0
L: 8080 Series /CS1 CS2 A0 /RD /WR D7~D0
Moreover, data bus signals are recognized by a combination
of A0, /RD (E), /WR (R/W) signals, as shown in Table 3.
Table 3
Shared 6800 Series 8080 Series
A0 R/W /RD /WR Function
1 1 0 1 Reads the display data
1 0 1 0 Writes the display data
0 1 0 1 Status read
0 0 1 0 Write control data (command)
ST7565R
ST7565R
Ver 1.7 24/72 2007/06/01
The 4-line SPI Interface
When the 4-line SPI interface has been selected (P/S = “L”)
then when the chip is in active state (/CS1 = “L” and CS2 =
“H”) the 4-line SPI data input (SI) and the 4-line SPI clock
input (SCL) can be received. The 4-line SPI data is read from
the 4-line SPI data input pin in the rising edge of the 4-line
SPI clocks D7, D6 through D0, in this order. This data is
converted to 8 bits parallel data in the rising edge of the
eighth 4-line SPI clock for the processing. The A0 input is
used to determine whether or the 4-line SPI data input is
display data or command data; when A0 = “H”, the data is
display data, and when A0 = “L” then the data is command
data. The A0 input is read and used for detection every 8th
rising edge of the 4-line SPI clock after the chip becomes
active. Figure 1 is a 4-line SPI interface signal chart.
1234567891011121314
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2
CS1
CS2
SI
SCL
A0
Figure 1
* When the chip is not active, the shift registers and the counter are reset to their initial states.
* Reading is not possible while in 4-line SPI interface mode.
* Caution is required on the SCL signal when it comes to line-end reflections and external noise. We recommend that operation
be rechecked on the actual equipment.
The Chip Select
The ST7565R have two chip select terminals: /CS1 and
CS2. The MPU interface or the 4-line SPI interface is
enabled only when /CS1 = “L” and CS2 = “H”.
When the chip select is inactive, D0 to D7 enter a high
impedance state, and the A0, /RD, and /WR inputs are
inactive. When the 4-line SPI interface is selected, the shift
register and the counter are reset.
The Accessing the Display Data RAM and the Internal Registers
Data transfer at a higher speed is ensured since the MPU is
required to satisfy the cycle time (tCYC) requirement alone in
accessing the ST7565R. Wait time may not be considered.
And, in the ST7565R, each time data is sent from the MPU, a
type of pipeline process between LSIs is performed through
the bus holder attached to the internal data bus. Internal
data bus.
For example, when the MPU writes data to the display data
RAM, once the data is stored in the bus holder, then it is
written to the display data RAM before the next data write
cycle. Moreover, when the MPU reads the display data RAM,
the first data read cycle (dummy) stores the read data in the
bus holder, and then the data is read from the bus holder to
the system bus at the next data read cycle.
There is a certain restriction in the read sequence of the
display data RAM. Please be advised that data of the
specified address is not generated by the read instruction
issued immediately after the address setup. This data is
generated in data read of the second time. Thus, a dummy
read is required whenever the address setup or write cycle
operation is conducted.
This relationship is shown in Figure 2.
The Busy Flag
When the busy flag is “1” it indicates that the ST7565R is
running internal processes, and at this time no command
aside from a status read will be received. The busy flag is
outputted to D7 pin with the read instruction. If the cycle time
(tCYC) is maintained, it is not necessary to check for this flag
before each command. This makes vast improvements in
MPU processing capabilities possible.
ST7565R ><fi>
ST7565R
Ver 1.7 25/72 2007/06/01
NN+1 N+2 N+3
N+3N+2N+1N
DATA
BUS
Holder
Write
Signal
WR
MPUInternal Timing
Writing
DATA
WR
MPU
Reading
N N n n+1
RD
Preset N Increment N+1 N+2
nn+1Nn+2
Address
Preset
Read
Signal
Column
Address
Bus Holder
Internal Timing
Address
Set #n Dummy
Read Data Read
#n Data Read
#n+1
Figure 2
ST7565F1‘ 83 (H) a a (7 Column Address (7 0 (H)
ST7565R
Ver 1.7 26/72 2007/06/01
Display Data RAM
The display data RAM stores the dot data for the LCD. It has
a 65 (8 page x 8 bit +1) x 132 bit structure.
As is shown in Figure 3, the D7 to D0 display data from the
MPU corresponds to the LCD display common direction;
there are few constraints at the time of display data transfer
when multiple ST7565R are used, thus and display
structures can be created easily and with a high degree of
freedom.
Moreover, reading from and writing to the display RAM from
the MPU side is performed through the I/O buffer, which is
an independent operation from signal reading for the liquid
crystal driver. Consequently, even if the display data RAM is
accessed asynchronously during liquid crystal display, it will
not cause adverse effects on the display (such as flickering).
0
1
0
0
1
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
0
0
0
0
0
D0
D1
D2
D3
D4
-
Display data RAM
COM0
COM1
COM2
COM3
COM4
-
Liquid crystal display
Figure 3
The Page Address Circuit
Page address of the display data RAM is specified through
the Page Address Set Command. The page address must
be specified again when changing pages to perform access.
Page address 8 (D3, D2, D1, D0 = 1, 0, 0, 0) is a special
RAM for icons, and only display data D0 is used.
(see Figure 4)
The Column Addresses
The display data RAM column address is specified by the
Column Address Set command. The specified column
address is incremented (+1) with each display data
read/write command. This allows the MPU display data to be
accessed continuously. Moreover, the incrementing of
column addresses stops with 83H. Because the column
address is independent of the page address, when moving,
for example, from page 0 column 83H to page 1 column 00H,
it is necessary to respective both the page address and the
column address.
Furthermore, as is shown in Table 4, the ADC command
(segment driver direction select command) can be used to
reverse the relationship between the display data RAM
column address and the segment output. Because of this,
the constraints on the IC layout when the LCD module is
assembled can be minimized. As is shown in Figure 4,
Table 4
SEG Output
ADC
SEG0 SEG 131
(D0) “0”
(D0) “1”
0 (H) Column Address 83 (H)
83 (H) Column Address 0 (H)
The Line Address Circuit
The line address circuit, as shown in Table 4, specifies the
line address relating to the COM output when the contents of
the display data RAM are displayed. Using the display start
line address set command, what is normally the top line of
the display can be specified (this is the COM0 output when
the common output mode is normal, and the COM63 output
for ST7565R, the detail is shown page.11 The display area
is a 65 line area for the ST7565R.
If the line addresses are changed dynamically using the
display start line address set command, screen scrolling,
page swapping, etc. can be performed.
ST7565F1‘ ED
ST7565R
Ver 1.7 27/72 2007/06/01
Page Address
D3 D2 D1 D0 Data Line
Address When the common
output is normal COM
Output
D0 00H COM0
D1 01H COM1
D2 02H COM2
D3 03H COM3
D4 04H COM4
D5 05H COM5
D6 06H COM6
0 0 0 0
D7
Page 0
07H COM7
D0 08H COM8
D1 09H COM9
D2 0AH COM10
D3 0BH COM11
D4 0CH COM12
D5 0DH COM13
D6 0EH COM14
0 0 0 1
D7
Page 1
0FH COM15
D0 10H COM16
D1 11H COM17
D2 12H COM18
D3 13H COM19
D4 14H COM20
D5 15H COM21
D6 16H COM22
0 0 1 0
D7
Page 2
17H COM23
D0 18H COM24
D1 19H COM25
D2 1AH COM26
D3 1BH COM27
D4 1CH COM28
D5 1DH COM29
D6 1EH COM30
0 0 1 1
D7
Page 3
1FH COM31
D0 20H COM32
D1 21H COM33
D2 22H COM34
D3 23H COM35
D4 24H COM36
D5 25H COM37
D6 26H COM38
0 1 0 0
D7
Page 4
27H COM39
D0 28H COM40
D1 29H COM41
D2 2AH COM42
D3 2BH COM43
D4 2CH COM44
D5 2DH COM45
D6 2EH COM46
0 1 0 1
D7
Page 5
2FH COM47
D0 30H COM48
D1 31H COM49
D2 32H COM50
D3 33H COM51
D4 34H COM52
D5 35H COM53
D6 36H COM54
0 1 1 0
D7
Page 6
37H COM55
D0 38H COM56
D1 39H COM57
D2 3AH COM58
D3 3BH COM59
D4 3CH COM60
D5 3DH COM61
D6 3EH COM62
0 1 1 1
D7
Page 7
3FH
COM63
1 0 0 0 D0 Page 8 COMS
00
01
02
03
04
05
06
07
08
7B
7C
7D
7E
7F
80
81
82
83
0
D0
83
82
81
80
7F
7E
7D
7C
7B
08
07
06
05
04
03
02
01
00
1
D0
ADC
Column
address
Regardless of the display
start line address,
1/65duty => 64th line,
1/49duty =>48th line.
S0
S1
S2
S3
S4
S5
S6
S7
S8
S123
S124
S125
S126
S127
S128
S129
S130
S131
LCD
Out
1/33duty =>32th line,
1/55duty =>54th line,
1/53duty =>52th line.
Figure 4
ST7565R a
ST7565R
Ver 1.7 28/72 2007/06/01
The Display Data Latch Circuit
The display data latch circuit is a latch that temporarily
stores the display data that is output to the liquid crystal
driver circuit from the display data RAM.
Because the display normal/reverse status, display ON/OFF
status, and display all points ON/OFF commands control
only the data within the latch, they do not change
the data within the display data RAM itself.
The Oscillator Circuit
This is a CR-type oscillator that produces the display clock.
The oscillator circuit is only enabled when CLS = “H”. When CLS = “L” the oscillation stops, and the external
clock is input through the CL terminal.
Display Timing Generator Circuit
The display timing generator circuit generates the timing
signal to the line address circuit and the display data latch
circuit using the display clock. The display data is latched
into the display data latch circuit synchronized with the
display clock, and is output to the data driver output terminal.
Reading to the display data liquid crystal driver circuits is
completely independent of accesses to the display data
RAM by the MPU. Consequently, even if the display data
RAM is accessed asynchronously during liquid crystal
display, there is absolutely no adverse effect (such as
flickering) on the display.
Moreover, the display timing generator circuit generates the
common timing and the liquid crystal alternating current
signal (FR) from the display clock. It generates a drive wave
form using a 2 frame alternating current drive method, as is
shown in Figure 5, for the liquid crystal drive circuit.
Two-frame alternating current drive waveform
6465123456 606162636465123456
V0
V1
V4
VSS
COM0
V0
V1
V4
Vss
COM1
VSS
V3
V2
V0
RAM
Data
SEGn
FR
CL
Figure 5
ST7565F1‘ \ ~> COMGS ~> COMO a COM47 4» COMO » COMS‘ ~> COMO a COMES ~> COMO » COMS‘ ~> COMO
ST7565R
Ver 1.7 29/72 2007/06/01
The Common Output Status Select Circuit
In the ST7565R chips, the COM output scan direction can be
selected by the common output status select command. (See Table 6.) Consequently, the constraints in IC layout at
the time of LCD module assembly can be minimized.
Table 6
COM Scan Direction
Status 1/65 DUTY 1/49 DUTY 1/33 DUTY 1/55 DUTY 1/53 DUTY
Normal
Reverse
COM0 COM63
COM63 COM0
COM0 COM47
COM47 COM0 COM0 COM31
COM31 COM0 COM0 COM53
COM53 COM0
COM0 COM51
COM51 COM0
Common output pins
Duty COM
dir COM[0:15] COM[16:23] COM[24:26] COM[27:36] COM[37:39] COM[40:47] COM[48:63]
0 COM[0:63]
1/65 1 COM[63:0]
0 COM[0:23] Reserved COM[24:47]
1/49 1 COM[47:24] Reserved COM[23:0]
0 COM[0:15] Reserved COM[16:31]
1/33 1 COM[31:16] Reserved COM[15:0]
0 COM[0:26] Reserved COM[27:53]
1/55 1 COM[53:27] Reserved COM[26:0]
0 COM[0:25] Reserved COM[26:51]
1/53 1 COM[51:26] Reserved COM[25:0]
ST7565F1’
ST7565R
Ver 1.7 30/72 2007/06/01
The LCD Driver Circuits
These are a 187-channel that generates four voltage levels
for driving the LCD . The combination of the display data, the
COM scan signal, and the FR signal produces the liquid
crystal drive voltage output.
Figure 6 shows examples of the SEG and COM output
wave form.
SEG 0 1
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
VDD
VSS
M
V0
V1
V2
V3
V4
VSS
COM0
to
SEG1 -V4
-V3
-V2
-V1
-V0
V0
V1
V2
V3
V4
VSS
COM0
to
SEG0 -V4
-V3
-V2
-V1
-V0
V0
V1
V2
V3
V4
VSS
COM2
COM1
V0
V1
V2
V3
V4
VSS
V0
V1
V2
V3
V4
VSS
COM0
COM0
COM15
234
V0
V1
V2
V3
V4
VSS
SEG0
V0
V1
V2
V3
V4
VSS
SEG1
Figure 6
ST7565F1’ voltage follower mun ave used
ST7565R
Ver 1.7 31/72 2007/06/01
The Power Supply Circuits
The power supply circuits are low-power consumption power
supply circuits that generate the voltage levels required for
the LCD drivers. They are Booster circuits, voltage regulator
circuits, and voltage follower circuits. The power supply
circuits can turn the Booster circuits, the voltage regulator
circuits, and the voltage follower circuits ON or OFF
independently through the use of the Power Control Set
command. Consequently, it is possible to make an external
power supply and the internal power supply function
somewhat in parallel. Table 7 shows the Power Control Set
Command 3-bit data control function, and Table 8 shows
reference combinations.
Table 7
bit function Status
“1” “0”
D2
D1
D0
Booster circuit control bit
Voltage regulator circuit control bit (V/R circuit)
Voltage follower circuit control bit (V/F circuit)
ON OFF
ON OFF
ON OFF
The Control Details of Each Bit of the Power Control Set Command
Table 8
Use Settings D2 D1 D0 Voltage
booster
Voltage
regulator
Voltage
follower
External
voltage
input
Step-up
voltage
Only the internal power supply is used 1 1 1 ON ON ON VDD2 Used
Only the voltage regulator circuit and the
voltage follower circuit are used 0 1 1 OFF ON ON VOUT, VDD2 Open
Only the V/F circuit is used 0 0 1 OFF OFF ON V0, VDD2 Open
Only the external power supply is used 0 0 0 OFF OFF OFF V0 to V4 Open
Reference Combinations
* The “step-up system terminals” refer CAP1N, CAP1P, CAP2N, CAP2P, and CAP3N.
* While other combinations, not shown above, are also possible, these combinations are not recommended
because they have no practical use.
The Step-up Voltage Circuits
Using the step-up voltage circuits equipped within the
ST7565R chips it is possible to product a 2X,3X,4X,5X or 6X
step-up of the VSS – VDD2 voltage levels.
6X step-up: Connect capacitor C1 between CAP1N and
CAP1P, between CAP2N and CAP2P, between
CAP1N and CAP3P, between CAP2N and
CAP4P,between CAP1N and CAP5P, and
between VDD2 and VOUT, to produce a voltage
level in the positive direction at the VOUT
terminal that is 6 times the voltage level
between VSS and VDD2.
5X step-up: Connect capacitor C1 between CAP1N and
CAP1P, between CAP2N and CAP2P, between
CAP1N and CAP3P, between CAP2N and
CAP4P,and between VDD2 and VOUT, to
produce a voltage level in the positive direction
at the VOUT terminal that is 5 times the voltage
level between VSS and VDD2.
4X step-up: Connect capacitor C1 between CAP1N and
CAP1P, between CAP2N and CAP2P, between
CAP1N and CAP3P, and between VDD2 and
VOUT, to produce a voltage level in the positive
direction at the VOUT terminal that is 4 times the
voltage level between VSS and VDD2.
3X step-up: Connect capacitor C1 between CAP1N and
CAP1P, between CAP2N and CAP2P and between
VDD2 and VOUT, and short between CAP3P and
VOUT to produce voltages level in the positive direction
at the VOUT terminal that is 3 times the voltage difference
between VSS and VDD2.
2X step-up: Connect capacitor C1 between CAP1N and
CAP1P, and between VDD2 and VOUT, leave
CAP2N open, and short between CAP2P,
CAP3P and VOUT to produce a voltage in the
positive direction at the VOUT terminal that Is
twice the voltage between VSS and VDD2.
The step-up voltage relationships are shown in Figure 7.
ST7565F1’ gamma.» 5 55 5 gamma.» : 55 gamma.» I— l— madam!» 5 55 55 madam!»
ST7565R
Ver 1.7 32/72 2007/06/01
2x voltage booster circuit
CAP1N
CAP1P
C1
CAP5POPEN
VDD2 or VSS
VOUT
C1
CAP2NOPEN
CAP4POPEN
CAP2P
CAP3P
3x voltage booster circuit
CAP1N
CAP1P
C1
CAP5POPEN
VDD2 or VSS
VOUT
C1
CAP4POPEN
CAP3P
CAP2N
CAP2P
C1
3x boost voltage relationship
VSS
VDD2
VOUT<=3xVDD2
Do NOT over voltage
limitation
2x boost voltage relationship
VSS
VDD2
VOUT<=2xVDD2
Do NOT over voltage
limitation
4x voltage booster circuit
CAP1N
CAP1P
C1
CAP5POPEN
VDD2 or VSS
VOUT
C1
CAP4POPEN
CAP2N
CAP2P
C1
CAP3P
C1
4x boost voltage relationship
VSS
VDD2
VOUT<=4xVDD2
Do NOT over voltage
limitation
5x voltage booster circuit
CAP1N
CAP1P
C1
CAP5POPEN
VDD2 or VSS
VOUT
C1
CAP4P
CAP2N
CAP2P
C1
CAP3P
C1
C1
5x boost voltage relationship
VSS
VDD2
VOUT<=5xVDD2
Do NOT over voltage
limitation
6x boost voltage relationship
VSS
VDD2
VOUT<=6xVDD2
Do NOT over voltage
limitation
6x voltage booster circuit
CAP1N
CAP1P
C1
VDD2 or VSS
VOUT
C1
CAP4P
CAP2N
CAP2P
C1
CAP3P
C1
C1
CAP5P
C1
Figure 7
* The VDD2 voltage range must be set so that the VOUT terminal voltage does not exceed the absolute maximum rated value.
* The maximum voltage of the booster capacitor terminals are :
VMAX: CAP5P > CAP4P > CAP3P > CAP2P > CAP1P > CAP2N = CAP1N.
ST7565R
ST7565R
Ver 1.7 33/72 2007/06/01
The Voltage Regulator Circuit
The step-up voltage generated at VOUT outputs the LCD
driver voltage V0 through the voltage regulator circuit.
Because the ST7565R chips have an internal high-accuracy
fixed voltage power supply with a 64-level electronic volume
function and internal resistors for the V0 voltage regulator,
systems can be constructed without having to include
high-accuracy voltage regulator circuit components.
(VREG thermal gradients approximate -0.05%/°C)
(A) When the V0 Voltage Regulator Internal Resistors Are Used
Through the use of the V0 voltage regulator internal resistors
and the electronic volume function the liquid crystal power
supply voltage V0 can be controlled by commands alone
(without adding any external resistors), making it possible to
adjust the liquid crystal display brightness. The V0 voltage
can be calculated using equation A-1 over the range where
| V0 | < | VOUT |.
()
Rb
Ra
+1 VEVV0=
=()
Rb
Ra
+1 (1-
α
162)VREG
[
VEV =(1-
α
162)VREG]
Internal Ra VEV(constant voltage supply+electronic volume)
VSS
V0
Internal Rb
Figure 8
VREG is the IC-internal fixed voltage supply, and its voltage at Ta = 25°C is as shown in Table 9.
Table 9
Part no. Equipment Type Thermal Gradient VREG
ST7565R Internal Power Supply –0.05 %/°C 2.1V
α is set to 1 level of 64 possible levels by the electronic volume function depending on the data set in the 6-bit electronic
volume registers. Table 10 shows the value for α depending on the electronic volume register settings.
Rb/Ra is the V0 voltage regulator internal resistor ratio, and can be set to 8 different levels through the V0 voltage regulator
internal resistor ratio set command. The (1 + Rb/Ra) ratio assumes the values shown in Table 11 depending on the 3-bit data
settings in the V0 voltage regulator internal resistor ratio register.
ST7565R
ST7565R
Ver 1.7 34/72 2007/06/01
Table 10
D5 D4 D3 D2 D1 D0 α
0 0 0 0 0 0
0 0 0 0 0 1
0 0 0 0 1 0
:
:
1 1 1 1 0 1
1 1 1 1 1 0
1 1 1 1 1 1
63
62
61
:
:
2
1
0
V0 voltage regulator internal resistance ratio register value and (1 + Rb/Ra) ratio (Reference value)
Table 11
Register ST7565R
D2 D1 D0 (1) –0.05 %/°C
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
Figures 9, 10 show V0 voltage measured by values of the internal resistance ratio resistor for V0 voltage adjustment and electric
volume resister for each temperature grade model.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
00H 1FH 3FH
V0
UNIT:V
000
001
010
011
100
101
110
111
V0 voltage regulator
internal resistor ratio
set D2,D1,D0
Electronic volume
registered
D5 ~ D0
Ta = 25 °C and booster off ,regulator,follower on
VDD=3V
Figure 9 : (1) For ST7565R the Thermal Gradient = -0.05%/°C
The V0 voltage as a function of the V0 voltage regulator internal resistor ratio register and the electronic volume register.
Setup example: When selecting Ta = 25°C and V0 = 7V for an ST7565R on which Temperature gradient = –0.05%/°C.
Using Figure 9 and the equation A-1, the following setup is enabled.
At this time, the variable range and the notch width of the V0 voltage is, as shown Table 13, as dependent on the electronic
volume.
ST7565F1’ E‘ectromc Vo‘ume Ru’
ST7565R
Ver 1.7 35/72 2007/06/01
Table 12
Register
Contents D5 D4 D3 D2 D1 D0
For V0 voltage regulator
Electronic Volume
— — — 0 1 0
1 0 0 1 0 1
Table 13
V0 Min Typ Max Units
Variable Range
Notch width 5.1 (63 levels) 7.0 (central value) 8.4 (0 level) [V]
51 [mV]
(B) When an External Resistance is Used (The V0 Voltage Regulator Internal Resistors Are Not Used) (1)
The liquid crystal power supply voltage V0 can also be set
without using the V0 voltage regulator internal resistors (IRS
terminal = “L”) by adding resistors Ra’ and Rb’ between VDD
and VR, and between VR and V0, respectively. When this is
done, the use of the electronic volume function makes it
possible to adjust the brightness of the liquid crystal display
by controlling the liquid crystal power supply voltage V0
through commands.
In the range where | V0 | < | VOUT |, the V0 voltage can be
calculated using equation B-1 based on the external
resistances Ra’ and Rb’.
()
Rb'
Ra'
+1 VEVV0=
=()
Rb'
Ra'
+1 (1-
α
162)VREG
[
VEV =(1-
α
162)VREG]
External
resistor Ra'
VEV(fixed voltage power supply+electronic volume)
VSS
V0
External
resistor Rb'
Figure 11
Setup example: When selecting Ta = 25°C and V0 = 7 V for
ST7565R the temperature gradient = –0.05%/°C.
When the central value of the electron volume register is
(D5, D4, D3, D2, D1, D0) = (1, 0, 0, 0, 0, 0), then α = 31 and
VREG = 2.1V so, according to equation B-1,
=()
Rb'
Ra'
+1 (1- 31
162)(2.1)7V
=()
Rb'
Ra'
+1 (1-
α
162)VREGV0
Moreover, when the value of the current running through
Ra’ and Rb’ is set to 5 uA,
Ra’ + Rb’ = 1.4M (Equation B-3)
Consequently, by equations B-2 and B-3,
=
Rb'
Ra' 3.12
Ra' = 340k
Ω
Rb' = 1060k
Ω
ST7565R m m ' 152' [6.7 ' RI+R2 ' M2
ST7565R
Ver 1.7 36/72 2007/06/01
At this time, the V0 voltage variable range and notch width, based on the electron volume function, is as given in Table 14.
Table 14
V0 Min Typ Max Units
Variable Range
Notch width 5.3 (63 levels) 7.0 (central value) 8.6 (0 level) [V]
52 [mV]
(C) When External Resistors are Used (The V0 Voltage Regulator Internal Resistors Are Not Used) (2)
When the external resistor described above are used,
adding a variable resistor as well makes it possible to
perform fine adjustments on Ra’ and Rb’, to set the liquid
crystal drive voltage V0. In this case, the use of the electronic
volume function makes it possible to control the liquid crystal
power supply voltage V0 by commands to adjust the liquid
crystal display brightness.
In the range where | V0 | < | VOUT | the V0 voltage can be
calculated by equation C-1 below based on the R1 and R2
(variable resistor) and R3 settings, where R2 can
be subjected to fine adjustments (Δ R2).
()
R3+R2-
Δ
R2
R1+
Δ
R2
+1 VEVV0=
=()
+1 (1-
α
162)VREG
[
VEV =(1-
α
162)VREG]
R3+R2-
Δ
R2
R1+
Δ
R2
External
resistor R1
VEV(fixed voltage power supply+electronic volume)
VSS
V0
External
resistor R3
VR
ΔR2
External
resistor R2
Rb'
Ra'
Figure 12
Setup example: When selecting Ta = 25°C and V0= 5 to 9 V
(using R2) for an ST7565R the temperature gradient
= –0.05%/°C.
When the central value for the electronic volume register is
set at (D5, D4, D3, D2, D1, D0) = (1, 0, 0, 0, 0, 0), then α =
31 and VREG = 2.1 V so, according to equation C-1, when Δ
R2 = 0 Ω, in order to make V0 = 9 V,
(R3+R2
R1
+19V = ) (1- 31
162)(2.1)
When ΔR2 = R2, in order to make V = –5 V,
(R3
R1+R2
+15V = ) (1- 31
162)(2.1)
When the current flowing VDD and V0 is set to 5 uA,
R1 + R2 + R3 = 1.4M (Equation C-4)
With this, according to equation C-2, C-3 and C-4,
R1 = 264k
Ω
R2 = 211k
Ω
R3 = 925k
Ω
The V0 voltage variable range and notch width based on the
electron volume function is as shown in Table 15.
ST7565F1’ ya V
ST7565R
Ver 1.7 37/72 2007/06/01
Table 15
V0 Min Typ Max Units
Variable Range
Notch width 5.3 (63 levels) 7.0 (central value) 8.7 (0 level) [V]
53 [mV]
* When the V0 voltage regulator internal resistors or the electronic volume function is used, it is necessary to at least set the
voltage regulator circuit and the voltage follower circuit to an operating mode using the power control set commands.
Moreover, it is necessary to provide a voltage from VOUT when the Booster circuit is OFF.
* The VR terminal is enabled only when the V0 voltage regulator internal resistors are not used (i.e. the IRS terminal = “L”).
When the V0 voltage regulator internal resistors are used (i.e. when the IRS terminal = “H”), then the VR terminal is left open.
* Because the input impedance of the VR terminal is high, it is necessary to take into consideration short leads, shield cables,
etc. to handle noise.
The LCD Voltage Generator Circuit
The V0 voltage is produced by a resistive voltage divider
within the IC, and can be produced at the V1, V2, V3, and V4
voltage levels required for liquid crystal driving. Moreover,
when the voltage follower changes the impedance, it
provides V1, V2, V3 and V4 to the liquid crystal drive circuit.
High Power Mode
The power supply circuit equipped in the ST7565R chips has
very low power consumption (normal mode: HPM = “H”).
However, for LCD panels with large loads (size), this
low-power power supply may cause display quality to
degrade. When this occurs, set the HPM terminal to “L”
(high power mode) can improve the display quality.
SITRONIX recommends that the display be checked on
actual equipment to determine whether or not to use this
mode. Moreover, if the improvement to the display is
inadequate even after high power mode has been set, then it
is necessary to add a liquid crystal drive power supply
externally.
The Internal Power Supply Shutdown Command Sequence
The sequence shown in Figure 13 is recommended for
shutting down the internal power supply, first placing the
internal power supply in power saver mode and then turning
the internal power supply OFF. The power consumption can
be reduced by this sequence. Please refer to the “Sleep
Mode Set” section for the detailed power saving information.
Sequence Details Command address
(Command, status) D7 D6 D5 D4 D3 D2 D1 D0
Step1 Display OFF 1 0 1 0 1 1 1 0 Power saver
Step2 Display all points ON 1 0 1 0 0 1 0 1 commands
End Internal power supply OFF (compound)
Figure 13
ST7565F1’ : i :5 5E? REFER :5 5 PER: fig???
ST7565R
Ver 1.7 38/72 2007/06/01
Reference Circuit Examples
1. When used all of the step-up circuit, voltage regulating circuit and V/F circuit
(1) When the voltage regulator internal resistor
is used.
(Example where VDD2 = VDD, with 4x step-up)
(2) When the voltage regulator internal resistor
is not used.
(Example where VDD2 = VDD, with 4x step-up)
VDD2 or VSS
VOUT
CAP3P
CAP1N
CAP1P
CAP2N
CAP2P
VR
ST7565R
IRS M/S
C1
C1
C1
C1
VDD
VDD2 or VSS
CAP3P
CAP1N
CAP1P
CAP2N
CAP2P
VR
VSS
V1
V2
V3
V4
V0
ST7565R
IRS M/S
C1
C1
C1
VDD
R3
R2
R1
CAP4P
CAP5P
CAP4P
CAP5P
VDD2 or VSS
V1
V2
V3
V4
V0
VDD2 or VSS
VSS
C2
C2
C2
C2
C2
C2
C2
C2
C2
C2
VDD2 or VSS
VOUT
C1VDD2 or VSS
VSS
2. When the voltage regulator circuit and V/F circuit alone are used
(1) When the V0 voltage regulator internal resistor
is not used. (2) When the V0 voltage regulator internal resistor
is used.
VDD2 or VSS
VOUT
CAP3P
CAP1N
CAP1P
CAP2N
CAP2P
VR
ST7565R
IRS M/S
VDD2 or VSS
CAP4P
CAP5P
VDD2 or VSS
V1
V2
V3
V4
V0
C2
C2
C2
C2
C2
VSS
External
power
supply
R3
R2
R1
VDD2 or VSS
VOUT
CAP3P
CAP1N
CAP1P
CAP2N
CAP2P
VR
ST7565R
IRS M/S
VDD
VDD2 or VSS
CAP4P
CAP5P
VDD2 or VSS
V1
V2
V3
V4
V0
C2
C2
C2
C2
C2
VSS
External
power
supply
VDDVSS
ST7565F1’ ‘%—V ‘— 4H7 4H7 4H7 4H7
ST7565R
Ver 1.7 39/72 2007/06/01
(3) When the V/F circuit alone is used (4) When the built-in power is not used
VSS
VOUT
CAP3P
CAP1N
CAP1P
CAP2N
CAP2P
VR
ST7565R
IRS M/S
VDD
External power supply
CAP4P
CAP5P
VDD2 or VSS
V0
V1
V2
V3
V4
VSSVDD2 or VSS
VOUT
CAP3P
CAP1N
CAP1P
CAP2N
CAP2P
VR
ST7565R
IRS M/S
VDD
VDD2 or VSS
CAP4P
CAP5P
VDD2 or VSS
V1
V2
V3
V4
V0
C2
C2
C2
C2
C2
VSS
External
power
supply
VDD2 or VSS
VSS
Item Set value unit
C1
C2 1 ~ 2.2
0.1 ~ 1 uF
uF
Note:
z C1 ~ C2 are determined by the size of the LCD being driven.
z The recommended panel size is smaller than 1.8”.
z If the panel loading is too heavy and cause poor display quality, adding V0 capacitor can improve display quality.
* 1. Because the VR terminal input impedance is high, use short leads and shielded lines.
* 2. C1 ~ C2 are determined by the LCD loading (size). Select a suitable value that matches the module.
Example of the Process by which to Determine the Settings:
• Turn the voltage regulator circuit and voltage follower circuit ON and supply a voltage to VOUT from the outside.
• Determine C2 by displaying an LCD pattern with a heavy load (such as horizontal stripes) and selecting the capacitor that
stabilizes the liquid crystal drive voltages (V0 to V4). Note that all C2 capacitors must have the same capacitance value.
• Next, remove external VOUT and turn all internal power supplies ON and then select C1.
ST7565F1’
ST7565R
Ver 1.7 40/72 2007/06/01
The Reset Circuit
When the /RES input comes to the “L” level, these LSIs
return to the default state. Their default states are as follows:
1. Display OFF
2. Normal display
3. ADC select: Normal (ADC command D0 = “L”)
4. Power control register: (D2, D1, D0) = (0, 0, 0)
5. 4-line SPI interface internal register data clear
6. LCD power supply bias rate:
1/65 DUTY = 1/9 bias
1/49,1/55,1/53 DUTY = 1/8 bias
1/33 DUTY = 1/6 bias
7. Power saving clear
8. V0 voltage regulator internal resistors Ra and Rb
separation
9. Output conditions of SEG and COM terminals
SEG=VSS, COM=VSS
10. Read modify write OFF
11. Display start line set to first line
12. Column address set to Address 0
13. Page address set to Page 0
14. Common output status normal
15. V0 voltage regulator internal resistor ratio set mode clear
16. Electronic volume register set mode clear Electronic
volume register :
(D5, D4, D3, D2, D1, D0) = (1, 0. 0, 0, 0,0)
17. Test mode clear
On the other hand, when the reset command is used, the
above default settings from 11 to 17 are only executed.
When the power is turned on, the IC internal state becomes
unstable, and it is necessary to initialize it using the /RES
terminal. After the initialization, each input terminal should
be controlled normally.
Moreover, when the control signal from the MPU is in the
high impedance, an over current may flow to the IC. After
applying a current, it is necessary to take proper measures
to prevent the input terminal from getting into the high
impedance state.
If the internal liquid crystal power supply circuit is not used
on ST7565R,it is necessary that /RES is “H” when the
external liquid crystal power supply is turned on. This IC has
the function to discharge V0 when /RES is “L,” and the
external power supply short-circuits to Vss when /RES is “L.”
While /RES is “L,” the oscillator and the display timing
generator stop, and the CL, FR and /DOF terminals are fixed
to “H.” The terminals D0 to D7 are not affected. The VSS level
is output from the SEG and COM output terminals. This
means that an internal resistor is connected between
VSS and V0.
When the internal liquid crystal power supply circuit is not
used on other models of ST7565R series, it is necessary
that /RES is “L” when the external liquid crystal power supply
is
turned on.
While /RES is “L,” the oscillator works but the display timing
generator stops, and the CL, FR and /DOF terminals are
fixed to “H.” The terminals D0 to D7 are not affected.
ST7565F1’ Tms command turns the display ON and OFF. WR WR WR
ST7565R
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The ST7565R identify the data bus signals by a combination of A0, /RD (E), /WR(R/W) signals. Command interpretation and
execution does not depend on the external clock, but rather is performed through internal timing only, and
thus the processing is fast enough that normally a busy check is not required.
In the 8080 MPU interface, commands are launched by inputting a low pulse to the RD terminal for reading, and inputting a low
pulse to the /WR terminal for writing. In the 6800 Series MPU interface, the interface is placed in a read mode when an “H”
signal is input to the R/W terminal and placed in a write mode when a “L” signal is input to the R/W terminal and then the
command is launched by inputting a high pulse to the E terminal. Consequently, the 6800 Series MPU interface is different than
the 80x86 Series MPU interface in that in the explanation of commands and the display commands the status read and display
data read /RD (E) becomes “1(H)”. In the explanations below the commands are explained using the 8080 Series MPU
interface as the example.
When the 4-line SPI interface is selected, the data is input in sequence starting with D7.
<Explanation of Commands>
Display ON/OFF
This command turns the display ON and OFF.
E R/W
A0 /RD /WR D7 D6 D5 D4 D3 D2 D1 D0 Setting
0 1 0
1 0 1 0 1 1 1 1
0
Display ON
Display OFF
When the display OFF command is executed when in the display all points ON mode, sleep mode is entered. See the
section on the Sleep Mode Set for details.
Display Start Line Set
This command is used to specify the display start line address of the display data RAM shown in Figure 4. For further details
see the explanation of this function in “The Line Address Circuit”.
E R/W
A0 /RD /WR D7 D6 D5 D4