CC1150 Datasheet by Texas Instruments

View All Related Products | Download PDF Datasheet
i TEXAS INSTRUMENTS
Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
CC1150
SWRS037B –JANUARY 2006REVISED MARCH 2015
CC1150 Low Power Sub-1 GHz RF Transmitter
1 Device Overview
1.1 Features
1
Small Size 64-byte TX Data FIFO
QLP 4-mm × 4-mm Package, 16 Pins Suited for Systems Compliant with EN 300 220
and FCC CFR Part 15
True Single Chip UHF RF Transmitter Many Powerful Digital Features Allow a High-
Frequency Bands performance RF system to be made Using an
300 to 348 MHz Inexpensive Microcontroller
400 to 464 MHz Efficient SPI interface: All Registers Can be
800 to 928 MHz Programmed With One "Burst" Transfer
Programmable Data Rate Up to 500 kBaud Integrated Analog Temperature Sensor
Low Current Consumption Lead-free “Green” Package
Programmable Output Power Up to +10 dBm for Flexible Support for Packet Oriented Systems
All Supported Frequencies On-chip Support for Sync-Word Insertion,
Programmable Baseband Modulator Flexible Packet Length and Automatic CRC
Ideal For Multi-channel Operation Handling
Very Few External Components OOK and Flexible ASK Shaping Supported
Completely On-chip Frequency Synthesizer 2-FSK, GFSK and MSK Supported
No External Filters Needed Optional Automatic Whitening of Data
Configurable Packet Handling Hardware Support for Asynchronous Transparent Transmit
Suitable for Frequency Hopping Systems Due to a Mode for Backwards Compatibility with Existing
Fast Settling Frequency Synthesizer Radio Communication Protocols
Optional Forward Error Correction with Interleaving
1.2 Applications
Ultra-low Power UHF Wireless Transmitters Low Power Telemetry
Operating in the 315-, 433-, 868-, and 915-MHz Home and Building Automation
ISM/SRD bands Wireless Alarm and Security Systems
AMR – Automatic Meter Reading Industrial Monitoring and Control
Consumer Electronics Wireless Sensor Networks
RKE – Remote Keyless Entry
1.3 Description
The CC1150 is a true single-chip UHF transmitter designed for very low power wireless applications. The
circuit is mainly intended for the ISM (Industrial, Scientific and Medical) and SRD (Short Range Device)
frequency bands at 315-, 433-, 868-, and 915-MHz, but can easily be programmed for operation at other
frequencies in the 300 to 348 MHz, 400 to 464 MHz and 800 to 928 MHz bands.
The RF transmitter is integrated with a highly configurable baseband modulator. The modulator supports
various modulation formats and has a configurable data rate up to 500 kBaud. The CC1150 device
provides extensive hardware support for packet handling, data buffering and burst transmissions.
The main operating parameters and the 64-byte transmit FIFO of CC1150 can be controlled via an SPI
interface. In a typical system, the CC1150 device will be used together with a microcontroller and a few
additional passive components.
CC1150 is part of the SmartRF™ technology platform based on 0.18-μm CMOS technology from Texas
Instruments.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
l TEXAS INSTRUMENTS ® , {ATEST} ‘ u‘ i I RBIAS xoscfi1 xoscfiz
BIAS
XOSC_Q1 XOSC_Q2
XOSC
FREQ
SYNTH
RADIO CONTROL
RF_P
RF_N
CSn
SI
SO (GDO1)
SCLK
GDO0 (ATEST)
RBIAS
PA
FEC /
INTERLEAVER
PACKET
HANDLER
MODULATOR
TX FIFO
DIGITAL
INTERFACE
TO MCU
CC1150
SWRS037B JANUARY 2006REVISED MARCH 2015
www.ti.com
Table 1-1. Device Information(1)
PART NUMBER PACKAGE BODY SIZE
CC1150 VQFNP (16) 4.00 mm × 4.00 mm
(1) For more information, see Section 8,Mechanical Packaging and Orderable Information.
1.4 Functional Block Diagram
2Device Overview Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS \u-mx mm
CC1150
www.ti.com
SWRS037B –JANUARY 2006REVISED MARCH 2015
Table of Contents
1 Device Overview ......................................... 15.7 Data Rate Programming ............................ 18
1.1 Features .............................................. 15.8 Packet Handling Hardware Support................. 19
1.2 Applications........................................... 15.9 Modulation Formats ................................. 23
1.3 Description............................................ 15.10 Forward Error Correction with Interleaving.......... 24
1.4 Functional Block Diagram ............................ 25.11 Radio Control........................................ 26
2 Revision History ......................................... 45.12 Data FIFO ........................................... 29
3 Terminal Configuration and Functions.............. 55.13 Frequency Programming ........................... 31
3.1 Pin Attributes ......................................... 55.14 VCO ................................................. 31
4 Specifications ............................................ 65.15 Voltage Regulators.................................. 32
4.1 Absolute Maximum Ratings .......................... 65.16 Output Power Programming......................... 32
4.2 ESD Ratings.......................................... 65.17 General Purpose and Test Output Control Pins .... 33
4.3 Recommended Operating Conditions ................ 65.18 Asynchronous and Synchronous Serial Operation.. 35
4.4 General Characteristics .............................. 65.19 System Considerations and Guidelines ............. 36
4.5 Current Consumption................................. 75.20 Memory.............................................. 38
4.6 RF Transmit .......................................... 76 Applications, Implementation, and Layout........ 51
4.7 Crystal Oscillator ..................................... 86.1 Application Information .............................. 51
4.8 Frequency Synthesizer Characteristics .............. 86.2 Design Requirements ............................... 53
4.9 Analog Temperature Sensor ......................... 96.3 PCB Layout Recommendations..................... 55
4.10 DC Characteristics ................................... 97 Device and Documentation Support ............... 58
4.11 Power-On Reset .................................... 10 7.1 Device Support ...................................... 58
4.12 Thermal Resistance Characteristics for VQFNP 7.2 Documentation Support ............................. 58
Package ............................................. 10 7.3 Trademarks.......................................... 59
5 Detailed Description ................................... 11 7.4 Electrostatic Discharge Caution..................... 59
5.1 Overview ............................................ 11 7.5 Export Control Notice ............................... 59
5.2 Functional Block Diagram........................... 11 7.6 Glossary ............................................. 59
5.3 Configuration Overview ............................. 11 8 Mechanical Packaging and Orderable
5.4 Configuration Software.............................. 12 Information .............................................. 59
5.5 4-wire Serial Configuration and Data Interface ..... 13 8.1 Packaging Information .............................. 59
5.6 Microcontroller Interface and Pin Configuration..... 17
Copyright © 2006–2015, Texas Instruments Incorporated Table of Contents 3
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS
CC1150
SWRS037B JANUARY 2006REVISED MARCH 2015
www.ti.com
2 Revision History
This data manual revision history highlights the changes made to the SWRS037A device-specific data
manual to make it an SWRS037B revision.
Changes from January 1, 2006 to February 19, 2015 Page
Updated RST package to RGV. .................................................................................................. 58
4Revision History Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS DGUARD 3 S :
GND
Exposed die
attach pad
5
XOSC_Q1
6
AVDD
7
XOSC_Q2
8
GDO0 (ATEST)
9 CSn
10 RF_P
11 RF_N
12 AVDD
13
AVDD
14
RBIAS
15
DGUARD
16
SI
1SCLK
2SO (GDO1)
3DVDD
4DCOUPL
CC1150
www.ti.com
SWRS037B –JANUARY 2006REVISED MARCH 2015
3 Terminal Configuration and Functions
The CC1150 pinout is shown in Figure 3-1 and Table 3-1
Figure 3-1. Pinout Top View
3.1 Pin Attributes
Table 3-1. Pin Attributes(1)
PIN NO. PIN NAME TYPE DESCRIPTION
1 SCLK Digital Input Serial configuration interface, clock input.
Serial configuration interface, data output.
2 SO (GDO1) Digital Output Optional general output pin when CSn is high.
1.8-V to 3.6-V digital power supply for digital I/Os and for the digital
3 DVDD Power (Digital) core voltage regulator.
4 DCOUPL(2) Power (Digital) 1.6-V to 2.0-V digital power supply output for decoupling.
5 XOSC_Q1 Analog I/O Crystal oscillator pin 1, or external clock input.
6 AVDD Power (Analog) 1.8-V to 3.6-V analog power supply connection.
7 XOSC_Q2 Analog I/O Crystal oscillator pin 2.
Digital output pin for general use:
Test signals
GDO0 FIFO status signals
8 Digital I/O
(ATEST) Clock output, down-divided from XOSC
Serial input TX data
Also used as analog test I/O for prototype/production testing.
9 CSn Digital Input Serial configuration interface, chip select.
10 RF_P RF I/O Positive RF output signal from PA.
11 RF_N RF I/O Negative RF output signal from PA.
12 AVDD Power (Analog) 1.8-V to 3.6-V analog power supply connection.
13 AVDD Power (Analog) 1.8-V to 3.6-V analog power supply connection.
14 RBIAS Analog I/O External bias resistor for reference current.
15 DGUARD Power (Digital) Power supply connection for digital noise isolation.
16 SI Digital Input Serial configuration interface, data input.
(1) The exposed die attach pad must be connected to a solid ground plane as this is the main ground connection for the chip.
(2) This pin is intended for use with the CC1150 only. It can not be used to provide supply voltage to other devices.
Copyright © 2006–2015, Texas Instruments Incorporated Terminal Configuration and Functions 5
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS
CC1150
SWRS037B JANUARY 2006REVISED MARCH 2015
www.ti.com
4 Specifications
4.1 Absolute Maximum Ratings(1)(2)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT CONDITION
All supply pins must have the same
Supply voltage –0.3 3.6 V voltage
Voltage on any digital pin –0.3 VDD + 0.3, max 3.6 V
Voltage on the pins RF_P, RF_N and –0.3 2.0 V
DCOUPL
Voltage ramp-up 120 kV/µs
Input RF level +10 dBm
Storage temperature range, Tstg –50 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.
4.2 ESD Ratings
VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(2) < 500
V(ESD) Electrostatic discharge V
Charged-device model (CDM) 250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
(2) According to JEDEC STD 22, method A114, Human Body Model
4.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT CONDITION
Operating temperature –40 85 °C
All supply pins must have the same
Operating supply voltage 1.8 3.6 V voltage
4.4 General Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT CONDITION
300 348 MHz
Frequency range 400 464 MHz
800 928 MHz
1.2 500 kBaud 2-FSK
1.2 250 kBaud GFSK, OOK and ASK
(Shaped) MSK (also known as
Data rate differential offset QPSK)
26 500 kBaud Optional Manchester encoding (the
data rate in kbps will be half the
baud rate)
6Specifications Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS
CC1150
www.ti.com
SWRS037B –JANUARY 2006REVISED MARCH 2015
4.5 Current Consumption
Tc= 25°C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the CC1150EM reference design
(see [1] and [2]).
PARAMETER TYP UNIT CONDITION
200 nA Voltage regulator to digital part off, register values lost (SLEEP state)
Voltage regulator to digital part on, all other modules in power down
222 µA (XOFF state)
Only voltage regulator to digital part and crystal oscillator running
1.1 mA
Current consumption (IDLE state)
Only the frequency synthesizer running (FSTXON state). This
current consumption also representative for the other intermediate
7.7 mA states when going from IDLE until reaching TX, and frequency
calibration states
25.6 mA Transmit mode, +10 dBm output power (0xC4)
Current consumption, 315 MHz 14.1 mA Transmit mode, 0 dBm output power (0x60)
See more in Section 5.16 and DN012 [3].
26.1 mA Transmit mode, +10 dBm output power (0xC2)
Current consumption, 433 MHz 14.6 Transmit mode, 0 dBm output power (0x60)
See more in Section 5.16 and DN012 [3].
29.3 mA Transmit mode, +10 dBm output power (0xC3)
Current consumption, 868 MHz 15.5 Transmit mode, 0 dBm output power (0x60)
See more in Section 5.16 and DN012 [3].
29.3 mA Transmit mode, +10 dBm output power (0xC0)
Current consumption, 915 MHz 15.2 mA Transmit mode, 0 dBm output power (0x50)
See more in Section 5.16 and DN012 [3].
4.6 RF Transmit
Tc= 25°C, VDD = 3.0 V, if nothing else stated. All measurement results are obtained using the CC1150EM reference design
(see [1] and [2]).
PARAMETER TYP MAX UNIT CONDITION
315 MHz 122 + j31 ΩDifferential impedance as seen from the RF-
Differential load 433 MHz 116 + j41 Ωport (RF_P and RF_N) towards the antenna.
impedance Follow the CC1150EM reference design
86.5 +
868/915 MHz Ω(see [1] and [2]).
j43
Output power is programmable, and full
range is available across all frequency
bands. Output power may be restricted by
regulatory limits. See also
DN006 [5].
Delivered to a 50-Ωsingle-ended load via
Output power, highest setting +10 dBm CC1150 EM reference design (see [1] and
[2]) RF matching network. Maximum output
power can be increased 1 to 2 dB by using
wire-wound inductors instead of multilayer
inductors in the balun and filter circuit for the
868/915 MHz band, see more in DN017 [6].
Output power is programmable, and full
range is available across all frequency
bands.
Output power, lowest setting –30 dBm Delivered to a 50 Ωsingle-ended load via
CC1150 EM reference design (see [1] and
[2]) RF matching network.
Copyright © 2006–2015, Texas Instruments Incorporated Specifications 7
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS
CC1150
SWRS037B JANUARY 2006REVISED MARCH 2015
www.ti.com
RF Transmit (continued)
Tc= 25°C, VDD = 3.0 V, if nothing else stated. All measurement results are obtained using the CC1150EM reference design
(see [1] and [2]).
PARAMETER TYP MAX UNIT CONDITION
25 MHz to 1 GHz –36 dBm
Spurious 47 to 74 MHz,
emissions and 87.5 to 118 MHz, –54 dBm
harmonics(1), 174 to 230 MHz,
433/868 MHz 470 to 862 MHz
Otherwise above 1 GHz –30 dBm
< 200 µV/m at 3 m below dBm
–49.2
960 MHz EIRP
Spurious emissions,
315/915 MHz < 500 µV/m at 3 m above dBm
–41.2
960 MHz EIRP
Whe output power is maximum
2nd, 3rd and 4th harmonic –20 dBc 6 mV/m at 3 m (–19.6 dBm EIRP)
Harmonics 315 MHz
5th harmonic –41.2 dBm
2nd harmonic –20 dBc With +10 dBm output power
Harmonics 915 MHz 3rd, 4th, and 5th harmonic –41.2 dBm
Serial operation. Time from sampling the
TX latency 8 Bits data on the transmitter data input pin until it
is observed on the RF output ports.
(1) Note that close-in spurs vary with centre frequency and limits the frequencies and output power level which the CC1150 can operate at
without violating regulatory restrictions. See also Section 6.2.5 for information regarding additional filtering.
4.7 Crystal Oscillator
Tc= 25°C, VDD = 3.0 V if nothing else is stated. All measurement results obtained using the CC1150EM reference design
(see [1] and [2]).
PARAMETER MIN TYP MAX UNIT CONDITION
Crystal frequency 26 26 27 MHz
This is the total tolerance including a) initial
tolerance, b) aging and c) temperature
dependence.
Tolerance ±40 ppm The acceptable crystal tolerance depends on
RF frequency and channel spacing /
bandwidth
Load capacitance 10 13 20 pF Simulated over operating conditions
ESR 100 Ω
Measured on the CC1150EM reference
Start-up time 150 µs design (see [1] and [2]). This parameter is to
a large degree crystal dependent.
4.8 Frequency Synthesizer Characteristics
Tc= 25°C, VDD = 3.0 V if nothing else is stated. All measurement results obtained using the CC1150EM reference design
(see [1] and [2]).
PARAMETER MIN TYP MAX UNIT CONDITION
Programmed frequency 26 MHz to 27 MHz crystals. The resolution
397 FXOSC / 216 412 Hz
resolution (in Hz) is equal for all frequency bands.
Given by crystal used. Required accuracy
(including temperature and aging) depends
Synthesizer frequency tolerance ±40 ppm on frequency band and channel bandwidth /
spacing.
@ 50 kHz offset from carrier,
RF carrier phase noise –82 dBc/Hz carrier at 868 MHz
@ 100 kHz offset from carrier,
RF carrier phase noise –86 dBc/Hz carrier at 868 MHz
8Specifications Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS
CC1150
www.ti.com
SWRS037B –JANUARY 2006REVISED MARCH 2015
Frequency Synthesizer Characteristics (continued)
Tc= 25°C, VDD = 3.0 V if nothing else is stated. All measurement results obtained using the CC1150EM reference design
(see [1] and [2]).
PARAMETER MIN TYP MAX UNIT CONDITION
@ 200 kHz offset from carrier,
RF carrier phase noise –90 dBc/Hz carrier at 868 MHz
@ 500 kHz offset from carrier,
RF carrier phase noise –98 dBc/Hz carrier at 868 MHz
@ 1 MHz offset from carrier,
RF carrier phase noise –106 dBc/Hz carrier at 868 MHz
@ 2 MHz offset from carrier,
RF carrier phase noise –113 dBc/Hz carrier at 868 MHz
@ 5 MHz offset from carrier,
RF carrier phase noise –119 dBc/Hz carrier at 868 MHz
@ 10 MHz offset from carrier,
RF carrier phase noise –127 dBc/Hz carrier at 868 MHz
Time from leaving the IDLE state until
arriving in the FSTXON or TX state, when
PLL turn-on / hop time 85.1 88.4 88.4 µs not performing calibration.
Crystal oscillator running.
Calibration can be initiated manually or
XOSC
18739 automatically before entering or after leaving
cycles TX.
PLL calibration time
Min/typ/max time is for 27/26/26 MHz crystal
694 721 721 µs frequency.
4.9 Analog Temperature Sensor(1)
Tc= 25°C, VDD = 3.0 V if nothing else is stated.
PARAMETER MIN TYP MAX UNIT CONDITION
Output voltage at –40°C 0.651 V
Output voltage at 0°C 0.747 V
Output voltage at +40°C 0.847 V
Output voltage at +80°C 0.945 V
Temperature coefficient 2.45 mV/°C Fitted from –20°C to +80°C
From –20°C to +80°C
when using
Absolute error in calculated temperature –2(2) 2(2) °C 2.45 mV / °C, after 1-point
calibration at room
temperature
Current consumption increase when 0.3 mA
enabled
(1) It is necessary to write 0xBF to the PTEST register to use the analog temperature sensor in the IDLE state.
(2) Indicated minimum and maximum error with 1-point calibration is based on simulated values for typical process parameters
4.10 DC Characteristics
Tc= 25°C if nothing else stated.
DIGITAL INPUTS/OUTPUTS MIN MAX UNIT CONDITION
Logic "0" input voltage 0 0.7 V
Logic "1" input voltage VDD – 0.7 VDD V
Logic "0" output voltage 0 0.5 V For up to 4 mA output current
Logic "1" output voltage VDD – 0.3 VDD V For up to 4 mA output current
Logic "0" input current N/A –1 µA Input equals 0 V
Logic "1" input current N/A 1 µA Input equals VDD
Copyright © 2006–2015, Texas Instruments Incorporated Specifications 9
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS
CC1150
SWRS037B JANUARY 2006REVISED MARCH 2015
www.ti.com
4.11 Power-On Reset
For proper Power-On-Reset functionality, the power supply must comply with the requirements in this table. Otherwise, the
chip should be assumed to have unknown state until transmitting an SRES strobe over the SPI interface. See Section 5.11.1
for a description of the recommended start-up sequence after turning power on.
PARAMETER MIN TYP MAX UNIT CONDITION
Power up ramp-up time 5 ms From 0 V until reaching 1.8 V
Minimum time between power on and
Power-off time 1 ms power off
4.12 Thermal Resistance Characteristics for VQFNP Package
NAME DESCRIPTION °C/W(1) (2)
RθJC(top) Junction-to-case (top) 54.0
RθJB Junction-to-board 25.1
RθJA Junction-to-free air 48.3
PsiJT Junction-to-package top 1.6
PsiJB Junction-to-board 25.2
RθJC(bottom) Junction-to-case (bottom) 6.3
(1) °C/W = degrees Celsius per watt.
(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RθJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
Power dissipation of 2 W and an ambient temperature of 70ºC is assumed.
10 Specifications Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS Z I (D 7 {ATEST} ‘ u‘ i I REIAS xoscfi1 xoscfiz
BIAS
XOSC_Q1 XOSC_Q2
XOSC
FREQ
SYNTH
RADIO CONTROL
RF_P
RF_N
CSn
SI
SO (GDO1)
SCLK
GDO0 (ATEST)
RBIAS
PA
FEC /
INTERLEAVER
PACKET
HANDLER
MODULATOR
TX FIFO
DIGITAL
INTERFACE
TO MCU
CC1150
www.ti.com
SWRS037B –JANUARY 2006REVISED MARCH 2015
5 Detailed Description
5.1 Overview
The CC1150 transmitter is based on direct synthesis of the RF frequency. The frequency synthesizer
includes a completely on-chip LC VCO.
A crystal is to be connected to XOSC_Q1 and XOSC_Q2. The crystal oscillator generates the reference
frequency for the synthesizer, as well as clocks for the digital part. A 4-wire SPI serial interface is used for
configuration and data buffer access. The digital baseband includes support for channel configuration,
packet handling and data buffering.
5.2 Functional Block Diagram
Figure 5-1. CC1150 Simplified Block Diagram
5.3 Configuration Overview
CC1150 can be configured to achieve optimum performance for many different applications. Configuration
is done using the SPI interface. The following key parameters can be programmed:
Power-down and power-up mode
Crystal oscillator power up and power down
Transmit mode
RF channel selection
Data rate
Modulation format
RF output power
Data buffering with 64-byte transmit FIFO
Packet radio hardware support
Forward Error Correction with interleaving
Data Whitening
Details of each configuration register can be found in Section 5.20.
Figure 5-2 shows a simplified state diagram that explains the main CC1150 states, together with typical
usage and current consumption. For detailed information on controlling the CC1150 state machine, and a
complete state diagram, see Section 5.11.
Copyright © 2006–2015, Texas Instruments Incorporated Detailed Description 11
Submit Documentation Feedback
Product Folder Links: CC1150
*9 TEXAS INSTRUMENTS Ustdsc FrTQcc Ittch m
Transmit mode
IDLE
Manual freq.
synth. calibration
TX FIFO
underflow
Frequency
synthesizer on
SFSTXON
STX
STX
SFTX
SIDLE
SCAL
IDLE
TXOFF_MODE=00
SRX or STX or SFSTXON
Sleep
SPWD
Crystal
oscillator off
SXOFF
CSn=0
CSn=0
TXOFF_MODE=01
Frequency
synthesizer startup,
optional calibration,
settling
Optional freq.
synth. calibration
Default state when the radio is not
receiving or transmitting. Typ.
current consumption: 1.1 mA.
Lowest power mode.
Register values are lost.
Current consumption typ
200nA.
All register values are
retained. Typ. current
consumption; 0.22 mA.
Used for calibrating frequency
synthesizer upfront (entering
transmit mode can then be
done quicker). Transitional
state. Typ. current
consumption: 7.7 mA.
Frequency synthesizer is turned on, can optionally be
calibrated, and then settles to the correct frequency.
Transitional state. Typ. current consumption: 7.7 mA.
Frequency synthesizer is on,
ready to start transmitting.
Transmission starts very
quickly after receiving the STX
command strobe.Typ. current
consumption: 7.7 mA.
Typ. current consumption 868 MHz:
14 mA at -10 dBm output,
15 mA at 0 dBm output,
24 mA at +7 dBm output,
29 mA at +10 dBm output.
Optional transitional state. Typ.
current consumption: 7.7 mA.
In FIFO-based modes,
transmission is turned off and
this state entered if the TX
FIFO becomes empty in the
middle of a packet. Typ.
current consumption: 1.1 mA.
CC1150
SWRS037B JANUARY 2006REVISED MARCH 2015
www.ti.com
Figure 5-2. Simplified State Diagram with Typical Usage and Current Consumption
5.4 Configuration Software
CC1150 can be configured using the SmartRF Studio [11] software. The SmartRF Studio software is
highly recommended for obtaining optimum register settings, and for evaluating performance and
functionality. A screenshot of the SmartRF Studio user interface for CC1150 is shown in Figure 5-3.
After chip reset, all the registers have default values as shown in the tables in Section 5.20. The optimum
register setting might differ from the default value. After a reset all registers that shall be different from the
default value therefore needs to be programmed through the SPI interface.
12 Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: CC1150
I TEXAS INSTRUMENTS [akulalmn wmdnw m. sumvs me D i LJ 0 El may“: . mmuulmm m . \ucrammmy MD . mcmmzlmm mm Hmmfilmm mm mm my man sww my flxflfl mm Imus) mm mcmomm mun :wmwmm} mm rnzuzmoym mam mum macaw] flxflfl MDMEFEI mm) MD MDMEFEamml m MDMCFEZ mm m: MDMEFEI mm) mm MDMEFEH‘UH41MH Dzvmm Inns: um Mcsm |M7I mm MESW Im m mm FRENWW‘ZZI m rsm: [main mm rsmz [mm mm rsw ms: um Fsmu [Mat mm rsrzsr [mm mm Prisv laminar; lEslz mm mm] Gum mm um mrwmm ymwmm u r ‘ mm . Sm n >45»de |n,,,...v..1 mm Wm [firmfismwum] V can...“ m RF Run-v |rmmmx| finnmunv MHz u v Gm r PAH-mm V mm mm mum gum?" > Hum EVEN“ W: ”55134 kE-ud ZFSK v '— Mw' RFFIau-q >FREI1|23151 mm .m m m... [Jfimmsss m weasmz wt We j ,SEJn'W.m "mm Mm manna. Wm Mammal-Ms a. m: M > ow: mu...“ maxim ‘ on me (m) > Drum» numaz .nm NM »> MUDJERMAVRM Mmm. m.) wmzsvsuu mum .092 a...‘ Mun—‘1 ) mmsch v MDMD’En-Ma m...‘ Mxmul -> msm v smrx P-muxl lmfimv h V syn-mom 32m; . mm [—w. I? ‘ rum-u mun-m Tn 7mm" mu Mgr '7 mm Immmamsnsumusmmcmwwumam huh MWEFfiv-m ,. Mm > uumflwupm r 1.. rummm mu» r MWEFEQ-M! m Swnnd‘ smcxunalm mum-am ham > PXLFnHMAln nI ERL‘ mm >1 mun pifwm'"‘”¥um mmmn . .) Fundla‘byfw H. I I | [wume-m b. ummJ-wnsmn
CC1150
www.ti.com
SWRS037B –JANUARY 2006REVISED MARCH 2015
Figure 5-3. SmartRF Studio User Interface
5.5 4-wire Serial Configuration and Data Interface
CC1150 is configured via a simple 4-wire SPI-compatible interface (SI, SO, SCLK and CSn) where
CC1150 is the slave. This interface is also used to read and write buffered data. All address and data
transfer on the SPI interface is done most significant bit first.
All transactions on the SPI interface start with a header byte containing a read/write bit, a burst access bit
and a 6-bit address.
During address and data transfer, the CSn pin (Chip Select, active low) must be kept low. If CSn goes
high during the access, the transfer will be cancelled. The timing for the address and data transfer on the
SPI interface is shown in Figure 5-4 with reference to Table 5-1.
When CSn is pulled low, the MCU must wait until the CC1150 SO pin goes low before starting to transfer
the header byte. This indicates that the voltage regulator has stabilized and the crystal is running. Unless
the chip is in the SLEEP or XOFF states, the SO pin will always go low immediately after taking CSn low.
Copyright © 2006–2015, Texas Instruments Incorporated Detailed Description 13
Submit Documentation Feedback
Product Folder Links: CC1150
fi‘ TEXAS INSTRUMENTS \ AH \ x x flHHE‘)% Li jL) , um 3: mun- 3 , EC- ;inx >< 'x="" 117411741141="" cdcdcdckdcd-i="" i191):="" ctctctcztcwcwcw="" a-3="" q="" cdcdcdqcdc="" “—="">
0A6 A5 A4 A3 A2 A0A1 DW7 DW6 DW5 DW4 D W
3 DW2 DW1 D W0
1A6 A5 A4 A3 A2 A0A1
DR
7 DR
6 DR5 DR
4 DR
3 D R
2 DR1 DR0
Read from register:
Write to register:
Hi-Z
X
SCLK:
CSn:
SI
SO
SI
SO Hi-Z
tsp tch tcl tsd thd tns
X X
Hi-Z
X
S7 S6 S5 S4 S3 S2 S1 S0
Hi-Z
S7 S6 S5 S4 S3 S2 S1 S0 S7 S6 S5 S4 S3 S2 S1 S0 S7
X
CC1150
SWRS037B JANUARY 2006REVISED MARCH 2015
www.ti.com
Figure 5-4. Configuration Registers Write and Read Operations
Table 5-1. SPI Interface Timing Requirements
PARAMETER DESCRIPTION MIN MAX UNIT
SCLK frequency
— 10
100 ns delay inserted between address byte and data byte (single access), or
between address and data, and between each data byte (burst access).
SCLK frequency, single access
fSCLK MHz
9
No delay between address and data byte
SCLK frequency, burst access 6.5
No delay between address and data byte, or between data bytes
tsp,pd CSn low to positive edge on SCLK, in power-down mode 150 µs
tsp CSn low to positive edge on SCLK, in active mode 20 ns
tch Clock high 50 ns
tcl Clock low 50 ns
trise Clock rise time 5 ns
tfall Clock fall time 5 ns
Setup data (negative SCLK edge) to positive edge on Single access 55 — ns
SCLK
tsd (tsd applies between address and data bytes, and Burst access 76 — ns
between data bytes)
thd Hold data after positive edge on SCLK 20 ns
tns Negative edge on SCLK to CSn high 20 ns
NOTE
The minimum tsp,pd figure in Table 5-1 can be used in cases where the user does not read
the CHIP_RDYn signal. CSn low to positive edge on SCLK when the chip is woken from
power-down depends on the start-up time of the crystal being used. The 150 μs in Table 5-1
is the crystal oscillator start-up time measured using crystal AT-41CD2 from NDK.
5.5.1 Chip Status Byte
When the header byte, data byte or command strobe is sent on the SPI interface, the chip status byte is
sent by the CC1150 on the SO pin. The status byte contains key status signals, useful for the MCU. The
first bit, s7, is the CHIP_RDYn signal; this signal must go low before the first positive edge of SCLK. The
CHIP_RDYn signal indicates that the crystal is running and the regulated digital supply voltage is stable.
Bit 6, 5 and 4 comprises the STATE value. This value reflects the state of the chip. The XOSC and power
to the digital core is on in the IDLE state, but all other modules are in power down. The frequency and
channel configuration should only be updated when the chip is in this state. The TX state will be active
when the chip is transmitting.
14 Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS
CC1150
www.ti.com
SWRS037B –JANUARY 2006REVISED MARCH 2015
The last four bits (3:0) in the status byte con-tains FIFO_BYTES_AVAILABLE. This field contains the
number of bytes free for writing into the TX FIFO. When FIFO_BYTES_AVAILABLE=15, 15 or more bytes
are free. Table 5-2 gives a status byte summary.
Table 5-2. Status Byte Summary
BITS NAME DESCRIPTION
Stays high until power and crystal have stabilized. Should always be low when using the
7 CHIP_RDYn SPI interface.
Indicates the current main state machine mode.
The binary number is the value, the result is the state, and the definition is the current
main state machine mode.
000 = Idle : IDLE state(1)
001 = Not used : Not used
6:04 STATE[2:0] 010 = TX : Transmit mode
011 = FSTXON : Fast TX ready
100 = CALIBRATE : Frequency synthesizer calibration is running
101 = SETTLING : PLL is settling
110 = Not used : Not used
111 = TXFIFO_UNDERFLOW : TX FIFO has underflowed. Acknowledge with SFTX
3:00 FIFO_BYTES_AVAILABLE[3:0] The number of free bytes in the TX FIFO.
(1) Also reported for some transitional states instead of SETTLING or CALIBRATE, due to a small error.
5.5.2 Register Access
The configuration registers on the CC1150 are located on SPI addresses from 0x00 to 0x2E. Table 5-12
lists all configuration registers. The detailed description of each register is found in Section 5.20.
All configuration registers can be both written and read. The read/write bit controls if the register should be
written or read. When writing to registers, the status byte is sent on the SO pin each time a header byte or
data byte is transmitted on the SI pin. When reading from registers, the status byte is sent on the SO pin
each time a header byte is transmitted on the SI pin.
Registers with consecutive addresses can be accessed in an efficient way by setting the burst bit in the
address header. The address sets the start address in an internal address counter. This counter is
incremented by one each new byte (every 8 clock pulses). The burst access is either a read or a write
access and must be terminated by setting CSn high.
For register addresses in the range 0x30 through 0x3D, the burst bit is used to select between status
registers (burst bit is 1) and command strobes (burst bit is 0). See more in Section 5.5.3. Because of this,
burst access is not available for status registers, so they must be read one at a time. The status registers
can only be read.
5.5.3 SPI Read
When reading register fields over the SPI interface while the register fields are updated by the radio
hardware (for example, MARCSTATE or TXBYTES), there is a small, but finite, probability that a single
read from the register is being corrupt. As an example, the probability of any single read from TXBYTES
being corrupt, assuming the maximum data rate is used, is approximately 80 ppm. Refer to the CC1150
Errata Notes [8] for more details.
5.5.4 Command Strobes
Command Strobes may be viewed as single byte instructions to CC1150. By addressing a Command
Strobe register, internal sequences will be started. These commands are used to disable the crystal
oscillator, enable transmit mode, flush the TX FIFO, and so on. The nine command strobes are listed in
Table 5-11.
Copyright © 2006–2015, Texas Instruments Incorporated Detailed Description 15
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS
CC1150
SWRS037B JANUARY 2006REVISED MARCH 2015
www.ti.com
NOTE
An SIDLE strobe will clear all pending command strobes until IDLE state is reached. This
means that if for example an SIDLE strobe is issued while the radio is in TX state, any other
command strobes issued before the radio reaches IDLE state will be ignored.
The command strobe registers are accessed in the same way as for a register write operation, but no data
is transferred. That is, only the R/W bit (set to 0), burst access (set to 0) and the six address bits (in the
range 0x30 through 0x3D) are written.
When writing command strobes, the status byte is sent on the SO pin.
A command strobe may be followed by any other SPI access without pulling CSn high. However, if an
SRES command strobe is being issued, on will have to wait for the SO pin to go low before the next
command strobe can be issued as shown in Figure 5-5.The command strobes are executed immediately,
with the exception of the SPWD and the SXOFF strobes that are executed when CSn goes high.
Figure 5-5. SRES Command Strobe
5.5.5 FIFO Access
The 64-byte TX FIFO is accessed through the 0x3F addresses. When the read/write bit is zero, the TX
FIFO is accessed. The TX FIFO is write-only.
The burst bit is used to determine if FIFO access is single byte or a burst access. The single byte access
method expects address with burst bit set to zero and one data byte. After the data byte a new address is
expected; hence, CSn can remain low. The burst access method expects one address byte and then
consecutive data bytes until terminating the access by setting CSn high.
The following header bytes access the FIFO:
0x3F: Single byte access to TX FIFO
0x7F: Burst access to TX FIFO
When writing to the TX FIFO, the status byte (see Section 5.5.1) is output for each new data byte on SO,
as shown in Figure 5-5. This status byte can be used to detect TX FIFO underflow while writing data to
the TX FIFO.
NOTE
The status byte contains the number of bytes free before writing the byte in progress to the
TX FIFO.
When the last byte that fits in the TX FIFO is transmitted to the SI pin, the status byte received
concurrently on the SO pin will indicate that one byte is free in the TX FIFO.
The TX FIFO may be flushed by issuing a SFTX command strobe. The SFTX command strobe can only
be issues in the IDLE or TX_UNDERFLOW states. The FIFO is cleared when going to the SLEEP state.
Figure 5-6 gives a brief overview of different register access types possible.
16 Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS mug, X ADDgw: ADDE X ADDEW: ADDBW M. M
DATA
byte 0
ADDR
FIFO DATA
byte 1 DATA
byte 2 DATA
byte n-1 DATA
byte n
...
ADDR
strobe
DATA
ADDR
strobe
ADDR
reg
ADDR
reg n DATA
nDATA
n+1 DATA
n+2 ...
ADDR
strobe ...
CSn:
Command strobe(s):
Read or write register(s):
Read or write consecutive registers (burst):
DATA
ADDR
reg DATA
ADDR
reg ...
DATA
byte 0
ADDR
FIFO DATA
byte 1
Combinations: DATAADDR
reg DATAADDR
reg
ADDR
strobe ADDR
strobe ...
Read or write n+1 bytes from/to RF FIFO:
CC1150
www.ti.com
SWRS037B –JANUARY 2006REVISED MARCH 2015
Figure 5-6. Register Access Types
5.5.6 PATABLE Access
The 0x3E address is used to access the PATABLE, which is used for selecting PA power control settings.
The SPI expects up to eight data bytes after receiving the address. By programming the PATABLE,
controlled PA power ramp-up and ramp-down can be achieved, as well as ASK modulation shaping for
reduced bandwidth.
NOTE
The ASK modulation shaping is limited to output powers below –1 dBm. See SmartRF Studio
[11] for recommended shaping sequence.
See also Section 5.16 for details on output-power programming.
The PATABLE is an 8-byte table that defines the PA control settings to use for each of the eight PA power
values (selected by the 3-bit value FREND0.PA_POWER). The table is written and read from the lowest
setting (0) to the highest (7), one byte at a time. An index counter is used to control the access to the
table. This counter is incremented each time a byte is read or written to the table, and set to the lowest
index when CSn is high. When the highest value is reached the counter restarts at zero.
The access to the PATABLE is either single byte or burst access depending on the burst bit. When using
burst access the index counter will count up; when reaching 7 the counter will restart at 0. The read/write
bit controls whether the access is a write access (R/W=0) or a read access (R/W=1).
If one byte is written to the PATABLE and this value is to be read out then CSn must be set high before
the read access in order to set the index counter back to zero.
NOTE
The content of the PATABLE is lost when entering the SLEEP state. For more information,
see DN501 [8].
5.6 Microcontroller Interface and Pin Configuration
In a typical system, CC1150 will interface to a microcontroller. This microcontroller must be able to do the
following:
Program CC1150 into different modes
Write buffered data
Read back status information via the 4-wire SPI-bus configuration interface (SI, SO, SCLK and CSn)
5.6.1 Configuration Interface
The microcontroller uses four I/O pins for the SPI configuration interface (SI, SO, SCLK and CSn). The
SPI is described in Section 5.5.
Copyright © 2006–2015, Texas Instruments Incorporated Detailed Description 17
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS DRATEiE
( ) DRATE _ E
DATA XOSC
28
256 DRATE _ M 2
R f
2
+ ´
= ´
CC1150
SWRS037B JANUARY 2006REVISED MARCH 2015
www.ti.com
5.6.2 General Control and Status Pins
The CC1150 has one dedicated configurable pin (GDO0) and one shared pin (GDO1/SO) that can output
internal status information useful for control software. These pins can be used to generate interrupts on
the MCU. See Section 5.17 for more details of the signals that can be programmed. The shared pin is the
SO pin in the SPI interface. The default setting for GDO1/SO is 3-state output. By selecting any other of
the programming options the GDO1/SO pin will become a generic pin. When CSn is low, the pin will
always function as a normal SO pin.
In the synchronous and asynchronous serial modes, the GDO0 pin is used as a serial TX data input pin
while in transmit mode.
The GDO0 pin can also be used for an on-chip analog temperature sensor. By measuring the voltage on
the GDO0 pin with an external ADC, the temperature can be calculated. Specifications for the temperature
sensor are found in Section 4.9. With default PTEST register setting (0x7F), the temperature sensor
output is only available when the frequency synthesizer is enabled (for example, the MANCAL, FSTXON
and TX states). It is necessary to write 0xBF to the PTEST register to use the analog temperature sensor
in the IDLE state. Before leaving the IDLE state, the PTEST register should be restored to its default value
(0x7F).
5.6.3 Optional Radio Control Feature
The CC1150 has an optional way of controlling the radio by reusing SI, SCLK, and CSn from the SPI
interface. This feature allows for a simple three-pin control of the major states of the radio: SLEEP, IDLE,
and TX.
This optional functionality is enabled with the MCSM0.PIN_CTRL_EN configuration bit.
State changes are commanded as follows:
If CSn is high, the SI and SCLK are set to the desired state according to Table 5-3.
If CSn goes low, the state of SI and SCLK is latched and a command strobe is generated internally
according to the pin configuration.
It is only possible to change state with the latter functionality. That means that for instance TX will not be
restarted if SI and SCLK are set to TX and CSn toggles. When CSn is low the SI and SCLK has normal
SPI functionality.
All pin control command strobes are executed immediately except the SPWD strobe. The SPWD strobe is
delayed until CSn goes high.
Table 5-3. Optional Pin Control Coding
CSn SCLK SI FUNCTION
1 X X Chip unaffected by SCLK/SI
0 0 Generates SPWD strobe
0 1 Generates STX strobe
1 0 Generates SIDLE strobe
1 1 Defined on the transceiver version (CC1101)
SPI mode (wakes up into IDLE if in
0 SPI mode SPI mode SLEEP/XOFF)
5.7 Data Rate Programming
The data rate used when transmitting is programmed by the MDMCFG3.DRATE_M and the
MDMCFG4.DRATE_E configuration registers. The data rate is given by the formula below. As Equation 1
shows, the programmed data rate depends on the crystal frequency.
(1)
18 Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: CC1150
TEXAS INSTRUMENTS XOSC
20
DATA
2
XOSC
28
DATA
DRATE _ E
XOSC
R 2
DRATE _ E log f
R 2
DRATE _ M 256
f 2
é ù
æ ö
´
ê ú
ç ÷
=ç ÷
ê ú
è ø
ë û
´
= -
´
CC1150
www.ti.com
SWRS037B –JANUARY 2006REVISED MARCH 2015
The following approach shown in Equation 2 can be used to find suitable values for a given data rate.
(2)
If DRATE_M is rounded to the nearest integer and becomes 256, increment DRATE_E and use
DRATE_M=0.
The data rate can be set from 0.8 kBaud to 500 kBaud with the minimum data rate step size changes
according to Table 5-4.
Table 5-4. Data Rate Step Size
MIN DATA RATE TYPICAL DATA RATE MAX DATA RATE DATA RATE STEP SIZE
[kBaud] [kBaud] [kBaud] [kBaud]
0.8 1.2 / 2.4 3.17 0.0062
3.17 4.8 6.35 0.0124
6.35 9.6 12.7 0.0248
12.7 19.6 25.4 0.0496
25.4 38.4 50.8 0.0992
50.8 76.8 101.6 0.1984
101.6 153.6 203.1 0.3967
203.1 250 406.3 0.7935
406.3 500 500 1.5869
5.8 Packet Handling Hardware Support
The CC1150 has built-in hardware support for packet oriented radio protocols.
In transmit mode, the packet handler can be configured to add the following elements to the packet stored
in the TX FIFO:
A programmable number of preamble bytes.
A two byte Synchronization Word. Can be duplicated to give a 4-byte sync word (recommended). It is
not possible to only insert preamble or only insert a sync word.
Optionally whitening the data with a PN9 sequence.
Optionally Interleave and Forward Error Code the data.
Optionally compute and add a 2-byte CRC checksum over the data field.
In a system where CC1150 is used as the transmitter and CC1101 as the receiver the recommended
setting is 4-byte preamble and 4-byte sync word except for 500 kBaud data rate where the recommended
preamble length is 8 bytes.
NOTE
Register fields that control the packet handling features should only be altered when CC1150
is in the IDLE state.
5.8.1 Data Whitening
From a radio perspective, the ideal over the air data are random and DC free. This results in the
smoothest power distribution over the occupied bandwidth. This also gives the regulation loops in the
receiver uniform operation conditions (no data dependencies).
Copyright © 2006–2015, Texas Instruments Incorporated Detailed Description 19
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS mourn m % ‘> <* a=""><* a="" d="" d="" d="">< nus="">< x="" a="">
Preamble bits
(1010...1010)
Sync word
Length field
Address field
Data field
CRC-16
Optional CRC-16 calculation
Optionally FEC encoded/decoded
Optional data whitening
Legend:
Inserted automatically in TX,
processed and removed in RX.
Optional user-provided fields processed in TX,
processed but not removed in RX.
Unprocessed user data (apart from FEC
and/or whitening)
8 x n bits 16/32
bits
8
bits
8
bits 8 x n bits 16 bits
TX_OUT[7:0]
TX_DATA
8 7 6 5 4 3 2 1 0
76 5 4 3 2 1 0
The first TX_DATA byte is shifted in before doing the XOR-operation providing the first TX_OUT[7:0] byte. The
second TX_DATA byte is then shifted in before doing the XOR-operation providing the second TX_OUT[7:0] byte.
CC1150
SWRS037B JANUARY 2006REVISED MARCH 2015
www.ti.com
Real world data often contain long sequences of zeros and ones. Performance can then be improved by
whitening the data before transmitting, and de-whitening in the receiver. With CC1150, in combination with
a CC1101 at the receiver end, this can be done automatically by setting PKTCTRL0WHITE_DATA=1. All
data, except the preamble and the sync word, are then XOR-ed with a 9-bit pseudo-random (PN9)
sequence before being transmitted as shown in Figure 5-7. The PN9 sequence is initialized to all ones. At
the receiver end, the data are XOR-ed with the same pseudo-random sequence. This way, the whitening
is reversed, and the original data appear in the receiver.
Setting PKTCTRL0.WHITE_DATA=1 is recommended for all uses, except when over-the-air compatibility
with other systems is needed.
Figure 5-7. Data Whitening in TX Mode
5.8.2 Packet Format
The format of the data packet can be configured and consists of the following items:
• Preamble
Synchronization word
Optional length byte
Optional Address byte
• Payload
Optional 2 byte CRC
Figure 5-8. Packet Format
20 Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS
CC1150
www.ti.com
SWRS037B –JANUARY 2006REVISED MARCH 2015
The preamble pattern is an alternating sequence of ones and zeros (01010101…). The number of
preamble bytes is programmed with the MDMCFG1.NUM_PREAMBLE value. When enabling TX, the
modulator will start transmitting the preamble. When the programmed number of preamble bytes has been
transmitted, the modulator will send the sync word and then data from the TX FIFO if data is available. If
the TX FIFO is empty, the modulator will continue to send preamble bytes until the first byte is written to
the TX FIFO. The modulator will then send the sync word and then the data bytes.
The synchronization word is a two-byte value set in the SYNC1 and SYNC0 registers. The sync word
provides byte synchronization of the incoming packet. A one-byte synch word can be emulated by setting
the SYNC1 value to the preamble pattern. It is also possible to emulate a 32 bit sync word by using
MDMCFG2.SYNC_MODE set to 3 or 7. The sync word will then be repeated twice.
C1150 supports both fixed packet length protocols and variable packet length protocols. Variable or fixed
packet length mode can be used for packets up to 255 bytes. For longer packets, infinite packet length
mode must be used.
Fixed packet length mode is selected by setting PKTCTRL0.LENGTH_CONFIG=0. The desired packet
length is set by the PKTLEN register. In variable packet length mode PKTCTRL0.LENGTH_CONFIG=1,
the packet length is configured by the first byte after the sync word. The packet length is defined as the
payload data, excluding the length byte and the optional automatic CRC.
With PKTCTRL0.LENGTH_CONFIG=2, the packet length is set to infinite and transmission will continue
until turned off manually. The infinite mode can be turned off while a packet is being transmitted. As
described in Section 5.8.2.1, this can be used to support packet formats with different length configuration
than natively supported by CC1150. One should make sure that TX mode is not turned off during the
transmission of the first half of any byte. Refer to the CC1150 Errata Notes [8] for more details.
NOTE
The minimum packet length supported (excluding the optional length byte and CRC) is one
byte of payload data.
5.8.2.1 Arbitrary Length Field Configuration
The packet automation control register, PKTCTRL0, can be reprogrammed during TX. This opens the
possibility to transmit packets that are longer than 256 bytes and still be able to use the packet handling
hardware support. At the start of the packet, the infinite mode (PKTCTRL0.LENGTH_CONFIG=2) must be
active. The PKTLEN register is set to mod(length, 256). When less than 256 bytes remains of the packet,
the MCU disables infinite packet length and activates fixed length packets. When the internal byte counter
reaches the PKTLEN value, the transmission ends (the radio enters the state determined by
TXOFF_MODE). Automatic CRC appending can be used (by setting PKTCTRL0.CRC_EN=1).
When, for example, a 600-byte packet is to be transmitted, the MCU should do the following (see also
Figure 5-9):
Set PKTCTRL0.LENGTH_CONFIG=2.
Pre-program the PKTLEN register to mod(600,256)=88.
Transmit at least 345 bytes, for example by filling the 64-byte TX FIFO six times (384 bytes
transmitted).
Set PKTCTRL0.LENGTH_CONFIG=0.
The transmission ends when the packet counter reaches 88. A total of 600 bytes are transmitted.
Copyright © 2006–2015, Texas Instruments Incorporated Detailed Description 21
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS Inlernal byte coumer m packet hand‘er counts from O (0 255 and then slams al 0 again
0,1,..........,88,....................255,0,........,88,..................,255,0,........,88,..................,255,0,.......................
Internal byte counter in packet handler counts from 0 to 255 and then starts at 0 again
Length field transmitted. Tx PKTLEN value set to mod(600,256) = 88
Infinite packet length enabled Fixed packet length
enabled when less than
256 bytes remains of
packet
600 bytes transmitted
CC1150
SWRS037B JANUARY 2006REVISED MARCH 2015
www.ti.com
Figure 5-9. Arbitrary Length Field Configuration
5.8.3 Packet Handling in Transmit Mode
The payload that is to be transmitted must be written into the TX FIFO. The first byte written must be the
length byte when variable packet length is enabled. The length byte has a value equal to the payload of
the packet (including the optional address byte). If fixed packet length is enabled, then the first byte written
to the TX FIFO is interpreted as the destination address, if this feature is enabled in the device that
receives the packet.
The modulator will first send the programmed number of preamble bytes. If data is available in the TX
FIFO, the modulator will send the two-byte (optionally 4-byte) sync word and then the payload in the TX
FIFO. If CRC is enabled, the checksum is calculated over all the data pulled from the TX FIFO and the
result is sent as two extra bytes at the end of the payload data. If the TX FIFO runs empty before the
complete packet has been transmitted, the radio will enter TXFIFO_UNDERFLOW state. The only way to
exit this state is by issuing an SFTX strobe. Writing to the TX FIFO after it has underflowed will not restart
TX mode.
If whitening is enabled, the length byte, payload data and the two CRC bytes will be whitened. This is
done before the optional FEC/Interleaver stage. Whitening is enabled by setting
PKTCTRL0.WHITE_DATA=1.
If FEC/Interleaving is enabled, the length byte, payload data and the two CRC bytes will be scrambled by
the interleaver, and FEC encoded before being modulated. FEC is enabled by setting
MDMCFG1.FEC_EN=1.
5.8.4 Packet Handling in Firmware
When implementing a packet oriented radio protocol in firmware, the MCU needs to know when a packet
has been transmitted. Additionally, for packets longer than 64 bytes, the TX FIFO needs to be refilled
while in TX. This means that the MCU needs to know the number of bytes that can be written to the TX
FIFO. There are two possible solutions to get the necessary status information:
a. Interrupt Driven Solution
The GDO pins can be used in TX to give an interrupt when a sync word has been transmitted or
when a complete packet has been transmitted by setting IOCFGx.GDOx_CFG=0x06. In addition,
there are two configurations for the IOCFGx.GDOx_CFG register that can be used as an interrupt
source to provide information on how many bytes that is in the TX FIFO. The
IOCFGx.GDOx_CFG=0x02 and the IOCFGx.GDOx_CFG=0x03 configurations are associated with
the TX FIFO. See Table 5-10 for more information.
b. SPI Polling
The PKTSTATUS register can be polled at a given rate to get information about the current GDO2
and GDO0 values respectively. The TXBYTES register can be polled at a given rate to get
information about the number of bytes in the TX FIFO. Alternatively, the number of bytes in the TX
FIFO can be read from the chip status byte returned on the MISO line each time a header byte,
data byte, or command strobe is sent on the SPI bus.
22 Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: CC1150
TEXAS INSTRUMENTS
DEVIATION _ E
xosc
dev 17
f
f (8 DEVIATION _ M) 2
2
= ´ + ´
CC1150
www.ti.com
SWRS037B –JANUARY 2006REVISED MARCH 2015
It is recommended to employ an interrupt driven solution due to that when using SPI polling, there
is a small, but finite, probability that a single read from registers PKTSTATUS and TXBYTES is
being corrupt. The same is the case when reading the chip status byte. This is explained in the
CC1150 Errata Notes [8] Refer to the TI website for SW examples [12].
5.9 Modulation Formats
CC1150 supports amplitude, frequency and phase shift modulation formats. The desired modulation
format is set in the MDMCFG2.MOD_FORMAT register.
Optionally, the data stream can be Manchester coded by the modulator. This option is enabled by setting
MDMCFG2.MANCHESTER_EN=1. Manchester encoding cuts the effective data rate in half, and thus
Manchester is not supported for 500 kBaud. Further note that Manchester encoding is not supported at
the same time as using the FEC/Interleaver option or when using MSK modulation.
5.9.1 Frequency Shift Keying
CC1150 has the possibility to use Gaussian shaped 2_FSK (GFSK). The 2-FSK signal is then shaped by
a Gaussian filter with BT=1, producing a GFSK modulated signal. This spectrum-shaping feature improves
adjacent channel power (ACP) and occupied bandwidth.
In “true” 2-FSK systems with abrupt frequency shifting, the spectrum is inherently broad. By making the
frequency shift “softer”, the spectrum can be made significantly narrower. Thus, higher data rates can be
transmitted in the same bandwidth using GFSK.
The frequency deviation is programmed with the DEVIATION_M and DEVIATION_E values in the
DEVIATN register. The value has an exponent/mantissa form, and the resultant deviation is given by
Equation 3.
(3)
The symbol encoding is shown in Table 5-5.
Table 5-5. Symbol Encoding for 2-FSK/GFSK
Modulation
FORMAT SYMBOL CODING
0 – Deviation
2-FSK/GFSK 1 + Deviation
5.9.2 Minimum Shift Keying
When using MSK [(Identical to offset QPSK with half-sine shaping (data coding may differ)], the complete
transmission (preamble, sync word, and payload) will be MSK modulated.
Phase shifts are performed with a constant transition time. The fraction of a symbol period used to change
the phase can be modified with the DEVIATN.DEVIATION_M setting. This is equivalent to changing the
shaping of the symbol.
NOTE
When using MSK, Manchester encoding must be disabled by setting
MDMCFG2.MANCHESTER_EN=0.
The MSK modulation format implemented in CC1150 inverts the data compared to,
for example, signal generators.
Copyright © 2006–2015, Texas Instruments Incorporated Detailed Description 23
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS
CC1150
SWRS037B JANUARY 2006REVISED MARCH 2015
www.ti.com
5.9.3 Amplitude Modulation
CC1150 supports two different forms of amplitude modulation: On-Off Keying (OOK) and Amplitude Shift
Keying (ASK).
OOK modulation simply turns on or off the PA to modulate 1 and 0 respectively.
The ASK variant supported by the CC1150 allows programming of the modulation depth (the difference
between 1 and 0), and shaping of the pulse amplitude. Pulse shaping will produce a more bandwidth
constrained output spectrum.
NOTE
The OOK/ASK pulse shaping feature on the CC1150 does only support output power up to
about –1 dBm. The DEVIATN register has no effect when using ASK/OOK.
5.10 Forward Error Correction with Interleaving
5.10.1 Forward Error Correction (FEC)
CC1150 has built in support for Forward Error Correction (FEC) that can be used with CC1101 at the
receiver end. To enable this option, set MDMCFG1.FEC_EN to 1. FEC is only supported in fixed packet
length mode, that is, when PKTCTRL0.LENGTH_CONFIG=0. FEC is employed on the data field and CRC
word in order to reduce the gross bit error rate when operating near the sensitivity limit. Redundancy is
added to the transmitted data in such a way that the receiver can restore the original data in the presence
of some bit errors.
The use of FEC allows correct reception at a lower Signal-to-Noise RATIO (SNR), thus extending
communication range. Alternatively, for a given SNR, using FEC decreases the bit error rate (BER). As
the packet error rate (PER) is related to BER by Equation 4.
PER = 1 – (1 – BER)packet_length (4)
A lower BER can be used to allow longer packets, or a higher percentage of packets of a given length, to
be transmitted successfully.
Finally, in realistic ISM radio environments, transient and time-varying phenomena will produce occasional
errors even in otherwise good reception conditions. FEC will mask such errors and, combined with
interleaving of the coded data, even correct relatively long periods of faulty reception (burst errors).
The FEC scheme adopted for CC1150 is convolutional coding, in which n bits are generated based on k
input bits and the m most recent input bits, forming a code stream able to withstand a certain number of
bit errors between each coding state (the m-bit window).
The convolutional coder is a rate 1/2 code with a constraint length of m = 4. The coder codes one input bit
and produces two output bits; hence, the effective data rate is halved. This means that in order to transmit
at the same effective data rate when using FEC, it is necessary to use twice as high over-the-air data rate.
24 Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS
Packet
Engine
FEC
Encoder Modulator
Interleaver
Write buffer
Interleaver
Read buffer
Demodulator FEC
Decoder
Packet
Engine
Interleaver
Write buffer
Interleaver
Read buffer
CC1150
www.ti.com
SWRS037B –JANUARY 2006REVISED MARCH 2015
5.10.2 Interleaving
Data received through real radio channels will often experience burst errors due to interference and time-
varying signal strengths. In order to increase the robustness to errors spanning multiple bits, interleaving
is used when FEC is enabled. After de-interleaving, a continuous span of errors in the received stream will
become single errors spread apart.
CC1150 employs matrix interleaving, which is illustrated in Figure 5-10. The on-chip interleaving buffer is
a 4 × 4 matrix. In the transmitter, the data bits are written into the rows of the matrix, whereas the bit
sequence to be transmitted is read from the columns of the matrix and fed to the rate ½ convolutional
coder. Conversely, in a CC1101 receiver, the received symbols are written into the rows of the matrix,
whereas the data passed onto the convolutional decoder is read from the columns of the matrix.
When FEC and interleaving is used, at least one extra byte is required for trellis termination. In addition,
the amount of data transmitted over the air must be a multiple of the size of the interleaver buffer (two
bytes). The packet control hardware therefore automatically inserts one or two extra bytes at the end of
the packet, so that the total length of the data to be interleaved is an even number. Note that these extra
bytes are invisible to the user, as they are removed before the received packet enters the RX FIFO in a
CC1101.
When FEC and interleaving is used, the minimum data payload is 2 bytes in fixed and variable packet
length mode.
Figure 5-10. : General Principle of Matrix Interleaving
Copyright © 2006–2015, Texas Instruments Incorporated Detailed Description 25
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS
TX
19,20
IDLE
1
CALIBRATE
8
MANCAL
3,4,5
SETTLING
9,10
TX_UNDERFLOW
22
FSTXON
18
SFSTXON
FS_AUTOCAL = 00 | 10 | 11
&
STX | SFSTXON
STX
STX
TXFIFO_UNDERFLOW
SFTX
SIDLE
SCAL
CAL_COMPLETE
FS_AUTOCAL = 01
&
STX | SFSTXON
CAL_COMPLETE
CALIBRATE
12
IDLE
1
TXOFF_MODE = 00
&
FS_AUTOCAL = 10 | 11
TXOFF_MODE = 00
&
FS_AUTOCAL = 00 | 01
TXOFF_MODE = 10
FS_WAKEUP
6,7
STX | SFSTXON
SLEEP
0
SPWD
XOFF
2
SXOFF
CSn = 0
CSn = 0
TXOFF_MODE = 01
CC1150
SWRS037B JANUARY 2006REVISED MARCH 2015
www.ti.com
5.11 Radio Control
Figure 5-11. Radio Control State Diagram
26 Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS
XOSC Stable
CSn
SO
CC1150
www.ti.com
SWRS037B –JANUARY 2006REVISED MARCH 2015
CC1150 has a built-in state machine that is used to switch between different operations states (modes).
The change of state is done either by using command strobes or by internal events such as TX FIFO
underflow.
A simplified state diagram, together with typical usage and current consumption, is shown in Figure 5-2.
The complete radio control state diagram is shown in Figure 5-11. The numbers refer to the state number
readable in the MARCSTATE status register. This functionality is primarily for test purposes.
5.11.1 Power On Start-up Sequence
When the power supply is turned on, the system must be reset. This is achieved by one of the two
sequences described in Section 5.11.1.1 or Section 5.11.1.2, that is, automatic power-on reset or manual
reset. After the automatic power-on reset or manual reset it is also recommended to change the signal
that is output on the GDO0 pin. The default setting is to output a clock signal with a frequency of
CLK_XOSC/192, but to optimize performance in TX, an alternative GDO setting should be selected from
the settings found in Table 5-10.
5.11.1.1 Automatic POR
A power-on reset circuit is included in the CC1150. The minimum requirements stated in Section 4.7 must
be followed for the power-on reset to function properly. The internal power-up sequence is completed
when CHIP_RDYn goes low. CHIP_RDYn is observed on the SO pin after CSn is pulled low. See Section
10.1 for more details on CHIP_RDYn.
When the CC1150 reset is completed the chip will be in the IDLE state and the crystal oscillator running. If
the chip has had sufficient time for the crystal oscillator and voltage regulator to stabilize after the power-
on-reset, the SO pin will go low immediately after taking CSn low. If CSn is taken low before reset is
completed the SO pin will first go high, indicating that the crystal oscillator and voltage regulator is not
stabilized, before going low as shown in Figure 5-12.
Figure 5-12. Power-on Reset
5.11.1.2 Manual Reset
The other global reset possibility on CC1150 is the SRES command strobe. By issuing this strobe, all
internal registers and states are set to the default, IDLE state. The power-up sequence is as follows (see
Figure 5-13):
Set SCLK = 1 and SI = 0.
Strobe CSn low / high. Make sure to hold CSn high for at least 40 µs relative to pulling CSn low.
Pull CSn low and wait for SO to go low (CHIP_RDYn).
Issue the SRES strobe on the SI line.
When SO goes low again, reset is complete and the chip is in the IDLE state.
Copyright © 2006–2015, Texas Instruments Incorporated Detailed Description 27
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS xosc and vauage regulator switched an
CSn
SO
XOSC Stable
XOSC and voltage regulator switched on
SI SRES
40 µs
CC1150
SWRS037B JANUARY 2006REVISED MARCH 2015
www.ti.com
Figure 5-13. Power-up with SRES
NOTE
The above reset procedure is only required just after the power supply is first turned on. If
the user wants to reset the CC1150 after this, it is only necessary to issue an SRES
command strobe.
It is recommended to always send a SRES command strobe on the SPI interface after power-on even
though power-on reset is used.
5.11.2 Crystal Control
The crystal oscillator is automatically turned on when CSn goes low. It will be turned off if the SXOFF or
SPWD command strobes are issued; the state machine then goes to XOFF or SLEEP respectively. This
can only be done from IDLE state. The XOSC will be turned off when CSn is released (goes high). The
XOSC will be automatically turned on again when CSn goes low. The state machine will then go to the
IDLE state. The SO pin on the SPI interface must be pulled low before the SPI interface is ready to be
used; as described in Section 5.5.1.
Crystal oscillator start-up time depends on crystal ESR and load capacitances. The electrical specification
for the crystal oscillator can be found in Section 4.7.
5.11.3 Voltage Regulator Control
The voltage regulator to the digital core is controlled by the radio controller. When the chip enters the
SLEEP state, which is the state with the lowest current consumption, the voltage regulator is disabled.
This occurs after CSn is released when a SPWD command strobe has been sent on the SPI interface.
The chip is then in the SLEEP state. Setting CSn low again will turn on the regulator and crystal oscillator
and make the chip enter the IDLE state.
On the CC1150, all register values (with the exception of the MCSM0.PO_TIMEOUT field) are lost in the
SLEEP state. After the chip gets back to the IDLE state, the registers will have default (reset) contents
and must be reprogrammed over the SPI interface.
5.11.4 Active Mode
The active transmit mode is activated by the MCU by using the STX command strobe.
The frequency synthesizer must be calibrated regularly. CC1150 has one manual calibration option (using
the SCAL strobe), and three automatic calibration options, controlled by the MCSM0.FS_AUTOCAL
setting:
Calibrate when going from IDLE to TX (or FSTXON)
Calibrate when going from TX to IDLE
Calibrate every fourth time when going from TX to IDLE
28 Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS
CC1150
www.ti.com
SWRS037B –JANUARY 2006REVISED MARCH 2015
The calibration takes a constant number of XOSC cycles; see Table 5-6 for timing details. When TX is
active, the chip will remain in the TX state until the current packet has been successfully transmitted. Then
the state will change as indicated by the MCSM1.TXOFF_MODE setting. The possible destinations are:
• IDLE
FSTXON: Frequency synthesizer on and ready at the TX frequency. Activate TX with STX.
TX: Start sending preambles
The SIDLE command strobe can always be used to force the radio controller to go to the IDLE state. Note
that if the radio goes from TX to IDLE by issuing an SIDLE strobe, the automatic calibration-when-going-
from-TX-to-IDLE will not be performed.
5.11.5 Timing
The radio controller controls most timing in CC1150, such as synthesizer calibration and PLL lock.
Table 5-6 shows timing in crystal clock cycles for key state transitions. Timing from IDLE to TX is
constant, dependent on the auto calibration setting. The calibration time is constant 18739 clock periods.
Power on time and XOSC start-up times are variable, but within the limits stated in Section 4.7.
NOTE
In a frequency hopping spread spectrum or a multi-channel protocol, the calibration time can
be reduced from 721 µs to approximately 150 µs. This is explained in Section 5.19.2.
Table 5-6. State Transition Timing
DESCRIPTION XOSC PERIODS 26 MHz CRYSTAL
Idle to TX/FSTXON, no calibration 2298 88.4 µs
Idle to TX/FSTXON, with calibration 21037 809 µs
TX to IDLE, no calibration 2 0.1 µs
TX to IDLE, including calibration 18739 721 µs
Manual calibration 18739 721 µs
5.12 Data FIFO
The CC1150 contains a 64 byte FIFO for data to be transmitted. The SPI interface is used for writing to
the TX FIFO. Section 10.5 contains details on the SPI FIFO access. The FIFO controller will detect
underflow in the TX FIFO.
When writing to the TX FIFO, it is the responsibility of the MCU to avoid TX FIFO overflow. This will not be
detected by the CC1150. A TX FIFO overflow will result in an error in the TX FIFO content.
Table 5-7. FIFO_THR Settings
and the Corresponding FIFO
Thresholds
BYTES in TX
FIFO_THR FIFO
0000 61
0001 57
0010 53
0011 49
0100 45
0101 41
0110 37
Copyright © 2006–2015, Texas Instruments Incorporated Detailed Description 29
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS A A TXFIFO
8 bytes
Underflow
margin
FIFO_THR=13
TXFIFO
CC1150
SWRS037B JANUARY 2006REVISED MARCH 2015
www.ti.com
Table 5-7. FIFO_THR Settings
and the Corresponding FIFO
Thresholds (continued)
BYTES in TX
FIFO_THR FIFO
0111 33
1000 29
1001 25
1010 21
1011 17
1100 13
1101 9
1110 5
1111 1
The chip status byte that is available on the SO pin while transferring the SPI address contains the fill
grade of the TX FIFO. Section 5.5.1 contains more details on this.
The number of bytes in the TX FIFO can also be read from the TXBYTES.NUM_TXBYTES status register.
The 4-bit FIFOTHR.FIFO_THR setting is used to program the FIFO threshold point. Table 5-7 lists the 16
FIFO_THR settings and the corresponding thresholds for the TX FIFO.
Figure 5-14. Example of FIFO at Threshold
A flag will assert when the number of bytes in the FIFO is equal to or higher than the programmed
threshold. The flag is used to generate the FIFO status signals that can be viewed on the GDO pins (see
Section 5.17).
Figure 5-15 shows the number of bytes in the TX FIFO when the threshold flag toggles, in the case of
FIFO_THR=13. Figure 5-15 shows the flag as the FIFO is filled above the threshold, and then drained
below.
30 Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS ))
( )
( )
()
CHANSPC _ E 2
XOSC
carrier 16
f
f FREQ CHAN 256 CHANSPC _ M 2
2
-
= ´ + ´ + ´
6 7 8 9 678910
NUM_TXBYTES
GDO
CC1150
www.ti.com
SWRS037B –JANUARY 2006REVISED MARCH 2015
Figure 5-15. FIFO_THR=13 versus Number of Bytes in FIFO
5.13 Frequency Programming
The frequency programming in CC1150 is designed to minimize the programming needed in a channel-
oriented system.
To set up a system with channel numbers, the desired channel spacing is programmed with the
MDMCFG0.CHANSPC_M and MDMCFG1.CHANSPC_E registers. The channel spacing registers are
mantissa and exponent respectively.
The base or start frequency is set by the 24-bit frequency word located in the FREQ2, FREQ1 and
FREQ0 registers. This word will typically be set to the centre of the lowest channel frequency that is to be
used.
The desired channel number is programmed with the 8-bit channel number register, CHANNR.CHAN,
which is multiplied by the channel offset. The resultant carrier frequency is given by Equation 5.
(5)
With a 26-MHz crystal, the maximum channel spacing is 405 kHz. To get, for example, 1-MHz channel
spacing on solution is to use 333-kHz channel spacing and select each third channel in CHANNR.CHAN.
If any frequency programming register is altered when the frequency synthesizer is running, the
synthesizer may give an undesired response. Hence, the frequency programming should only be updated
when the radio is in the IDLE state.
5.14 VCO
The VCO is completely integrated on-chip.
5.14.1 VCO and PLL Self-Calibration
The VCO characteristics will vary with temperature and supply voltage changes, as well as the desired
operating frequency. In order to ensure reliable operation, CC1150 includes frequency synthesizer self-
calibration circuitry. This calibration should be done regularly, and must be performed after turning on
power and before using a new frequency (or channel). The number of XOSC cycles for completing the
PLL calibration is given in Table 5-6.
The calibration can be initiated automatically or manually. The synthesizer can be automatically calibrated
each time the synthesizer is turned on, or each time the synthesizer is turned off. This is configured with
the MCSM0.FS_AUTOCAL register setting.
In manual mode, the calibration is initiated when the SCAL command strobe is activated in the IDLE
mode.
The calibration values are not maintained in sleep mode. Therefore, the CC1150 must be recalibrated
after reprogramming the configuration registers when the chip has been in the SLEEP state.
To check that the PLL is in lock the user can program register IOCFGx.GDOx_CFG to 0x0A and use the
lock detector output available on the GDOx pin as an interrupt for the MCU (x = 0, 1, or 2). A positive
transition on the GDOx pin means that the PLL is in lock. As an alternative the user can read register
FSCAL1. The PLL is in lock if the register content is different from 0x3F. See more information in the
CC1150 Errata Notes [8].
For more robust operation the source code could include a check so that the PLL is re-calibrated until PLL
lock is achieved if the PLL does not lock the first time.
Copyright © 2006–2015, Texas Instruments Incorporated Detailed Description 31
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS V VVVVVV m FRENDD register
e.g 6
PA_POWER[2:0]
in FREND0 register
PATABLE(0)[7:0]
PATABLE(1)[7:0]
PATABLE(2)[7:0]
PATABLE(3)[7:0]
PATABLE(4)[7:0]
PATABLE(5)[7:0]
PATABLE(6)[7:0]
PATABLE(7)[7:0]
Index into PATABLE(7:0)
The PA uses this
setting.
Settings 0 to PA_POWER are
used during ramp-up at start of
transmission and ramp-down at
end of transmission, and for
ASK/OOK modulation.
The SmartRF Studio software
should be used to obtain optimum
PATABLE settings for various
output powers.
TM
CC1150
SWRS037B JANUARY 2006REVISED MARCH 2015
www.ti.com
5.15 Voltage Regulators
CC1150 contains several on-chip linear voltage regulators, which generate the supply voltage needed by
low-voltage modules. These voltage regulators are invisible to the user, and can be viewed as integral
parts of the various modules. The user must however make sure that the absolute maximum ratings and
required pin voltages in Section 4.1 and Table 3-1 are not exceeded.
Setting the CSn pin low turns on the voltage regulator to the digital core and start the crystal oscillator.
The SO pin on the SPI interface must go low before the first positive edge on the SCLK (setup time is s
given in Table 5-1).
If the chip is programmed to enter power-down mode (SPWD strobe issued), the power will be turned off
after CSn goes high. The power and crystal oscillator will be turned on again when CSn goes low.
The voltage regulator for the digital core requires one external decoupling capacitor. The voltage regulator
output should only be used for driving the CC1150.
5.16 Output Power Programming
The RF output power level from the device has two levels of programmability, as illustrated in Figure 5-16.
Firstly, the special PATABLE register can hold up to eight user selected output power settings. Secondly,
the 3-bit FREND0.PA_POWER value selects the PATABLE entry to use. This two-level functionality
provides flexible PA power ramp up and ramp down at the start and end of transmission, as well as ASK
modulation shaping. In each case, all the PA power settings in the PATABLE from index 0 up to the
FREND0.PA_POWER value are used.
The power ramping at the start and at the end of a packet can be turned off by setting
FREND0.PA_POWER to zero and then programming the desired output power to index 0 in the
PATABLE.
If OOK modulation is used, the logic 0 and logic 1 power levels shall be programmed to index 0 and 1
respectively.
Table 5-8 contains recommended PATABLE settings for various output levels and frequency bands.
DN012 [3] gives complete tables for the different frequency bands. Using PA settings from 0x61 to 0x6F is
not recommended. Table 5-9 contains output power and current consumption for default PATABLE setting
(0xC6).
PATABLE must be programmed in burst mode if you want to write to other entries than PATABLE[0]. See
Section 5.5.6 for PATABLE programming details.
Figure 5-16. PA_POWER and PATABLE
32 Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS
11 0 0 0 1 0 Bit Sequence
1
FREND0.PA_POWER = 3
FREND0.PA_POWER = 7
Time
PATABLE[0]
PATABLE[1]
PATABLE[2]
PATABLE[3]
PATABLE[4]
PATABLE[5]
PATABLE[6]
PATABLE[7]
Output Power
CC1150
www.ti.com
SWRS037B –JANUARY 2006REVISED MARCH 2015
Table 5-8. Optimum PATABLE Settings for Various Output Power Levels and Frequency Bands
315 MHz 433 MHz 868 MHz 915 MHz
OUTPUT CURRENT CURRENT CURRENT CURRENT
POWER SETTING CONSUMPTION, SETTING CONSUMPTION, SETTING CONSUMPTION, SETTING CONSUMPTION,
[dBm] TYP. [mA] TYP. [mA] TYP. [mA] TYP. [mA]
–30 0x12 9.9 0x03 10.8 0x03 11.2 0x03 11.1
–20 0x0E 10.4 0x0E 11.4 0x0C 11.7 0x0F 11.7
–10 0x26 12.5 0x26 13.3 0x26 13.7 0x34 13.6
–5 0x57 12.2 0x57 12.9 0x57 13.3 0x56 13.3
0 0x60 14.1 0x60 14.6 0x60 15.5 0x50 15.2
3 0x8B 15.8 0x8A 16.5 0x8A 17.4 0x89 17.4
7 0xCC 21.4 0xC8 23 0xCC 24.4 0xC8 24.6
10 0xC4 25.6 0xC2 26.1 0xC3 29.3 0xC0 29.3
Table 5-9. Output Power and Current Consumption for Default PATABLE Setting
315 MHz 433 MHz 868 MHz 915 MHz
DEFAULT OUTPUT CURRENT OUTPUT CURRENT OUTPUT CURRENT OUTPUT CURRENT
POWER POWER CONSUMPTION, POWER CONSUMPTION, POWER CONSUMPTION, POWER CONSUMPTION,
SETTING [dBm] TYP. [mA] [dBm] TYP. [mA] [dBm] TYP. [mA] [dBm] TYP. [mA]
0xC6 9.3 24.4 8.1 23.9 8.9 27.3 7.7 25.5
5.16.1 Shaping and PA Ramping
With ASK modulation, up to eight power settings are used for shaping. The modulator contains a counter
that counts up when transmitting a one and down when transmitting a zero. The counter counts at a rate
equal to 8 times the symbol rate. The counter saturates at FREND0.PA_POWER and 0 respectively. This
counter value is used as an index for a lookup in the power table. Thus, in order to utilize the whole table,
FREND0.PA_POWER should be 7 when ASK is active. The shaping of the ASK signal is dependent on
the configuration of the PATABLE. Figure 5-17 shows some examples of ASK shaping.
NOTE
The OOK/ASK pulse shaping feature on the CC1150 is only supported for output power
levels below –1 dBm.
Figure 5-17. Shaping of ASK Signal
5.17 General Purpose and Test Output Control Pins
The two digital output pins GDO0 and GDO1 are general control pins. Their functions are programmed by
IOCFG0.GDO0_CFG and IOCFG1.GDO1_CFG respectively. Table 5-10 shows the different signals that
can be monitored on the GDO pins. These signals can be used as an interrupt to the MCU.
GDO1 is the same pin as the SO pin on the SPI interface, thus the output programmed on this pin will
only be valid when CSn is high. The default value for GDO1 is 3-stated, which is useful when the SPI
interface is shared with other devices.
Copyright © 2006–2015, Texas Instruments Incorporated Detailed Description 33
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS
CC1150
SWRS037B JANUARY 2006REVISED MARCH 2015
www.ti.com
The default value for GDO0 is a 125 to 146 kHz clock output (XOSC frequency divided by 192). Because
the XOSC is turned on at power-on-reset, this can be used to clock the MCU in systems with only one
crystal. When the MCU is up and running it can change the clock frequency by writing to
IOCFG0.GDO0_CFG.
An on-chip analog temperature sensor is enabled by writing the value 128 (0x80h) to the
IOCFG0.GDO0_CFG register. The voltage on the GDO0 pin is then proportional to temperature. See
Section 4.9 for temperature sensor specifications.
Table 5-10. GDO signal selection(x = 0 or 1)
GDOx_CFG[5:0] DESCRIPTION
0 (0x00) Reserved – defined on the transceiver version (CC1101).
1 (0x01) Reserved – defined on the transceiver version (CC1101).
Associated to the TX FIFO: Asserts when the TX FIFO is filled at or above the TX FIFO threshold. De-asserts
2 (0x02) when the TX FIFO is below the same threshold.
Associated to the TX FIFO: Asserts when TX FIFO is full. De-asserts when the TX FIFO is drained below the
3 (0x03) TX FIFO threshold.
4 (0x04) Reserved – defined on the transceiver version (CC1101).
5 (0x05) Asserts when the TX FIFO has underflowed. De-asserts when the FIFO is flushed.
Asserts when sync word has been sent, and de-asserts at the end of the packet. In TX the pin will also de-
6 (0x06) assert if the TX FIFO underflows.
7 (0x07) Reserved – defined on the transceiver version (CC1101).
8 (0x08) Reserved – defined on the transceiver version (CC1101).
9 (0x09) Reserved – defined on the transceiver version (CC1101).
Lock detector output. The PLL is in lock if the lock detector output has a positive transition or is constantly
10 (0x0A) logic high. To check for PLL lock the lock detector output should be used as an interrupt for the MCU.
Serial Clock. Synchronous to the data in synchronous serial mode.
11 (0x0B) In TX mode, data is sampled by CC1150 on the rising edge of the serial clock when GDOx_INV=0.
12 (0x0C) Reserved – defined on the transceiver version (CC1101).
13 (0x0D) Reserved – defined on the transceiver version (CC1101).
14 (0x0E) Reserved – defined on the transceiver version (CC1101).
15 (0x0F) Reserved – defined on the transceiver version (CC1101).
16 (0x10) Reserved – used for test.
17 (0x11) Reserved – used for test.
18 (0x12) Reserved – used for test.
19 (0x13) Reserved – used for test.
20 (0x14) Reserved – used for test.
21 (0x15) Reserved – used for test.
22 (0x16) Reserved – defined on the transceiver version (CC1101).
23 (0x17) Reserved – defined on the transceiver version (CC1101).
24 (0x18) Reserved – used for test.
25 (0x19) Reserved – used for test.
26 (0x1A) Reserved – used for test.
27 (0x1B) PA_PD. PA is enabled when 1, in power-down when 0.
28 (0x1C) Reserved – defined on the transceiver version (CC1101).
29 (0x1D) Reserved – defined on the transceiver version (CC1101).
30 (0x1E) Reserved – used for test.
31 (0x1F) Reserved – used for test.
32 (0x20) Reserved – used for test.
33 (0x21) Reserved – used for test.
34 (0x22) Reserved – used for test.
35 (0x23) Reserved – used for test.
34 Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS
CC1150
www.ti.com
SWRS037B –JANUARY 2006REVISED MARCH 2015
Table 5-10. GDO signal selection(x = 0 or 1) (continued)
GDOx_CFG[5:0] DESCRIPTION
36 (0x24) Reserved – defined on the transceiver version (CC1101).
37 (0x25) Reserved – defined on the transceiver version (CC1101).
38 (0x26) Reserved – used for test.
39 (0x27) Reserved – defined on the transceiver version (CC1101).
40 (0x28) Reserved – used for test.
41 (0x29) CHIP_RDYn
42 (0x2A) Reserved – used for test.
43 (0x2B) XOSC_STABLE
44 (0x2C) Reserved – used for test.
45 (0x2D) GDO0_Z_EN_N. When this output is 0, GDO0 is configured as input (for serial TX data).
46 (0x2E) High impedance (3-state)
47 (0x2F) HW to 0 (HW1 achieved by setting GDOx_INV=1)
48 (0x30) CLK_XOSC/1
49 (0x31) CLK_XOSC/1.5
50 (0x32) CLK_XOSC/2
51 (0x33) CLK_XOSC/3
52 (0x34) CLK_XOSC/4
53 (0x35) CLK_XOSC/6
54 (0x36) CLK_XOSC/8
55 (0x37) CLK_XOSC/12 See (1)(2)
56 (0x38) CLK_XOSC/16
57 (0x39) CLK_XOSC/24
58 (0x3A) CLK_XOSC/32
59 (0x3B) CLK_XOSC/48
60 (0x3C) CLK_XOSC/64
61 (0x3D) CLK_XOSC/96
62 (0x3E) CLK_XOSC/128
63 (0x3F) CLK_XOSC/192
(1) There are 2 GDO pins, but only one CLK_XOSC/n can be selected as an output at any time. If CLK_XOSC/n is to be monitored on one
of the GDO pins, the other GDO pin must be configured to values less than 0x30. The GDO0 default value is CLK_XOSC/192.
(2) To optimize RF performance, these signals should not be used while the radio is in TX mode.
5.18 Asynchronous and Synchronous Serial Operation
Several features and modes of operation have been included in the CC1150 to provide backward
compatibility with previous TI products and other existing RF communication systems. For new systems, it
is recommended to use the built-in packet handling features, as they can give more robust
communication, significantly offload the microcontroller and simplify software development.
5.18.1 Asynchronous Serial Operation
For backward compatibility with systems already using the asynchronous data transfer from other TI
products, asynchronous transfer is also included in CC1150.
When asynchronous transfer is enabled, several of the support mechanisms for the MCU that are included
in CC1150 will be disabled, such as packet handling hardware, buffering in the FIFO and so on. The
asynchronous transfer mode does not allow the use of the data whitener, interleaver and FEC, and it is
not possible to use Manchester encoding. MSK is not supported for asynchronous transfer.
Setting PKTCTRL0.PKT_FORMAT to 3 enables asynchronous transparent (serial) mode. In TX, the
GDO0 pin is used for data input (TX data).
Copyright © 2006–2015, Texas Instruments Incorporated Detailed Description 35
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS (SWRAOQO)
CC1150
SWRS037B JANUARY 2006REVISED MARCH 2015
www.ti.com
The MCU must control start and stop of transmit with the STX and SIDLE strobes.
The CC1150 modulator samples the level of the asynchronous input 8 times faster than the programmed
data rate. The timing requirement for the asynchronous stream is that the error in the bit period must be
less than one eighth of the programmed data rate.
5.18.2 Synchronous Serial Operation
Setting PKTCTRL0.PKT_FORMAT to 1 enables synchronous serial operation mode. In this operational
mode the data must be NRZ encoded (MDMCFG2.MANCHESTER_EN=0). In synchronous serial
operation mode, data is transferred on a two wire serial interface. The CC1150 provides a clock that is
used to set up new data on the data input line. Data input (TX data) is the GDO0 pin. This pin will
automatically be configured as an input when TX is active. The TX latency is 8 bits.
Preamble and sync word insertion may or may not be active, dependent on the sync mode set by the
MDMCFG3.SYNC_MODE.
If preamble and sync word is disabled, all other packet handler features and FEC should also be disabled.
The MCU must then handle preamble and sync word insertion in software.
If preamble and sync word insertion is left on, all packet handling features and FEC can be used. When
using the packet handling features synchronous serial mode, the CC1150 will insert the preamble and
sync word and the MCU will only provide the data payload. This is equivalent to the recommended FIFO
operation mode.
5.19 System Considerations and Guidelines
5.19.1 SRD Regulations
International regulations and national laws regulate the use of radio receivers and transmitters. Short
Range Devices (SRDs) for license free operation below 1 GHz are usually operated in the 315-MHz, 433-
MHz, 868-MHz or 915-MHz frequency bands. The CC1150 is specifically designed for such use with its
300 to 348 MHz, 400 to 464 MHz and 800 to 928 MHz operating ranges. The most important regulations
when using the CC1150 in the 315-MHz, 433-MHz, 868-MHz or 915-MHz frequency bands are EN 300
220 (Europe) and FCC CFR47 part 15 (USA). A summary of the most important aspects of these
regulations can be found in AN001 SRD Regulations for Licence Free Transceiver Operation (SWRA090).
NOTE
Compliance with regulations is dependent on complete system performance. It is the end-
product manufactor’s responsibility to ensure that the system complies with regulations.
5.19.2 Frequency Hopping and Multi-Channel Systems
The 315-MHz, 433-MHz, 868-MHz or 915-MHz bands are shared by many systems both in industrial,
office and home environments. It is therefore recommended to use frequency hopping spread spectrum
(FHSS) or a multi-channel protocol because the frequency diversity makes the system more robust with
respect to interference from other systems operating in the same frequency band. FHSS also combats
multipath fading.
CC1150 is highly suited for FHSS or multi-channel systems due to its agile frequency synthesizer and
effective communication interface. Using the packet handling support and data buffering is also beneficial
in such systems as these features will significantly offload the host controller.
Charge pump current, VCO current and VCO capacitance array calibration data is required for each
frequency when implementing frequency hopping for CC1150. There are 3 ways of obtaining the
calibration data from the chip:
1. Frequency hopping with calibration for each hop. The PLL calibration time is approximately 720 µs.
The blanking interval between each frequency hop is then approximately 810 µs.
36 Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS
CC1150
www.ti.com
SWRS037B –JANUARY 2006REVISED MARCH 2015
2. Fast frequency hopping without calibration for each hop can be done by calibrating each frequency at
startup and saving the resulting FSCAL3, FSCAL2 and FSCAL1 register values in MCU memory. The
VCO capacitance calibration FSCAL1 register value must be found for each RF frequency to be used.
The VCO current calibration value and the charge pump current calibration value available in FSCAL2
and FSCAL3 respectively are not dependent on the RF frequency, so the same value can therefore be
used for all RF frequencies for these two registers. Between each frequency hop, the calibration
process can then be replaced by writing the FSCAL3, FSCAL2 and FSCAL1 register values that
corresponds to the next RF frequency. The PLL turn on time is approximately 90 µs. The blanking
interval between each frequency hop is then approximately 90 µs.
3. Run calibration on a single frequency at startup. Next write 0 to FSCAL3[5:4] to disable the charge
pump calibration. After writing to FSCAL3[5:4], strobe STX with MCSM0.FS_AUTOCAL=1 for each
new frequency hop. That is, VCO current and VCO capacitance calibration is done, but not charge
pump current calibration. When charge pump current calibration is disabled the calibration time is
reduced from approximately 720 µs to approximately 150 µs. The blanking interval between each
frequency hop is then approximately 240 µs.
There is a trade off between blanking time and memory space needed for storing calibration data in non-
volatile memory. Solution (2) above gives the shortest blanking interval, but requires more memory space
to store calibration values. This solution also requires that the supply voltage and temperature do not vary
much in order to have a robust solution. Solution (3) gives approximately 570 µs smaller blanking interval
than solution (1).
The recommended settings for TEST0.VCO_SEL_CAL_EN change with frequency. This means that one
should always use SmartRF Studio [11] to get the correct settings for a specific frequency before doing a
calibration, regardless of which calibration method is being used. It must be noted that the content of the
CC1150 is not retained in SLEEP state, and thus it is necessary to write to the TEST0 register, along with
other registers, when returning from the SLEEP state and initiating calibrations.
5.19.3 Wideband Modulation Not Using Spread Spectrum
Digital modulation systems under FFC part 15.247 include FSK and GFSK modulation. A maximum peak
output power of 1W (+30 dBm) is allowed if the 6 dB bandwidth of the modulated signal exceeds 500 kHz.
In addition, the peak power spectral density conducted to the antenna shall not be greater than +8 dBm in
any 3 kHz band.
Operating at high data rates and frequency deviation the CC1150 is suited for systems targeting
compliance with digital modulation system as defined by FFC part 15.247. An external power amplifier is
needed to increase the output above +10 dBm. Please refer to DN006 [5] for further details concerning
wideband modulation and CC1150.
5.19.4 Data Burst Transmissions
The high maximum data rate of CC1150 opens up for burst transmissions. A low average data rate link
(for example, 10 kBaud), can be realized using a higher over-the-air data rate. Buffering the data and
transmitting in bursts at high data rate (for example, 500 kBaud) will reduce the time in active mode, and
hence also reduce the average current consumption significantly. Reducing the time in active mode will
reduce the likelihood of collisions with other systems in the same frequency range.
5.19.5 Continuous Transmissions
In data streaming applications the CC1150 opens up for continuous transmissions at 500 kBaud effective
data rate. As the modulation is done with a closed loop PLL, there is no limitation in the length of a
transmission (open loop modulation used in some transceivers often prevents this kind of continuous data
streaming and reduces the effective data rate).
Copyright © 2006–2015, Texas Instruments Incorporated Detailed Description 37
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS Antenna
BALUN,
Matching and
Filtering
Antenna
PA Filter
CC1150
CC1150
SWRS037B JANUARY 2006REVISED MARCH 2015
www.ti.com
5.19.6 Low-Cost Systems
As the CC1150 provides 500-kBaud multi-channel performance without any external filters, a very low cost
system can be made. A HC-49 type SMD crystal is used in the CC1150EM reference design (see [1] and
[2]).
NOTE
The crystal package strongly influences the price. In a size constrained PCB design a
smaller, but more expensive, crystal may be used.
5.19.7 Battery-Operated Systems
In low power applications, the SLEEP state should be used when the CC1150 is not active.
5.19.8 Increasing Output Power
In some applications it may be necessary to extend the link range. Adding an external power amplifier is
the most effective way of doing this.
The power amplifier should be inserted between the antenna and the balun as shown in Figure 5-18.
Figure 5-18. Block Diagram of CC1150 Usage with External Power Amplifier
5.20 Memory
The configuration of CC1150 is done by programming 8-bit registers. The configuration data based on
selected system parameters are most easily found by using the SmartRF Studio [11] software. Complete
descriptions of the registers are given in Section 5.20.1. After chip reset, all the registers have default
values as shown in the tables. The optimum register setting might differ from the default value. After a
reset, all registers that shall be different from the default value therefore needs to be programmed through
the SPI interface.
There are 9 Command Strobe Registers, listed in Table 5-11 Accessing these registers will initiate the
change of an internal state or mode. There are 29 normal 8-bit Configuration Registers, listed in Table 5-
12. Many of these registers are for test purposes only, and need not be written for normal operation of
CC1150.
There are also 6 Status registers, which are listed in Table 5-13. These registers, which are read-only,
contain information about the status of CC1150.
The TX FIFO is accessed through one 8-bit register. Only write operations are allowed to the TX FIFO.
During the address transfer and while writing to a register or the TX FIFO, a status byte is returned. This
status byte is described in Table 5-2.
38 Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS
CC1150
www.ti.com
SWRS037B –JANUARY 2006REVISED MARCH 2015
Figure 5-19 summarizes the SPI address space. Registers that are only defined on the CC1101
transceiver are also listed. CC1101 and CC1150 are register compatible, but registers and fields only
implemented in the transceiver always contain 0 in CC1150.
The address to use is given by adding the base address to the left and the burst and read/write bits on the
top. Note that the burst bit has different meaning for base addresses above and below 0x2F.
Table 5-11. Command Strobes
ADDRESS STROBE NAME DESCRIPTION
0x30 SRES Reset chip.
0x31 SFSTXON Enable and calibrate frequency synthesizer (if MCSM0.FS_AUTOCAL=1).
0x32 SXOFF Turn off crystal oscillator.
0x33 SCAL Calibrate frequency synthesizer and turn it off (enables quick start). SCAL can be strobed in
IDLE state without setting manual calibration mode (MCSM0.FS_AUTOCAL=0)
0x35 STX Enable TX. Perform calibration first if MCSM0.FS_AUTOCAL=1.
0x36 SIDLE Exit TX and turn off frequency synthesizer.
0x39 SPWD Enter power down mode when CSn goes high.
0x3B SFTX Flush the TX FIFO buffer.
0x3D SNOP No operation. May be used to pad strobe commands to two bytes for simpler software.
Table 5-12. Configuration Registers Overview
ADDRESS ACRONYM REGISTER NAME SECTION
0x01 IOCFG1 GDO1 output pin configuration Table 5-14
0x02 IOCFG0 GDO0 output pin configuration Table 5-15
0x03 FIFOTHR FIFO threshold Table 5-16
0x04 SYNC1 Sync word, high byte Table 5-17
0x05 SYNC0 Sync word, low byte Table 5-18
0x06 PKTLEN Packet length Table 5-19
0x08 PKTCTRL0 Packet automation control Table 5-20
0x09 ADDR Device address Table 5-21
0x0A CHANNR Channel number Table 5-22
0x0D FREQ2 Frequency control word, high byte Table 5-23
0x0E FREQ1 Frequency control word, middle byte Table 5-24
0x0F FREQ0 Frequency control word, low byte Table 5-25
0x10 MDMCFG4 Modulator configuration Table 5-26
0x11 MDMCFG3 Modulator configuration Table 5-27
0x12 MDMCFG2 Modulator configuration Table 5-28
0x13 MDMCFG1 Modulator configuration Table 5-29
0x14 MDMCFG0 Modulator configuration Table 5-30
0x15 DEVIATN Modulator deviation setting Table 5-31
0x17 MCSM1 Main Radio Control State Machine configuration Table 5-32
0x18 MCSM0 Main Radio Control State Machine configuration Table 5-33
Copyright © 2006–2015, Texas Instruments Incorporated Detailed Description 39
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS
CC1150
SWRS037B JANUARY 2006REVISED MARCH 2015
www.ti.com
Table 5-12. Configuration Registers Overview (continued)
ADDRESS ACRONYM REGISTER NAME SECTION
0x22 FREND0 Front end TX configuration Table 5-34
0x23 FSCAL3 Frequency synthesizer calibration Table 5-35
0x24 FSCAL2 Frequency synthesizer calibration Table 5-36
0x25 FSCAL1 Frequency synthesizer calibration Table 5-37
0x26 FSCAL0 Frequency synthesizer calibration Table 5-38
0x29 FSTEST Frequency synthesizer calibration control Table 5-39
0x2A PTEST Production test Table 5-40
0x2C TEST2 Various test settings Table 5-41
0x2D TEST1 Various test settings Table 5-42
0x2E TEST0 Various test settings Table 5-43
Table 5-13. Status Registers Overview
ADDRESS ACRONYM REGISTER NAME SECTION
0x30 (0xF0) PARTNUM Part number for CC1150 Table 5-44
0x31 (0xF1) VERSION Current version number Table 5-45
0x35 (0xF5) MARCSTATE Control state machine state Table 5-46
0x38 (0xF8) PKTSTATUS Current GDOx status and packet status Table 5-47
0x39 (0xF9) VCO_VC_DAC Current setting from PLL calibration module Table 5-48
0x3A (0xFA) TXBYTES Underflow and number of bytes in the TX FIFO Table 5-49
40 Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: CC1150
Write Read
Single byte Burst Single byte Burst
+0x00 +0x40 +0x80 +0xC0
0x00 IOCFG2
R/W configuration registers, burst access possible
0x01 IOCFG1
0x02 IOCFG0
0x03 FIFOTHR
0x04 SYNC1
0x05 SYNC0
0x06 PKTLEN
0x07 PKTCTRL1
0x08 PKTCTRL0
0x09 ADDR
0x0A CHANNR
0x0B FSCTRL1
0x0C FSCTRL0
0x0D FREQ2
0x0E FREQ1
0x0F FREQ0
0x10 MDMCFG4
0x11 MDMCFG3
0x12 MDMCFG2
0x13 MDMCFG1
0x14 MDMCFG0
0x15 DEVIATN
0x16 MCSM2
0x17 MCSM1
0x18 MCSM0
0x19 FOCCFG
0x1A BSCFG
0x1B AGCCTRL2
0x1C AGCCTRL1
0x1D AGCCTRL0
0x1E WOREVT1
0x1F WOREVT0
0x20 WORCTRL
0x21 FREND1
0x22 FREND0
0x23 FSCAL3
0x24 FSCAL2
0x25 FSCAL1
0x26 FSCAL0
0x27 RCCTRL1
0x28 RCCTRL0
0x29 FSTEST
0x2A PTEST
0x2B AGCTEST
0x2C TEST2
0x2D TEST1
0x2E TEST0
0x2F
0x30 SRES SRES PARTNUM
Command Strobes, Status registers
(read only) and multi byte registers
0x31 SFSTXON SFSTXON VERSION
0x32 SXOFF SXOFF FREQEST
0x33 SCAL SCAL LQI
0x34 SRX SRX RSSI
0x35 STX STX MARCSTATE
0x36 SIDLE SIDLE WORTIME1
0x37 SAFC SAFC WORTIME0
0x38 SWOR SWOR PKTSTATUS
0x39 SPWD SPWD VCO_VC_DAC
0x3A SFRX SFRX TXBYTES
0x3B SFTX SFTX RXBYTES
0x3C SWORRST SWORRST
0x3D SNOP SNOP
0x3E PATABLE PATABLE PATABLE PATABLE
0x3F TX FIFO TX FIFO RX FIFO RX FIFO
CC1150
www.ti.com
SWRS037B –JANUARY 2006REVISED MARCH 2015
Greyed text: not implemented on CC1150 thus only valid for the transceiver version (CC1101)
Figure 5-19. SPI Address Space
Copyright © 2006–2015, Texas Instruments Incorporated Detailed Description 41
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS
CC1150
SWRS037B JANUARY 2006REVISED MARCH 2015
www.ti.com
5.20.1 Configuration Register Details
Table 5-14. 0x01: IOCFG1 – GDO1 Output Pin configuration
BIT FIELD TYPE RESET DESCRIPTION
7 GDO_DS R/W 0x0 Set high (1) or low (0) output drive strength on the GDO pins.
6 GDO1_INV R/W 0x0 Invert output, that is, select active low (1) / high (0).
5:0 GDO1_CFG[5:0] R/W 0x2E Default is tri-state (See Table 5-10).
Table 5-15. 0x02: IOCFG0 – GDO0 Output Pin Configuration
BIT FIELD TYPE RESET DESCRIPTION
7 TEMP_SENSOR_ENABLE R/W 0x0 Enable analog temperature sensor. Write 0 in all other register
bits when using temperature sensor.
6 GDO0_INV R/W 0x0 Invert output, that is, select active low (1) / high (0).
5:0 GDO0_CFG[5:0] R/W 0x3F Default is CLK_XOSC/192 (See Table 5-10).
It is recommended to disable the clock output during initialization
in order to optimize RF performance.
Table 5-16. 0x03: FIFOTHR – FIFO Threshold
BIT FIELD TYPE RESET DESCRIPTION
7:4 Reserved R/W 0x0 Write 0 for compatibility with possible future
extensions.
3:0 FIFO_THR[3:0] R/W 0x07 Set the threshold for the TX FIFO. The
threshold is exceeded when the number of
bytes in the FIFO is equal to or higher than the
threshold value.
The binary number is the setting and the result
(Bytes in TX FIFO) is the next state after
finishing packet transmission.
0000 = 61
0001 = 57
0010 = 53
0011 = 49
0100 = 45
0101 = 41
0110 = 37
0111 = 33
1000 = 29
1001 = 25
1010 = 21
1011 = 17
1100 = 13
1101 = 9
1110 = 5
1111 = 1
Table 5-17. 0x04: SYNC1 – Sync Word, High Byte
BIT FIELD TYPE RESET DESCRIPTION
7:0 SYNC[15:8] R/W 0xD3 8 MSB of 16-bit sync word.
Table 5-18. 0x05: SYNC0 – Sync Word, Low Byte
BIT FIELD TYPE RESET DESCRIPTION
7:0 SYNC[7:0] R/W 0x91 8 LSB of 16-bit sync word.
42 Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS
CC1150
www.ti.com
SWRS037B –JANUARY 2006REVISED MARCH 2015
Table 5-19. 0x06: PKTLEN – Packet Length
BIT FIELD TYPE RESET DESCRIPTION
7:0 PACKET_LENGTH R/W 0xFF Indicates the packet length when fixed length
packets are enabled. If variable packet length
mode is used, this value indicates the
maximum packet length allowed.
Table 5-20. 0x08: PKTCTRL0 – Packet Automation Control
BIT FIELD TYPE RESET DESCRIPTION
7 R0 Not Used.
6 WHITE_DATA R/W 0x1 Turn data whitening on / off
0: Whitening off
1: Whitening on
5:4 PKT_FORMAT[1:0] R/W 0x0 Format of TX data:
The binary number is the setting and the result
is the packet format.
00 = Normal mode, use TX FIFO
01 = Serial Synchronous mode, data in on
GDO0
...
10 = Random TX mode; sends random
data using PN9 generator. Used for
test/debug.
11 = Asynchronous transparent mode.
Data in on GDO0
3 R/W 0x0 Not used.
2 CRC_EN R/W 0x1 1: CRC calculation enabled
0: CRC disabled
1:0 LENGTH_CONFIG[1:0] R/W 0x1 Configure the packet length:
The binary number is the setting and the result
is the packet length configuration.
00 = Fixed length packets, length
configured in PKTLEN register
01 = Variable length packets, packet length
configured by the first byte after sync word
10 = Infinite packet length packets
11 = Reserved
Table 5-21. 0x09: ADDR – Device Address
BIT FIELD TYPE RESET DESCRIPTION
7:0 DEVICE_ADDRESS [7:0] R/W 0x0 Address used for packet filtration. Optional
broadcast addresses are 0 (0x00) and 255
(0xFF).
Table 5-22. 0x0A: CHANNR – Channel Number
BIT FIELD TYPE RESET DESCRIPTION
7:0 CHAN[7:0] R/W 0x0 The 8-bit unsigned channel number, which is
multiplied by the channel spacing setting and
added to the base frequency.
Copyright © 2006–2015, Texas Instruments Incorporated Detailed Description 43
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS
CHANSPC _ E
xosc
channel 18
f
f (256 CHANSPC _ M) 2 CHAN
2
D = ´ + ´ ´
[ ]
xosc
carrier 16
f
f FREQ 23 : 0
2
= ´
CC1150
SWRS037B JANUARY 2006REVISED MARCH 2015
www.ti.com
Table 5-23. 0x0D: FREQ2 – Frequency Control Word, High Byte
BIT FIELD TYPE RESET DESCRIPTION
7:6 FREQ[23:22] R 0x0 FREQ[23:22] is always 0 (the FREQ2 register
is less than 36 with 26 MHz or higher crystal
frequency).
5:0 FREQ[21:16] R/W 0x1E FREQ[23:0] is the base frequency for the
frequency synthesiser in increments of
FXOSC / 216.
(6)
Table 5-24. 0x0E: FREQ1 – Frequency Control Word, Middle Byte
BIT FIELD TYPE RESET DESCRIPTION
7:0 FREQ[15:8] R/W 0xC4 Ref. FREQ2 register.
Table 5-25. 0x0F: FREQ0 – Frequency Control Word, Low Byte
BIT FIELD TYPE RESET DESCRIPTION
7:0 FREQ[7:0] R/W 0xEC Ref. FREQ2 register.
Table 5-26. 0x10: MDMCFG4 – Modulator Configuration
BIT FIELD TYPE RESET DESCRIPTION
7:4 Reserved R0 0x08 Defined on the transceiver version (CC1101).
3:0 DRATE_E[3:0] R/W 0x0C The exponent of the user specified symbol
rate.
Table 5-27. 0x11: MDMCFG3 – Modulator Configuration
BIT FIELD TYPE RESET DESCRIPTION
7:0 DRATE_M[7:0] R/W 0x22 The mantissa of the user specified symbol rate. The symbol rate is
configured using an unsigned, floating-point number with 9-bit
mantissa and 4-bit exponent. The 9th bit is a hidden ‘1’. The
resulting data rate is:
(7)
The default values give a data rate of 115.051 kBaud (closest
setting to 115.2 kBaud), assuming a 26.0 MHz crystal.
44 Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS
CC1150
www.ti.com
SWRS037B –JANUARY 2006REVISED MARCH 2015
Table 5-28. 0x12: MDMCFG2 – Modulator Configuration
BIT FIELD TYPE RESET DESCRIPTION
7 Reserved R0 0x0 Defined on the transceiver version (CC1101).
6:4 MOD_FORMAT[2:0] R/W 0x0 The modulation format of the radio signal:
The binary number is the setting and the result is the
modulation format.
000 = 2-FSK
001 = GFSK
010 = N/A
011 = ASK/OOK
100 = N/A
101 = N/A
110 = N/A
111 = MSK
The OOK/ASK pulse shaping feature is only supported for
output powers up to –1 dBm.
MSK is only supported for data rates above 26 kBaud.
3 MANCHESTER_EN 0 0x0 Enables Manchester encoding/decoding.
0 = Disable
1 = Enable
2:0 SYNC_MODE[2:0] 2 0x2 Combined sync-word qualifier mode.
The values 0 (000) and 4 (100) disables preamble and sync
word transmission. The values 1 (001), 2 (010), 5 (101) and 6
(110) enables 16-bit sync word transmission. The values 3
(011) and 7 (111) enables repeated sync word transmission.
The binary number is the setting and the result is the Sync-
word qualifier mode (for compatibility with the CC1101
transceiver).
000 = No preamble/sync word
001 = 15/16 sync word bits detected
010 = 16/16 sync word bits detected
011 = 30/32 sync word bits detected
100 = No preamble/sync, carrier-sense above threshold
101 = 15/16 + carrier-sense above threshold
110 = 16/16 + carrier-sense above threshold
111 = 30/32 + carrier-sense above threshold
Table 5-29. 0x13: MDMCFG1 – Modulator Configuration
BIT FIELD TYPE RESET DESCRIPTION
7 FEC_EN R/W 0x2 Enable Forward Error Correction (FEC) with interleaving
for packet payload
0 = Disable
1 = Enable (Only supported for fixed packet length
mode, that is, PKTCTRL0.LENGTH_CONFIG=0)
6:4 NUM_PREAMBLE[2:0] R/W 0x2 Sets the minimum number of preamble bytes to be
transmitted.
The binary number is the setting and the result is the
minimum number of preamble bytes to be transmitted.
000 = 2
001 = 3
010 = 4
011 = 6
100 = 8
101 = 12
110 = 16
111 = 24
3:2 R0 Not Used.
1:0 CHANSPC_E[1:0] R/W 0x2 2 bit exponent of channel spacing.
Copyright © 2006–2015, Texas Instruments Incorporated Detailed Description 45
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS
DEVIATION _ E
xosc
dev 17
f
f (8 DEVIATION _ M) 2
2
= ´ + ´
CHANSPC _ E
xosc
channel 18
f
f (256 CHANSPC _ M) 2 CHAN
2
D = ´ + ´ ´
CC1150
SWRS037B JANUARY 2006REVISED MARCH 2015
www.ti.com
Table 5-30. 0x14: MDMCFG0 – Modulator Configuration
BIT FIELD TYPE RESET DESCRIPTION
7:0 CHANSPC_M[7:0] R/W 0xF8 8-bit mantissa of channel spacing (initial 1 assumed).
The channel spacing is multiplied by the channel
number CHAN and added to the base frequency. It is
unsigned and has the format:
(8)
The default values give 199.951 kHz channel spacing
(the closest setting to 200 kHz), assuming 26.0 MHz
crystal frequency.
Table 5-31. 0x15: DEVIATN – Modulator Deviation Setting
BIT FIELD TYPE RESET DESCRIPTION
7 R0 Not Used.
6:4 DEVIATION_E[2:0] R/W 0x4 Deviation exponent.
3 R0 Not Used.
2:0 DEVIATION_M[2:0] R/W 0x7 When MSK modulation is enabled:
Specifies the fraction of symbol period (1/8-8/8) during
which a phase change occurs (‘0’: +90deg, ‘1’: –90deg).
Refer to the SmartRF Studio [11] software for correct
DEVIATN setting when using MSK.
When 2-FSK/GFSK modulation is enabled:
Deviation mantissa, interpreted as a 4-bit value with MSB
implicit 1. The resulting frequency deviation is given by
Equation 9:
(9)
The default values give ±47.607 kHz deviation, assuming
26.0 MHz crystal frequency.
When ASK/OOK modulation is enabled:
This setting has no effect.
Table 5-32. 0x17: MCSM1 – Main Radio Control State Machine Configuration
BIT FIELD TYPE RESET DESCRIPTION
7:6 R0 Not Used.
5:2 Reserved R0 0x0C Defined on the transceiver version (CC1101).
1:0 TXOFF_MODE[1:0] R/W 0x0 Select what should happen when a packet has been
sent (TX):
The binary number is the setting and the result is the
next state after finishing packet transmission.
00 = IDLE
01 = FSTXON
10 = Stay in TX (start sending preamble)
11 = Do not use, not implemented on CC1150
46 Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS
CC1150
www.ti.com
SWRS037B –JANUARY 2006REVISED MARCH 2015
Table 5-33. 0x18: MCSM0 – Main Radio Control State Machine Configuration
BIT FIELD TYPE RESET DESCRIPTION
7:6 R0 Not Used.
5:4 FS_AUTOCAL[1:0] R/W 0x0 Automatically calibrate when going to TX, or back to
IDLE:
The binary number is the setting and the result is when
to perform automatic calibration.
00 = Never (manually calibrate using SCAL strobe)
01 = When going from IDLE to TX (or FSTXON)
10 = When going from TX back to IDLE
11 = Every 4th time when going from TX to IDLE
3:2 PO_TIMEOUT R/W 0x1 Programs the number of times the six-bit ripple counter
must expire after XOSC has stabilized before
CHP_RDY_N goes low.
The XOSC is off during power-down and if the regulated
digital supply voltage has sufficient time to stabilize while
waiting for the crystal to be stable, PO_TIMEOUT can be
set to 0. For robust operation it is recommended to use
PO_TIMEOUT=2.
The binary number is the setting, the result is the expire
count, and the definition is the timeout after XOSC start.
00 = 1 : Approx. 2.3 μs – 2.7 μs
01 = 16 : Approx. 37 μs – 43 μs
10 = 64 : Approx. 146 μs – 171 μs
11 = 256 : Approx. 585 μs – 683 μs
Exact timeout depends on crystal frequency.
In order to reduce start up time from the SLEEP state,
this field is preserved in powerdown (SLEEP state).
1:0 Reserved R0 Defined on the transceiver version (CC1101)
Table 5-34. 0x22: FREND0 – Front End TX Configuration
BIT FIELD TYPE RESET DESCRIPTION
7:6 R0 Not Used.
5:4 LODIV_BUF_ R/W 0x1 Adjusts current TX LO buffer (input to PA).
CURRENT_TX[1:0] The value to use in register field is given by
the SmartRF Studio [11] software.
3 R0 Not Used.
2:0 PA_POWER[2:0] R/W 0x0 Selects PA power setting. This value is an
index to the PATABLE, which can be
programmed with up to 8 different PA
settings. In ASK mode, this selects the
PATABLE index to use when transmitting a
‘1’. PATABLE index zero is used in ASK when
transmitting a ‘0’. The PATABLE settings from
index ‘0’ to the PA_POWER value are used
for ASK TX shaping, and for power ramp-
up/ramp-down at the start/end of transmission
in all TX modulation formats.
Copyright © 2006–2015, Texas Instruments Incorporated Detailed Description 47
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS
CC1150
SWRS037B JANUARY 2006REVISED MARCH 2015
www.ti.com
Table 5-35. 0x23: FSCAL3 – Frequency Synthesizer Calibration
BIT FIELD TYPE RESET DESCRIPTION
7:6 FSCAL3[7:6] R/W 0x02 Frequency synthesizer calibration
configuration. The value to write in this field
before calibration is given by the SmartRF
Studio software.
5:4 CHP_CURR_CAL_EN[1:0] R/W 0x02 Disable charge pump calibration stage when
0.
3:0 FSCAL3[3:0] R/W 0x09 Frequency synthesizer calibration result
register. Digital bit vector defining the charge
pump output current, on an exponential scale:
I_OUT = I0·2FSCAL3[3:0]/4.
Fast frequency hopping without calibration for
each hop can be done by calibrating up front
for each frequency and saving the resulting
FSCAL3, FSCAL2 and FSCAL1 register
values. Between each frequency hop,
calibration can be replaced by writing the
FSCAL3, FSCAL2 and FSCAL1 register
values corresponding to the next RF
frequency.
Table 5-36. 0x24: FSCAL2 – Frequency Synthesizer Calibration
BIT FIELD TYPE RESET DESCRIPTION
7:6 R0 Not Used.
5 VCO_CORE_H_EN R/W 0x0 Choose high (1)/ low (0) VCO.
5:0 FSCAL2[5:0] R/W 0x0A Frequency synthesizer calibration result register. VCO
current calibration result and override value.
Fast frequency hopping without calibration for each
hop can be done by calibrating up front for each
frequency and saving the resulting FSCAL3, FSCAL2
and FSCAL1 register values. Between each frequency
hop, calibration can be replaced by writing the
FSCAL3, FSCAL2 and FSCAL1 register values
corresponding to the next RF frequency.
Table 5-37. 0x25: FSCAL1 – Frequency Synthesizer Calibration
BIT FIELD TYPE RESET DESCRIPTION
7:6 R0 Not Used.
5:0 FSCAL1[5:0] R/W 0x20 Frequency synthesizer calibration result register. Capacitor
array setting for VCO coarse tuning.
Fast frequency hopping without calibration for each hop
can be done by calibrating up front for each frequency and
saving the resulting FSCAL3, FSCAL2 and FSCAL1
register values. Between each frequency hop, calibration
can be replaced by writing the FSCAL3, FSCAL2 and
FSCAL1 register values corresponding to the next RF
frequency.
Table 5-38. 0x26: FSCAL0 – Frequency Synthesizer Calibration
BIT FIELD TYPE RESET DESCRIPTION
7 Reserved R0 Not Used.
6:0 FSCAL0[6:0] R/W 0x0D Frequency synthesizer calibration control. The
value to use in register field is given by the
SmartRF Studio [11] software.
Table 5-39. 0x29: FSTEST – Frequency Synthesizer Calibration Control
BIT FIELD TYPE RESET DESCRIPTION
7:0 FSTEST[7:0] R/W 0x57 For test only. Do not write to this register.
48 Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS
CC1150
www.ti.com
SWRS037B –JANUARY 2006REVISED MARCH 2015
Table 5-40. 0x2A: PTEST – Production Test
BIT FIELD TYPE RESET DESCRIPTION
7:0 PTEST[7:0] R/W 0x7F Writing 0xBF to this register makes the on-
chip temperature sensor available in the IDLE
state. The default 0x7F value should then be
written back before leaving the IDLE state.
Other use of this register is for test only.
Table 5-41. 0x2C: TEST2 – Various Test Settings
BIT FIELD TYPE RESET DESCRIPTION
7:0 TEST2[7:0] R/W The value to use in this register is given by
the SmartRF Studio [11] software.
Table 5-42. 0x2D: TEST1 – Various Test Settings
BIT FIELD TYPE RESET DESCRIPTION
7:0 TEST1[7:0] R/W 0x21 The value to use in this register is given by
the SmartRF Studio [11] software.
Table 5-43. 0x2E: TEST0 – Various Test Settings
BIT FIELD TYPE RESET DESCRIPTION
7:2 TEST0[7:2] R/W 0x02 The value to use in this register is given by
the SmartRF Studio [11] software.
1 VCO_SEL_CAL_EN R/W 0x1 Enable VCO selection calibration stage when
1. The value to use in this register is given by
the SmartRF Studio [11] software.
0 TEST0[0] R/W 0x1 The value to use in this register is given by
the SmartRF Studio [11] software.
5.20.2 Status Register Details
Table 5-44. 0x30 (0xF0): PARTNUM – Chip ID
BIT FIELD TYPE RESET DESCRIPTION
7:0 PARTNUM[7:0] R 0x02 Chip part number.
Table 5-45. 0x31 (0xF1): VERSION – Chip ID
BIT FIELD TYPE RESET DESCRIPTION
7:0 VERSION[7:0] R 0x04 Chip version number.
Subject to change without notice
Copyright © 2006–2015, Texas Instruments Incorporated Detailed Description 49
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS
CC1150
SWRS037B JANUARY 2006REVISED MARCH 2015
www.ti.com
Table 5-46. 0x35 (0xF5): MARCSTATE – Main Radio Control State Machine State
BIT FIELD TYPE RESET DESCRIPTION
7:5 Reserved R0
4:0 MARC_STATE[4:0] R Main Radio Control FSM State(1)
The bit enumerations show the value, the state name, and
the state(2).
0x00 = SLEEP : SLEEP
0x01 = IDLE : IDLE
0x02 = XOFF : XOFF
0x03 = VCOON_MC : MANCAL
0x04 = REGON_MC : MANCAL
0x05 = MANCAL : MANCAL
0x06 = VCOON : FS_WAKEUP
0x07 = REGON : FS_WAKEUP
0x08 = STARTCAL : CALIBRATE
0x09 = BWBOOST : SETTLING
0x0A = FS_LOCK : SETTLING
0x0B = N/A : N/A
0x0C = ENDCAL : CALIBRATE
0x0D = N/A : N/A
0x0E = N/A : N/A
0x0F = N/A : N/A
0x10 = N/A : N/A
0x11 = N/A : N/A
0x12 = FSTXON : FSTXON
0x13 = TX : TX
0x14 = TX_END : TX
0x15 = N/A : N/A
0x16 = TX_UNDERFLOW : TX_UNDERFLOW
(1) It is not possible to read back the SLEEP or XOFF state numbers because setting CSn low will make the chip enter the IDLE mode from
the SLEEP or XOFF states.
(2) State (see Figure 5-11).
Table 5-47. 0x38 (0xF8): PKTSTATUS – Current GDOx Status
BIT FIELD TYPE RESET DESCRIPTION
7:2 Reserved R0 Defined on the transceiver version (CC1101).
1 R0 Not Used.
0 GDO0 R Current GDO0 value. Note: the reading gives the
non-inverted value irrespective what
IOCFG0.GDO0_INV is programmed to.
It is not recommended to check for PLL lock by
reading PKTSTATUS[0] with GDO0_CFG = 0x0A.
Table 5-48. 0x39 (0xF9): VCO_VC_DAC – Current Setting from PLL Calibration Module
BIT FIELD TYPE RESET DESCRIPTION
7:0 VCO_VC_DAC[7:0] R Status registers for test only.
Table 5-49. 0x3A (0xFA): TXBYTES – Underflow and Number of Bytes
BIT FIELD TYPE RESET DESCRIPTION
7 TXFIFO_UNDERFLOW R
6:0 NUM_TXBYTES R Number of bytes in TX FIFO.
50 Detailed Description Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS
Digital Inteface
1.8 V-3.6 V power supply
8 GDO0
5 XOSC_Q1
6 AVDD
7 XOSC_Q2
SI 16
DGUARD 15
RBIAS 14
AVDD 13
1 SCLK
2 SO
(GDO1)
3 DVDD
4 DCOUPL
AVDD 12
RF_N 11
RF_P 10
CSn 9
XTAL
R141
C51 C71
C41
CSn
GDO0
(optional)
SO
(GDO1)
SCLK
SI
CC1150
DIE ATTACH PAD:
Antenna
(50 Ohm)
L102 L103
C102 C103
C105
C111
C101
L101
L111
C104
CC1150
www.ti.com
SWRS037B –JANUARY 2006REVISED MARCH 2015
6 Applications, Implementation, and Layout
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
6.1 Application Information
6.1.1 Typical Application
A simplified block diagram of CC1150 is shown in Figure 5-1.
Only a few external components are required for using the CC1150. The recommended application circuits
are shown in Figure 6-1 and Figure 6-2. The external components are described in Table 6-1, and typical
values are given in Table 6-2.
Figure 6-1. Typical Application and Evaluation Circuit 315/433 MHz
(Excluding Supply Decoupling Capacitors)
Copyright © 2006–2015, Texas Instruments Incorporated Applications, Implementation, and Layout 51
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS L111 L104 W 1
Digital Inteface
1.8 V-3.6 V power supply
8 GDO0
5 XOSC_Q1
6 AVDD
7 XOSC_Q2
SI 16
DGUARD 15
RBIAS 14
AVDD 13
1 SCLK
2 SO
(GDO1)
3 DVDD
4 DCOUPL
AVDD 12
RF_N 11
RF_P 10
CSn 9
XTAL
R141
C51 C71
C41
CSn
GDO0
(optional)
SO
(GDO1)
SCLK
SI
CC1150
DIE ATTACH PAD:
Antenna
(50 Ohm)
L101
C105
L111
L104
C101
C102
L102
L112
C104
C111
L103
C103
C106L105
C106 and L105 may
be added to build an
optional filter to reduce
emission at 699 MHz
CC1150
SWRS037B JANUARY 2006REVISED MARCH 2015
www.ti.com
Figure 6-2. Typical Application and Evaluation Circuit 868/915 MHz
(Excluding Supply Decoupling Capacitors)
Table 6-1. Overview of External Components (Excluding Supply Decoupling Capacitors)
COMPONENT DESCRIPTION
C41 Decoupling capacitor for on-chip voltage regulator to digital part
C51/C71 Crystal loading capacitors
C101/C111 RF balun/matching capacitors
C102 RF LC filter/matching filter capacitor (315 and 433 MHz). RF balun/matching capacitor (868/915 MHz).
C103 RF LC filter/matching capacitors
C104 RF balun DC blocking capacitor
C105 RF LC filter DC blocking capacitor and part of optional RF LC filter (868/915 MHz)
C106 Part of optional RF LC filter and DC Block (868/915 MHz)
L101/L111 RF balun/matching inductors (inexpensive multi-layer type)
RF LC filter/matching filter inductor (315 and 433 MHz). RF balun/matching inductor (868/915 MHz)
L102 (inexpensive multi-layer type)
L103 RF LC filter/matching inductor (inexpensive multi-layer type)
L104 RF LC filter/matching inductor (inexpensive multi-layer type)
L105 Part of optional RF LC filter (868/915 MHz)(inexpensive multi-layer type)
R141 Resistor for internal bias current reference
XTAL 26 to 27 MHz crystal
52 Applications, Implementation, and Layout Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS CC1 150EM433 CC1150EM868.
CC1150
www.ti.com
SWRS037B –JANUARY 2006REVISED MARCH 2015
Table 6-2. Bill of Materials for the Application Circuit(1)
COMPONENT VALUE @ 31 5MHz VALUE @ 433 MHz VALUE @ 868/915 MHz
C41 100 nF ± 10%, 0402 X5R
C51 27 pF ± 5%, 0402 NP0
C71 27 pF ± 5%, 0402 NP0
C101 6.8 pF ± 0.5 pF, 0402 NP0 3.9 pF ± 0.25 pF, 0402 NP0 1.0 pF ± 0.25 pF, 0402 NP0
C102 12 pF ± 5%, 0402 NP0 8.2 pF ± 0.5 pF, 0402 NP0 1.5 pF ± 0.25 pF, 0402 NP0
C103 6.8 pF ± 0.5 pF, 0402 NP0 5.6 pF ± 0.5pF, 0402 NP0 3.3 pF ± 0.25 pF, 0402 NP0
C104 220 pF ± 5%, 0402 NP0 220 pF ± 5%, 0402 NP0 100 pF ± 5%, 0402 NP0
100 pF ± 5%, 0402 NP0
C105 220 pF ± 5%, 0402 NP0 220 pF ± 5%, 0402 NP0 (12 pF ± 5%, 0402 NP0 if optionally
699 MHz filter is desired)
(47 pF ± 5%, 0402 NP0 if optionally
C106 699 MHz filter is desired)
C111 6.8 pF ± 0.5 pF, 0402 NP0 3.9 pF ± 0.25 pF, 0402 NP0 1.5 pF ± 0.25pF, 0402 NP0
L101 33 nH ± 5%, 0402 monolithic 27 nH ± 5%, 0402 monolithic 12 nH ± 5%, 0402 monolithic
L102 18 nH ± 5%, 0402 monolithic 22 nH ± 5%, 0402 monolithic 18 nH ± 5%, 0402 monolithic
L103 33 nH ± 5%, 0402 monolithic 27 nH ± 5%, 0402 monolithic 12 nH ± 5%, 0402 monolithic
(12 nH ± 5%, 0402 monolithic if
L104 optionally 699 MHz filter is desired)
L105 3.3 nH ± 5%, 0402 monolithic
L111 33 nH ± 5%, 0402 monolithic 27 nH ± 5%, 0402 monolithic 12 nH ± 5%, 0402 monolithic
L112 18 nH ± 5%, 0402 monolithic
R141 56 kΩ±1%, 0402
XTAL 26.0 MHz surface mount crystal
(1) Murata LQG15HS and GRM1555C series inductors and capacitors, resistor from the Koa RK73 series, and AT-41CD2 crystal from NDK
6.2 Design Requirements
6.2.1 Bias Resistor
The bias resistor R141 is used to set an accurate bias current.
6.2.2 Balun and RF Matching
The components between the RF_N/RF_P pins and the point where the two signals are joined together
[(C111, C101, L101 and L111 for the 315/433 MHz design) and (L101, L111, C101, L102, C111, C102
and L112 for the 868/915 MHz reference design)] form a balun that converts the differential RF signal on
CC1150 to a single-ended RF signal. C104 is needed for dc blocking. Together with an appropriate LC
filter network, the balun components also transform the impedance to match a 50-Ωantenna (or cable).
C105 provides dc blocking and is only needed if there is a dc path in the antenna. For the 868/915 MHz
reference design, this component may also be used for additional filtering, see Section 6.2.5.
Suggested values for 315 MHz, 433 MHz, and 868/915 MHz are listed in Table 6-2.
The balun and LC filter component values and their placement are important to achieve optimal
performance. It is highly recommended to follow the CC1150EM reference design (see [1] and [2]). Gerber
files and schematics for the reference designs are available for download from CC1150EM433 and
CC1150EM868.
Copyright © 2006–2015, Texas Instruments Incorporated Applications, Implementation, and Layout 53
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS X D :E xoscioz I
XOSC_Q1 XOSC_Q2
XTAL
C51 C71
L parasitic
51 71
1
C C
1 1
C C
= +
+
CC1150
SWRS037B JANUARY 2006REVISED MARCH 2015
www.ti.com
6.2.3 Crystal
A crystal in the frequency range of 26 to 27 MHz must be connected between the XOSC_Q1 and
XOSC_Q2 pins. The oscillator is designed for parallel mode operation of the crystal. In addition, loading
capacitors (C51 and C71) for the crystal are required. The loading capacitor values depend on the total
load capacitance, CL, specified for the crystal. The total load capacitance seen between the crystal
terminals should equal CLfor the crystal to oscillate at the specified frequency.
(10)
The parasitic capacitance is constituted by pin input capacitance and PCB stray capacitance. Total
parasitic capacitance is typically 2.5 pF.
The crystal oscillator circuit is shown in Figure 6-3. Typical component values for different values of CLare
given in Table 6-3.
Figure 6-3. Crystal Oscillator Circuit
The crystal oscillator is amplitude regulated. This means that a high current is used to start up the
oscillations. When the amplitude builds up, the current is reduced to what is necessary to maintain
approximately 0.4 Vpp signal swing. This ensures a fast start up, and keeps the drive level to a minimum.
The ESR of the crystal should be within the specification in order to ensure a reliable start up (see
Section 4.7).
The initial tolerance, temperature drift, aging and load pulling should be carefully specified in order to meet
the required frequency accuracy in a certain application.
Table 6-3. Crystal Oscillator Component Values
COMPONENT CL= 10 pF CL= 13 pF CL= 16 pF
C51 15 pF 22 pF 27 pF
C71 15 pF 22 pF 27 pF
54 Applications, Implementation, and Layout Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS
CC1150
www.ti.com
SWRS037B –JANUARY 2006REVISED MARCH 2015
6.2.4 Reference Signal
The chip can alternatively be operated with a reference signal from 26 to 27 MHz instead of a crystal. This
input clock can either be a full-swing digital signal (0 V to VDD) or a sine wave of maximum 1-V peak-to-
peak amplitude. The reference signal must be connected to the XOSC_Q1 input. The sine wave must be
connected to XOSC_Q1 using a serial capacitor. The XOSC_Q2 line must be left unconnected. C51 and
C71 can be omitted when using a reference signal.
6.2.5 Additional Filtering
In the 868/915 MHz reference design, C106 and L105 together with C105 build an optional filter to reduce
emission at 699 MHz. This filter may be necessary for applications seeking compliance with ETSI EN 300-
220, for more information, see DN017 [6]. If this filtering is not necessary, C105 will work as a DC block
(only necessary if there is a DC path in the antenna). C106 and L105 should in that case be left
unmounted.
Additional external components (for example, an RF SAW filter) may be used in order to improve the
performance in specific applications. The use of wire-wound inductors in the application circuit will also
improve the RF performance and give higher output power. For more information, see DN017 [6].
6.2.6 Power Supply Decoupling
The power supply must be properly decoupled close to the supply pins.
NOTE
Decoupling capacitors are not shown in the application circuit. The placement and the size of
the decoupling capacitors are very important to achieve the optimum performance.
The CC1150EM reference design should be followed closely (see [1] and [2]).
6.3 PCB Layout Recommendations
The top layer should be used for signal routing, and the open areas should be filled with metallization
connected to ground using several vias.
The area under the chip is used for grounding and shall be connected to the bottom ground plane with
several vias for good thermal performance and sufficiently low inductance to ground.
In the CC1150EM reference designs (see [1] and [2]), 5 vias are placed inside the exposed die attached
pad. These vias should be “tented” (covered with solder mask) on the component side of the PCB to avoid
migration of solder through the vias during the solder-reflow process.
The solder paste coverage should not be 100%. If it is, out gassing may occur during the reflow process,
which may cause defects (splattering, solder balling). Using “tented” vias reduces the solder paste
coverage below 100%. See Figure 6-4 for top solder resist and top paste masks.
All the decoupling capacitors should be placed as close as possible to the supply pin it is supposed to
decouple. Each decoupling capacitor should be connected to the power line (or power plane) by separate
vias. The best routing is from the power line (or power plane) to the decoupling capacitor and then to the
CC1150 supply pin. Supply power filtering is very important.
Copyright © 2006–2015, Texas Instruments Incorporated Applications, Implementation, and Layout 55
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS A m \/ V m \/ r\ 1‘ u \/
CC1150
SWRS037B JANUARY 2006REVISED MARCH 2015
www.ti.com
Each decoupling capacitor ground pad should be connected to the ground plane by separate vias. Direct
connections between neighboring power pins will increase noise coupling and should be avoided unless
absolutely necessary. Routing in the ground plane underneath and between the chip, the balun/RF
matching circuit and the decoupling capacitor’s ground vias should also be avoided. This improves the
grounding and ensures the shortest possible return path for stray currents.
The external components should ideally be as small as possible (0402 is recommended) and surface
mount devices are highly recommended. Please note that components smaller than those specified may
have differing characteristics.
Precaution should be used when placing the microcontroller in order to avoid noise interfering with the RF
circuitry.
It is strongly advised that the CC1150EM reference design (see [1] and [2]) layout is followed very closely
in order to get the best performance. Gerber files and schematics for the reference designs are available
for download from the TI website.
Circles are Vias
Figure 6-4. Left: Top Solder Resist Mask (Negative) and Right: Top Paste Mask
56 Applications, Implementation, and Layout Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS 8.28mm 2.4ern \ B.7Bmm [2|me BBSmm 8.37mm 2.88mm
CC1150
www.ti.com
SWRS037B –JANUARY 2006REVISED MARCH 2015
6.3.1 Package Description (QLP 16)
Figure 6-5. Recommended PCB Layout for Package (QLP 16)
Figure 6-5 is an illustration only and not to scale. There are five 10-mil diameter via holes distributed
symmetrically in the ground pad under the package. See also the CC1150EM reference design ( [1] and
[2]).
Copyright © 2006–2015, Texas Instruments Incorporated Applications, Implementation, and Layout 57
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS (www.1i.com) www.1i.com. (SWRROM) (SWRRO42) (SWRA150) (SWRA123) (SWRA168) (SWRA161) (SWRZm a) (SWRA110) (SWRAOQO) (SmanRF Studio) (SWRU109) Terms of Use.
CC1150
SWRS037B JANUARY 2006REVISED MARCH 2015
www.ti.com
7 Device and Documentation Support
7.1 Device Support
7.1.1 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers. Each
device has one of three prefixes: X, P, or null (no prefix) (for example, CC1150 is in production; therefore,
no prefix is assigned).
Device development evolutionary flow:
XExperimental device that is not necessarily representative of the final device's electrical
specifications and may not use production assembly flow.
PPrototype device that is not necessarily the final silicon die and may not necessarily meet
final electrical specifications.
null Production version of the silicon die that is fully qualified.
Production devices have been characterized fully, and the quality and reliability of the device have been
demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be
used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, RGV).
For orderable part numbers of CC1150 devices in the RGV
package types, see the Package Option Addendum of this document, the TI website (www.ti.com), or
contact your TI sales representative.
7.2 Documentation Support
The following documents describe the CC1150 device. Copies of these documents are available on the
Internet at www.ti.com.
1. [1] CC1150EM 315 – 433 MHz Reference Design (SWRR041)
2. [2] CC1150EM 868 – 915 MHz Reference Design (SWRR042)
3. [3] DN012 Programming Output Power on CC1100 and CC1150 (SWRA150)
4. [5] DN006 CC11xx Settings for FCC 15.247 Solutions (SWRA123)
5. [6] DN017 CC11xx 868/915 MHz Matching (SWRA168)
6. [7] AN058 Antenna Selection Guide (SWRA161)
7. [8] CC1150 Errata Notes (SWRZ018)
8. [9] DN501 PATABLE Access (SWRA110)
9. [10] AN001 SRD Regulations for Licence Free Transceiver Operation (SWRA090)
10. [11] (SmartRF Studio)
11. [12] CC1100/CC1150DK and CC2500/CC2550DK Development Kit Examples and Libraries User
Manual (SWRU109)
7.2.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
58 Device and Documentation Support Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: CC1150
l TEXAS INSTRUMENTS Tl EZEW Online Commu 1 TI Embedded Processors Wiki SLY2022
CC1150
www.ti.com
SWRS037B –JANUARY 2006REVISED MARCH 2015
TI E2E Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster
collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,
explore ideas and help solve problems with fellow engineers.
TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help
developers get started with Embedded Processors from Texas Instruments and to foster
innovation and growth of general knowledge about the hardware and software surrounding
these devices.
7.3 Trademarks
SmartRF, E2E are trademarks of Texas Instruments.
7.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
7.5 Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data
(as defined by the U.S., EU, and other Export Administration Regulations) including software, or any
controlled product restricted by other applicable national regulations, received from disclosing party under
nondisclosure obligations (if any), or any direct product of such technology, to any destination to which
such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior
authorization from U.S. Department of Commerce and other competent Government authorities to the
extent required by those laws.
7.6 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
8 Mechanical Packaging and Orderable Information
8.1 Packaging Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2006–2015, Texas Instruments Incorporated Mechanical Packaging and Orderable Information 59
Submit Documentation Feedback
Product Folder Links: CC1150
I TEXAS INSTRUMENTS Sample: Sample:
PACKAGE OPTION ADDENDUM
www.ti.com 7-Mar-2016
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
CC1150-RTR1 OBSOLETE VQFN RST 16 TBD Call TI Call TI -40 to 85 CC1150
CC1150-RTY1 OBSOLETE VQFN RST 16 TBD Call TI Call TI -40 to 85 CC1150
CC1150RGVR ACTIVE VQFN RGV 16 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR -40 to 85 CC1150
CC1150RGVT ACTIVE VQFN RGV 16 250 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR -40 to 85 CC1150
CC1150RST OBSOLETE VQFN RST 16 TBD Call TI Call TI -40 to 85 CC1150
CC1150RSTR OBSOLETE VQFN RST 16 TBD Call TI Call TI -40 to 85 CC1150
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 7-Mar-2016
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
I TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “K0 '«m» Reel Diame|er AD Dimension deswgned to accommodate the componem wwdlh E0 Dimension desxgned to accommodate the componenl \ength KO Dimenslun deswgned to accommodate the componem thickness 7 w OveraH wwdm loe earner cape i p1 Pitch between successwe cavuy cemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D O Sprockemoles ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CC1150RGVR VQFN RGV 16 2500 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2
CC1150RGVT VQFN RGV 16 250 180.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 21-Nov-2016
Pack Materials-Page 1
I TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CC1150RGVR VQFN RGV 16 2500 336.6 336.6 28.6
CC1150RGVT VQFN RGV 16 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 21-Nov-2016
Pack Materials-Page 2
MECHANICAL DATA YGV (Si'flmeim 13> 3‘ WSWC QUAD H A '/'\'3K K37 7/0 4 fl » \ V V 4 v V 4 v \ \ U U M ‘ A ‘ fl“ 3 P , 3 x ' H H H >4 NC‘LS A‘ hue/Jr mmenswons are m mflhmetem Dwmens amng C’vd (c‘erancv‘g per ASML W45N719§4 fimDOm) Tm: draw'flq ‘5 subject to change We“: rohce Quad F‘ut' , NW‘euds (ow) pucmge omngmum, The par, as warm pod r'ust be so‘deved to the board 101 (hevmu‘ and 'vvedvuvicn‘ peflorvnuuce See me uscwhoru‘ Ngme n we swam pm Sweet ‘01 salads 'eguvdvg he exucsed UVev'vvu‘ pod Vectmes and dwnens'w'vs Fm S w M 1 yEDEC M07220 {if TEXAS INSTRUMENTS www.1i.com
THERMAL PAD MECHANICAL DATA RGV ($7PVQFN7NTB) PLASTlC QUAD FLATPACK NoiLEAD THERMAL lNFORMATlON This package incorporates an exposed thermal pad that is designed to be attached directly to an external heatsink. The thermal pad rnust be soldered directly to the printed circuit board (PCB). After soldering, the PCB can be used as a heatsink. in addition. through the use of thermal vias. the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device. or alternatively. can be attached to a special heatsink structure designed into the PCB. This design optimizes the heat transfer from the integrated circuit (lC), For iniormation on the Quad Flatpack NoiLead (OFN) package and its advantages, refer to Application Report. OFN/SON PCB Attachment. Texas instruments Literature No. SLUA27l. This document is available at www,ticorn, The exposed thermal pad dimensions (or this package are shown in the following illustration. PIN i lNDlCATOR C 0,30 ‘l 4 \L; U U U Exposed Thermal Pad 16 C5 3 C 2.30:0,10 D l C ‘3 C5 0 {T 12 9 2.3010,“) Bottom Wew Exposed Thermal Pad Dimensions 4206351—4/L 05/13 NOTE: All linear dimensions are in millimeters {I} TEXAS INSTRUMENTS www.ti.cum
MECHANICAL DATA RST (S—PQFP—N16) PLASTIC QUAD FLATF’ACK Exposed Tre'mm Ewe Fad A 16 ‘5 «16x7 0,35 0,73 I3 m YLBE 390 3,65 W I-I-l-I_*T_L Seemg Pmne (M90 0‘65 045 4ZC7SOS/A 04/06 NO’ES' A. AH Hnec' dimensmrs c'e m m'Hmekers I3 Th5 drawer ‘3 sums , 0 change thruut nohce C o’N (mud Hctnunk Na Lead) Package cunfgumfiur A3 The package hema‘ pad 'vms‘ he smderec m We board for trevmew and memnem pe'formmce See the 310(1ch 3m Sheet w d eafls reqcvdwg he exposed (henna pm: dvhe'vswns ‘4‘ TEXAS INSTRUMENTS www.li.com
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2016, Texas Instruments Incorporated

Products related to this Datasheet

RF TX IC 2-FSK 300-348MHZ 16QFN
RF TX IC 2-FSK 300-348MHZ 16QFN
RF TX IC 2-FSK 300-348MHZ 16QFN
RF TX IC 2-FSK 300-348MHZ 16QFN
RF TX IC 2-FSK 300-348MHZ 16QFN
RF TX IC 2-FSK 300-348MHZ 16QFN