XMC4300 Datasheet by Infineon Technologies

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Data Sheet
V1.1 2018-09
Microcontrollers
XMC4300
Microcontroller Series
for Industrial Applications
XMC4000 Family
ARM® Cortex®-M4
32-bit processor core
Edition 2018-09
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2018 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
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and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
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@w
Data Sheet
V1.1 2018-09
Microcontrollers
XMC4300
Microcontroller Series
for Industrial Applications
XMC4000 Family
ARM® Cortex®-M4
32-bit processor core
Inhneon”
XMC4300
XMC4000 Family
Data Sheet V1.1, 2018-09
Trademarks
C166™, TriCore™, XMC™ and DAVE™ are trademarks of Infineon Technologies AG.
ARM®, ARM Powered®, Cortex®, Thumb® and AMBA® are registered trademarks of
ARM, Limited.
CoreSight™, ETM™, Embedded Trace Macrocell™ and Embedded Trace Buffer™ are
trademarks of ARM, Limited.
Synopsys™ is a trademark of Synopsys, Inc.
XMC4300 Data Sheet
Revision History: V1.1 2018-09
Previous Versions:
V1.0 2016-02
Page Subjects
Initial version.
42 Added RMS Noise parameter in VADC Parameters table.
We Listen to Your Comments
Is there any information in this document that you feel is wrong, unclear or missing?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
mcdocu.comments@infineon.com
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XMC4300
XMC4000 Family
Table of Contents
Data Sheet 5 V1.1, 2018-09
1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.2 Device Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3 Device Type Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.4 Definition of Feature Variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.5 Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2 General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1 Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2 Pin Configuration and Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.1 Package Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.2 Port I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2.2.1 Port I/O Function Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3 Power Connection Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.1 General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.1.1 Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.1.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.1.3 Pin Reliability in Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.1.4 Pad Driver and Pad Classes Summary . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.1.5 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.2 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.2.1 Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.2.2 Analog to Digital Converters (VADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.2.3 Digital to Analog Converters (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.2.4 Out-of-Range Comparator (ORC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.2.5 Die Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.2.6 USB OTG Interface DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.2.7 Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.2.8 Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.2.9 Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.3 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.3.1 Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.3.2 Power-Up and Supply Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.3.3 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.3.4 Phase Locked Loop (PLL) Characteristics . . . . . . . . . . . . . . . . . . . . . . 68
3.3.5 Internal Clock Source Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.3.6 JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.3.7 Serial Wire Debug Port (SW-DP) Timing . . . . . . . . . . . . . . . . . . . . . . . . 73
3.3.8 Peripheral Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.3.8.1 Synchronous Serial Interface (USIC SSC) Timing . . . . . . . . . . . . . . 74
Table of Contents
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XMC4300
XMC4000 Family
Table of Contents
Data Sheet 6 V1.1, 2018-09
3.3.8.2 Inter-IC (IIC) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.3.8.3 Inter-IC Sound (IIS) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.3.8.4 SDMMC Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
3.3.9 USB Interface Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
3.3.10 Ethernet Interface (ETH) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 91
3.3.10.1 ETH Measurement Reference Points . . . . . . . . . . . . . . . . . . . . . . . . 91
3.3.10.2 ETH Management Signal Parameters (ETH_MDC, ETH_MDIO) . . . 92
3.3.10.3 ETH RMII Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
3.3.11 EtherCAT (ECAT) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
3.3.11.1 ECAT Measurement Reference Points . . . . . . . . . . . . . . . . . . . . . . . 94
3.3.11.2 ETH Management Signal Parameters (MCLK, MDIO) . . . . . . . . . . . 94
3.3.11.3 MII Timing TX Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
3.3.11.4 MII Timing RX Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
3.3.11.5 Sync/Latch Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4 Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.1 Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.1.1 Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.2 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
5 Quality Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
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XMC4300
XMC4000 Family
About this Document
Data Sheet 7 V1.1, 2018-09
About this Document
This Data Sheet is addressed to embedded hardware and software developers. It
provides the reader with detailed descriptions about the ordering designations, available
features, electrical and physical characteristics of the XMC4300 series devices.
The document describes the characteristics of a superset of the XMC4300 series
devices. For simplicity, the various device types are referred to by the collective term
XMC4300 throughout this manual.
XMC4000 Family User Documentation
The set of user documentation includes:
Reference Manual
decribes the functionality of the superset of devices.
Data Sheets
list the complete ordering designations, available features and electrical
characteristics of derivative devices.
Errata Sheets
list deviations from the specifications given in the related Reference Manual or
Data Sheets. Errata Sheets are provided for the superset of devices.
Attention: Please consult all parts of the documentation set to attain consolidated
knowledge about your device.
Application related guidance is provided by Users Guides and Application Notes.
Please refer to http://www.infineon.com/xmc4000 to get access to the latest versions
of those documents.
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XMC4300
XMC4000 Family
Summary of Features
Data Sheet 8 V1.1, 2018-09
1 Summary of Features
The XMC4300 devices are members of the XMC4000 Family of microcontrollers based
on the ARM Cortex-M4 processor core. The XMC4000 is a family of high performance
and energy efficient microcontrollers optimized for Industrial Connectivity, Industrial
Control, Power Conversion, Sense & Control.
Figure 1 System Block Diagram
CPU Subsystem
•CPU Core
High Performance 32-bit ARM Cortex-M4 CPU
16-bit and 32-bit Thumb2 instruction set
DSP/MAC instructions
System timer (SysTick) for Operating System support
Floating Point Unit
Memory Protection Unit
Nested Vectored Interrupt Controller
General Purpose DMA with up-to 8 channels
Event Request Unit (ERU) for programmable processing of external and internal
service requests
Flexible CRC Engine (FCE) for multiple bit error detection
PMU
ROM & Flash
Bus Matrix
CPU
ARM Cortex-M4
DSRAM1PSRAM
FCE
GPDMA0 USB
OTG
Ethernet
DCodeSystem ICode
Peripherals 0 Peripherals 1
PBA0
Data Code
WDT
RTC
ERU0
SCU
ERU1 VADC CCU40 CCU41
USIC0 CCU80 LEDTS0 PORTS DAC
SDMMC USIC1
MultiCAN
System
Masters System
Slaves
PBA1
EtherCAT
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XMC4300
XMC4000 Family
Summary of Features
Data Sheet 9 V1.1, 2018-09
On-Chip Memories
16 KB on-chip boot ROM
64 KB on-chip high-speed program memory
64 KB on-chip high speed data memory
256 KB on-chip Flash Memory with 8 KB instruction cache
Communication Peripherals
Ethernet MAC module capable of 10/100 Mbit/s transfer rates
EtherCATSlave interface (ECAT) capable of 100 Mbit/s transfer rates with 2 MII
ports, 8 Fieldbus Memory Management Units (FMMU), 8 Sync Manager, 64 bit
distributed clocks
Universal Serial Bus, USB 2.0 host, Full-Speed OTG, with integrated PHY
Controller Area Network interface (MultiCAN), Full-CAN/Basic-CAN with 2 nodes, 64
message objects (MO), data rate up to 1 MBaud
Four Universal Serial Interface Channels (USIC),providing 4 serial channels, usable
as UART, double-SPI, quad-SPI, IIC, IIS and LIN interfaces
LED and Touch-Sense Controller (LEDTS) for Human-Machine interface
SD and Multi-Media Card interface (SDMMC) for data storage memory cards
Analog Frontend Peripherals
Two Analog-Digital Converters (VADC) of 12-bit resolution, 8 channels each, with
input out-of-range comparators
Digital-Analog Converter (DAC) with two channels of 12-bit resolution
Industrial Control Peripherals
One Capture/Compare Units 8 (CCU8) for motor control and power conversion
Two Capture/Compare Units 4 (CCU4) for use as general purpose timers
Window Watchdog Timer (WDT) for safety sensitive applications
Die Temperature Sensor (DTS)
Real Time Clock module with alarm support
System Control Unit (SCU) for system configuration and control
Input/Output Lines
Programmable port driver control module (PORTS)
Individual bit addressability
Tri-stated in input mode
Push/pull or open drain output mode
Boundary scan test support over JTAG interface
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XMC4300
XMC4000 Family
Summary of Features
Data Sheet 10 V1.1, 2018-09
On-Chip Debug Support
Full support for debug features: 8 breakpoints, CoreSight, trace
Various interfaces: ARM-JTAG, SWD, single wire trace
1.1 Ordering Information
The ordering code for an Infineon microcontroller provides an exact reference to a
specific product. The code “XMC4<DDD>-<Z><PPP><T><FFFF>” identifies:
<DDD> the derivatives function set
<Z> the package variant
–E: LFBGA
–F: LQFP
–Q: VQFN
<PPP> package pin count
<T> the temperature range:
F: -40°C to 85°C
K: -40°C to 125°C
<FFFF> the Flash memory size.
For ordering codes for the XMC4300 please contact your sales representative or local
distributor.
This document describes several derivatives of the XMC4300 series, some descriptions
may not apply to a specific product. Please see Table 1.
For simplicity the term XMC4300 is used for all derivatives throughout this document.
1.2 Device Types
These device types are available and can be ordered through Infineon’s direct and/or
distribution channels.
1.3 Device Type Features
The following table lists the available features per device type.
Table 1 Synopsis of XMC4300 Device Types
Derivative1)
1) x is a placeholder for the supported temperature range.
Package Flash
Kbytes SRAM
Kbytes
XMC4300-F100x256 PG-LQFP-100 256 128
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XMC4300
XMC4000 Family
Summary of Features
Data Sheet 11 V1.1, 2018-09
1.4 Definition of Feature Variants
The XMC4300 types are offered with several memory sizes and number of available
VADC channels. Table 4 describes the location of the available Flash memory, Table 5
describes the location of the available SRAMs, Table 6 the available VADC channels.
Table 2 Features of XMC4300 Device Types
Derivative1)
1) x is a placeholder for the supported temperature range.
LED
TS
Intf.
SD
MMC
Intf.
ETH
Intf. ECAT
Slave
Intf.
USB
Intf. USIC
Chan. MultiCAN
Nodes, MO
XMC4300-F100x256 1 1 RMII 2 x MII 1 2 x 2 N0, N1
MO[0..63]
Table 3 Features of XMC4300 Device Types
Derivative1)
1) x is a placeholder for the supported temperature range.
ADC Chan. DAC Chan. CCU4 Slice CCU8 Slice
XMC4300-F100x256 16 2 2 x 4 1 x 4
Table 4 Flash Memory Ranges
Total Flash Size Cached Range Uncached Range
256 Kbytes 0800 0000H
0803 FFFFH
0C00 0000H
0C03 FFFFH
Table 5 SRAM Memory Ranges
Total SRAM Size Program SRAM System Data SRAM
128 Kbytes 1FFF 0000H
1FFF FFFFH
2000 0000H
2000 FFFFH
Table 6 ADC Channels1)
1) Some pins in a package may be connected to more than one channel. For the detailed mapping see the Port
I/O Function table.
Package VADC G0 VADC G1
PG-LQFP-100 CH0..CH7 CH0..CH7
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XMC4300
XMC4000 Family
Summary of Features
Data Sheet 12 V1.1, 2018-09
1.5 Identification Registers
The identification registers allow software to identify the marking.
Table 7 XMC4300 Identification Registers
Register Name Value Marking
SCU_IDCHIP 0004 3001HAA
JTAG IDCODE 101D F083HAA
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XMC4300
XMC4000 Family
General Device Information
Data Sheet 13 V1.1, 2018-09
2 General Device Information
This section summarizes the logic symbols and package pin configurations with a
detailed list of the functional I/O mapping.
2.1 Logic Symbols
Figure 2 XMC4300 Logic Symbol PG-LQFP-100
Port 0
13 bit
Port 1
16 bit
Port 2
13 bit
Port 3
7 bit
Port 4
2 bit
Port 5
4 bit
VAGND
(1)
VAREF
(1)
VDDP
(4)
JTAG
3 bit
TCK SWD
1 bit
VDDC
(4)
XTAL1
XTAL2
USB_DP
USB_DM
VBUS
Port 14
14 bit
Port 15
4 bit
TMS
PORST
via Port Pins
VDDA
(1)
RTC_XTAL1
RTC_XTAL2
HIB_IO_0
HIB_IO_1
VSSA
(1)
VBAT (1)
(1) VSSO
Exp. Die Pad
(VSS)
VSS
(1)
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XMC4300
XMC4000 Family
General Device Information
Data Sheet 14 V1.1, 2018-09
2.2 Pin Configuration and Definition
The following figures summarize all pins, showing their locations on the four sides of the
different packages.
Figure 3 XMC4300 PG-LQFP-100 Pin Configuration (top view)
2P0.0
1P0.1
100 P0.2
99 P0.3
98 P0.4
97 P0.5
96 P0.6
89 P0.7
88 P0.8
4P0.9
3P0.10
95 P0.11
94 P0.12
79 P1.0
78 P1.1
77 P1.2
76 P1.3
75 P1.4
74 P1.5
83 P1.6
82 P1.7
81 P1.8
80 P1.9
73 P1.10
72 P1.11
71 P1.12
70 P1.13
69 P1.14
68 P1.15
52 P2.0
51 P2.1
50P2.2
49P2.3
48P2.4
47P2.5
54 P2.6
53 P2.7
46P2.8
45P2.9
44P2.10
41P2.14
40P2.15
7P3.0
6P3.1
5P3.2
93 P3.3
92 P3.4
91 P3.5
90 P3.6
85 P4.0
84 P4.1
58 P5.0
57 P5.1
56 P5.2
55 P5.7
31P14.0
30P14.1
29P14.2
28P14.3
27P14.4
26P14.5
25P14.6
24P14.7
37P14.8
36P14.9
23P14.12
22P14.13
21P14.14
20P14.15
19P15.2
18P15.3
39P15.8
38P15.9
14HIB_IO_0
13HIB_IO_1
65 PORST
15RTC_XTAL2
16RTC_XTAL1
67 TCK
66 TMS
8USB_DM
9USB_DP
32VAGND
33VAREF
17VBAT
10VBUS
35VDDA
12VDDC
42VDDC
64 VDDC
86 VDDC
11VDDP
43VDDP
60 VDDP
87 VDDP
59 VSS
34VSSA
63 VSSO
61 XTAL1
62 XTAL2
XMC4300
(Top View)
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XMC4300
XMC4000 Family
General Device Information
Data Sheet 15 V1.1, 2018-09
2.2.1 Package Pin Summary
The following general scheme is used to describe each pin:
The table is sorted by the “Function” column, starting with the regular Port pins (Px.y),
followed by the dedicated pins (i.e. PORST) and supply pins.
The following columns, titled with the supported package variants, lists the package pin
number to which the respective function is mapped in that package.
The “Pad Type” indicates the employed pad type (A1, A1+, A2, special=special pad,
In=input pad, AN/DIG_IN=analog and digital input, Power=power supply). Details about
the pad properties are defined in the Electrical Parameters.
In the “Notes”, special information to the respective pin/function is given, i.e. deviations
from the default configuration after reset. Per default the regular Port pins are configured
as direct input with no internal pull device active.
Table 8 Package Pin Mapping Description
Function Package A Package B ... Pad
Type Notes
Name N Ax ... A2
Table 9 Package Pin Mapping
Function LQFP-100 Pad Type Notes
P0.0 2 A1+
P0.1 1 A1+
P0.2 100 A2
P0.3 99 A2
P0.4 98 A2
P0.5 97 A2
P0.6 96 A2
P0.7 89 A2 After a system reset, via HWSEL
this pin selects the DB.TDI function.
P0.8 88 A2 After a system reset, via HWSEL
this pin selects the DB.TRST
function, with a weak pull-down
active.
P0.9 4 A2
P0.10 3 A1+
P0.11 95 A1+
P0.12 94 A1+
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XMC4300
XMC4000 Family
General Device Information
Data Sheet 16 V1.1, 2018-09
P1.0 79 A1+
P1.1 78 A1+
P1.2 77 A2
P1.3 76 A2
P1.4 75 A1+
P1.5 74 A1+
P1.6 83 A2
P1.7 82 A2
P1.8 81 A2
P1.9 80 A2
P1.10 73 A1+
P1.11 72 A1+
P1.12 71 A2
P1.13 70 A2
P1.14 69 A2
P1.15 68 A2
P2.0 52 A2
P2.1 51 A2 After a system reset, via HWSEL
this pin selects the DB.TDO
function.
P2.2 50 A2
P2.3 49 A2
P2.4 48 A2
P2.5 47 A2
P2.6 54 A1+
P2.7 53 A1+
P2.8 46 A2
P2.9 45 A2
P2.10 44 A2
P2.14 41 A2
P2.15 40 A2
P3.0 7 A2
P3.1 6 A2
Table 9 Package Pin Mapping (cont’d)
Function LQFP-100 Pad Type Notes
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XMC4300
XMC4000 Family
General Device Information
Data Sheet 17 V1.1, 2018-09
P3.2 5 A2
P3.3 93 A1+
P3.4 92 A1+
P3.5 91 A2
P3.6 90 A2
P4.0 85 A2
P4.1 84 A2
P5.0 58 A1+
P5.1 57 A1+
P5.2 56 A1+
P5.7 55 A1+
P14.0 31 AN/DIG_IN
P14.1 30 AN/DIG_IN
P14.2 29 AN/DIG_IN
P14.3 28 AN/DIG_IN
P14.4 27 AN/DIG_IN
P14.5 26 AN/DIG_IN
P14.6 25 AN/DIG_IN
P14.7 24 AN/DIG_IN
P14.8 37 AN/DAC/DIG_IN
P14.9 36 AN/DAC/DIG_IN
P14.12 23 AN/DIG_IN
P14.13 22 AN/DIG_IN
P14.14 21 AN/DIG_IN
P14.15 20 AN/DIG_IN
P15.2 19 AN/DIG_IN
P15.3 18 AN/DIG_IN
P15.8 39 AN/DIG_IN
P15.9 38 AN/DIG_IN
Table 9 Package Pin Mapping (cont’d)
Function LQFP-100 Pad Type Notes
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XMC4300
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General Device Information
Data Sheet 18 V1.1, 2018-09
HIB_IO_0 14 A1 special At the first power-up and with every
reset of the hibernate domain this
pin is configured as open-drain
output and drives "0".
As output the medium driver mode
is active.
HIB_IO_1 13 A1 special At the first power-up and with every
reset of the hibernate domain this
pin is configured as input with no
pull device active.
As output the medium driver mode
is active.
USB_DP 9 special
USB_DM 8 special
TCK 67 A1 Weak pull-down active.
TMS 66 A1+ Weak pull-up active.
As output the strong-soft driver
mode is active.
PORST 65 special Weak pull-up permanently active,
strong pull-down controlled by EVR.
XTAL1 61 clock_IN
XTAL2 62 clock_O
RTC_XTAL1 16 clock_IN
RTC_XTAL2 15 clock_O
VBAT 17 Power When VDDP is supplied VBAT has
to be supplied as well.
VBUS 10 special
VAREF 33 AN_Ref
VAGND 32 AN_Ref
VDDA 35 AN_Power
VSSA 34 AN_Power
VDDC 12 Power
VDDC 42 Power
VDDC 64 Power
VDDC 86 Power
VDDP 11 Power
Table 9 Package Pin Mapping (cont’d)
Function LQFP-100 Pad Type Notes
Subject to Agreement on the Use of Product Information
Inhneon”
XMC4300
XMC4000 Family
General Device Information
Data Sheet 19 V1.1, 2018-09
VDDP 43 Power
VDDP 60 Power
VDDP 87 Power
VSS 59 Power
VSSO 63 Power
VSS Exp. Pad Power Exposed Die Pad
The exposed die pad is connected
internally to VSS. For proper
operation, it is mandatory to connect
the exposed pad directly to the
common ground on the board.
For thermal aspects, please refer to
the Data Sheet. Board layout
examples are given in an
application note.
Table 9 Package Pin Mapping (cont’d)
Function LQFP-100 Pad Type Notes
Subject to Agreement on the Use of Product Information
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XMC4300
XMC4000 Family
General Device Information
Data Sheet 20 V1.1, 2018-09
2.2.2 Port I/O Functions
The following general scheme is used to describe each Port pin:
Figure 4 Simplified Port Structure
Pn.y is the port pin name, defining the control and data bits/registers associated with it.
As GPIO, the port is under software control. Its input value is read via Pn_IN.y, Pn_OUT
defines the output value.
Up to four alternate output functions (ALT1/2/3/4) can be mapped to a single port pin,
selected by Pn_IOCR.PC. The output value is directly driven by the respective module,
with the pin characteristics controlled by the port registers (within the limits of the
connected pad).
The port pin input can be connected to multiple peripherals. Most peripherals have an
input multiplexer to select between different possible input sources.
The input path is also active while the pin is configured as output. This allows to feedback
an output to on-chip resources without wasting an additional external pin.
By Pn_HWSEL it is possible to select between different hardware “masters”
(HWO0/HWI0). The selected peripheral can take control of the pin(s). Hardware control
overrules settings in the respective port pin registers.
Table 10 Port I/O Function Description
Function Outputs Inputs
ALT1 ALTn HWO0 HWI0 Input Input
P0.0 MODA.OUT MODB.OUT MODB.INA MODC.INA
Pn.y MODA.OUT MODA.INA MODC.INB
XMC4000
Pn.y
VDDP
GND
Pn.y
ALT1
...
ALTn
HWO0
HWO1
SW
Control Logic
Input 0
Input n
... PAD
HWI0
HWI1
MODB.OUT
MODB
MODA
MODA.INA
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Data Sheet 25 V1.1, 2018-09
2.3 Power Connection Scheme
Figure 5. shows a reference power connection scheme for the XMC4300.
Figure 5 Power Connection Scheme
Every power supply pin needs to be connected. Different pins of the same supply need
also to be externally connected. As example, all VDDP pins must be connected externally
to one VDDP net. In this reference scheme one 100 nF capacitor is connected at each
supply pin against VSS. An additional 10 µF capacitor is connected to the VDDP nets and
an additional 10 uF capacitor to the VDDC nets.
VBAT
M x VDDC
N x VDDP
VSS
VDDA
VAREF
VAGND
Hibernate domain
RTC Hibernate
control
Retention
Memory
32 kHz
Clock
Core Domain
CPU
Dig.
Peripherals
Analog Domain
ADC DAC
GPIOs
Out-of-range comparator
PAD Domain
Level
shift.
FLASH
RAMs
100 nF x M
10 µF x 1
100 nF
Reference
100 nF
3.3V
XMC4000
EVR
VSSA
Exp. Die Pad
VSS
GND
GND
GND
GND
AGND
100 nF x N
10 µF x 1
3.3V
2.1...3.6 V
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XMC4000 Family
Data Sheet 26 V1.1, 2018-09
The XMC4300 has a common ground concept, all VSS, VSSA and VSSO pins share the
same ground potential. In packages with an exposed die pad it must be connected to the
common ground as well.
VAGND is the low potential to the analog reference VAREF. Depending on the application it
can share the common ground or have a different potential. In devices with shared
VDDA/VAREF and VSSA/VAGND pins the reference is tied to the supply. Some analog
channels can optionally serve as “Alternate Reference”; further details on this operating
mode are described in the Reference Manual.
When VDDP is supplied, VBAT must be supplied as well. If no other supply source (e.g.
battery) is connected to VBAT, the VBAT pin can also be connected directly to VDDP.
Subject to Agreement on the Use of Product Information
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Electrical Parameters
Data Sheet 27 V1.1, 2018-09
3 Electrical Parameters
Attention: All parameters in this chapter are preliminary target values and may
change based on characterization results.
3.1 General Parameters
3.1.1 Parameter Interpretation
The parameters listed in this section partly represent the characteristics of the XMC4300
and partly its requirements on the system. To aid interpreting the parameters easily
when evaluating them for a design, they are marked with a two-letter abbreviation in
column “Symbol”:
CC
Such parameters indicate Controller Characteristics, which are a distinctive feature
of the XMC4300 and must be regarded for system design.
SR
Such parameters indicate System Requirements, which must be provided by the
application system in which the XMC4300 is designed in.
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Inhneon”
XMC4300
XMC4000 Family
Electrical Parameters
Data Sheet 28 V1.1, 2018-09
3.1.2 Absolute Maximum Ratings
Stresses above the values listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Figure 6 explains the input voltage ranges of VIN and VAIN and its dependency to the
supply level of VDDP.The input voltage must not exceed 4.3 V, and it must not be more
than 1.0 V above VDDP. For the range up to VDDP + 1.0 V also see the definition of the
overload conditions in Section 3.1.3.
Table 12 Absolute Maximum Rating Parameters
Parameter Symbol Values Unit Note /
Test Con
dition
Min. Typ. Max.
Storage temperature TST SR -65 150 °C–
Junction temperature TJ SR -40 150 °C –
Voltage at 3.3 V power supply
pins with respect to VSS
VDDP SR – 4.3 V
Voltage on any Class A and
dedicated input pin with
respect to VSS
VIN SR -1.0 VDDP + 1.0
or max. 4.3 V whichever
is lower
Voltage on any analog input
pin with respect to VAGND
VAIN
VAREF SR -1.0 – VDDP + 1.0
or max. 4.3 V whichever
is lower
Input current on any pin
during overload condition
IIN SR -10 +10 mA
Absolute maximum sum of all
input circuit currents for one
port group during overload
condition1)
1) The port groups are defined in Table 16.
ΣIIN SR -25 +25 mA
Absolute maximum sum of all
input circuit currents during
overload condition
ΣIIN SR -100 – +100 mA
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XMC4000 Family
Electrical Parameters
Data Sheet 29 V1.1, 2018-09
Figure 6 Absolute Maximum Input Voltage Ranges
3.1.3 Pin Reliability in Overload
When receiving signals from higher voltage devices, low-voltage devices experience
overload currents and voltages that go beyond their own IO power supplies specification.
Table 13 defines overload conditions that will not cause any negative reliability impact if
all the following conditions are met:
full operation life-time is not exceeded
Operating Conditions are met for
pad supply levels (VDDP or VDDA)
– temperature
If a pin current is outside of the Operating Conditions but within the overload
conditions, then the parameters of this pin as stated in the Operating Conditions can no
longer be guaranteed. Operation is still possible in most cases but with relaxed
parameters.
Note: An overload condition on one or more pins does not require a reset.
Note: A series resistor at the pin to limit the current to the maximum permitted overload
current is sufficient to handle failure situations like short to battery.
V
4.3
V
SS
-1.0
A
A
B
Abs. max. input voltage V
IN
with V
DDP
> 3.3 V
Abs. max. input voltage V
IN
with V
DDP
3.3 V
V
V
DDP
+ 1.0
V
SS
-1.0
V
DDP
B
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XMC4300
XMC4000 Family
Electrical Parameters
Data Sheet 30 V1.1, 2018-09
Figure 7 shows the path of the input currents during overload via the ESD protection
structures. The diodes against VDDP and ground are a simplified representation of these
ESD protection structures.
Figure 7 Input Overload Current via ESD structures
Table 14 and Table 15 list input voltages that can be reached under overload conditions.
Note that the absolute maximum input voltages as defined in the Absolute Maximum
Ratings must not be exceeded during overload.
Table 13 Overload Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Input current on any port pin
during overload condition
IOV SR -5 5 mA
Absolute sum of all input
circuit currents for one port
group during overload
condition1)
1) The port groups are defined in Table 16.
IOVG SR – 20 mA Σ|IOVx|, for all
IOVx <0mA
––20mAΣ|IOVx|, for all
IOVx >0mA
Absolute sum of all input
circuit currents during
overload condition
IOVS SR – 80 mA ΣIOVG
Pn.y IOVx
GND
ESD Pad
GND
VDDP
VDDP
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XMC4300
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Electrical Parameters
Data Sheet 31 V1.1, 2018-09
Table 14 PN-Junction Characterisitics for positive Overload
Pad Type IOV =5mA, TJ=-4C IOV =5mA, TJ=15C
A1 / A1+ VIN =VDDP +1.0V VIN =VDDP +0.75V
A2 VIN =VDDP +0.7V VIN =VDDP +0.6V
AN/DIG_IN VIN =VDDP +1.0V VIN =VDDP +0.75V
Table 15 PN-Junction Characterisitics for negative Overload
Pad Type IOV =5mA, TJ=-4C IOV =5mA, TJ=15C
A1 / A1+ VIN =VSS -1.0V VIN =VSS -0.75V
A2 VIN =VSS -0.7V VIN =VSS -0.6V
AN/DIG_IN VIN =VDDP -1.0V VIN =VDDP -0.75V
Table 16 Port Groups for Overload and Short-Circuit Current Sum
Parameters
Group Pins
1 P0.[12:0], P3.[6:0]
2 P14.[15:0], P15.[9:2]
3 P2.[15:0], P5.[7:0]
4 P1.[15:0], P4.[1:0]
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Inhneon” OOO
XMC4300
XMC4000 Family
Electrical Parameters
Data Sheet 32 V1.1, 2018-09
3.1.4 Pad Driver and Pad Classes Summary
This section gives an overview on the different pad driver classes and their basic
characteristics.
Figure 8 Output Slopes with different Pad Driver Modes
Figure 8 is a qualitative display of the resulting output slope performance with different
output driver modes. The detailed input and output characteristics are listed in
Section 3.2.1.
Table 17 Pad Driver and Pad Classes Overview
Class Power
Supply Type Sub-Class Speed
Grade Load Termination
A3.3 V LVTTL
I/O A1
(e.g. GPIO) 6 MHz 100 pF No
A1+
(e.g. serial I/Os) 25 MHz 50 pF Series termination
recommended
A2
(e.g. ext. Bus) 80 MHz 15 pF Series termination
recommended
V
VDDP
VSS
VOH
VOL
t
A
B
C
DEF
A
B
C
D
E
F
Output High Voltage
Output Low Voltage
Weak drive strength
Medium drive strength
Strong – slow drive strength
Strong – soft drive strength
Strong – medium drive strength
Strong – sharp drive strength
AB
CEFClass A2 Pads
CD
EFClass A1+ Pads
EFClass A1 Pads
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XMC4300
XMC4000 Family
Electrical Parameters
Data Sheet 33 V1.1, 2018-09
3.1.5 Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct
operation and reliability of the XMC4300. All parameters specified in the following
sections refer to these operating conditions, unless noted otherwise.
Table 18 Operating Conditions Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Ambient Temperature TA SR -40 85 °C Temp. Range F
-40 125 °C Temp. Range K
Digital supply voltage VDDP SR 3.131)
1) See also the Supply Monitoring thresholds, Section 3.3.2.
3.3 3.63 2)
2) Voltage overshoot to 4.0 V is permissible at Power-Up and PORST low, provided the pulse duration is less
than 100 μs and the cumulated sum of the pulses does not exceed 1 h over lifetime.
V
Core Supply Voltage VDDC
CC
1) 1.3 V Generated
internally
Digital ground voltage VSS SR 0 −−V
ADC analog supply
voltage
VDDA SR 3.0 3.3 3.62) V
Analog ground voltage for
VDDA
VSSA SR -0.1 0 0.1 V
Battery Supply Voltage for
Hibernate Domain
VBAT SR 1.953)
3) To start the hibernate domain it is required that VBAT 2.1 V, for a reliable start of the oscillation of RTC_XTAL
in crystal mode it is required that VBAT 3.0 V.
3.63 V When VDDP is
supplied VBAT
has to be
supplied as
well.
System Frequency fSYS SR −−144 MHz
Short circuit current of
digital outputs
ISC SR -5 5mA
Absolute sum of short
circuit currents per pin
group4)
4) The port groups are defined in Table 16.
ΣISC_PG
SR
−−20 mA
Absolute sum of short
circuit currents of the
device
ΣISC_D
SR
−−100 mA
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Inhneon”
XMC4300
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Electrical Parameters
Data Sheet 34 V1.1, 2018-09
3.2 DC Parameters
3.2.1 Input/Output Pins
The digital input stage of the shared analog/digital input pins is identical to the input
stage of the standard digital input/output pins.
The Pull-up on the PORST pin is identical to the Pull-up on the standard digital
input/output pins.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 19 Standard Pad Parameters
Parameter Symbol Values Unit Note / Test Condition
Min. Max.
Pin capacitance (digital
inputs/outputs)
CIO CC 10 pF
Pull-down current |IPDL|
SR 150 −μA1)VIN 0.6 × VDDP
1) Current required to override the pull device with the opposite logic level (“force current”).
With active pull device, at load currents between force and keep current the input state is undefined.
10 μA2)VIN 0.36 × VDDP
2) Load current at which the pull device still maintains the valid logic level (“keep current”).
With active pull device, at load currents between force and keep current the input state is undefined.
Pull-Up current |IPUH|
SR
10 μA2)VIN 0.6 × VDDP
100 −μA1)VIN 0.36 × VDDP
Input Hysteresis for
pads of all A classes3)
3) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can not
be guaranteed that it suppresses switching due to external system noise.
HYSA
CC 0.1 ×
VDDP
V
PORST spike filter
always blocked pulse
duration
tSF1 CC 10 ns
PORST spike filter
pass-through pulse
duration
tSF2 CC 100 ns
PORST pull-down
current |IPPD|
CC 13 mA VIN =1.0 V
Subject to Agreement on the Use of Product Information
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XMC4300
XMC4000 Family
Electrical Parameters
Data Sheet 35 V1.1, 2018-09
Figure 9 Pull Device Input Characteristics
Figure 9 visualizes the input characteristics with an active internal pull device:
in the cases “A” the internal pull device is overridden by a strong external driver;
in the cases “B” the internal pull device defines the input logical state against a weak
external load.
XMC4000 IN
I
PDL
AI
PDL
150 μA
BI
PDL
10 μA
V
DDP
GND
V
V
DDP
V
SS
0.6 x V
DDP
A
0.36 x V
DDP
B
Valid High
Valid Low
Invalid digital input
XMC4000
IN
I
PUH
AI
PUH
100 μA
BI
PUH
10 μA
V
V
DDP
V
SS
0.6 x V
DDP
B
0.36 x V
DDP
A
Valid High
Valid Low
Invalid digital input
Pull-down active
Pull-up active
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XMC4300
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Electrical Parameters
Data Sheet 36 V1.1, 2018-09
Table 20 Standard Pads Class_A1
Parameter Symbol Values Unit Note /
Test Condition
Min. Max.
Input leakage current IOZA1 CC -500 500 nA 0 V VIN VDDP
Input high voltage VIHA1 SR 0.6 × VDDP VDDP + 0.3 V max. 3.6 V
Input low voltage VILA1 SR -0.3 0.36 × VDDP V
Output high voltage,
POD1) = weak
VOHA1
CC
VDDP - 0.4 VIOH -400 μA
2.4 VIOH -500 μA
Output high voltage,
POD1) = medium
VDDP - 0.4 VIOH -1.4 mA
2.4 VIOH -2 mA
Output low voltage VOLA1
CC
0.4 V IOL 500 μA;
POD1) = weak
0.4 V IOL 2mA;
POD1) = medium
Fall time tFA1 CC 150 ns CL=20pF;
POD1) = weak
1) POD = Pin Out Driver
50 ns CL=50pF;
POD1) = medium
Rise time tRA1 CC 150 ns CL=20pF;
POD1) = weak
50 ns CL=50pF;
POD1) = medium
Table 21 Standard Pads Class_A1+
Parameter Symbol Values Unit Note /
Test Condition
Min. Max.
Input leakage current IOZA1+ CC -1 1 μA0VVIN VDDP
Input high voltage VIHA1+ SR 0.6 × VDDP VDDP + 0.3 V max. 3.6 V
Input low voltage VILA1+ SR -0.3 0.36 × VDDP V
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XMC4300
XMC4000 Family
Electrical Parameters
Data Sheet 37 V1.1, 2018-09
Output high voltage,
POD1) = weak
VOHA1+
CC
VDDP - 0.4 VIOH -400 μA
2.4 VIOH -500 μA
Output high voltage,
POD1) = medium
VDDP - 0.4 VIOH -1.4 mA
2.4 VIOH -2 mA
Output high voltage,
POD1) = strong
VDDP - 0.4 VIOH -1.4 mA
2.4 VIOH -2 mA
Output low voltage VOLA1+
CC
0.4 V IOL 500 μA;
POD1) = weak
0.4 V IOL 2mA;
POD1) = medium
0.4 V IOL 2mA;
POD1) = strong
Fall time tFA1+ CC 150 ns CL=20pF;
POD1) = weak
50 ns CL=50pF;
POD1) = medium
28 ns CL=50pF;
POD1) = strong;
edge = slow
16 ns CL=50pF;
POD1) = strong;
edge = soft;
Rise time tRA1+ CC 150 ns CL=20pF;
POD1) = weak
50 ns CL=50pF;
POD1) = medium
28 ns CL=50pF;
POD1) = strong;
edge = slow
16 ns CL=50pF;
POD1) = strong;
edge = soft
1) POD = Pin Out Driver
Table 21 Standard Pads Class_A1+
Parameter Symbol Values Unit Note /
Test Condition
Min. Max.
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XMC4300
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Electrical Parameters
Data Sheet 38 V1.1, 2018-09
Table 22 Standard Pads Class_A2
Parameter Symbol Values Unit Note /
Test Condition
Min. Max.
Input Leakage current IOZA2
CC -6 6 μA0VVIN <
0.5*VDDP -1V;
0.5*VDDP +1V
<VIN VDDP
-3 3 μA0.5*VDDP -1V <
VIN <0.5*VDDP
+1V
Input high voltage VIHA2
SR 0.6 × VDDP VDDP + 0.3 V max. 3.6 V
Input low voltage VILA2 SR -0.3 0.36 ×
VDDP
V
Output high voltage,
POD = weak
VOHA2
CC
VDDP - 0.4 VIOH -400 μA
2.4 VIOH -500 μA
Output high voltage,
POD = medium
VDDP - 0.4 VIOH -1.4 mA
2.4 VIOH -2 mA
Output high voltage,
POD = strong
VDDP - 0.4 VIOH -1.4 mA
2.4 VIOH -2 mA
Output low voltage,
POD = weak
VOLA2
CC
0.4 V IOL 500 μA
Output low voltage,
POD = medium
0.4 V IOL 2mA
Output low voltage,
POD = strong
0.4 V IOL 2mA
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Inhneon”
XMC4300
XMC4000 Family
Electrical Parameters
Data Sheet 39 V1.1, 2018-09
Fall time tFA2 CC 150 ns CL=20pF;
POD = weak
50 ns CL=50pF;
POD = medium
3.7 ns CL=50pF;
POD = strong;
edge = sharp
7ns
CL=50pF;
POD = strong;
edge = medium
16 ns CL=50pF;
POD = strong;
edge = soft
Rise time tRA2 CC 150 ns CL=20pF;
POD = weak
50 ns CL=50pF;
POD = medium
3.7 ns CL=50pF;
POD = strong;
edge = sharp
7.0 ns CL=50pF;
POD = strong;
edge = medium
16 ns CL=50pF;
POD = strong;
edge = soft
Table 22 Standard Pads Class_A2
Parameter Symbol Values Unit Note /
Test Condition
Min. Max.
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Inhneon”
XMC4300
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Electrical Parameters
Data Sheet 40 V1.1, 2018-09
Table 23 HIB_IO Class_A1 special Pads
Parameter Symbol Values Unit Note /
Test Condition
Min. Max.
Input leakage current IOZHIB
CC -500 500 nA 0 V VIN VBAT
Input high voltage VIHHIB
SR 0.6 × VBAT VBAT + 0.3 V max. 3.6 V
Input low voltage VILHIB
SR -0.3 0.36 × VBAT V
Input Hysteresis for
HIB_IO pins1)
1) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can not
be guaranteed that it suppresses switching due to external system noise.
HYSHIB
CC 0.1 × VBAT VVBAT 3.13 V
0.06 ×
VBAT
VVBAT <3.13 V
Output high voltage,
POD1) = medium
VOHHIB
CC
VBAT - 0.4 VIOH -1.4 mA
Output low voltage VOLHIB
CC
0.4 V IOL 2mA
Fall time tFHIB CC 50 ns VBAT 3.13 V
CL=50pF
100 ns VBAT <3.13 V
CL=50pF
Rise time tRHIB CC 50 ns VBAT 3.13 V
CL=50pF
100 ns VBAT <3.13 V
CL=50pF
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XMC4300
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Electrical Parameters
Data Sheet 41 V1.1, 2018-09
3.2.2 Analog to Digital Converters (VADC)
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 24 VADC Parameters (Operating Conditions apply)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Analog reference voltage5) VAREF
SR
VAGND
+ 1
VDDA +
0.051) V
Analog reference ground5) VAGND
SR
VSSM -
0.05
VAREF -
1V
Analog reference voltage
range2)5) VAREF -
VAGND
SR
1VDDA +
0.1 V
Analog input voltage VAIN SR VAGND VDDA V
Input leakage at analog
inputs3) IOZ1 CC -100 200 nA 0.03 × VDDA <
VAIN <0.97 × VDDA
-500 100 nA 0 V VAIN 0.03
× VDDA
-100 500 nA 0.97 × VDDA
VAIN VDDA
Input leakage current at
VAREF
IOZ2 CC -1 1μA0V VAREF
VDDA
Input leakage current at
VAGND
IOZ3 CC -1 1μA0VVAGND
VDDA
Internal ADC clock fADCI CC 2 36 MHz VDDA = 3.3 V
Switched capacitance at
the analog voltage inputs4) CAINSW
CC
46.5 pF
Total capacitance of an
analog input
CAINTOT
CC
12 20 pF
Switched capacitance at
the positive reference
voltage input5)6)
CAREFSW
CC
15 30 pF
Total capacitance of the
voltage reference inputs5) CAREFTOT
CC
20 40 pF
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Electrical Parameters
Data Sheet 42 V1.1, 2018-09
Total Unadjusted Error TUE CC -4 4 LSB 12-bit resolution;
VDDA = 3.3 V;
VAREF = VDDA7)
Differential Non-Linearity
Error8) EADNL
CC -3 3LSB
Gain Error8) EAGAIN
CC -4 4LSB
Integral Non-Linearity8) EAINLCC -3 3LSB
Offset Error8) EAOFF
CC -4 4LSB
RMS Noise9) ENRMS
CC
12
10)11) LSB
Worst case ADC VDDA
power supply current per
active converter
IDDAA
CC
1.5 2 mA during conversion
VDDP =3.6V,
TJ= 150 oC
Charge consumption on
VAREF per conversion5) QCONV
CC
30 pC 0 V VAREF
VDDA12)
ON resistance of the
analog input path
RAIN CC 600 1 200 Ohm
ON resistance for the ADC
test (pull down for AIN7)
RAIN7T
CC 180 550 900 Ohm
Resistance of the
reference voltage input
path
RAREF
CC
700 1 700 Ohm
1) A running conversion may become imprecise in case the normal conditions are violated (voltage overshoot).
2) If the analog reference voltage is below VDDA, then the ADC converter errors increase. If the reference voltage
is reduced by the factor k (k<1), TUE, DNL, INL, Gain, and Offset errors increase also by the factor 1/k.
3) The leakage current definition is a continuous function, as shown in figure ADCx Analog Inputs Leakage. The
numerical values defined determine the characteristic points of the given continuous linear approximation -
they do not define step function (see Figure 12).
4) The sampling capacity of the conversion C-network is pre-charged to VAREF/2 before the sampling moment.
Because of the parasitic elements, the voltage measured at AINx can deviate from VAREF/2.
5) Applies to AINx, when used as alternate reference input.
6) This represents an equivalent switched capacitance. This capacitance is not switched to the reference voltage
at once. Instead, smaller capacitances are successively switched to the reference voltage.
7) For 10-bit conversions, the errors are reduced to 1/4; for 8-bit conversions, the errors are reduced to 1/16.
Never less than ±1 LSB.
8) The sum of DNL/INL/GAIN/OFF errors does not exceed the related total unadjusted error TUE.
Table 24 VADC Parameters (Operating Conditions apply)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
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Data Sheet 43 V1.1, 2018-09
Figure 10 VADC Reference Voltage Range
The power-up calibration of the VADC requires a maximum number of 4 352 fADCI cycles.
9) This parameter is valid for soldered devices and requires careful analog board design.
10) Resulting worst case combined error is arithmetic combination of TUE and ENRMS.
11) Value is defined for one sigma Gauss distribution.
12) The resulting current for a conversion can be calculated with IAREF =QCONV /tc.
The fastest 12-bit post-calibrated conversion of tc= 459 ns results in a typical average current of
IAREF = 65.4 µA.
Minimum VAREF - VAGND is 1 V
V
VDDA + 0.05
VAGND + 1
VAGND
Valid VAREF
VDDA
e.g. VAREF = 4/5 of VDDA
Conversion error
increases by 5/4
Precise conversion range (12 bit)
t
VAREF
VSSA
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Data Sheet 44 V1.1, 2018-09
Figure 11 VADC Input Circuits
Figure 12 VADC Analog Input Leakage Current
Reference Voltage Input Circuitry
Analog Input Circuitry
Analog_InpRefDiag
REXT
=
VAIN CEXT
RAIN, On
CAINTOT - CAINSW
CAINSW
ANx
VAREF
RAREF, On
CAREFTOT - CAREFSW CAREFSW
VAGNDx
VAREFx
RAIN7T
VAGNDx
ADC-Leakage.vsd
V
IN
[% V
DDA
]
200 nA
500 nA
3% 100%97%
I
OZ1
100 nA
-500 nA
-100 nA
Single ADC Input
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Data Sheet 45 V1.1, 2018-09
Conversion Time
STC defines additional clock cycles to extend the sample time
PC adds two cycles if post-calibration is enabled
DM adds one cycle for an extended conversion time of the MSB
Conversion Time Examples
System assumptions:
fADC = 144 MHz i.e. tADC = 6.9 ns, DIVA = 3, fADCI = 36 MHz i.e. tADCI = 27.8 ns
According to the given formulas the following minimum conversion times can be
achieved (STC = 0, DM = 0):
12-bit post-calibrated conversion (PC = 2):
tCN12C = (2 + 12 + 2) × tADCI + 2 × tADC = 16 × 27.8 ns + 2 × 6.9 ns = 459 ns
12-bit uncalibrated conversion:
tCN12 = (2 + 12) × tADCI + 2 × tADC = 14 × 27.8 ns + 2 × 6.9 ns = 403 ns
10-bit uncalibrated conversion:
tCN10 = (2 + 10) × tADCI + 2 × tADC = 12 × 27.8 ns + 2 × 6.9 ns = 348 ns
8-bit uncalibrated:
tCN8 = (2 + 8) × tADCI + 2 × tADC = 10 × 27.8 ns + 2 × 6.9 ns = 292 ns
3.2.3 Digital to Analog Converters (DAC)
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 25 Conversion Time (Operating Conditions apply)
Parameter Symbol Values Unit Note
Conversion
time
tCCC 2 ×TADC +
(2+N+STC+PC+DM)× TADCI
μs N = 8, 10, 12 for
N-bit conversion
TADC =1/fPERIPH
TADCI =1/fADCI
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Data Sheet 46 V1.1, 2018-09
Table 26 DAC Parameters (Operating Conditions apply)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
RMS supply current IDD CC 2.5 4 mA per active DAC
channel,
without load
currents of DAC
outputs
Resolution RES CC 12 Bit
Update rate fURATE_ACC 2 Msam
ple/s data rate, where
DAC can follow
64 LSB code jumps
to ± 1LSB accuracy
Update rate fURATE_F CC 5 Msam
ple/s data rate, where
DAC can follow
64 LSB code jumps
to ± 4 LSB accuracy
Settling time tSETTLE CC 12 μs at full scale jump,
output voltage
reaches target
value ± 20 LSB
Slew rate SR CC 2 5 V/μs
Minimum output
voltage
VOUT_MIN
CC
0.3 V code value
unsigned: 000H;
signed: 800H
Maximum output
voltage
VOUT_MAX
CC
2.5 V code value
unsigned: FFFH;
signed: 7FFH
Integral non-linearity INL CC -5.5 ±2.5 5.5 LSB RL 5kOhm,
CL 50 pF
Differential non-
linearity
DNL CC -2 ±1 2 LSB RL 5kOhm,
CL 50 pF
Offset error EDOFF CC ±20 mV
Gain error EDG_IN CC -6.5 -1.5 3 %
Startup time tSTARTUP CC 15 30 μs time from output
enabling till code
valid ±16 LSB
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Data Sheet 47 V1.1, 2018-09
Conversion Calculation
Unsigned:
DACxDATA = 4095 × (VOUT - VOUT_MIN) / (VOUT_MAX - VOUT_MIN)
Signed:
DACxDATA = 4095 × (VOUT - VOUT_MIN) / (VOUT_MAX - VOUT_MIN) - 2048
3dB Bandwidth of
Output Buffer
fC1 CC 2.5 5 MHz verified by design
Output sourcing
current
IOUT_SOURCE
CC
-30 mA
Output sinking
current
IOUT_SINK
CC
0.6 mA
Output resistance ROUT CC 50 Ohm
Load resistance RL SR 5 −− kOhm
Load capacitance CL SR −−50 pF
Signal-to-Noise
Ratio SNR CC 70 dB examination
bandwidth < 25 kHz
Total Harmonic
Distortion THD CC 70 dB examination
bandwidth < 25 kHz
Power Supply
Rejection Ratio PSRR CC 56 dB to VDDA
verified by design
Table 26 DAC Parameters (Operating Conditions apply) (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
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Data Sheet 48 V1.1, 2018-09
Figure 13 DAC Conversion Examples
DAC output
VOUT_MIN
VOUT_MAX
64 LSBs
+/- 4LSB
fURATE_F (max)
64 LSBs
+/- 1LSB
fURATE_A (max)
DAC output
VOUT_MIN
VOUT_MAX 20 LSBs
tSETTLE
20 LSBs
tSETTLE
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Data Sheet 49 V1.1, 2018-09
3.2.4 Out-of-Range Comparator (ORC)
The Out-of-Range Comparator (ORC) triggers on analog input voltages (VAIN) above the
analog reference1) (VAREF) on selected input pins (GxORCy) and generates a service
request trigger (GxORCOUTy).
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
The parameters in Table 27 apply for the maximum reference voltage
VAREF =VDDA +50mV.
1) Always the standard VADC reference, alternate references do not apply to the ORC.
Table 27 ORC Parameters (Operating Conditions apply)
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
DC Switching Level VODC CC 100 125 210 mV VAIN VAREF + VODC
Hysteresis VOHYS CC 50 VODC mV
Detection Delay of a
persistent
Overvoltage
tODD CC 50 450 ns VAIN VAREF + 210 mV
45 105 ns VAIN VAREF + 400 mV
Always detected
Overvoltage Pulse
tOPDD CC 440 −− ns VAIN VAREF + 210 mV
90 −− ns VAIN VAREF + 400 mV
Never detected
Overvoltage Pulse
tOPDN CC −−45 ns VAIN VAREF + 210 mV
−−30 ns VAIN VAREF + 400 mV
Release Delay tORD CC 65 105 ns VAIN VAREF
Enable Delay tOED CC 100 200 ns
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Data Sheet 50 V1.1, 2018-09
Figure 14 GxORCOUTy Trigger Generation
Figure 15 ORC Detection Ranges
VSS
VAREF
tORD
VODC
VOHYS
tODD
GxORCOUTy
GxORCy
VAIN (V)
VAREF + 400 mV
t
VAREF + 200 mV
Overvoltage
may be
detected
(level uncertain)
Never
detected
Overvoltage
Pulse
(Too short)
T < tOPDN
tOPDN < T < tOPDD
Overvoltage
may be
detected
T > tOPDD
Always detected
Overvoltage Pulse
T < tOPDN
Never
detected
Overvoltage
Pulse
(Too short)
tOPDN < T < tOPDD T > tOPDD
Always detected
Overvoltage Pulse
VAREF + 100 mV
Overvoltage
may be
detected
T > tOPDN
Never
detected
Overvoltage
Pulse
(Too low)
VAREF
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Data Sheet 51 V1.1, 2018-09
3.2.5 Die Temperature Sensor
The Die Temperature Sensor (DTS) measures the junction temperature TJ.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
The following formula calculates the temperature measured by the DTS in [oC] from the
RESULT bit field of the DTSSTAT register.
Temperature TDTS = (RESULT - 605) / 2.05 [°C]
This formula and the values defined in Table 28 apply with the following calibration
values:
DTSCON.BGTRIM = 8H
DTSCON.REFTRIM = 4H
Table 28 Die Temperature Sensor Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Temperature sensor range TSR SR -40 150 °C
Linearity Error
(to the below defined formula)
Δ
TLE CC ±1 °C per
Δ
TJ30 °C
Offset Error
Δ
TOE CC ±6 °C
Δ
TOE = TJ - TDTS
VDDP 3.3 V1)
1) At VDDP_max = 3.63 V the typical offset error increases by an additional
Δ
TOE C.
Measurement time tMCC −−100 μs
Start-up time after reset
inactive
tTSST SR −−10 μs
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Data Sheet 52 V1.1, 2018-09
3.2.6 USB OTG Interface DC Characteristics
The Universal Serial Bus (USB) Interface is compliant to the USB Rev. 2.0 Specification
and the OTG Specification Rev. 1.3. High-Speed Mode is not supported.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 29 USB OTG VBUS and ID Parameters (Operating Conditions apply)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
VBUS input voltage
range
VIN CC 0.0 5.25 V
A-device VBUS valid
threshold
VB1 CC 4.4 −− V
A-device session valid
threshold
VB2 CC 0.8 2.0 V
B-device session valid
threshold
VB3 CC 0.8 4.0 V
B-device session end
threshold
VB4 CC 0.2 0.8 V
VBUS input
resistance to ground
RVBUS_IN
CC 40 100 kOhm
B-device VBUS pull-
up resistor
RVBUS_PU
CC 281 −− Ohm Pull-up voltage =
3.0 V
B-device VBUS pull-
down resistor
RVBUS_PD
CC 656 −− Ohm
USB.ID pull-up
resistor
RUID_PU
CC 14 25 kOhm
VBUS input current IVBUS_IN
CC
−−150 μA0 V VIN 5.25 V:
TAVG = 1 ms
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Data Sheet 53 V1.1, 2018-09
Table 30 USB OTG Data Line (USB_DP, USB_DM) Parameters (Operating
Conditions apply)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Input low voltage VIL SR −−0.8 V
Input high voltage
(driven)
VIH SR 2.0 −− V
Input high voltage
(floating) 1)
1) Measured at A-connector with 1.5 kOhm ± 5% to 3.3 V ± 0.3 V connected to USB_DP or USB_DM and at B-
connector with 15 kOhm ± 5% to ground connected to USB_DP and USB_DM.
VIHZ SR 2.7 3.6 V
Differential input
sensitivity
VDIS CC 0.2 −− V
Differential common
mode range
VCM CC 0.8 2.5 V
Output low voltage VOL CC 0.0 0.3 V 1.5 kOhm pull-
up to 3.6 V
Output high voltage VOH CC 2.8 3.6 V 15 kOhm pull-
down to 0 V
DP pull-up resistor (idle
bus)
RPUI CC 900 1 575 Ohm
DP pull-up resistor
(upstream port
receiving)
RPUA CC 1 425 3 090 Ohm
DP, DM pull-down
resistor
RPD CC 14.25 24.8 kOhm
Input impedance DP,
DM
ZINP CC 300 −− kOhm 0 V VIN VDDP
Driver output resistance
DP, DM
ZDRV CC 28 44 Ohm
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Data Sheet 54 V1.1, 2018-09
3.2.7 Oscillator Pins
Note: It is strongly recommended to measure the oscillation allowance (negative
resistance) in the final target system (layout) to determine the optimal parameters
for the oscillator operation. Please refer to the limits specified by the crystal or
ceramic resonator supplier.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
The oscillator pins can be operated with an external crystal (see Figure 16) or in direct
input mode (see Figure 17).
Figure 16 Oscillator in Crystal Mode
XTAL1
XTAL2
f
OSC
Damping resistor
may be needed for
some crystals
V
PPX
V
PPX_min
V
PPX
V
PPX_max
t
V
V
PPX_min
t
OSCS
GND
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Data Sheet 55 V1.1, 2018-09
Figure 17 Oscillator in Direct Input Mode
V
VIHBX_max
VSS
t
Input High Voltage
Input Low Voltage
Input High Voltage
XTAL1
XTAL2
not connected
External Clock
Source
Direct Input Mode
VIHBX_min
VILBX_max
VILBX_min
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Data Sheet 56 V1.1, 2018-09
Table 31 OSC_XTAL Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Input frequency fOSC SR 4 40 MHz Direct Input Mode
selected
425 MHz External Crystal
Mode selected
Oscillator start-up
time1)2)
1) tOSCS is defined from the moment the oscillator is enabled wih SCU_OSCHPCTRL.MODE until the oscillations
reach an amplitude at XTAL1 of 0.4 * VDDP.
2) The external oscillator circuitry must be optimized by the customer and checked for negative resistance and
amplitude as recommended and specified by crystal suppliers.
tOSCS
CC
−−10 ms
Input voltage at XTAL1 VIX SR -0.5 VDDP +
0.5 V
Input amplitude (peak-
to-peak) at XTAL12)3)
3) If the shaper unit is enabled and not bypassed.
VPPX SR 0.4 ×
VDDP
VDDP +
1.0 V
Input high voltage at
XTAL14)
4) If the shaper unit is bypassed, dedicated DC-thresholds have to be met.
VIHBXSR 1.0 VDDP +
0.5 V
Input low voltage at
XTAL14) VILBX SR -0.5 0.4 V
Input leakage current at
XTAL1
IILX1 CC -100 100 nA Oscillator power
down
0V VIX VDDP
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Data Sheet 57 V1.1, 2018-09
Table 32 RTC_XTAL Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Input frequency fOSC SR 32.768 kHz
Oscillator start-up
time1)2)3)
1) tOSCS is defined from the moment the oscillator is enabled by the user with SCU_OSCULCTRL.MODE until the
oscillations reach an amplitude at RTC_XTAL1 of 400 mV.
2) The external oscillator circuitry must be optimized by the customer and checked for negative resistance and
amplitude as recommended and specified by crystal suppliers.
3) For a reliable start of the oscillation in crystal mode it is required that VBAT 3.0 V. A running oscillation is
maintained across the full VBAT voltage range.
tOSCS
CC
−−5s
Input voltage at
RTC_XTAL1
VIX SR -0.3 VBAT +
0.3 V
Input amplitude (peak-
to-peak) at
RTC_XTAL12)4)
4) If the shaper unit is enabled and not bypassed.
VPPX SR 0.4 −−V
Input high voltage at
RTC_XTAL15)
5) If the shaper unit is bypassed, dedicated DC-thresholds have to be met.
VIHBXSR 0.6 ×
VBAT
VBAT +
0.3 V
Input low voltage at
RTC_XTAL15) VILBX SR -0.3 0.36 ×
VBAT
V
Input Hysteresis for
RTC_XTAL15)6)
6) Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce. It can not
be guaranteed that it suppresses switching due to external system noise.
VHYSX
CC 0.1 ×
VBAT
V3.0V
VBAT <3.6V
0.03 ×
VBAT
VVBAT <3.0V
Input leakage current at
RTC_XTAL1
IILX1 CC -100 100 nA Oscillator power
down
0V VIX VBAT
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Data Sheet 58 V1.1, 2018-09
3.2.8 Power Supply Current
The total power supply current defined below consists of a leakage and a switching
component.
Application relevant values are typically lower than those given in the following tables,
and depend on the customer's system operating conditions (e.g. thermal connection or
used application configurations).
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
If not stated otherwise, the operating conditions for the parameters in the following table
are:
VDDP = 3.3 V, TA = 25 oC
Table 33 Power Supply Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Active supply current1)11)
Peripherals enabled
Frequency:
fCPU / fPERIPH / fCCU in MHz
IDDPA CC 135 mA 144 / 144 / 144
125 144 / 72 / 72
97 72 / 72 / 144
80 24 / 24 / 24
68 1/1/1
Active supply current
Code execution from RAM
Flash in Sleep mode
IDDPA CC 108 mA 144 / 144 / 144
98 144 / 72 / 72
Active supply current2)
Peripherals disabled
Frequency:
fCPU / fPERIPH / fCCU in MHz
IDDPA CC 86 mA 144 / 144 / 144
85 144 / 72 / 72
70 72 / 72 / 144
55 24 / 24 / 24
50 1/1/1
Sleep supply current3)
Peripherals enabled
Frequency:
fCPU / fPERIPH / fCCU in MHz
IDDPS CC 127 mA 144 / 144 / 144
115 144 / 72 / 72
93 72 / 72 / 144
57 24 / 24 / 24
47 1/1/1
fCPU / fPERIPH / fCCU in kHz 48 100 / 100 / 100
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Data Sheet 59 V1.1, 2018-09
Sleep supply current4)
Peripherals disabled
Frequency:
fCPU / fPERIPH / fCCU in MHz
IDDPS CC 77 mA 144 / 144 / 144
76 144 / 72 / 72
65 72 / 72 / 144
53 24 / 24 / 24
46 1/1/1
fCPU / fPERIPH / fCCU in kHz 47 100 / 100 / 100
Deep Sleep supply
current5)
Flash in Sleep mode
Frequency:
fCPU / fPERIPH / fCCU in MHz
IDDPD CC 11 mA 24 / 24 / 24
7.0 4/4/4
6.6 1/1/1
fCPU / fPERIPH / fCCU in kHz 7.6 100 / 100 / 100
6)
Hibernate supply current
RTC on7) IDDPH CC 8.7 −μAVBAT =3.3V
6.5 VBAT =2.4V
5.7 VBAT =2.0V
Hibernate supply current
RTC off8) IDDPH CC 8.0 −μAVBAT =3.3V
6.0 VBAT =2.4V
5.0 VBAT =2.0V
Hibernate off9) IDDPH CC 4.4 −μAVBAT =3.3V
3.5 VBAT =2.4V
3.1 VBAT =2.0V
Worst case active supply
current10) IDDPA CC −−250
11) mA VDDP =3.6V,
TJ=150oC
VDDA power supply current IDDA CC −−−
12) mA
IDDP current at PORST Low IDDP_PORST
CC
510mAVDDP =3.3V,
TJ=25oC
13 55 mA VDDP =3.6V,
TJ=150oC
Power Dissipation PDISS CC −−1.4 W VDDP =3.6V,
TJ=150oC
Table 33 Power Supply Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
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Data Sheet 60 V1.1, 2018-09
Wake-up time from Sleep to
Active mode
tSSA CC 6cycles
Wake-up time from Deep
Sleep to Active mode
−−−ms Defined by the
wake-up of the
Flash module,
see
Section 3.2.9
Wake-up time from
Hibernate mode
−−−ms Wake-up via
power-on reset
event, see
Section 3.3.2
1) CPU executing code from Flash, all peripherals idle.
2) CPU executing code from Flash.
3) CPU in sleep, all peripherals idle, Flash in Active mode.
4) CPU in sleep, Flash in Active mode.
5) CPU in sleep, peripherals disabled, after wake-up code execution from RAM.
6) To wake-up the Flash from its Sleep mode, fCPU 1 MHz is required.
7) OSC_ULP operating with external crystal on RTC_XTAL
8) OSC_ULP off, Hibernate domain operating with OSC_SI clock
9) VBAT supplied, but Hibernate domain not started; for example state after factory assembly
10) Test Power Loop: fSYS = 144 MHz, CPU executing benchmark code from Flash, all CCUs in 100kHz timer
mode, all ADC groups in continuous conversion mode, USICs as SPI in internal loop-back mode, CAN in
500kHz internal loop-back mode, interrupt triggered DMA block transfers to parity protected RAMs and FCE,
DTS measurements and FPU calculations.
The power consumption of each customer application will most probably be lower than this value, but must be
evaluated separately.
11) IDDP decreases typically by approximately 5 mA when fSYS decreases by 10 MHz, at constant TJ
12) Sum of currents of all active converters (ADC and DAC)
Table 33 Power Supply Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
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Data Sheet 61 V1.1, 2018-09
Peripheral Idle Currents
Default test conditions:
fsys and derived clocks at 144 MHz
VDDP =3.3V, Ta=25 °C
all peripherals are held in reset (see the PRSTAT registers in the Reset Control Unit
of the SCU)
the peripheral clocks are disabled (see CGATSTAT registers in the Clock Control
Unit of the SCU
no I/O activity
The given values are a result of differential measurements with asserted and deasserted
peripheral reset as well as disabled and enabled clock of the peripheral under test.
The tested peripheral is left in the state after the peripheral reset is deasserted, no further
initialisation or configuration is done. E.g. no timer is running in the CCUs, no
communication active in the USICs, etc.
Table 34 Peripheral Idle Currents
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
PORTS
FCE
WDT
IPER CC −≤0.3 mA
MultiCAN
ERU
LEDTSCU0
ETH
CCU4x1), CCU8x1)
1) Enabling the fCCU clock for the CCU4x/CCU8x modules adds approximately IPER = 4.8 mA, disregarding which
and how many of those peripherals are enabled.
−≤1.0
DAC (digital)2)
2) The current consumption of the analog components are given in the dedicated Data Sheet sections of the
respective peripheral.
1.3
USICx
SDMMC
3.0
VADC (digital)2) 4.5
DMA0, USB, EtherCAT 6.0
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Data Sheet 62 V1.1, 2018-09
3.2.9 Flash Memory Parameters
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 35 Flash Memory Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Erase Time per 256
Kbyte Sector
tERP CC 55.5s
Erase Time per 64 Kbyte
Sector
tERP CC 1.2 1.4 s
Erase Time per 16 Kbyte
Logical Sector
tERP CC 0.3 0.4 s
Program time per page1) tPRP CC 5.5 11 ms
Erase suspend delay tFL_ErSusp
CC
−−15 ms
Wait time after margin
change
tFL_Margin
Del CC 10 −−μs
Wake-up time tWU CC −−270 μs
Read access time ta CC 22 −−ns For operation
with 1 / fCPU < ta
wait states must
be configured2)
Data Retention Time,
Physical Sector3)4) tRET CC 20 −−years Max. 1000
erase/program
cycles
Data Retention Time,
Logical Sector3)4) tRETL CC 20 −−years Max. 100
erase/program
cycles
Data Retention Time,
User Configuration Block
(UCB)3)4)
tRTU CC 20 −−years Max. 4
erase/program
cycles per UCB
Endurance on 64 Kbyte
Physical Sector PS4
NEPS4
CC 10000 −−cycles Cycling
distributed over
life time5)
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Electrical Parameters
Data Sheet 63 V1.1, 2018-09
1) In case the Program Verify feature detects weak bits, these bits will be programmed once more. The
reprogramming takes an additional time of 5.5 ms.
2) The following formula applies to the wait state configuration: FCON.WSPFLASH × (1 / fCPU) ta.
3) Storage and inactive time included.
4) Values given are valid for an average weighted junction temperature of TJ = 110°C.
5) Only valid with robust EEPROM emulation algorithm, equally cycling the logical sectors. For more details see
the Reference Manual.
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Data Sheet 64 V1.1, 2018-09
3.3 AC Parameters
3.3.1 Testing Waveforms
Figure 18 Rise/Fall Time Parameters
Figure 19 Testing Waveform, Output Delay
Figure 20 Testing Waveform, Output High Impedance
AC_Rise-Fall-Times.vsd
10%
90%
V
SS
V
DDP
t
R
t
F
10%
90%
AC_TestPoints.vsd
V
DDP
/ 2 V
DDP
/ 2
V
DDP
V
SS
Test Points
AC_HighImp.vsd
V
LOAD
+ 0.1V Timing
Reference
Points
V
LOAD
-0.1V
V
OH
-0.1V
V
OL
+ 0.1V
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Electrical Parameters
Data Sheet 65 V1.1, 2018-09
3.3.2 Power-Up and Supply Monitoring
PORST is always asserted when VDDP and/or VDDC violate the respective thresholds.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Figure 21 PORST Circuit
Table 36 Supply Monitoring Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Digital supply voltage reset
threshold
VPOR CC 2.791)
1) Minimum threshold for reset assertion.
3.052) V3)
Core supply voltage reset
threshold
VPV CC −−1.17 V
VDDP voltage to ensure
defined pad states
VDDPPA
CC
1.0 V
PORST rise time tPR SR −−2μs4)
Startup time from power-on
reset with code execution
from Flash
tSSW CC 2.5 3.5 ms Time to the first
user code
instruction
VDDC ramp up time tVCR CC 550 −μs Ramp up after
power-on or
after a reset
triggered by a
violation of
VPOR or VPV
VDDP
PORST
GND
PORESET
VDDP
GND
XMC4000
RPORST
(optional)
External
reset
trigger
Supply
Monitoring
IPPD
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Electrical Parameters
Data Sheet 66 V1.1, 2018-09
Figure 22 Power-Up Behavior
3.3.3 Power Sequencing
While starting up and shutting down as well as when switching power modes of the
system it is important to limit the current load steps. A typical cause for such load steps
is changing the CPU frequency fCPU. Load steps exceeding the below defined values
may cause a power on reset triggered by the supply monitor.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
2) Maximum threshold for reset deassertion.
3) The VDDP monitoring has a typical hysteresis of VPORHYS =180mV.
4) If tPR is not met, low spikes on PORST may be seen during start up (e.g. reset pulses generated by the supply
monitoring due to a slow ramping VDDP).
as programmed
V
POR
V
PV
V
DDP
V
DDC
Pads
PORST
V
DDPPA
Undefined High-impedance or pull -device active
3.3 V
1.3 V
t
SSW
t
VCR
t
PR
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Data Sheet 67 V1.1, 2018-09
Positive Load Step Examples
System assumptions:
fCPU = fSYS, target frequency fCPU = 144 MHz, main PLL fVCO = 288 MHz, stepping done
by K2 divider, tPLSS between individual steps:
24 MHz - 48 MHz - 72 MHz - 96 MHz - 144 MHz (K2 steps 12 - 6 - 4 - 3 - 2)
24 MHz - 48 MHz - 96 MHz - 144 MHz (K2 steps 12 - 6 - 3 - 2)
24 MHz - 72 MHz - 144 MHz (K2 steps 12 - 4 - 2)
Table 37 Power Sequencing Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Positive Load Step Current
Δ
IPLS SR - 50 mA Load increase
on VDDP
Δ
t 10 ns
Negative Load Step
Current
Δ
INLS SR - 150 mA Load decrease
on VDDP
Δ
t 10 ns
VDDC Voltage Over-
/ Undershoot from Load
Step
Δ
VLS CC - ±100 mV For maximum
positive or
negative load
step
Positive Load Step Settling
Time
tPLSS SR 50 -μs
Negative Load Step
Settling Time
tNLSS SR 100 -μs
External Buffer Capacitor
on VDDC
CEXT SR - 10 - μF In addition
C= 100 nF
capacitor on
each VDDC pin
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Electrical Parameters
Data Sheet 68 V1.1, 2018-09
3.3.4 Phase Locked Loop (PLL) Characteristics
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Main and USB PLL
Table 38 PLL Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Accumulated Jitter DP CC −−±5 ns accumulated
over 300 cycles
fSYS =144MHz
Duty Cycle1)
1) 50% for even K2 divider values, 50±(10/K2) for odd K2 divider values.
DDC CC 46 50 54 % Low pulse to
total period,
assuming an
ideal input clock
source
PLL base frequency fPLLBASE
CC 30 140 MHz
VCO input frequency fREF CC 4 16 MHz
VCO frequency range fVCO CC 260 520 MHz
PLL lock-in time tL CC −−400 μs
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Data Sheet 69 V1.1, 2018-09
3.3.5 Internal Clock Source Characteristics
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Fast Internal Clock Source
Table 39 Fast Internal Clock Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Nominal frequency fOFINC
CC
36.5 MHz not calibrated
24 MHz calibrated
Accuracy
Δ
fOFI
CC -0.5 0.5 % automatic
calibration1)2)
1) Error in addition to the accuracy of the reference clock.
2) Automatic calibration compensates variations of the temperature and in the VDDP supply voltage.
-15 15 % factory
calibration,
VDDP =3.3V
-25 25 % no calibration,
VDDP =3.3V
-7 7 % Variation over
voltage range3)
3.13 V VDDP
3.63 V
3) Deviations from the nominal VDDP voltage induce an additional error to the uncalibrated and/or factory
calibrated oscillator frequency.
Start-up time tOFIS CC 50 −μs
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Data Sheet 70 V1.1, 2018-09
Slow Internal Clock Source
Table 40 Slow Internal Clock Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Nominal frequency fOSI CC 32.768 kHz
Accuracy
Δ
fOSI
CC -4 4%VBAT = const.
CTA
85 °C
-5 5%
VBAT = const.
TA<C or
TA>85 °C
-5 5%2.4VVBAT,
TA=2C
-10 10 % 1.95 V
VBAT <2.4V,
TA=2C
Start-up time tOSIS CC 50 −μs
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Data Sheet 71 V1.1, 2018-09
3.3.6 JTAG Interface Timing
The following parameters are applicable for communication through the JTAG debug
interface. The JTAG module is fully compliant with IEEE1149.1-2000.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Note: Operating conditions apply.
Table 41 JTAG Interface Timing Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
TCK clock period t1SR 25 ns
TCK high time t2SR 10 ns
TCK low time t3SR 10 ns
TCK clock rise time t4SR––4ns
TCK clock fall time t5SR––4ns
TDI/TMS setup
to TCK rising edge
t6SR6––ns
TDI/TMS hold
after TCK rising edge
t7SR6––ns
TDO valid after TCK falling
edge1) (propagation delay)
1) The falling edge on TCK is used to generate the TDO timing.
t8CC––13nsC
L=50pF
3––nsC
L=20pF
TDO hold after TCK falling
edge1) t18 CC2––ns
TDO high imped. to valid
from TCK falling edge1)2)
2) The setup time for TDO is given implicitly by the TCK cycle time.
t9CC––14nsC
L=50pF
TDO valid to high imped.
from TCK falling edge1) t10 CC – – 13.5 ns CL=50pF
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Electrical Parameters
Data Sheet 72 V1.1, 2018-09
Figure 23 Test Clock Timing (TCK)
Figure 24 JTAG Timing
JTAG_TCK.vsd
0.9
V
DDP
0.5
V
DDP
TCK
t
1
t
2
0.1
V
DDP
t
3
t
5
t
4
JTAG_IO.vsd
t
6
t
7
t
6
t
7
t
9
t
8
t
10
TCK
TMS
TDI
TDO
t
18
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Electrical Parameters
Data Sheet 73 V1.1, 2018-09
3.3.7 Serial Wire Debug Port (SW-DP) Timing
The following parameters are applicable for communication through the SW-DP
interface.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Note: Operating conditions apply.
Figure 25 SWD Timing
Table 42 SWD Interface Timing Parameters (Operating Conditions apply)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
SWDCLK clock period tSC SR 25 ns CL=30pF
40 ns CL=50pF
SWDCLK high time t1 SR 10 500000 ns
SWDCLK low time t2 SR 10 500000 ns
SWDIO input setup
to SWDCLK rising edge
t3 SR 6 ns
SWDIO input hold
after SWDCLK rising edge
t4 SR 6 ns
SWDIO output valid time
after SWDCLK rising edge
t5 CC 17 ns CL=50pF
13 ns CL=30pF
SWDIO output hold time
from SWDCLK rising edge
t6 CC 3 ns
SWDCLK
SWDIO
(Output)
t1t2
t6
t5
tSC
SWDIO
(Input)
t3t4
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Data Sheet 74 V1.1, 2018-09
3.3.8 Peripheral Timing
3.3.8.1 Synchronous Serial Interface (USIC SSC) Timing
The following parameters are applicable for a USIC channel operated in SSC mode.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 43 USIC SSC Master Mode Timing
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
SCLKOUT master clock
period
tCLK CC 33.3 −− ns
Slave select output SELO
active to first SCLKOUT
transmit edge
t1 CC tPB -
6.51)
1) tPB = 1 / fPB
−− ns
Slave select output SELO
inactive after last
SCLKOUT receive edge
t2 CC tPB -
8.51) −− ns
Data output DOUT[3:0]
valid time
t3 CC -6 8ns
Receive data input
DX0/DX[5:3] setup time to
SCLKOUT receive edge
t4 SR 23 −− ns
Data input DX0/DX[5:3]
hold time from SCLKOUT
receive edge
t5 SR 1 −− ns
Table 44 USIC SSC Slave Mode Timing
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
DX1 slave clock period tCLK SR 66.6 −− ns
Select input DX2 setup to
first clock input DX1 transmit
edge1)
t10 SR 3 −− ns
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Data Sheet 75 V1.1, 2018-09
Select input DX2 hold after
last clock input DX1 receive
edge1)
t11 SR 4 −− ns
Receive data input
DX0/DX[5:3] setup time to
shift clock receive edge1)
t12 SR 6 −− ns
Data input DX0/DX[5:3] hold
time from clock input DX1
receive edge1)
t13 SR 4 −− ns
Data output DOUT[3:0] valid
time
t14 CC 0 24 ns
1) This input timing is valid for asynchronous input signal handling of slave select input, shift clock input, and
receive data input (bits DXnCR.DSEN = 0).
Table 44 USIC SSC Slave Mode Timing
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
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Data Sheet 76 V1.1, 2018-09
Figure 26 USIC - SSC Master/Slave Mode Timing
Note: This timing diagram shows a standard configuration, for which the slave select
signal is low-active, and the serial clock signal is not shifted and not inverted.
t
2
t
1
USIC_SSC_TMGX.VSD
Clock Output
SCLKOUT
Data Output
DOUT[3:0]
t
3
t
3
t
5
Data
valid
t
4
First Transmit
Edge
Data Input
DX0/DX[5:3]
Select Output
SELOx
Active
Master Mode Timing
Slave Mode Timing
t
11
t
10
Clock Input
DX1
Data Output
DOUT[3:0]
t
14
t
14
Data
valid
Data Input
DX0/DX[5:3]
Select Input
DX2
Active
t
13
t
12
Transmit Edge: with this clock edge, transmit data is shifted to transmit data output.
Receive Edge: with this clock edge, receive data at receive data input is latched.
Receive
Edge Last Receive
Edge
InactiveInactive
Transmit
Edge
InactiveInactive
First Transmit
Edge Receive
Edge Transmit
Edge Last Receive
Edge
t
5
Data
valid
t
4
Data
valid
t
12
t
13
Drawn for BRGH .SCLKCFG = 00B. Also valid for for SCLKCFG = 01B with inverted SCLKOUT signal.
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Data Sheet 77 V1.1, 2018-09
3.3.8.2 Inter-IC (IIC) Interface Timing
The following parameters are applicable for a USIC channel operated in IIC mode.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 45 USIC IIC Standard Mode Timing1)
1) Due to the wired-AND configuration of an IIC bus system, the port drivers of the SCL and SDA signal lines
need to operate in open-drain mode. The high level on these lines must be held by an external pull-up device,
approximalely 10 kOhm for operation at 100 kbit/s, approximately 2 kOhm for operation at 400 kbit/s.
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Fall time of both SDA and
SCL
t1
CC/SR --300ns
Rise time of both SDA and
SCL
t2
CC/SR - - 1000 ns
Data hold time t3
CC/SR 0- - µs
Data set-up time t4
CC/SR 250 - - ns
LOW period of SCL clock t5
CC/SR 4.7 - - µs
HIGH period of SCL clock t6
CC/SR 4.0 - - µs
Hold time for (repeated)
START condition
t7
CC/SR 4.0 - - µs
Set-up time for repeated
START condition
t8
CC/SR 4.7 - - µs
Set-up time for STOP
condition
t9
CC/SR 4.0 - - µs
Bus free time between a
STOP and START
condition
t10
CC/SR 4.7 - - µs
Capacitive load for each
bus line
Cb SR - - 400 pF
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Data Sheet 78 V1.1, 2018-09
Table 46 USIC IIC Fast Mode Timing1)
1) Due to the wired-AND configuration of an IIC bus system, the port drivers of the SCL and SDA signal lines
need to operate in open-drain mode. The high level on these lines must be held by an external pull-up device,
approximalely 10 kOhm for operation at 100 kbit/s, approximately 2 kOhm for operation at 400 kbit/s.
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Fall time of both SDA and
SCL
t1
CC/SR 20 +
0.1*Cb
2)
2) Cb refers to the total capacitance of one bus line in pF.
- 300 ns
Rise time of both SDA and
SCL
t2
CC/SR 20 +
0.1*Cb
2)
- 300 ns
Data hold time t3
CC/SR 0- - µs
Data set-up time t4
CC/SR 100 - - ns
LOW period of SCL clock t5
CC/SR 1.3 - - µs
HIGH period of SCL clock t6
CC/SR 0.6 - - µs
Hold time for (repeated)
START condition
t7
CC/SR 0.6 - - µs
Set-up time for repeated
START condition
t8
CC/SR 0.6 - - µs
Set-up time for STOP
condition
t9
CC/SR 0.6 - - µs
Bus free time between a
STOP and START
condition
t10
CC/SR 1.3 - - µs
Capacitive load for each
bus line
Cb SR - - 400 pF
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Electrical Parameters
Data Sheet 79 V1.1, 2018-09
Figure 27 USIC IIC Stand and Fast Mode Timing
3.3.8.3 Inter-IC Sound (IIS) Interface Timing
The following parameters are applicable for a USIC channel operated in IIS mode.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 47 USIC IIS Master Transmitter Timing
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Clock period t1 CC 33.3 −−ns
Clock high time t2 CC 0.35 x
t1min
−−ns
Clock low time t3 CC 0.35 x
t1min
−−ns
Hold time t4 CC 0 −−ns
Clock rise time t5 CC −−0.15 x
t1min
ns
SCL
SDA
SCL
SDA
t
1
t
2
t
1
t
2
t
10
t
9
t
7
t
8
t
7
t
3
t
4
t
5
t
6
PSSr
S
70%
30%
9
th
clock
9
th
clock
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Data Sheet 80 V1.1, 2018-09
Figure 28 USIC IIS Master Transmitter Timing
Figure 29 USIC IIS Slave Receiver Timing
Table 48 USIC IIS Slave Receiver Timing
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Clock period t6 SR 66.6 −−ns
Clock high time t7 SR 0.35 x
t6min
−−ns
Clock low time t8 SR 0.35 x
t6min
−−ns
Set-up time t9 SR 0.2 x
t6min
−−ns
Hold time t10 SR 0 −−ns
SCK
WA/
DOUT
t
1
t
5
t
3
t
2
t
4
SCK
WA/
DIN
t
6
t
10
t
8
t
7
t
9
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Data Sheet 81 V1.1, 2018-09
3.3.8.4 SDMMC Interface Timing
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Note: Operating Conditions apply, total external capacitive load CL = 40 pF.
AC Timing Specifications (Full-Speed Mode)
Table 49 SDMMC Timing for Full-Speed Mode
Parameter Symbol Values Unit Note/ Test
Condition
Min. Max.
Clock frequency in full speed
transfer mode (1/tpp)
fpp CC 0 24 MHz
Clock cycle in full speed
transfer mode
tpp CC 40 ns
Clock low time tWL CC 10 ns
Clock high time tWH CC 10 ns
Clock rise time tTLH CC 10 ns
Clock fall time tTHL CC 10 ns
Inputs setup to clock rising
edge
tISU_F SR 2 ns
Inputs hold after clock rising
edge
tIH_F SR 2 ns
Outputs valid time in full speed
mode
tODLY_F CC 10 ns
Outputs hold time in full speed
mode
tOH_F CC 0 ns
Table 50 SD Card Bus Timing for Full-Speed Mode1)
Parameter Symbol Values Unit Note/ Test
Condition
Min. Max.
SD card input setup time tISU 5ns
SD card input hold time tIH 5ns
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Data Sheet 82 V1.1, 2018-09
Full-Speed Output Path (Write)
Figure 30 Full-Speed Output Path
Full-Speed Write Meeting Setup (Maximum Delay)
The following equations show how to calculate the allowed skew range between the
SD_CLK and SD_DAT/CMD signals on the PCB.
No clock delay:
(1)
SD card output valid time tODLY 14 ns
SD card output hold time tOH 0ns
1) Reference card timing values for calculation examples. Not subject to production test and not characterized.
Table 50 SD Card Bus Timing for Full-Speed Mode1) (cont’d)
Parameter Symbol Values Unit Note/ Test
Condition
Min. Max.
SD Clock at
Host Pin
SD Clock at
Card Pin
Output at
Host Pins
Output at
Card Pins
t
pp
(Clock Cycle)
Driving
Edge
Sampling
Edge
t
WL
t
CLK_DELAY
Output Valid Time:
t
ODLY_H
Output Hold Time:
t
OH_H
t
DATA _DELAY
+ t
TAP_DELAY
t
ISU
t
IH
tODLY_F tDATA_DELAY tTAP_DELAY tISU
+++tWL
<
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Electrical Parameters
Data Sheet 83 V1.1, 2018-09
With clock delay:
(2)
(3)
The data can be delayed versus clock up to 5 ns in ideal case of tWL= 20 ns.
Full-Speed Write Meeting Hold (Minimum Delay)
The following equations show how to calculate the allowed skew range between the
SD_CLK and SD_DAT/CMD signals on the PCB.
(4)
The clock can be delayed versus data up to 18.2 ns (external delay line) in ideal case of
tWL= 20 ns, with maximum tTAP_DELAY = 3.2 ns programmed.
tODLY_F tDATA_DELAY tTAP_DELAY tISU
+++tWL tCLK_DELAY
+<
tDATA_DELAY tTAP_DELAY tWL
++tPP tCLK_DELAY tISU
tODLY_F
+<
tDATA_DELAY tTAP_DELAY 20++40tCLK_DELAY 5–10+<
tDATA_DELAY 5tCLK_DELAY tTAP_DELAY
+<
tCLK_DELAY tWL tOH_F tDATA_DELAY tTAP_DELAY tIH
++ +<
tCLK_DELAY 20 tDATA_DELAY tTAP_DELAY 5++<
tDATA_DELAY 15 tCLK_DELAY tTAP_DELAY
++<
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Data Sheet 84 V1.1, 2018-09
Full-Speed Input Path (Read)
Figure 31 Full-Speed Input Path
Full-Speed Read Meeting Setup (Maximum Delay)
The following equations show how to calculate the allowed combined propagation delay
range of the SD_CLK and SD_DAT/CMD signals on the PCB.
(5)
The data + clock delay can be up to 4 ns for a 40 ns clock cycle.
SD Clock at
Host Pin
SD Clock at
Card Pin
Output at
Host Pins
Output at
Card Pins
t
pp
(Clock Cycle )
Driving
Edge
Sampling
Edge
t
CLK_DELAY
t
ODLY
t
OH
t
DATA_DELAY
+ t
TAP_DELAY
t
IH_H
t
ISU_H
tCLK_DELAY tDATA_DELAY tTAP_DELAY tODLY tISU_F
+ + + + 0,5 t×pp
<
tCLK_DELAY tDATA_DELAY
+ 0,5 t×pp tODLY tISU_F
tTAP_DELAY
<
tCLK_DELAY tDATA_DELAY
+ 20142tTAP_DELAY
<
tCLK_DELAY tDATA_DELAY
+4tTAP_DELAY
<
Subject to Agreement on the Use of Product Information
Inhneon”
XMC4300
XMC4000 Family
Electrical Parameters
Data Sheet 85 V1.1, 2018-09
Full-Speed Read Meeting Hold (Minimum Delay)
The following equations show how to calculate the allowed combined propagation delay
range of the SD_CLK and SD_DAT/CMD signals on the PCB.
(6)
The data + clock delay must be greater than 2 ns if tTAP_DELAY is not used.
If the tTAP_DELAY is programmed to at least 2 ns, the data + clock delay must be greater
than 0 ns (or less). This is always fulfilled.
AC Timing Specifications (High-Speed Mode)
Table 51 SDMMC Timing for High-Speed Mode
Parameter Symbol Values Unit Note/ Test
Condition
Min. Max.
Clock frequency in high speed
transfer mode (1/tpp)
fpp CC 0 48 MHz
Clock cycle in high speed
transfer mode
tpp CC 20 ns
Clock low time tWL CC 7 ns
Clock high time tWH CC 7 ns
Clock rise time tTLH CC 3ns
Clock fall time tTHL CC 3ns
Inputs setup to clock rising
edge
tISU_H SR 2 ns
Inputs hold after clock rising
edge
tIH_H SR 2 ns
Outputs valid time in high
speed mode
tODLY_H CC 14 ns
Outputs hold time in high
speed mode
tOH_H CC 2 ns
tCLK_DELAY tOH tDATA_DELAY tTAP_DELAY tIH_F
>++ +
tCLK_DELAY tDATA_DELAY tIH_F tOH
tTAP_DELAY
>+
tCLK_DELAY tDATA_DELAY 2tTAP_DELAY
>+
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XMC4300
XMC4000 Family
Electrical Parameters
Data Sheet 86 V1.1, 2018-09
High-Speed Output Path (Write)
Figure 32 High-Speed Output Path
High-Speed Write Meeting Setup (Maximum Delay)
The following equations show how to calculate the allowed skew range between the
SD_CLK and SD_DAT/CMD signals on the PCB.
Table 52 SD Card Bus Timing for High-Speed Mode1)
1) Reference card timing values for calculation examples. Not subject to production test and not characterized.
Parameter Symbol Values Unit Note/ Test
Condition
Min. Max.
SD card input setup time tISU 6ns
SD card input hold time tIH 2ns
SD card output valid time tODLY 14 ns
SD card output hold time tOH 2.5 ns
SD Clock at
Host Pin
SD Clock at
Card Pin
Output at
Host Pins
Output at
Card Pins
tpp
(Clock Cycle)
Driving
Edge
Sampling
Edge
tWL
tCLK_DELAY
Output Valid Time:
tODLY_H
Output Hold Time:
tOH_H
tDATA_DELAY
+ tTAP_DELAY
tISU
tIH
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XMC4300
XMC4000 Family
Electrical Parameters
Data Sheet 87 V1.1, 2018-09
No clock delay:
(7)
With clock delay:
(8)
(9)
The data delay is less than the clock delay by at least 10 ns in the ideal case where tWL=
10 ns.
High-Speed Write Meeting Hold (Minimum Delay)
The following equations show how to calculate the allowed skew range between the
SD_CLK and SD_DAT/CMD signals on the PCB.
(10)
The clock can be delayed versus data up to 13.2 ns (external delay line) in ideal case of
tWL= 10 ns, with maximum tTAP_DELAY = 3.2 ns programmed.
tODLY_H tDATA_DELAY tTAP_DELAY tISU
+++tWL
<
tODLY_H tDATA_DELAY tTAP_DELAY tISU
+++tWL tCLK_DELAY
+<
tDATA_DELAY tTAP_DELAY tCLK_DELAY
+ tWL tISU
tODLY_H
<
tDATA_DELAY tCLK_DELAY
tWL tISU
tODLY_H
tTAP_DELAY
<
tDATA_DELAY tCLK_DELAY
–106–14tTAP_DELAY
<
tDATA_DELAY tCLK_DELAY
–10tTAP_DELAY
<
tCLK_DELAY tWL tOH_H tDATA_DELAY tTAP_DELAY tIH
++ +<
tCLK_DELAY tDATA_DELAY
tWL tOH_H tTAP_DELAY tIH
++<
tCLK_DELAY tDATA_DELAY
–102tTAP_DELAY 2++<
tCLK_DELAY tDATA_DELAY
–10tTAP_DELAY
+<
Subject to Agreement on the Use of Product Information
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XMC4300
XMC4000 Family
Electrical Parameters
Data Sheet 88 V1.1, 2018-09
High-Speed Input Path (Read)
Figure 33 High-Speed Input Path
High-Speed Read Meeting Setup (Maximum Delay)
The following equations show how to calculate the allowed combined propagation delay
range of the SD_CLK and SD_DAT/CMD signals on the PCB.
(11)
The data + clock delay can be up to 4 ns for a 20 ns clock cycle.
SD Clock at
Host Pin
SD Clock at
Card Pin
Output at
Host Pins
Output at
Card Pins
t
pp
(Clock Cycle)
Driving
Edge
Sampling
Edge
t
CLK_DELAY
t
ODLY
t
OH
t
DATA_DELAY
+ t
TAP_DELAY
t
IH_H
t
ISU_H
tCLK_DELAY tDATA_DELAY tTAP_DELAY tODLY tISU_H
++++tpp
<
tCLK_DELAY tDATA_DELAY
+tpp tODLY tISU_H
tTAP_DELAY
<
tCLK_DELAY tDATA_DELAY
+ 20142tTAP_DELAY
<
tCLK_DELAY tDATA_DELAY
+4tTAP_DELAY
<
Subject to Agreement on the Use of Product Information
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XMC4300
XMC4000 Family
Electrical Parameters
Data Sheet 89 V1.1, 2018-09
High-Speed Read Meeting Hold (Minimum Delay)
The following equations show how to calculate the allowed combined propagation delay
range of the SD_CLK and SD_DAT/CMD signals on the PCB.
(12)
The data + clock delay must be greater than -0.5 ns for a 20 ns clock cycle. This is always
fulfilled.
tCLK_DELAY tOH tDATA_DELAY tTAP_DELAY tIH_H
>++ +
tCLK_DELAY tDATA_DELAY tIH_H tOH
tTAP_DELAY
>+
tCLK_DELAY tDATA_DELAY 2 2,5 tTAP_DELAY
>+
tCLK_DELAY tDATA_DELAY 0,5tTAP_DELAY
>+
Subject to Agreement on the Use of Product Information
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XMC4300
XMC4000 Family
Electrical Parameters
Data Sheet 90 V1.1, 2018-09
3.3.9 USB Interface Characteristics
The Universal Serial Bus (USB) Interface is compliant to the USB Rev. 2.0 Specification
and the OTG Specification Rev. 1.3. High-Speed Mode is not supported.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Figure 34 USB Signal Timing
Table 53 USB Timing Parameters (operating conditions apply)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Rise time tRCC 4 20 ns CL=50pF
Fall time tFCC 4 20 ns CL=50pF
Rise/Fall time matching tR/tFCC 90 111.11 % CL=50pF
Crossover voltage VCRS CC 1.3 2.0 V CL=50pF
USB_Rise-Fall-Times.vsd
10%
90%
D-
D+
t
R
t
F
10%
90%
V
CRS
V
SS
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XMC4300
XMC4000 Family
Electrical Parameters
Data Sheet 91 V1.1, 2018-09
3.3.10 Ethernet Interface (ETH) Characteristics
For proper operation of the Ethernet Interface it is required that fSYS 100 MHz.
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
3.3.10.1 ETH Measurement Reference Points
Figure 35 ETH Measurement Reference Points
ETH_Testpoints.vsd
ETH Clock 1.4
V
1.4
V
2.0
V
0.8
V
2.0
V
0.8
V
t
R
t
F
ETH I/O
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XMC4300
XMC4000 Family
Electrical Parameters
Data Sheet 92 V1.1, 2018-09
3.3.10.2 ETH Management Signal Parameters (ETH_MDC, ETH_MDIO)
Figure 36 ETH Management Signal Timing
Table 54 ETH Management Signal Timing Parameters
Parameter Symbol Values Unit Note /
Test Conditi
on
Min. Typ. Max.
ETH_MDC period t1CC 400 ns CL=25pF
ETH_MDC high time t2CC 160 ns
ETH_MDC low time t3CC 160 ns
ETH_MDIO setup time (output) t4CC 10 ns
ETH_MDIO hold time (output) t5CC 10 ns
ETH_MDIO data valid (input) t6SR 0 300 ns
ETH_Timing-Mgmt.vsd
ETH_MDC
ETH_MDIO
(output)
t
5
Valid Data
t
4
Valid Data
t
6
ETH_MDIO
(input)
ETH_MDC
ETH_MDIO sourced by STA:
ETH_MDIO sourced by PHY:
ETH_MDC
t
1
t
3
t
2
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XMC4300
XMC4000 Family
Electrical Parameters
Data Sheet 93 V1.1, 2018-09
3.3.10.3 ETH RMII Parameters
In the following, the parameters of the RMII (Reduced Media Independent Interface) are
described.
Figure 37 ETH RMII Signal Timing
Table 55 ETH RMII Signal Timing Parameters
Parameter Symbol Values Unit Note /
Test Condit
ion
Min. Typ. Max.
ETH_RMII_REF_CL clock period t13 SR 20 ns CL=25pF;
50 ppm
ETH_RMII_REF_CL clock high time t14 SR 7 13 ns CL=25pF
ETH_RMII_REF_CL clock low time t15 SR 7 13 ns
ETH_RMII_RXD[1:0],
ETH_RMII_CRS setup time
t16 SR 4 ns
ETH_RMII_RXD[1:0],
ETH_RMII_CRS hold time
t17 SR 2 ns
ETH_RMII_TXD[1:0],
ETH_RMII_TXEN data valid
t18 CC 4 15 ns
ETH_Timing-RMII.vsd
ETH_RMII_REF_CL
t17
Valid Data
t16
Valid Data
t18
t13
t15 t14
ETH_RMII_REF_CL
ETH_RMII_REF_CL
ETH_RMII _RXD[1:0]
ETH_RMII _CRS
ETH_RMII _TXD[1:0]
ETH_RMII _TXEN
(sourced by STA )
(sourced by PHY )
Valid Data
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XMC4300
XMC4000 Family
Electrical Parameters
Data Sheet 94 V1.1, 2018-09
3.3.11 EtherCAT (ECAT) Characteristics
3.3.11.1 ECAT Measurement Reference Points
Figure 38 Measurement Reference Points
3.3.11.2 ETH Management Signal Parameters (MCLK, MDIO)
Table 56 ECAT Management Signal Timing Parameters
Parameter Symbol Values Unit Note /
Test Conditi
on
Min. Typ. Max.
ECAT_MCLK period tMCLKCC 400 ns IEEE802.3
requirement
(2.5 MHz)
CL=25pF
ECAT_MCLK high time tMCLK_h
CC 160 – ns
ECAT_MCLK low time tMCLK_l
CC 160 – ns
ECAT_MDIO setup time
(output)
tD_setup
CC 10 – – ns
ECAT_MDIO hold time (output) tD_hold
CC 10 – – ns
ECAT_MDIO data valid (input) tD_valid
SR 0 300 ns
ECAT_Testpoints.vsd
ECAT Clock 1.4 V1.4 V
2.0 V
0.8 V
2.0 V
0.8 V
tRtF
ECAT I/O
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XMC4300
XMC4000 Family
Electrical Parameters
Data Sheet 95 V1.1, 2018-09
Figure 39 ECAT Management Signal Timing
3.3.11.3 MII Timing TX Characteristics
Table 57 ETH MII TX Signal Timing Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
PHY_CLK25, TX_CLK
period
tTX_CLK
SR –40–ns
Delay between PHY clock
source PHY_CLK25 and
TX_CLK output of the PHY
tPHY_delay
SR ns PHY dependent
ECAT_Timing-Mgmt.vsd
ECAT_MCLK
ECAT_MDIO
(output) Valid Data
tD_setup
Valid Data
tD_valid
ECAT_MDIO
(input)
ECAT_MCLK
ECAT_MDIO sourced by STA:
ECAT_MDIO sourced by PHY:
ECAT_MCLK
tMCLK
tMCLK_l tMCLK_h
tD_hold
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XMC4300
XMC4000 Family
Electrical Parameters
Data Sheet 96 V1.1, 2018-09
Note: ECAT0_CONPx.TX_SHIFT can be adjusted by displaying TX_CLK of a PHY and
TXEN/TXD[3:0] on an oscilloscope. TXEN/TXD[3:0] is allowed to change between
0 ns and 25 ns after a rising edge of TX_CLK (according to IEEE802.3 – check
your PHY’s documentation). Configure TX_SHIFT so that TXEN/TXD[3:0] change
near the middle of this range. It is sufficient to check just one of the TXEN/TXD[3:0]
signals, because they are nearly generated at the same time.
Figure 40 MII TX Characteristics
PHY setup requirement:
TXEN/TXD[3:0] with respect
to TX_CLK
tTX_setup
SR 15 0 ns PHY dependent
IEEE802.3 limit
is 15 ns
PHY hold requirement:
TXEN/TXD[3:0] with respect
to TX_CLK
tTX_hold
CC 0 25 ns PHY dependent
IEEE802.3 limit
is 0 ns
Table 57 ETH MII TX Signal Timing Parameters (cont’d)
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
tPHY_delady
ECAT_MII_TXD[3:0]
ECAT_MII_TXEN Valid Data
ECAT_MII_TX_CLK
PHY_CLK25
tPHY_TX_Setup tPHY_TX_Hold
TX_Shift[1:0]=00
Valid Data
Valid Data
10ns
20ns
30ns
ECAT_MII_TXD[3:0]
ECAT_MII_TXEN
TX_Shift[1:0]=01
ECAT_MII_TXD[3:0]
ECAT_MII_TXEN
TX_Shift[1:0]=10
ECAT_MII_TXD[3:0]
ECAT_MII_TXEN
TX_Shift[1:0]=11
Valid Data
FAIL:Setup/HoldTimingviolated
tTX_CLK
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XMC4300
XMC4000 Family
Electrical Parameters
Data Sheet 97 V1.1, 2018-09
3.3.11.4 MII Timing RX Characteristics
Figure 41 MII RX characteristics
Table 58 ETH MII RX Signal Timing Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
RX_CLK period tRX_CLK
SR –40–nsC
L=25pF,
IEEE802.3
requirement
RX_DV/RX_DV/RXD[3:0]
valid before rising
edge of RX_CLK
tRX_setup
SR 10 – – ns
RX_DV/RX_DV/RXD[3:0]
valid after rising
edge of RX_CLK
tRX_hold
SR 10 – – ns
ECAT_MII_RX_CLK
tRX_hold
tRX_setup
Valid Data
ECAT_MII_RXD[3:0]
ECAT_MII_RX_DV
ECAT_MII_RX_ER
tRX_CLK
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XMC4000 Family
Electrical Parameters
Data Sheet 98 V1.1, 2018-09
3.3.11.5 Sync/Latch Timings
Note: SYNC0/1 pulse length are initially loaded by EEPROM content ADR 0x0002. The
actual used value can be read back from Register DC_PULSE_LEN.
Figure 42 Sync/Latch Timings
Table 59 Sync/Latch Timings
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
SYNC0/1 tDC_SYNC_
Jitter SR 11 +
m1)
1) additional delay form logic and pad, number is added after characterization
ns
LATCH0/1 tDC_LATCH
SR 12 +
n2)
2) additional shaping delay, number is added after characterization
–– ns
tDC_SYNC_Jiiter
SYNC0/1
LATCH0/1
tDC_LATCH tDC_LATCH
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XMC4300
XMC4000 Family
Package and Reliability
Data Sheet 99 V1.1, 2018-09
4 Package and Reliability
The XMC4300 is a member of the XMC4000 Family of microcontrollers. It is also
compatible to a certain extent with members of similar families or subfamilies.
Each package is optimized for the device it houses. Therefore, there may be slight
differences between packages of the same pin-count but for different device types. In
particular, the size of the Exposed Die Pad may vary.
If different device types are considered or planned for an application, it must be ensured
that the board layout fits all packages under consideration.
4.1 Package Parameters
Table 60 provides the thermal characteristics of the packages used in XMC4300.
Note: For electrical reasons, it is required to connect the exposed pad to the board
ground VSS, independent of EMC and thermal requirements.
4.1.1 Thermal Considerations
When operating the XMC4300 in a system, the total heat generated in the chip must be
dissipated to the ambient environment to prevent overheating and the resulting thermal
damage.
The maximum heat that can be dissipated depends on the package and its integration
into the target board. The “Thermal resistance RΘJA” quantifies these parameters. The
power dissipation must be limited so that the average junction temperature does not
exceed 150 °C.
Table 60 Thermal Characteristics of the Packages
Parameter Symbol Limit Values Unit Package Types
Min. Max.
Exposed Die Pad
dimensions including U-
Groove
Ex × Ey
CC -7.0×7.0 mm PG-LQFP-100-25
Exposed Die Pad
dimensions excluding U-
Groove
Ax × Ay
CC -6.2×6.2 mm PG-LQFP-100-25
Thermal resistance
Junction-Ambient
TJ150 °C
RΘJA
CC - 22.5 K/W PG-LQFP-100-251)
1) Device mounted on a 4-layer JEDEC board (JESD 51-7) with thermal vias; exposed pad soldered.
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Package and Reliability
Data Sheet 100 V1.1, 2018-09
The difference between junction temperature and ambient temperature is determined by
ΔT = (PINT + PIOSTAT + PIODYN) × RΘJA
The internal power consumption is defined as
PINT = VDDP × IDDP (switching current and leakage current).
The static external power consumption caused by the output drivers is defined as
PIOSTAT = Σ((VDDP-VOH) × IOH) + Σ(VOL × IOL)
The dynamic external power consumption caused by the output drivers (PIODYN) depends
on the capacitive load connected to the respective pins and their switching frequencies.
If the total power dissipation for a given system configuration exceeds the defined limit,
countermeasures must be taken to ensure proper system operation:
Reduce VDDP, if possible in the system
Reduce the system frequency
Reduce the number of output pins
Reduce the load on active output drivers
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Inf
XMC4300
XMC4000 Family
Package and Reliability
Data Sheet 101 V1.1, 2018-09
4.2 Package Outlines
The exposed die pad dimensions are listed in Table 60.
Figure 43 PG-LQFP-100-25 (Plastic Green Low Profile Quad Flat Package)
All dimensions in mm.
You can find complete information about Infineon packages, packing and marking in our
Infineon Internet Page “Packages”: http://www.infineon.com/packages
PG-LQFP-100-24, -25-PO V04
0.5
24 x 0.5 = 12
0.2 A-B0.08 MC
C
D100x
100x
-0.03
+0.07 2)
1.6 MAX.
±0.05
±0.05
C
0.1
0.08
1.4
±0.15
0.6
H
A B
Index Marking
1
100
D
14 1)
16
0.2 C A-B D
0.2 H A-B D
100x
4x
14
1)
16
Bottom View
100
1
Exposed Diepad
SEATING
PLANE
COPLANARITY
STAND OFF
-0.037
+0.073
0.127
0°...7°
3)
Ex
3)
Ax
3)
Ey
3)
Ay
1) Does not include plastic or metal protrusion of 0.25 max. per side
2) Does not include dambar protrusion of 0.08 max. per side
3) Refer table for exposed pad dimension details
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Inhneon”
XMC4300
XMC4000 Family
Quality Declarations
Data Sheet 102 V1.1, 2018-09
5 Quality Declarations
The qualification of the XMC4300 is executed according to the JEDEC standard
JESD47I.
Note: For automotive applications refer to the Infineon automotive microcontrollers.
Table 61 Quality Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Operation lifetime tOP CC 20 −− aTJ 109°C,
device permanent
on
ESD susceptibility
according to Human Body
Model (HBM)
VHBM
SR
−−3 000 V EIA/JESD22-
A114-B
ESD susceptibility
according to Charged
Device Model (CDM)
VCDM
SR
−−1 000 V Conforming to
JESD22-C101-C
Moisture sensitivity level MSL
CC
−−3JEDEC
J-STD-020D
Soldering temperature TSDR
SR
−−260 °C Profile according
to JEDEC
J-STD-020D
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