PCI9656 Brief Datasheet by Broadcom Limited

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PCI 9656
64-bit, 66MHz PCI Bus Mastering I/O Accelerator for Motorola
PowerQUICC& Generic 32-bit, 66MHz Local Bus Design
s
Maximum PCI Bandwidth for Your 32-bit Local Bus Applications
The PCI 9656 offers flexible connectivity and high performance I/O acceleration features
to enable leading edge PCI, CompactPCI, and embedded host designs.
Motorola®MPC 850/860 PowerQUICC Designs
The PCI 9656 is the perfect match for the industry leading 32-bit communication proces-
sor, the Motorola MPC 850/860 PowerQUICC. The PCI 9656 provides a direct connection
to PowerQUICC devices, enabling high-speed 64-bit, 66MHz PCI performance with its
Data Pipe Architecture™ technology.
Generic 32-bit, 66MHz Local Bus Designs
The PCI 9656 provides direct connection to two generic industry standard interconnect
buses. Designers use these 32-bit, 66MHz buses for a myriad of high-speed devices rang-
ing from processors, to DSPs, to memories, to custom ASICs and FPGAs.
The PCI 9656 Data Pipe Architecture technology enables high-speed, 64-bit, 66MHz PCI
I/O with those devices.
Move Your 32-bit Local Bus Designs Up to
64-bit, 66MHz PCI Operation
As PCI evolves to meet the ever increasing I/O demands of leading edge systems, PLX
continues to provide leading edge, high performance PCI I/O acceleration solutions. Based
on the architecture of the industry-leading PCI 9054, the PCI 9656 offers a variety of
enhancements for the needs of today's telecom, networking, and I/O adapter designs:
64-bit, 66MHz PCI operation
32-bit, 66MHz local bus operation
Dynamic DMA descriptor ring management with Valid bit semaphore control
PICMG 2.1 r2.0 Hot Swap Silicon, including Bias Voltage, Early Power, 64-bit
Initialization, and Intially Not Responding Support
PCI Power Management r1.1 D3COLD Power Management Event (PME) generation
PCI arbiter supporting 7 external masters
Reset and interrupt pins configurable for embedded host applications
JTAG boundary scan
The PCI 9656 is register compatible with the PCI 9054, enabling easy software migration.
Connectivity
64-bit, 66MHz PCI r2.2 compliant
Motorola PowerQUICC and
generic 32-bit, 66MHz local
bus modes
3.3V I/O, 5V tolerant bus
interfaces
PICMG 2.1 r2.0 Hot Swap Silicon
272-ball, 27 x 27 mm, 1.27 mm
pitch PBGA
Performance
Zero wait state burst operation
PCI bus bursts to 528 MB/sec
Local bus bursts to 264 MB/sec
2 DMA Channels
Block and Scatter/Gather transfers
DMA descriptor ring management
Demand Mode and EOT
Hardware controls
Direct Master data transfers
Generate any PCI transaction
Read ahead and programmable
read prefetch counter
Direct Slave data transfers
Access 8-, 16-, and 32-bit local
bus devices
Deferred reads, deferred writes,
read ahead, posted writes, pro-
grammable read prefetch counter
Control
I2O r1.5 messaging unit
Eight mailbox and two
doorbell registers
PCI arbiter supports 7
external masters
Host mode reset/interrupt signal
configuration
PCI D3COLD Power Management
Event (PME) generation support
Serial EEPROM interface
JTAG boundary scan
VERSION 1.0 2002
Independent 16 Qword (128 byte) read
and 32 Qword (256 byte) write FIFOs
Deferred reads, deferred writes, posted
writes, read ahead, and programmable read
prefetch counter
Programmable #READY time out
and recovery
Advanced Performance Features Common to
DMA, Direct Master, and Direct Slave
Zero wait state PCI & local bus bursts
Deep FIFOs prolong bursts
Unaligned PCI and local bus transfers of
any byte length
On-the-fly Endian conversion
Programmable local bus wait states
Parity checking on both buses
Messaging
Provides industry standard I2O r1.5
messaging unit
Supports general-purpose messaging
for proprietary message schemes
Eight 32-bit mailbox registers for polled
environments
Two 32-bit doorbell register for interrupt
driven environments
Embedded Host Features
PCI arbiter supports 7 external masters
Reset and interrupt signals configurable for
embedded host operation
Type 0/1 Configuration support allows
local bus master to configure PCI bus
and devices
Package
272-pin PBGA
27 mm x 27 mm, 1.27 mm ball pitch
Low power 2.5V CMOS core
3.3V I/O, 5V tolerant
Industrial temperature range operation
IEEE 1149.1 JTAG boundary scan
Backward Compatibility
The PCI 9656 register set is backward
compatible with the PCI 9054, with new
registers added for the new functionality
enhancements
Related PLX Products
Support for 32-bit, 66MHz PCI with 32-bit,
66MHz C, J, and M Local Bus support is
provided by the PCI 9056
See the PCI 9056 product brief for details
Serial EEPROM
Store configuration register power on,
reset values
An alternative to expansion ROM for stor-
ing Vital Product Data (VPD)
Supports 2 Kbit/4 Kbit microwire devices
with sequential read
Data Pipe Architecture
DMA
Service DMA descriptors, mastering on both
bus interfaces during data transfer
Two independent channels provide flexible
prioritization scheme
Each channel has its own bi-directional
32 Qword (256 byte) deep FIFO
Block Mode services a single DMA
descriptor in PCI 9656 registers
Scatter/Gather Mode services DMA
descriptor linked lists in memory
Burst descriptors from PCI or local
bus memory
Descriptor lists either linear (static) or
circular (dynamic) with Valid bit sema-
phore control
Direct Hardware DMA controls
Demand Mode to pause/resume
End of Transfer (EOT) to abort
Programmable local bus burst length,
including infinite
Enhanced M Mode supports bursts beyond
PowerQUICC 16 byte limit
Direct Master
Service local bus masters by mastering on
the PCI bus
Two local bus address spaces map to PCI
bus: one to memory; one to I/O
Generate all PCI memory and I/O
transaction types, including Memory
Write and Invalidate (MWI)
Independent 16 Qword (128 byte) read
and 32 Qword (256 byte) write FIFOs
Read ahead and programmable read
prefetch counter
PowerQUICC deferred reads and IDMA
(M mode only)
Direct Slave
Service PCI bus masters by mastering on the
local bus
Two general-purpose and one expansion
ROM PCI address spaces map to local
bus memory
Each address space may specify 8-, 16-,
or 32-bit local bus data transfer
PCI 9656 Features
The PCI 9656 64-bit, 66MHz PCI I/O accelera-
tor is the most advanced, general-purpose
bus mastering device available for Motorola
MPC 850/860 PowerQUICC and generic
32-bit, 66MHz local bus based designs. The
PCI 9656 incorporates PLX’s industry leading
Data Pipe Architecture technology, featuring
DMA engines, programmable Direct Master
and Direct Slave data transfer modes, and PCI
messaging functions.
Interfaces
PCI
64-bit, 66MHz r2.2 operation
Zero wait state bursts to 528 MB/s
Dual Address Cycle (DAC) support as a
PCI bus master
Vital Product Data (VPD)
3.3V I/O, 5V tolerant
PICMG 2.1 r2.0 Hot Swap Silicon
Programming Interface 0 (P=0)
Bias Voltage Support
Early Power Support
Initially Not Responding Support
PCI Hot Plug r1.0
PCI Power Management r1.1
Supports D0, D1, D2, D3HOT, & D3COLD
power states
D3COLD Power Management Event (PME)
generation to meet PC 2001 Windows
98/2000 communication adapter logo
certification requirements
Local Bus
Three local bus options on the device
M Mode: Motorola MPC 850/860
PowerQUICC and PowerPC 80x/82x
C Mode: De-multiplexed address and data
buses for Intel i960
®
, DSPs, custom ASICs
and FPGAs, and others
J Mode: Multiplexed address and data
buses for Intel i960, IBM PowerPC 401, IDT
RC32364, DSPs, IOP 480, and others
32-bit, 66MHz operation
Zero wait state bursts to 264 MB/s
3.3V I/O, 5V tolerant
Asynchronous clock inputs to PCI
and local bus
32-bit, 66MHz
Local Bus
MPC860 SDRAM Flash
PCI 9656
EEPROM
J 2
J 1
64-bit, 66MHz PCI Bus
1
2
IDMA DMA 0
DMA 1
COM 1
COM 2
COM N
2
PCI 9656 Applications
Motorola PowerQUICC Designs
The PCI 9656 is ideal for MPC 850/860-based
PowerQUICC designs. Targeted datacom and
telecom applications include high-speed
routers/switches, Frame Relay adapters,
WAN/LAN controllers, and modem cards.
The PCI 9656 simplifies these designs by
providing an enhanced direct-connect inter-
face to the PowerQUICC processor family.
The flexible 3.3V, 5V tolerant I/O buffers,
combined with local bus operation up to
66MHz, are ideally suited for current and
future PowerQUICC processors.
The PCI 9656 supports the PowerQUICC
IDMA channels for data transfer between
the integrated PowerQUICC communication
channels and PCI.
In addition, the PCI 9656 exploits PLX’s
leading edge Data Pipe Architecture technol-
ogy, allowing unlimited bursts, as illustrated
in the figure below.
For PowerQUICC IDMA operation,
the PCI 9656 transfers data to the PCI
bus under the control of the IDMA
handshake protocol using Direct
Master transfers.
Simultaneously, the two PCI 9656
DMA channels run as masters on both
buses to perform bi-directional data
transfers between the local bus and
the PCI bus.
This is a prime example of how the PCI 9656
gives PowerQUICC designers greater flexibil-
ity in implementing multiple simultaneous
I/O transfers.
Generic 32-bit, 66MHz Local Bus Designs
The PCI 9656 also supports two generic
de facto standard bus interfaces, one with
demultiplexed and the other with multi-
plexed address and data busses. Because of
their high speed and relative simplicity, these
C and J bus modes have been embraced by
designers of a wide variety of devices
including processors, DSPs, memories,
custom ASICs, and FPGAs.
CompactPCI Adapters
The PCI 9656 is the ideal choice for
CompactPCI adapters in industrial, telecom,
and networking applications. These applica-
tions include WAN/LAN controllers,
modem cards, Frame Relay adapters, and
telephony cards for telecom switches and
remote-access systems.
The PCI 9656 has integrated key features
to enable live insertion and extraction of
CompactPCI Hot Swap adapters. The PCI
9656 is PICMG 2.1 r2.0 Hot Swap Silicon,
supporting Programming Interface 0 (PI=0).
It includes Bias Voltage and Early Power
support for ease of Hot Swap board design.
Further, the PCI 9656 includes an option to
suppress PCI target retries during chip ini-
tialization, providing the optimal behavior
for live insertion in Hot Swap systems.
The PCI 9656, with its internal PCI arbiter,
reset signal direction control, and Type 0/1
PCI configuration support, is
ideal for CompactPCI system cards.
PCI Adapters
The PCI 9656 is also designed for traditional
PCI adapter card applications requiring 64-bit,
66MHz PCI operation and bandwidth.
Specific applications are high performance
communications, networking, disk control,
RAID, and data encryption adapters.
Today, Power Management and Green
PCs are major initiatives in traditional PCI
applications. The PCI 9656 supports PCI
power management, including generation
of PME in the D3COLD state. This is a
requirement for modem and communica-
tions adapters in Windows desktop and
server systems..
Embedded Host Designs
I/O intensive embedded host designs are
another major application of the PCI 9656.
These applications include network
switches/routers, printer engines, set-top
boxes, CompactPCI system cards, and
industrial equipment.
While the support requirements of these
embedded host designs share many similari-
ties with peripheral card designs, there are
three significant differences:
A host must configure the PCI bus. The
PCI 9656 supports PCI Type 0 and Type
1 configuration cycles.
A host must provide a PCI bus arbiter.
The PCI 9656 arbiter supports seven exter-
nal PCI masters, enough for a CompactPCI
backplane with 7 peripheral slots.
For hosts, the directions of reset and inter-
rupt signals reverse. The PCI 9656 includes
a strapping option to accomplish this. In
one setting, the directions are appropriate
for a peripheral. In the other, they are
appropriate for a host.
PCI 9656 PowerQUICC
CompactPCI Adapter
2
1
Dir. Slave Read
FIFOs
PCI Bus
State
Machines
Local Bus
State
Machines
Local Bus
Interface
Dynamic Bus
Width (8-, 16-,
or 32-bit)
Endian
Conversion
Muxed or
non-Muxed
Address/Data
Buses
Control Logic
64-bit, 66MHz PCI Bus
32-bit, 66MHz Local Bus
PCI Master
(For DMA
Ch 0/1 Xfers)
PCI Master
(For Direct
Master Xfers)
Local Slave
(For Direct
Master Xfers)
Local Master
(For DMA
Ch 0/1 Xfers)
Direct SlaveI20 Messaging DMA
PCI Target
(For Direct
Slave Xfers)
DMA Channel 0
DMA Channel 1
Direct Master Write
Direct Master Read
Direct Slave Read Local Master
(For Direct
Slave Xfers)
Configuration
Registers
PCI Bus
Local Bus
DMA
I2O
Run-Time
PCI Bus
Interface
PCI
Arbiter
Direct Master
EEPROM
Interrupts Power ManagementHot Swap
Direct Slave Write
Serial EEPROM
– User-specified
register
initialzation
values
Vital Product
Data
PLX Technology, Inc.
870 Maude Ave.
Sunnyvale, CA 94085 USA
Tel: 1-800-759-3735
Tel: 1-408-774-9060
Fax: 1-408-774-2169
Email: info@plxtech.com
Web Site: www.plxtech.com
©
2002 by PLX Technology, Inc. All rights reserved. PLX and Data Pipe Architecture are trademarks of PLX Technology, Inc. All oth er product names that appear in this material are for identification purposes only and are acknowledged to be
trademarks or registered trademarks of their respective companies. Information supplied by PLX is believed to be accurate and r eliable, but PLX Technology, Inc. assumes no responsibility for any errors that may appear in this material. PLX
Technology, Inc. reserves the right, without notice, to make changes in product design or specification.
PLX recognizes that software often repre-
sents the largest investment in development.
The PCI 9656 is fully compliant with PLX’s
SDK-LITE and SDK-PRO which enable quick
and easy development of high performance
local processor and host PCI software
through standard APIs, I 2O messaging pro-
tocols, PCI debug tools, and sample drivers.
Product Ordering Information
64-bit, 66 MHz PCI Bus Mastering I/O Accelerator for PowerQUICC PCI 9656-BA66BI G
and Generic 32-bit, 66MHz Bus Based Designs (Lead-Free)
64-bit, 66 MHz PCI Bus Mastering I/O Accelerator for PowerQUICC PCI 9656-BA66BI
and Generic 32-bit, 66MHz Bus Based Designs
CompactPCI 9656RDK-860 CompactPCI 9656 Rapid Development Kit with Motorola MPC860
PowerQUICC CPU and communications channels
SDK-LITE Windows Host-Side Software Development Kit
for PLX I/O Accelerators and I/O Processors
SDK-PRO Windows Host-Side and Local-Side Software Development Kit
for PLX I/O Accelerators and I/O Processors
PCI 9656RDK-LITE PCI 9656 Rapid Development Kit with prototyping area
for generic Local Bus designs
Development Tools Support
To minimize risk and lower your product
development costs, PLX offers Software
Development Kits (SDKs) and Rapid
Development Kits (RDKs) that support the
PCI 9656. These kits enable designers to
quickly bring new designs to production.
PCI 9656 design support is provided
through RDKs that include a robust PCI
development platform, complete with
OrCAD schematics, documentation, a
PCI 9656 chip sample, and software.
9656-SIL-PB-P1-1.0 2/02 3K
PCI 9656 Internal Block Diagram

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