CY7C1350G Datasheet by Cypress Semiconductor Corp

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CY7C1350G
4-Mbit (128K × 36) Pipelined SRAM
with NoBL™ Architecture
Cypress Semiconductor Corporation 198 Champion Court San Jose,CA 95134-1709 408-943-2600
Document Number: 38-05524 Rev. *S Revised April 3, 2019
4-Mbit (128K × 36) Pipelined SRAM with NoBL™ Architectur e
Features
Pin compatible and functionally equivalent to ZBT™ devices
Internally self-timed output buffer control to eliminate the need
to use OE
Byte write capability
128K × 36 common I/O architecture
3.3 V power supply (VDD)
2.5 V/3.3 V I/O power supply (VDDQ)
Fast clock-to-output times
2.8 ns (for 200 MHz device)
Clock enable (CEN) pin to suspend operation
Synchronous self-timed writes
Asynchronous output enable (OE)
Available in Pb-free 100-pin TQFP package, Pb-free and
non Pb-free 119-ball BGA package
Burst capability – linear or interleaved burst order
“ZZ” sleep mode option
Functional Description
The CY7C1350G is a 3.3 V, 128K × 36 synchronous-pipelined
burst SRAM designed specifically to support unlimited true
back-to-back read/write operations without the insertion of wait
states. The CY7C1350G is equipped with the advanced No Bus
Latency™ (NoBL™) logic required to enable consecutive
read/write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of the
SRAM, especially in systems that require frequent write/read
transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which, when
deasserted, suspends operation and extends the previous clock
cycle. Maximum access delay from the clock rise is 2.8 ns
(200-MHz device).
Write operations are controlled by the four byte write select
(BW[A:D]) and a write enable (WE) input. All writes are conducted
with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. In order to avoid bus
contention, the output drivers are synchronously tri-stated during
the data portion of a write sequence.
For a complete list of related documentation, click here.
A0, A1, A
C
MODE
BW
A
BW
B
WE
CE1
CE2
CE3
OE READ LOGIC
DQs
DQP
A
DQP
B
DQP
C
DQP
D
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
MEMORY
ARRAY
E
E
INPUT
REGISTER 0
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1 WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC A0'
A1'
D1
D0 Q1
Q0
A0
A1
C
ADV/LD
ADV/LD
E
INPUT
REGISTER 1
S
E
N
S
E
A
M
P
S
E
CLK
CEN
WRITE
DRIVERS
BW
C
BW
D
ZZ
SLEEP
CONTROL
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
Logic Block Diagram
Errata: For information on silicon errata, see "Errata" on page 19. Details include trigger conditions, devices affected, and proposed workaround.
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CY7C1350G
Document Number: 38-05524 Rev. *S Page 2 of 22
Contents
Selection Guide ................................................................ 3
Pin Configurations ........................................................... 3
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 6
Single Read Accesses ................................................ 6
Burst Read Accesses .................................................. 6
Single Write Accesses ................................................. 6
Burst Write Accesses .................................................. 6
Sleep Mode ................................................................. 6
Interleaved Burst Address Table ................................. 7
Linear Burst Address Table ......................................... 7
ZZ Mode Electrical Characteristics .............................. 7
Truth Table ........................................................................ 8
Partial Truth Table for Read/Write .................................. 9
Maximum Ratings ........................................................... 10
Operating Range ............................................................. 10
Electrical Characteristics ............................................... 10
Capacitance .................................................................... 11
Thermal Resistance ........................................................ 11
AC Test Loads and Waveforms ..................................... 11
Switching Characteristics .............................................. 12
Switching Waveforms .................................................... 13
Ordering Information ...................................................... 15
Ordering Code Definitions ......................................... 15
Package Diagrams .......................................................... 16
Acronyms ........................................................................ 18
Document Conventions ................................................. 18
Units of Measure ....................................................... 18
Errata ............................................................................... 19
Part Numbers Affected .............................................. 19
Product Status ........................................................... 19
Ram9 NoBL ZZ Pin Issues Errata Summary ............. 19
Document History Page ................................................. 20
Sales, Solutions, and Legal Information ...................... 22
Worldwide Sales and Design Support ....................... 22
Products .................................................................... 22
PSoC® Solutions ...................................................... 22
Cypress Developer Community ................................. 22
Technical Support ..................................................... 22
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CY7C1350G
Document Number: 38-05524 Rev. *S Page 3 of 22
Selection Guide
Description 200 MHz 133 MHz Unit
Maximum access time 2.8 4.0 ns
Maximum operating current 265 225 mA
Maximum CMOS standby current 40 40 mA
Pin Configurations
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout [1]
A
A
A
A
A1
A0
NC/288M
NC/144M
VSS
VDD
NC/36M
A
A
A
A
A
A
DQPB
DQB
DQB
VDDQ
VSS
DQB
DQB
DQB
DQB
VSS
VDDQ
DQB
DQB
VSS
NC
VDD
DQA
DQA
VDDQ
VSS
DQA
DQA
DQA
DQA
VSS
VDDQ
DQA
DQA
DQPA
DQPC
DQC
DQC
VDDQ
VSS
DQC
DQC
DQC
DQC
VSS
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSS
DQD
DQD
DQD
DQD
VSS
VDDQ
DQD
DQD
DQPD
A
A
CE1
CE2
BWD
BWC
BWB
BWA
CE3
VDD
VSS
CLK
WE
CEN
OE
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
ADV/LD
ZZ
MODE
NC/72M
NC/18M
NC/9M
CY7C1350G
BYTE B
BYTE A
BYTE C
BYTE D
Note
1. Errata: The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see "Errata" on page 19.
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CY7C1350G
Document Number: 38-05524 Rev. *S Page 4 of 22
Figure 2. 119-Ball BGA (14 × 22 × 2.4 mm) pinout [2]
Pin Configurations (continued)
Note
2. Errata: The ZZ ball (T7) needs to be externally connected to ground. For more information, see "Errata" on page 19.
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CY7C1350G
Document Number: 38-05524 Rev. *S Page 5 of 22
Pin Definitions
Name I/O Description
A0, A1, A Input-
synchronous
Address inputs used to select one of the 128K address locations. Sampled at the rising edge of the
CLK. A[1:0] are fed to the two-bit burst counter.
BW[A:D] Input-
synchronous
Byte write inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising
edge of CLK.
WE Input-
synchronous
Write enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal
must be asserted LOW to initiate a write sequence.
ADV/LD Input-
synchronous
Advance/load input. Used to advance the on-chip address counter or load a new address. When HIGH
(and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be
loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to
load a new address.
CLK Input-clock Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is
only recognized if CEN is active LOW.
CE1Input-
synchronous
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
and CE3 to select/deselect the device.
CE2Input-
synchronous
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
and CE3 to select/deselect the device.
CE3Input-
synchronous
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
and CE2 to select/deselect the device.
OE Input-
asynchronous
Output enable, asynchronous input, active LOW. Combined with the synchronous logic block inside
the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as
outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during
the data portion of a write sequence, during the first clock when emerging from a deselected state, when
the device has been deselected.
CEN Input-
synchronous
Clock enable input, active LOW. When asserted LOW the Clock signal is recognized by the SRAM.
When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device,
CEN can be used to extend the previous cycle when required.
ZZ[3] Input-
asynchronous
ZZ “sleep” input. This active HIGH input places the device in a non-time critical “sleep” condition with
data integrity preserved. During normal operation, this pin has to be low or left floating. ZZ pin has an
internal pull-down.
DQs I/O-
synchronous
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
address during the clock rise of the read cycle. The direction of the pins is controlled by OE and the
internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQs and
DQPX are placed in a tristate condition. The outputs are automatically tri-stated during the data portion of
a write sequence, during the first clock when emerging from a deselected state, and when the device is
deselected, regardless of the state of OE.
DQP[A:D] I/O-
synchronous
Bidirectional data parity I/O lines. Functionally, these signals are identical to DQs. During write
sequences, DQP[A:D] is controlled by BW[A:D] correspondingly.
MODE Input
strap pin
Mode input. Selects the burst order of the device. When tied to GND selects linear burst sequence.
When tied to VDD or left floating selects interleaved burst sequence.
VDD Power supply Power supply inputs to the core of the device.
VDDQ I/O power
supply
Power supply for the I/O circuitry.
VSS Ground Ground for the device.
NC No Connects. Not internally connected to the die. 9M, 18M, 36M, 72M, 144M and 288M are address
expansion pins in this device and will be used as address pins in their respective densities.
Note
3. Errata: The ZZ pin needs to be externally connected to ground. For more information, see "Errata" on page 19.
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CY7C1350G
Document Number: 38-05524 Rev. *S Page 6 of 22
Functional Overview
The CY7C1350G is a synchronous-pipelined burst SRAM
designed specifically to eliminate wait states during write/read
transitions. All synchronous inputs pass through input registers
controlled by the rising edge of the clock. The clock signal is
qualified with the clock enable input signal (CEN). If CEN is
HIGH, the clock signal is not recognized and all internal states
are maintained. All synchronous operations are qualified with
CEN. All data outputs pass through output registers controlled by
the rising edge of the clock. Maximum access delay from the
clock rise (tCO) is 2.8 ns (200 MHz device).
Accesses can be initiated by asserting all three chip enables
(CE1, CE2, CE3) active at the rising edge of the clock. If clock
enable (CEN) is active LOW and ADV/LD is asserted LOW, the
address presented to the device will be latched. The access can
either be a read or write operation, depending on the status of
the write enable (WE). BW[A:D] can be used to conduct byte write
operations.
Write operations are qualified by the write enable (WE). All writes
are simplified with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
should be driven LOW once the device has been deselected in
order to load a new address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, (3) the write enable input signal
WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The
address presented to the address inputs is latched into the
address register and presented to the memory core and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the input
of the output register. At the rising edge of the next clock the
requested data is allowed to propagate through the output
register and onto the data bus, provided OE is active LOW. After
the first clock of the read access the output buffers are controlled
by OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. During the
second clock, a subsequent operation (read/write/deselect) can
be initiated. Deselecting the device is also pipelined. Therefore,
when the SRAM is deselected at clock rise by one of the chip
enable signals, its output will tristate following the next clock rise.
Burst Read Accesses
The CY7C1350G has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to four
reads without reasserting the address inputs. ADV/LD must be
driven LOW in order to load a new address into the SRAM, as
described in Single Read Accesses. The sequence of the burst
counter is determined by the MODE input signal. A LOW input
on MODE selects a linear burst mode, a HIGH selects an inter-
leaved burst sequence. Both burst counters use A0 and A1 in the
burst sequence, and will wrap around when incremented suffi-
ciently. A HIGH input on ADV/LD will increment the internal burst
counter regardless of the state of chip enables inputs or WE. WE
is latched at the beginning of a burst cycle. Therefore, the type
of access (read or write) is maintained throughout the burst
sequence.
Single Write Accesses
Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, and (3) the write signal WE is
asserted LOW. The address presented to the address inputs is
loaded into the address register. The write signals are latched
into the control logic block.
On the subsequent clock rise the data lines are automatically
tri-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQs and
DQP[A:D]. In addition, the address for the subsequent access
(read/write/deselect) is latched into the address register
(provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQs and DQP[A:D]
(or a subset for byte write operations, see Write Cycle
Description table for details) inputs is latched into the device and
the write is complete.
The data written during the write operation is controlled by
BW[A:D] signals. The CY7C1350G provides byte write capability
that is described in the Write Cycle Description table. Asserting
the write enable input (WE) with the selected byte write select
(BW[A:D]) input will selectively write to only the desired bytes.
Bytes not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has been
provided to simplify the write operations. Byte write capability
has been included in order to greatly simplify read/modify/write
sequences, which can be reduced to simple byte write
operations.
Because the CY7C1350G is a common I/O device, data should
not be driven into the device while the outputs are active. The
output enable (OE) can be deasserted HIGH before presenting
data to the DQs and DQP[A:D] inputs. Doing so will tristate the
output drivers. As a safety precaution, DQs and DQP[A:D] are
automatically tri-stated during the data portion of a write cycle,
regardless of the state of OE.
Burst Write Accesses
The CY7C1350G has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to four
write operations without reasserting the address inputs. ADV/LD
must be driven LOW in order to load the initial address, as
described in Single Write Accesses. When ADV/LD is driven
HIGH on the subsequent clock rise, the chip enables (CE1, CE2,
and CE3) and WE inputs are ignored and the burst counter is
incremented. The correct BW[A:D] inputs must be driven in each
cycle of the burst write in order to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleepmode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE1, CE2,
and CE3, must remain inactive for the duration of tZZREC after the
ZZ input returns LOW.
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CY7C1350G
Document Number: 38-05524 Rev. *S Page 7 of 22
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Linear Burst Address Table
(MODE = GND)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min Max Unit
IDDZZ Snooze mode standby current ZZ > VDD 0.2 V 40 mA
tZZS Device operation to ZZ ZZ > VDD 0.2 V 2tCYC ns
tZZREC ZZ recovery time ZZ < 0.2 V 2tCYC –ns
tZZI ZZ active to snooze current This parameter is sampled 2tCYC ns
tRZZI ZZ inactive to exit snooze current This parameter is sampled 0 ns
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CY7C1350G
Document Number: 38-05524 Rev. *S Page 8 of 22
Truth Table
The Truth Table for part CY7C1350G is as follows. [4, 5, 6, 7, 8, 9, 10]
Operation Address Used CE ZZ ADV/LD WE BWxOE CEN CLK DQ
Deselect cycle None H L L X X X L L–H Tristate
Continue deselect cycle None X L H X X X L L–H Tristate
Read cycle (begin burst) External L L L H X L L L–H Data out (Q)
Read cycle (continue burst) Next X L H X X L L L–H Data out (Q)
NOP/dummy read (begin burst) External L L L H X H L L–H Tristate
Dummy read (continue burst) Next X L H X X H L L–H Tristate
Write cycle (begin burst) External L L L L L X L L–H Data in (D)
Write cycle (continue burst) Next X L H X L X L L–H Data in (D)
NOP/WRITE ABORT (begin burst) None L L L L H X L L–H Tristate
WRITE ABORT (continue burst) Next X L H X H X L L–H Tristate
IGNORE CLOCK EDGE (stall) Current X L X X X X H L–H
SNOOZE MODE None XH X XXXX X Tristate
Notes
4. X =”Don't Care.” H = Logic HIGH, L = Logic LOW. CE stands for all chip enables active. BWx = L signifies at least one byte write select is active, BWx = valid signifies
that the desired byte write selects are asserted, see Write Cycle Description table for details.
5. Write is defined by BWX, and WE. See Write Cycle Descriptions table.
6. When a write cycle is detected, all DQs are tri-stated, even during byte writes.
7. The DQ and DQP pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
8. CEN = H, inserts wait states.
9. Device will power-up deselected and the DQs in a tristate condition, regardless of OE.
10. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP[A:D] = tristate when OE is
inactive or when the device is deselected, and DQs and DQP[A:D] = data when OE is active.
CYPRESS mm“, mmmw — :Lag GH,L ‘fl’ ‘92
CY7C1350G
Document Number: 38-05524 Rev. *S Page 9 of 22
Partial Truth Table for Read/Write
The Partial Truth Table for read or write for part CY7C1350G is as follows. [11, 12, 13]
Function WE BWDBWCBWBBWA
Read H X X X X
Write no bytes written L H H H H
Write byte A(DQA and DQPA)LHHHL
Write byte B(DQB and DQPB)LHHLH
Write bytes A, B L H H L L
Write byte C (DQC and DQPC)LHLHH
Write bytes C, A L H L H L
Write bytes C, B L H L L H
Write bytes C, B, A L H L L L
Write byte D(DQD and DQPD)LLHHH
Write bytes D, A L L H H L
Write bytes D, B L L H L H
Write bytes D, B, A L L H L L
Write bytes D, C L L L H H
Write bytes D, C, A L L L H L
Write bytes D, C, B L L L L H
Write all bytes LLLLL
Notes
11. X =”Don't Care.” H = Logic HIGH, L = Logic LOW. CE stands for all chip enables active. BWx = L signifies at least one byte write select is active, BWx = valid signifies
that the desired byte write selects are asserted, see Write Cycle Description table for details.
12. Write is defined by BWX, and WE. See Write Cycle Descriptions table.
13. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done on which byte write is active.
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CY7C1350G
Document Number: 38-05524 Rev. *S Page 10 of 22
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature 65 °C to +150 °C
Ambient temperature with
power applied 55 °C to +125 °C
Supply voltage on VDD relative to GND  0.5 V to +4.6 V
Supply voltage on VDDQ relative to GND 0.5 V to +VDD
DC voltage applied to outputs
in tristate  0.5 V to VDDQ + 0.5 V
DC input voltage  0.5 V to VDD + 0.5 V
Current into outputs (LOW) ........................................ 20 mA
Static discharge voltage
(per MIL-STD-883, method 3015) .......................... > 2001 V
Latch-up current .................................................... > 200 mA
Operating Range
Range Ambient
Temperature (TA)VDD VDDQ
Commercial 0 °C to +70 °C 3.3 V 5% /
+ 10%
2.5 V 5% to
VDD
Industrial 40 °C to +85 °C
Electrical Characteristics
Over the Operating Range
Parameter [14, 15] Description Test Conditions Min Max Unit
VDD Power supply voltage 3.135 3.6 V
VDDQ I/O supply voltage 2.375 VDD V
VOH Output HIGH voltage for 3.3 V I/O, IOH =4.0 mA 2.4 V
for 2.5 V I/O, IOH =1.0 mA 2.0 V
VOL Output LOW voltage for 3.3 V I/O, IOL=8.0 mA 0.4 V
for 2.5 V I/O, IOL=1.0 mA 0.4 V
VIH Input HIGH voltage [14] VDDQ = 3.3 V 2.0 VDD + 0.3 V V
VDDQ = 2.5 V 1.7 VDD + 0.3 V V
VIL Input LOW voltage [14] VDDQ = 3.3 V –0.3 0.8 V
VDDQ = 2.5 V –0.3 0.7 V
IXInput leakage current except ZZ
and MODE
GND VI VDDQ 55A
Input current of MODE Input = VSS 30 A
Input = VDD –5A
Input current of ZZ Input = VSS –5 A
Input = VDD –30A
IOZ Output leakage current GND VI VDDQ, output disabled 55A
IDD VDD operating supply current VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
5-ns cycle,
200 MHz
–265mA
7.5-ns cycle,
133 MHz
–225mA
ISB1 Automatic CE power-down
current – TTL inputs
VDD = Max, device deselected,
VIN VIH or VIN VIL
f = fMAX = 1/tCYC
5-ns cycle,
200 MHz
–110mA
7.5-ns cycle,
133 MHz
–90mA
ISB2 Automatic CE power-down
current – CMOS inputs
VDD = Max, device deselected,
VIN 0.3 V or VIN > VDDQ 0.3 V,
f = 0
All speeds 40 mA
Notes
14. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2).
15. TPower-up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
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CY7C1350G
Document Number: 38-05524 Rev. *S Page 11 of 22
ISB3 Automatic CE power-down
current – CMOS inputs
VDD = Max, device deselected,
VIN 0.3 V or VIN > VDDQ 0.3 V,
f = fMAX = 1/tCYC
5-ns cycle,
200 MHz
–95mA
7.5-ns cycle,
133 MHz
–75mA
ISB4 Automatic CE power-down
current – TTL inputs
VDD = Max, device deselected,
VIN VIH or VIN VIL, f = 0
All speeds 45 mA
Electrical Characteristics (continued)
Over the Operating Range
Parameter [14, 15] Description Test Conditions Min Max Unit
Capacitance
Parameter [16] Description Test Conditions 100-pin TQFP
Max
119-ball BGA
Max Unit
CIN Input capacitance TA = 25 °C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 3.3 V
55pF
CCLK Clock input capacitance 5 5 pF
CI/O Input/Output capacitance 5 7 pF
Thermal Resistance
Parameter [16] Description Test Conditions 100-pin TQFP
Package
119-ball BGA
Package Unit
JA Thermal resistance
(junction to ambient)
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51.
30.32 34.1 °C/W
JC Thermal resistance
(junction to case)
6.85 14.0 °C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
OUTPUT
R = 317
R = 351
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT
RL= 50
Z0= 50
VT= 1.5 V
3.3 V ALL INPUT PULSES
VDDQ
GND
90%
10%
90%
10%
1 ns 1 ns
(c)
OUTPUT
R = 1667
R =1538
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT
RL= 50
Z0= 50
VT= 1.25 V
2.5 V ALL INPUT PULSES
VDDQ
GND
90%
10%
90%
10%
1 ns 1 ns
(c)
3.3 V I/O Test Load
2.5 V I/O Test Load
Note
16. Tested initially and after any design or process changes that may affect these parameters.
aCYPRESS' ' manna: mlanRRaw [2o 21 22] [20 21,22] Z [20, 21, 22] [20 21,22]
CY7C1350G
Document Number: 38-05524 Rev. *S Page 12 of 22
Switching Characteristics
Over the Operating Range
Parameter [17, 18] Description -200 -133 Unit
Min Max Min Max
tPOWER VDD(typical) to the first access [19] 1 – 1 – ms
Clock
tCYC Clock cycle time 5.0 7.5 ns
tCH Clock HIGH 2.0 3.0 ns
tCL Clock LOW 2.0 3.0 ns
Output Times
tCO Data output valid after CLK rise 2.8 4.0 ns
tDOH Data output hold after CLK rise 1.0 1.5 ns
tCLZ Clock to low Z [20, 21, 22] 0 – 0 – ns
tCHZ Clock to high Z [20, 21, 22] 2.8 4.0 ns
tOEV OE LOW to output valid 2.8 4.0 ns
tOELZ OE LOW to output low Z [20, 21, 22] 0 – 0 – ns
tOEHZ OE HIGH to output high Z [20, 21, 22] 2.8 4.0 ns
Setup Times
tAS Address setup before CLK rise 1.2 1.5 ns
tALS ADV/LD setup before CLK rise 1.2 1.5 ns
tWES GW, BWX setup before CLK rise 1.2 1.5 ns
tCENS CEN setup before CLK rise 1.2 1.5 ns
tDS Data input setup before CLK rise 1.2 1.5 ns
tCES Chip enable setup before CLK rise 1.2 1.5 ns
Hold Times
tAH Address hold after CLK rise 0.5 0.5 ns
tALH ADV/LD hold after CLK rise 0.5 0.5 ns
tWEH GW, BWX hold after CLK rise 0.5 0.5 ns
tCENH CEN hold after CLK rise 0.5 0.5 ns
tDH Data input hold after CLK rise 0.5 0.5 ns
tCEH Chip enable hold after CLK rise 0.5 0.5 ns
Notes
17. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.
18. Test conditions shown in (a) of Figure 3 on page 11 unless otherwise noted.
19. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a Read or Write operation can
be initiated.
20. tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 3 on page 11. Transition is measured ±200 mV from steady-state voltage.
21. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
tristate prior to low Z under the same system conditions.
22. This parameter is sampled and not 100% tested.
CY7C1350G
Document Number: 38-05524 Rev. *S Page 13 of 22
Switching Waveforms
Figure 4. Read/Write Timing [23, 24, 25]
WRITE
D(A1)
123456789
CLK
tCYC
t
CL
t
CH
10
CE
t
CEH
t
CES
WE
CEN
t
CENH
t
CENS
BW[A:D]
ADV/LD
t
AH
t
AS
ADDRESS A1 A2 A3 A4 A5 A6 A7
t
DH
t
DS
Data
In-Out (DQ)
t
CLZ
D(A1) D(A2) D(A5)Q(A4)Q(A3)
D(A2+1)
t
DOH
t
CHZ
t
CO
WRITE
D(A2) BURST
WRITE
D(A2+1)
READ
Q(A3) READ
Q(A4) BURST
READ
Q(A4+1)
WRITE
D(A5) READ
Q(A6) WRITE
D(A7) DESELECT
OE
t
OEV
t
OELZ
t
OEHZ
t
DOH
DON’T CARE UNDEFINED
Q(A6)
Q(A4+1)
Notes
23. For this waveform ZZ is tied LOW.
24. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
25. Order of the burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
A V.‘ lm‘ ‘ a V ’%:m:/ ‘ A A l//;
CY7C1350G
Document Number: 38-05524 Rev. *S Page 14 of 22
Figure 5. NOP, STALL, and DESELECT Cycles [26, 27, 28]
Figure 6. ZZ Mode Timing [29, 30]
Switching Waveforms (continued)
READ
Q(A3)
45678910
CLK
CE
WE
CEN
BW
[A:D]
ADV/LD
ADDRESS A3 A4 A5
D(A4)
Data
In-Out (DQ)
A1
Q(A5)
WRITE
D(A4) STALLWRITE
D(A1)
123
READ
Q(A2) STALL NOP READ
Q(A5) DESELECT CONTINUE
DESELECT
DON’T CARE UNDEFINED
t
CHZ
A2
D(A1) Q(A2) Q(A3)
tZZ
I
SUPPLY
CLK
ZZ
tZZREC
ALL INPUTS
(except ZZ)
DON’T CARE
IDDZZ
tZZI
tRZZI
Outputs (Q)
High-Z
DESELECT or READ Only
Notes
26. For this waveform ZZ is tied LOW.
27. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
28. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.
29. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
30. DQs are in high Z when exiting ZZ sleep mode.
CY7C1350G
Document Number: 38-05524 Rev. *S Page 15 of 22
Ordering Code Definitions
Ordering Information
The following table contains only the list of parts that are currently available. If you do not see what you are looking for, contact your
local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary
page at http://www.cypress.com/products.
Cypress maintains a worldwide network of offices, solution centers, manufacturers representatives and distributors. To find the
office closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz) Ordering Code
Package
Diagram Package Type Operating
Range
133 CY7C1350G-133AXC 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free Commercial
CY7C1350G-133AXI 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free Industrial
200 CY7C1350G-200AXC 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free Commercial
Temperature Range: X = C or I
C = Commercial; I = Industrial
Pb-free
Package Type: XX = A or BG
A = 100-pin TQFP; BG = 119-ball BGA
Speed Grade: XXX = 133 MHz or 200 MHz
Process Technology: G 90 nm
Part Identifier: 1350 = PL, 128Kb × 36 (4Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
C 1350 G - XXX X XCY 7XX
‘CYPRESS' ' manna: mmmw LE sans: PLhNE m in m mmmmmmm A, a x V“ E E [h an“ ’5; wwmmummm :x a: mu vxzu SYANDrDVV in mm A sun: vxEv :5: mm A
CY7C1350G
Document Number: 38-05524 Rev. *S Page 16 of 22
Package Diagrams
Figure 7. 100-pin TQFP (16 × 22 × 1.6 mm) Package Outline, 51-85050
ș
ș1
ș2
NOTE:
3. JEDEC SPECIFICATION NO. REF: MS-026.
2. BODY LENGTH DIMENSION DOES NOT
MOLD PROTRUSION/END FLASH SHALL
1. ALL DIMENSIONS ARE IN MILLIMETERS.
BODY SIZE INCLUDING MOLD MISMATCH.
L11.00 REF
L
c
0.45 0.60 0.75
0.20
NOM.MIN.
D1
R2
E1
E
0.08
D
2
A
A
1
A
1.35 1.40
SYMBOL MAX.
0.20
1.45
1.60
0.15
ș
b0.22 0.30 0.38
e0.65 TYP
DIMENSIONS
1
R0.08
L20.25 BSC
0.05
0.20
INCLUDE MOLD PROTRUSION/END FLASH.
15.80 16.00 16.20
13.90 14.00 14.10 NOT EXCEED 0.0098 in (0.25 mm) PER SIDE.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC
21.80 22.00 22.20
19.90 20.00 20.10
L30.20
ș1
11° 13°ș212°
51-85050 *G
EMPRESS ' EMIEunmmlnNannaw Macaw? u Linux) EEF ‘0 75k“ ‘50le ‘ fl ' (900 God A E 73900 000 a c 000 000 c a 000 DOC a E 000 000 E F 000 000 F S o 000 ooo G J a ooo ooo H a J i : Coo ooo K M N 000 000 l N ooo ooo M p ooo ooo N , ooo 000 p R GOO 000 w L 000 000 , ooo ooo u ~ mm H -~ 8 m “' 5 mm 3 I IE ”mm B , ~ E: A 1 E “mmzmfi_mm saws pwz NOTE: Fuckug: Wexght' 5:2 Cypress Puckuq: Mounm Doommuon Dntasheu (won) posted an the Cypress web,
CY7C1350G
Document Number: 38-05524 Rev. *S Page 17 of 22
Figure 8. 119-ball BGA (14 × 22 × 2.4 mm) Package Outline, 51-85115
Package Diagrams
51-85115 *D
nnnnnnnnnnnnnnnnnn
CY7C1350G
Document Number: 38-05524 Rev. *S Page 18 of 22
Acronyms Document Conventions
Units of Measure
Acronym Description
BGA Ball Grid Array
CE Chip Enable
CEN Clock Enable
CMOS Complementary Metal Oxide Semiconductor
EIA Electronic Industries Alliance
I/O Input/Output
JEDEC Joint Electron Devices Engineering Council
NoBL No Bus Latency
OE Output Enable
SRAM Static Random Access Memory
TQFP Thin Quad Flat Pack
TTL Transistor-Transistor Logic
WE Write Enable
Symbol Unit of Measure
°C degree Celsius
MHz megahertz
µA microampere
mA milliampere
mm millimeter
ms millisecond
mV millivolt
nm nanometer
ns nanosecond
ohm
% percent
pF picofarad
Vvolt
Wwatt
CY7C1350G
Document Number: 38-05524 Rev. *S Page 19 of 22
Errata
This section describes the Ram9 NoBL ZZ pin issue. Details include trigger conditions, the devices affected, proposed workaround
and silicon revision applicability. Please contact your local Cypress sales representative if you have further questions.
Part Numbers Affected
Product Status
All of the devices in the Ram9 4Mb NoBL family are qualified and available in production quantities.
Ram9 NoBL ZZ Pin Issues Errata Summary
The following table defines the errata applicable to available Ram9 4Mb NoBL family devices.
1. ZZ Pin Issue
PROBLEM DEFINITION
The problem occurs only when the device is operated in the normal mode with ZZ pin left floating. The ZZ pin on the SRAM
device does not have an internal pull-down resistor. Switching noise in the system may cause the SRAM to recognize a HIGH
on the ZZ input, which may cause the SRAM to enter sleep mode. This could result in incorrect or undesirable operation of the
SRAM.
TRIGGER CONDITIONS
Device operated with ZZ pin left floating.
SCOPE OF IMPACT
When the ZZ pin is left floating, the device delivers incorrect data.
WORKAROUND
Tie the ZZ pin externally to ground.
FIX STATUS
For the 4M Ram9 (90 nm) devices, there is no plan to fix this issue.
Density & Revision Package Type Operating Range
4Mb-Ram9 NoBL™ SRAMs: CY7C135*G 100-pin TQFP Commercial/
Industrial
119-ball BGA Commercial
Item Issues Description Device Fix Status
1. ZZ Pin When asserted HIGH, the ZZ pin places
device in a “sleep” condition with data integrity
preserved.The ZZ pin currently does not have
an internal pull-down resistor and hence
cannot be left floating externally by the user
during normal mode of operation.
4M-Ram9 (90 nm) For the 4M Ram9 (90 nm)
devices, there is no plan to fix
this issue.
CYPRESS s‘a‘us from Prelimin duress of Cypress 8 Champio me Do:
CY7C1350G
Document Number: 38-05524 Rev. *S Page 20 of 22
Document History Page
Document Title: CY7C1350G, 4-Mbit (128K × 36) Pipelined SRAM with NoBL™ Architecture
Document Number: 38-05524
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
** 224380 RKF 05/17/2004 New data sheet.
*A 276690 VBL 10/14/2004 Updated Ordering Information (Updated part numbers; added comment of
BGA Pb-free package availability below the table).
*B 332895 SYT 03/14/2005 Changed status from Preliminary to Final.
Updated Features (Removed 225 MHz and 100 MHz frequencies related
information).
Updated Selection Guide (Removed 225 MHz and 100 MHz frequencies
related information).
Updated Pin Configurations (Modified Address Expansion balls in the pinouts
for 119-ball BGA Package as per JEDEC standards).
Updated Electrical Characteristics (Updated test conditions for VOL and VOH
parameters, removed 225 MHz and 100 MHz frequencies related information).
Updated Thermal Resistance (Replaced TBD’s for JA and JC to their
respective values).
Updated Switching Characteristics (Removed 225 MHz and 100 MHz
frequencies related information).
Updated Ordering Information (Updated part numbers (By removing Shaded
Parts); changed the package name for 100-pin TQFP from A100RA to A101;
removed comment on the availability of BGA Pb-free package).
*C 351194 PCI 04/19/2005 Updated Ordering Information (Updated part numbers).
*D 419264 RXU 01/10/2006 Changed status from Preliminary to Final.
Changed address of Cypress Semiconductor Corporation from “3901 North
First Street” to “198 Champion Court”.
Updated Electrical Characteristics (Updated Note 15 (Changed test condition
from VDDQ < VDD to VDDQ < VDD), changed “Input Load Current except ZZ and
MODE” to “Input Leakage Current except ZZ and MODE”).
Updated Ordering Information:
Updated part numbers.
Removed “Package Name” column.
Added “Package Diagram” column.
Updated Package Diagrams:
spec 51-85050 – Changed revision from *A to *B.
*E 419705 RXU 01/24/2006 Added 100 MHz Frequency Range related information in all instances across
the document.
*F 480368 VKN 07/17/2006 Updated Maximum Ratings:
Added Maximum Rating for “Supply Voltage on VDDQ Relative to GND”.
Updated Ordering Information:
Updated part numbers.
*G 2896584 NJY 03/20/2010 Updated Ordering Information:
Updated part numbers.
Updated Package Diagrams:
spec 51-85050 – Changed revision from *B to *C.
spec 51-85115 – Changed revision from *B to *C.
*H 3053085 NJY 10/08/2010 Updated Ordering Information:
Updated part numbers.
Added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Minor edits.
Updated to new template.
Completing Sunset Review.
@cvpness nnnnnnnnnnnnnnnnnn
CY7C1350G
Document Number: 38-05524 Rev. *S Page 21 of 22
*I 3211361 CS 03/31/2011 Updated Ordering Information:
Updated part numbers.
*J 3353361 PRIT 08/24/2011 Updated Functional Description (Updated Note as “For best practices
recommendations, refer to SRAM System Design Guidelines.” and referred the
note in same place in the section).
Updated Package Diagrams:
spec 51-85050 – Changed revision from *C to *D.
Completing Sunset Review.
*K 3590312 NJY / PRIT 05/10/2012 Removed 250 MHz, 166 MHz and 100 MHz Frequencies Range related
information in all instances across the document.
Updated Functional Description:
Updated description (Removed the Note “For best practices
recommendations, refer to SRAM System Design Guidelines.”).
*L 3753416 PRIT 09/24/2012 Updated Package Diagrams:
spec 51-85115 – Changed revision from *C to *D.
Completing Sunset Review.
*M 3990978 PRIT 05/04/2013 Added Errata.
*N 4039645 PRIT 06/25/2013 Added Errata Footnotes.
Updated to new template.
*O 4150716 PRIT 12/13/2013 Updated Errata.
*P 4574263 PRIT 11/19/2014 Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Ordering Information:
Updated part numbers.
Updated Package Diagrams:
spec 51-85050 – Changed revision from *D to *E.
*Q 5512429 PRIT 11/07/2016 Updated Package Diagrams:
spec 51-85050 – Changed revision from *E to *F.
Updated to new template.
Completing Sunset Review.
*R 6021180 RMES 01/09/2018 Updated Package Diagrams:
spec 51-85050 – Changed revision from *F to *G.
Updated to new template.
Completing Sunset Review.
*S 6532203 RMES 04/03/2019 Updated Ordering Information:
Updated part numbers.
Updated to new template.
Document History Page (continued)
Document Title: CY7C1350G, 4-Mbit (128K × 36) Pipelined SRAM with NoBL™ Architecture
Document Number: 38-05524
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
nnnnnnnnnnnnnnnnnnn
Document Number: 38-05524 Rev. *S Revised April 3, 2019 Page 22 of 22
ZBT is a trademark of Integrated Device Technology, Inc. NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation.
CY7C1350G
© Cypress Semiconductor Corporation, 2004–2019. This document is the property of Cypress Semiconductor Corporation and its subsidiaries (“Cypress”). This document, including any software or
firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress
reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property
rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants
you a personal, non-exclusive, nontransferable license (without t he right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce
the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or
indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as provided by
Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the
Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such
as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING
CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively, “Security
Breach”). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security Breach. In
addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted
by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or
circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the
responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. “High-Risk Device”
means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other
medical devices. “Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk
Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of
a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from
and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress
product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i)
Cypress’s published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to
use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Sales, Solutions, and Legal Information
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Cypress maintains a worldwide network of offices, solution centers, manufacturers representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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Microcontrollers cypress.com/mcu
PSoC cypress.com/psoc
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Touch Sensing cypress.com/touch
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