XMC1100/1200/1300 Datasheet Addendum by Infineon Technologies

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Data Sheet Addendum
V1.0 2016-02
Microcontrollers
XMC1100 / XMC1200 /
XMC1300
Fixed Flash Wait States
XMC1000 Family
ARM® Cortex®-M0
32-bit processor core
Edition 2016-02
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2016 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
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characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
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and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
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Data Sheet Addendum
V1.0 2016-02
Microcontrollers
XMC1100 / XMC1200 /
XMC1300
Fixed Flash Wait States
XMC1000 Family
ARM® Cortex®-M0
32-bit processor core
Inhneon”
XMC1100 / XMC1200 / XMC1300
XMC1000 Family
Data Sheet Addendum V1.0, 2016-02
Trademarks
C166™, TriCore™ , XMC™ and DAVE™ are trademarks of Infineon Technologies AG.
ARM®, ARM Powered®, Cortex®, Thumb® and AMBA® are registered trademarks of
ARM, Limited.
CoreSight™, ETM™, Embedded Trace Macrocell™ and Embedded Trace Buffer™ are
trademarks of ARM, Limited.
XMC1100 / XMC1200 / XMC1300 Data Sheet Addendum
Revision History: V1.0 2016-02
Previous Version: none
Page Subjects
Initial version.
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XMC1100 / XMC1200 / XMC1300
XMC1000 Family
Table of Contents
Data Sheet Addendum 5 V1.0, 2016-02
1 Fixed Flash Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Flash read access with fixed wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2 NVM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3.1 Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table of Contents
Subject to Agreement on the Use of Product Information
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XMC1100 / XMC1200 / XMC1300
XMC1000 Family
Fixed Flash Wait States
Data Sheet Addendum 6 V1.0, 2016-02
1 Fixed Flash Wait States
The parameter limits defined in this addendum extend the electrical parameters defined
in the XMC1100 / XMC1200 / XMC1300 Data Sheet stated below.
Data Sheet AA-Step, V1.4, 2014-05
Data Sheet AB-Step, V1.6, 2015-04
1.1 Flash read access with fixed wait states
Per default the XMC1100 / XMC1200 / XMC1300 devices use a configuration with
adaptive wait states for read accesses to the flash memory, dynamically adapting to the
system frequency and flash access timing without user software interaction.
Alternatively, it is possible to configure the XMC1100 / XMC1200 / XMC1300 devices to
apply fixed wait states to each flash read access, improving determinism of program
execution from flash. The required number of wait states depends on the system
frequency fMCLK, as defined in the parameter NFWSFLASH. The number of wait states can
be configured with the bit NVM_NVMCONF.WS, the selection of adaptive or fixed wait
states is done with the bit NVM_CONFIG1.WS.
Attention: Any write operation to the register NVM_CONFIG1 to switch between
adaptive and fixed wait states configuration must only modify the bit
NVM_CONFIG1.FIXWS. Changing other bits in NVM_CONFIG1 can lead
to unpredictable results.
Attention: Before and after the fixed wait states configuration or the system
frequency fMCLK is changed, the number of selected wait states must
always comply to the parameter NFWSFLASH.
Below is a code snippet defining the register addresses, configuring one wait state and
then switching to operation with fixed wait states.
Example
// Headers and variables to fix number of wait states to "1"
#define ADDR1 0x40050008 //Address of NVM_NVMCONF
uint32_t * NVM_NVMCONF = (uint32_t *) ADDR1;
#define ADDR2 0x40050048 //Address of NVM_CONFIG1
uint32_t * NVM_CONFIG1 = (uint32_t *) ADDR2;
// init sequence to fix number of wait states to "1"
*NVM_NVMCONF = *NVM_NVMCONF | 0x1000; //Set .WS bit => 1WS
*NVM_CONFIG1 = *NVM_CONFIG1 | 0x0800; //Set .FIXWS bit => fixed
WS scheme
Subject to Agreement on the Use of Product Information
Inhneon”
XMC1100 / XMC1200 / XMC1300
XMC1000 Family
Fixed Flash Wait States
Data Sheet Addendum 7 V1.0, 2016-02
1.2 NVM Registers
NVM Configuration Register
The definition of bit NVMCONF.12 changes to NVMCONF.WS.
NVM_NVMCONF
NVM Configuration Register (4005 0008H) Reset Value: 9000H
1514131211109876543210
NVM
_ON INT_
ON 0 WS SECPROT 0 HRLEV 0
rw rw rw rw rw r rw rw
Field Bits Type Description
NVM_ON 15 rw NVM On
When cleared, no software code can be executed anymore
from the NVM, until it is set again. I.e., already the software
code that initiates the change in NVM_ON itself may not
reside in the NVM, otherwise the software is stalled forever.
0BSLEEP, NVM is switched to or stays in sleep mode.
1BNORM, NVM is switched to or stays in normal mode.
INT_ON 14 rw Interrupt On
When enabled the completion of a sequence started by
setting NVMPROG.ACTION (write or erase sequence) will
be indicated by NVM interrupt. The same is true for the
wake-up sequence.
0BINTOFF, No NVM ready interrupts are generated.
1BINTON, NVM ready interrupts are generated.
013 rw Reserved for Future Use
Must be written with 0 to allow correct operation.
WS 12 rw Number of fixed Wait States
Defines the number of fixed wait states when
NVM_CONFIG1.FIXWS = 1B.
0B0 fixed wait states.
1B1 fixed wait state.
SECPROT 11:4 rw Sector Protection1)
This field defines the number of write, erase, verify
protected sectors, starting with physical sector 0.
Subject to Agreement on the Use of Product Information
Inhneon”
XMC1100 / XMC1200 / XMC1300
XMC1000 Family
Fixed Flash Wait States
Data Sheet Addendum 8 V1.0, 2016-02
Configuration 1 Register
The bit NVM_CONFIG1.FIXWS allows to switch between adaptive and fixed wait state
configuration.
Attention: Any write operation to the register NVM_CONFIG1 to switch between
adaptive and fixed wait states configuration must only modify the bit
NVM_CONFIG1.FIXWS. Changing other bits in NVM_CONFIG1 can lead
to unpredictable results.
03r Reserved
Read as 0; should be written with 0.
HRLEV 2:1 rw Hardread Level2)
Defines single hardread level for verification with
NVMPROG.ACTION.VERIFY = 11B:
00BNR, Normal read
01BHRW, Hardread written
10BHRE, Hardread erased
11BRFU, Reserved for Future Use
00rwReserved for Future Use
Must be written with 0 to allow correct operation.
1) For SECPROT > 0, SECPROT defines the number of protected sectors. The sectors 0 to SECPROT-1 cannot
be written, erased, or verified. All writes that target the protected sectors are accepted, but are internally
ignored.
2) HRLEV defines the hardread level for a stand-alone verification sequence started with
NVMPROG.ACTION.VERIFY = 11B. This hardread level is used until the end of the verification sequence.
HRLEV may not be changed in between.
NVM_CONFIG1
Configuration 1 Register (4005 0048H) Reset Value: XXXXH
1514131211109876543210
RES FIX
WS RES
rw rw rw
Field Bits Type Description
RES 15:12 rw Reserved
Must not be changed when programming the
NVM_CONFIG1 register.
Field Bits Type Description
Subject to Agreement on the Use of Product Information
Inhneon”
XMC1100 / XMC1200 / XMC1300
XMC1000 Family
Fixed Flash Wait States
Data Sheet Addendum 9 V1.0, 2016-02
FIXWS 11 rw Wait States Scheme
Defines the scheme by which flash wait states are
generated. Withfixed wait states NVM_NVMCONF.WS
defines the number of wait states.
0Badaptive wait states.
1Bfixed wait states.
RES 10:0 rw Reserved
Must not be changed when programming the
NVM_CONFIG1 register.
Field Bits Type Description
Subject to Agreement on the Use of Product Information
Inhneon”
XMC1100 / XMC1200 / XMC1300
XMC1000 Family
Fixed Flash Wait States
Data Sheet Addendum 10 V1.0, 2016-02
1.3 Electrical Parameters
1.3.1 Flash Memory Parameters
This definition expands the flash wait states definition by parameters for the
configuration with fixed wait states.
Table 1 Flash Memory Parameters
Parameter Symbol Values Unit Note /
Test Condition
Min. Typ. Max.
Fixed Flash Wait States
configured in bit
NVM_NVMCONF.WS
NFWSFLASH
SR 0 0 1 NVM_CONFIG1.
FIXWS = 1B,
fMCLK 16 MHz
1 1 1 NVM_CONFIG1.
FIXWS = 1B,
16 MHz < fMCLK
32 MHz
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Published by Infineon Technologies AG

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