BCM6123x60E10A5yzz Datasheet by Vicor Corporation

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BCM® Bus Converter
BCM6123x60E10A5yzz
Isolated Fixed-Ratio DC-DC Converter
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NRTL
CUS
CUS
®
BCM® Bus Converter Rev 1.4
Page 1 of 29 07/2018
Features & Benefits
Up to 150A continuous secondary current
Up to 2206W/in3 power density
97.6% peak efficiency
2,250VDC isolation
Parallel operation for multi-kW arrays
OV, OC, UV, short circuit and thermal protection
BCM6123 through-hole ChiP package
2.402 x 0.990 x 0.284in
[61.00 x 25.14 x 7.21mm]
PMBus™ management interface [a]
Typical Applications
High-End Computing Systems
Automated Test Equipment
Industrial Systems
High-Density Power Supplies
Communications Systems
Transportation
Product Description
The BCM6123x60E10A5yzz is a high-efficiency Bus Converter,
operating from a 36 to 60VDC primary bus to deliver an isolated,
ratiometric secondary voltage from 6 to 10VDC.
The BCM6123x60E10A5yzz offers low noise, fast transient
response, and industry leading efficiency and power density. In
addition, it provides an AC impedance beyond the bandwidth of
most downstream regulators, allowing input capacitance normally
located at the input of a PoL regulator to be located at the primary
side of the BCM. With a primary to secondary K factor of 1/6, that
capacitance value can be reduced by a factor of 36x, resulting in
savings of board area, material and total system cost.
Leveraging the thermal and density benefits of Vicor ChiP
packaging technology, the BCM offers flexible thermal
management options with very low top and bottom side thermal
impedances. Thermally-adept ChiP-based power components
enable customers to achieve low cost power system solutions
with previously unattainable system size, weight and efficiency
attributes quickly and predictably.
Product Ratings
VPRI = 54V (36 – 60V) ISEC = up to 150A
VSEC = 9V (6 – 10V)
(no load)K = 1/6
[a] When used with D44TL1A0 and I13TL1A0
VICOR’
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BCM6123x60E10A5yzz
BCM
VAUX
EN
+VPRI
–VPRI
+VSEC
–VSEC
SW1
VPRI
enable/disable
switch
F1
ISOLATION BOUNDARY
PRIMARY SECONDARY
GND
CPRI
TM
PoL
Typical Applications
BCM6123x60E10A5y00 at point-of-load
BCM
SER-IN
EN
+VPRI
–VPRI
+VSEC
–VSEC
enable/disable
switch
FUSE
ISOLATION BOUNDARY
PRIMARY SECONDARY
SER-OUT
CI_BCM_ELEC
SOURCE_RTN
V
PRI
PRI_OUT_A
PRI_COM
SEC_IN_A
SEC_OUT_C
Digital Isolator
I13TL1A0
VDDB
VDD
TXD
RXD
PMBus
SGND
t
Host µC
SEC_COM PMBus
SGND
+
VEXT
PRI_IN_C
SEC_IN_BPRI_OUT_B
NC
SGND
SGND
SGND
SER-OUT
SER-IN
SER-IN
SER-OUT
PoL
Digital
Supervisor
D44TL1A0
BCM6123x60E10A5y01 at point-of-load
VICOR
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[b] For proper operation an external low impedance connection must be made between listed –VSEC1 and –VSEC2 terminals.
12
A
B
C
D
E
F
G
H
+VPRI
+VSEC
TOP VIEW
BCM6123 ChiP™
I
–VSEC1
–VSEC1
+VSEC
+VSEC
–VSEC1
+VSEC
–VSEC1
+VPRI J
+VPRI K
+VPRI L
A’
B’
C’
D’
E’
F’
G’
H’
I’
J’
K’
L’
+VSEC
–VSEC2
–VSEC2
+VSEC
+VSEC
–VSEC2
+VSEC
–VSEC2
–VPRI
TM/SER-OUT
EN
VAUX/SER-IN
Pin Configuration
Pin Descriptions
Power Pins
Pin Number Signal Name Type Function
I1, J1, K1, L1 +VPRI PRIMARY POWER Positive primary transformer power terminal
L’2 –VPRI PRIMARY POWER
RETURN Negative primary transformer power terminal
A1, D1, E1, H1, A’2,
D’2, E’2, H’2 +VSEC SECONDARY
POWER Positive secondary transformer power terminal
B1, C1, F1, G1
B’2, C’2, F’2, G’2 –VSEC [b] SECONDARY
POWER RETURN Negative secondary transformer power terminal
Analog Control Signal Pins
Pin Number Signal Name Type Function
I’2 TM OUTPUT Temperature Monitor; primary side referenced signals
J’2 EN INPUT Enables and disables power supply; primary side referenced signals
K’2 VAUX OUTPUT Auxiliary Voltage Source; primary side referenced signals
PMBus™ Control Signal Pins
Pin Number Signal Name Type Function
I’2 SER-OUT OUTPUT UART transmit pin; Primary side referenced signals
J’2 EN INPUT Enables and disables power supply; Primary side referenced signals
K’2 SER-IN INPUT UART receive pin; Primary side referenced signals
BCM® Bus Converter Rev 1.4
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Part Ordering Information
Standard Models
Product
Function
Package
Size
Package
Mounting
Max Primary
Input Voltage
Range
Identifier
Max
Secondary
Voltage
Secondary
Output
Current
Temperature
Grade Option
BCM 6123 x 60 E 10 A5 y zz
Bus Converter
Module
61 = L
23 = W T = TH 60V 36 – 60V 10V
No Load 150A T = –40 to 125°C
M = –55 to 125°C
00 = Analog Ctrl
01 = PMBus Ctrl
0R = Reversible Analog Ctrl
0P = Reversible PMBus Ctrl
Product
Function
Package
Size
Package
Mounting
Max Primary
Input Voltage
Range
Identifier
Max
Secondary
Voltage
Secondary
Output
Current
Temperature
Grade Option
BCM 6123 T 60 E 10 A5 T 00
BCM 6123 T 60 E 10 A5 T 01
All products shipped in JEDEC standard high profile (0.400” thick) trays (JEDEC Publication 95, Design Guide 4.10).
Absolute Maximum Ratings
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to the device.
Parameter Comments Min Max Unit
+VPRI_DC to –VPRI_DC –1 80 V
VPRI_DC or VSEC_DC Slew Rate
(Operational) 1 V/µs
+VSEC_DC to –VSEC_DC –1 15 V
TM/SER-OUT to –VPRI_DC
–0.3
4.6 V
EN to –VPRI_DC 5.5 V
VAUX/SER-IN to –VPRI_DC 4.6 V
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Attribute Symbol Conditions / Notes Min Typ Max Unit
General Powertrain PRIMARY to SECONDARY Specification (Forward Direction)
Primary Input Voltage Range
(Continuous) VPRI_DC 36 60 V
VPRI µController VµC_ACTIVE
VPRI_DC voltage where µC is initialized,
(i.e., VAUX = Low, powertrain inactive) 14 V
PRI to SEC Input Quiescent Current IPRI_Q
Disabled, EN Low, VPRI_DC = 54V 5 mA
TINTERNAL ≤ 100ºC 10
PRI to SEC No-Load
Power Dissipation PPRI_NL
VPRI_DC = 54V, TINTERNAL = 25ºC 7.2 9
W
VPRI_DC = 54V 5 14
VPRI_DC = 36 – 60V, TINTERNAL = 25ºC 12
VPRI_DC = 36 – 60V 17
PRI to SEC Inrush Current Peak IPRI_INR_PK
VPRI_DC = 60V, CSEC_EXT = 6000μF,
RLOAD_SEC = 20% of full-load current 30 A
TINTERNAL ≤ 100ºC 35
DC Primary Input Current IPRI_IN_DC At ISEC_OUT_DC = 150A, TINTERNAL ≤ 100ºC 25.5 A
Transformation Ratio K Primary to secondary, K = VSEC_DC / VPRI_DC, at no load 1/6 V/V
Secondary Output Current
(Continuous) ISEC_OUT_DC 150 A
Secondary Output Current (Pulsed) ISEC_OUT_PULSE 10ms pulse, 25% duty cycle,
ISEC_OUT_AVG ≤ 50% of rated ISEC_OUT_DC 180 A
PRI to SEC Efficiency (Ambient) ηAMB
VPRI_DC = 54V, ISEC_OUT_DC = 150A 96.1 96.7
%VPRI_DC = 36 – 60V, ISEC_OUT_DC = 150A 94.5
VPRI_DC = 54V, ISEC_OUT_DC = 75A 96.9 97.6
PRI to SEC Efficiency (Hot) ηHOT VPRI_DC = 54V, ISEC_OUT_DC = 150A 95.4 96 %
PRI to SEC Efficiency
(Over Load Range) η20% 30A < ISEC_OUT_DC < 150A 90 %
PRI to SEC Output Resistance
RSEC_COLD VPRI_DC = 54V, ISEC_OUT_DC = 150A, TINTERNAL = –40°C 0.9 1.2 1.5
RSEC_AMB VPRI_DC = 54V, ISEC_OUT_DC = 150A 1.2 1.6 2
RSEC_HOT VPRI_DC = 54V, ISEC_OUT_DC = 150A, TINTERNAL = 100°C 1.6 2 2.2
Switching Frequency FSW Frequency of the output voltage ripple = 2x FSW 0.85 0.90 0.95 MHz
Secondary Output Voltage Ripple VSEC_OUT_PP
CSEC_EXT = 0μF, ISEC_OUT_DC =150A, VPRI_DC = 54V,
20MHz BW 140 mV
TINTERNAL ≤ 100ºC 200
Primary Input Leads Inductance
(Parasitic) LPRI_IN_LEADS Frequency 2.5MHz (double switching frequency),
simulated lead model 6.7 nH
Secondary Output Leads Inductance
(Parasitic) LSEC_OUT_LEADS Frequency 2.5MHz (double switching frequency),
simulated lead model 0.64 nH
Electrical Specifications
Specifications apply over all line and load conditions, unless otherwise noted; boldface specifications apply over the temperature range of
–40°C ≤ TINTERNAL ≤ 125°C (T-Grade). All other specifications are at TINTERNAL = 25ºC unless otherwise noted.
VICOR
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Electrical Specifications (Cont.)
Specifications apply over all line and load conditions, unless otherwise noted; boldface specifications apply over the temperature range of
–40°C ≤ TINTERNAL ≤ 125°C (T-Grade). All other specifications are at TINTERNAL = 25ºC unless otherwise noted.
Attribute Symbol Conditions / Notes Min Typ Max Unit
General Powertrain PRIMARY to SECONDARY Specification (Forward Direction) Cont.
Effective Primary Capacitance
(Internal) CPRI_INT Effective value at 54VPRI_DC 11.2 µF
Effective Secondary Capacitance
(Internal) CSEC_INT Effective value at 9VSEC_DC 202 µF
Rated Secondary Output
Capacitance (External) CSEC_OUT_EXT Excessive capacitance may drive module
into short-circuit protection 6000 µF
Rated Secondary Output Capacitance
(External), Parallel Array Operation CSEC_OUT_AEXT CSEC_OUT_AEXT Max = N • 0.5 • CSEC_OUT_EXT MAX, where
N = the number of units in parallel
Powertrain Protection PRIMARY to SECONDARY (Forward Direction)
Auto Restart Time tAUTO_RESTART
Start up into a persistent fault condition. Non-latching
fault detection given VPRI_DC > VPRI_UVLO+ 490 560 ms
Primary Overvoltage
Lockout Threshold VPRI_OVLO+ 63 67 71 V
Primary Overvoltage
Recovery Threshold VPRI_OVLO– 61 65 69 V
Primary Overvoltage
Lockout Hysteresis VPRI_OVLO_HYST 2 V
Primary Overvoltage
Lockout Response Time tPRI_OVLO 100 µs
Secondary Soft-Start Time tSEC_SOFT-START From powertrain active; fast current limit protection
disabled during soft start 1 ms
Secondary Output Overcurrent
Trip Threshold ISEC_OUT_OCP 170 210 240 A
Secondary Output Overcurrent
Response Time Constant tSEC_OUT_OCP Effective internal RC filter 3 ms
Secondary Output Short-Circuit
Protection Trip Threshold ISEC_OUT_SCP 225 A
Secondary Output Short-Circuit
Protection Response Time tSEC_OUT_SCP 1 µs
Overtemperature
Shut-Down Threshold tOTP+ Temperature sensor located inside controller IC 125 °C
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Electrical Specifications (Cont.)
Specifications apply over all line and load conditions, unless otherwise noted; boldface specifications apply over the temperature range of
–40°C ≤ TINTERNAL ≤ 125°C (T-Grade); All other specifications are at TINTERNAL = 25ºC unless otherwise noted.
Attribute Symbol Conditions / Notes Min Typ Max Unit
Powertrain Supervisory Limits PRIMARY to SECONDARY (Forward Direction)
Primary Overvoltage
Lockout Threshold VPRI_OVLO+ 64 66 68 V
Primary Overvoltage
Recovery Threshold VPRI_OVLO– 60 64 66 V
Primary Overvoltage
Lockout Hysteresis VPRI_OVLO_HYST 2 V
Primary Overvoltage
Lockout Response Time tPRI_OVLO 100 µs
Primary Undervoltage
Lockout Threshold VPRI_UVLO– 26 28 30 V
Primary Undervoltage
Recovery Threshold VPRI_UVLO+ 28 30 32 V
Primary Undervoltage
Lockout Hysteresis VPRI_UVLO_HYST 2 V
Primary Undervoltage
Lockout Response Time tPRI_UVLO 100 µs
Primary-to-Secondary Start-Up Delay tPRI_TO_SEC_DELAY
From VPRI_DC = VPRI_UVLO+ to powertrain active, EN
floating (i.e., one-time start-up delay from application
of VPRI_DC to VSEC_DC)
20 ms
Secondary Output Overcurrent
Trip Threshold ISEC_OUT_OCP 192 204 216 A
Secondary Output Overcurrent
Response Time Constant tSEC_OUT_OCP Effective internal RC filter 3 ms
Overtemperature
Shut-Down Threshold tOTP+ Temperature sensor located inside controller IC 125 °C
Overtemperature
Recovery Threshold tOTP– 105 110 115 °C
Undertemperature
Shut-Down Threshold tUTP Temperature sensor located inside controller IC;
Protection not available for M-Grade units. –45 °C
Undertemperature Restart Time tUTP_RESTART Start up into a persistent fault condition. Non-latching
fault detection given VPRI_DC > VPRI_UVLO+ 3 s
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Attribute Symbol Conditions / Notes Min Typ Max Unit
General Powertrain SECONDARY to PRIMARY Specification (Reverse Direction)
Secondary Input Voltage Range
(Continuous) VSEC_DC 6 10 V
SEC to PRI No-Load
Power Dissipation PSEC_NL
VSEC_DC = 9V, TINTERNAL = 25ºC 7.2 9
W
VSEC_DC = 9V 5 14
VSEC_DC = 6 – 10V, TINTERNAL = 25ºC 12
VSEC_DC = 6 – 10V 17
DC Secondary Input Current ISEC_IN_DC At IPRI_DC = 25A, TINTERNAL ≤ 100ºC 152 A
Primary Output Current (Continuous) IPRI_OUT_DC 25 A
Primary Output Current (Pulsed) IPRI_OUT_PULSE 10ms pulse, 25% duty cycle,
IPRI_OUT_AVG ≤ 50% of rated IPRI_OUT_DC 30 A
SEC to PRI Efficiency (Ambient) ηAMB
VSEC_DC = 9V, IPRI_OUT_DC = 25A 96.0 96.5
%VSEC_DC = 6 – 10V, IPRI_OUT_DC= 25A 93.8
VSEC_DC = 9V, IPRI_OUT_DC = 12.5A 96.9 97.5
SEC to PRI Efficiency (Hot) ηHOT VSEC_DC = 9V, IPRI_OUT_DC = 25A 95.4 95.9 %
SEC to PRI Efficiency
(Over Load Range) η20% 5A < IPRI_OUT_DC < 25A 90 %
SEC to PRI Output Resistance
RPRI_COLD VSEC_DC = 9V, IPRI_OUT_DC = 25A, TINTERNAL = –40°C 47 55 63
RPRI_AMB VSEC_DC = 9V, IPRI_OUT_DC = 25A 61 72 83
RPRI_HOT VSEC_DC = 9V, IPRI_OUT_DC = 25A, TINTERNAL = 100°C 76 84 92
Primary Output Voltage Ripple VPRI_OUT_PP
CPRI_OUT_EXT = 0μF, IPRI_OUT_DC = 25A,
VSEC_DC = 9V, 20MHz BW 800 mV
TINTERNAL ≤ 100ºC 1200
Electrical Specifications (Cont.)
Specifications apply over all line and load conditions, unless otherwise noted; boldface specifications apply over the temperature range of
–40°C ≤ TINTERNAL ≤ 125°C (T-Grade); All other specifications are at TINTERNAL = 25ºC unless otherwise noted.
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Attribute Symbol Conditions / Notes Min Typ Max Unit
Protection SECONDARY to PRIMARY (Reverse Direction)
Effective Primary Output
Capacitance (External) CPRI_OUT_EXT Excessive capacitance may drive module
into SC protection 100 V
Secondary Overvoltage
Lockout Threshold VSEC_OVLO+ Module latched shut down with VPRI_DC < VPRI_UVLO–_R 10.6 11.2 11.8 V
Secondary Overvoltage
Lockout Response Time tPRI_OVLO 100 µs
Secondary Undervoltage
Lockout Threshold VSEC_UVLO– Module latched shut down with VPRI_DC < VPRI_UVLO–_R 4.3 4.7 5.1 V
Secondary Undervoltage
Lockout Response Time tSEC_UVLO 100 µs
Primary Undervoltage
Lockout Threshold VPRI_UVLO–_R
Applies only to reversible products in forward and in
reverse direction; IPRI_DC ≤ 20% while
VPRI_UVLO–_R < VPRI_DC < VPRI_MIN
26 28 30 V
Primary Undervoltage
Recovery Threshold VPRI_UVLO+_R Applies only to reversible products in forward and in
reverse direction 28 30 32 V
Primary Undervoltage
Lockout Hysteresis VPRI_UVLO_HYST_R Applies only to reversible products in forward and in
reverse direction 2 V
Primary Output Overcurrent
Trip Threshold (Analog) IPRI_OUT_OCP Module latched shutdown with VPRI_DC < VPRI_UVLO–_R 28.3 35 40 A
Primary Output Overcurrent
Response Time Constant (Analog) tPRI_OUT_OCP Effective internal RC filter 3 ms
Primary Short Circuit Protection
Trip Threshold IPRI_SCP Module latched shutdown with VPRI_DC < VPRI_UVLO–_R 37.5 A
Primary Short Circuit Protection
Response Time tPRI_SCP 1 µs
Primary Output Overcurrent
Trip Threshold (PMBus™) IPRI_OUT_OCP Module latched shutdown with VPRI_DC < VPRI_UVLO–_R 32 34 36 A
Primary Output Overcurrent
Response Time Constant (PMBus) tPRI_OUT_OCP Effective internal RC filter 3 ms
Electrical Specifications (Cont.)
Specifications apply over all line and load conditions, unless otherwise noted; boldface specifications apply over the temperature range of
–40°C ≤ TINTERNAL ≤ 125°C (T-Grade); All other specifications are at TINTERNAL = 25ºC unless otherwise noted.
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Operating Area
Secondary Output Current (A
)
Primary Input Voltage (V)
ISEC_OUT_DC ISEC_OUT_PULSE
0
50
100
150
200
36 38 41 43 46 48 50 53 55 58 60
Secondary Output Po
wer (W)
Primary Input Voltage (V)
PSEC_OUT_DCPSEC_OUT_PULSE
800
900
1000
1100
1200
1300
1400
1500
1600
1700
1800
1900
2000
36 38 41 43 46 48 50 53 55 58 60
Figure 1 — Specified thermal operating area
Figure 2 — Specified electrical operating area using rated RSEC_HOT
Secondary Output
Capacitance
(% Rated CSEC_EXT_MAX)
Secondary Output Current (% I
SEC_DC
)
0
10
20
30
40
50
60
70
80
90
100
110
0 20 40 60 80 100
Secondary Output Current (A
)
Case Temperature (°C)
Top only at temperature Top and leads at temperature
Top, leads and belly at temperature
0
25
50
75
100
125
150
175
20 30 40 50 60 70 80 90 100 110 120
Figure 3 — Specified primary start up into load current and external capacitance
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Analog Control Signal Characteristics
Specifications apply over all line and load conditions, unless otherwise noted; boldface specifications apply over the temperature range of
–40°C ≤ TINTERNAL ≤ 125°C (T-Grade); All other specifications are at TINTERNAL = 25ºC unless otherwise noted.
Temperature Monitor
The TM pin is a standard analog I/O configured as an output from an internal µC.
The TM pin monitors the internal temperature of the controller IC within an accuracy of ±5°C.
µC 250kHz PWM output internally pulled high to 3.3V.
Signal Type State Attribute Symbol Conditions / Notes Min Typ Max Unit
DIGITAL
OUTPUT
Start Up Powertrain Active
to TM Time tTM 100 µs
Regular
Operation
TM Duty Cycle TMPWM 18.18 68.18 %
TM Current ITM 4mA
Recommended external filtering
TM Capacitance (External) CTM_EXT Recommended external filtering 0.01 µF
TM Resistance (External) RTM_EXT Recommended external filtering 1
Specifications using recommended filter
TM Gain ATM 10 mV / °C
TM Voltage Reference VTM_AMB Internal temperature = 27ºC 1.27 V
TM Voltage Ripple VTM_PP
RTM_EXT = 1kΩ, CTM_EXT = 0.01µF,
VPRI_DC = 54V, ISEC_DC = 150A 28 mV
TINTERNAL ≤ 100ºC 40
Enable / Disable Control
The EN pin is a standard analog I/O configured as an input to an internal µC.
It is internally pulled high to 3.3V.
When held low, the BCM internal bias will be disabled and the powertrain will be inactive.
In an array of BCMs, EN pins should be interconnected to synchronize start up.
Signal Type State Attribute Symbol Conditions / Notes Min Typ Max Unit
ANALOG
INPUT
Start Up EN to Powertrain
Active Time tEN_START
VPRI_DC > VPRI_UVLO+, EN held low both
conditions satisfied for T > tPRI_UVLO+_DELAY
250 µs
Regular
Operation
EN Voltage Threshold VEN_TH 2.3 V
EN Resistance (Internal) REN_INT Internal pull-up resistor 1.5
EN Disable Threshold VEN_DISABLE_TH 1V
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Auxiliary Voltage Source
The VAUX pin is a standard analog I/O configured as an output from an internal µC.
VAUX is internally connected to µC output and internally pulled high to a 3.3V regulator with 2% tolerance, a 1% resistor of 1.5kΩ.
VAUX can be used as a “Ready to process full power” flag. This pin transitions VAUX voltage after a 2ms delay from the start of powertrain activating,
signaling the end of soft start.
VAUX can be used as “Fault flag”. This pin is pulled low internally when a fault protection is detected.
Signal Type State Attribute Symbol Conditions / Notes Min Typ Max Unit
ANALOG
OUTPUT
Start Up Powertrain Active to
VAUX Time tVAUX Powertrain active to VAUX High 2ms
Regular
Operation
VAUX Voltage VVAUX 2.8 3.3 V
VAUX Available Current IVAUX 4mA
VAUX Voltage Ripple VVAUX_PP
50 mV
TINTERNAL ≤ 100ºC 100
VAUX Capacitance
(External) CVAUX_EXT 0.01 µF
VAUX Resistance (External) RVAUX_EXT VPRI_DC < VµC_ACTIVE 1.5 kΩ
Fault VAUX Fault Response Time tVAUX_FR From fault to VVAUX = 2.8V, CVAUX = 0pF 10 µs
Analog Control Signal Characteristics (Cont.)
Specifications apply over all line and load conditions, unless otherwise noted; boldface specifications apply over the temperature range of
–40°C ≤ TINTERNAL ≤ 125°C (T-Grade); All other specifications are at TINTERNAL = 25ºC unless otherwise noted.
BCM® Bus Converter Rev 1.4
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UART SER-IN / SER-OUT Pins
Universal Asynchronous Receiver/Transmitter (UART) pins.
The BCM communication version is not intended to be used without a Digital Supervisor.
Isolated I2C communication and telemetry is available when using Vicor Digital Isolator and Vicor Digital Supervisor. Please see specific product data sheet
for more details.
UART SER-IN pin is internally pulled high using a 1.5kΩ to 3.3V.
Signal Type State Attribute Symbol Conditions / Notes Min Typ Max Unit
GENERAL I/O
Regular
Operation
Baud Rate BRUART Rate 750 Kbit/s
DIGITAL
INPUT
SER-IN Pin
SER-IN Input Voltage Range VSER-IN_IH 2.3 V
VSER-IN_IL 1 V
SER-IN Rise Time tSER-IN_RISE 10 – 90% 400 ns
SER-IN Fall Time tSER-IN_FALL 10 – 90% 25 ns
SER-IN RPULLUP RSER-IN_PLP Pull up to 3.3V 1.5
SER-IN External Capacitance CSER-IN_EXT 400 pF
DIGITAL
OUTPUT
SER-OUT Pin
SER-OUT Output
Voltage Range
VSER-OUT_OH 0mA ≥ IOH ≥ –4mA 2.8 V
VSER-OUT_OL 0mA ≤ IOL ≤ 4mA 0.5 V
SER-OUT Rise Time tSER-OUT_RISE 10 – 90% 55 ns
SER-OUT Fall Time tSER-OUT_FALL 10 – 90% 45 ns
SER-OUT Source Current ISER-OUT VSER-OUT = 2.8V 6 mA
SER-OUT Output Impedance ZSER-OUT 120 Ω
Enable / Disable Control
The EN pin is a standard analog I/O configured as an input to an internal µC.
It is internally pulled high to 3.3V.
When held low, the BCM internal bias will be disabled and the powertrain will be inactive.
In an array of BCMs, EN pins should be interconnected to synchronize start up.
PMBus ON/OFF command has no effect if the BCM EN pin is not in the active state. This BCM has active high EN pin logic.
Signal Type State Attribute Symbol Conditions / Notes Min Typ Max Unit
ANALOG
INPUT
Start Up EN to Powertrain Active Time tEN_START
VPRI_DC > VPRI_UVLO+,
EN held low both conditions satisfied
for t > tPRI_UVLO+_DELAY
250 µs
Regular
Operation
EN Voltage Threshold VENABLE 2.3 V
EN Resistance (Internal) REN_INT Internal pull-up resistor 1.5 kΩ
EN Disable Threshold VEN_DISABLE_TH 1 V
PMBus™ Control Signal Characteristics
Specifications apply over all line, load conditions, unless otherwise noted; boldface specifications apply over the temperature range of
–40°C ≤ TINTERNAL ≤ 125°C (T-Grade); All other specifications are at TINTERNAL = 25ºC unless otherwise noted.
BCM® Bus Converter Rev 1.4
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PMBus™ Reported Characteristics
Specifications apply over all line, load conditions, unless otherwise noted; boldface specifications apply over the temperature range of
–40°C ≤ TINTERNAL ≤ 125°C (T-Grade); All other specifications are at TINTERNAL = 25ºC unless otherwise noted.
Monitored Telemetry
The BCM communication version is not intended to be used without a Digital Supervisor.
The current telemetry is only available in forward operation. The input and output current reported value is not supported in reverse operation.
Attribute Digital Supervisor
PMBus Read Command
Accuracy
(Rated Range)
Functional
Reporting Range
Update
Rate Reported Units
Input Voltage (88h) READ_VIN ±5% (LL – HL) 28 – 66V 100µs VACTUAL = VREPORTED x 10–1
Input Current (89h) READ_IIN ±20% (10 – 20% of FL)
±5% (20 – 133% of FL) 0 – 34A 100µs IACTUAL = IREPORTED x 10–2
Output Voltage [b] (8Bh) READ_VOUT ±5% (LL – HL) 4.7 – 11V 100µs VACTUAL = VREPORTED x 10–1
Output Current (8Ch) READ_IOUT ±20% (10 – 20% of FL)
±5% (20 – 133% of FL) 0 – 204A 100µs IACTUAL = IREPORTED x 10–2
Output Resistance (D4h) READ_ROUT ±5% (50 – 100% of FL) at NL
±10% (50 – 100% of FL) (LL – HL) 0.5 – 3mΩ 100ms RACTUAL = RREPORTED x 10–5
Temperature [c] (8Dh) READ_TEMPERATURE_1 ±7°C (Full Range) –55 to 130ºC 100ms TACTUAL = TREPORTED
Variable Parameter
Factory setting of all below Thresholds and Warning limits are 100% of listed protection values.
Variables can be written only when module is disabled either EN pulled low or VIN < VIN_UVLO–.
Module must remain in a disabled mode for 3ms after any changes to the below variables allowing ample time to commit changes to EEPROM.
Attribute Digital Supervisor
PMBus Command [d] Conditions / Notes Accuracy
(Rated Range)
Functional
Reporting
Range
Default
Value
Input / Output Overvoltage
Protection Limit (55h) VIN_OV_FAULT_LIMIT VIN_OVLO– is automatically 3%
lower than this set point ±5% (LL – HL) 28 – 66V 100%
Input / Output Overvoltage
Warning Limit (57h) VIN_OV_WARN_LIMIT ±5% (LL – HL) 28 – 66V 100%
Input / Output Undervoltage
Protection Limit (D7h) DISABLE_FAULTS Can only be disabled to a preset
default value ±5% (LL – HL) 14 – 36V 100%
Input Overcurrent
Protection Limit (5Bh) IIN_OC_FAULT_LIMIT ±20% (10 – 20% of FL)
±5% (20 – 133% of FL) 0 – 34A 100%
Input Overcurrent
Warning Limit (5Dh) IIN_OC_WARN_LIMIT ±20% (10 – 20% of FL)
±5% (20 – 133% of FL) 0 – 34A 100%
Overtemperature
Protection Limit (4Fh) OT_FAULT_LIMIT ±7°C (Full Range) 0 – 125°C 100%
Overtemperature
Warning Limit (51h) OT_WARN_LIMIT ±7°C (Full Range) 0 – 125°C 100%
Turn-On Delay (60h) TON_DELAY Additional time delay to the
undervoltage start-up delay ±50µs 0 – 100ms 0ms
[c] Default READ Output Voltage returned when unit is disabled = –300V.
[d] Default READ Temperature returned when unit is disabled = –273°C.
[e] Refer to Digital Supervisor datasheet for complete list of supported commands.
VICOR
BCM® Bus Converter Rev 1.4
Page 15 of 29 07/2018
BCM6123x60E10A5yzz
BCM Timing Diagram
EN
TM
+VPRI
BIDIR
INPUT
+VSEC
OUTPUT
VPRI_DCINPUT TURN-ON
SECONDARY OUTPUT
TURN-ON
PRIMARY INPUT OVERVOLTAGE
VPRI_DCINPUT RESTART
ENABLE PULLED LOW
ENABLE PULLED HIGH
SHORT CIRCUIT EVENT
PRIMARY INPUT VOLTAGE
TURN-OFF
OUTPUT
OUTPUT
VAUX
EN & VAUX INTERNAL Pull-up
START UP OVERVOLTAGEENABLE CONTROL
OVERCURRENT
SHUT DOWN
µc INITIALIZE
VPRI_OVLO-
VPRI_OVLO+
VPRI_UVLO+
VµC_ACTIVE
VNOM
VPRI_UVLO-
tSEC_OUT_SCP
t
tVAUX tAUTO-RESTART
>
tPRI_TO_SEC_DELAY
PRI_TO_SEC_DELAY
Ap Icallan of Input vonage to v falling edge, TP detected Input OVLO or UVLO, Output OCF, UTF detected ENABLE falling e or OTP delecle Input OVLO or UVLO, lpul ocp, or UTP detected Short Circuit detected VICOR
BCM® Bus Converter Rev 1.4
Page 16 of 29 07/2018
BCM6123x60E10A5yzz
FAULT
SEQUENCE
TM Low
EN High
VAUX Low
Powertrain Stopped
VµC_ACTIVE < VPRI_DC < VPRI_UVLO+
VPRI_DC > VPRI_UVLO+
tPRI_TO_SEC_DELAY
expired
ONE TIME DELAY
INITIAL START UP
Fault
Auto-
recovery
ENABLE falling edge,
or OTP detected
Input OVLO or UVLO,
Output OCP,
or UTP detected
ENABLE falling edge,
or OTP detected
Input OVLO or UVLO,
Output OCP,
or UTP detected
Short Circuit detected
Application
of input voltage to VPRI_DC
SUSTAINED
OPERATION
TM PWM
EN High
VAUX High
Powertrain Active
START-UP SEQUENCE
TM Low
EN High
VAUX Low
Powertrain Stopped
STANDBY SEQUENCE
TM Low
EN High
VAUX Low
Powertrain Stopped
High-Level Functional State Diagram
VICOR
BCM® Bus Converter Rev 1.4
Page 17 of 29 07/2018
BCM6123x60E10A5yzz
PRI to SEC, Power
Dissipation (W)
Primary Input Voltage (V)
- 40°C 25°C 80°C
TTOP SURFACE CASE:
3
4
5
6
7
8
9
10
11
12
13
14
15
36 39 41 44 47 49 52 55 57 60
Case Temperature (ºC)
36V54V60V
PRI to SEC, Full
Load Efficiency (%)
VPRI:
96.0
96.5
97.0
97.5
98.0
-40 -20 0 20 40 60 80 100
PRI to SEC, Efficiency
(%)
Secondary Output Current (A)
36V 54V60V
VPRI
:
80
82
84
86
88
90
92
94
96
98
0153045607590105 120135 150
Figure 4 — No-load power dissipation vs. VPRI_DC Figure 5 — Full-load efficiency vs. temperature; VPRI_DC
Figure 6 — Efficiency at TCASE = –4C
PRI to SEC, Efficiency
(%)
Load Current (A)
36V 54V60V
VPRI
:
80
82
84
86
88
90
92
94
96
98
0153045607590 105 120 135 150
Figure 8 — Efficiency at TCASE = 25°C
PRI to SEC, Po
wer Dissipation
Secondary Output Current (A)
36V 54V60V
VPRI
:
0
6
12
18
24
30
36
42
48
54
0153045607590 105 120 135 150
Figure 7 — Power dissipation at TCASE = –40°C
PRI to SEC, Po
wer Dissipation
Load Current (A)
36V 54V60V
VPRI
:
0
6
12
18
24
30
36
42
48
54
0153045607590 105 120 135 150
Figure 9 — Power dissipation at TCASE = 25°C
Application Characteristics
Temperature controlled via top-side cold plate, unless otherwise noted. All data presented in this section are collected from units processing power in the
forward direction (primary side to secondary side). See associated figures for general trend data.
CH1 m CH2 ,~ A n A [fl w x .z‘ /\ w w /\r (‘fo \‘v" \‘\IV/ \L/Hw/ \‘v \w/ \V/ \4 CH1 V550: 100mV/div Tlmebase: soans/div CH2 hm: mom/aw VICOR
BCM® Bus Converter Rev 1.4
Page 18 of 29 07/2018
BCM6123x60E10A5yzz
Figure 14 — Full-load secondary voltage and primary current
ripple, 2700µF CPRI_IN_EXT; no external CSEC_OUT_EX T.
Board-mounted module, scope setting:
20MHz analog BW
Voltage Ripple (mVPK-PK)
Load Current (A)
54V
VPRI:
0
25
50
75
100
125
150
175
200
0 15 30 45 60 75 90 105 120 135 150
Figure 13 — VSEC_OUT_ PP vs. ISEC_DC ; no external CSEC_OUT_ EXT.
Board-mounted module, scope setting:
20MHz analog BW
PRI to SEC, Efficiency
(%)
Secondary Output Current (A)
36V 54V60V
VPRI
:
80
82
84
86
88
90
92
94
96
98
13 25 38 50 63 75 88 100 113 125
0
PRI to SEC, Output Resistance (mΩ)
Case Temperature (°C)
150AISEC:
0
1
2
3
-40-20 020406080100
Figure 10 — Efficiency at TCASE = 80°C
Figure 12 — RSEC vs. temperature; nominal VPRI_DC
ISEC_DC = 125A at TCASE = 80°C
wer Dissipation
Secondary Output Current (A)
36V 54V60V
VPRI
:
0
6
12
18
24
30
36
42
48
54
13 25 38 50 63 75 88 100 113 125
0
Figure 11 — Power dissipation at TCASE = 80°C
Application Characteristics (Cont.)
Temperature controlled via top-side cold plate, unless otherwise noted. All data presented in this section are collected from units processing power in the
forward direction (primary side to secondary side). See associated figures for general trend data.
.CH1 W CH2 4 % CH2 L———I .. ..._—._.—_.__ CH1 ngc WIdiv Tlmebase Sus/div CH1 vSFc 1V/div Tlmebasa Spa/Aim CH2 I555 mA/aw CH2 ISEC EDA/div .; ‘ ‘ CH1 CH! ‘ CH2 CH2 > .1 CH3 CH3 —F CH1 VFRI SUV/div CH3 VAUX.4V/d|v Tlmebase ems/div CH2 vsgd ewmv CH4 EN awaw CH1 EN 3VIdiv CH3 VAUX awdiv Tlmebase 400ps/div CH2 vm-swaw CHMPHI 20AM" VICOR
BCM® Bus Converter Rev 1.4
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BCM6123x60E10A5yzz
Figure 15 — 0 – 150A transient response:
CPRI_IN_EXT = 2700µF, no external CSEC_OUT_ EXT
Figure 16 — 150 – 0A transient response:
CPRI_IN_EXT = 2700µF, no external CSEC_OUT_ EXT
Application Characteristics (Cont.)
Temperature controlled via top-side cold plate, unless otherwise noted. All data presented in this section are collected from units processing power in the
forward direction (primary side to secondary side). See associated figures for general trend data.
Figure 17 — Start up from application of VPRI_DC = 54V,
20% ISEC_OUT_ DC, 100% CSEC_OUT_EX T
Figure 18 — Start up from application of EN with pre-applied
VPRI_DC = 54V, 20% ISEC_OUT_ DC, 100% CSEC_OUT_ EXT
VICOR
BCM® Bus Converter Rev 1.4
Page 20 of 29 07/2018
BCM6123x60E10A5yzz
General Characteristics
Specifications apply over all line and load conditions, unless otherwise noted; boldface specifications apply over the temperature range of
–40°C ≤ TINTERNAL ≤ 125°C (T-Grade); All other specifications are at TINTERNAL = 25ºC unless otherwise noted.
Attribute Symbol Conditions / Notes Min Typ Max Unit
Mechanical
Length L 60.87 [2.396] 61.00 [2.402] 61.13 [2.407] mm [in]
Width W 24.76 [0.975] 25.14 [0.990] 25.52 [1.005] mm [in]
Height H 7.11 [0.280] 7.21 [0.284] 7.31 [0.288] mm [in]
Volume Vol Without heatsink 11.06 [0.675] cm3 [in3]
Weight W 41 [1.45] g [oz]
Lead Finish
Nickel 0.51 2.03
µmPalladium 0.02 0.15
Gold 0.003 0.051
Thermal
Operating Temperature TINTERNAL BCM6123x60E10A5yzz (T-Grade) –40 125 °C
Thermal Resistance Top Side θINT-TOP
Estimated thermal resistance to maximum
temperature internal component from
isothermal top
1.4 °C/W
Thermal Resistance Leads θINT-LEADS
Estimated thermal resistance to
maximum temperature internal
component from isothermal leads
1.3 °C/W
Thermal Resistance Bottom Side θINT-BOTTOM
Estimated thermal resistance to
maximum temperature internal
component from isothermal bottom
1.4 °C/W
Thermal Capacity 34 Ws/°C
Assembly
Storage Temperature BCM6123x60E10A5yzz (T-Grade) –55 125 °C
ESD Withstand ESDHBM Human Body Model, “ESDA / JEDEC JDS-001-2012” Class I-C (1kV to < 2kV)
ESDCDM Charge Device Model, “JESD 22-C101-E” Class II (200V to < 500V)
VICDR
BCM® Bus Converter Rev 1.4
Page 21 of 29 07/2018
BCM6123x60E10A5yzz
General Characteristics (Cont.)
Specifications apply over all line and load conditions, unless otherwise noted; boldface specifications apply over the temperature range of
–40°C ≤ TINTERNAL ≤ 125°C (T-Grade); All other specifications are at TINTERNAL = 25ºC unless otherwise noted.
Attribute Symbol Conditions / Notes Min Typ Max Unit
Soldering [e]
Peak Temperature Top Case 135 °C
Safety
Isolation voltage / Dielectric test VHIPOT
PRIMARY to SECONDARY 2,250
VDC
PRIMARY to CASE 2,250
SECONDARY to CASE 707
Isolation Capacitance CPRI_SEC Unpowered Unit 620 780 940 pF
Insulation Resistance RPRI_SEC At 500VDC 10
MTBF
MIL-HDBK-217Plus Parts Count - 25°C
Ground Benign, Stationary, Indoors /
Computer
4.45 MHrs
Telcordia Issue 2 - Method I Case III; 25°C
Ground Benign, Controlled 7.01 MHrs
Agency Approvals / Standards
cTÜVus EN 60950-1
cURus UL 60950-1
CE Marked for Low Voltage Directive and RoHS Recast Directive, as applicable
[f] Product is not intended for reflow solder attach.
VICOR
BCM® Bus Converter Rev 1.4
Page 22 of 29 07/2018
BCM6123x60E10A5yzz
The PMBus communication enabled bus converter provides accurate telemetry monitoring and reporting, threshold and warning
limits adjustment, in addition to corresponding status flags.
The BCM internal µC is referenced to primary ground. The Digital Isolator allows UART communication interface with the host Digital
Supervisor at typical speed of 750kHz across the isolation barrier. One of the advantages of the Digital Isolator is its low power
consumption. Each transmission channel is able to draw its internal bias circuitry directly from the input signal being transmitted to
the output with minimal to no signal distortion.
The Digital Supervisor provides the host system µC with access to an array of up to four BCMs. This array is constantly polled for
status by the Digital Supervisor. Direct communication to individual BCM is enabled by a page command. For example, the page
(0x00) prior to a telemetry inquiry points to the Digital Supervisor data and pages (0x01 – 0x04) prior to a telemetry inquiry points to
the array of BCMs connected data. The Digital Supervisor constantly polls the BCM data through the UART interface.
The Digital Supervisor enables the PMBus compatible host interface with an operating bus speed of up to 400kHz. The Digital
Supervisor follows the PMBus command structure and specification.
Please refer to the Digital Supervisor data sheet for more details.
SER-OUT
1DXTNI-RES
RXD1 RXD4
RXD3
RXD2
RXD1
TXD4
TXD3
TXD2
TXD1
NC
NC
SADDR
CNCN
SGND
SDA
NC
NC
SCL
VDDB
VDD
NC
NC
NC
SSTOP
VDD
10 k
10 k
5V EXT
Digital Isolator
D44TL1A0
Host
µc
PMBus
SDA
SCL
CP
D
Q
SGND
D
Flip-flop
VCC
SD
RD
Q
SCL
SDA
SGND
VDD
3 k3 k
PRI-OUT-A
PRI-OUT-B
PRI-IN-C
PRI-COM
SEC-IN-A
SEC-IN-B
SEC-OUT-C
SEC-COM
BCM EN
74LVC1G74DC
FDG6318P
EN Control
3.3V, at least 20mA
when using 4xDISO
Ref to Digital Isolator
datasheet for more details
R2 R1
-OUT
BCM
-IN BCM
PMBus™ System Diagram
Q (1) (3) V C:(V ,71 .-R)-K (5) VICOR
BCM® Bus Converter Rev 1.4
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BCM6123x60E10A5yzz
The BCM uses a high-frequency resonant tank to move energy
from primary to secondary and vice versa. The resonant LC tank,
operated at high frequency, is amplitude modulated as a function
of the primary voltage and the secondary current. A small amount
of capacitance embedded in the primary and secondary stages of
the module is sufficient for full functionality and is key to achieving
high power density.
The BCM6123x60E10A5yzz can be simplified into the model
shown in Figure 19.
At no load:
K represents the “turns ratio” of the BCM.
Rearranging Equation 1:
In the presence of a load, VSEC is represented by:
and ISEC is represented by:
RSEC represents the impedance of the BCM, and is a function of
the RDS_ON of the primary and secondary MOSFETs and the winding
resistance of the power transformer. IPRI_Q represents the quiescent
current of the BCM controller, gate drive circuitry and core losses.
The effective DC voltage transformer action provides additional
interesting attributes. Assuming that RSEC = 0Ω and
IPRI_Q = 0A, Equation 3 now becomes Equation 1 and is essentially
load independent, resistor R is now placed in series with VPRI.
The relationship between VPRI and VSEC becomes:
Substituting the simplified version of Equation 4
(IPRI_Q is assumed = 0A) into Equation 5 yields:
This is similar in form to Equation 3, where RSEC is used to represent
the characteristic impedance of the BCM. However, in this case a
real resistor, R on the primary side of the BCM is effectively scaled
by K2 with respect to the secondary.
Assuming that R = 1Ω, the effective R as seen from the secondary
side is 28mΩ, with K = 1/6.
+
+
VSEC
VPRI
V•I
K
+
+
CPRI_INT
11.2µF
IPRI_Q
140mA
1/6 • ISEC 1/6 • VPRI
CPRI_INT_ESR
0.75mΩ
CSEC_INT
202µF
CSEC_INT_ESR
81µΩ
LPRI_IN_LEADS
6.7nH
LSEC_OUT_LEADS
0.64nH
RSEC
1.62mΩ
ISEC
0.24nH
5mΩ
R
BCM
K = 1/6
VPRI
VSEC
+
Figure 20 — K = 1/6 BCM with series primary resistor
Figure 19 — BCM AC model
BCM in a ChiP™
V
SEC
= V
PRI
K(1)
K =
V
SEC
V
PRI
(2)
ISEC =
I
PRI
– I
PRI_Q
K
(4)
V
SEC
= V
PRI
• K – I
SEC
• R
SEC
(3)
V
SEC
= (V
PRI
– I
PRI
• R)K(5)
VSEC = VPRI • K – ISEC • R • K2(6)
u dV dz C dV (8) P 5mm” : P MUN ’ P Dmimrzo : P I'KIJN ’ (10) P my; ’ P (11) VICOR
BCM® Bus Converter Rev 1.4
Page 24 of 29 07/2018
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A similar exercise can be performed with the additon of a capacitor
or shunt impedance at the primary of the BCM. A switch in series
with VPRI is added to the circuit. This is depicted in Figure 21.
A change in VPRI with the switch closed would result in a change in
capacitor current according to the following equation:
Assume that with the capacitor charged to VPRI, the switch is
opened and the capacitor is discharged through the idealized
BCM. In this case,
substituting Equation 1 and 8 into Equation 7 reveals:
The equation in terms of the secondary has yielded a K2 scaling
factor for C, specified in the denominator of the equation.
A K factor less than unity results in an effectively larger capacitance
on the secondary when expressed in terms of the primary. With
K = 1/6 as shown in Figure 21, C = 1µF would appear as
C = 36µF when viewed from the secondary.
Low impedance is a key requirement for powering a high-current,
low-voltage load efficiently. A switching regulation stage
should have minimal impedance while simultaneously providing
appropriate filtering for any switched current. The use of a BCM
between the regulation stage and the point of load provides a
dual benefit of scaling down series impedance leading back to
the source and scaling up shunt capacitance or energy storage
as a function of its K factor squared. However, these benefits are
not achieved if the series impedance of the BCM is too high. The
impedance of the BCM must be low, i.e., well beyond the crossover
frequency of the system.
A solution for keeping the impedance of the BCM low involves
switching at a high frequency. This enables the use of small
magnetic components because magnetizing currents remain low.
Small magnetics mean small path lengths for turns. Use of low-loss
core material at high frequencies also reduces core losses.
The two main terms of power loss in the BCM are:
No load power dissipation (PPRI_NL): defined as the power
used to power up the module with an enabled powertrain
at no load.
Resistive loss (PRSEC): refers to the power loss across
the BCM modeled as pure resistive impedance.
Therefore,
The above relations can be combined to calculate the overall
module efficiency:
C
S
BCM
K = 1/6
VPRI
VSEC
+
Figure 21 — BCM with primary capacitor
IC (t) = C
dV
PRI
dt
(7)
ISEC(t) = (9)
C
K 2
dV
SEC
dt
I
C
= I
SEC
K(8)
P
DISSIPATED
= P
PRI_NL
+ P
RSEC
(10)
P
SEC_OUT
= P
PRI_IN
– P
DISSIPATED
= P
PRI_IN
– P
PRI_NL
– P
RSEC
(11)
P
SEC_OUT
PPRI_IN
P
PRI_IN
– P
PRI_NL
– P
RSEC
PPRI_IN
VPRI • IPRI – PPRI_NL(ISEC)2 • RSEC
VPRI • IPRI
PPRI_NL + (ISEC)2 • RSEC
VPRI • IPRI
= 1 –
η =
=
=(
12)
()
T rPD-Q :T VICOR
BCM® Bus Converter Rev 1.4
Page 25 of 29 07/2018
BCM6123x60E10A5yzz
Input and Output Filter Design
A major advantage of BCM systems versus conventional PWM
converters is that the transformer based BCM does not require
external filtering to function properly. The resonant LC tank,
operated at extreme high frequency, is amplitude modulated as a
function of primary voltage and secondary current and efficiently
transfers charge through the isolation transformer. A small amount
of capacitance embedded in the primary and secondary stages
of the module is sufficient for full functionality and is key to
achieving power density.
This paradigm shift requires system design to carefully evaluate
external filters in order to:
Guarantee low source impedance:
To take full advantage of the BCM’s dynamic response, the
impedance presented to its primary terminals must be low from
DC to approximately 5MHz. The connection of the bus converter
module to its power source should be implemented with minimal
distribution inductance. If the interconnect inductance exceeds
100nH, the input should be bypassed with a RC damper to
retain low source impedance and stable operation. With an
interconnect inductance of 200nH, the RC damper may be as
high as 1µF in series with 0.3Ω. A single electrolytic or equivalent
low-Q capacitor may be used in place of the series RC bypass.
Further reduce primary and/or secondary voltage ripple
without sacrificing dynamic response:
Given the wide bandwidth of the module, the source response
is generally the limiting factor in the overall system response.
Anomalies in the response of the primary source will appear at
the secondary of the module multiplied by its K factor.
Protect the module from overvoltage transients imposed
by the system that would exceed maximum ratings and
induce stresses:
The module primary/secondary voltage ranges shall not be
exceeded. An internal overvoltage lockout function prevents
operation outside of the normal operating primary range. Even
when disabled, the powertrain is exposed to the applied voltage
and the power MOSFETs must withstand it.
Total load capacitance at the secondary of the BCM shall not
exceed the specified maximum. Owing to the wide bandwidth and
low secondary impedance of the module, low-frequency bypass
capacitance and significant energy storage may be more densely
and efficiently provided by adding capacitance at the primary of
the module. At frequencies <500kHz the module appears as an
impedance of RSEC between the source and load.
Within this frequency range, capacitance at the primary appears as
effective capacitance on the secondary per the relationship defined
in Equation 13.
This enables a reduction in the size and number of capacitors used
in a typical system.
Thermal Considerations
The ChiP™ module provides a high degree of flexibility in that
it presents three pathways to remove heat from the internal
power-dissipating components. Heat may be removed from the
top surface, the bottom surface and the leads. The extent to which
these three surfaces are cooled is a key component in determining
the maximum current that is available from a ChiP, as can be
seen from Figure 1.
Since the ChiP has a maximum internal temperature rating, it
is necessary to estimate this internal temperature based on a
system-level thermal solution. Given that there are three pathways
to remove heat from the ChiP, it is helpful to simplify the thermal
solution into a roughly equivalent circuit where power dissipation
is modeled as a current source, isothermal surface temperatures
are represented as voltage sources and the thermal resistances are
represented as resistors. Figure 22 shows the “thermal circuit” for a
BCM6123 ChiP in an application where the top, bottom, and leads
are cooled. In this case, the BCM power dissipation is PDTOTAL and
the three surface temperatures are represented as TCASE_TOP,
TCASE_BOTTOM, and TLEADS. This thermal system can now be very
easily analyzed using a SPICE simulator with simple resistors,
voltage sources, and a current source. The results of the simulation
provide an estimate of heat flow through the various dissipation
pathways as well as internal temperature.
Alternatively, equations can be written around this circuit and
analyzed algebraically:
Where TINT represents the internal temperature and PD1, PD2, and
PD3 represent the heat flow through the top side, bottom side, and
leads, respectively.
+
+
+
MAX INTERNAL TEMP
Power Dissipation
(W)
Thermal Resistance
Top
Thermal Resistance
Bottom
θINT-BOTTOM
θINT-TOP
θINT-LEADS
Thermal Resistance
Leads
TCASE_BOTTOM(°C) TLEADS(°C) TCASE_TOP(°C)
+
+
MAX INTERNAL TEMP
Power Dissipation
(W)
Thermal Resistance
Top
Thermal Resistance
Bottom
θINT-BOTTOM
θINT-TOP
θINT-LEADS
Thermal Resistance
Leads
TCASE_BOTTOM(°C) TLEADS(°C) TCASE_TOP(°C)
Figure 22 — Top case, bottom case and leads thermal model
Figure 23 — Top case and leads thermal model
T
INT
– PD
1
• θ
INT-TOP
= T
CASE_TOP
TINT – PD2 • θINT-BOTTOM = TCASE_BOTTO
M
TINT – PD3 • θINT-LEADS = TLEADS
PDTOTAL = PD1+ PD2+ PD3
CSEC_EXT =
C
PRI_EXT
K
2 (13)
T in) -9 :T LVN} T rPD-Q :T VICOR
BCM® Bus Converter Rev 1.4
Page 26 of 29 07/2018
BCM6123x60E10A5yzz
Figure 23 shows a scenario where there is no bottom side cooling.
In this case, the heat flow path to the bottom is left open and the
equations now simplify to:
Figure 24 shows a scenario where there is no bottom side and
leads cooling. In this case, the heat flow paths to the bottom and
leads are left open and the equations now simplify to:
Please note that Vicor has a suite of online tools, including a
simulator and thermal estimator that greatly simplify the task of
determining whether or not a BCM thermal configuration is valid
for a given condition. These tools can be found at:
http://www.vicorpower.com/powerbench.
Current Sharing
The performance of the BCM topology is based on efficient
transfer of energy through a transformer without the need of
closed loop control. For this reason, the transfer characteristic
can be approximated by an ideal transformer with a positive
temperature coefficient series resistance.
This type of characteristic is close to the impedance characteristic
of a DC power distribution system both in dynamic (AC) behavior
and for steady state (DC) operation.
When multiple BCMs of a given part number are connected in an
array, they will inherently share the load current according to the
equivalent impedance divider that the system implements from the
power source to the point of load. Ensuring equal current sharing
among modules requires that BCM array impedances be matched.
Some general recommendations to achieve matched array
impedances include:
Dedicate common copper planes within the PCB to deliver and
return the current to the modules.
Provide as symmetric a PCB layout as possible among modules
A dedicated input filter for each BCM in an array is required to
prevent circulating currents.
For further details see:
AN:016 Using BCM Bus Converters in High Power Arrays.
Fuse Selection
In order to provide flexibility in configuring power systems,
ChiP™ modules are not internally fused. Input line fusing
of ChiP products is recommended at the system level to provide
thermal protection in case of catastrophic failure.
The fuse shall be selected by closely matching system
requirements with the following characteristics:
Current rating
(usually greater than maximum current of BCM)
Maximum voltage rating
(usually greater than the maximum possible input voltage)
Ambient temperature
Nominal melting I2t
Recommend fuse: ≤40A Littelfuse 456 Series (primary side)
Reverse Operation
BCMs are capable of reverse power operation. Once the unit is
started, energy will be transferred from the secondary back to
the primary whenever the secondary voltage exceeds VPRI • K.
The module will continue operation in this fashion for as long as
no faults occur.
Transient operation in reverse is expected in cases where there is
significant energy storage on the output and transient voltages
appear on the input.
BCM®1
R0_1
ZIN_EQ1 ZOUT_EQ1
ZOUT_EQ2
VSEC
ZOUT_EQn
ZIN_EQ2
ZIN_EQn
R0_2
R0_n
BCM®2
BCM®n
Load
DC
VPRI
+
Figure 25 — BCM parallel array
+
MAX INTERNAL TEMP
Power Dissipation
(W)
Thermal Resistance
Top
Thermal Resistance
Bottom
θINT-BOTTOM
θINT-TOP
θINT-LEADS
Thermal Resistance
Leads
TCASE_BOTTOM(°C) TLEADS(°C) TCASE_TOP(°C)
Figure 24 — Top case thermal model
T
INT
PD
1
θ
INT-TOP
= T
CASE_TOP
TINT – PD3 • θINT-LEADS = TLEADS
PDTOTAL = PD1+ PD3
T
INT
– PD
1
• θ
INT-TOP
= T
CASE_TOP
PDTOTAL = PD1
“FLUKE—r W [ mm \157\ m], [- '0 \ \ rm \ Hymn“ ‘ a, i f *7, 7 o mama] ‘ rop VlEW/COMPONENYSIDE} / / mum! mm mm. [mm] ¢ \ mug ' J 1 17 u l m; {m} _ mm mm 11 mm ”mm? m m 125nm [Avumui m N “has [ 13200:? m m D A m as [ 2m 00: )i m m m: 5.1 a. [ mm 00:] mm mm VICOR
BCM® Bus Converter Rev 1.4
Page 27 of 29 07/2018
BCM6123x60E10A5yzz
25.14±.38
.990±.015
12.57
.495
30.50
1.201
61.00±.13
2.402±.005
0
00
0
TOP VIEW (COMPONENT SIDE)
2.03
.080
(9) PL.
1.02
.040
(3) PL.
2.03
.080
(9) PL.
1.02
.040
(3) PL.
11.43
.450
0
27.21
1.071
(2) PL.
17.09
.673
(2) PL.
7.94
.312
(2) PL.
1.49
.058
(2) PL.
18.05
.710
(2) PL.
23.64
.931
(2) PL.
21.94
.864
(2) PL.
12.52
.493
(2) PL.
3.37
.132
(2) PL.
6.76
.266
(2) PL.
20.84
.820
(2) PL.
27.55
1.085
(2) PL.
0
11.81
.465
11.81
.465
0
0
BOTTOM VIEW
.41
.016
(24) PL.
7.21±.10
.284±.004
4.17
.164
(24) PL.
SEATING
PLANE
.05 [.002]
1.52±.08
.060±.003
PLATED THRU
.25 [.010]
ANNULAR RING
(6) PL.
2.54±.08
.100±.003
PLATED THRU
.38 [.015]
ANNULAR RING
(18) PL.
0
21.94±.08
.864±.003
(2) PL.
12.52±.08
.493±.003
(2) PL.
3.37±.08
.132±.003
(2) PL.
6.76±.08
.266±.003
(2) PL.
20.84±.08
.820±.003
(2) PL.
27.55±.08
1.085±.003
(2) PL.
27.21±.08
1.071±.003
(2) PL.
17.09±.08
.673±.003
(2) PL.
7.94±.08
.312±.003
(2) PL.
1.49±.08
.058±.003
(2) PL.
18.05±.08
.710±.003
(2) PL.
23.64±.08
.931±.003
(2) PL.
0
11.81±.08
.465±.003
11.81±.08
.465±.003
0
0
+VSEC+VSEC
+VSEC
+VSEC+VSEC
+VSEC
+VSEC+VSEC
-VSEC1 -VSEC2
-VSEC1 -VSEC2
-VSEC1 -VSEC2
-VSEC1 -VSEC2
+VPRI
+VPRI
+VPRI
+VPRI
TM/SER-OUT
EN
VAUX/SER-IN
-VPRI
RECOMMENDED HOLE PATTERN
(COMPONENT SIDE)
NOTES:
1- RoHS COMPLIANT PER CST-0001 LATEST REVISION.
2- UNLESS OTHERWISE SPECIFIED
DIMENSIONS ARE : MM / [INCH]
BCM Through-Hole Package Mechanical Drawing and Recommended Land Pattern
VICDR
BCM® Bus Converter Rev 1.4
Page 28 of 29 07/2018
BCM6123x60E10A5yzz
Revision History
Revision Date Description Page Number(s)
1.0 08/26/15 Initial Release n/a
1.1 09/28/15 Changed PRI to SEC Input Quiescent Current 5
1.2 07/26/16
Added PMBus enabled product and associated related specifications
Updated electrical specifications table for forward direction
Added electrical specifications table for reverse direction
Updated figure 2
Updated figures 14 & 15
all
5, 6 & 7
8 & 9
10
18
1.3 07/28/17 Updated height specification 1, 20, 27
1.4 07/16/18 Implemented content improvements All
VIC'OR
BCM® Bus Converter Rev 1.4
Page 29 of 29 07/2018
BCM6123x60E10A5yzz
Vicor’s comprehensive line of power solutions includes high density AC-DC and DC-DC modules and
accessory components, fully configurable AC-DC and DC-DC power supplies, and complete custom
power systems.
Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for its use. Vicor
makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication. Vicor reserves
the right to make changes to any products, specifications, and product descriptions at any time without notice. Information published by
Vicor has been checked and is believed to be accurate at the time it was printed; however, Vicor assumes no responsibility for inaccuracies.
Testing and other quality controls are used to the extent Vicor deems necessary to support Vicor’s product warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
Specifications are subject to change without notice.
Visit http://www.vicorpower.com/dc-dc/isolated-fixed-ratio/lv-bus-converter-module for the latest product information.
Vicor’s Standard Terms and Conditions and Product Warranty
All sales are subject to Vicor’s Standard Terms and Conditions of Sale, and Product Warranty which are available on Vicor’s webpage
(http://www.vicorpower.com/termsconditionswarranty) or upon request.
Life Support Policy
VICOR’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE
EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL COUNSEL OF VICOR CORPORATION. As used
herein, life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and
whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to
result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform
can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. Per Vicor Terms
and Conditions of Sale, the user of Vicor products and components in life support applications assumes all risks of such use and indemnifies
Vicor against all liability and damages.
Intellectual Property Notice
Vicor and its subsidiaries own Intellectual Property (including issued U.S. and Foreign Patents and pending patent applications) relating to the
products described in this data sheet. No license, whether express, implied, or arising by estoppel or otherwise, to any intellectual property
rights is granted by this document. Interested parties should contact Vicor’s Intellectual Property Department.
The products described on this data sheet are protected by the following U.S. Patents Numbers:
6,911,848; 6,930,893; 6,934,166; 7,145,786; 7,782,639; 8,427,269 and for use under 6,975,098 and 6,984,965.
Contact Us: http://www.vicorpower.com/contact-us
Vicor Corporation
25 Frontage Road
Andover, MA, USA 01810
Tel: 800-735-6200
Fax: 978-475-6715
www.vicorpower.com
email
Customer Service: custserv@vicorpower.com
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I2C™ is a trademark of NXP Semiconductor
All other trademarks, product names, logos and brands are property of their respective owners.

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