TS81001 Datasheet by Semtech Corporation

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V. '1 SEMTECH DC 1882001 7531001 Application Processor Supply 1551001 E E 7551111 :pplicaticn Luad rocessor 1.- Transmitter Receiver
TS81001
Final Datasheet Rev 1.2
June 2, 2015
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Semtech
TS81001
TRIUNE PRODUCTS
Features
Supports Qi®, PMA and proprietary charging applications
Dual-mode Qi + PMA functionality using a single LC reso-
nant circuit
Wireless power systems up to 40W+
Compatible with variable voltage, variable frequency and
variable duty cycle transmitters
Supports indirect (fixed voltage) and single/multi-cell
battery charging applications (>2.0V)
Integrated controller and FLASH for communications and
control
High precision data converter
Low external component count
Applications
Qi® , PMA and non-standard wireless chargers for:
Cell Phones and Smartphones
GPS Devices
Digital Cameras
Tablets and eReaders
Portable Lighting
Toys
Medical devices
Industrial devices Description
High Efficiency Receiver Controller
for Wireless Power Systems
Description
The TS81001 is a power receiver communications and control
unit for wireless charging applications. The TS81001 can
support systems up to 40W+, and supports Qi® compliant,
PMA compliant and proprietary applications.
The TS81001 performs the necessary coding of packets to
send commands to the transmitter to adjust the power level
accordingly.
Specification
RISC-based controller core with flash and SRAM memory
12-bit A/D converter
Two 16-bit timers
8-bit timer
Auto-wakeup and watchdog timers
8 configurable analog general purpose IOs
Charging LED output
I2C interface
20 pin 3x3 QFN
Typical Application Circuit
MOEO o
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Pinout
(Top View)
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Pin Description
Pin # Pin Name Pin Function Description
1 NRST Reset Reset input
2SDA I2C Data I2C data
3 SCL I2C Clock I2C clock
4 VSS Power GND Power GND
5 VDD Input power Input power supply
6 EN_LOAD Load enable Output FET enable (some systems)
7 GPIO3 GPIO GPIO 3
8 LED LED output Charging LED control
9 GPIO6 GPIO GPIO 6
10 GPIO7 GPIO GPIO 7
11 GPIO8 GPIO GPIO 8
12 AMUX Analog GPIO AMUX input from TS51111
13 VREF Analog GPIO VREF input from TS51111
14 VACDET GPIO VACDET input from TS51111
15 GPIO5 Open-Drain GPIO True Open-Drain GPIO 5
16 GPIO4 Open-Drain GPIO True Open-Drain GPIO 4
17 EN_MOD GPIO EN_MOD output to TS51111
18 GPIO1 GPIO GPIO 1
19 GPIO2 GPIO GPIO 2
20 DEBUG Debug Debug interface
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Functional Block Diagram
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Symbol Parameter Min Typ Max Unit
VDD Input Operating Voltage 1.85 3.6 V
FMCU Operating Frequency 2 16 MHz
VDD Decoupling capacitor value 1 uF
LDO Decoupling capacitor value 1 uF
TA Operating Free Air Temperature -40 85 °C
TJ Operating Junction Temperature -40 105 °C
Communication Interfaces
I2C or UART communication can only take place in the following cases:
The Wireless Power Receiver is placed on the Wireless Power Transmitter and power transfer is taking place, or
External power is applied, either through the system power supply or on the TS51111 USB pin
In both cases, an internal voltage regulator inside the TS51111 provides 3.3V on the VCORE pin for the TS81001 to use.
The Applications Processor can interrogate the TS81001 using the I2C or UART interfaces. The TS81001 acknowledges its I2C Slave
Address only if it is powered. No ACK from the TS81001 after its slave address means that power transfer does not take place and
power is not applied to the TS51111 USB pin.
Absolute Maximum Ratings
Over operating free–air temperature range unless otherwise noted(1, 2, 3)
MIN MAX UNIT
VDD, VSS -0.3 4.0 V
GPIO1, GPIO2, GPIO3, VACDET, VREF, SCL, SDA, EN_MOD,
DEBUG, GPIO6, AMUX, EN_LOAD, GPIO7, LED, GPIO8, NRST VSS - 0.3 4.0 V
GPIO4, GPIO5 VSS - 0.3 VDD + 4.0 V
Operating Junction Temperature Range, TJ -40 125 °C
Storage Temperature Range, TSTG -65 150 °C
Electrostatic Discharge – Human Body Model ±2k V
Lead Temperature (soldering, 10 seconds) 260 °C
Notes:
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating condi-
tions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) ESD testing is performed according to the respective JESD22 JEDEC standard.
Recommended Operating Conditions
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I2C
I2C Signal Pins
ALERT pin (GPIO pin) - optional:
Driven high when an event is active in the internal STATUS register
Driven low when all the internal events are cleared
Note: The ALERT pin is provided to help with I2C communication, i.e. to signal events to the EC so the EC can interrogate the TS8100x via I2C.
The use of the ALERT pin is not mandatory in the application.
SCL_TXD pin:
Clock pin for the I2C interface.
True open-drain. Needs external pull-ups.
SDA_RXD pin:
Data pin for the I2C interface.
True open-drain. Needs external pull-ups.
I2C Protocol
The TS81001 Wireless Power Receiver acts as an I2C slave peripheral to allow communication with an application microcontroller.
The slave address (7 bit) is 0x49. The Embedded Controller is an I2C master and initiates every data transfer.
The TS81001 implements a set of registers available from the I2C bus. It also implements a set of API functions that receive
parameters and return values using the I2C bus. Four transfer types are possible:
Write Register
Read Register
Run API Function
Read API Function Return Buffer
Write Register Operations Description
START Start of the I2C transfer
M[SSlave Address (7 bits) 0 (1 bit) Slave ACK Slave address + R/nW bit (0x92 as 8-bit).
M[SRegister n address (8 bits) Slave ACK Address of the first register.
M[SRegister n Data (8 bits) Slave ACK Write the first register.
M[SRegister n+1 Data (8 bits) Slave ACK Optionally write the following registers.
...
M[SRegister n+k Data (8 bits) Slave ACK
STOP Stop of the I2C transfer.
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Read Register Operations Description
START Start of the I2C transfer
M[SSlave Address (7 bits) 0 (1 bit) Slave ACK Slave address + 0 as R/nW bit (0x92 as 8-bit).
M[SRegister n address (8 bits) Slave ACK Address of the first register.
START Repeated Start.
M[SSlave Address (7 bits) 1 (1 bit) Slave ACK Slave address + 1 as R/nW bit (0x93 as 8-bit).
S[MRegister n Data (8 bits) Master ACK Read the first register.
S[MRegister n+1 Data (8 bits) Master ACK Optionally read the following registers.
...
S[MRegister n+k Data (8 bits) Slave ACK The master should send a nACK after the last data byte was
received.
STOP Stop of the I2C transfer.
Run API Function Operations Description
START Start of the I2C transfer
M[SSlave Address (7 bits) 0 (1 bit) Slave ACK Slave address + R/nW bit (0x92 as 8-bit).
M[SAPI number (8 bits) Slave ACK API number.
M[SAPI input buffer length m (8 bits) Slave ACK API input buffer length. Equal to 0 if no input buffer data is
required by the API.
M[SInput buffer data[0] (8 bits) Slave ACK First byte of the input buffer (optional).
M[SInput buffer data[1] (8 bits) Slave ACK Second byte of the input buffer (optional).
...
M[SInput buffer data[m-1] (8 bits) Slave ACK Last byte of the input buffer (optional).
STOP Stop of the I2C transfer and execute the API function
Read API Function Return Buffer Description
START Start of the I2C transfer
M[SSlave Address (7 bits) 0 (1 bit) Slave ACK Slave address + R/nW bit (0x92 as 8-bit).
M[SRegister n address (8 bits) Slave ACK API number.
START Repeated Start.
M[SSlave Address (7 bits) 1 (1 bit) Slave ACK Slave address + 1 as R/nW bit (0x93 as 8-bit).
S[MAPI number (8 bits) Master ACK API number for the following return buffer.
S[MAPI return buffer length n (8 bits) Master ACK API return buffer length.
S[MOutput buffer data[0] (8 bits) Master ACK Read the first byte in the output buffer.
S[MOutput buffer data[1] (8 bits) Master ACK Optionally read the following bytes.
...
S[MOutput buffer data[n-1] (8 bits) Master nACK The master should send a nACK after the last data byte was
received.
STOP Stop of the I2C transfer.
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Internal Registers
Address Name Type Description
0x00 BOOTFW_REV_L R/W Bootloader Firmware Revision Low Register
0x01 BOOTFW_REV_H R/W Bootloader Firmware Revision High Register
0x02 FW_REV_L R/W Firmware Revision Low Register
0x03 FW_REV_H R/W Firmware Revision High Register
0x04 MODE_L R/W Operating Mode Low Register
0x05 MODE_H R/W Operating Mode High Register
0x06 RESET_L R/W Reset Low Register
0x07 RESET_H R/W Reset High Register
0x08 STATUS R Main Status Register
0x09 STATUS0 R Status0 Register
0x0A STATUS1 R Status1 Register
0x0B STATUS2 R Status2 Register
0x0C STATUS3 R Status3 Register
0x0D-0x7F RESERVED. Will be defined later.
Bootloader Firmware Revision Low Register (BOOTFW_REV_L)
Address: 0x00
Reset value: Minor version number of the bootloader firmware
76543210
REV_L[7:0]
rrrrrrrr
Bits 7:0 REV_L[7:0]: Bootloader Firmware Revision Low
These bits contain the minor version number of the bootloader firmware.
Bootloader Firmware Revision High Register (BOOTFW_REV_H)
Address: 0x01
Reset value: Major version number of the bootloader firmware
76543210
REV_H[7:0]
rrrrrrrr
Bits 7:0 REV_H[7:0]: Bootloader Firmware Revision High
These bits contain the major version number of the bootloader firmware.
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Firmware Revision Low Register (FW_REV_L)
Address: 0x02
Reset value: Minor version number of the user firmware
76543210
REV_L[7:0]
rrrrrrrr
Bits 7:0 REV_L[7:0]: Firmware Revision Low
These bits contain the minor version number of the user firmware.
Firmware Revision High Register (BOOTFW_REV_H)
Address: 0x03
Reset value: Major version number of the user firmware
76543210
REV_H[7:0]
rrrrrrrr
Bits 7:0 REV_H[7:0]: Bootloader Firmware Revision High
These bits contain the major version number of the user firmware.
Operating Mode Low Register (MODE_L)
Address: 0x04
Reset value: Depends on the bootloader mode and the firmware type
76543210
Res BOOTLDR
r
Bits 7:1 Reserved
Bit 0 BOOTLDR: Bootloader mode
0: The user firmware is running
1: The controller is in bootloader mode
Operating Mode High Register (MODE_H)
Address: 0x05
Reset value: Depends on the bootloader mode and the firmware type
76543210
Res
Bits 7:0 Reserved
Reset Low Register (RESET_L)
Address: 0x06
Reset value: 0x00
76543210
RESET_KEY_L[7:0]
wwwwwwww
Bits 7:0 RESET_KEY_L[7:0]: Reset Key
0x55: generate a system reset. Both the RESET_L and the RESET_H registers have to be written
with the correct key to generate a reset.
Any other value: a system reset is not generated.
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Reset High Register (RESET_H)
Address: 0x07
Reset value: 0x00
76543210
RESET_KEY_H[7:0]
wwwwwwww
Bits 7:0 RESET_KEY_H[7:0]: Reset Key
0xAA: generate a system reset. Both the RESET_L and the RESET_H registers have to
be written with the correct key to generate a reset.
Any other value: a system reset is not generated.
Main Status Register (STATUS)
Address: 0x08
Reset value: 0xC0
76543210
CTS CTS_API Res STATUS3 STATUS2 STATUS1 STATUS0
rw rw rw rw rw rw
Bit 7 CTS: Clear To Send
This bit indicates if a new command can be issued to the controller.
0: The controller is busy processing a previous command. New commands should
not be sent to the controller.
1: The controller can accept a new command over the communication interface.
Bit 6 CTS_API: Clear to Send for API
This bit indicates if a new API call can be issued to the controller.
0: The controller is busy processing a previous API call. New API calls should not be
sent to the controller.
1: The controller can accept a new API call over the communication interface.
Bits 5:4 Reserved
Bit 3 STATUS3: STATUS3 Event Flag
0: No event is signaled in the STATUS3 register
1: An event is signaled in the STATUS3 register
Bit 2 STATUS2: STATUS2 Event Flag
0: No event is signaled in the STATUS2 register
1: An event is signaled in the STATUS2 register
Bit 1 STATUS1: STATUS1 Event Flag
0: No event is signaled in the STATUS1 register
1: An event is signaled in the STATUS1 register
Bit 0 STATUS0: STATUS0 Event Flag
0: No event is signaled in the STATUS0 register
1: An event is signaled in the STATUS0 register
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API Functions
API Number API Name Description
0x80 BOOTLOADER_UNLOCK_FLASH Allow changes to the FLASH memory
0x81 BOOTLOADER_WRITE_BLOCK Write a page into the FLASH memory
0x82 BOOTLOADER_CRC_CHECK Check the CRC of the user firmware
0x83-0xFE RESERVED. Will be defined later.
0xFF API_ERROR
Value returned in the API field when a Read API Function
Return Buffer command is issued and the API function called
previously has generated an error.
Bootloader Unlock Flash (BOOTLOADER_UNLOCK_FLASH)
API number: 0x80
Input buffer size: TBD
Output buffer size: 1
Buffer Parameter Length (bytes) Description
Input buffer TBD
Return data buffer ERROR_CODE 1
Bootloader Write Block (BOOTLOADER_WRITE_BLOCK)
API number: 0x81
Input buffer size: 66
Output buffer size: 1
Buffer Parameter Length (bytes) Description
Input buffer Block Number 2 Block index. The first block has an index of 0.
Block Data 64 Data to be written to the FLASH page.
Return data buffer ERROR_CODE 1
Bootloader CRC Check (BOOTLOADER_CRC_CHECK)
API number: 0x82
Input buffer size: 0
Output buffer size: 1
Buffer Parameter Length (bytes) Description
Return data buffer ERROR_CODE 1
API Error Codes
Error Code Error Code Name Description
0x00 ERROR_GENERIC Generic error.
0x01 ERROR_OK Operation succeeded. This is not indicating an error.
0x02 ERROR_INVALID_CRC CRC error.
0x03 ERROR_FLASH_UNLOCK_FAILED FLASH unlocking has failed.
0x04 ERROR_API_NOT_IMPLEMENTED The API number is not implemented.
0x05 ERROR_API_DATA_OVERFLOW The API input buffer has been filled with more data than
its length.
0x06 ERROR_API_INVALID_PARAMETERS At least one of the API parameters is invalid.
0x07-0xFF RESERVED. Will be defined later.
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Application Schematic
Figure 1: TS81001 Application Schematic
AC 1
AC 2COIL
J2
1uF
6.3V
C16
100nF
50V
C1
100nF
50V
C12
10uF
25V
C3
GND
22nF
50V
C10
22nF
50V
C6
VCORE
1.8nF
50V
C8
100nF
10V
C17
10uF
6.3V
C13
0.020
R2
GND
10uF
6.3V
C14
GND
+
1
-
2Out
J1
5.6V
D2
PDC
TP7
PDC
EN_MOD
VACDET
SDA
SCL
AMUX
TP8
AMUX
PACKP
VAC1
VAC2
PACKS
AGND
AGND GND
100pF
50V
C7
10uF
25V
C4
10nF
10V
C15
GNDGNDGND
AGND
VCORE
SCL
EN_MOD
SDA
VACDET
RESET
DEBUG
AGND
10K
R4
2nF
10V
C18
VCORE
RESET
SCL
SDA
DEBUG
AGND
MOD2
35 MOD1
34
AGND 33
AMUX
30
SCL
27
EN_MOD
1
USB36
PACKN32
VREF 29
SDA
26
PACKS4
TXD
2UART
31
THERM
25
VCORE24
PACKP6
RXD
3
OVP21
BST1
23
PDC7
PDC13
PDC14
BST2
22
VAC1
8
VAC1
11
VAC2
15
VAC2
16
VAC2
20
PGND 17
PGND 10
PGND 18
PAD37
VACDET
19
PACKP_K5
PGND 9
VAC1
12
NC 28
U1
TS51111_QFN36
VREF
NP
D1
150
R5
1
2
3
4
D5
AMUX
AGND
LEDG
LEDR
TP9
USB
10uF
25V
C5
47nF 50V
C2
68nF 50V
C9
68nF 50V
C11
GND
LEDG
LEDR
TP1
TP2
TP3
TP4
TP5
TP6
TP10
VAC1
VREF
USB
100
R1
GND
VAC1
VAC2
10K (NP)
R3
D3
BAT54CW (NP) 5.1V (NP)
D4
GND
VCORE
NRST
1
GPIO1
2
GPIO2
3
VSS
4
LDO
5VDD
6
GPIO3
7
GPIO58
GPIO49
VACDET 10
VREF 11
SCL12
SDA13
EN_MOD 14
DEBUG
15
GPIO616
AMUX 17
EN_LOAD18
GPIO719
LED20
U2
TS81000-QFN
1uF
6.3V
C19
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Package Dimensions
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QFN Package (Top marking)
Legend:
Line 1 Marking: L151 Internal part code
Line 2 Marking: SS Assembly site identifier
LL Lot trace code
Line 3 Marking: D Assembly year
WW Assembly week
Y Additional marking
o Pin 1 Identifier
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Ordering Information
Part Number Description
TS81001-QFNR Bootloader programmed device
RoHS and Reach Compliance
Triune Systems is fully committed to environmental quality.
All Triune Systems materials and suppliers are fully compliant
with RoHS (European Union Directive 2011/65/EU), REACH
SVHC Chemical Restrictions (EC 1907/2006), IPC-1752 Level
3 materials declarations, and their subsequent amendments.
Triune Systems maintains certified laboratory reports for
all product materials, from all suppliers, which show full
compliance to restrictions on the following:
Cadmium (Cd)
Chlorofluorocarbons (CFCs)
Chlorinate Hydrocarbons (CHCs)
Halons (Halogen free)
Hexavalent Chromium (CrVI)
Hydrobromofluorocarbons (HBFCs)
Hydrochlorofluorocarbons (HCFCs)
Lead (Pb)
Mercury (Hg)
Perfluorocarbons (PFCs)
Polybrominated biphenyls (PBB)
Polybrominated Diphenyl Ethers (PBDEs)
a SEMTECH
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Contact Information
Semtech Corporation
200 Flynn Road, Camarillo, CA 93012
Phone: (805) 498-2111, Fax: (805) 498-3804
www.semtech.com
IMPORTANT NOTICE
Information relating to this product and the application or design described herein is believed to be reliable, however such information is provided as a
guide only and Semtech assumes no liability for any errors in this document, or for the application or design described herein. Semtech reserves the right
to make changes to the product or this document at any time without notice. Buyers should obtain the latest relevant information before placing orders
and should verify that such information is current and complete. Semtech warrants performance of its products to the specifications applicable at the time
of sale, and all sales are made in accordance with Semtechs standard terms and conditions of sale.
SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES
OR SYSTEMS, OR IN NUCLEAR APPLICATIONS IN WHICH THE FAILURE COULD BE REASONABLY EXPECTED TO RESULT IN PERSONAL INJURY, LOSS OF LIFE
OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. INCLUSION OF SEMTECH PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN
SOLELY AT THE CUSTOMER’S OWN RISK. Should a customer purchase or use Semtech products for any such unauthorized application, the customer shall
indemnify and hold Semtech and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and attorney
fees which could arise.
The Semtech name and logo are registered trademarks of the Semtech Corporation. All other trademarks and trade names mentioned may be marks and
names of Semtech or their respective companies. Semtech reserves the right to make changes to, or discontinue any products described in this document
without further notice. Semtech makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any
particular purpose. All rights reserved.
© Semtech 2015

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