HV7351 Datasheet by Microchip Technology

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Supertex inc.
Supertex inc.
Supertex inc.
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HV7351
Doc.# DSFP-HV7351
NR050213
Features
Eight channels with return to zero
Up to ±70V output voltage
±3.0A output current
Store up to four different patterns
Independent programmable delays
Single 11x11 QFN-80 package
Application
Medical ultrasound imaging
NDT, non-destructive testing
Arbitrary pattern generator
High speed PIN diode driver
General Description
The Supertex HV7351 is an 8-channel programmable high
voltage ultrasound transmit beamformer. Each channel is
capable of swinging up to ±70V with an active discharge back
to 0V. The outputs can source and sink more than 3.0A to
achieve fast output rise and fall times. The active discharge is
also capable of sourcing and sinking 3.0A for a fast return to
ground. The topology of the HV7351 will significantly reduce
the number of I/O logic control lines needed.
Each pulser has four associated 64-bit shift registers for
storing pre-determined transmit patterns and a 10-bit delay
counter for controlling the transmit time. One of four arbitrary
patterns can be transmitted with adjustable delay, depending
on the data loaded into these shift registers and the delay
counter. The delay counter can be clocked up to 200MHz,
allowing incremental delays down to 5ns.
Eight Channel Programmable
High Voltage Ultrasound Transmit Beamformer
Tx128
Trigger
Tx127
Tx3
Tx2
Tx1t
DELAY1
Trigger
HV7351
8-channel
U1
HV7351
8-channel
U2
HV7351
8-channel
U16
t
DELAY2
t
DELAY3
t
DELAY127
t
DELAY128
E3
E1
E2
E127
E128
Array
Probe
Typical Application Circuit
Absolute Maximum Ratings L:Lo|Nu YV:Yea ww:w A:Ass C:C0 Typical Thermal Resistance F!
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Doc.# DSFP-HV7351
NR050213
Ordering Information
Part Number Package Option Packing
HV7351K6-G 80-Lead QFN (11x11) 176/Tray
Absolute Maximum Ratings
Absolute Maximum Ratings are those values beyond which damage to the
device may occur. Functional operation under these conditions is not implied.
Continuous operation of the device at the absolute rating level may affect
device reliability. All voltages are referenced to device ground.
Pin Configuration
Package Marking
1
80
L = Lot Number
YY = Year Sealed
WW = Week Sealed
A = Assembler ID
C = Country of Origin
= “Green” Packaging
HV7351K6
LLLLLLLLL
YYWW
AAA CCC
80-Lead QFN
80-Lead QFN
(top view)
Package may or may not include the following marks: Si or
Parameter Value
VLL, Positive logic supply -0.5V to 5.5V
DVDD, Positive logic supply voltage -0.5V to 5.5V
PVDD, Positive gate drive supply voltage -0.5V to 5.5V
AVDD, Positive analog supply voltage -0.5V to 5.5V
PVSS, Negative gate drive supply voltage +0.5V to -5.5V
VPP
, High voltage positive supply voltage -0.5V to +80V
VNN, High voltage negative supply voltage +0.5V to -80V
(VPP - VNN), Differential high voltage supply +160V
VPF, Positive floating supply voltage VPP - 6.0V to VPP
VNF, Negative floating supply voltage VNN to VNN +6.0V
VRP
, Positive supply for VNF regulator 0V to 15V
VRN, Negative supply for VPF regulator 0V to -15V
Operating temperature -40°C to +125°C
Storage temperature -65°C to +150°C
Operating Supply Voltages
(TJ = 25°C unless otherwise specified)
Sym Parameter Min Typ Max Units Conditions
VPP Positive high voltage supply 3.0 - 70 V ---
VNN Negative high voltage supply -70 - -3.0 V ---
VLL Logic interface voltage 2.85 3.30 3.6 V ---
AVDD
Low voltage positive analog
supply voltage 4.75 5.00 5.25 V ---
DVDD
Low voltage positive digital
supply voltage 4.75 5.00 5.25 V ---
PVDD
Low voltage positive gate drive
supply voltage 4.75 5.00 5.25 V ---
PVSS
Low voltage negative gate drive
supply voltage -5.25 -5.00 -4.75 V ---
Typical Thermal Resistance
Package θja
80-Lead QFN 14OC/W
-G denotes a lead (Pb)-free / RoHS compliant package
TCK
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Doc.# DSFP-HV7351
NR050213
Sym Parameter Min Typ Max Units Conditions
VRP
Low voltage positive supply for
VNF regulator 4.75 - 12 V ---
VRN
Low voltage negative supply for
VPF regulator -12 - -4.75 V ---
TCK Reference voltage logic trip
point for TCK pin 0.4VLL 0.5VLL 0.6VLL V ---
ITCK TCK input current - - ±10 μA VTCK = 0 to VLL
Regulator Outputs
(Operating conditions unless otherwise specified, VLL = 3.3V, AVDD = DVDD = PVDD = VRP = 5.0V, PVSS = VRN = -5.0V, VPP = +70V, VNN = -70V, TJ =25ºC)
Sym Parameter Min Typ Max Units Conditions
VPF
Positive floating gate drive
voltage VPP -5.25 VPP -5.00 VPP -4.00 V 4.0µF ceramic capacitor across
VPF and VPP
VNF
Negative floating gate drive
voltage VNN +4.00 VNN +5.00 VNN +5.25 V 4.0µF ceramic capacitor across
VNF and VNN
Electrical Characteristics
(Operating conditions unless otherwise specified, VLL =3.3V, AVDD = DVDD = PVDD = VRP = 5.0V, PVSS = VRN = -5.0V, VPP = +70V, VNN = -70V, TJ = 25ºC)
Sym Parameter Min Typ Max Units Conditions
IVLLQ VLL quiescent current - 384 500 µA EN = Low, all inputs are static
IAVDDQ AVDD quiescent current - 12 30
µA EN = Low, all inputs are staticIDVDDQ DVDD quiescent current - 12 30
IPVDDQ PVDD quiescent current - 70 100
IVRPQ VRP quiescent current - 0.3 6.0 µA EN = Low, all inputs are static
IVRNQ VRN quiescent current - -0.01 6.0
IPVSSQ PVSS quiescent current -85 -45 - µA EN = Low, all inputs are static
IVPPQ VPP quiescent current - 2.6 6.0 µA EN = Low, all inputs are static
IVNNQ VNN quiescent current - -1.6 6.0
IVLLEN VLL enabled quiescent current - 390 500 µA EN = High, all inputs are static
IAVDDEN AVDD enabled quiescent current - 600 800 µA EN = High, all inputs are static
IDVDDEN DVDD enabled quiescent current - 22 55
IPVDDEN PVDD enabled quiescent current - 44 100 µA EN = High, all inputs are static
IVRPEN VRP enabled quiescent current - 450 650 µA EN = High, all inputs are static
IVRNEN VRN enabled quiescent current -650 -350 -
IPVSSEN PVSS enabled quiescent current -100 -44 - µA EN = High, all inputs are static
IVPPEN VPP enabled quiescent current - 370 620 µA EN = High, all inputs are static
IVNNEN VNN enabled quiescent current -620 -420 -
Operating Supply Voltages (cont.)
(TJ = 25°C unless otherwise specified)
VH7: +5. CW= Hw on TCK, 57mm Set-up txme E siu (:52 Set-up txme m
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Sym Parameter Min Typ Max Units Conditions
IVLLCW VLL current at TCK = 80MHz - 500 - µA VPP = +5.0V, VNN = -5.0V, EN = High,
CW = High, 80MHz on TCK, 0.5VLL
on TCK, all 8 channels active at
5.0MHz, No load
IDVDDCW DVDD current at CW = 5MHz - 25 - mA
IVPPCW VPP current at CW = 5MHz - 141 - mA
IVNNCW VNN current at CW = 5MHz - 98 - mA
AC Electrical Characteristics
(Operating conditions unless otherwise specified, VLL = 3.3V, AVDD = DVDD = PVDD = VRP = 5.0V, PVSS = VRN = -5.0V, VPP = +70V, VNN = -70V, TJ = 25ºC)
Sym Parameter Min Typ Max Units Conditions
fTCK Transmit clock frequency 0 - 200 MHz ---
fSCK Serial clock frequency 0 - 80 MHz No daisy chain
0 - 70 Daisy chained
tSU-DIN Set-up time data in to SCK 2.0 1.0 - ns ---
tH-DIN Hold time SCK to data in 2.0 1.0 - ns ---
tSU-CS1 Set-up time CS1 low to SCK 2.0 - - ns ---
tSU-CS2 Set-up time CS2 low to SCK 2.0 - - ns ---
tSU-TRIG Set-up time TRIG low to TCK 2.0 - - ns ---
tW-TRIG TRIG pulse width 2TCK - - - ---
tLHDO
SCK to data out low to high
delay time
3.0 9.0 12 ns For DOUT1
3.0 9.0 10 For DOUT2
tHLDO
SCK to data out high to low
delay time
3.0 9.0 12 ns For DOUT1
3.0 9.0 10 For DOUT2
tWA1A0 A1A0 pulse width tW-TRIG +40 - -
ns ---
tSUA1A0
Set-up time A1A0 to TRIG rising
edge - 20 -
tHA1A0
Hold time A1A0 to TRIG falling
edge - 20 -
tEN-ON Device enable time - 1.0 - ms 1.0µF capacitor on every VPF and
VNF pin.
tEN-OFF Device disable time - - 100 ns ---
tr1 Output rise time from 0V to +HV - 9.0 13
ns Load = 330pF//2.5kΩ
tf1 Output fall time from 0V to -HV - 9.0 13
tr2
Damping output rise time from
-HV to 0V - 9.0 13
tf2
Damping output fall time from
+HV to 0V - 9.0 13
tr3 Output rise time from -HV to +HV - 17 23
tf3 Output fall time from +HV to -HV - 17 23
trcw CW output rise time - 9.0 16 ns VPP = +5.0V, VNN = -5.0V,
Load = 330pF//2.5kΩ
tfcw CW output fall time - 9.0 16
Electrical Characteristics (cont.)
(Operating conditions unless otherwise specified, VLL =3.3V, AVDD = DVDD = PVDD = VRP = 5.0V, PVSS = VRN = -5.0V, VPP = +70V, VNN = -70V, TJ = 25ºC)
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Doc.# DSFP-HV7351
NR050213
Sym Parameter Min Typ Max Units Conditions
tdr1
Output propagation delay rise
time 1 10.85 13.35 15.85
ns No Load.
tdf1
Output propagation delay fall
time 1 11.35 13.85 16.35
tdr2
Output propagation delay rise
time 2 11.25 13.75 16.25
tdf2
Output propagation delay fall
time 2 11.75 14.25 16.75
tdr3
Output propagation delay rise
time 3 11.35 13.85 16.35
tdf3
Output propagation delay fall
time 3 11.45 13.95 16.45
tdcwlh
CW output propagation delay
time from low to high 10.45 12.95 15.45
ns VPP = +5.0V, VNN = -5.0V,
No Load
tdcwhl
CW output propagation delay
time from high to low 10.35 12.85 15.35
Δtdcwhl Delay time matching - ±0.7 - ns P to N, channel-to-channel matching
tJCW Delay jitter on rise or fall - 13 - ps VPP = +5.0V, VNN = -5.0V, Load = 50Ω
LAT Latency 3.5TCK 3.5TCK 3.5TCK - ---
Output P-channel MOSFET to VPP
, CW = 0
IOUT Output saturation current 2.2 3.2 - A ---
RON Output ON-resistance - 4.2 - ΩIOUT = 100mA
COSS Output capacitance - 62 - pF VPP - VOUT = 25V, f = 1.0MHz
Output N-channel MOSFET to VNN, CW = 0
IOUT Output saturation current - -3.2 -2.2 A ---
RON Output ON-resistance - 2.4 - ΩIOUT = -100mA
COSS Output capacitance - 50 - pF VNN - VOUT = -25V, f = 1.0MHz
Output P-channel MOSFET to VPP
, CW = 1
IOUT Output saturation current 1.2 1.5 - A ---
RON Output ON-resistance - 8.0 - ΩIOUT = 100mA
COSS Output capacitance - 62 - pF VPP - VOUT = 25V, f = 1.0MHz
Output N-channel MOSFET to VNN, CW = 1
IOUT Output saturation current - -1.5 -1.2 A ---
RON Output ON-resistance - 6.6 - ΩIOUT = -100mA
COSS Output capacitance - 50 - pF VNN - VOUT = -25V, f = 1.0MHz
AC Electrical Characteristics (cont.)
(Operating conditions unless otherwise specified, VLL =3.3V, AVDD = DVDD = PVDD = VRP = 5.0V, PVSS = VRN = -5.0V, VPP = +70V, VNN = -70V, TJ = 25ºC)
Tux ’rcx TTK fl
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NR050213
Sym Parameter Min Typ Max Units Conditions
Damping P-channel MOSFET to PGND
IOUT Output saturation current 2.2 3.2 - A ---
RON Output ON-resistance - 4.0 - ΩIOUT = 100mA
COSS Output capacitance - 62 - pF VPP - VOUT = 25V, f = 1.0MHz
Damping N-channel MOSFET to PGND
IOUT Output saturation current - -3.2 -2.2 A ---
RON Output ON-resistance - 2.3 - ΩIOUT = -100mA
COSS Output capacitance - 50 - pF VNN - VOUT = -25V, f = 1.0MHz
Logic Inputs
ITCK Input current for TCK - ±1.0 - µA VTCK = 0 to VLL
VIH Input logic high voltage for TCK TCK
+0.15 TCK VLL V Only for TCK input, TCK = 0.5VLL
VIL Input logic low voltage for TCK 0 TCK TCK
-0.15 V Only for TCK input, TCK = 0.5VLL
VIH Input logic high voltage 0.8VLL - VLL V For all logic inputs except TCK
VIL Input logic low voltage 0 - 0.2VLL V For all logic inputs except TCK
IIH Input logic high current - - 1.0 µA ---
IIL Input logic low current -1.0 - - µA ---
VOL Output logic low voltage 0 - 0.7 V IOUT = 0 to -10mA
VOH Output logic high voltage VLL -0.7 - VLL V IOUT = 0 to 10mA
CIN Input logic capacitance - - 5.0 pF ---
AC Electrical Characteristics (cont.)
(Operating conditions unless otherwise specified, VLL =3.3V, AVDD = DVDD = PVDD = VRP = 5.0V, PVSS = VRN = -5.0V, VPP = +70V, VNN = -70V, TJ = 25ºC)
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NR050213
Logic Truth Table
Mode
Inputs Outputs
Comments
EN CW 10-bit
Counter INV NIN PIN N-ch P-ch RTZ
Non-CW mode.
Outputs not inverted.
Outputs are con-
trolled by data in the
shift registers
1 0 X X 0 0 OFF OFF ON
RTZ (return-to-zero) is activat-
ed when NIN and PIN are both
low. Output is pulled to ground
through a series diode.
1 0 X 0 0 1 OFF ON OFF
Not inverted. Logic 1 in the
P-channel register turns on the
output P-channel MOSFET.
1 0 X 0 1 0 ON OFF OFF
Not inverted. Logic 1 in the
N-channel register turns on the
output N-channel MOSFET.
1 0 X X 11 OFF OFF OFF
Avoids cross over current. A
logic 1 in both P- and N-chan-
nel registers will put the output
in a Hi-Z state.
Non-CW mode.
Outputs are inverted.
Outputs are con-
trolled by data in the
shift registers
1 0 X 1 0 1 ON OFF OFF Inverted, for harmonic imaging
1 0 X 1 1 0 OFF ON OFF Inverted, for harmonic imaging
CW mode.
Output follows fcw
1 X All 1 X X X OFF OFF OFF
Off channels are the ones with
all 1’s in their respective 10-bit
counters. Output follows the fCW
signal. Shift registers for NIN
and PIN should remain static to
save power.
1 1 Not all 1 X X X OFF/
ON
ON/
OFF OFF
Device Disabled 0 X X X X X OFF OFF OFF Hi-Z state
SIZE a m" o In » TCK P-ch RegImrs N-ch Regmm 24m Re I Panel" 24ch Re I Pam". 151mm Reglsher Pntem 2 “In—h“ Re Ism Plflem 24m Rzgl Panel" : um Re I Pntem 16IJZ-lzlt Ra Ism Panel" um Regl Pntem 4
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Block Diagram
INV
EN/LD
CW
CLK
16/32 bit
Serial
Shift Reg.
INV
EN/LD
CW
CLK
16/32 bit
Serial
Shift Reg.
INV
EN/LD
CW
CLK
16/32 bit
Serial
Shift Reg.
INV
EN/LD
CW
CLK
16/32 bit
Serial
Shift Reg.
Divide
by 2
6-bit Counter
Divide by N
N = 1 to 64
Linear
Regulator
Linear
Regulator
EN
EN
10-bit Delay
Counter
Divide
by 2
VLL to VDD
Translator
-
+
PGND
PGND
VPF
VPF
VNF
VNF
PVSS
PVDD
PVSS
PVDD
VPP
VPF
VRN
VRP
VNF
VNN
VPP
Tx1
VNN
PGND
PVDD
PVSS
VPP
Tx8
VNN
PGND
CW
fCW
PIN
NIN
Control
Logic
CW
fCW
PIN
NIN
Control
Logic
RTZ GATE Driver
Supply Voltages
6-bit Counter
Divide by N
N = 1 to 64
ENEN
10-bit Delay
Counter
8 10-bit Registers
for Delay Counters 6-bit for
Divide by N
16/32-bit Register
Pattern 4
16/32-bit Register
Pattern 3
16/32-bit Register
Pattern 2
16/32-bit Register
Pattern 1
16/32-bit Register
Pattern 4
16/32-bit Register
Pattern 3
16/32-bit Register
Pattern 2
16/32-bit Register
Pattern 1
P-ch Registers N-ch Registers
Decoder
VPF
VRN
VPP
VNF
VNN
VRP
VLL
AVDD
DVDD
EN
SIZE
CS1
SCK
DIN1
DOUT1
A0
A1
DIN2
DOUT2
CS2
CW
INV
TRIG
TCK
TCK
DGND
AGND
VSUB
'—
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Timing Diagram 1
TCk
0V
3.3V
Trig
Tx1
0V
+70V
Internal CLK
(for N=2)
0V
Example with Tx2 delay having
two TCk cycles more than Tx1
TCk = 1.65V (0.5V
LL
)
Tx2
Delay time set by
Tx2 10 bit counter
Delay time set by
Tx1 10-bit counter
tWTRIG needs to be at least
2 rising edges of TCk
0V
3.3V
0V
3.3V
-70V
+70V
-70V
3.5 TCk cycles
tWTRIG
tSU-TRIG
tdr1 tdf2
tdf1
tr1 tf2
tdr2
10%10%
90% 90%
10%10%
90% 90%
tf1 tr2
Timing Diagram 2
Example with Tx2 delay having
one TCk cycle more than Tx1
Delay time set by
Tx2 10 bit counter
3.5 TCk cycles
t
SU-TRIG
t
WTRIG
needs to be at least
2 rising edges of TCk
t
WTRIG
Delay time set by
Tx1 10-bit counter
t
df3
90%
10%10%
90%
t
f3
t
r3
t
dr3
TCk
0V
3.3V
Trig
Tx1
0V
+70V
Internal CLk
(for N=2)
0V
TCk = 1.65V (0.5V
LL
)
Tx2
0V
3.3V
0V
3.3V
-70V
+70V
-70V
E diagram of the patt e 4 programmable _ r patterns can be — pins, A1 and A0. 32 bits fol P-ch Pallern1 n. Each pattern / \/ \ pin determines \\ \\ H will set the p litto 16 bltsw K 5 high G
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Loading Data into the Four 16/32 bit Pattern Registers
2 to 4
Decoder
D
OUT
1
SCK
D
IN
1
SIZE
EN
DIN
SCK
SIZE
16/32 bits
Shift Register
P-ch. Pattern 1
CS1
16/32 bits
Shift Register
P-ch. Pattern 2
16/32 bits
Shift Register
P-ch. Pattern 3
16/32 bits
Shift Register
P-ch. Pattern 4
16/32 bits
Shift Register
N-ch. Pattern 4
16/32 bits
Shift Register
N-ch. Pattern 3
16/32 bits
Shift Register
N-ch. Pattern 2
16/32 bits
Shift Register
N-ch. Pattern 1
SIZE
EN
DIN
SCK
Size
EN
DIN
SCK
Size
EN
DIN
SCK
A1 A0 CS1
A1 A0 CS1
A1 A0 CS1
A1 A0 CS1
A1
A0
A1 A0 CS1
A1 A0 CS1
A1 A0 CS1
A1 A0 CS1
A detailed circuit diagram of the pattern registers is shown
above. There are 4 programmable patterns that can be
stored. One of four patterns can be selected via the two in-
put logic decoder pins, A1 and A0. Data can be loaded on
the selected pattern. Each pattern can be either 16 or 32
bits wide. The SIZE pin determines whether they are 16 or
32 bits wide. SIZE = H will set the pattern to be 32 bits wide
while SIZE = L will set it to 16 bits wide. DIN1 is the input data
for the register. When CS1 is high, data will not be shifted in.
Data is shifted in only when CS1 is low.
With SIZE = H, the circuit is effectively a 64-bit serial shift
register. The data first enters into the P-channel register and
continues to be shifted though to the N-channel register.
Data is clocked in during the rising edge of the clock. There
is no activity during the falling edge of the clock. The data,
DIN1, enters from the P-channel register and exits from the
N-channel register from DOUT1.
For size = High, 32 bits wide (size = Low, 16-bits wide)
A1 = A0 = Low, Pattern 1 selected
CS1 = Low, data can be shifted in
64-bit serial shift register: 32 bits for the P-channel and
32 bits for the N-channel
Data is shifted in during the rising edge of the clock. S1 is
the first bit shifted in, entering the P-channel register. After
64 clock cycles, S1 will be located in the N-channel register
as shown below. It will also be clocked out to DOUT1.
A 2-to-4 decoder is provided to select which of the four pat-
terns is to be used for all of the outputs. Logic inputs A1 and
A0 determine which patterns are selected per the decoder
truth table shown below. Once A1 and A0 are set, a rising
edge on the trigger logic input pin will automatically load the
selected pattern to all of the outputs.
Decoder Truth Table
D
OUT
1
D
IN
1
SCK
S64 S63 S34 S33 S32 S31 S2 S1
32 bits for P-ch Pattern 1 32 bits for N-ch Pattern 1
32 bits for
P-ch Pattern 1
32 bits for
N-ch Pattern 1
Logic Decoder Input Pattern Selected
A1 A0
001
012
103
114
Pattern Register Circuit Diagram
Loading D and the D Each output 0 delay counter divide-by-N c TX frequenc and the divi is provided. registers us Cisz is high m ../— ._/—
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Loading Data into the Delay Counters
and the Divide-by-N Counter
Each output channel, TX, has its own programmable 10-bit
delay counter. For 8 channels, 80 bits are needed. A 6-bit
divide-by-N counter is also provided to program the desired
TX frequency. To program all the individual delay counters
and the divide-by-N counter, an 86-bit serial shift register
is provided. It uses the same clock input that the pattern
registers uses. DIN2 is the input data for this register. When
CS2 is high, data will not be shifted in. Data is shifted in only
when CS2 is low.
As shown below, the data first enters into the 10-bit regis-
ter for the TX8 delay counter and continues to be shifted
though to the 6-bit register for the divide by N counter. Data
is clocked in during the rising edge of the clock. There is no
activity during the falling edge of the clock. The MSB bit in
the 6-bit divide-by-N register is clocked out into DOUT2 for
cascading multiple devices if desired.
10-Bit Delay Counter
The input clock for the 10-bit delay counter is the TCK pin.
The TCK pin is the only pin that is capable of high frequency,
200MHz. This helps maximum delay time resolution. The
counter counts upward. Please refer to the table below.
10 bits Tx8
86-bit Serial Shift Register: 80 bits for the delay counters and 6 bits for the divide by N
10 bits Tx7 6 bits
divide by N
10 bits Tx6 10 bits Tx5 10 bits Tx4 10 bits Tx310 bits Tx210 bits Tx1
10 bits for Tx8 delay Counter 10 bits for Tx7 delay Counter 6 bits for divide by N
D
OUT
2
S86 S85 S84 S83 S82 S81 S80 S79 S78 S77 S76 S75 S74 S73 S72 S71 S70 S69 S68 S67 S6 S5 S4 S3 S2 S1
LSB MSB LSB MSB LSB MSB
D
IN
2
SCK
MSB LSB Delay Time
0000000000 1023 TCK cycles
0000000001 1022 TCK cycles
0000000010 1021 TCK cycles
0000000011 1020 TCK cycles
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
1111111100 3 TCK cycles
1111111101 2 TCK cycles
1111111110 1 TCK cycle
1 1 1 1 1 1 1 1 1 1 No trigger
Delay Counter Table
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6-Bit Divide-by-N Counter
The input clock for the 6-bit divide-by-N counter is the TCK
pin. It generates the clock frequency for the 16/32 bit serial
shift register for the output P- and N-channel patterns. Each
clock cycle will set the TX output to be either at VPP
, VNN,
ground, or high impedance depending on what was prepro-
grammed in their corresponding registers.
MSB LSB Output Shift Register
Clock Frequency
000000 fTCK ÷ 64
000001 fTCK ÷ 63
000010 fTCK ÷ 62
000011 fTCK ÷ 61
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
111100 fTCK ÷ 4
111101 fTCK ÷ 3
111110 fTCK ÷ 2
111111 fTCK ÷ 1
Pin Name Description
1 AVDD Positive analog supply voltage (+5.0V).
2 DIN2 Serial data in for delay counters and frequency divider.
3 CS2 Activates DIN2. Input logic high = off, input logic low = on.
4 SIZE Sets pattern width to either 16-bits or 32-bits. Logic low = 16-bits, logic high = 32-bits.
5 INV Inverts the TX output waveform. See logic truth table for details.
6 CW Activates CW mode. Logic low = non-CW mode, logic high = CW mode. See logic truth table for details.
7 DOUT2 Data out for delay counters and frequency divider.
8 EN Enables and disables device. Logic low = off, logic high = on.
9 SCK Serial clock input for serial shift registers.
10 DVDD Positive digital supply voltage (+5.0V).
11 DGND Digital ground.
12 TRIG
Toggles all TX outputs to transmit. Needs to be high for 2 rising edges of TCK. Delay counters will
start on the rising edge of the TCK pin right after the falling edge of the TRIG signal. See timing
diagram for details.
13 TCK Transmitter clock for the delay counters and input frequency for the divide by N. Can be CMOS,
LVDS, or SSTL.
14 TCK Logic trip point TCK. Can be set to a DC value from 0.4VLL to 0.6VLL or driven differentially with TCK.
15 VLL Logic interface supply voltage (3.0V or 3.3V).
16 CS1 Activates DIN1. Input logic high = off, input logic low = on.
17 DOUT1 Data out for P-channel and N-channel pattern registers.
Pin Description
13
HV7351
Supertex inc.
www.supertex.com
Doc.# DSFP-HV7351
NR050213
Pin Description (cont.)
Pin Name Description
18 A0 Decoded to select 1 of 4 patterns to be loaded.
19 A1
20 DIN1 Serial data in for P-channel and N-channel pattern registers.
21 VRN Negative supply for VPF regulator (-5.0V).
22 PVDD Positive gate drive supply voltage for RTZ output transistors (+5.0V).
23 PGND Power ground path for RTZ output transistors.
24 PGND
25 PVSS Negative gate drive supply voltage for RTZ output transistors (-5.0V).
26 VPF Linear regulator output gate drive voltage for the P-channel output transistors. A low voltage 1.0µF
ceramic capacitor needs to be connected across every VPF and VPP pin. There are four in total.
27 NC No connection.
28 VNF Linear regulator output gate drive voltage for the N-channel output transistors. A low voltage 1.0µF
ceramic capacitor needs to be connected across every VNF to VNN pins. There are four in total.
29 VNN Negative high voltage supply (-3.0V to -70V).
30 TX1 Transmit pulser outputs for channel 1.
31 VPP Positive high voltage supply (+3.0V to +70V).
32 VPP
33 TX2 Transmit pulser outputs for channel 2.
34 VNN Negative high voltage supply (-3.0V to -70V).
35 VNN
36 TX3 Transmit pulser outputs for channel 3.
37 VPP Positive high voltage supply (+3.0V to +70V).
38 VPP
39 TX4 Transmit pulser outputs for channel 4.
40 VNN Negative high voltage supply (-3.0V to -70V).
41 VNN
42 VNF Linear regulator output gate drive voltage for the N-channel output transistors. A low voltage 1.0µF
ceramic capacitor needs to be connected across every VNF to VNN pins. There are four in total.
43 DGND Digital ground.
44 VPP Positive high voltage supply (+3.0V to +70V).
45 VPF Linear regulator output gate drive voltage for the P-channel output transistors. A low voltage 1.0µF
ceramic capacitor needs to be connected across every VPF and VPP pin. There are four in total.
46 PGND Power ground path for RTZ output transistors.
47 PVSS Negative gate drive supply voltage for RTZ output transistors (-5.0V).
48 PGND Power ground path for RTZ output transistors.
49 PVDD Positive gate drive supply voltage for RTZ output transistors (+5.0V).
14
HV7351
Supertex inc.
www.supertex.com
Doc.# DSFP-HV7351
NR050213
Pin Name Description
50 DVDD Positive digital supply voltage (+5.0V).
51 DGND Digital ground.
52 PVDD Positive gate drive supply voltage for RTZ output transistors (+5.0V).
53 PGND Power ground path for RTZ output transistors.
54 PVSS Negative gate drive supply voltage for RTZ output transistors (-5.0V).
55 PGND Power ground path for RTZ output transistors.
56 VPF Linear regulator output gate drive voltage for the P-channel output transistors. A low voltage 1.0µF
ceramic capacitor needs to be connected across every VPF and VPP pin. There are four in total.
57 VPP Positive high voltage supply (+3.0V to +70V).
58 DGND Digital ground.
59 VNF Linear regulator output gate drive voltage for the N-channel output transistors. A low voltage 1.0µF
ceramic capacitor needs to be connected across every VNF to VNN pins. There are four in total.
60 VNN Negative high voltage supply (-3.0V to -70V).
61 VNN
62 TX5 Transmit pulser outputs for channel 5.
63 VPP Positive high voltage supply (+3.0V to +70V).
64 VPP
65 TX6 Transmit pulser outputs for channel 6.
66 VNN Negative high voltage supply (-3.0V to -70V).
67 VNN
68 TX7 Transmit pulser outputs for channel 7.
69 VPP Positive high voltage supply (+3.0V to +70V).
70 VPP
71 TX8 Transmit pulser outputs for channel 8.
72 VNN Negative high voltage supply (-3.0V to -70V).
73 VNF Linear regulator output gate drive voltage for the N-channel output transistors. A low voltage 1.0µF
ceramic capacitor needs to be connected across every VNF to VNN pins. There are four in total.
74 NC No connection.
75 VPF Linear regulator output gate drive voltage for the P-channel output transistors. A low voltage 1.0µF
ceramic capacitor needs to be connected across every VPF and VPP pin. There are four in total.
76 PVSS Negative gate drive supply voltage for RTZ output transistors (-5.0V).
77 PGND Power ground path for RTZ output transistors.
78 PGND
79 PVDD Positive gate drive supply voltage for RTZ output transistors (+5.0V).
80 VRP Positive supply for VNF regulator (+5.0V).
VSUB Exposed center pad. Needs to be externally connected to digital ground, DGND.
Pin Description (cont.)
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Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
©2013
Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
15
HV7351
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-HV7351
NR050213
80-Lead QFN Package Outline (K6)
11.00x11.00mm body, 1.00mm height (max), 0.50mm pitch
Seating
Plane
Top View
Side View
Bottom View
View B
1
80
D
E
1
80
Note 1
(Index Area
D/2 x E/2)
Note 1
(Index Area
D/2 x E/2)
e
b
D2
E2
Note 3
Note 2
L
L1
View B
A
A1
A3
θ
Symbol A A1 A3 b D D2 E E2 e L L1 θ
Dimension
(mm)
MIN 0.80 0.00 0.20
REF
0.18 10.90 9.50 10.90 9.50 0.50
BSC
0.30 0.00 0O
NOM 0.90 0.02 0.25 11.00 9.65 11.00 9.65 0.40 - -
MAX 1.00 0.05 0.30 11.10 9.75 11.10 9.75 0.50 0.15 14O
Drawings are not to scale.
Supertex Doc.#: DSPD-80QFNK611X11P050, Version A111511
Notes:
1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded
metal marker; or a printed indicator.
2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present.
3. The inner tip of the lead may be either rounded or square.

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