MP6922 Datasheet by Monolithic Power Systems Inc.

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"IFS?
MP6922
Dual Fast Turn-off Intelligent Controller
MP6922 Rev. 1.25 www.MonolithicPower.com 1
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© 2016 MPS. All Rights Reserved.
The Future of Analog IC Technology
DESCRIPTION
The MP6922 is a dual fast turn-off intelligent
controller to drive two N-CH power MOSFETs
in LLC resonant converters for synchronous
rectification.
The IC regulates the forward voltage drop of the
power switch to about 70mV and turns it off
before the voltage goes negative.
MP6922 has a light-load function to latch-off the
gate driver at light load condition, during which
only about 600μA quiescent current is
consumed.
The fast turn-off speed of MP6922 makes both
CCM and DCM driving available. An internal
Reverse Current Protection (RCP) function
ensures safe operation of the MOSFETs in high
frequency CCM condition.
MP6922 requires a minimum number of readily
available standard external components and is
available in SOIC8E, SOIC8 or SOIC14
package.
FEATURES
Works with both Standard and Logic Level
FETs
Compatible with Energy Star, 0.5W Standby
Requirements
V
DD Range From 8V to 24V
70m VDS Regulation Function (1)
Fast Turn-off Total Delay of 20ns
Reverse Current Protection Function
Max 300kHz Switching Frequency
Light Load Mode Function (1) with <600uA
Quiescent Current
Supports CCM, CrCM and DCM Operation
Mode
Available in SOIC8E, SOIC8 or SOIC14
package
APPLICATIONS
AC-DC Adapter
LCD & PDP TV
Telecom SMPS
A
ll MPS parts are lead-free and adhere to the RoHS directive. For MPS green
status, please visit MPS website under Quality Assurance.
“MPS” and “The Future of Analog IC Technology” are Registered Trademarks of
Monolithic Power Systems, Inc.
Notes:
1) Related issued patent: US Patent US8,067,973; US8,400,790.
CN Patent ZL201010504140.4; ZL200910059751.X. Other
patents pending.
TYPICAL APPLICATION
Q1
Q2
S
2S
1
L
s
C
s
Lm
T
Cin
Cout
VOUT
V
D2
VG2 VG1
VS2 VS
EN
PGND
VDD
C1
R1
MP6922
1
2
3
45
6
7
8
VD
EN Signal
GND
1
1
Q1
Q2
S
2S
1
L
s
Cs
L
m
T
Cin
Cout
VOUT
C1
MP6922
EN Signal
NC
VS1
EN
1
2
3
4
5
69
10
11
12
13
14
RCP
78
NC
VD1
VG1
VS2
V
DD
LL
VD2
VG2
GND
R1
R3
R
PGND PGND
R2
C2
4
SOIC8E SOIC14
MP5“
MP6922—DUAL FAST TURN-OFF INTELLIGENT CONTROLLER
MP6922 Rev. 1.25 www.MonolithicPower.com 2
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ORDERING INFORMATION
Part Number Package Top Marking
MP6922DN* SOIC8E MP6922
MP6922DS** SOIC14 MP6922
MP6922DSE*** SOIC8 MP6922
*For Tape & Reel, add suffix –Z (e.g. MP6922DN–Z);
For RoHS Compliant Packaging, add suffix –LF; (e.g. MP6922DN–LF–Z)
**For Tape & Reel, add suffix –Z (e.g. MP6922DS–Z);
For RoHS Compliant Packaging, add suffix –LF; (e.g. MP6922DS–LF–Z)
***For Tape & Reel, add suffix –Z (e.g. MP6922DSE–Z);
For RoHS Compliant Packaging, add suffix –LF; (e.g. MP6922DSE–LF–Z)
PACKAGE REFERENCE
TOP VIEW
PGND
EN
VDD
1
2
3
45
7
8
MP6922
SOIC-8
6
V
D2
VG
V
V
V
G2
D1
SS
1
TOP VIEW
PGND
EXPOSED PAD
( SOIC8 N ONLY)
VD1
EN VDD
1
2
3
45
7
8
MP6922
SOIC-8E
6
V
D2
VG
V
S1
V
S2
VG2
D1
S1
1
TOP VIEW
V
S1
EN
1
2
3
4
5
69
10
11
12
13
14
RCP
78
NC
MP6922
SOIC-14
VD1
VG1
VS2
PGND
VDD
LL
V
D2
VG2
PGND
NC
SOIC8 SOIC8E SOIC14
ABSOLUTE MAXIMUM RATINGS (2)
VDD to VS1,VS2, VSS ........................ -0.3V to +26V
PGND to VS1,VS2, VSS ................... -0.3V to +0.3V
VG1 to VS1, VSS ................................. -0.3V to VDD
VG2 to VS2, VSS ................................. -0.3V to VDD
VD1 to VS1, VSS ............................. -0.7V to +180V
VD2 to VS2, VSS ............................. -0.7V to +180V
LL, EN to VS1,VS2, VSS .................. -0.3V to +6.5V
Maximum Operating Frequency ............ 300 kHz
Continuous Power Dissipation .. (TA = +25°C) (3)
SOIC8E ...................................................... 2.5W
SOIC14 ...................................................... 1.5W
SOIC8 ........................................................ 1.4W
Junction Temperature ............................... 150C
Lead Temperature (Solder)....................... 260C
Storage Temperature .............. -55°C to +150C
Recommended Operation Conditions (4)
VDD to VS1,VS2, VSS............................... 8V to 24V
Operating Junction Temp. (TJ). ... -40°C to +125°C
Thermal Resistance (4) θJA θJC
SOIC8 ..................................... 90 ...... 45 ... C/W
SOIC8E ................................... 50 ...... 10 ... C/W
SOIC14 ................................... 86 ...... 38 ... C/W
Notes:
2) Exceeding these ratings may damage the device.
3) TA=+25. The maximum allowable power dissipation is a
function of the maximum junction temperature TJ (MAX), the
junction-to-ambient thermal resistance θJA, and the ambient
temperature TA. The maximum allowable continuous powe
r
dissipation at any ambient temperature is calculated by PD
(MAX) = (TJ (MAX)-TA)/θJA. Exceeding the maximum allowable
power dissipation will cause excessive die temperature, and
the regulator will go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
4) The device is not guaranteed to function outside of its
operating conditions.
5) Measured on JESD51-7, 4-layer PCB. Without heatsink.
MP5“
MP6922—DUAL FAST TURN-OFF INTELLIGENT CONTROLLER
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ELECTRICAL CHARACTERISTICS
VDD = 12V, TA= +25C, unless otherwise noted.
Parameter Symbol Conditions Min Typ Max Units
VDD Voltage Range 8 24 V
VDD UVLO Threshold Rising 5.0 6.0 7.0 V
Hysteresis 0.5 1 1.5 V
Quiescent Current Iq VD1-VS1=-0.5V,
VD2-VS2=-0.5V 4 6 mA
Shutdown Current VDD=20V, EN=0V 600 µA
Light-load Mode Current 600 µA
Thermal shutdown
(6)
150 oC
Thermal Shutdown hysteresis
(6) 30 oC
Enable Shutdown Threshold Rising 1.1 1.5 1.9 V
Hysteresis 0.2 0.4 V
Enable UVLO Threshold Rising 2.5 3 3.5 V
Hysteresis 0.2 V
Internal Pull-up Current on EN 10 15 µA
CONTROL CIRCUITRY SECTION
VS1,2 –VD1,2 forward voltage Vfwd 55 70 85 mV
Turn-on delay TDon C
LOAD = 5nF 150 ns
TDon C
LOAD = 10nF 250 ns
Input bias current on VD1,2 pin VD1,2 = 180V 1 µA
Minimum on-time TMIN C
LOAD = 5nF 1 µs
Minimum off-time TOFF 1.6 µs
Light-load-enter delay TLL-Dela
y
R
LL=100k 120 150 µs
Light-load-enter pulse width TLL R
LL=100k 2.2 µs
Light-load turn on pulse width
hysteresis TLL-H R
LL=100k 0.2 µs
Light-load-enter off period
width TLL-OFF R
LL=100k 50 µs
Light-load mode exit pulse
width threshold (VD1
,
2-VS1
,
2) VLL-DS -400 -250 mV
Light-load mode enter pulse
width threshold (VG1
,
2-VS1
,
2) (6) VLL-GS 1.0 V
Reverse Current Protection
threshold VRCP 3 V
Reverse Current Protection
latch time TRCP 100 µs
GATE DRIVER SECTION
VG1
2 (Low) ILOAD=1mA 0.05 0.1 V
VG1,2 (High) VDD >16V 14 V
VDD <16V VDD-2.2
Turn off threshold (VS1,2-VD1,2)
(6) -30 mV
Turn-off propagation delay VD1
,
2=VSS 15 ns
Turn-off total delay TDoff
TDoff
VD1,2 =VSS, CLOAD=5nF,
RGATE=0 35 ns
VD1,2 =VSS, CLOAD=10nF,
RGATE=0 45 ns
Pull down impedance 1 2
MP6922- DUAL FAST TURN-OFF INTELLIGENT CONTROLLER
MPS CONFIDENTIAL AND PROPRIETARY INFORMATION – INTERNAL USE ONLY
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Pull down current
(6)
3V <VG1
2<10V 3 A
6) Guaranteed by Design and Characterization
MP5“ threshold,
MP6922—DUAL FAST TURN-OFF INTELLIGENT CONTROLLER
MP6922 Rev. 1.25 www.MonolithicPower.com 5
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PIN FUNCTIONS
Pin #
(SOIC8) Pin #
(SOIC8E) Pin #
(SOIC14) Name Description
1 1 2 VG2 FET 2 gate driver output
3 2 3 EN
Enable Pin. When EN pin voltage is larger than EN Shutdown threshold,
the internal logic of the IC is start but the gate driver will be latched until
the EN pin voltage has exceed the EN UVLO threshold
4 3 6 VD2 FET 2 drain voltage sense
- 4 7 VS2 Source pin used as reference for VD2
- 5 8 VS1 Source pin used as reference for VD1
6 6 9 VD1 FET 1 drain voltage sense
7 7 12 VDD Supply Voltage
8 8 13 VG1 FET 1 gate driver output
2 EXPOSE
D PAD 1,14 PGND Power Ground, return for power switch
- - 5,10 NC No Connection
- - 4 LL Light load timing setting. Connect a resistor to set the light load timing
- - 11 RCP Reverse Protection function, internal 5V reference.
5 - - VSS Common source pin used as reference for both channels
I'I'IPS' TEMPERATURE (”C) TEMPERATURE (“(3) TEMPERATURE (”c) SHUTDOWN CURRENT (pA) TEMPERATURE (“0) TEMPERATURE (“0)
MP6922—DUAL FAST TURN-OFF INTELLIGENT CONTROLLER
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TYPICAL PERFORMANCE CHARACTERISTICS
VDD = 12V, unless otherwise noted.
VDD UVLO Rising vs.
Temperature Quiescent Current vs.
Temperature
Vfwd vs. TemperatureShutdown Current (VDD=20V)
vs. Temperature
VD1,2 Breakdown Voltage
vs. Temperature
225
230
235
240
245
250
255
260
265
-50-30 -10 10 30 50 70 90110130150
BREAKDOWN VOLTAGE ( V)
5.7
5.75
5.8
5.85
5.9
5.95
6
6.05
6.1
6.15
-50 -30 -10 10 30 50 70 90110130150
VDD UVLO RISING( V)
3
3.2
3.4
3.6
3.8
4
4.2
4.4
4.6
4.8
-50 -30 -10 10 30 50 70 90 110130150
QUIESCENT CURRENT (mA)
370
380
390
400
410
420
430
440
450
-50 -30 -10 10 30 50 70 90110 130150 -50 -30 -10 10 30 50 70 90110130150
VFWD (mV)
68
68.5
69
69.5
70
70.5
71
71.5
72
l'lll'5‘ Zus/div.
MP6922—DUAL FAST TURN-OFF INTELLIGENT CONTROLLER
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VDD = 12V, unless otherwise noted.
Operation in 180W LLC
Converter
V
IN
=220Vac, V
OUT
=12V, I
OUT
=15A
Operation in 180W LLC
Converter
V
IN
=240Vac, V
OUT
=12V, I
OUT
=15A
V
DS1
20V/div.
V
GS1
5V/div.
V
DS2
20V/div.
V
GS2
5V/div.
V
DS1
20V/div.
V
GS1
5V/div.
V
DS2
20V/div.
V
GS2
5V/div.
V
DS1
20V/div.
V
GS1
5V/div.
V
DS2
20V/div.
V
GS2
5V/div.
Operation in 180W LLC
Converter
V
IN
=260Vac, V
OUT
=12V, I
OUT
=15A
MP5“ I: ] Proleclian —[J —[J |_ Logic [II—'— E1 i @532," Comma, Protecfion J Switcher Comparator Driver Von Driver F'I
MP6922—DUAL FAST TURN-OFF INTELLIGENT CONTROLLER
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BLOCK DIAGRAM
VDD
EN
VD1
VS1
VD2
VG1
VG2
PGND
VS2
RCP LL
Figure 1—Functional Block Diagram
OPERATION
The MP6922 supports operation in DCM, CCM
and CrCM condition. Operating in either a DCM
or CrCM condition, the control circuitry controls
the gate in forward mode and will turn the gate
off when the MOSFET current is fairly low. In
CCM operation, the control circuitry turns off the
gate when very fast transients occur.
Blanking
The control circuitry contains blanking function.
When it pulls the MOSFET on/off, it makes sure
that the on/off state at least lasts for some time.
The turn on blanking time is ~1us, which
determines the minimum on-time. During the turn
on blanking period, the turn off threshold is not
totally blanked, but changed to ~+100mV
(instead of 30mV). This assures that the part can
always be turned off even during the turn on
blanking period. (Albeit slower, so it is not
recommended to set the synchronous period less
than 1μs at
CCM condition in LLC converter, otherwise shoot
through may occur)
VD Clamp
Because VD1,2 can go as high as 180V, a High-
Voltage JFET is used at the input. To avoid
excessive currents when Vg goes below -0.7V, a
small resistor is recommended between VD1,2 pin
and the drain of the external MOSFET.
Under-Voltage Lockout (UVLO)
When VDD is below UVLO threshold, the part falls
into sleep mode and Vg is pulled down by a
10k resistor.
Enable pin
If EN is pulled low, the part is in sleep mode.
Thermal shutdown
If the junction temperature of the IC exceeds
150oC, Vg will be pulled low and the part
I'I'IPS'
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stops switching. The part will return to normal
operation after the junction temperature has
dropped to 120oC.
Turn-on Phase
When the switch current flows through the body
diode of the MOSFET, there will be a negative
VDS (VD-VSS) across it (<-500mV), the VDS is
much lower than the turn on threshold of the
control circuitry (-70mV), which then turns on the
MOSFET after 200ns turn-on delay (defined in
Fig.2).
As soon as the turn on threshold (-70mV) is
triggered, a blanking time (Minimum on-time:
~1us) will be added during which the turn off
threshold will be changed from 0mV to +50mV.
This blanking time can help to avoid error trigger
on turn off threshold caused by the turn on
ringing of the synchronous power switch.
+30mV
-70mV
2V
VDS
VGS
Flag
Turn On
Delay Turn Off
Delay
Turn On
Blanking
Driver begin to
be pulled down
~1us
Driver turn off
Off threshold
changes to
+100mV during
blanking time
+100mV
Figure 2—Turn on and Turn off delay
Conducting Phase
When the MOSFET is turned on, VDS (-ISD X
rDS(ON)) becomes to rise according to the drop of
the switch current (ISD) , as soon as VDS rises
above the turn on threshold (-70mV), the control
circuitry stops pulling up the gate driver and the
driver voltage of the MOSFET dropped, which
makes the on resistance rDS(ON) of the MOSFET
becomes larger. By doing that, VDS (-ISD x rDS(ON))
is adjusted to be around -70mV even when the
switch current ISD is fairly small, this function can
make the turn off threshold (0mV) of the internal
driver never triggered until the current through
the MOSFET has dropped to near zero.
Turn-off Phase
When VDS rises to trigger the turn off threshold
(30mV), the driver voltage of the switch is pulled
to
low after about 20ns turn off delay (defined in
Fig.4) by the control circuitry. Similar with turn-on
phase, a 1.6us blanking time is added after the
switch is turned off, during which the MOSFET is
never turned on to avoid error trigger.
Fig.3 show the MP6922 operation at heavy load
condition. Due to the high current, the driver
voltage will be saturated at first. After VDS goes to
above -70mV, driver voltage decreases to adjust
the VDS to typical -70mV.
Fig.4 show the MP6922 operation at light load
condition. Due to the low current, the driver
voltage never saturates but begins to decrease
as soon as the synchronous power switch is
turned on and adjust the VDS.
Figure 3—Synchronous Rectification
Operation at heavy load
Figure 4Synchronous Rectification
Operation at light load
I'III'E‘
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Light-load Latch-off Function
The gate driver of MP6922 is latched to save the
driver loss at light-load condition to improve light
load efficiency.
Latch off during Normal Operation
When the MOSFET conducting period during
each switching cycle keeps lower than 2.2us (TLL),
the MP6922 falls into light-load mode and latches
off the MOSFET after 120us delay (light-load-
enter delay, TLL-Delay)
After falling into light-load mode, MP6922
monitors the MOSFET’s body diode conducting
period by sensing VDS (when VDS exceeds -
250mV (VLL-DS), MP6922 considers the
MOSFET’s body diode conducting period
finishes). If the MOSFET’s body diode
conducting period is longer than ~2.4us (TLL+TLL-
H), the light-load mode is finished and the
MOSFET is unlatched to restart the synchronous
rectification.
For SOIC14 package MP6922 with LL pin, the
TLL could be adjusted by an external resistor:
LL
LL
R
T2.2s
100k

Latch off during Burst Operation
The IC also monitors the synchronous MOSFET
off period, if the off period is longer than the light-
load-enter off period width (TLL-OFF), MP6922
enters light-load mode and latches off the gate
driver.
The gate driver is unlatched when the drain-
source voltage of the synchronous MOSFET VDS
drops below -70mV.
Reverse Current Protection Function
When the LLC system operates in CCM with very
high frequency, the synchronous current may get
reverse before the IC turns off the gate driver
which leads to shoot through (in center-tapped
output with full-wave rectification topology).
MP6922 has protection function to latch off the
gate driver when the current reverses before the
driver signal is pulled low.
When the synchronous current reverses, the high
spike can be observed between Drain-Source of
MOSFET. The MP6922 monitors the voltage by
RCP pin through a voltage divider. When the
voltage of RCP pin exceeds VRCP, MP6922 will
latch the driver signal of both channels for
~100us (TRCP) to protect the synchronous
MOSFET. At the end of TRCP, MP6922 restarts
the synchronous rectification.
4,>‘_1 H,“— I'I'IPS' WWW .W. ”fir“ m. 51 1 W 131$.” F u 31 L i H. 1h. .
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TYPICAL APPLICATION CIRCUIT
AGND
AGND
AGND
PGND
PGND
AGND
AG N D AGND
54
L1
AGND
3
2
4
1
6
7
8
5
T1
N ET00039 CS
Vcc
Vcc
Bu rs t
CS CS
6
CT
3
BO
7
LA TC H
8
FSET
4
BU R S T
5
SS
1
TIM ER
2
LG 11
SW 14
GND 10
N.C. 13
Vcc 12
BST 16
HG 15
PFC 9
U1
HR1000
VD 2
3VD1 6
VS2
4
EN
2
VS 1 5
VDD 7
VG 2
1VG1 8
U2
MP 6922DN
NC
5
VD2
6
PGND
1
VG2
2
NC 10
RCP 11
VD 1 9
PGND 14
VG 1 13
EN
3
VS2
7VS1 8
VDD 12
LL
4
U3
MP6922DS
PGND PGND
PGND
Vg 1
Vg2
Vg1Vg2
PGND
VD1
VD2
VS1
VS2
VS2
Vg1
Vg2
VS1 VD1
Burst
PGND
VD2
10R23
0
R4
2.21KR2
820K
R3
9.53K
R1
3.57K
R5
1M
R6
10K
R7
1M
R8
10R10
10R9
10KR1 2
10KR11
1
R14
1
R1 5
1
R13
1K
R16
51
R17
1K
R21
1K
R22
10KR25
10KR27
10
R28
10R26
10
R24
10K
R19
2K
R2 0
100K
R18
10K
R2 9
137K
R30
10K
R36
38.3K
R35
3.3K
R3 1
1K
R34
1.8K
R33
40.2K
R3 2
1
2
CN1
1
2
CN2
SS-5-1A
21 F1
34
21 CR1
1uF
C1
0.47uF
C2
470pF
C3
10nF
C4
100n
C7
2.2uF
C8
12
100uF
C9
10nF
C1 0
33 n F
CX1
2.2nFC1 3
2.2nFC14
1nF
C1 2
2.2uF
C15
470pF
C1 9
0.1uFC2 1
22nF
C1 6
10uF
C1 7
12
2200uF
C2 0
12
2200uF
C18
12
100uF
C5
12
100uF
C6
12 D1
12 D2
12
D4
1 2
D5
1 2
D6
23
1M2
23
1M1
12
43
U4
PC817A
1
2
3
U5
1nF
C1 1
1 2
D3
4
5, 6, 7, 8
1, 2, 3
M3
4
5, 6 , 7 , 8
1, 2, 3
M4
1nF
C22
1n F
C23
Vg1
Vg2
Vs1
Vs2
VD1
VD2
VDD
VDD
PGND
VD2
3VD1 6
4
EN
2
VS S 5
VDD 7
VG2
1VG1 8
U6
MP6922DSE
PGND
Figure 5Synchronous Rectification in LLC with MP6922
MP5“ 0.10 4.00 i 0.124(115) H HEFH TOP VIEW 0.051030) EI: H L 0.00 0.00 o. 013 o. as) FRONT VIEW RECOMMENDED LAND PATTERN " SIDE VIEW #— DETAIL"A"
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PACKAGE INFORMATION
SOIC8E (EXPOSED PAD)
SEE DETAIL "A"
0.0075(0.19)
0.0098(0.25)
0.050(1.27)
BSC
0.013(0.33)
0.020(0.51)
SEATING PLANE
0.000(0.00)
0.006(0.15)
0.051(1.30)
0.067(1.70)
TOP VIEW
FRONT VIEW
SIDE VIEW
BOTTOM VIEW
NOTE:
1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN
BRACKET IS IN MILLIMETERS.
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS.
3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH
OR PROTRUSIONS.
4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING)
SHALL BE 0.004" INCHES MAX.
5) DRAWING CONFORMS TO JEDEC MS-012, VARIATION BA.
6) DRAWING IS NOT TO SCALE.
0.089(2.26)
0.101(2.56)
0.124(3.15)
0.136(3.45)
RECOMMENDED LAND PATTERN
0.213(5.40)
0.063(1.60)
0.050(1.27)0.024(0.61)
0.103(2.62)
0.138(3.51)
0.150(3.80)
0.157(4.00)
PIN 1 ID
0.189(4.80)
0.197(5.00)
0.228(5.80)
0.244(6.20)
14
85
0.016(0.41)
0.050(1.27)
0o-8o
DETAIL "A"
0.010(0.25)
0.020(0.50) x 45o
0.010(0.25) BSC
GAUGE PLANE
0.51% % EH. 0500. 27) TOP VIEW EEEEEEE 4Pwfl4 L FRONT VIEW DETAIL"A" {E EE EE EE 444W EEEEEEE RECOMMENDED LAND PATTERN 7, /,—~\ 0.053(1 .35) ,’ / \ i I )3 E f R! \\ ’ j): \ _ I 0.004 0.10 SIDE VIEW NOTE:
MP6922—DUAL FAST TURN-OFF INTELLIGENT CONTROLLER
MP6922 Rev. 1.25 www.MonolithicPower.com 13
6/7/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
SOIC14
0.016(0.41)
0.050(1.27)
0o-8o
DETAIL "A"
0.010(0.25)
0.020(0.50) x 45o
SEE DETAIL "A"
0.0075(0.19)
0.0098(0.25)
0.150
(3.80)
0.157
(4.00)
PIN 1 ID
0.050(1.27)
BSC
0.013(0.33)
0.020(0.51)
SEATING PLANE
0.004(0.10)
0.010(0.25)
0.338(8.55)
0.344(8.75)
0.053(1.35)
0.069(1.75)
TOP VIEW
FRONT VIEW
0.228
(5.80)
0.244
(6.20)
SIDE VIEW
17
14 8
RECOMMENDED LAND PATTERN
0.213
(5.40)
0.063
(1.60)
0.050(1.27)
0.024(0.61)
NOTE:
1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN
BRACKET IS IN MILLIMETERS.
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS.
3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH
OR PROTRUSIONS.
4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING)
SHALL BE 0.004" INCHES MAX.
5) DRAWING CONFORMS TO JEDEC MS-012, VARIATION AB.
6) DRAWING IS NOT TO SCALE.
0.010(0.25) BSC
GAUGE PLANE
I'III‘E'
MP6922—DUAL FAST TURN-OFF INTELLIGENT CONTROLLER
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MP6922 Rev. 1.25 www.MonolithicPower.com 14
6/7/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
SOIC8
0.016(0.41)
0.050(1.27)
0
o
-8
o
DETAIL "A"
0.010(0.25)
0.020(0.50) x 45
o
SEE DETAIL "A"
0.0075(0.19)
0.0098(0.25)
0.150(3.80)
0.157(4.00)
PIN 1 ID
0.050(1.27)
BSC
0.013(0.33)
0.020(0.51)
SEATING PLANE
0.004(0.10)
0.010(0.25)
0.189(4.80)
0.197(5.00)
0.053(1.35)
0.069(1.75)
TOP VIEW
FRONT VIEW
0.228(5.80)
0.244(6.20)
SIDE VIEW
14
85
RECOMMENDED LAND PATTERN
0.213(5.40)
0.063(1.60)
0.050(1.27)
0.024(0.61)
NOTE:
1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN
BRACKET IS IN MILLIMETERS.
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS.
3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH
OR PROTRUSIONS.
4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING)
SHALL BE 0.004" INCHES MAX.
5) DRAWING CONFORMS TO JEDEC MS-012, VARIATION AA.
6) DRAWING IS NOT TO SCALE.
0.010(0.25) BSC
GAUGE PLANE

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