TMC5072 Datasheet by Trinamic Motion Control GmbH

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TMC5072 DATASHEET + chtep’“ A? \I/ aelSt ep‘" stallGuardE BLOCK DIAGRAM {I \, baa A TRINAMIC MOTION CON'IROL
POWER DRIVER FOR STEPPER MOTORS INTEGRATED CIRCUITS
TRINAMIC Motion Control GmbH & Co. KG
Hamburg, Germany
MOTION CONTROLLER
with Linear 6 Point
RAMP Generator
MOTION CONTROLLER
with Linear 6 Point
RAMP Generator DRIVER 1
DRIVER 2
TMC5072
Protection
& Diagnostics
Programmable
256 µStep
Sequencer
Programmable
256 µStep
Sequencer
Protection
& Diagnostics
Encoder
Unit
ABN Encoder
Input 2x Ref. Switches
2x Ref. Switches
SPI
UART
stallGuard2 coolStep dcStep
Power
Supply
Charge
Pump
Step/Dir
Step/Dir
Encoder
Unit
ABN Encoder
Input
Motor 1
Motor 2
TMC5072 DATASHEET
BLOCK DIAGRAM
FEATURES AND BENEFITS
Two 2-phase stepper motors
Drive Capability up to 2x 1.1A coil current (2x 1.5A peak)
Parallel Option for one motor at 2.2A (3A peak)
Motion Controller with sixPoint ramp
Voltage Range 4.75… 26V DC
SPI & Single Wire UART
Dual Encoder Interface and 2x Ref.-Switch input per axis
Highest Resolution up to 256 microsteps per full step
stealthChop™ for extremely quiet operation and smooth motion
spreadCycle™ highly dynamic motor control chopper
dcStep™ load dependent speed control
stallGuard2™ high precision sensorless motor load detection
coolStep™ current control for energy savings up to 75%
Passive Breaking and freewheeling mode
Full Protection & Diagnostics
Compact Size 7x7mm2 QFN48 package
APPLICATIONS
CCTV, Security
Office Automation
Antenna Positioning
Heliostat Controller
Battery powered applications
ATM, Cash recycler, POS
Lab Automation
Liquid Handling
Medical
Printer and Scanner
Pumps and Valves
DESCRIPTION
The TMC5072 is a dual high performance
stepper motor controller and driver IC
with serial communication interfaces. It
combines flexible ramp generators for
automatic target positioning with
industries’ most advanced stepper motor
drivers. Based on TRINAMICs
sophisticated stealthChop chopper, the
driver ensures absolutely noiseless
operation combined with maximum
efficiency and best motor torque. High
integration, high energy efficiency and a
small form factor enable miniaturized
and scalable systems for cost effective
solutions. The complete solution reduces
learning curve to a minimum while
giving best performance in class.
Dual controller/driver for up to two 2-phase bipolar stepper motors. No-noise stepper operation.
Integrated motion controller and encoder counter. SPI, UART (single wire) and Step/Dir.
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 2
www.trinamic.com
APPLICATION EXAMPLES: HIGH FLEXIBILITY MULTIPURPOSE USE
The TMC5072 scores with power density, complete motion controlling features and integrated power
stages. It offers a versatility that covers a wide spectrum of applications from battery systems up to
embedded applications with 1.5A motor current per coil. The small form factor keeps costs down and
allows for miniaturized layouts. Extensive support at the chip, board, and software levels enables rapid
design cycles and fast time-to-market with competitive products. High energy efficiency and reliability
deliver cost savings in related systems such as power supplies and cooling.
ORDER CODES
Order code
Description
Size [mm2]
TMC5072-LA
Dual axis stealthChop controller/driver, QFN-48
7 x 7
TMC5072-EVAL
Evaluation board for TMC5072
85 x 55
STARTRAMPE
Baseboard for TMC5072-EVAL and further evaluation boards
85 x 55
ESELSBRÜCKE
Connector board for plug-in evaluation board system
61 x 38
TMC5072-EVAL EVALUATION BOARD
EVALUATION & DEVELOPMENT PLATFORM
The TMC5072-EVAL is part of TRINAMICs universal
evaluation board system which provides a
convenient handling of the hardware as well as a
user-friendly software tool for evaluation. The
TMC5072 evaluation board system consists of three
parts: STARTRAMPE (base board), ESELSBRÜCKE
(connector board including several test points), and
TMC5072-EVAL.
The stepper motor driver
outputs are switched in
parallel. A dual ABN encoder
interface and two reference
switch inputs are used.
An application for up to 510
stepper motors is shown.
The UART single wire diffe-
rential interface allows for a
decentralized distributed
system with a minimized
number of components.
Additionally, an ABN
encoder and up to two
reference switches can be
used for each motor. A
single CPU can control the
whole system. The CPU-
board and controller / driver
boards are highly economi-
cal and space saving.
CPU TMC5072
High-Level
Interface
SPI
CPU
High-Level
Interface TMC5072
TMC5072
Up to 255 TMC5072
can be addressed.
UART
MINIATURIZED DESIGN FOR ONE STEPPER MOTOR
COMPACT DESIGN FOR UP TO 510 STEPPER MOTORS
M
Encoder
Ref.
Switches
Motor 1
Motor 2
M
M
Motor 3
Motor 4
M
M
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 3
www.trinamic.com
TABLE OF CONTENTS
1 PRINCIPLES OF OPERATION 5
1.1 KEY CONCEPTS 5
1.2 CONTROL INTERFACES 6
1.3 SOFTWARE 6
1.4 MOVING AND CONTROLLING THE MOTOR 7
1.5 STEALTHCHOP DRIVER WITH PROGRAMMABLE
MICROSTEPPING WAVE 7
1.6 STALLGUARD2 MECHANICAL LOAD SENSING 7
1.7 COOLSTEP LOAD ADAPTIVE CURRENT CONTROL 8
1.8 DCSTEP LOAD DEPENDENT SPEED CONTROL 8
1.9 ENCODER INTERFACES 8
2 PIN ASSIGNMENTS 9
2.1 PACKAGE OUTLINE 9
2.2 SIGNAL DESCRIPTIONS 9
3 SAMPLE CIRCUITS 12
3.1 STANDARD APPLICATION CIRCUIT 12
3.2 5 V ONLY SUPPLY 13
3.3 ONE MOTOR WITH HIGH CURRENT 14
3.4 EXTERNAL 5V POWER SUPPLY 14
3.5 OPTIMIZING ANALOG PRECISION 16
3.6 DRIVER PROTECTION AND EME CIRCUITRY 16
4 SPI INTERFACE 18
4.1 SPI DATAGRAM STRUCTURE 18
4.2 SPI SIGNALS 19
4.3 TIMING 20
5 UART SINGLE WIRE INTERFACE 21
5.1 DATAGRAM STRUCTURE 21
5.2 CRC CALCULATION 23
5.3 UART SIGNALS 23
5.4 ADDRESSING MULTIPLE SLAVES 24
5.5 RING MODE 26
6 REGISTER MAPPING 27
6.1 GENERAL CONFIGURATION REGISTERS 28
6.2 RAMP GENERATOR REGISTERS 31
6.3 ENCODER REGISTERS 37
6.4 MICROSTEP TABLE REGISTERS 39
6.5 MOTOR DRIVER REGISTERS 41
6.6 VOLTAGE PWM MODE STEALTHCHOP 46
7 CURRENT SETTING 47
7.1 SENSE RESISTORS 48
8 STEALTHCHOP™ 49
8.1 TWO MODES FOR CURRENT REGULATION 49
8.2 AUTOMATIC SCALING 50
8.3 FIXED SCALING 52
8.4 COMBINING STEALTHCHOP WITH OTHER CHOPPER
MODES 54
8.5 FLAGS IN STEALTHCHOP 55
8.6 FREEWHEELING AND PASSIVE MOTOR BRAKING 56
9 SPREADCYCLE AND CLASSIC CHOPPER 57
9.1 SPREADCYCLE CHOPPER 58
9.2 CLASSIC CONSTANT OFF TIME CHOPPER 61
9.3 RANDOM OFF TIME 62
10 DRIVER DIAGNOSTIC FLAGS 63
10.1 TEMPERATURE MEASUREMENT 63
10.2 SHORT TO GND PROTECTION 63
10.3 OPEN LOAD DIAGNOSTICS 63
11 RAMP GENERATOR 64
11.1 REAL WORLD UNIT CONVERSION 64
11.2 MOTION PROFILES 65
11.3 INTERRUPT HANDLING 67
11.4 VELOCITY THRESHOLDS 67
11.5 REFERENCE SWITCHES 68
12 STALLGUARD2 LOAD MEASUREMENT 70
12.1 TUNING STALLGUARD2 THRESHOLD SGT 71
12.2 STALLGUARD2 UPDATE RATE AND FILTER 73
12.3 DETECTING A MOTOR STALL 73
12.4 HOMING WITH STALLGUARD 73
12.5 LIMITS OF STALLGUARD2 OPERATION 73
13 COOLSTEP OPERATION 74
13.1 USER BENEFITS 74
13.2 SETTING UP FOR COOLSTEP 74
13.3 TUNING COOLSTEP 76
14 DCSTEP 77
14.1 USER BENEFITS 77
14.2 DESIGNING-IN DCSTEP 77
14.3 ENABLING DCSTEP 78
14.4 STALL DETECTION IN DCSTEP MODE 78
14.5 MEASURING ACTUAL MOTOR VELOCITY IN DCSTEP
OPERATION 79
15 SINE-WAVE LOOK-UP TABLE 80
15.1 USER BENEFITS 80
15.2 MICROSTEP TABLE 80
16 STEP/DIR INTERFACE 82
16.1 TIMING 82
16.2 CHANGING RESOLUTION 83
16.3 MICROPLYER STEP INTERPOLATOR AND STAND
STILL DETECTION 83
17 ABN INCREMENTAL ENCODER INTERFACE 85
17.1 ENCODER TIMING 86
17.2 SETTING THE ENCODER TO MATCH MOTOR
RESOLUTION 86
17.3 CLOSING THE LOOP 86
18 QUICK CONFIGURATION GUIDE 88
19 GETTING STARTED 93
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 4
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19.1 INITIALIZATION EXAMPLES 93
20 EXTERNAL RESET 95
21 CLOCK OSCILLATOR AND CLOCK INPUT 95
21.1 USING THE INTERNAL CLOCK 95
21.2 USING AN EXTERNAL CLOCK 95
21.3 CONSIDERATIONS ON THE FREQUENCY 96
22 ABSOLUTE MAXIMUM RATINGS 97
23 ELECTRICAL CHARACTERISTICS 97
23.1 OPERATIONAL RANGE 97
23.2 DC CHARACTERISTICS AND TIMING
CHARACTERISTICS 98
23.3 THERMAL CHARACTERISTICS 101
24 LAYOUT CONSIDERATIONS 102
24.1 EXPOSED DIE PAD 102
24.2 WIRING GND 102
24.3 SUPPLY FILTERING 102
24.4 SINGLE DRIVER CONNECTION 102
24.5 LAYOUT EXAMPLE 103
25 PACKAGE MECHANICAL DATA 104
25.1 DIMENSIONAL DRAWINGS 104
25.2 PACKAGE CODES 104
26 DESIGN PHILOSOPHY 105
27 DISCLAIMER 105
28 ESD SENSITIVE DEVICE 105
29 TABLE OF FIGURES 106
30 REVISION HISTORY 107
31 REFERENCES 107
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 5
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1 Principles of Operation
Diff. Tranceiver
Half Bridge 2
Half Bridge 1
Half Bridge 1
Half Bridge 2
+VM
VS
2 x current
comparator
2 phase
stepper
motor
N
S
Stepper driver
Protection
& diagnostics
programmable
sine table
4*256 entry
2 x DAC
stallGuard2
coolStep™
x
step multiplier
O1A1
O1A2
BR1A / B
RSENSE RSENSE
O1B1
O1B2
spreadCycle &
stealthChop
Chopper
VCC_IO
TMC5072
Dual stepper motor
driver / controller
SPI interface
CSN/IO0
SCK/IO1
SDO/RING
SDI/IO2
2x linear 6 point
RAMP generator
reference switch
processing
Step &
Direction pulse
generation
REFL1/STEP1
Stepper
#1
Motion control
coolStep motor
driver
REFR1/DIR1
Half Bridge 2
Half Bridge 1
Half Bridge 1
Half Bridge 2
+VM
VS
2 x current
comparator
2 phase
stepper
motor
N
S
programmable
sine table
4*256 entry
2 x DAC
stallGuard2
coolStep™
x
step multiplier
O2A1
O2A2
BR2A / B
RSENSE RSENSE
O2B1
O2B2
spreadCycle &
stealthChop
Chopper
reference switch
processing
Step &
Direction pulse
generation
Stepper
#2
coolStep motor
driver
2x linear 6 point
RAMP generator
Motion control
Control register
set
Single wire
interface
CLK oscillator/
selector
5V Voltage
regulator
temperature
measurement
charge pump
CPO
CPI
VCP
22n
100n
SWION
SW_SEL
CLK_IN
Interface
REFL2/STEP2
REFR2/DIR2
SWIOP
+VM
5VOUT
VSA
4.7µ
+VIO
Dual
Encoder
unit
ENC1A
ENC1B
IO0/SWIOP/REFL1
1A
1B
1N
2A
2B
2N
REFR1
REFR2
IO1/SWION/REFL2
ENC1A/INT
ENC1B/PP INT & position
pulse output
NEXTADDR
DRV_ENN
DRV_ENN
SINGLEDRV
SINGLEDRV
DRV2:=DRV1
GNDP
GNDP
GND
GNDA
FF
F
F
F
F
F
F F F = 60ns spike filter
TST_MODE
dcStep™
dcStep™
DIE PAD
VCC
RSENSE=0R25 allows for
maximum coil current
SPI™
single wire
UART
opt. ext. clock
12-16MHz
3.3V or 5V
I/O voltage
100n
100n
100n
100n
interface
selection
encoder or
interrupt out
ref. / stop switches or
step & dir (motor 2)
ref. / stop switches or
step & dir (motor 1)
opt. driver enable
Figure 1.1 Basic application and block diagram
The TMC5072 motion controller and driver chip is an intelligent power component interfacing between
the CPU and one or two stepper motors. All stepper motor logic is completely within the TMC5072. No
software is required to control the motor just provide target positions. The TMC5072 offers a
number of unique enhancements which are enabled by the system-on-chip integration of driver and
controller. The sixPoint ramp generator of the TMC5072 uses stealthChop, dcStep, coolStep, and
stallGuard2 automatically to optimize every motor movement. The clear concept and the
comprehensive solution save design time.
1.1 Key Concepts
The TMC5072 implements several advanced features which are exclusive to TRINAMIC products. These
features contribute toward greater precision, greater energy efficiency, higher reliability, smoother
motion, and cooler operation in many stepper motor applications.
stealthChop No-noise, high-precision chopper algorithm for inaudible motion and inaudible
standstill of the motor.
dcStep™ Load dependent speed control. The motor moves as fast as possible and never loses
a step.
stallGuard2 High-precision load measurement using the back EMF on the motor coils.
coolStep Load-adaptive current control which reduces energy consumption by as much as
75%.
spreadCycle High-precision chopper algorithm available as an alternative to the traditional
constant off-time algorithm.
sixPoint Fast and precise positioning using a hardware ramp generator with a set of four
acceleration / deceleration settings. Quickest response due to dedicated hardware.
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 6
www.trinamic.com
In addition to these performance enhancements, TRINAMIC motor drivers offer safeguards to detect
and protect against shorted outputs, output open-circuit, overtemperature, and undervoltage
conditions for enhancing safety and recovery from equipment malfunctions.
1.2 Control Interfaces
The TMC5072 supports both, an SPI and a UART based single wire interface with CRC checking.
Selection of the actual interface is done via the configuration pin SW_SEL, which can be hardwired to
GND or VCC_IO depending on the desired interface.
1.2.1 SPI Interface
The SPI interface is a bit-serial interface synchronous to a bus clock. For every bit sent from the bus
master to the bus slave another bit is sent simultaneously from the slave to the master.
Communication between an SPI master and the TMC5072 slave always consists of sending one 40-bit
command word and receiving one 40-bit status word.
The SPI command rate typically is a few commands per complete motor motion.
1.2.2 UART Interface
The single wire interface allows differential operation similar to RS485 (using SWIOP and SWION) or
single wire interfacing (leaving open SWION). It can be driven by any standard UART. No baud rate
configuration is required. An optional ring mode allows chaining of slaves to optimize interfacing for
applications with regularly distributed drives.
1.3 Software
From a software point of view the TMC5072 is a peripheral with a number of control and status
registers. Most of them can either be written only or read only. Some of the registers allow both read
and write access. In case read-modify-write access is desired for a write only register, a shadow
register can be realized in master software.
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 7
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1.4 Moving and Controlling the Motor
1.4.1 Integrated Motion Controller
The integrated 32 bit motion controller automatically drives the motor to target positions, or
accelerates to target velocities. All motion parameters can be changed on the fly. The motion
controller recalculates immediately. A minimum set of configuration data consists of acceleration and
deceleration values and the maximum motion velocity. A start and stop velocity is supported as well
as a second acceleration and deceleration setting. The integrated motion controller supports
immediate reaction to mechanical reference switches and to the sensorless stall detection stallGuard2.
Benefits are:
- Flexible ramp programming
- Efficient use of motor torque for acceleration and deceleration allows higher machine throughput
- Immediate reaction to stop and stall conditions
1.4.2 STEP/DIR Interface
One or both motors can optionally be controlled by a step and direction input. In this case, the
respective motion controller remains unused. Active edges on the STEP input can be rising edges or
both rising and falling edges as controlled by another mode bit (DEDGE). Using both edges cuts the
toggle rate of the STEP signal in half, which is useful for communication over slow interfaces such as
optically isolated interfaces. On each active edge, the state sampled from the DIR input determines
whether to step forward or back. Each step can be a fullstep or a microstep, in which there are 2, 4, 8,
16, 32, 64, 128, or 256 microsteps per fullstep. During microstepping, a step impulse with a low state
on DIR increases the microstep counter and a high decreases the counter by an amount controlled by
the microstep resolution. An internal table translates the counter value into the sine and cosine
values which control the motor current for microstepping.
1.5 stealthChop Driver with Programmable Microstepping
Wave
Current into the motor coils is controlled using a cycle-by-cycle chopper mode. Up to three chopper
modes are available: a traditional constant off-time mode and the spreadCycle mode as well as the
unique stealthChop. The constant off-time mode provides higher torque at highest velocity, while
spreadCycle mode offers smoother operation and greater power efficiency over a wide range of speed
and load. The spreadCycle chopper scheme automatically integrates a fast decay cycle and guarantees
smooth zero crossing performance. In contrast to the other chopper modes, stealthChop is a voltage
chopper based principle. It guarantees that the motor is absolutely quiet in standstill and in slow
motion, except for noise generated by ball bearings. The extremely smooth motion is beneficial for
many applications.
Programmable microstep shapes allow optimizing the motor performance.
Benefits of using stealthChop:
- Significantly improved microstepping with low cost motors
- Motor runs smooth and quiet
- Absolutely no standby noise
- Reduced mechanical resonances yields improved torque
1.6 stallGuard2 Mechanical Load Sensing
stallGuard2 provides an accurate measurement of the load on the motor. It can be used for stall
detection as well as other uses at loads below those which stall the motor, such as coolStep load-
adaptive current reduction. This gives more information on the drive allowing functions like
sensorless homing and diagnostics of the drive mechanics.
W
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 8
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1.7 coolStep Load Adaptive Current Control
coolStep drives the motor at the optimum current. It uses the stallGuard2 load measurement
information to adjust the motor current to the minimum amount required in the actual load situation.
This saves energy and keeps the components cool.
Benefits are:
- Energy efficiency power consumption decreased up to 75%
- Motor generates less heat improved mechanical precision
- Less or no cooling improved reliability
- Use of smaller motor less torque reserve required cheaper motor does the job
Figure 1.2 shows the efficiency gain of a 42mm stepper motor when using coolStep compared to
standard operation with 50% of torque reserve. coolStep is enabled above 60RPM in the example.
0
0,1
0,2
0,3
0,4
0,5
0,6
0,7
0,8
0,9
0 50 100 150 200 250 300 350
Efficiency
Velocity [RPM]
Efficiency with coolStep
Efficiency with 50% torque reserve
Figure 1.2 Energy efficiency with coolStep (example)
1.8 dcStep Load Dependent Speed Control
dcStep allows the motor to run near its load limit and at its velocity limit without losing a step. If the
mechanical load on the motor increases to the stalling load, the motor automatically decreases
velocity so that it can still drive the load. With this feature, the motor will never stall. In addition to
the increased torque at a lower velocity, dynamic inertia will allow the motor to overcome
mechanical overloads by decelerating. dcStep directly integrates with the ramp generator, so that the
target position will be reached, even if the motor velocity needs to be decreased due to increased
mechanical load. A dynamic range of up to factor 10 or more can be covered by dcStep without any
step loss. By optimizing the motion velocity in high load situations, this feature further enhances
overall system efficiency.
Benefits are:
- Motor does not loose steps in overload conditions
- Application works as fast as possible
- Highest possible acceleration automatically
- Highest energy efficiency at speed limit
- Highest possible motor torque using fullstep drive
- Cheaper motor does the job
1.9 Encoder Interfaces
The TMC5072 provides two encoder interfaces for external incremental encoders. The encoders can be
used for homing of the motion controllers (alternatively to reference switches) and for consistency
checks on-the-fly between encoder position and ramp generator position. A programmable prescaler
allows the adaptation of the encoder resolution to the motor resolution. 32 bit encoder counters are
provided.
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 9
www.trinamic.com
2 Pin Assignments
2.1 Package Outline
B. Dwersteg, TRINAMIC 2012
TMC 5072-LA
QFN48 7mm x 7mm
0.5 pitch
REFL1
CPO
GNDP
TST_MODE
O1A1
VS
O1B1
BR1A
O1A2
VS
O1B2
VCC_IO
ENC1B/PP
O2A2
BR2A
BR2B
VS
O2B2
VS
O2B1
1
ENC1A/INT
SDO/RING
SWIOP
GND
SDI/IO2
SCK/IO1
CSN/IO0
REFR1
REFL2
VSA
GNDA
GND
CPI
CLK
SWION
GNDP
REFR2
BR1B
O2A1
2
3
4
5
6
7
8
9
10
11
14
15
16
17
18
19
20
21
22
23
24
36
35
34
33
32
31
30
29
28
27
26
48
47
46
45
44
43
42
41
40
39
38
DRV_ENN
VCP
37
25
-13
12
-
SWSEL
-
VCC
NEXTADDR
5VOUT
Figure 2.1 TMC5072 pin assignments.
2.2 Signal Descriptions
Pin
Number
Type
Function
GND
6, 34
GND
Digital ground pin for IO pins and digital circuitry.
VCC_IO
7
3.3V or 5V I/O supply voltage pin for all digital pins.
VSA
30
Analog supply voltage for 5V regulator typically supplied with
driver supply voltage. An additional 100nF capacitor to GND (GND
plane) is recommended for best performance.
GNDA
31
GND
Analog GND. Tie to GND plane.
5VOUT
32
Output of internal 5V regulator. Attach 2.2 μF or larger ceramic
capacitor to GNDA near to pin for best performance. May be used to
supply VCC of chip.
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 10
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Pin
Number
Type
Function
VCC
33
5V supply input for digital circuitry within chip and charge pump.
Attach 470nF capacitor to GND (GND plane). May be supplied by
5VOUT. A 2.2 resistor is recommended for decoupling noise from
5VOUT. When using an external supply, make sure, that VCC comes
up before or in parallel to 5VOUT or VCC_IO, whichever comes up
later!
DIE_PAD
-
GND
Connect the exposed die pad to a GND plane. Provide as many as
possible vias for heat transfer to GND plane.
Table 2.1 Low voltage digital and analog power supply pins
Pin
Number
Type
Function
CPO
35
O(VCC)
Charge pump driver output. Outputs 5V (GND to VCC) square wave
with 1/16 of internal oscillator frequency.
CPI
36
I(VCP)
Charge pump capacitor input: Provide external 22nF or 33nF / 50 V
capacitor to CPO.
VCP
37
Output of charge pump. Provide external 100nF capacitor to VS.
Table 2.2 Charge pump pins
Pin
Number
Type
Function
ENC1A/INT
1
I/O
Input A for incremental encoder 1. Can be programmed to provide
interrupt output based on ramp generator flags RAMP_STAT bits 4, 5,
6 & 7 and encoder null event status ENC_STATUS bit 0
(poscmp_enable=1).
ENC1B/PP
2
I/O
Input B for incremental encoder 1. Can be programmed to provide
position compare output for motor 1 (poscmp_enable=1).
CSN/IO0
3
I/O
Chip select input of SPI interface, programmable IO in UART mode
SCK/IO1
4
I/O
Serial clock input of SPI interface, programmable IO in UART mode
SDI/IO2
5
I/O
Data input of SPI interface, programmable IO in UART mode
SDO/RING
8
I/O
Data output of SPI interface (Tristate, enabled with CSN=0), mode
configuration input in UART mode (0 = Normal mode, 1 = Single wire
ring mode SWIO_P is input, SWIO_N is output)
SWIOP
9
I/O
Single wire I/O (positive). Serial input in ring mode. Multi-purpose
input in SPI mode or encoder 1 N input.
SWION
10
I/O
Single wire I/O (negative) for differential mode. Leave open in non-
differential mode when operating at 5V IO voltage or tie to desired
threshold voltage. Serial output in ring mode. Multi-purpose input in
SPI mode or encoder 2 N input.
CLK
11
I
Clock input. Tie to GND using short wire for internal clock or supply
external clock. The first high signal disables the internal oscillator
until power down.
SWSEL
12
I
Interface selection input. Tie to GND for SPI mode, tie to VCC_IO for
single wire (UART) interface mode.
NEXTADDR
24
I
Address increment (if tied high) for single wire (UART) mode. General
purpose input in SPI mode
REFR2/DIR2
25
I
Right reference switch input for motor 2, optional DIR input for
STEP/DIR operation of motor 2 or encoder 2 B input
REFL2/STEP2
26
I
Left reference switch input for motor 2, optional STEP input for
STEP/DIR operation of motor 2
REFR1/DIR1
27
I
Right reference switch input for motor 1, optional DIR input for
STEP/DIR operation of motor 1 or encoder 2 A input
REFL1/STEP1
28
I
Left reference switch input for motor 1, optional STEP input for
STEP/DIR operation of motor 1
DRV_ENN
29
I
Enable input for motor drivers. The power stage becomes switched
off (all motor outputs floating) when this pin becomes driven to a
high level. Tie to GND for normal operation.
TST_MODE
48
I
Test mode input. Tie to GND using short wire.
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 11
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Pin
Number
Type
Function
-
13, 23, 38
N.C.
Unused pins no internal electrical connection. Leave open or tie to
GND for compatibility with future devices.
Table 2.3 Digital I/O pins (all related to VCC_IO supply)
Pin
Number
Type
Function
O2A1
14
O (VS)
Motor 2 coil A output 1
BR2A
15
Sense resistor connection for motor 2 coil A. Place sense resistor to
GND near pin.
O2A2
16
O (VS)
Motor 2 coil A output 2
VS
17, 19
Motor supply voltage. Provide filtering capacity near pin with
shortest loop to nearest GNDP pin (respectively via GND plane).
GNDP
18
GND
Power GND. Connect to GND plane near pin.
O2B1
20
O (VS)
Motor 2 coil B output 1
BR2B
21
Sense resistor connection for motor 2 coil B. Place sense resistor to
GND near pin.
O2B2
22
O (VS)
Motor 2 coil B output 2
O1B2
39
O (VS)
Motor 1 coil B output 2
BR1B
40
Sense resistor connection for motor 1 coil B. Place sense resistor to
GND near pin.
O1B1
41
O (VS)
Motor 1 coil B output 1
VS
42, 44
Motor supply voltage. Provide filtering capacity near pin with
shortest loop to nearest GNDP pin (respectively via GND plane).
GNDP
43
GND
Power GND. Connect to GND plane near pin.
O1A2
45
O (VS)
Motor 1 coil A output 2
BR1A
46
Sense resistor connection for motor 1 coil A. Place sense resistor to
GND near pin.
O1A1
47
O (VS)
Motor 1 coil A output 1
Table 2.4 Power driver pins
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 12
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3 Sample Circuits
The sample circuits show the connection of the external components in different operation and
supply modes. The connection of the bus interface and further digital signals is left out for clarity.
3.1 Standard Application Circuit
VCC_IO
TMC5072
SPI interface
CSN/IO0
SCK/IO1
SDO/RING
SDI/IO2
reference switch
processing
REFL1/STEP1
REFR1/DIR1
reference switch
processing
Controller 2
Single wire
interface
5V Voltage
regulator
charge pump
VCP
22n
100n
SWION
SW_SEL
CLK_IN
REFL2/STEP2
REFR2/DIR2
SWIOP
+VM
5VOUT
VSA
4.7µ
+VIO
ENC1A/INT
ENC1B/PP INT & position
pulse output
NEXTADDR
DRV_ENN
DRV_ENN
GNDP
GND
GNDA
TST_MODE
DIE PAD
VCC
opt. ext. clock
12-16MHz
3.3V or 5V
I/O voltage
100n
100n
Controller 1
Full Bridge A
Full Bridge B
+VM
VS
stepper
motor #1
N
S
O1A1
O1A2
BR1A
O1B1
O1B2
Driver 1
100n
BR1B
Full Bridge A
Full Bridge B
stepper
motor #2
N
S
O2A1
O2A2
BR2A
O2B1
O2B2
Driver 2
BR2B
VS
100n
+VM
100µF
CPI
CPO
+VIO
Optional use lower
voltage down to 6V
2R2
470n
R1A
R1B
R2A
R2B
Figure 3.1 Standard application circuit
The standard application circuit uses a minimum set of additional components in order to operate the
motor. Use low ESR capacitors for filtering the power supply which are capable to cope with the
current ripple. The current ripple often depends on the power supply and cable length. The VCC_IO
voltage can be supplied from 5VOUT, or from an external source, e.g. a low drop 3.3V regulator. In
order to minimize linear voltage regulator power dissipation of the internal 5V voltage regulator in
applications where VM is high, a different (lower) supply voltage can be used for VSA, if available. For
example, many applications provide a 12V supply in addition to a higher supply voltage like 24V.
Using the 12V supply for VSA will reduce the power dissipation of the internal 5V regulator to about
37% of the dissipation caused by supply with the full motor voltage. For best motor chopper
performance, an optional R/C-filter de-couples 5VOUT from digital noise cause by power drawn from
VCC.
Basic layout hints
Place sense resistors and all filter capacitors as close as possible to the related IC pins. Use a solid
common GND for all GND connections, also for sense resistor GND. Connect 5VOUT filtering capacitor
directly to 5VOUT and GNDA pin. See layout hints for more details. Low ESR electrolytic capacitors are
recommended for VS filtering.
Attention
In case VSA is supplied by a different voltage source, make sure that VSA does not exceed VS by
more than one diode drop upon power up or power down.
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 13
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3.2 5 V Only Supply
VCC_IO
TMC5072
SPI interface
CSN/IO0
SCK/IO1
SDO/RING
SDI/IO2
reference switch
processing
REFL1/STEP1
REFR1/DIR1
reference switch
processing
Controller 2
Single wire
interface
5V Voltage
regulator
charge pump
VCP
22n
100n
SWION
SW_SEL
CLK_IN
REFL2/STEP2
REFR2/DIR2
SWIOP
+5V
5VOUT
VSA
4.7µ
+VIO
ENC1A/INT
ENC1B/PP INT & position
pulse output
NEXTADDR
DRV_ENN
DRV_ENN
GNDP
GND
GNDA
TST_MODE
DIE PAD
VCC
opt. ext. clock
12-16MHz
3.3V or 5V
I/O voltage
100n
470n
Controller 1
Full Bridge A
Full Bridge B
+5V
VS
stepper
motor #1
N
S
O1A1
O1A2
BR1A
RS1B
O1B1
O1B2
Driver 1
100n
BR1B
RS1A
Full Bridge A
Full Bridge B
stepper
motor #2
N
S
O2A1
O2A2
BR2A
RS2B
O2B1
O2B2
Driver 2
BR2B
RS2A
VS
100n
+5V
100µF
CPI
CPO
+VIO
Figure 3.2 5V only operation
While the standard application circuit is limited to roughly 5.5 V lower supply voltage, a 5 V only
application lets the IC run from a normal 5 V +/-5% supply. In this application, linear regulator drop
must be minimized. Therefore, the major 5 V load is removed by supplying VCC directly from the
external supply. In order to keep supply ripple away from the analog voltage reference, 5VOUT should
have an own filtering capacity and the 5VOUT pin does not become bridged to the 5V supply.
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 14
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3.3 One Motor with High Current
The TMC5072 supports double motor current for a single driver by paralleling both power stages. In
order to operate in this mode, activate the flag single_driver in the global configuration register
GCONF. This register can be locked for subsequent write access.
VCC_IO
TMC5072
SPI interface
CSN/IO0
SCK/IO1
SDO/RING
SDI/IO2
reference switch
processing
REFL1/STEP1
REFR1/DIR1
reference switch
processing
Controller 2
Single wire
interface
5V Voltage
regulator
charge pump
VCP
22n
100n
SWION
SW_SEL
CLK_IN
REFL2/STEP2
REFR2/DIR2
SWIOP
+VM
5VOUT
VSA
4.7µ
+VIO
ENC1A/INT
ENC1B/PP INT & position
pulse output
NEXTADDR
DRV_ENN
DRV_ENN
GNDP
GND
GNDA
TST_MODE
DIE PAD
VCC
opt. ext. clock
12-16MHz
3.3V or 5V
I/O voltage
100n
100n
Controller 1
Full Bridge A
Full Bridge B
+VM
VS
high current
stepper motor
N
S
O1A1
O1A2
BR1A
RS1B
O1B1
O1B2
Driver 1
100n
BR1B
RS1A
Full Bridge A
Full Bridge B
O2A1
O2A2
BR2A
O2B1
O2B2
Driver 2
BR2B
VS
100n
+VM
100µF
CPI
CPO
+VIO
Figure 3.3 Driving a single motor with high current
3.4 External 5V Power Supply
When an external 5V power supply is available, the power dissipation caused by the internal linear
regulator can be eliminated. This especially is beneficial in high voltage applications, and when
thermal conditions are critical. There are two options for using this external 5V source: either the
external 5V source is used to support the digital supply of the driver by supplying the VCC pin, or the
complete internal voltage regulator becomes bridged and is replaced by the external supply voltage.
3.4.1 Support for the VCC Supply
This scheme uses an external supply for all digital circuitry within the driver (Figure 3.4). As the digital
circuitry makes up for most of the power dissipation, this way the internal 5V regulator sees only low
remaining load. The precisely regulated voltage of the internal regulator is still used as the reference
for the motor current regulation as well as for supplying internal analog circuitry.
When cutting pin VCC from 5VOUT, make sure that the VCC supply comes up before or synchronously
with the 5VOUT supply to ensure a correct power up reset of the internal logic. A simple schematic
uses two diodes forming an OR of the internal and the external power supplies for VCC. In order to
prevent the chip from drawing part of the power from its internal regulator, a low drop 1A Schottky
diode is used for the external 5V supply path, while a silicon diode is used for the 5VOUT path. An
enhanced solution uses a dual PNP transistor as an active switch. It minimizes voltage drop and thus
gives best performance.
In certain setups, switching of VCC voltage can be eliminated. A third variant uses the VCC_IO supply
to ensure power-on reset. This is possible, if VCC_IO comes up synchronously with or delayed to VCC.
Use a linear regulator to generate a 3.3V VCC_IO from the external 5V VCC source. This 3.3V regulator
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 15
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will cause a certain voltage drop. A voltage drop in the regulator of 0.9V or more (e.g. LD1117-3.3)
ensures that the 5V supply already has exceeded the lower limit of about 3.0V once the reset
conditions ends. The reset condition ends earliest, when VCC_IO exceeds the undervoltage limit of
minimum 2.1V. Make sure that the power-down sequence also is safe. Undefined states can result
when VCC drops well below 4V without safely triggering a reset condition. Triggering a reset upon
power-down can be ensured when VSA goes down synchronously with or before VCC.
5V Voltage
regulator
5VOUT
VSA
4.7µ
VCC
100n
470n
+5V LL4448
MSS1P3
+VM
5V Voltage
regulator
5VOUT
VSA
4.7µ
VCC
100n
+5V
+VM
VCC_IO
470n 100n
3.3V
regulator
3.3V
VCC supplied from external 5V. 5V or 3.3V IO voltage. VCC supplied from external 5V. 3.3V IO voltage generated from same source.
5V Voltage
regulator
5VOUT
VSA
4.7µ
VCC
100n
470n
+5V BAT54
+VM
VCC supplied from external 5V using active switch. 5V or 3.3V IO voltage.
4k7
10k
2x BC857 or
1x BC857BS
Figure 3.4 Using an external 5V supply for digital circuitry of driver (different options)
3.4.2 Internal Regulator Bridged
In case a clean external 5V supply is available, it can be used for complete supply of analog and
digital part (Figure 3.5). The circuit will benefit from a well regulated supply, e.g. when using a +/-1%
regulator. A precise supply guarantees increased motor current precision, because the voltage at
5VOUT directly is the reference voltage for all internal units of the driver, especially for motor current
control. For best performance, the power supply should have low ripple to give a precise and stable
supply at 5VOUT pin with remaining ripple well below 5mV. Some switching regulators have a higher
remaining ripple, or different loads on the supply may cause lower frequency ripple. In this case,
increase capacity attached to 5VOUT. In case the external supply voltage has poor stability or low
frequency ripple, this would affect the precision of the motor current regulation as well as add
chopper noise.
5V Voltage
regulator
+5V
5VOUT
VSA
4.7µ
VCC
470n
10R
Well-regulated, stable
supply, better than +-5%
Figure 3.5 Using an external 5V supply to bypass internal regulator
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 16
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3.5 Optimizing Analog Precision
The 5VOUT pin is used as an analog reference for operation of the TMC5072. Performance will degrade
when there is voltage ripple on this pin. Most of the high frequency ripple in a TMC5072 design
results from the operation of the internal digital logic. The digital logic switches with each edge of
the clock signal. Further, ripple results from operation of the charge pump, which operates with
roughly 1 MHz and draws current from the VCC pin. In order to keep this ripple as low as possible, an
additional filtering capacitor can be put directly next to the VCC pin with vias to the GND plane giving
a short connection to the digital GND pins (pin 6 and pin 34). Analog performance is best, when this
ripple is kept away from the analog supply pin 5VOUT, using an additional series resistor of 2.2 . The
voltage drop on this resistor will be roughly 100 mV (IVCC * R).
5V Voltage
regulator
charge pump
VCP
22n
100n
+VM
5VOUT
VSA
4.7µ
VCC
100n
470n
CPI
CPO
GNDA
2R2
Figure 3.6 RC-Filter on VCC for reduced ripple
3.6 Driver Protection and EME Circuitry
Some applications have to cope with ESD events caused by motor operation or external influence.
Despite ESD circuitry within the driver chips, ESD events occurring during operation can cause a reset
or even a destruction of the motor driver, depending on their energy. Especially plastic housings and
belt drive systems tend to cause ESD events. It is best practice to avoid ESD events by attaching all
conductive parts, especially the motors themselves to PCB ground, or to apply electrically conductive
plastic parts. In addition, the driver can be protected up to a certain degree against ESD events or live
plugging / pulling the motor, which also causes high voltages and high currents into the motor
connector terminals. A simple scheme uses capacitors at the driver outputs to reduce the dV/dt caused
by ESD events. Larger capacitors will bring more benefit concerning ESD suppression, but cause
additional current flow in each chopper cycle, and thus increase driver power dissipation, especially at
high supply voltages. The values shown are example values they might be varied between 100pF
and 1nF. The capacitors also dampen high frequency noise injected from digital parts of the circuit
and thus reduce electromagnetic emission. A more elaborate scheme uses LC filters to de-couple the
driver outputs from the motor connector. Varistors in between of the coil terminals eliminate coil
overvoltage caused by live plugging. Optionally protect all outputs by a varistor against ESD voltage.
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 17
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Full Bridge A
Full Bridge B
stepper
motor
N
S
OA1
OA2
OB1
OB2
Driver
470pF
100V
470pF
100V
470pF
100V
470pF
100V
Full Bridge A
Full Bridge B
stepper
motor
N
S
OA1
OA2
OB1
OB2
Driver
470pF
100V
470pF
100V
50Ohm @
100MHz
50Ohm @
100MHz
50Ohm @
100MHz
50Ohm @
100MHz
V1
V2
Fit varistors to supply voltage
rating. SMD inductivities
conduct full motor coil
current.
470pF
100V
470pF
100V
Varistors V1 and V2 protect
against inductive motor coil
overvoltage.
V1A, V1B, V2A, V2B:
Optional position for varistors
in case of heavy ESD events.
BRB
RSA
BRA
100nF
16V
RSB 100nF
16V
V1A
V1B
V2A
V2B
Figure 3.7 Simple ESD enhancement and more elaborate motor output protection
.Ez
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 18
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4 SPI Interface
4.1 SPI Datagram Structure
The TMC5072 uses 40 bit SPI (Serial Peripheral Interface, SPI is Trademark of Motorola) datagrams
for communication with a microcontroller. Microcontrollers which are equipped with hardware SPI are
typically able to communicate using integer multiples of 8 bit. The NCS line of the TMC5072 must be
handled in a way, that it stays active (low) for the complete duration of the datagram transmission.
Each datagram sent to the device is composed of an address byte followed by four data bytes. This
allows direct 32 bit data word communication with the register set. Each register is accessed via 32
data bits even if it uses less than 32 data bits.
For simplification, each register is specified by a one byte address:
- For a read access the most significant bit of the address byte is 0.
- For a write access the most significant bit of the address byte is 1.
Most registers are write only registers, some can be read additionally, and there are also some read
only registers.
4.1.1 Selection of Write / Read (WRITE_notREAD)
The read and write selection is controlled by the MSB of the address byte (bit 39 of the SPI
datagram). This bit is 0 for read access and 1 for write access. So, the bit named W is a
WRITE_notREAD control bit. The active high write bit is the MSB of the address byte. So, 0x80 has to
be added to the address for a write access. The SPI interface always delivers data back to the master,
independent of the W bit. The data transferred back is the data read from the address which was
transmitted with the previous datagram, if the previous access was a read access. If the previous
access was a write access, then the data read back mirrors the previously received write data. So, the
difference between a read and a write access is that the read access does not transfer data to the
addressed register but it transfers the address only and its 32 data bits are dummies, and, further the
following read or write access delivers back the data read from the address transmitted in the
preceding read cycle.
A read access request datagram uses dummy write data. Read data is transferred back to the master
with the subsequent read or write access. Hence, reading multiple registers can be done in a
pipelined fashion.
Whenever data is read from or written to the TMC5072, the MSBs delivered back contain the SPI
status, SPI_STATUS, a number of eight selected status bits.
SPI DATAGRAM STRUCTURE
MSB (transmitted first)
40 bit
LSB (transmitted last)
39 ...
... 0
8 bit address
8 bit SPI status
32 bit data
39 ... 32
31 ... 0
to TMC5072:
RW + 7 bit address
from TMC5072:
8 bit SPI status
8 bit data
8 bit data
8 bit data
8 bit data
39 / 38 ... 32
31 ... 24
23 ... 16
15 ... 8
7 ... 0
W
38...32
31...28
27...24
23...20
19...16
15...12
11...8
7...4
3...0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
8
7
6
5
4
3
2
1
0
amen data sent to TMC5072 data recewed from TMC5072
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 19
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Example:
For a read access to the register (XACTUAL) with the address 0x21, the address byte has to
be set to 0x21 in the access preceding the read access. For a write access to the register
(VACTUAL), the address byte has to be set to 0x80 + 0x22 = 0xA2. For read access, the data
bit might have any value (-). So, one can set them to 0.
action data sent to TMC5072 data received from TMC5072
read XACTUAL 0x2100000000 0xSS & unused data
read XACTUAL 0x2100000000 0xSS & XACTUAL
write VMAX:= 0x00ABCDEF 0xA700ABCDEF 0xSS & XACTUAL
write VMAX:= 0x00123456 0xA700123456 0xSS00ABCDEF
*)S: is a placeholder for the status bits SPI_STATUS
4.1.2 SPI Status Bits Transferred with Each Datagram Read Back
New status information becomes latched at the end of each access and is available with the next SPI
transfer.
SPI_STATUS status flags transmitted with each SPI access in bits 39 to 32
Bit
Name
Comment
7
-
reserved (0)
6
status_stop_l(2)
RAMP_STAT2[0] 1: Signals motor 2 stop left switch status
5
status_stop_l(1)
RAMP_STAT1[0] 1: Signals motor 1 stop left switch status
4
velocity_reached(2)
RAMP_STAT2[8] 1: Signals motor 2 has reached its target velocity
3
velocity_reached(1)
RAMP_STAT1[8] 1: Signals motor 1 has reached its target velocity
2
driver_error(2)
GSTAT[2] 1: Signals driver 2 driver error (clear by reading GSTAT)
1
driver_error(1)
GSTAT[1] 1: Signals driver 1 driver error (clear by reading GSTAT)
0
reset_flag
GSTAT[0] 1: Signals, that a reset has occurred (clear by reading GSTAT)
4.1.3 Data Alignment
All data are right aligned. Some registers represent unsigned (positive) values, some represent integer
values (signed) as two’s complement numbers, single bits or groups of bits are represented as single
bits respectively as integer groups.
4.2 SPI Signals
The SPI bus on the TMC5072 has four signals:
- SCK bus clock input
- SDI serial data input
- SDO serial data output
- CSN chip select input (active low)
The slave is enabled for an SPI transaction by a low on the chip select input CSN. Bit transfer is
synchronous to the bus clock SCK, with the slave latching the data from SDI on the rising edge of SCK
and driving data to SDO following the falling edge. The most significant bit is sent first. A minimum
of 40 SCK clock cycles is required for a bus transaction with the TMC5072.
If more than 40 clocks are driven, the additional bits shifted into SDI are shifted out on SDO after a
40-clock delay through an internal shift register. This can be used for daisy chaining multiple chips.
CSN must be low during the whole bus transaction. When CSN goes high, the contents of the internal
shift register are latched into the internal control register and recognized as a command from the
master to the slave. If more than 40 bits are sent, only the last 40 bits received before the rising edge
of CSN are recognized as the command.
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 20
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4.3 Timing
The SPI interface is synchronized to the internal system clock, which limits the SPI bus clock SCK to
half of the system clock frequency. If the system clock is based on the on-chip oscillator, an additional
10% safety margin must be used to ensure reliable data transmission. All SPI inputs as well as the
ENN input are internally filtered to avoid triggering on pulses shorter than 20ns. Figure 4.1 shows the
timing parameters of an SPI bus transaction, and the table below specifies their values.
CSN
SCK
SDI
SDO
tCC tCC
tCL tCH
bit39 bit38 bit0
bit39 bit38 bit0
tDO tZC
tDU tDH
tCH
Figure 4.1 SPI timing
Hint
Usually this SPI timing is referred to as SPI MODE 3
SPI interface timing
AC-Characteristics
clock period: tCLK
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
SCK valid before or after change
of CSN
tCC
10
ns
CSN high time
tCSH
*) Min time is for
synchronous CLK
with SCK high one
tCH before CSN high
only
tCLK*)
>2tCLK+10
ns
SCK low time
tCL
*) Min time is for
synchronous CLK
only
tCLK*)
>tCLK+10
ns
SCK high time
tCH
*) Min time is for
synchronous CLK
only
tCLK*)
>tCLK+10
ns
SCK frequency using internal
clock
fSCK
assumes minimum
OSC frequency
4
MHz
SCK frequency using external
16MHz clock
fSCK
assumes
synchronous CLK
8
MHz
SDI setup time before rising
edge of SCK
tDU
10
ns
SDI hold time after rising edge
of SCK
tDH
10
ns
Data out valid time after falling
SCK clock edge
tDO
no capacitive load
on SDO
tFILT+5
ns
SDI, SCK and CSN filter delay
time
tFILT
rising and falling
edge
12
20
30
ns
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 21
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5 UART Single Wire Interface
The UART single wire interface allows the control of the TMC5072 with any microcontroller UART. It
shares transmit and receive line like an RS485 based interface. Data transmission is secured using a
cyclic redundancy check, so that increased interface distances (e.g. over cables between two PCBs) can
be bridged without the danger of wrong or missed commands even in the event of electro-magnetic
disturbance. The automatic baud rate detection and an advanced addressing scheme make this
interface easy and flexible to use.
5.1 Datagram Structure
5.1.1 Write Access
UART WRITE ACCESS DATAGRAM STRUCTURE
each byte is LSB…MSB, highest byte transmitted first
0 … 63
sync + reserved
8 bit slave
address
RW + 7 bit
register addr.
32 bit data
CRC
0…7
8…15
16…23
24…55
56…63
1
0
1
0
Reserved (don’t cares
but included in CRC)
SLAVEADDR
register
address
1
data bytes 3, 2, 1, 0
(high to low byte)
CRC
0
1
2
3
4
5
6
7
8
15
16
23
24
55
56
63
A sync nibble precedes each transmission to and from the TMC5072 and is embedded into the first
transmitted byte, followed by an addressing byte. Each transmission allows a synchronization of the
internal baud rate divider to the master clock. The actual baud rate is adapted and variations of the
internal clock frequency are compensated. Thus, the baud rate can be freely chosen within the valid
range. Each transmitted byte starts with a start bit (logic 0, low level on SWIOP) and ends with a stop
bit (logic 1, high level on SWIOP). The bit time is calculated by measuring the time from the
beginning of start bit (1 to 0 transition) to the end of the sync frame (1 to 0 transition from bit 2 to
bit 3). All data is transmitted byte wise. The 32 bit data words are transmitted with the highest byte
first.
A minimum baud rate of 9000 baud is permissible, assuming 20 MHz clock (worst case for low baud
rate). Maximum baud rate is fCLK/16 due to the required stability of the baud clock.
The slave address is determined by the register SLAVEADDR. If the external address pin NEXTADDR is
set, the slave address becomes incremented by one.
The communication becomes reset if a pause time of longer than 63 bit times between the start bits
of two successive bytes occurs. This timing is based on the last correctly received datagram. In this
case, the transmission needs to be restarted after a failure recovery time of minimum 12 bit times of
bus idle time. This scheme allows the master to reset communication in case of transmission errors.
Any pulse on an idle data line below 16 clock cycles will be treated as a glitch and leads to a timeout
of 12 bit times, for which the data line must be idle. Other errors like wrong CRC are also treated the
same way. This allows a safe re-synchronization of the transmission after any error conditions.
Remark, that due to this mechanism, an abrupt reduction of the baud rate to less than 15 percent of
the previous value is not possible.
Each accepted write datagram becomes acknowledged by the receiver by incrementing an internal
cyclic datagram counter (8 bit). Reading out the datagram counter allows the master to check the
success of an initialization sequence or single write accesses. Read accesses do not modify the
counter.
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5.1.2 Read Access
UART READ ACCESS REQUEST DATAGRAM STRUCTURE
each byte is LSB…MSB, highest byte transmitted first
sync + reserved
8 bit slave address
RW + 7 bit register
address
CRC
0...7
8…15
16…23
24…31
1
0
1
0
Reserved (don’t cares
but included in CRC)
SLAVEADDR
register address
0
CRC
0
1
2
3
4
5
6
7
8
15
16
23
24
31
The read access request datagram structure is identical to the write access datagram structure, but
uses a lower number of user bits. Its function is the addressing of the slave and the transmission of
the desired register address for the read access. The TMC5072 responds with the same baud rate as
the master uses for the read request.
In order to ensure a clean bus transition from the master to the slave, the TMC5072 does not
immediately send the reply to a read access, but it uses a programmable delay time after which the
first reply byte becomes sent following a read request. This delay time can be set in multiples of
eight bit times using SENDDELAY time setting (default=8 bit times) according to the needs of the
master.
UART READ ACCESS REPLY DATAGRAM STRUCTURE
each byte is LSB…MSB, highest byte transmitted first
0 ...... 63
sync + reserved
8 bit slave
address
RW + 7 bit
register addr.
32 bit data
CRC
0…7
8…15
16…23
24…55
56…63
1
0
1
0
reserved (0)
0xFF
register
address
0
data bytes 3, 2, 1, 0
(high to low byte)
CRC
0
1
2
3
4
5
6
7
8
15
16
23
24
55
56
63
The read response is sent to the master using address code %1111. The transmitter becomes switched
inactive four bit times after the last bit is sent.
Address %11111111 is reserved for read accesses going to the master. A slave cannot use this
address.
ERRATA IN READ ACCESS
A known bug in the UART interface implementation affects read access to registers that change during
the access. While the SPI interface takes a snapshot of the read register before transmission, the UART
interface transfers the register directly MSB to LSB without taking a snapshot. This may lead to
inconsistent data when reading out a register that changes during the transmission. Further, the CRC
sent from the driver may be incorrect in this case (but must not), which will lead to the master
repeating the read access. As a workaround, it is advised not to read out quickly changing registers
like XACTUAL, MSCNT or X_ENC during a motion, but instead first stop the motor or check the
position_reached flag to become active, and read out these values afterwards. If possible, use
X_LATCH and ENC_LATCH for a safe readout during motion (e.g. for homing). As the encoder cannot be
guaranteed to stand still during motor stop, only a dual read access and check for identical result
ensures correct X_ENC read data. Therefore it is advised to use the latching function instead. Use the
vzero and velocity_reached flag rather than reading VACTUAL.
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 23
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5.2 CRC Calculation
An 8 bit CRC polynomial is used for checking both read and write access. It allows detection of up to
eight single bit errors. The CRC8-ATM polynomial with an initial value of zero is applied LSB to MSB,
including the sync- and addressing byte. The sync nibble is assumed to always be correct. The
TMC5072 responds only to correctly transmitted datagrams containing its own slave address. It
increases its datagram counter for each correctly received write access datagram.
 
Hint:
The CRC can be calculated within a CPU using a bit-wise cyclic XOR calculation of incoming and
outgoing bits accumulated to an 8 bit CRC register. You find the algorithm in the TMC5072-EVAL
evaluation board firmware.
CRC = (CRC << 1) OR (CRC.7 XOR CRC.1 XOR CRC.0 XOR [new incoming bit])
-- CRC.n is meant to extract bit n from the 8 bit CRC register
For a parallel 8 bit calculation of CRC in your CPU, you can use a look-up table. Additional algorithms
can be found in literature.
5.3 UART Signals
The UART interface on the TMC5072 has following signals:
TMC5072 UART INTERFACE SIGNALS
SWIOP
Non-inverted data input and output
SWION
Inverted data input and output for use in differential transmission. Can be left open
in a 5V IO voltage system. Tie to the half IO level voltage for best performance in a
3.3V single wire non-differential application.
NEXTADDR
Address increment pin for sequential addressing scheme
SDO/RING
A low level on this input selects standard mode, a high level switches to ring mode
In UART mode (SW_SEL high) the slave checks the single wire SWIOP and SWION for correctly
received datagrams with its own address continuously. Both signals are switched as input during this
time. It adapts to the baud rate based on the sync nibble, as described before. In case of a read
access, it switches on its output drivers on SWIOP and SWION and sends its response using the same
baud rate.
NEXTADDR m m N Nsxmm N Nsxmm dGIMS dorms dorms
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 24
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5.4 Addressing Multiple Slaves
ADDRESSING ONE OR TWO SLAVES
If only one or two TMC5072 are addressed by a master using a single UART interface, a hardware
address selection can be done by setting the NEXTADDR pins to different levels.
ADDRESSING UP TO 255 SLAVES
A different approach can address any number of devices by using the input NEXTADDR as a selection
pin. Addressing up to 255 units is possible.
Master CPU
(µC with UART,
software
switches TXD to
hi-Z for
receiving)
TMC5072
#1
NEXTADDR
CSN/IO0
SWIOP
SWION
TMC5072
#2
NEXTADDR
SWIOP
SWION
+VIO
CSN/IO0
TMC5072
#3
NEXTADDR
SWIOP
SWION
+VIO
TXD
RIDLE
+VIO
RIDLE forces stop bit level in idle conditions,
3k3 is sufficient with 14 slaves
RXD
10k 10k
address 0, IO0 is high-Z address 1 address 1
program to address 254 & set IO0 low address 0, IO0 is high-Z address 1
address 254 program to address 253 & set IO0 low address 0
address 254 address 253 program to address 252 & set IO0 low
Addressing phase 1:
Addressing phase 2:
Addressing phase 3:
Addressing phase 4:
EXAMPLE FOR ADDRESSING UP TO 255 TMC5072
Addressing phase X:continue procedure
Figure 5.1 Addressing multiple TMC5072 via single wire interface using chaining
Proceed as follows:
- Tie the NEXTADDR pin of your first TMC5072 to GND.
- Interconnect one of the general purpose IO-pins of the first TMC5072 to the next drivers
NEXTADDR pin using an additional pull-up resistor. Connect further drivers in the same
fashion.
- Now, the first driver responds to address 0. Following drivers are set to address 1.
- Program the first driver to its dedicated slave address. Note: once a driver is initialized with
its slave address, its general purpose output, which is tied to the next drivers NEXTADDR has
to be programmed as output and set to 0.
- Now, the second driver is accessible and can get its slave address. Further units can be
programmed to their slave addresses sequentially.
an? mm 6 g g T éé e3 EXTADDR éé es ‘ L
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 25
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Master CPU
(µC with RS485
tranceiver)
TMC5072
#1
NEXTADDR
CSN/IO0
SWIOP
SWION
TMC5072
#2
NEXTADDR
SWIOP
SWION
TMC5072
#3
SWIOP
SWION
A
B
Addressing phase 1: address 0, IO0 high address 1 address 1
Addressing phase 2: program to address 254 & set IO0 low address 0, IO0 high address 1
Addressing phase 3: address 254 program to address 253 & set NAO low address 0, IO0 high
Addressing phase 4: address 254 address 253 program to address 252 & set IO0 low
1k
+VIO
CSN/IO0
NEXTADDR
EXAMPLE FOR ADDRESSING UP TO 255 TMC5072
Addressing phase X:continue procedure
RTERM RTERM
RFILT
CFILT
RFILT
CFILT
+VIO
10k
+VIO
10k
Figure 5.2 Addressing multiple TMC5072 via differential interface, additional filtering for NEXTADDR
A different scheme (not shown) uses bus switches (like 74HC4066) to connect the bus to the next unit
in the chain without using the NAI input. The bus switch can be controlled in the same fashion, using
the NAO output to enable it (low level shall enable the bus switch). Once the bus switch is enabled it
allows addressing the next bus segment. As bus switches add a certain resistance, the maximum
number of nodes will be reduced.
It is possible to mix different styles of addressing in a system. For example a system using two
boards with each two TMC5072 can have both devices on a board with a different level on NEXTADDR,
while the next board is chained using analog switches separating the bus until the drivers on the first
board have been programmed.
SDDIRING SDOIRING SDOIRING NEXTADDR NEXTADDR NEXTADDR
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 26
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5.5 Ring Mode
In a second mode of operation, all slaves are cascaded in a ring. The intention is to allow a simple
scheme of addressing without the need for additional NEXTADDR wires. At the same time, the
distance between each two chips can be kept short due to the chain structure, and the load on each
line is only a single input. Therefore the logical ring is optimum when wiring cost is critical. In case
the physical structure more resembles a line rather than a ring, the devices can be cascaded in a way
that each second IC is chained in direction left to right and back. This way, the distance from the last
slave’s data output to the master is no longer than the distance between three slaves.
Master CPU
(µC with UART)
TMC5072
#1
NEXTADDR
SWIOP
SWION
TMC5072
#2
NEXTADDR
SWIOP
SWION
TMC5072
#n
SWIOP
SWION
TXD
RXD
+VIO
SDO/RING
+VIO
SDO/RING
NEXTADDR
+VIO
SDO/RING
Figure 5.3 Ring Mode Example
The ring mode is enabled by tying SDO/RING high and enabling UART mode. In this mode, SWIO_P is
the data input (CMOS level), while SWIO_N is the data output. SWIO_N stays high (idle state) and does
forward data coming in via SWIO_P, until SLAVEADDR has been programmed. This way, the
addressing phase can be accomplished for a number of cascaded slaves. All data is forwarded from
SWIO_P to SWIO_N after the address setting has been programmed to a value different from 0.
Having addressed all slaves in the chain allows master requests to go to all slaves, while slave
response travels via all devices to the master. The NEXTADDR input is not required for addressing in
this mode, unless two rings with a common start point are intended. Please be aware, that data can
only pass from any slave through the ring structure back to the master after all slaves have been
assigned an address different from 0. Do not assign two identical addresses.
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 27
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6 Register Mapping
This chapter gives an overview of the complete register set. Some of the registers bundling a number
of single bits are detailed in extra tables. The functional practical application of the settings is
detailed in dedicated chapters.
Note
- All registers become reset to 0 upon power up, unless otherwise noted.
- Add 0x80 to the address Addr for write accesses!
NOTATION OF HEXADECIMAL AND BINARY NUMBERS
0x
precedes a hexadecimal number, e.g. 0x04
%
precedes a multi-bit binary number, e.g. %100
NOTATION OF R/W FIELD
R
Read only
W
Write only
R/W
Read- and writable register
R+C
Clear upon read
OVERVIEW REGISTER MAPPING
REGISTER
DESCRIPTION
General Configuration Registers
These registers contain
- global configuration
- global status flags
- slave address configuration
- and I/O configuration
Ramp Generator Motion Control Register Set
This register set offers registers for
- choosing a ramp mode
- choosing velocities
- homing
- acceleration and deceleration
- target positioning
Ramp Generator Driver Feature Control Register Set
This register set offers registers for
- driver current control
- setting thresholds for coolStep operation
- setting thresholds for different chopper modes
- setting thresholds for dcStep operation
- reference switch and stallGuard2 event
configuration
- a ramp and reference switch status register
Encoder Register Set
The encoder register set offers all registers needed for
proper ABN encoder operation.
Motor Driver Register Set
This register set offers registers for
- setting / reading out microstep table and
counter
- chopper and driver configuration
- coolStep and stallGuard2 configuration
- dcStep configuration, and
- reading out stallGuard2 values and driver error
flags
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6.1 General Configuration Registers
GENERAL CONFIGURATION REGISTERS (0X00…0X0F)
R/W
Addr
n
Register
Description / bit names
RW
0x00
11
GCONF
Bit
GCONF Global configuration flags
0
single_driver
0: Two motors can be operated.
1: Single motor, double current operation - driver 2
outputs are identical to driver 1, all driver 2
related controls are unused in this mode.
Attention: Set correctly before driver enable!
1
stepdir1_enable
0: Motor 1 is driven by internal ramp generator 1.
1: External control of motor 1 using STEP1 and DIR1
ramp generator 1 is not used.
2
stepdir2_enable
0: Motor 2 is driven by internal ramp generator 2.
1: External control of motor 2 using STEP2 and DIR2
ramp generator 2 is not used.
3
poscmp_enable
0: Encoder 1 A and B inputs are mapped.
1: Position compare pulse (PP) and interrupt output
(INT) are available, Encoder 1 is unused.
4
enc1_refsel
0: N channel 1 mapped depending on interface to
SWIOP (if SW_SEL=0) or IO0 (if SW_SEL=1).
1: N channel 1 mapped to REFL1.
5
enc2_enable
0: Right reference switches are available.
1: Encoder 2 A and B signals are mapped to REFR1
and REFR2 inputs.
6
enc2_refsel
0: N channel 2 mapped depending on interface to
SWION (if SW_SEL=0) or IO1 (if SW_SEL=1).
1: N channel 2 mapped to REFL2.
7
test_mode
0: Normal operation
1: Enable analog test output on pin REFR2
SLAVEADDR selects the function of REFR2:
0…4: T120, DAC1, VDDH1, DAC2, VDDH2
Attention: Not for user, set to 0 for normal operation!
8
shaft1
1: Inverse motor 1 direction
9
shaft2
1: Inverse motor 2 direction
10
lock_gconf
1: GCONF is locked against further write access.
11
dc_sync
1: Synchronizes both motors, when both are
operated in dcStep mode. The slower motor will
slow down the other motor, too.
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 29
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GENERAL CONFIGURATION REGISTERS (0X00…0X0F)
R/W
Addr
n
Register
Description / bit names
R+C
0x01
4
GSTAT
Bit
GSTAT Global status flags
0
reset
1: Indicates that the IC has been reset since the last
read access to GSTAT. All registers have been
cleared to reset values.
1
drv_err1
1: Indicates, that driver 1 has been shut down due
to overtemperature or short circuit detection
since the last read access. Read DRV_STATUS1 for
details. The flag can only be reset when all error
conditions are cleared.
2
drv_err2
1: Indicates, that driver 2 has been shut down due
to overtemperature or short circuit detection
since the last read access. Read DRV_STATUS2 for
details. The flag can only be reset when all error
conditions are cleared.
3
uv_cp
1: Indicates an undervoltage on the charge pump.
The driver is disabled in this case.
R
0x02
8
IFCNT
Interface transmission counter. This register becomes
incremented with each successful UART interface write access.
It can be read out to check the serial transmission for lost
data. Read accesses do not change the content. Disabled in SPI
operation. The counter wraps around from 255 to 0.
W
0x03
8
+
4
SLAVECONF
Bit
SLAVECONF
7..0
SLAVEADDR:
Sets the address of unit for the UART interface. The
address becomes incremented by one when the
external address pin NEXTADDR is active.
Range: 0-253 (254), default=0
In ring mode, 0 disables forwarding.
11..8
SENDDELAY:
0, 1: 8 bit times,
2, 3: 3*8 bit times
4, 5: 5*8 bit times
6, 7: 7*8 bit times
8, 9: 9*8 bit times
10, 11: 11*8 bit times
12, 13: 13*8 bit times
14, 15: 15*8 bit times
R
0x04
8
+
8
INPUT
Bit
INPUT
Reads the digital state of all input pins available plus
the state of IO pins set to output.
0
io0_in: IO0 polarity
1
io1_in: IO1 polarity
2
io2_in: IO2 polarity
3
io3_in: IO3 polarity
4
iop_in: IOP pin polarity (always input in SPI mode)
5
ion_in: ION pin polarity (always input in SPI mode)
6
nextaddr_in: NEXTADDR pin polarity
7
drv_enn_in: DRV_ENN pin polarity
8
sw_comp_in: UART input comparator (1: IOP voltage is
above ION voltage). The accuracy is about 20mV.
31..
VERSION: 0x10=version of the IC
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 30
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GENERAL CONFIGURATION REGISTERS (0X00…0X0F)
R/W
Addr
n
Register
Description / bit names
24
Identical numbers mean full digital compatibility.
W
4
+
4
OUTPUT
Bit
OUTPUT
Sets the IO output pin polarity and data direction.
0
io0_out: IO0 output polarity
1
io1_out: IO1 output polarity
2
io2_out: IO2 output polarity
3
-
8
ioddr0 (IO0: 0=input, 1=output)
9
ioddr1 (IO1: 0=input, 1=output)
10
ioddr2 (IO2: 0=input, 1=output)
11
- (IO3 is always input)
W
0x05
32
X_COMPARE
Position comparison register for motor 1 position strobe.
Activate poscmp_enable to get position pulse on output PP.
XACTUAL = X_COMPARE:
- Output PP becomes high. It returns to a low state, if
the positions mismatch.
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 31
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6.2 Ramp Generator Registers
Addresses Addr are specified for motor 1 (upper value) and motor 2 (second address).
6.2.1 Ramp Generator Motion Control Register Set
RAMP GENERATOR MOTION CONTROL REGISTER SET (MOTOR 1: 0X20…0X2D, MOTOR 2: 0X40…0X4D)
R/W
Addr
n
Register
Description / bit names
Range [Unit]
RW
0x20
0x40
2
RAMPMODE
RAMPMODE:
0: Positioning mode (using all A, D and V
parameters)
1: Velocity mode to positive VMAX (using
AMAX acceleration)
2: Velocity mode to negative VMAX (using
AMAX acceleration)
3: Hold mode (velocity remains unchanged,
unless stop event occurs)
0…3
RW
0x21
0x41
32
XACTUAL
Actual motor position (signed)
Hint: This value normally should only be
modified, when homing the drive. In
positioning mode, modifying the register
content will start a motion.
-2^31…
+(2^31)-1
R
0x22
0x42
24
VACTUAL
Actual motor velocity from ramp generator
(signed)
The sign matches the motion direction. A
negative sign means motion to lower
XACTUAL.
+-(2^23)-1
[µsteps / t]
W
0x23
0x43
18
VSTART
Motor start velocity (unsigned)
Set VSTOP VSTART!
0…(2^18)-1
[µsteps / t]
W
0x24
0x44
16
A1
First acceleration between VSTART and V1
(unsigned)
0…(2^16)-1
[µsteps / ta²]
W
0x25
0x45
20
V1
First acceleration / deceleration phase
threshold velocity (unsigned)
0: Disables A1 and D1 phase, use AMAX, DMAX
only
0…(2^20)-1
[µsteps / t]
W
0x26
0x46
16
AMAX
Second acceleration between V1 and VMAX
(unsigned)
This is the acceleration and deceleration value
for velocity mode.
0…(2^16)-1
[µsteps / ta²]
W
0x27
0x47
23
VMAX
Motion ramp target velocity (for positioning
ensure VMAX VSTART) (unsigned)
This is the target velocity in velocity mode. It
can be changed any time during a motion.
0…(2^23)-512
[µsteps / t]
W
0x28
0x48
16
DMAX
Deceleration between VMAX and V1 (unsigned)
0…(2^16)-1
[µsteps / ta²]
W
0x2A
0x4A
16
D1
Deceleration between V1 and VSTOP
(unsigned)
Attention: Do not set 0 in positioning mode,
even if V1=0!
1…(2^16)-1
[µsteps / ta²]
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RAMP GENERATOR MOTION CONTROL REGISTER SET (MOTOR 1: 0X20…0X2D, MOTOR 2: 0X40…0X4D)
R/W
Addr
n
Register
Description / bit names
Range [Unit]
W
0x2B
0x4B
18
VSTOP
Motor stop velocity (unsigned)
Attention: Set VSTOP VSTART!
Attention: Do not set 0 in positioning mode,
minimum 10 recommended!
1…(2^18)-1
[µsteps / t]
W
0x2C
0x4C
16
TZEROWAIT
Waiting time after ramping down to zero
velocity before next movement or direction
inversion can start and before motor power
down starts. Time range is about 0 to 2
seconds.
This setting avoids excess acceleration e.g.
from VSTOP to -VSTART.
0…(2^16)-1 *
512 tCLK
RW
0x2D
0x4D
32
XTARGET
Target position for ramp mode (signed). Write
a new target position to this register in order
to activate the ramp generator positioning in
RAMPMODE=0. Initialize all velocity,
acceleration and deceleration parameters
before.
Hint: The position is allowed to wrap around,
thus, XTARGET value optionally can be treated
as an unsigned number.
Hint: The maximum possible displacement is
+/-((2^31)-1).
Hint: When increasing V1, D1 or DMAX during
a motion, rewrite XTARGET afterwards in order
to trigger a second acceleration phase, if
desired.
-2^31…
+(2^31)-1
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 33
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6.2.2 Ramp Generator Driver Feature Control Register Set
RAMP GENERATOR DRIVER FEATURE CONTROL REGISTER SET (MOTOR 1: 0X30…0X36, MOTOR 2: 0X50…0X56)
R/W
Addr
n
Register
Description / bit names
W
0x30
0x50
5
+
5
+
4
IHOLD_IRUN
Bit
IHOLD_IRUN Driver current control
4..0
IHOLD
Standstill current (0=1/32…31=32/32)
In combination with stealthChop mode, setting
IHOLD=0 allows to choose freewheeling or coil
short circuit for motor stand still.
12..8
IRUN
Motor run current (0=1/32…31=32/32)
Hint: Choose sense resistors in a way, that normal
IRUN is 16 to 31 for best microstep performance.
19..16
IHOLDDELAY
Controls the number of clock cycles for motor
power down after a motion as soon as TZEROWAIT
has expired. The smooth transition avoids a motor
jerk upon power down.
0: instant power down
1..15: Delay per current reduction step in multiple
of 2^18 clocks
W
0x31
0x51
23
VCOOLTHRS
This is the lower threshold velocity for switching on smart
energy coolStep and stallGuard feature. Further it is the upper
operation velocity for stealthChop. (unsigned)
Set this parameter to disable coolStep at low speeds, where it
cannot work reliably. The stop on stall function (enable with
sg_stop when using internal motion controller) becomes
enabled when exceeding this velocity. In non-dcStep mode, it
becomes disabled again once the velocity falls below this
threshold. This allows for homing procedures with stallGuard
by blanking out the stallGuard signal at low velocities (will not
work in combination with stealthChop).
VHIGH ≥ |VACT| VCOOLTHRS:
- coolStep and stop on stall are enabled, if configured
- Voltage PWM mode stealthChop is switched off, if
configured
(Only bits 22..8 are used for value and for comparison)
W
0x32
0x52
23
VHIGH
This velocity setting allows velocity dependent switching into
a different chopper mode and fullstepping to maximize torque.
(unsigned)
|VACT| ≥ VHIGH:
- coolStep is disabled (motor runs with normal current
scale)
- If vhighchm is set, the chopper switches to chm=1
with TFD=0 (constant off time with slow decay, only).
- If vhighfs is set, the motor operates in fullstep mode.
- Voltage PWM mode stealthChop is switched off, if
configured
(Only bits 22..8 are used for value and for comparison)
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 34
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RAMP GENERATOR DRIVER FEATURE CONTROL REGISTER SET (MOTOR 1: 0X30…0X36, MOTOR 2: 0X50…0X56)
R/W
Addr
n
Register
Description / bit names
W
0x33
0x53
23
VDCMIN
Automatic commutation dcStep becomes enabled above
velocity VDCMIN (unsigned)
In this mode, the actual position is determined by the sensor-
less motor commutation and becomes fed back to XACTUAL. In
case the motor becomes heavily loaded, VDCMIN also is used
as the minimum step velocity.
0: Disable, dcStep off
|VACT| VDCMIN ≥ 256:
- Triggers the same actions as exceeding VHIGH.
- Switches on automatic commutation dcStep
Hint: Also set bits vhighfs and vhighchm and set DCCTRL
parameters in order to operate dcStep.
(Only bits 228 are used for value and for comparison)
RW
0x34
0x54
12
SW_MODE
Switch mode configuration
See separate table!
R+C
0x35
0x55
14
RAMP_STAT
Ramp status and switch event status
See separate table!
R
0x36
0x56
32
XLATCH
Ramp generator latch position, latches XACTUAL upon a
programmable switch event (see SW_MODE).
Hint: The encoder position can be latched to ENC_LATCH
together with XLATCH to allow consistency checks.
Time reference t for velocities: t = 2^24 / fCLK
Time reference ta² for accelerations: ta² = 2^41 / (fCLK
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 35
www.trinamic.com
6.2.2.1 SW_MODE Reference Switch & stallGuard2 Event Configuration Register
0X34, 0X54: SW_MODE REFERENCE SWITCH AND STALLGUARD2 EVENT CONFIGURATION REGISTER
Bit
Name
Comment
11
en_softstop
0: Hard stop
1: Soft stop
The soft stop mode always uses the deceleration ramp settings DMAX, V1,
D1, VSTOP and TZEROWAIT for stopping the motor. A stop occurs when
the velocity sign matches the reference switch position (REFL for negative
velocities, REFR for positive velocities) and the respective switch stop
function is enabled.
A hard stop also uses TZEROWAIT before the motor becomes released.
Attention: Do not use soft stop in combination with stallGuard2.
10
sg_stop
1: Enable stop by stallGuard2. Disable to release motor after stop event.
Attention: Do not enable during motor spin-up, wait until the motor
velocity exceeds a certain value, where stallGuard2 delivers a stable result,
or set VCOOLTHRS to a suitable value.
9
en_latch_encoder
1: Latch encoder position to ENC_LATCH upon reference switch event.
8
latch_r_inactive
1: Activates latching of the position to XLATCH upon an inactive going
edge on the right reference switch input REFR. The active level is defined
by pol_stop_r.
7
latch_r_active
1: Activates latching of the position to XLATCH upon an active going edge
on the right reference switch input REFR.
Hint: Activate latch_r_active to detect any spurious stop event by reading
status_latch_r.
6
latch_l_inactive
1: Activates latching of the position to XLATCH upon an inactive going
edge on the left reference switch input REFL. The active level is defined
by pol_stop_l.
5
latch_l_active
1: Activates latching of the position to XLATCH upon an active going edge
on the left reference switch input REFL.
Hint: Activate latch_l_active to detect any spurious stop event by reading
status_latch_l.
4
swap_lr
1: Swap the left and the right reference switch input REFL and REFR
3
pol_stop_r
Sets the active polarity of the right reference switch input
0=non-inverted, high active: a high level on REFR stops the motor
1=inverted, low active: a low level on REFR stops the motor
2
pol_stop_l
Sets the active polarity of the left reference switch input
0=non-inverted, high active: a high level on REFL stops the motor
1=inverted, low active: a low level on REFL stops the motor
1
stop_r_enable
1: Enables automatic motor stop during active right reference switch input
Hint: The motor restarts in case the stop switch becomes released.
0
stop_l_enable
1: Enables automatic motor stop during active left reference switch input
Hint: The motor restarts in case the stop switch becomes released.
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 36
www.trinamic.com
6.2.2.2 RAMP_STAT Ramp and Reference Switch Status Register
0X35, 0X55: RAMP_STAT RAMP AND REFERENCE SWITCH STATUS REGISTER
R/W
Bit
Name
Comment
R
13
status_sg
1: Signals an active stallGuard2 input from the coolStep driver or
from the dcStep unit, if enabled.
Hint: When polling this flag, stall events may be missed activate
sg_stop to be sure not to miss the stall event.
R+C
12
second_move
1: Signals that the automatic ramp required moving back in the
opposite direction, e.g. due to on-the-fly parameter change
(Flag is cleared upon reading)
R
11
t_zerowait_
active
1: Signals, that TZEROWAIT is active after a motor stop. During this
time, the motor is in standstill.
R
10
vzero
1: Signals, that the actual velocity is 0.
R
9
position_
reached
1: Signals, that the target position is reached.
This flag becomes set while XACTUAL and XTARGET match.
R
8
velocity_
reached
1: Signals, that the target velocity is reached.
This flag becomes set while VACTUAL and VMAX match.
R+C
7
event_pos_
reached
1: Signals, that the target position has been reached
(position_reached becoming active).
(Flag and interrupt condition are cleared upon reading)
This bit is ORed to the interrupt output signal.
R+C
6
event_stop_
sg
1: Signals an active StallGuard2 stop event.
Reading the register will clear the stall condition and the motor may
re-start motion, unless the motion controller has been stopped.
(Flag and interrupt condition are cleared upon reading)
This bit is ORed to the interrupt output signal.
R
5
event_stop_r
1: Signals an active stop right condition due to stop switch.
The stop condition and the interrupt condition can be removed by
setting RAMP_MODE to hold mode or by commanding a move to the
opposite direction. In soft_stop mode, the condition will remain
active until the motor has stopped motion into the direction of the
stop switch. Disabling the stop switch or the stop function also
clears the flag, but the motor will continue motion.
This bit is ORed to the interrupt output signal.
4
event_stop_l
1: Signals an active stop left condition due to stop switch.
The stop condition and the interrupt condition can be removed by
setting RAMP_MODE to hold mode or by commanding a move to the
opposite direction. In soft_stop mode, the condition will remain
active until the motor has stopped motion into the direction of the
stop switch. Disabling the stop switch or the stop function also
clears the flag, but the motor will continue motion.
This bit is ORed to the interrupt output signal.
R+C
3
status_latch_r
1: Latch right ready
(enable position latching using SWITCH_MODE settings
latch_r_active or latch_r_inactive)
(Flag is cleared upon reading)
2
status_latch_l
1: Latch left ready
(enable position latching using SWITCH_MODE settings
latch_l_active or latch_l_inactive)
(Flag is cleared upon reading)
R
1
status_stop_r
Reference switch right status (1=active)
0
status_stop_l
Reference switch left status (1=active)
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 37
www.trinamic.com
6.3 Encoder Registers
ENCODER REGISTER SET (MOTOR 1: 0X38…0X3C, MOTOR 2: 0X58…0X5C)
R/W
Addr
n
Register
Description / bit names
Range [Unit]
RW
0x38
0x58
12
ENCMODE
Encoder configuration and use of N channel
See separate table!
RW
0x39
0x59
32
X_ENC
Actual encoder position (signed)
-2^31…
+(2^31)-1
W
0x3A
0x5A
32
ENC_CONST
Accumulation constant (signed)
16 bit integer part, 16 bit fractional part
X_ENC accumulates
+/- ENC_CONST / (2^16*X_ENC) (binary)
or
+/-ENC_CONST / (10^4*X_ENC) (decimal)
ENCMODE bit enc_sel_decimal switches
between decimal and binary setting.
Use the sign, to match rotation direction!
binary:
± [µsteps/2^16]
±(0
32767.999847)
decimal:
±(0.0
32767.9999)
reset default =
1.0 (=65536)
R+C
0x3B
0x5B
1
ENC_STATUS
bit 0: n_event
1: Encoder N event detected. Status bit is
cleared on read: Read (R) + clear (C)
This bit is ORed to the interrupt output
signal.
R
0x3C
0x5C
32
ENC_LATCH
Encoder position X_ENC latched on N event
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 38
www.trinamic.com
6.2.2.3 ENCMODE Encoder Register
0X38, 0X58: ENCMODE ENCODER REGISTER
Bit
Name
Comment
11
latch_now
1
Latch X_ENC (and XACTUAL if selected by bit latch_x_act) directly
upon write access to ENCMODE. This allows checking the encoder
deviation by comparing the X_LATCH and ENC_LATCH.
0
No action
10
enc_sel_decimal
0
Encoder prescaler divisor binary mode:
Counts ENC_CONST(fractional part) /65536
1
Encoder prescaler divisor decimal mode:
Counts in ENC_CONST(fractional part) /10000
9
latch_x_act
1: Also latch XACTUAL position together with X_ENC.
Allows latching the ramp generator position upon an N channel event as
selected by pos_edge and neg_edge.
8
clr_enc_x
0
Upon N event, X_ENC becomes latched to ENC_LATCH only
1
Latch and additionally clear encoder counter X_ENC at N-event
7
neg_edge
n p
N channel event sensitivity
6
pos_edge
0 0
N channel event is active during an active N event level
0 1
N channel is valid upon active going N event
1 0
N channel is valid upon inactive going N event
1 1
N channel is valid upon active going and inactive going N event
5
clr_once
1: Latch or latch and clear X_ENC on the next N event following the write
access
4
clr_cont
1: Always latch or latch and clear X_ENC upon an N event (once per
revolution, it is recommended to combine this setting with edge sensitive
N event)
3
ignore_AB
0
An N event occurs only when polarities given by
pol_N, pol_A and pol_B match.
1
Ignore A and B polarity for N channel event
2
pol_N
Defines active polarity of N (0=neg., 1=pos.)
1
pol_B
Required B polarity for an N channel event (0=neg., 1=pos.)
0
pol_A
Required A polarity for an N channel event (0=neg., 1=pos.)
1024 1024
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 39
www.trinamic.com
6.4 Microstep Table Registers
COMMON MICROSTEP TABLE REGISTERS (MOTOR 1/2: 0X60…0X69)
R/W
Addr
n
Register
Description / bit names
Range [Unit]
W
0x60
32
MSLUT[0]
microstep
table entries
0…31
Each bit gives the difference between entry x
and entry x+1 when combined with the cor-
responding MSLUTSEL W bits:
0: W= %00: -1
%01: +0
%10: +1
%11: +2
1: W= %00: +0
%01: +1
%10: +2
%11: +3
This is the differential coding for the first
quarter of a wave. Start values for CUR_A and
CUR_B are stored for MSCNT position 0 in
START_SIN and START_SIN90.
ofs31, ofs30, …, ofs01, ofs00
ofs255, ofs254, …, ofs225, ofs224
32x 0 or 1
reset default=
sine wave
table
W
0x61
0x67
7
x
32
MSLUT[1...7]
microstep
table entries
32…255
7x
32x 0 or 1
reset default=
sine wave
table
W
0x68
32
MSLUTSEL
This register defines four segments within
each quarter MSLUT wave. Four 2 bit entries
determine the meaning of a 0 and a 1 bit in
the corresponding segment of MSLUT.
See separate table!
0<X1<X2<X3
reset default=
sine wave
table
W
0x69
8
+
8
MSLUTSTART
bit 7… 0: START_SIN
bit 23… 16: START_SIN90
START_SIN gives the absolute current at
microstep table entry 0.
START_SIN90 gives the absolute current for
microstep table entry at positions 256.
Start values are transferred to the microstep
registers CUR_A and CUR_B, whenever the
reference position MSCNT=0 is passed.
START_SIN
reset default
=0
START_SIN90
reset default
=247



MIRCOSTEP TABLE CALCULATION FOR A SINE WAVE EQUIVALENT TO THE POWER ON DEFAULT:
- i:[0… 255] is the table index
- The amplitude of the wave is 248. The resulting maximum positive value is 247 and the
maximum negative value is -248.
- The round function rounds values from 0.5 to 1.4999 to 1
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 40
www.trinamic.com
6.4.1 MSLUTSEL Look up Table Segmentation Definition
0X68: MSLUTSEL LOOK UP TABLE SEGMENTATION DEFINITION
Bit
Name
Function
Comment
31
X3
LUT segment 3 start
The sine wave look up table can be divided into up to
four segments using an individual step width control
entry Wx. The segment borders are selected by X1, X2
and X3.
Segment 0 goes from 0 to X1-1.
Segment 1 goes from X1 to X2-1.
Segment 2 goes from X2 to X3-1.
Segment 3 goes from X3 to 255.
For defined response the values shall satisfy:
0<X1<X2<X3
30
29
28
27
26
25
24
23
X2
LUT segment 2 start
22
21
20
19
18
17
16
15
X1
LUT segment 1 start
14
13
12
11
10
9
8
7
W3
LUT width select from
ofs(X3) to ofs255
Width control bit coding W0W3:
%00: MSLUT entry 0, 1 select: -1, +0
%01: MSLUT entry 0, 1 select: +0, +1
%10: MSLUT entry 0, 1 select: +1, +2
%11: MSLUT entry 0, 1 select: +2, +3
6
5
W2
LUT width select from
ofs(X2) to ofs(X3-1)
4
3
W1
LUT width select from
ofs(X1) to ofs(X2-1)
2
1
W0
LUT width select from
ofs00 to ofs(X1-1)
0
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 41
www.trinamic.com
6.5 Motor Driver Registers
MOTOR DRIVER REGISTER SET (MOTOR 1: 0X6A…0X6F, MOTOR 2: 0X7A…0X7F)
R/W
Addr
n
Register
Description / bit names
Range [Unit]
R
0x6A
0x7A
10
MSCNT
Microstep counter. Indicates actual position
in the microstep table for CUR_A. CUR_B uses
an offset of 256.
Hint: Move to a position where MSCNT is
zero before re-initializing MSLUTSTART or
MSLUT and MSLUTSEL.
0…1023
R
0x6B
0x7B
9
+
9
MSCURACT
bit 8… 0: CUR_A (signed):
Actual microstep current for
motor phase A as read from
MSLUT (not scaled by current)
bit 24… 16: CUR_B (signed):
Actual microstep current for
motor phase B as read from
MSLUT (not scaled by current)
+/-0...255
RW
0x6C
0x7C
32
CHOPCONF
chopper and driver configuration
See separate table!
W
0x6D
0x7D
25
COOLCONF
coolStep smart current control register
and stallGuard2 configuration
See separate table!
W
0x6E
0x7E
8
+
8
DCCTRL
dcStep (DC) automatic commutation
configuration register:
bit 7… 0: DC_TIME: Upper PWM on time
limit for commutation (DC_TIME *
1/fCLK). Set slightly above effective
blank time TBL.
bit 15… 8: DC_SG: Max. PWM on time for
step loss detection using dcStep
stallGuard2 in dcStep mode.
(DC_SG * 16/fCLK)
Set slightly higher than
DC_TIME/16
0=disable
R
0x6F
0x7F
32
DRV_
STATUS
stallGuard2 value and driver error flags
See separate table!
m
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 42
www.trinamic.com
6.5.1 CHOPCONF Chopper Configuration
0X6C, 0X7C: CHOPCONF CHOPPER CONFIGURATION
Bit
Name
Function
Comment
31
-
reserved
set to 0
30
diss2g
short to GND
protection disable
0: Short to GND protection is on
1: Short to GND protection is disabled
29
dedge
enable double edge
step pulses
1: Enable step impulse at each step edge to reduce
step frequency requirement.
Attention: Use only in Step/Dir mode.
Step/Dir options, set 0 when stepdir_enable = 0
28
intpol16
16 microsteps with
interpolation
1: In 16 microstep mode with Step/Dir interface, the
microstep resolution becomes extrapolated to 256
microsteps for smoothest motor operation
27
mres3
MRES
micro step resolution
%0000:
Native 256 microstep setting. Use this setting when
the IC is operated with the internal ramp generator.
26
mres2
25
mres1
24
mres0
%0001 … %1000:
128, 64, 32, 16, 8, 4, 2, FULLSTEP
Reduced microstep resolution for Step/Dir operation.
The resolution gives the number of microstep entries
per sine quarter wave.
Especially when switching to a low resolution of 8
microsteps and below, take care to switch at certain
microstep positions. The switching position
determines the sequence of patterns.
step width=2^MRES [microsteps]
Hint: Reduced microstep resolutions are also useful
in special cases to extend the acceleration or
position range
23
-
reserved
set to 0
22
-
21
-
20
-
19
vhighchm
high velocity chopper
mode
This bit enables switching to chm=1 and fd=0, when VHIGH
is exceeded. This way, a higher velocity can be achieved.
Can be combined with vhighfs=1. If set, the TOFF setting
automatically becomes doubled during high velocity
operation in order to avoid doubling of the chopper
frequency.
18
vhighfs
high velocity fullstep
selection
This bit enables switching to fullstep, when VHIGH is
exceeded. Switching takes place only at 45° position.
The fullstep target current uses the current value from
the microstep table at the 45° position.
17
vsense
sense resistor voltage
based current scaling
0: Low sensitivity, high sense resistor voltage
1: High sensitivity, low sense resistor voltage
16
tbl1
TBL
blank time select
%00 … %11:
Set comparator blank time to 16, 24, 36 or 54 clocks
Hint: %01 or %10 recommended for most applications
15
tbl0
14
chm
chopper mode
0
Standard mode (spreadCycle)
1
Constant off time with fast decay time.
Fast decay time is also terminated when the
negative nominal current is reached. Fast decay is
after on time.
13
rndtf
random TOFF time
0
Chopper off time is fixed as set by TOFF
1
Random mode, TOFF is random modulated by
dNCLK= -12 … +3 clocks.
12
disfdcc
fast decay mode
chm=1:
disfdcc=1 disables current comparator usage for termi-
nation of the fast decay cycle
ox
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 43
www.trinamic.com
0X6C, 0X7C: CHOPCONF CHOPPER CONFIGURATION
Bit
Name
Function
Comment
11
fd3
TFD [3]
chm=1:
MSB of fast decay time setting TFD
10
hend3
HEND
hysteresis low value
OFFSET
sine wave offset
chm=0
%0000 … %1111:
Hysteresis is -3, -2, -1, 0, 1, …, 12
(1/512 of this setting adds to current setting)
This is the hysteresis value which becomes
used for the hysteresis chopper.
9
hend2
8
hend1
7
hend0
chm=1
%0000 … %1111:
Offset is -3, -2, -1, 0, 1, …, 12
This is the sine wave offset and 1/512 of the
value becomes added to the absolute value
of each sine wave entry.
6
hstrt2
HSTRT
hysteresis start value
added to HEND
chm=0
%000 … %111:
Add 1, 2, …, 8 to hysteresis low value HEND
(1/512 of this setting adds to current setting)
Attention: Effective HEND+HSTRT 16.
Hint: Hysteresis decrement is done each 16
clocks
5
hstrt1
4
hstrt0
TFD [2..0]
fast decay time setting
chm=1
Fast decay time setting (MSB: fd3):
%0000 … %1111:
Fast decay time setting TFD with
NCLK= 32*HSTRT (%0000: slow decay only)
3
toff3
TOFF off time
and driver enable
Off time setting controls duration of slow decay phase
NCLK= 12 + 32*TOFF
%0000: Driver disable, all bridges off
%0001: 1 use only with TBL 36 clocks
%0010 … %1111: 2 … 15
2
toff2
1
toff1
0
toff0
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 44
www.trinamic.com
6.5.2 COOLCONF Smart Energy Control coolStep and stallGuard2
0X6D, 0X7D: COOLCONF SMART ENERGY CONTROL COOLSTEP AND STALLGUARD2
Bit
Name
Function
Comment
-
reserved
set to 0
24
sfilt
stallGuard2 filter
enable
0
Standard mode, high time resolution for
stallGuard2
1
Filtered mode, stallGuard2 signal updated for each
four fullsteps only to compensate for motor pole
tolerances
23
-
reserved
set to 0
22
sgt6
stallGuard2 threshold
value
This signed value controls stallGuard2 level for stall
output and sets the optimum measurement range for
readout. A lower value gives a higher sensitivity. Zero is
the starting value working with most motors.
-64 to +63: A higher value makes stallGuard2 less
sensitive and requires more torque to
indicate a stall.
21
sgt5
20
sgt4
19
sgt3
18
sgt2
17
sgt1
16
sgt0
15
seimin
minimum current for
smart current control
0: 1/2 of current setting (IRUN)
1: 1/4 of current setting (IRUN)
14
sedn1
current down step
speed
%00: For each 32 stallGuard2 values decrease by one
%01: For each 8 stallGuard2 values decrease by one
%10: For each 2 stallGuard2 values decrease by one
%11: For each stallGuard2 value decrease by one
13
sedn0
12
-
reserved
set to 0
11
semax3
stallGuard2 hysteresis
value for smart current
control
If the stallGuard2 result is equal to or above
(SEMIN+SEMAX+1)*32, the motor current becomes
decreased to save energy.
%0000 … %1111: 0 … 15
10
semax2
9
semax1
8
semax0
7
-
reserved
set to 0
6
seup1
current up step width
Current increment steps per measured stallGuard2 value
%00 … %11: 1, 2, 4, 8
5
seup0
4
-
reserved
set to 0
3
semin3
minimum stallGuard2
value for smart current
control and
smart current enable
If the stallGuard2 result falls below SEMIN*32, the motor
current becomes increased to reduce motor load angle.
%0000: smart current control coolStep off
%0001 … %1111: 1 … 15
2
semin2
1
semin1
0
semin0
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 45
www.trinamic.com
6.5.3 DRV_STATUS stallGuard2 Value and Driver Error Flags
0X6F, 0X7F: DRV_STATUS STALLGUARD2 VALUE AND DRIVER ERROR FLAGS
Bit
Name
Function
Comment
31
stst
standstill indicator
This flag indicates motor stand still in each operation mode. It
is especially useful for step & dir mode.
30
olb
open load indicator
phase B
1: Open load detected on phase A or B.
Hint: This is just an informative flag. The driver takes no action
upon it. False detection may occur in fast motion and
standstill. Check during slow motion or after a motion, only.
29
ola
open load indicator
phase A
28
s2gb
short to ground
indicator phase B
1: Short to GND detected on phase A or B. The driver becomes
disabled. The flags stay active, until the driver is disabled by
software (TOFF=0) or by the ENN input.
27
s2ga
short to ground
indicator phase A
26
otpw
overtemperature pre-
warning flag
1: Overtemperature pre-warning threshold is exceeded.
The overtemperature pre-warning flag is common for both
drivers.
25
ot
overtemperature flag
1: Overtemperature limit has been reached. Drivers become
disabled until otpw is also cleared due to cooling down of the
IC.
The overtemperature flag is common for both drivers.
24
stallGuard
stallGuard2 status
1: Motor stall detected (SG_RESULT=0) or dcStep stall in dcStep
mode.
23
-
reserved
Ignore these bits
22
21
20
CS
ACTUAL
actual motor current /
smart energy current
Actual current control scaling, for monitoring smart energy
current scaling controlled via settings in register COOLCONF, or
for monitoring the function of the automatic current scaling.
19
18
17
16
15
fsactive
full step active
indicator
1: Indicates that the driver has switched to fullstep as defined
by chopper mode settings and velocity thresholds.
14
-
reserved
Ignore these bits
13
12
11
10
9
SG_
RESULT
stallGuard2 result
respectively PWM on
time for coil A in stand
still for motor
temperature detection
Mechanical load measurement:
The stallGuard2 result gives a means to measure mechanical
motor load. A higher value means lower mechanical load. A
value of 0 signals highest load. With optimum SGT setting,
this is an indicator for a motor stall. The stall detection
compares SG_RESULT to 0 in order to detect a stall. SG_RESULT
is used as a base for coolStep operation, by comparing it to a
programmable upper and a lower limit. It is not applicable in
stealthChop mode.
SG_RESULT is also applicable when dcStep is active.
stallGuard2 works best with microstep operation.
Temperature measurement:
In standstill, no stallGuard2 result can be obtained. SG_RESULT
shows the chopper on-time for motor coil A instead. If the
motor is moved to a determined microstep position at a
certain current setting, a comparison of the chopper on-time
can help to get a rough estimation of motor temperature. As
the motor heats up, its coil resistance rises and the chopper
on-time increases.
8
7
6
5
4
3
2
1
0
fPWM fox W44W——
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 46
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6.6 Voltage PWM mode stealthChop
MOTOR DRIVER PWM REGISTER SET (MOTOR 1: 0X10…0X17, MOTOR 2: 0X18…0X1F)
R/W
Addr
n
Register
Description / bit names
Range [Unit]
W
0x10
0x18
22
PWMCONF
Voltage PWM mode chopper configuration
See separate table!
R
0x11
0x19
8
PWM_
STATUS
Actual PWM scaler (255=max. Voltage)
0…255
6.6.1 PWMCONF Voltage PWM mode stealthChop
0X10, 0X18: PWMCONF VOLTAGE MODE PWM
Bit
Name
Function
Comment
-
reserved
Set to 0
21
freewheel1
Allows different
standstill modes
Stand still option when motor current setting is zero
(I_HOLD=0).
%00: Normal operation
%01: Freewheeling
%10: Coil shorted using LS drivers
%11: Coil shorted using HS drivers
20
freewheel0
19
-
reserved
Set to 0
18
pwm_
autoscale
PWM automatic
amplitude scaling
0
User defined PWM amplitude. The current settings
have no influence.
1
Enable automatic current control
Attention: When using a user defined sine wave
table, the amplitude of this sine wave table should
not be less than 244. Best results are obtained with
247 to 252 as peak values.
17
pwm_freq1
PWM frequency
selection
%00: fPWM=2/1024 fCLK
%01: fPWM=2/683 fCLK
%10: fPWM=2/512 fCLK
%11: fPWM=2/410 fCLK
16
pwm_freq0
15
PWM_
GRAD
User defined
regulation loop
gradient
(bits 15…12 currently
unused, set to 0)
pwm_
autoscale=0
0: stealthChop disabled
1…15: stealthChop enabled (the actual
value is not used)
14
13
12
11
pwm_
autoscale=1
0: stealthChop disabled
1…15: User defined maximum PWM
amplitude change per half wave (1
to 15)
10
9
8
7
PWM_
AMPL
User defined amplitude
pwm_
autoscale=0
User defined PWM amplitude
The resulting amplitude (0…255) is set by
this value.
6
5
4
3
pwm_
autoscale=1
User defined maximum PWM amplitude
when switching back from current chopper
mode to voltage PWM mode (switch over
velocity defined by TPWMTHRS). Do not set
too low values, as the regulation cannot
measure the current when the actual PWM
value goes below a setting specific value.
Settings above 0x40 recommended.
2
1
0
32 R + 20ml). E 248 32 R + 20ml).
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 47
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7 Current Setting
The internal 5 V supply voltage available at the pin 5VOUT is used as a reference for the coil current
regulation based on the sense resistor voltage measurement. The desired maximum motor current is
set by selecting an appropriate value for the sense resistor. The sense resistor voltage range can be
selected by the vsense bit in CHOPCONF. The low sensitivity setting (high sense resistor voltage,
vsense=0) brings best and most robust current regulation, while high sensitivity (low sense resistor
voltage, vsense=1) reduces power dissipation in the sense resistor. The high sensitivity setting reduces
the power dissipation in the sense resistor by nearly half.
After choosing the vsense setting and selecting the sense resistor, the currents to both coils are
scaled by the 5-bit current scale parameters (IHOLD, IRUN). The sense resistor value is chosen so that
the maximum desired current (or slightly more) flows at the maximum current setting (IRUN =
%11111).
Using the internal sine wave table, which has the amplitude of 248, the RMS motor current can be
calculated by:
 
 
 
The momentary motor current is calculated by:
 
 
 
 
CS is the current scale setting as set by the IHOLD and IRUN and coolStep.
VFS is the full scale voltage as determined by vsense control bit (please refer to electrical
characteristics, VSRTL and VSRTH).
CURA/B is the actual value from the internal sine wave table.
The internal resistance of 20mΩ will be increased by external trace resistance, 5mΩ are realistic.
CHOICE OF RSENSE AND RESULTING MAX. MOTOR CURRENT
RSENSE [Ω]
RMS current [A]
(CS=31, vsense=0)
RMS current [A]
(CS=31, vsense=1)
1.00
0.21
0.12
0.82
0.26
0.15
0.75
0.28
0.16
0.68
0.31
0.18
0.50
0.42
0.24
0.47
0.45
0.25
0.33
0.63
0.35
0.27
0.76
0.43
0.22
0.91
0.51
0.15
1.29*)
0.72
*) Value exceeds upper current rating for single motor operation.
Hint
For best precision of current setting, it is advised to measure and fine tune the current in the
application.
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 48
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Parameter
Description
Setting
Comment
IRUN
Current scale when motor is running. Scales coil
current values as taken from the internal sine
wave table. For high precision motor operation,
work with a current scaling factor in the range 16
to 31, because scaling down the current values
reduces the effective microstep resolution by
making microsteps coarser. This setting also
controls the maximum current value set by
coolStep.
0 … 31
scaling factor
1/32, 2/32, … 32/32
IHOLD
Identical to IRUN, but for motor in stand still.
IHOLD
DELAY
Allows smooth current reduction from run current
to hold current. IHOLDDELAY controls the number
of clock cycles for motor power down after
TZEROWAIT in increments of 2^18 clocks: 0=instant
power down, 1..15: Current reduction delay per
current step in multiple of 2^18 clocks.
Example: When using IRUN=31 and IHOLD=16, 15
current steps are required for hold current
reduction. A IHOLDDELAY setting of 4 thus results
in a power down time of 4*15*2^18 clock cycles,
i.e. roughly one second at 16MHz.
0
instant IHOLD
1 …15
1*218 … 15*218
clocks per current
decrement
vsense
Allows control of the sense resistor voltage range
for full scale current.
0
VFS = 0.32 V
1
VFS = 0.18 V
7.1 Sense Resistors
Sense resistors should be carefully selected. The full motor current flows through the sense resistors.
They also see the switching spikes from the MOSFET bridges. A low-inductance type such as film or
composition resistors is required to prevent spikes causing ringing on the sense voltage inputs
leading to unstable measurement results. A low-inductance, low-resistance PCB layout is essential.
Any common GND path for the two sense resistors must be avoided, because this would lead to
coupling between the two current sense signals. A massive ground plane is best. Please also refer to
layout considerations in chapter 24.
The sense resistor needs to be able to conduct the peak motor coil current in motor standstill
conditions, unless standby power is reduced. Under normal conditions, the sense resistor conducts
less than the coil RMS current, because no current flows through the sense resistor during the slow
decay phases.
The peak sense resistor power dissipation is:
 
For high current applications, power dissipation is halved by using the low vsense setting and using
an adapted resistance value. Please be aware, that in this case any voltage drop in PCB traces has a
larger influence on the result. A compact layout with massive ground plane is best to avoid parasitic
resistance effects.
Farr! n
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 49
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8 stealthChop™
stealthChop is an extremely quiet mode of operation for low and medium velocities. It is
based on a voltage mode PWM. In case of standstill and at low velocities, the motor is
absolutely noiseless. Thus, stealthChop operated stepper motor applications are very
suitable for indoor or home use. The motor operates absolutely free of vibration at low
velocities. With stealthChop, the motor current is applied by driving a certain effective
voltage into the coil, using a voltage mode PWM. There are no more configurations required except
for the regulation of the PWM voltage to yield the motor target current. Two algorithms are provided,
a manual and an automatic mode.
Figure 8.1 Motor coil sine wave current with stealthChop (measured with current probe)
8.1 Two Modes for Current Regulation
In order to match the motor current to a certain level, the voltage mode PWM voltage must be scaled
depending on the actual motor velocity. Several additional factors influence the required voltage level
to drive the motor at the target current: The motor resistance, its back EMF (i.e. directly proportional
to its velocity) as well as actual level of the supply voltage. For the ease of use, two modes of PWM
regulation are provided: An automatic mode using current feedback (pwm_autoscale = 1) and a fixed
scale mode (pwm_autoscale = 0). The fixed scale mode will not react to a change of operating
conditions like the supply voltage or to events like a motor stall, but it provides very stable
amplitude. It does not use nor require any means of current measurement. This is perfect when
motor type, velocity and supply voltage are well known. Since this mode does not measure the actual
current, it will not respond to modification of the current setting, like stand still current reduction.
Therefore we recommend the automatic mode, unless current regulation is not satisfying in the given
operating conditions.
The PWM frequency can be chosen in a range in four steps in order to adapt the frequency divider to
the frequency of the clock source. An optimum setting is slightly above the audible frequency range.
A slightly higher value might bring a benefit for some applications.
CHOICE OF PWM FREQUENCY FOR STEALTHCHOP
Clock frequency
fCLK
PWM_FREQ=%00
fPWM=2/1024 fCLK
PWM_FREQ=%01
fPWM=2/683 fCLK
PWM_FREQ=%10
fPWM=2/512 fCLK
PWM_FREQ=%11
fPWM=2/410 fCLK
18MHz
35.2kHz
52.7kHz
70.3kHz
87.8kHz
16MHz
31.3kHz
46.9kHz
62.5kHz
78.0kHz
(internal)
26kHz
38kHz
52kHz
64kHz
12MHz
23.4kHz
35.1kHz
46.9kHz
58.5kHz
10MHz
19.5kHz
29.3kHz
39.1kHz
48.8kHz
8MHz
15.6kHz
23.4kHz
31.2kHz
39.0kHz
Table 8.1 Choice of PWM frequency green: recommended
WWWWWW WWWWWWWWWW WWWWW : WWWWWW WWWIWWWWW WWWW MW WWW WWWWW rW‘W‘W‘WW WWW WWWWWWWWWW WWWWWWWWWW WIIW WW . (W‘ W WWW WWW WWWWWWWWW ‘ WW H W WWWWWWW WWWIWW WWWWWWW WWWWW W W WWWW W WWWW WWWWWWWW W WWW WWWW WW WWW” WWWWWWW
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 50
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8.2 Automatic Scaling
In stealthChop voltage PWM mode, the autoscaling function (pwm_autoscale = 1) regulates the motor
current to the desired current setting. The driver measures the motor current during the chopper on
time and uses a proportional regulator to regulate the PWM_SCALE in order match the motor current
to the target current. PWM_GRAD is the proportionality coefficient for this regulator. Basically, the
proportionality coefficient should be as small as possible in order to get a stable and soft regulation
behavior, but it must be large enough to allow the driver to quickly react to changes caused by
variation of the motor target current, the motor velocity or effects resulting from changes of the
supply voltage. As the supply voltage level and motor temperature normally change only slowly, a
minimum setting of the regulation gradient often is sufficient (PWM_GRAD=1). If stealthChop
operation is desired for a higher velocity range, variations of the motor back EMF caused by motor
acceleration and deceleration may require a quicker regulation. PWM_GRAD setting should be
optimized for the fastest required acceleration and deceleration ramp (see Figure 8.4). The quality of a
given setting can be examined when monitoring PWM_SCALE and motor velocity. Just as in the
acceleration phase, during a deceleration phase the voltage PWM amplitude must be adapted in order
to keep the motor coil current constant. When the upper acceleration and the upper deceleration used
in the application are identical, the value determined for the acceleration phase will already be
optimum for both.
Figure 8.2 Scope shot: good setting for PWM_GRAD
Figure 8.3 Scope shot: too small setting for PWM_GRAD
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 51
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Velocity
Time
Stand still
PWM scale
PWM reaches
max. amplitude
255
0
Motor current
Nominal current
(sine wave RMS)
RMS current
constant
0
PWM scale
Current may drop due
to high velocity
Velocity
Time
Stand still
PWM scale
255
0
Motor current
Nominal current
(sine wave RMS)
0
PWM scale
PWM_GRAD too small
PWM_GRAD ok
Current drops due to
too small PWM_GRAD
Current overshoots
due to too small
PWM_GRAD
PWM_GRAD ok
Setting for PWM_GRAD ok.
Setting for PWM_GRAD slightly too small.
Figure 8.4 Good and too small setting for PWM_GRAD
Be sure to use a symmetrical sense resistor layout and sense resistor traces of identical length and
well matching sense resistors for best performance.
Quick Start
For a quick start, see the Quick Configuration Guide in chapter 18.
8.2.1 Lower Current Limit
The autoscaling function imposes a lower limit for motor current regulation. As the coil current can
be measured in the shunt resistor during chopper on phase, only, a minimum chopper duty cycle
allowing coil current regulation is given by the blank time as set by TBL and by the chopper
frequency setting. Therefore, the motor specific minimum coil current in stealthChop autoscaling
mode rises with the supply voltage and the chopper frequency. A lower blanking time allows a lower
current limit. Extremely low currents (e.g. for standstill power down) can be realized with the non-
automatic current scaling or with the freewheeling option, only. The run current setting needs to be
kept above the lower limit: In case the PWM_SCALE drops to a too low value, e.g. because the current
scale was too low, the regulator may not be able to recover. The regulator will recover once the
motor is in standstill. The lower motor coil current limit can be calculated from motor parameters and
chopper settings:
  

1024: SD. 512 Sn.
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 52
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With VM the motor supply voltage and RCOIL the motor coil resistance.
ILower Limit can be treated as a thumb value for the minimum possible motor current setting.
Example:
A motor has a coil resistance of 5Ω, the supply voltage is 24V. With TBL=%01 and
PWM_FREQ=%00, tBLANK is 24 clock cycles, fPWM is 2/(1024 clock cycles):
 
 
 

 
For pwm_autoscale mode, a lower coil current limit applies. This limit can be calculated or measured
using a current probe. Keep the motor run-current setting IRUN well above this lower current limit.
8.2.2 PWM_AMPL for Using stealthChop and spreadCycle
When combining stealthChop with spreadCycle or constant off time classic PWM, a switching velocity
can be chosen using VCOOLTHRS. With this, stealthChop is only active at low velocities. Often, a very
low velocity in the range of 1 to a few 10 RPM fits best. In case a high switching velocity is chosen,
special care should be taken for switching back to stealthChop during deceleration, because the phase
jerk can produce a short time overcurrent. (Refer to chapter 8.4 for more details about combining
stealthChop with other chopper modes.)
To avoid a short time overcurrent and to minimize the jerk, the initial amplitude for switching back to
stealthChop at sinking velocity can be determined using the setting PWM_AMPL. Tune PWM_AMPL to a
value which gives a smooth and safe transition back to stealthChop within the application. As a
thumb rule, ½ to ¾ of the last PWM_SCALE value which was valid after the switching event at rising
velocity can be used. For high resistive steppers as well as for low transfer velocities (as set by
VCOOLTHRS), PWM_AMPL can be set to 255 as most universal setting.
Note
The autoscaling function only starts up regulation during motor standstill. After enabling stealthChop
and setting all parameters, be sure to wait until PWM_SCALE has reached a stable state before starting
a motion. Failure to do so will result in zero motor current!
In case the automatic scaling regulation is instable at your desired motion velocity, try modifying the
chopper frequency divider PWM_FREQ. Also adapt the blank time TBL and motor current for best
result.
8.2.3 Acceleration
In automatic current regulation mode (pwm_autoscale = 1), the PWM_GRAD setting should be
optimized for the fastest required acceleration ramp. Use a current probe and check the motor current
during (quick) acceleration. A setting of 1 may result in a too slow regulation, while a setting of 15
responds very quickly to velocity changes, but might produce regulation instabilities in some
constellations. A setting of 4 is a good starting value.
Hint
Operate the motor within your application when exploring stealthChop. Motor performance often is
better with a mechanical load, because it prevents the motor from stalling due mechanical oscillations
which can occur without load.
8.3 Fixed Scaling
Non-automatic, fixed scaling scales the stealthChop amplitude based on the user defined value
PWM_AMPL. The stepper motor has a certain coil resistance and thus needs a certain voltage
amplitude to yield a target current based on the basic formula I=U/R. With R being the coil resistance,
U the supply voltage scaled by the PWM value, the current I results. The initial value for PWM_AMPL
at low velocities can be calculated:
#3 N“ 374
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 53
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 
With VM the motor supply voltage and ICOIL the target RMS current
The effective PWM voltage UPWM (1/SQRT(2) x peak value) results considering the 8 bit resolution and
248 sine wave peak for the actual PWM amplitude shown as PWM_SCALE:
 
 



With rising motor velocity, the motor generates an increasing back EMF voltage. The back EMF voltage
is proportional to the motor velocity. It reduces the PWM voltage effective at the coil resistance and
thus current decreases. A higher scale value is necessary to compensate for this. When a higher value
is choosen, it should be made sure, that the maximum driver current is not exceeded during the
acceleration phase. This can be checked with the above formula. A short time excess current will not
do harm to the motor.
Hint
The setting for PWM_AMPL can easily be optimized by tracing the motor current with a current probe
on the oscilloscope. It is not even necessary to calculate the formulas if you carefully start with a low
setting for both.
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 54
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8.4 Combining stealthChop with other Chopper Modes
The TMC5072 allows combining stealthChop and different chopper modes based on velocity
thresholds. This way, the optimum chopper principle can be chosen for different velocity ranges. As a
first step, both chopper principles should be parameterized and optimized individually. In a next step,
a transfer velocity has to be fixed. For example, stealthChop operation is used for precise low speed
positioning, while spreadCycle shall be used for highly dynamic motion. VCOOLTHRS determines the
transition velocity. Use a low transfer velocity to avoid a jerk at the switching point. A jerk occurs
when switching at higher velocities, because the back-EMF of the motor (which rises with the
velocity) causes a phase shift of up to 90° between motor voltage and motor current. So when
switching at higher velocities between voltage PWM and current PWM mode, this jerk will occur with
increased intensity. At low velocities (e.g. 1 to a few 10 RPM), it can be completely neglected for most
motors. Therefore, the VCOOLTHRS should be set to a low velocity, in order to eliminate any jerk in
case an automatic switching between two chopper modes is desired. Set VCOOLTHRS and VHIGH to
high values (above VMAX) if you want to work with stealthChop only.
When enabling the stealthChop mode the first time using automatic current regulation, the motor
must be at stand still in order to allow a proper current regulation. When the drive switches to a
different chopper mode at a higher velocity, stealthChop logic stores the last current regulation
setting until the motor returns to a lower velocity again. This way, the regulation has a known
starting point when returning to a lower velocity, where stealthChop becomes re-enabled. Therefore,
neither the velocity threshold nor the supply voltage must be considerably changed during the phase
while the chopper is switched to a different mode, because otherwise the motor might lose steps or
the instantaneous current might be too high or too low.
A motor stall or a sudden change in the motor velocity may lead to the driver detecting a short
circuit or to a state of automatic current regulation, from which it cannot recover. Clear the error flags
and restart the motor from zero velocity to recover from this situation.
Hint
Start the motor from standstill when switching on stealthChop the first time and keep it stopped for
at least 128 chopper periods to allow stealthChop to do initial standstill current control.
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 55
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8.5 Flags in stealthChop
8.5.1 Open Load Flags
In stealthChop mode, status information is different from the cycle-by-cycle regulated chopper modes.
OLA and OLB show if the current regulation sees that the nominal current can be reached on both
coils.
- A flickering OLA or OLB can result from tiny asymmetries in the sense resistors or in the
motor coils.
- An interrupted motor coil leads to a continuously active open load flag for the coil.
- Both flags are active, if the current regulation did not succeed in scaling up to the full target
current within the last few fullsteps (because no motor is attached or a high acceleration
required a quick action of the current regulator).
With automatic scaling and PWM_GRAD > 1, the current regulation tries to increase the current
quickly to reach the target current in the interrupted motor coil. At the same time but a bit
slower the current regulation tries to decrease the motor current due to the other motor coil
seeing too high current.
Therefore it is recommended to do an on-demand open load test using the spreadCycle or classic
chopper prior to operation in stealthChop, and not to switch on stealthChop in case of open load
failure. Alternatively, PWM_SCALE can be checked for plausible values.
8.5.2 PWM_SCALE Informs about the Motor State
Information about the motor state is available with automatic scaling by reading out PWM_SCALE. As
this parameter reflects the actual voltage required to drive the target current into the motor, it
depends on several factors: motor load, coil resistance, supply voltage, and current setting. Therefore,
an evaluation of the PWM_SCALE value allows seeing the motor load (similar to stallGuard2) and
finding out if the target current can be reached. It even gives an idea on the motor temperature
(evaluate at a well-known state of operation).
waM m waM m waM m m m m
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 56
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8.6 Freewheeling and Passive Motor Braking
stealthChop provides different options for motor standstill. These options can be enabled by setting
the standstill current IHOLD to zero and choosing the desired option using the FREEWHEEL setting.
The desired option becomes enabled after a time period specified by TZEROWAIT and IHOLD_DELAY.
The PWM_SCALE regulation becomes frozen once the motor target current is at zero current in order
to ensure a quick startup.
Parameter
Description
Setting
Comment
VCOOLTHRS
VHIGH
Whichever is lower, specifies the upper velocity
for operation in stealthChop voltage PWM mode.
0 …
2^23-1
pwm_
autoscale
Enable automatic current scaling using current
measurement or use fixed scaling mode.
0
Fixed mode
1
Automatic scaling with
current regulator
PWM_FREQ
PWM frequency selection. stealthChop uses a fixed
PWM frequency by dividing the system clock
frequency using a programmable divider. Use the
lowest setting giving good results.
0
fPWM=1/1024 fCLK
1
fPWM=1/683 fCLK
2
fPWM=1/512 fCLK
3
fPWM=1/410 fCLK
PWM_GRAD
Global enable and
regulation loop gradient when pwm_autoscale=1.
0
Do not use stealthChop
1 15
stealthChop enabled
PWM_AMPL
User defined PWM amplitude for fixed scaling or
amplitude limit for re-entry into stealthChop mode
when pwm_autoscale=1.
0 … 255
FREEWHEEL
Stand still option when motor current setting is
zero (I_HOLD=0). Only available with stealthChop
enabled. The freewheeling option makes the
motor easy movable, while both coil short options
realize a passive brake. Mode 2 will brake more
intensely than mode 3, because low side drivers
(LS) have lower resistance than high side drivers.
0
Normal operation
1
Freewheeling
2
Coil shorted using LS
drivers
3
Coil shorted using HS
drivers
PWM_SCALE
Read back of the actual stealthChop voltage PWM
scaling as determined by the current regulation.
Can be used to detect motor load and stall when
autoscale=1.
0 … 255
(read
only)
The scaling value
becomes frozen when
operating in a different
chopper mode
TOFF
General enable for the motor driver, the actual
value does not influence stealthChop
0
Driver off
1 … 15
Driver enabled
TBL
Selects the comparator blank time. This time needs to
safely cover the switching event and the duration of the
ringing on the sense resistor. For most applications, a
setting of 1 or 2 is good. For highly capacitive loads,
e.g. when filter networks are used, a setting of 2 or 3
will be required. A lower setting allows stealthChop to
regulate down to lower coil current values.
0
16 tCLK
1
24 tCLK
2
36 tCLK
3
54 tCLK
IRUN
IHOLD
Run and hold current setting for stealth Chop
operation only used with pwm_autoscale=1
See chapter on current
setting for details
TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 57
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9 spreadCycle and Classic Chopper
While stealthChop is a voltage mode PWM controlled chopper, spreadCycle is a cycle-by-cycle current
control. Therefore, it can react extremely fast to changes in motor velocity or motor load. The currents
through both motor coils are controlled using choppers. The choppers work independently of each
other. In Figure 9.1 the different chopper phases are shown.
RSENSE
ICOIL
On Phase:
current flows in
direction of target
current
RSENSE
ICOIL
Fast Decay Phase:
current flows in
opposite direction
of target current
RSENSE
ICOIL
Slow Decay Phase:
current re-circulation
+VM+VM+VM
Figure 9.1 Chopper phases
Although the current could be regulated using only on phases and fast decay phases, insertion of the
slow decay phase is important to reduce electrical losses and current ripple in the motor. The
duration of the slow decay phase is specified in a control parameter and sets an upper limit on the
chopper frequency. The current comparator can measure coil current during phases when the current
flows through the sense resistor, but not during the slow decay phase, so the slow decay phase is
terminated by a timer. The on phase is terminated by the comparator when the current through the
coil reaches the target current. The fast decay phase may be terminated by either the comparator or
another timer.
When the coil current is switched, spikes at the sense resistors occur due to charging and discharging
parasitic capacitances. During this time, typically one or two microseconds, the current cannot be
measured. Blanking is the time when the input to the comparator is masked to block these spikes.
There are two cycle-by-cycle chopper modes available: a new high-performance chopper algorithm
called spreadCycle and a proven constant off-time chopper mode. The constant off-time mode cycles
through three phases: on, fast decay, and slow decay. The spreadCycle mode cycles through four
phases: on, slow decay, fast decay, and a second slow decay.
The chopper frequency is an important parameter for a chopped motor driver. A too low frequency
might generate audible noise. A higher frequency reduces current ripple in the motor, but with a too
high frequency magnetic losses may rise. Also power dissipation in the driver rises with increasing
frequency due to the increased influence of switching slopes causing dynamic dissipation. Therefore, a
compromise needs to be found. Most motors are optimally working in a frequency range of 16 kHz to
30 kHz. The chopper frequency is influenced by a number of parameter settings as well as by the
motor inductivity and supply voltage.
Hint
A chopper frequency in the range of 16 kHz to 30 kHz gives a good result for most motors when
using spreadCycle. A higher frequency leads to increased switching losses. It is advised to check the
resulting frequency and to work below 50 kHz.
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Three parameters are used for controlling both chopper modes:
9.1 spreadCycle Chopper
The spreadCycle (patented) chopper algorithm is a precise and simple to use chopper mode which
automatically determines the optimum length for the fast-decay phase. The spreadCycle will provide
superior microstepping quality even with default settings. Several parameters are available to
optimize the chopper to the application.
Each chopper cycle is comprised of an on phase, a slow decay phase, a fast decay phase and a
second slow decay phase (see Figure 9.3). The two slow decay phases and the two blank times per
chopper cycle put an upper limit to the chopper frequency. The slow decay phases typically make up
for about 30%-70% of the chopper cycle in standstill and are important for low motor and driver
power dissipation.
Calculation of a starting value for the slow decay time TOFF:
Assumptions:
Target Chopper frequency: 25kHz
Two slow decay cycles make up for 50% of overall chopper cycle time




For the TOFF setting this means:    
With 12 MHz clock this gives a setting of TOFF=3.4, i.e. 3 or 4.
With 16 MHz clock this gives a setting of TOFF=4.6, i.e. 4 or 5.
The hysteresis start setting forces the driver to introduce a minimum amount of current ripple into
the motor coils. The current ripple must be higher than the current ripple which is caused by resistive
losses in the motor in order to give best microstepping results. This will allow the chopper to
precisely regulate the current both for rising and for falling target current. The time required to
introduce the current ripple into the motor coil also reduces the chopper frequency. Therefore, a
higher hysteresis setting will lead to a lower chopper frequency. The motor inductance limits the
ability of the chopper to follow a changing motor current. Further the duration of the on phase and
the fast decay must be longer than the blanking time, because the current comparator is disabled
during blanking.
It is easiest to find the best setting by starting from a low hysteresis setting (e.g. HSTRT=0, HEND=0)
and increasing HSTRT, until the motor runs smoothly at low velocity settings. This can best be
Parameter
Description
Setting
Comment
TOFF
Sets the slow decay time (off time). This setting also
limits the maximum chopper frequency.
For operation with stealthChop, this parameter is not
used, but it is required to enable the motor. In case of
operation with stealthChop only, any setting is OK.
Setting this parameter to zero completely disables all
driver transistors and the motor can free-wheel.
0
chopper off
1…15
off time setting NCLK= 12 +
32*TOFF
(1 will work with minimum
blank time of 24 clocks)
TBL
Selects the comparator blank time. This time needs to
safely cover the switching event and the duration of the
ringing on the sense resistor. For most applications, a
setting of 1 or 2 is good. For highly capacitive loads,
e.g. when filter networks are used, a setting of 2 or 3
will be required.
0
16 tCLK
1
24 tCLK
2
36 tCLK
3
54 tCLK
chm
Selection of the chopper mode
0
spreadCycle
1
classic const. off time
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TMC5072 DATASHEET (Rev. 1.21 / 2016-APR-22) 59
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checked when measuring the motor current either with a current probe or by probing the sense
resistor voltages (see Figure 9.2). Checking the sine wave shape near zero transition will show a small
ledge between both half waves in case the hysteresis setting is too small. At medium velocities (i.e.
100 to 400 fullsteps per second), a too low hysteresis setting will lead to increased humming and
vibration of the motor.
Figure 9.2 No ledges in current wave with sufficient hysteresis (magenta: current A, yellow &
blue: sense resistor voltages A and B)
A too high hysteresis setting will lead to reduced chopper frequency and increased chopper noise but
will not yield any benefit for the wave shape.
Quick Start
For a quick start, see the Quick Configuration Guide in chapter 18.
For detail procedure see Application Note AN001 - Parameterization of spreadCycle
As experiments show, the setting is quite independent of the motor, because higher current motors
typically also have a lower coil resistance. Therefore choosing a low to medium default value for the
hysteresis (for example, effective hysteresis = 4) normally fits most applications. The setting can be
optimized by experimenting with the motor: A too low setting will result in reduced microstep
accuracy, while a too high setting will lead to more chopper noise and motor power dissipation.
When measuring the sense resistor voltage in motor standstill at a medium coil current with an
oscilloscope, a too low setting shows a fast decay phase not longer than the blanking time. When
the fast decay time becomes slightly longer than the blanking time, the setting is optimum. You can
reduce the off-time setting, if this is hard to reach.
The hysteresis principle could in some cases lead to the chopper frequency becoming too low, e.g.
when the coil resistance is high when compared to the supply voltage. This is avoided by splitting
the hysteresis setting into a start setting (HSTRT+HEND) and an end setting (HEND). An automatic
hysteresis decrementer (HDEC) interpolates between both settings, by decrementing the hysteresis
value stepwise each 16 system clocks. At the beginning of each chopper cycle, the hysteresis begins
with a value which is the sum of the start and the end values (HSTRT+HEND), and decrements during
the cycle, until either the chopper cycle ends or the hysteresis end value (HEND) is reached. This way,
the chopper frequency is stabilized at high amplitudes and low s