C-320 Series Datasheet by Swissbit

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Product data sheet
Industrial
CompactFlashTM Card
C-320 Series
up to UDMA4 / MDMA4 / PIO6
Standard & ZoneProtection
BU: Flash Products
Date: 18 January 2012
Revision: 1.20
File:
C-320_data_sheet_CF-HxBO_Rev120.doc
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C-320 Series Industrial UDMA CompactFlash™ Card,
2GByte up to 32GByte, 3.3/5V Supply
1 Features
Highly-integrated memory controller
o Fully compliant with CompactFlashTM specification 3.0,
compatible with specification 4.1
o Fully compatible with PCMCIA specification
o PC Card ATA Interface supported
o True IDE mode compatible
o Up to PIO mode 6 supported
o Up to MDMA4 supported
o Up to UDMA4 supported
o Hardware RS-code ECC (4 Bytes/528 Bytes correction)
o Fix drive (IDE mode) &
removable drive (PCMCIA mode) as default configuration
Small form factor
o CFC Type I: 36.4mm x 42.8mm x 3.3mm
Low-power CMOS technology
3.3V or 5.0V power supply
Power saving mode (with automatic wake-up)
S.M.A.R.T. support in *-SMA product type
Optional Security feature: Swissbit ZoneProtection on request in *-ZP1 product type (2GB up to 16GB)
Wear Leveling: equal wear leveling of static and dynamic data
The wear leveling assures that dynamic data as well as static data is balanced evenly across the
memory. With that the maximum write endurance of the device is guaranteed.
Data Retention: 10 year (JESD47)
Patented power-off reliability
o No data loss of older sectors
o Max. 32 sectors data loss (old data kept)
o All data written to the flash if card status is ready after write command
High reliability
o MTBF > 3,000,000 hours
o Data reliability: < 1 non-recoverable error per 1014 bits read
o Number of connector insertions/removals: >10,000
Hot swappable in PCMCIA modes
High performance
o Up to 66MB/s burst transfer rate in UDMA4
o Sustained Write performance: up to 35MB/s (UDMA4)
o Sustained Read Performance: up to 45MB/s (UDMA4)
Available densities
o up to 32GBytes
Operating System support
o Standard Software Drivers operation CompactFlash
2 Temperature ranges
o Commercial Temperature range 0 … +70°C
o Industrial Temperature range -40 … +85°C
Life Cycle Management
Controlled BOM
RoHS compatible
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2 Table of Contents
1 FEATURES ............................................................................................................................................................................... 2
2 TABLE OF CONTENTS ............................................................................................................................................................... 3
3 ORDER INFORMATION............................................................................................................................................................. 6
3.3 OFFERED OEM OPTIONS ................................................................................................................................................................. 6
4 PRODUCT SPECIFICATION ........................................................................................................................................................ 7
4.1 SYSTEM PERFORMANCE ................................................................................................................................................................... 7
4.2 ENVIRONMENTAL SPECIFICATIONS ...................................................................................................................................................... 8
4.3 PHYSICAL DIMENSIONS ................................................................................................................................................................... 9
4.4 RELIABILITY ................................................................................................................................................................................. 9
4.5 DRIVE GEOMETRY / CHS PARAMETER ............................................................................................................................................... 9
4.6 PHYSICAL DESCRIPTION ................................................................................................................................................................ 10
5 ELECTRICAL INTERFACE ......................................................................................................................................................... 11
5.1 ELECTRICAL DESCRIPTION ............................................................................................................................................................... 11
5.2 ELECTRICAL SPECIFICATION ............................................................................................................................................................. 16
5.3 ADDITIONAL REQUIREMENTS FOR COMPACTFLASH ADVANCED TIMING MODE ............................................................................................. 17
6 COMMAND INTERFACE .......................................................................................................................................................... 18
6.1 ATTRIBUTE MEMORY READ AND WRITE ............................................................................................................................................ 18
6.2 COMMON MEMORY READ AND WRITE ............................................................................................................................................. 19
6.3 I/O READ AND WRITE .................................................................................................................................................................. 21
6.4 TRUE IDE MODE ........................................................................................................................................................................ 22
6.5 ULTRA DMA MODE .................................................................................................................................................................... 24
7 CARD CONFIGURATION ......................................................................................................................................................... 43
7.1 CONFIGURATION OPTION REGISTER (200H IN ATTRIBUTE MEMORY) ....................................................................................................... 43
7.2 COMPACTFLASH MEMORY CARD CONFIGURATIONS .............................................................................................................................. 44
7.3 PIN REPLACEMENT REGISTER (204H IN ATTRIBUTE MEMORY) .............................................................................................................. 44
7.4 SOCKET AND COPY REGISTER (206H IN ATTRIBUTE MEMORY) .............................................................................................................. 45
7.5 ATTRIBUTE MEMORY FUNCTION ...................................................................................................................................................... 45
7.6 I/O TRANSFER FUNCTION .............................................................................................................................................................. 46
7.7 COMMON MEMORY TRANSFER FUNCTION .......................................................................................................................................... 46
7.8 TRUE IDE MODE I/O FUNCTION ..................................................................................................................................................... 46
7.9 HOST CONFIGURATION REQUIREMENTS FOR MASTER/SLAVE OR NEW TIMING MODES ................................................................................ 47
8 SOFTWARE INTERFACE .......................................................................................................................................................... 48
8.1 CF-ATA DRIVE REGISTER SET DEFINITION AND PROTOCOL ................................................................................................................... 48
8.2 MEMORY MAPPED ADDRESSING .................................................................................................................................................... 48
8.3 CONTIGUOUS I/O MAPPED ADDRESSING .......................................................................................................................................... 49
8.4 I/O PRIMARY AND SECONDARY ADDRESS CONFIGURATIONS ................................................................................................................. 50
8.5 TRUE IDE MODE ADDRESSING ...................................................................................................................................................... 50
9 CF-ATA REGISTERS ............................................................................................................................................................... 51
9.1 DATA REGISTER ........................................................................................................................................................................... 51
9.2 ERROR REGISTER ........................................................................................................................................................................ 51
9.3 FEATURE REGISTER ...................................................................................................................................................................... 52
9.4 SECTOR COUNT REGISTER .............................................................................................................................................................. 52
9.5 SECTOR NUMBER (LBA 7-0) REGISTER .......................................................................................................................................... 52
9.6 CYLINDER LOW (LBA 15-8) REGISTER ........................................................................................................................................... 52
9.7 CYLINDER HIGH (LBA 23-16) REGISTER ......................................................................................................................................... 52
9.8 DRIVE/HEAD (LBA 27-24) REGISTER ............................................................................................................................................ 52
9.9 STATUS & ALTERNATE STATUS REGISTERS ........................................................................................................................................ 53
9.10 DEVICE CONTROL REGISTER ......................................................................................................................................................... 54
9.11 CARD (DRIVE) ADDRESS REGISTER ................................................................................................................................................. 54
10 CF-ATA COMMAND DESCRIPTION ......................................................................................................................................... 56
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10.1 CHECK POWER MODE (98H OR E5H) ............................................................................................................................................ 57
10.2 ERASE SECTOR(S) (C0H) ............................................................................................................................................................. 57
10.3 EXECUTE DRIVE DIAGNOSTIC (90H) .............................................................................................................................................. 57
10.4 FLUSH CACHE (E7H) .................................................................................................................................................................. 58
10.5 FORMAT TRACK (50H) ................................................................................................................................................................ 58
10.6 IDENTIFY DEVICE (ECH) .............................................................................................................................................................. 58
10.7 IDLE (97H OR E3H) ................................................................................................................................................................... 66
10.8 IDLE IMMEDIATE (95H OR E1H) ................................................................................................................................................... 66
10.9 INITIALIZE DRIVE PARAMETERS (91H) ............................................................................................................................................ 66
10.10 NOP (00H) ........................................................................................................................................................................... 67
10.11 READ BUFFER (E4H) ................................................................................................................................................................. 67
10.12 READ DMA (C8H) ................................................................................................................................................................... 67
10.13 READ MULTIPLE (C4H).............................................................................................................................................................. 68
10.14 READ NATIVE MAX ADDRESS (F8H) ............................................................................................................................................. 68
10.15 READ SECTOR(S) (20H OR 21H) .................................................................................................................................................. 69
10.16 READ VERIFY SECTOR(S) (40H OR 41H) ....................................................................................................................................... 69
10.17 RECALIBRATE (1XH) .................................................................................................................................................................. 69
10.18 REQUEST SENSE (03H) ............................................................................................................................................................. 70
10.19 SEEK (7XH) ............................................................................................................................................................................ 70
10.20 SECURITY DISABLE PASSWORD (F6H) .......................................................................................................................................... 71
10.21 SECURITY ERASE PREPARE (F3H) ................................................................................................................................................. 71
10.22 SECURITY ERASE UNIT (F4H) ..................................................................................................................................................... 71
10.23 SECURITY FREEZE LOCK (F5H) .................................................................................................................................................... 72
10.24 SECURITY SET PASSWORD (F1H) .................................................................................................................................................. 72
10.25 SECURITY UNLOCK (F2H) ........................................................................................................................................................... 73
10.26 SET FEATURES (EFH) ................................................................................................................................................................ 73
10.27 SET MAX ADDRESS (F9H) ........................................................................................................................................................... 75
10.28 SET MULTIPLE MODE (C6H) ...................................................................................................................................................... 76
10.29 SET SLEEP MODE (99H OR E6H) ............................................................................................................................................... 77
10.30 S.M.A.R.T. (B0H)................................................................................................................................................................ 77
10.31 STANDBY (96H OR E2) ............................................................................................................................................................. 77
10.32 STANDBY IMMEDIATE (94H OR E0H) .......................................................................................................................................... 78
10.33 TRANSLATE SECTOR (87H) ......................................................................................................................................................... 78
10.34 WEAR LEVEL (F5H) ................................................................................................................................................................. 78
10.35 WRITE BUFFER (E8H) .............................................................................................................................................................. 78
10.36 WRITE DMA (CAH) ................................................................................................................................................................. 79
10.37 WRITE MULTIPLE COMMAND (C5H) ............................................................................................................................................. 79
10.38 WRITE MULTIPLE WITHOUT ERASE (CDH) ..................................................................................................................................... 80
10.39 WRITE SECTOR(S) (30H OR 31H) ................................................................................................................................................ 80
10.40 WRITE SECTOR(S) WITHOUT ERASE (38H) .................................................................................................................................... 81
10.41 WRITE VERIFY (3CH) ................................................................................................................................................................ 81
11 S.M.A.R.T FUNCTIONALITY ................................................................................................................................................... 82
11.1 S.M.A.R.T. ENABLE / DISABLE OPERATIONS ................................................................................................................................... 82
11.2 S.M.A.R.T. ENABLE / DISABLE ATTRIBUTE AUTOSAVE ...................................................................................................................... 82
11.3 S.M.A.R.T. READ DATA ............................................................................................................................................................. 82
11.4 S.M.A.R.T. READ ATTRIBUTE THRESHOLDS .................................................................................................................................... 87
11.5 S.M.A.R.T. RETURN STATUS ....................................................................................................................................................... 88
12 SWISSBIT ZONEPROTECTION FEATURE FUNCTIONALITY ......................................................................................................... 89
13 CIS INFORMATION (TYPICAL) ................................................................................................................................................. 90
14 PACKAGE MECHANICAL ......................................................................................................................................................... 94
15 DECLARATION OF CONFORMITY............................................................................................................................................. 95
16 ROHS AND WEEE UPDATE FROM SWISSBIT .......................................................................................................................... 96
17 PART NUMBER DECODER ...................................................................................................................................................... 98
17.1 MANUFACTURER ......................................................................................................................................................................... 98
17.2 MEMORY TYPE ........................................................................................................................................................................... 98
17.3 PRODUCT TYPE ........................................................................................................................................................................... 98
17.4 DENSITY ................................................................................................................................................................................... 98
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17.5 PLATFORM ................................................................................................................................................................................ 98
17.6 PRODUCT GENERATION ................................................................................................................................................................ 98
17.7 MEMORY ORGANIZATION .............................................................................................................................................................. 98
17.8 CONTROLLER TYPE ...................................................................................................................................................................... 98
17.9 NUMBER OF FLASH CHIP ............................................................................................................................................................. 98
17.10 FLASH CODE ............................................................................................................................................................................ 98
17.11 TEMP. OPTION .......................................................................................................................................................................... 99
17.12 DIE CLASSIFICATION .................................................................................................................................................................. 99
17.13 PIN MODE .............................................................................................................................................................................. 99
17.14 COMPACT FLASH XYZ ................................................................................................................................................................. 99
17.15 OPTION ................................................................................................................................................................................... 99
18 SWISSBIT CF LABEL SPECIFICATION .................................................................................................................................... 100
18.1 FRONT SIDE LABEL .................................................................................................................................................................... 100
18.2 BACK SIDE LABEL ..................................................................................................................................................................... 100
19 REVISION HISTORY .............................................................................................................................................................. 101
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3 Order Information
3.1 Standard part numbers
IDE-FIX & PCMCIA-Removable / PIO, DMA & UDMA support
Density
Part Number
2GB
SFCF2048HxBO2TO-t-M0-5y3-SMA
4GB
SFCF4096HxBO2TO-t-D1-5y3-SMA
8GB
SFCF8192HxBO2TO-t-Q1-5y3-SMA
16GB
SFCF16GBHxBO4TO-t-Q1-5y3-SMA
32GB
SFCF32GBHxBO4TO-t-NC-5y3-SMA
Table 1: product list for standard product variations
x= depends on product generation;
y=depends on latest FW revision
t=C: commercial temperature; I: industrial temperature
3.2 ZoneProtection part numbers
IDE-FIX & PCMCIA-Removable / PIO, DMA & UDMA support / ZoneProtection feature implemented
Density
Part Number
2GB
SFCF2048HxBO2TO-t-M0-5y3-ZP1
4GB
SFCF4096HxBO2TO-t-D1-5y3-ZP1
8GB
SFCF8192HxBO2TO-t-Q1-5y3-ZP1
16GB
SFCF16GBHxBO4TO-t-Q1-5y3-ZP1
32GB
Not available
Table 2: product list for ZoneProtection variations
x= depends on product generation;
y=depends on latest FW revision
t=C: commercial temperature; I: industrial temperature
3.3 Offered OEM options
Disabling MDMA and/or UDMA modes
Customer specified card size and card geometry (C/H/S cylinder/head/sector)
Customer specified CIS and drive ID strings
Preload service (also images with any file system)
Customized front label
ROM mode (write protected with preloaded software)
Special Firmware solutions for additional customer requirements
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4 Product Specification
The CompactFlash is a small form factor non-volatile memory card which provides high capacity data storage. Its
aim is to capture, retain and transport data, audio and images, facilitating the transfer of all types of digital
information between a large variety of digital systems.
The Card operates in three basic modes:
PC card ATA I/O mode
PC card ATA memory mode
True IDE mode
The CompactFlash also supports Advanced Timing modes. Advanced Timing modes are ATA I/O modes that are
100ns or faster, ATA Memory modes that are 100ns or 80ns.
Standard cards are shipped as max. PIO6 and MDMA4 (80ns) and UDMA4 (30ns).
If the cards should be used in extended speed modes, they should be qualified on the target system and the
system should fulfill the requirements listed below.
It conforms to the PCMCIA Card Specification 2.1 when operating in the ATA I/O mode, and in the ATA Memory mode
(Personal Computer Memory Card International Association standard, JEIDA in Japan), and to the ATA specification
when operating in True IDE Mode. CompactFlash Cards can be used with passive adapters in a PC-Card Type II or
Type III socket.
The Card has an internal intelligent controller which manages interface protocols, data storage and retrieval as
well as hardware RS-code Error Correction Code (ECC), defect handling, diagnostics and clock control.
The wear leveling mechanism assures an equal usage of the Flash memory cells to extend the life time.
Once the Card has been configured by the host, it behaves as a standard ATA (IDE) disk drive. The hardware RS-
code ECC allows to detect and correct 4 symbols per 528 Bytes.
The Card has a voltage detector and a powerful power-loss management feature to prevent data corruption after
power-down.
The specification has been realized and approved by the CompactFlash Association (CFA).
This non-proprietary specification enables users to develop CF products that function correctly and are compatible
with future CF design. The system highlights are shown in Table 3 Table 9.
Related Documentation
PCMCIA PC Card Standard, 1995
PCMCIA PC Card ATA Specification, 1995
AT Attachment Interface Document, American National Standards Institute, X3.221-1994
CF+ and CompactFlash Specification Revision 3.0
4.1 System Performance
Table 3: System Performance
System Performance
Typ.
Max.
Sleep to write
5
Sleep to read
5
Power up to Ready
<500
1000
Reset to Ready (PCMCIA/IDE Master )
200
500
Data transfer Rate (UDMA4 burst)
66
Sustained Read (measured)
2 channel 4k(1, 3)
2GB-32GB
37
45
Sustained Write (measured)
2 channel 4k(1, 3)
2GB-32GB
32
35
Sustained Read (measured)
2 channel 4k(2, 3)
2GB-32GB
27
30
Sustained Write (measured)
2 channel 4k(2, 3)
2GB-32GB
20
22
Command to DRQ
Read
100
2000
Write
30
1000
Access Time
Read
0.22
1. All values refer to Toshiba Flash chips with firmware revisions 1, 2, 4
2. All values refer to Toshiba Flash chips with firmware revision 3
3. CompactFlash Card in UDMA mode 4, cycle time 30ns in True-IDE mode with Sequential write/read test.
The number of flash is decoded in the part number, also the flash page size is depicted in this table.
Sustained Speed depends on flash type and number, file size, and burst speed.
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Requirements for using extended speed (PIO 5, 6/ MDMA 3, 4)
(CompactFlash Specification 3.0; section 4.3.7)
The CF Advanced Timing modes include PCMCIA I/O and Memory modes that are 100ns or faster and True
IDE PIO Modes 5,6 and Multiword DMA Modes 3,4.
When operating in CF Advanced timing modes, the host shall conform to the following requirements:
1. Only one CF device shall be attached to the CF Bus.
2. The host shall not present a load of more than 40pF to the device for all signals, including any cabling.
3. The maximum cable length is 0.05 m (2 in). The cable length is measured from the card connector to the
host controller. 0.46 m (18 in) cables are not supported.
4. The WAIT and IORDY signals shall be ignored by the host.
Devices supporting CF Advanced timing modes shall also support slower timing modes, to ensure operability with
systems that do not support CF Advanced timing modes.
Ultra DMA Electrical Requirements
(CompactFlash Specification 3.0; section 4.3.8)
Operation in Ultra DMA mode requires careful attention to cabling, printed circuit board (PCB) trace routing and
termination for reliable operation. These requirements are described in the following sections.
Host and Card signal capacitance limits for Ultra DMA operation
The host interface signal capacitance at the host connector shall be a maximum of 25pF for each signal as
measured at 1 MHz.
The card interface signal capacitance at the card connector shall be a maximum of 20pF for each signal as
measured at 1 MHz.
Series termination required for Ultra DMA operation
Series termination resistors are required at both the host and the card for operation in any of the Ultra DMA
modes. The CF specification describes typical values for series termination at the host and the device.
4.2 Environmental Specifications
4.2.1 Recommended Operating Conditions
Table 4: CF Card Recommended Operating Conditions
Parameter
Value
Commercial Operating Temperature
0°C to 70°C
Industrial Operating Temperature
-40°C to 85°C
Power Supply VCC Voltage (5V)
4.5V to 5.5V 5.0V ±10%
Power Supply VCC Voltage (3.3V)
2.97V to 3.63V 3.3V ±10%
Table 5: Current consumption (1)
Current Consumption (type)
3.3V
5V
Unit
Read (MDMA2/UDMA4/max)
60 / 90 / 140
100 / 140 / 180
mA
Write (MDMA2/UDMA4/max)
60 / 90 / 140
95 / 130 / 160
Sleep/Idle Mode (typ/max)
0.5 / 1.5
2.0 / 5.0
1. All values are typical at 25° C and nominal supply voltage and refer to 8Gbyte CompactFlash Card.
Max values are for 32GB cards in UDMA4 mode in IDE mode. Cards with smaller capacity have smaller current.
The card goes to Sleep/idle mode 20ms (default) after last host command.
The sleep current at 5V depends on the signal level at the CF-Bus
4.2.2 Recommended Storage Conditions
Table 6: CF Card Recommended Storage Conditions
Parameter
Value
Storage Temperature
-50°C to 100°C
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4.2.3 Shock, Vibration, and Humidity
Table 7: Shock, Vibration, and Humidity
Parameter
Value
Humidity (non-condensing)
85% RH 85°C, 1000 hrs (JEDEC JESD22, method A101-B)
Vibration
20 G peak, 20-2000Hz, 4 per direction (JEDEC JESD22, method B103)
5.35G RMS, 15 min per plane (IEC 68-2-6)
Shock
1.5k G peak, 0.5ms 5 times (JEDEC JESD22, method B110)
30 G, 11ms 1 time (IEC 68-2-27)
4.3 Physical Dimensions
Table 8: Physical Dimensions
Parameter
Value
Unit
Width
42.8
mm
Height
36.4
Thickness
3.3
Weight (typ.)
10
g
4.4 Reliability
Table 9: System Reliability and Maintenance
Parameter
Value
MTBF (at 25°C)
> 3,000,000 hours (1)
Insertions/Removals
> 10,000
Data Reliability
< 1 Non-Recoverable Error per 1014 bits Read (1)
Data Retention
10 years (JESD47)
(1) Dependent on final system qualification data.
4.5 Drive Geometry / CHS Parameter
Table 10: CF capacity specification
Capacity
Cylinders
Heads
Sectors / track
Sectors
Total addressable capacity (Byte)
2GB
3,970
16
63
4,001,760
2,048,901,120
4GB
7,964
16
63
8,027,712
4,110,188,544
8GB
15,880
16
63
16,007,040
8,195,604,480
16GB
16,383 (1)
16
63
31,717,728
16,239,476,736
32GB
16,383 (1)
16
63
64,028,160
32,782,417,920
(1) The CHS addressing is limited to about 8GB. Larger drives should be used in LBA mode.
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4.6 Physical description
The CompactFlash Memory Card contains a single chip controller and Flash memory module(s). The controller
interfaces with a host system allowing data to be written to and read from the Flash memory module(s). Figure 1
shows the Block Diagram of the CompactFlash Memory Card.
The Card is offered in a Type I package with a 50-pin connector consisting of two rows of 25 female contacts on 50
mil (1.27mm) centers. Figure 21 shows Type I Card Dimensions.
Figure 1: CompactFlash Memory Card Block Diagram
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5 Electrical interface
5.1 Electrical description
The CompactFlash Memory Card operates in three basic modes:
PC Card ATA using I/O Mode
PC Card ATA using Memory Mode
True IDE Mode with MWDMA and UDMA, which is compatible with most disk drives
The signal/pin assignments are listed in Table 11 Low active signals have a ‘-’ prefix. Pin types are Input, Output or
Input/Output.
The configuration of the Card is controlled using the standard PCMCIA configuration registers starting at address
200h in the Attribute Memory space of the memory card. Table 12 describes the I/O signals. Inputs are signals
sourced from the host while Outputs are signals sourced from the Card. The signals are described for each of the
three operating modes.
All outputs from the Card are totem pole except the data bus signals that are bi-directional tri-state. Refer to the
section titled “Electrical Specifications” for definitions of Input and Output type.
Table 11: Pin Assignment and Pin Type
Pin Num
PC Card Memory Mode
PC Card I/O Mode
True IDE Mode(4)
Signal
Name
Pin
Type
In, Out
Type
Signal
Name
Pin
Type
In, Out
Type
Signal
Name
Pin
Type
In, Out
Type
1
GND
Ground
GND
Ground
GND
Ground
2
D03
I/O
I1Z,OZ3
D03
I/O
I1Z,OZ3
D03
I/O
I1Z,OZ3
3
D04
I/O
I1Z,OZ3
D04
I/O
I1Z,OZ3
D04
I/O
I1Z,OZ3
4
D05
I/O
I1Z,OZ3
D05
I/O
I1Z,OZ3
D05
I/O
I1Z,OZ3
5
D06
I/O
I1Z,OZ3
D06
I/O
I1Z,OZ3
D06
I/O
I1Z,OZ3
6
D07
I/O
I1Z,OZ3
D07
I/O
I1Z,OZ3
D07
I/O
I1Z,OZ3
7
-CE1
I
I3U
-CE1
I
I3U
-CS0
I
I3Z
8
A10
I
I1Z
A10
I
I1Z
A10(2)
I
I1Z
9(1)
-OE
I
I3U
-OE
I
I3U
-ATASEL
I
I3U
10
A09
I
I1Z
A09
I
I1Z
A09(2)
I
I1Z
11
A08
I
I1Z
A08
I
I1Z
A08(2)
I
I1Z
12
A07
I
I1Z
A07
I
I1Z
A07(2)
I
I1Z
13
Vcc
Power
Vcc
Power
Vcc
Power
14
A06
I
I1Z
A06
I
I1Z
A06(2)
I
I1Z
15
A05
I
I1Z
A05
I
I1Z
A05(2)
I
I1Z
16
A04
I
I1Z
A04
I
I1Z
A04(2)
I
I1Z
17
A03
I
I1Z
A03
I
I1Z
A03(2)
I
I1Z
18
A02
I
I1Z
A02
I
I1Z
A02
I
I1Z
19
A01
I
I1Z
A01
I
I1Z
A01
I
I1Z
20
A00
I
I1Z
A00
I
I1Z
A00
I
I1Z
21
D00
I/O
I1Z,OZ3
D00
I/O
I1Z,OZ3
D00
I/O
I1Z,OZ3
22
D01
I/O
I1Z,OZ3
D01
I/O
I1Z,OZ3
D01
I/O
I1Z,OZ3
23
D02
I/O
I1Z,OZ3
D02
I/O
I1Z,OZ3
D02
I/O
I1Z,OZ3
24
WP
O
OT3
-IOIS16
O
OT3
-IOIS16
O
ON3
25
-CD2
O
Ground
-CD2
O
Ground
-CD2
O
Ground
26
-CD1
O
Ground
-CD1
O
Ground
-CD1
O
Ground
27
D11(1)
I/O
I1Z,OZ3
D11(1)
I/O
I1Z,OZ3
D11(1)
I/O
I1Z,OZ3
28
D12(1)
I/O
I1Z,OZ3
D12(1)
I/O
I1Z,OZ3
D12(1)
I/O
I1Z,OZ3
29
D13(1)
I/O
I1Z,OZ3
D13(1)
I/O
I1Z,OZ3
D13(1)
I/O
I1Z,OZ3
30
D14(1)
I/O
I1Z,OZ3
D14(1)
I/O
I1Z,OZ3
D14(1)
I/O
I1Z,OZ3
swissbit® Signal Name Dil. Pin Description
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Pin Num
PC Card Memory Mode
PC Card I/O Mode
True IDE Mode(4)
Signal
Name
Pin
Type
In, Out
Type
Signal
Name
Pin
Type
In, Out
Type
Signal
Name
Pin
Type
In, Out
Type
31
D15(1)
I/O
I1Z,OZ3
D15(1)
I/O
I1Z,OZ3
D15(1)
I/O
I1Z,OZ3
32
-CE2(1)
I
I3U
-CE2(1)
I
I3U
-CS1(1)
I
I3Z
33
-VS1
O
Ground
-VS1
O
Ground
-VS1
O
Ground
34
-IORD
I
I3U
-IORD
I
I3U
-IORD(7)
I
I3Z
HSTROBE(8)
-HDMARDY(9)
35
-IOWR
I
I3U
-IOWR
I
I3U
-IOWR(7)
I
I3Z
STOP(8)(9)
36
-WE
I
I3U
-WE
I
I3U
-WE(3)
I
I3U
37
READY
O
OT1
-IREQ
O
OT1
INTRQ
O
OZ1
38
Vcc
Power
Vcc
Power
Vcc
Power
39
-CSEL(5)
I
I2Z
-CSEL(5)
I
I2Z
-CSEL
I
I2U
40
-VS2
O
OPEN
-VS2
O
OPEN
-VS2
O
OPEN
41
RESET
I
I2Z
RESET
I
I2Z
-RESET
I
I2Z
42
-WAIT
O
OT1
-WAIT
O
OT1
IORDY(7)
O
ON1
-DDMARDY(8)
DSTROBE(9)
43
-INPACK
O
OT1
-INPACK
O
OT1
DMARQ
O
OZ1
44
-REG
I
I3U
-REG
I
I3U
-DMACK(6)
I
I3U
45
BVD2
I/O
I1U,OT1
-SPKR
I/O
I1U,OT1
-DASP
I/O
I1U,ON1
46
BVD1
I/O
I1U,OT1
-STSCHG
I/O
I1U,OT1
-PDIAG
I/O
I1U,ON1
47
D08(1)
I/O
I1Z,OZ3
D08(1)
I/O
I1Z,OZ3
D08(1)
I/O
I1Z,OZ3
48
D09(1)
I/O
I1Z,OZ3
D09(1)
I/O
I1Z,OZ3
D09(1)
I/O
I1Z,OZ3
49
D10(1)
I/O
I1Z,OZ3
D10(1)
I/O
I1Z,OZ3
D10(1)
I/O
I1Z,OZ3
50
GND
Ground
GND
Ground
GND
Ground
1. These signals are required only for 16 bit accesses and not required when installed in 8 bit systems.
Devices should allow for 3-state signals not to consume current.
2. The signal should be grounded by the host.
3. The signal should be tied to VCC by the host.
4. The mode is required for CompactFlash Storage Cards.
5. The CSEL signal is ignored by the card in PC Card modes. However, because it is not pulled up on the card
in these modes, it should not be left floating by the host in PC Card modes. In these modes, the pin
should be connected by the host to PC Card A25 or grounded by the host.
6. If DMA operations are not used, the signal must be held high or tied to VCC by the host, also for read
registers.
7. Signal usage in True IDE Mode except when Ultra DMA mode protocol is active.
8. Signal usage in True IDE Mode when Ultra DMA mode protocol DMA Write is active.
9. Signal usage in True IDE Mode when Ultra DMA mode protocol DMA Read is active. The signal should be
grounded by the host.
Table 12: Signal Description
Signal Name
Dir.
Pin
Description
A10 to A0
(PC Card Memory Mode)
I
8,10,11,12,
14,15,16,17,
18,19,20
These address lines along with the REG signal are used to
select the following: The I/O port address registers within the
CompactFlash Storage Card, the memory mapped port address
registers within the CompactFlash Storage Card, a byte in the
cards information structure and its configuration control and
status registers.
A10 to A0
(PC Card I/O Mode)
This signal is the same as the PC Card Memory Mode signal.
A2 to A0
(True IDE Mode)
In True IDE Mode, only A[2:0] are used to select the one of eight
registers in the Task File, the remaining address lines should be
grounded by the host.
BVD1
(PC Card Memory Mode)
I/O
46
This signal is asserted high, as BVD1 is not supported.
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Signal Name
Dir.
Pin
Description
STSCHG
(PC Card I/O Mode)
This signal is asserted low to alert the host to changes in the
READY and Write Protect states, while the I/O interface is
configured. Its use is controlled by the Card Config and Status
Register.
PDIAG
(True IDE Mode)
In the True IDE Mode, this input / output is the Pass Diagnostic
signal in the Master / Slave handshake protocol.
BVD2
(PC Card Memory Mode)
I/O
45
This signal is asserted high, as BVD2 is not supported.
SPKR
(PC Card I/O Mode)
This line is the Binary Audio output from the card. If the Card
does not support the Binary Audio function, this line should be
held negated.
DASP
(True IDE Mode)
In the True IDE Mode, this input/output is the Disk Active/Slave
Present signal in the Master/Slave handshake protocol.
D15-D00 (PC Card Memory Mode)
I/O
31, 30, 29,
28, 27, 49,
48, 47, 6,
5, 4, 3, 2,
23, 22, 21
These lines carry the Data, Commands and Status information
between the host and the controller. D00 is the LSB of the Even
Byte of the Word. D08 is the LSB of the Odd Byte of the Word.
D15-D00 (PC Card I/O Mode)
This signal is the same as the PC Card Memory Mode signal.
D15-D00 (True IDE Mode)
In True IDE Mode, all Task File operations occur in byte mode
on the low order bus D[7:0] while all data transfers are 16 bit
using D[15:0].
GND
(PC Card Memory Mode)
1, 50
Ground.
GND
(PC Card I/O Mode)
Same for all modes.
GND
(True IDE Mode)
Same for all modes.
INPACK
(PC Card Memory Mode)
O
43
This signal is not used in this mode.
INPACK
(PC Card I/O Mode)
The Input Acknowledge signal is asserted by the CompactFlash
Storage Card when the card is selected and
responding to an I/O read cycle at the address that is on the
address bus. This signal is used by the host to control the
enable
of any input data buffers between the CompactFlash Storage
Card and the CPU.
DMARQ
(True IDE Mode)
This signal is a DMA Request that is used for DMA data transfers
between host and device. It shall be asserted by the device
when it is ready to transfer data to or from the host. For
Multiword DMA transfers, the direction of data transfer is
controlled by IORD and IOWR. This signal is used in a
handshake manner with DMACK, i.e., the device shall wait
until
the host asserts DMACK before negating DMARQ, and
reasserting
DMARQ if there is more data to transfer.
DMARQ shall not be driven when the device is not selected.
While a DMA operation is in progress, -CS0 and CS1 shall be
held negated and the width of the transfers shall be 16 bits.
If there is no hardware support for DMA mode in the host, this
output signal is not used and should not be connected at the
host. In this case, the BIOS must report that DMA mode is not
supported by the host so that device drivers will not attempt
DMA mode.
A host that does not support DMA mode and implements both
PCMCIA and True-IDE modes of operation need not alter the
PCMCIA mode connections while in True-IDE mode as long as
this does not prevent proper operation in any mode.
IORD
(PC Card Memory Mode)
I
34
This signal is not used in this mode.
IORD
(PC Card I/O Mode)
This is an I/O Read strobe generated by the host. This signal
gates I/O data onto the bus from the CompactFlash Storage
Card when the card is configured to use the I/O
interface.
IORD
(True IDE Mode)
In True IDE Mode, while Ultra DMA mode is not active, this
signal has the same function as in PC Card I/O Mode.
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Signal Name
Dir.
Pin
Description
-HDMARDY
(True IDE Mode In Ultra
DMA Protocol DMA
Read)
In True IDE Mode when Ultra DMA mode DMA Read is active,
this signal is asserted by the host to indicate that the host is
read
to receive Ultra DMA data-in bursts. The host may negate
-HDMARDY to pause an Ultra DMA transfer.
HSTROBE
(True IDE Mode In Ultra
DMA Protocol DMA
Write)
In True IDE Mode when Ultra DMA mode DMA Write is active,
this signal is the data out strobe generated by the host. Both
the
rising and falling edge of HSTROBE cause data to be latched by
the device. The host may stop generating HSTROBE edges to
pause an Ultra DMA data-out burst.
CD1, CD2
(PC Card Memory Mode)
O
26, 25
These Card Detect pins are connected to ground on the
CompactFlash Storage Card. They are used by the
host to determine that the CompactFlash Storage Card or is fully
inserted into its socket.
CD1, CD2
(PC Card I/O Mode)
This signal is the same for all modes.
CD1, CD2
(True IDE Mode)
This signal is the same for all modes.
CE1, CE2
(PC Card Memory Mode)
I
7, 32
These input signals are used both to select the card and to
indicate to the card whether a byte or a word operation is being
performed. CE2 always accesses the odd byte of the word.
-CE1 accesses the even byte or the Odd byte of the word
depending on A0 and CE2. A multiplexing scheme based on
A0,
-CE1, -CE2 allows 8 bit hosts to access all data on D0-D7. See
Table 32, Table 40, Table 41Table 42, and Table 43.
CE1, CE2
(PC Card I/O Mode)
This signal is the same as the PC Card Memory Mode signal.
CS0, CS1
(True IDE Mode)
In the True IDE Mode, -CS0 is the chip select for the task file
registers while CS1 is used to select the Alternate Status
Register and the Device Control Register.
While DMACK is asserted, -CS0 and CS1 shall be held
negated and the width of the transfers shall be 16 bits.
CSEL
(PC Card Memory Mode)
I
39
This signal is not used for this mode, but should be connected
by
the host to PC Card A25 or grounded by the host.
CSEL
(PC Card I/O Mode)
This signal is not used for this mode, but should be connected
by
the host to PC Card A25 or grounded by the host.
CSEL
(True IDE Mode)
This internally pulled up signal is used to configure this device
as
a Master or a Slave when configured in the True IDE Mode.
When this pin is grounded, this device is configured as a
Master.
When the pin is open, this device is configured as a Slave.
IOWR
(PC Card Memory Mode)
I
35
This signal is not used in this mode.
IOWR
(PC Card I/O Mode)
The I/O Write strobe pulse is used to clock I/O data on the Card
Data bus into the CompactFlash Storage Card controller registers
when the CompactFlash Storage Card is configured to use the I/O
interface.
The clocking shall occur on the negative to positive edge of the
signal (trailing edge).
-IOWR
(True IDE Mode Except
Ultra DMA Protocol
Active)
In True IDE Mode, while Ultra DMA mode protocol is not active,
this signal has the same function as in PC Card I/O Mode.
When Ultra DMA mode protocol is supported, this signal must be
negated before entering Ultra DMA mode protocol.
STOP
(True IDE Mode Ultra
DMA Protocol Active)
In True IDE Mode, while Ultra DMA mode protocol is active, the
assertion of this signal causes the termination of the Ultra DMA
burst.
OE
(PC Card Memory Mode)
I
9
This is an Output Enable strobe generated by the host interface.
It is used to read data from the CompactFlash Storage
in Memory Mode and to read the CIS and
configuration registers.
OE
(PC Card I/O Mode)
In PC Card I/O Mode, this signal is used to read the CIS and
configuration registers.
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Signal Name
Dir.
Pin
Description
ATASEL
(True IDE Mode)
To enable True IDE Mode this input should be grounded by the
host.
READY
(PC Card Memory Mode)
O
37
In Memory Mode, this signal is set high when the CompactFlash
Storage Card is ready to accept a new data transfer operation
and is held low when the card is busy.
At power up and at Reset, the READY signal is held low (busy)
until the CompactFlash Storage Card has completed its power up
or reset function. No access of any type should be made to the
CompactFlash Storage Card during this time.
Note, however, that when a card is powered up and used with
RESET continuously disconnected or asserted, the Reset
function of the RESET pin is disabled. Consequently, the
continuous assertion of RESET from the application of power
shall not cause the READY signal to remain continuously in the
busy state.
IREQ
(PC Card I/O Mode)
I/O Operation After the CompactFlash Storage Card has been
configured for I/O operation, this signal is used as
-Interrupt Request. This line is strobed low to generate a pulse
mode interrupt or held low for a level mode interrupt.
INTRQ
(True IDE Mode)
In True IDE Mode signal is the active high Interrupt Request to
the host.
REG
(PC Card Memory Mode)
I
44
This signal is used during Memory Cycles to distinguish between
Common Memory and Register (Attribute) Memory accesses.
High for Common Memory, Low for Attribute Memory.
REG
(PC Card I/O Mode)
The signal shall also be active (low) during I/O Cycles when the
I/O address is on the Bus.
DMACK
(True IDE Mode)
This is a DMA Acknowledge signal that is asserted by the host in
response to DMARQ to initiate DMA transfers.
While DMA operations are not active, the card shall ignore the
-DMACK signal, including a floating condition.
If DMA operation is not supported by a True IDE Mode only host,
this signal should be driven high or connected to VCC by the
host.
A host that does not support DMA mode and implements both
PCMCIA and True-IDE modes of operation need not alter the
PCMCIA mode connections while in True-IDE mode as long as
this does not prevent proper operation all modes.
RESET
(PC Card Memory Mode)
I
41
The CompactFlash Storage Card is Reset when the
RESET pin is high with the following important exception:
The host may leave the RESET pin open or keep it continually
high from the application of power without causing a
continuous
Reset of the card. Under either of these conditions, the card
shall emerge from power-up having completed an initial Reset.
The CompactFlash Storage Card is also Reset
when the Soft Reset bit in the Card Configuration Option
Register is set.
RESET
(PC Card I/O Mode)
This signal is the same as the PC Card Memory Mode signal.
RESET
(True IDE Mode)
In the True IDE Mode, this input pin is the active low hardware
reset from the host.
Vcc
(PC Card Memory Mode)
13, 38
+5V, +3.3V power.
Vcc
(PC Card I/O Mode)
Same for all modes.
Vcc
(True IDE Mode)
Same for all modes.
VS1, VS2
(PC Card Memory Mode)
O
33, 40
Voltage Sense Signals. VS1 is grounded on the Card and
sensed by the Host so that the CompactFlash Storage Card
CIS can be read at 3.3 volts and VS2 is reserved by
PCMCIA for a secondary voltage and is not connected on the
Card.
VS1, VS2
(PC Card I/O Mode)
This signal is the same for all modes.
VS1, VS2
(True IDE Mode)
This signal is the same for all modes.
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Signal Name
Dir.
Pin
Description
WAIT
(PC Card Memory Mode)
O
42
The WAIT signal is driven low by the CompactFlash Storage
Card to signal the host to delay completion of a memory or I/O
cycle that is in progress.
WAIT
(PC Card I/O Mode)
This signal is the same as the PC Card Memory Mode signal.
IORDY
(True IDE Mode Except
Ultra DMA Mode)
In True IDE Mode, except in Ultra DMA modes, this output
signal may be used as IORDY.
-DDMARDY
(True IDE Mode Ultra
DMA Write Mode)
In True IDE Mode, when Ultra DMA mode DMA Write is active,
this signal is asserted by the host to indicate that the device is
read to receive Ultra DMA data-in bursts. The device may negate
DDMARDY to pause an Ultra DMA transfer.
DSTROBE
(True IDE Mode Ultra
DMA Read Mode)
In True IDE Mode, when Ultra DMA mode DMA Write is active,
this signal is the data out strobe generated by the device. Both
the rising and falling edge of DSTROBE cause data to be latched
by the host. The device may stop generating DSTROBE edges
to pause an Ultra DMA data-out burst.
WE
(PC Card Memory Mode)
I
36
This is a signal driven by the host and used for strobing memory
write data to the registers of the CompactFlash Storage
when the card is configured in the memory interface mode. It is
also used for writing the configuration registers.
WE
(PC Card I/O Mode)
In PC Card I/O Mode, this signal is used for writing the
configuration registers.
WE
(True IDE Mode)
In True IDE Mode, this input signal is not used and should be
connected to VCC by the host.
WP
(PC Card Memory Mode)
O
24
Memory Mode The CompactFlash Storage Card does not have
a write protect switch. This signal is held low after the
completion of the reset initialization sequence.
IOIS16
(PC Card I/O Mode)
I/O Operation When the CompactFlash Storage Card
is configured for I/O Operation Pin 24 is used for the I/O
Selected is 16 Bit Port (-IOIS16) function. A Low signal indicates
that a 16 bit or odd byte only operation can be performed at the
addressed port.
IOCS16
(True IDE Mode)
In True IDE Mode this output signal is asserted low when this
device is expecting a word data transfer cycle.
5.2 Electrical Specification
Table 13
defines the DC Characteristics for the CompactFlash Memory Card. Unless otherwise stated, conditions are:
Vcc = 5V ± 10%
Vcc = 3.3V ± 10%
0 °C to +85 °C
Table 13 shows that the Card operates correctly in both the voltage ranges and that the current requirements must
not exceed the maximum limit shown.
The current is measured by connecting an amp meter in series with the Vcc supply. The meter should be set to the
2A scale range, and have a fast current probe with an RC filter with a time constant of 0.1ms. Current
measurements are taken while looping on a data transfer command with a sector count of 128. Current
consumption values for both read and write commands are not to exceed the Maximum Average RMS Current
specified in Table 13.
Table 14 shows the Input Leakage Current, Table 15 the Input Characteristics, Table 16 the Output Drive Type and
Table 17 the Output Drive Characteristics.
Table 13: Absolute Maximum Conditions
Parameter
Symbol
Conditions
Input Power
VCC
-0.3V to 6.5V
Voltage on any pin except VCC with respect to GND
V
-0.5V to VCC +0.5V
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Table 14: Input Leakage current(1)
Type
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
IxZ
Input Leakage Current
IL
VIH =Vcc
-1
1
µA
VIL = GND
IxU
Pull Up Resistor
RPU1
Vcc = 5.0V
50
500
kOhm
IxD
Pull Down Resistor
RPD1
Vcc = 5.0V
50
500
kOhm
1. x refers to the characteristics described in Table 15 For example, I1U indicates a pull up resistor with a type 1 input
characteristic.
Table 15: Input characteristics
Type
Parameter
Symbol
Min.
Typ.
Max.
Min.
Typ.
Max.
Units
Vcc = 3.3V
Vcc = 5.0V
1
Input Voltage CMOS
VIH
2.0
3.6
2.0
5.3
V
VIL
-0.3
0.6
-0.3
0.8
2
Input Voltage CMOS
VIH
2.0
3.6
2.0
5.3
V
VIL
-0.3
0.6
-0.3
0.8
3
Input Voltage CMOS Schmitt
Trigger
VTH
2.0
3.6
2.0
5.3
V
VTL
-0.3
0.6
-0.3
0.8
Table 16: Output Drive Type(1)
Type
Output Type
Valid Conditions
Otx
Totempole
IOH & IOL
Ozx
Tri-State N-P Channel
IOH & IOL
Opx
P-Channel Only
IOH only
Onx
N-Channel Only
IOL only
1. x refers to the characteristics described in Table 15 For example, OT3 refers to totem pole output with a type 3 output drive
characteristic.
Table 17: Output Drive Characteristics
Type
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
1
Output Voltage
VOH
IOH= -1mA
2.4
V
VOL
IOL = 4mA
0.45
2
Output Voltage
VOH
IOH = -1mA
2.4
V
VOL
IOL = 4mA
0.45
3
Output Voltage
VOH
IOH= -1mA
2.4
V
VOL
IOL = 4mA
0.45
Tri-State
IOZ
VOL= Gnd
-10
10
µA
X
Leakage Current
VOH = Vcc
5.3 Additional requirements for CompactFlash Advanced Timing mode
When operating in a CompactFlash Advanced timing mode, the following conditions must be respected:
Only one CompactFlash Card must be connected to the CompactFlash bus.
The load capacitance (cable included) for all signals must be lower than 40pF.
The cable length must be lower than 0.15m (6 inches). The cable length is measured from the Card
connector to the host controller. 0.46m (18 inches) cables are not supported.
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6 Command Interface
There are two types of bus cycles and timing sequences that occur in the PCMCIA type interface, direct mapped I/O
transfer and memory access. Two types of bus cycles are also available in True IDE interface type: PIO transfer and
Multi-Word DMA transfer.
Table 18, Table 19, Table 20, Table 21, Table 22, Table 23, Table 24, and Table 25 show the read and write timing
parameters. Figure 2, Figure 3, Figure 4, Figure 5, Figure 6, Figure 7, and Figure 8 and Figure 9 show the read and
write timing diagrams.
In order to set the card mode, the OE (-ATASEL) signal must be set and kept stable before applying VCC until the
reset phase is completed. To place the card in Memory mode or I/O mode, -OE (-ATASEL) must be driven High,
while it must be driven Low to place the card in True IDE mode.
6.1 Attribute Memory Read and Write
Figure 2: Attribute Memory Read waveforms
Table 18: Attribute Memory Read timing
Speed version
300ns
Item
Symbol
IEEEE Symbol
Min. (ns)
Max. (ns)
Read Cycle Time
tcI
tAVAV
300
Address Access Time
ta(A)
tAVQV
300
Card Enable Access Time
ta(CE)
tELQV
300
Output Enable Access Time
ta(OE)
tGLQV
150
Output Disable Time from CE
tdis(CE)
tEHQZ
100
Output Disable Time from OE
tdis(OE)
tGHQZ
100
Output Enable Time from CE
ten(CE)
tELQNZ
5
Output Enable Time from OE
ten(OE)
tGLQNZ
5
Data Valid from Address Change
tv(A)
tAXQX
0
Address Setup Time
tsu(A)
tAVWL
30
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Figure 3: Configuration Register (Attribute Memory) Write waveforms
16 DIN signifies data provided by the system to the CompactFlash Card.
Table 19: Configuration Register (Attribute Memory) Write timing
Speed Version
250ns
Item
Symbol
IEEEE Symbol
Min. (ns)
Max. (ns)
Write Cycle Time
tc(W)
tAVAV
250
Write Pulse Width
tw(WE)
tWLWH
150
Address Setup Time
tsu(A)
tAVWL
30
Data Setup Time for WE
tsu(D-WEH)
tDVWH
80
Data Hold Time
th(D)
tWMDX
30
Write Recovery Time
trec(WE)
tWMAX
30
6.2 Common Memory Read and Write
Figure 4: Common Memory Read waveforms
17 DOUT means data provided by the CompactFlash Memory Card to the system.
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Table 20: Common Memory Read timing (1)$
18 Swissbit CF does not assert the WAIT signal.
Figure 5: Common Memory Write Waveforms
Table 21: Common Memory Write Timing(1)
Cycle Time Mode
250ns
120ns
100ns
80ns
Item
Symbol
IEEEE
Symbol
Min
(ns)
Max
(ns)
Min
(ns)
Max
(ns)
Min
(ns)
Max
(ns)
Min
(ns)
Max
(ns)
Data Setup before WE
tsu(D-WEH)
tDVWH
80
50
40
30
Data Hold following WE
th(D)
tIWMDX
30
15
10
10
WE Pulse Width
tw(WE)
tWLWH
150
70
60
55
Address Setup Time
tsu(A)
tAVWL
30
15
10
10
CE Setup before WE
tsu(CE)
tELWL
0
0
0
0
Write Recovery Time
trec(WE)
tWMAX
30
15
15
15
Address Hold Time
th(A)
tGHAX
20
15
15
10
CE Hold following WE
th(CE)
tGHEH
20
15
15
10
19 Swissbit CF does not assert the WAIT signal.
Cycle Time Mode
250ns
120ns
100ns
80ns
Item
Symbol
IEEEE
Symbol
Min
(ns)
Max
(ns)
Min
(ns)
Max
(ns)
Min
(ns)
Max
(ns)
Min
(ns)
Max
(ns)
Output Enable Access Time
ta(OE)
tGLQV
125
60
50
45
Output Disable Time from OE
tdis(OE)
tGHQZ
100
60
50
45
Address Setup Time
tsu(A)
tAVGL
30
15
10
10
Address Hold Time
th(A)
tGHAX
20
15
15
10
CE Setup before OE
tsu(CE)
tELGL
0
0
0
0
CE Hold following OE
th(CE)
tGHEH
20
15
15
10
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6.3 I/O Read and Write
Figure 6: I/O Read waveforms
20 DOUT signifies data provided by the CompactFlash Memory Card or to the system.
Table 22: I/O Read timing(1)
Cycle Time Mode
250ns
120ns
100ns
80ns
Item
Symbol
IEEEE
Symbol
Min
(ns)
Max
(ns)
Min
(ns)
Max
(ns)
Min
(ns)
Max
(ns)
Min
(ns)
Max
(ns)
Data Delay after IORD
td(IORD)
tIGLQV
100
50
50
45
Data Hold following IORD
th(IORD)
tIGHQX
0
5
5
5
IORD Width Time
tw(IORD)
tIGLIGH
165
70
65
55
Address Setup before IORD
tsuA(IORD)
tAVIGL
70
25
25
15
Address Hold following IORD
thA(IORD)
tIGHAX
20
10
10
10
CE setup before IORD
tsuCE(IORD)
tELIGL
5
5
5
5
CE Hold following IORD
thCE(IORD)
tIGHEH
20
10
10
10
REG setup before IORD
tsuREG(IORD)
tRGLIGL
5
5
5
5
REG Hold following IORD
thREG(IORD)
tIGHRGH
0
0
0
0
INPACK Delay Falling from
IORD
tdfINPACK(IORD)
tIGLIAL
0
45
0
NA(2)
0
NA(2)
0
NA(2)
NPACK Delay Rising from IORD
tdrINPACK(IORD)
tIGHIAH
45
NA(2)
NA(2)
NA(2)
IOIS16 Delay Falling from
Address
tdfIOIS16(ADR)
tAVISL
35
IOIS16 Delay Rising from
Address
tdrIOIS16(ADR)
tAVISH
35
1. Swissbit CF does not assert the WAIT signal.
2. IOIS16 is not supported in this mode.
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Figure 7: I/O Write waveforms
Table 23: I/O write timing
Cycle Time Mode
250ns
120ns
100ns
80ns
Item
Symbol
IEEEE
Symbol
Min
(ns)
Max
(ns)
Min
(ns)
Max
(ns)
Min
(ns)
Max
(ns)
Min
(ns)
Max
(ns)
Data Setup before IOWR
tsu(IOWR)
tDVIWH
60
20
20
15
Data Hold following IOWR
th(IOWR)
tIWHDX
30
10
5
5
IOWR Width Time
tw(IOWR)
tIWLIWH
165
70
65
55
Address Setup before IOWR
tsuA(IOWR)
tAVIWL
70
25
25
15
Address Hold following IOWR
thA(IOWR)
tIWHAX
20
20
10
10
CE setup before IOWR
tsuCE(IOWR)
tELIWL
5
5
5
5
CE Hold following IOWR
thCE(IOWR)
tIWHEH
20
20
10
10
REG setup before IOWR
tsuREG(IOWR)
tRGLIWL
5
5
5
5
REG Hold following IOWR
thREG(IOWR)
tIWHRGH
0
0
0
0
IOIS16 Delay Falling from Addr.
tdfIOIS16(ADR)
tAVISL
35
NA(2)
NA(2)
NA(2)
IOIS16 Delay Rising from Addr.
tdrIOIS16(ADR)
tAVISH
35
NA(2)
NA(2)
NA(2)
1. DIN signifies data provided by the system to the CompactFlash Memory Card.
2. IOIS16 and INPACK are not supported in this mode.
6.4 True IDE Mode
The timing waveforms for True IDE mode and True IDE DMA mode of operation in this section are drawn using the
conventions in the ATA-4 specification, which are different than the conventions used in the PCMCIA specification
and earlier versions of this specification. Signals are shown with their asserted state as High regardless of
whether the signal is actually negative or positive true. Consequently, the IORD, the
-IOWR and the IOCS16 signals are shown in the waveforms inverted from their electrical states on the bus.
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Figure 8: True IDE PIO mode Read/Write waveforms
1. The device addresses consists of CS0, −CS1, and A2-A0.
2. The Data I/O consist of D15-D0 (16-bit) or D7-D0 (8 bit).
3. IOCS16 is shown for PIO modes 0, 1 and 2. For other modes, this signal is ignored.
Table 24: True IDE PIO mode Read/Write timing(1)
Parameter
Symbol
Mode 0
(ns)
1
(ns)
2
(ns)
3
(ns)
4
(ns)
5(5)
(ns)
6(5)
(ns)
Cycle time (min)
t0(2)
600
383
240
180
120
100
80
Address Valid to IORD/-IOWR setup (min)
t1
70
50
30
30
25
15
10
-IORD/-IOWR (min)
t2(2)
165
125
100
80
70
65
55
-IORD/-IOWR (min) Register (8 bit)
t2(2)
290
290
290
80
70
65
55
-IORD/-IOWR recovery time (min)
t2i(2)
-
-
-
70
25
25
20
-IOWR data setup (min)
t3
60
45
30
30
20
20
15
-IOWR data hold (min)
t4
30
20
15
10
10
5
5
-IORD data setup (min)
t5
50
35
20
20
20
15
10
-IORD data hold (min)
t6z(3)
5
5
5
5
5
5
5
-IORD data tri-state (max)
t7(4)
30
30
30
30
30
20
20
Address valid to IOCS16 assertion (max)
t8(4)
90
50
40
NA
NA
NA
NA
Address valid to IOCS16 released (max)
t7
60
45
30
NA
NA
NA
NA
-IORD/-IOWR to address valid hold
t9
20
15
10
10
10
10
10
1. The maximum load on IOCS16 is 1 LSTTL with a 50pF total load.
2. t0 is the minimum total cycle time, t2 is the minimum command active time, and t2i is the minimum command recovery time or
command inactive time. The actual cycle time equals the sum of the actual command inactive time. The three timing requirements
of t0, t2, and t2i have to be met. The requirement is greater than the sum of t2 and t2i. This means a host implementation can ensure
that t0 is equal to or greater than the value reported in the devices identify drive Card implementation should support any legal
host implementation.
3. This parameter specifies the time from the falling edge of IORD to the moment when the CompactFlash Memory Card (tri-state).
4. t7 and t8 apply only to modes 0, 1 and 2. The IOCS16 signal is not valid for other modes.
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Figure 9: True IDE Multi-Word DMA Mode Read/Write waveforms
Table 25: True IDE Multi-Word DMA Mode Read/Write timing
Parameter
Symbol
Mode 0
(ns)
1
(ns)
2
(ns)
3
(ns)
4
(ns)
Cycle time (min)
t0(1)
480
150
120
100
80
-IORD / -IOWR asserted width (min)
tD(1)
215
80
70
65
55
-IORD data access (max)
tE
150
60
50
50
45
-IORD data hold (min)
tF
5
5
5
5
5
-IORD/-IOWR data setup (min)
tG
100
30
20
15
10
-IOWR data hold (min)
tH
20
15
10
5
5
DMACK to IORD/-IOWR setup (min)
tI
0
0
0
0
0
-IORD / -IOWR to DMACK hold (min)
tJ
20
5
5
5
5
-IORD Low width (min)
tKR(1)
50
50
25
25
20
-IOWR Low width (min)
tKW(1)
215
50
25
25
20
-IORD to DMARQ delay (max)
tLR
120
40
35
35
35
-IOWR to DMARQ delay (max)
tLW
40
40
35
35
35
CS(1:0) valid to IORD / -IOWR
tM
50
30
25
10
5
CS(1:0) hold
tN
15
10
10
10
10
-DMACK
tZ
20
25
25
25
25
1. t0 is the minimum total cycle time. TD is the minimum command active time. TKR and tKW are the minimum command recovery time
or command inactive time for input and output cycles, respectively. The actual cycle time is the sum of the actual command active
time and the actual command inactive time. The timing requirements of t0, tD, tKR, and tKW must be respected. T0 is higher than tD +
tKR or tD + tKW, for input and output cycles respectively. This means the host can lengthen either tD or tKR/tKW, or both, to ensure
that t0 is equal to or higher than the value reported in the devices identify device data. A CompactFlash Storage Card
implementation shall support any legal host implementation.
6.5 Ultra DMA Mode
6.5.1 Ultra DMA Overview
Ultra DMA is an optional data transfer protocol used with the READ DMA, and WRITE DMA, commands. When this
protocol is enabled, the Ultra DMA protocol shall be used instead of the Multiword DMA protocol when these
commands are issued by the host. This protocol applies to the Ultra DMA data burst only. When this protocol is
used there are no changes to other elements of the ATA protocol (e.g., Command Block Register access).
Ultra DMA operations can take place in any of the three basic interface modes: PC Card Memory mode, PC Card I/O
mode, and True IDE (the original mode to support UDMA). The usage of signals in each of the modes is shown in
Table 26: Ultra DMA Signal Usage In Each Interface Mode
DMARQ
DMACK
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Table 26: Ultra DMA Signal Usage In Each Interface Mode
UDMA Signal
Type
Pin # (Non UDMA
MEM MODE)
PC CARD MEM
MODE UDMA
PC CARD IO
MODE UDMA
TRUE IDE MODE
UDMA
DMARQ
Output
43 (-INPACK)
-DMARQ
-DMARQ
DMARQ
DMACK
Input
44 (-REG)
-DMACK
DMACK
-DMACK
STOP
Input
35 (-IOWR)
STOP 1
STOP 1
STOP 1
HDMARDYI
HSTROBE(W)
Input
34 (-IORD)
-HDMARDYI 1, 2
HSTROBE(W) 1, 3, 4
-HDMARDYI 1, 2
HSTROBE(W) 1, 3, 4
-HDMARDYI 1, 2
HSTROBE(W) 1, 3, 4
DDMARDY(W)
DSTROBEI
Output
42 (-WAIT)
-DDMARDY(W) 1, 3
DSTROBEI 1. 2. 4
-DDMARDY(W) 1, 3
DSTROBEI 1. 2. 4
-DDMARDY(W) 1, 3
DSTROBEI 1. 2. 4
DATA
Bidir
… (D[15:00])
D[15:00]
D[15:00]
D[15:00]
ADDRESS
Input
… (A[10:00])
A[10:00]
A[10:00]
A[02:00] 5
CSEL
Input
39 (-CSEL)
-CSEL
-CSEL
-CSEL
INTRQ
Output
37 (READY)
READY
-INTRQ
INTRQ
Card Select
Input
7 (-CE1)
31 (-CE2)
-CE1
-CE2
-CE1
-CE2
-CS0
-CS1
Notes:
1. The UDMA interpretation of this signal is valid only during an Ultra DMA data burst.
2. The UDMA interpretation of this signal is valid only during and Ultra DMA data burst during a DMA Read
command.
3. The UDMA interpretation of this signal is valid only during an Ultra DMA data burst during a DMA Write
command.
4. The HSTROBE and DSTROBE signals are active on both the rising and the falling edge.
5. Address lines 03 through 10 are not used in True IDE mode.
Several signal lines are redefined to provide different functions during an Ultra DMA burst. These lines assume
these definitions when:
1. an Ultra DMA mode is selected, and
2. a host issues a READ DMA, or a WRITE DMA command requiring data transfer, and
3. the device asserts (-)DMARQ, and
4. the host asserts DMACK.
These signal lines revert back to the definitions used for non-Ultra DMA transfers upon the negation of DMACK by
the host at the termination of an Ultra DMA burst.
With the Ultra DMA protocol, the STROBE signal that latches data from D[15:00] is generated by the same agent
(either host or device) that drives the data onto the bus. Ownership of D[15:00] and this data strobe signal are
given either to the device during an Ultra DMA data-in burst or to the host for an Ultra DMA data-out burst.
During an Ultra DMA burst a sender shall always drive data onto the bus, and, after a sufficient time to allow for
propagation delay, cable settling, and setup time, the sender shall generate a STROBE edge to latch the data.
Both edges of STROBE are used for data transfers so that the frequency of STROBE is limited to the same frequency
as the data.
Words in the IDENTIFY DEVICE data indicate support of the Ultra DMA feature and the Ultra DMA modes the device is
capable of supporting. The Set transfer mode subcommand in the SET FEATURES command shall be used by a host
to select the Ultra DMA mode at which the system operates. The Ultra DMA mode selected by a host shall be less
than or equal to the fastest mode of which the device is capable. Only one Ultra DMA mode shall be selected at
any given time. All timing requirements for a selected Ultra DMA mode shall be satisfied. Devices supporting any
Ultra DMA mode shall also support all slower Ultra DMA modes.
An Ultra DMA capable device shall retain the previously selected Ultra DMA mode after executing a software reset
sequence or the sequence caused by receipt of a DEVICE RESET command if a SET FEATURES disable reverting to
defaults command has been issued. The device may revert to a Multiword DMA mode if a SET FEATURES enable
reverting to default has been issued. An Ultra DMA capable device shall clear any previously selected Ultra DMA
mode and revert to the default non-Ultra DMA modes after executing a power-on or hardware reset.
Both the host and device perform a CRC function during an Ultra DMA burst. At the end of an Ultra DMA burst the
host sends its CRC data to the device. The device compares its CRC data to the data sent from the host. If the two
values do not match, the device reports an error in the error register. If an error occurs during one or more Ultra
DMA bursts for any one command, the device shall report the first error that occurred. If the device detects that a
CRC error has occurred before data transfer for the command is complete, the device may complete the transfer
and report the error or abort the command and report the error.
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NOTE If a data transfer is terminated before completion, the assertion of INTRQ should be passed through to the
host software driver regardless of whether all data requested by the command has been transferred.
6.5.2 Restrictions and Considerations During Ultra DMA Commands
There are number of important restrictions and considerations for the implementation and use of Ultra DMA
commands in CompactFlash devices. These are highlighted in the subsections below.
Additional restrictions on specific modes of operation are given in sections 5.3 and 6.5.3
6.5.2.1 System Restrictions for Ultra DMA modes 3 and above
Ultra DMA modes 3 and above are valid only for systems that meet the requirements of section 5.3
6.5.2.2 UDMA Address and Card Enable Signals
The Card Enable signals (-CE1 / -CS0 and CE2 / -CS1) shall remain negated during Ultra DMA data bursts.
The Address bus (A[10:00]) shall not transition unnecessarily during the UDMA command and shall remain fixed
during an Ultra DMA data burst. In True IDE mode, the address lines (A[02:00]) shall be held to all zeros. This will
reduce unnecessary noise during the UDMA command.
6.5.2.3 Task File registers shall not be written during an Ultra DMA command
The task file registers shall not be written after an Ultra DMA command is issued by the host and before the
command completes. Writing to the device control register is permitted between bursts, but is expected to occur
only to reset the card after an unrecoverable protocol error.
6.5.2.4 Ultra DMA transfers shall be 16 bits wide
All transfers during an Ultra DMA data burst are 16 bit wide transfers. The Set Features command that controls the
bus width for PIO transfers does not affect the width of Ultra DMA transfers.
6.5.2.5 No Access to Memory or I/O Space during an Ultra DMA Data Burst
No access to common or attribute memory or to I/O space on the device is permitted during an Ultra DMA data
burst.
6.5.3 Specific rules for PC Card Memory Mode Ultra DMA
In addition to the general restrictions for all Ultra DMA operations, these additional considerations exist for PC
Card Memory Mode Ultra DMA operations.
6.5.3.1 No Access to Attribute Memory during PC Card Memory Mode DMA Commands
The host shall not attempt to access Attribute Memory space during a PC Card Memory Mode DMA command either
before, between or within Ultra DMA data bursts.
6.5.3.2 READY signal handling during DMA commands in PC Card Memory Mode
In PC Card Memory Mode, the READY signal shall be negated (made BUSY) by the device upon receipt of a DMA
command and shall remain negated until the command has completed at which time it shall be re-asserted.
This treatment allows the host to receive a single interrupt at the end of the command and avoids the extra
overhead that would be associated with processing busy to ready transitions for each sector transferred as is the
case when the READY toggles at the end of every sector of PIO Memory Mode transfers.
The BSY bit in the status register is permitted to be negated in the status register at any time that the DRQ bit in
the status register is asserted. The only restriction is that either DRQ or BSY or both must remain asserted while
the command is in progress.
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6.5.4 Ultra DMA Phases of Operation
An Ultra DMA data transfer is accomplished through a series of Ultra DMA data-in or data-out bursts. Each Ultra
DMA burst has three mandatory phases of operation: the initiation phase, the data transfer phase, and the Ultra
DMA burst termination phase. In addition, an Ultra DMA burst may be paused during the data transfer phase (see:
6.5.4.4 , for the detailed protocol descriptions for each of these phases. Table 27: Ultra DMA Data Burst Timing
Requirements and Table 28: Ultra DMA Data Burst Timing Descriptions define the specific timing requirements). In
the following rules DMARDY is used in cases that could apply to either DDMARDY or HDMARDY, and STROBE is
used in cases that could apply to either DSTROBE or HSTROBE. The following are general Ultra DMA rules.
1. An Ultra DMA burst is defined as the period from an assertion of DMACK by the host to the subsequent
negation of DMACK.
2. When operating in Ultra DMA modes 2, 1, or 0 a recipient shall be prepared to receive up to two data
words whenever an Ultra DMA burst is paused. When operating in Ultra DMA modes 6, 5, 4, or 3 a
recipient shall be prepared to receive up to three data words whenever an Ultra DMA burst is paused.
6.5.4.1 Ultra DMA Burst Initiation Phase Rules
1. An Ultra DMA burst initiation phase begins with the assertion of DMARQ by a device and ends when the
sender generates a STROBE edge to transfer the first data word.
2. An Ultra DMA burst shall always be requested by a device asserting DMARQ.
3. When ready to initiate the requested Ultra DMA burst, the host shall respond by asserting DMACK.
4. A host shall never assert DMACK without first detecting that DMARQ is asserted.
5. For Ultra DMA data-in bursts: a device may begin driving D[15:00] after detecting that DMACK is asserted,
STOP negated, and HDMARDY is asserted.
6. After asserting DMARQ or asserting DDMARDY for an Ultra DMA data-out burst, a device shall not negate
either signal until the first STROBE edge is generated.
7. After negating STOP or asserting HDMARDY for an Ultra DMA data-in burst, a host shall not change the
state of either signal until the first STROBE edge is generated.
6.5.4.2 Ultra DMA Data transfer phase rules
1. The data transfer phase is in effect from after Ultra DMA burst initiation until Ultra DMA burst termination.
2. A recipient pauses an Ultra DMA burst by negating DMARDY and resumes an Ultra DMA burst by
reasserting DMARDY.
3. A sender pauses an Ultra DMA burst by not generating STROBE edges and resumes by generating STROBE
edges.
4. A recipient shall not signal a termination request immediately when the sender stops generating STROBE
edges. In the absence of a termination from the sender the recipient shall always negate DMARDY and
wait the required period before signaling a termination request.
5. A sender may generate STROBE edges at greater than the minimum period specified by the enabled Ultra
DMA mode. The sender shall not generate STROBE edges at less than the minimum period specified by the
enabled Ultra DMA mode. A recipient shall be able to receive data at the minimum period specified by the
enabled Ultra DMA mode.
6.5.4.3 Ultra DMA Burst Termination Phase Rules
1. Either a sender or a recipient may terminate an Ultra DMA burst.
2. Ultra DMA burst termination is not the same as command completion. If an Ultra DMA burst termination
occurs before command completion, the command shall be completed by initiation of a new Ultra DMA
burst at some later time or aborted by the host issuing a hardware or software reset or DEVICE RESET
command if implemented by the device.
3. An Ultra DMA burst shall be paused before a recipient requests a termination.
4. A host requests a termination by asserting STOP. A device acknowledges a termination request by
negating DMARQ.
5. A device requests a termination by negating DMARQ. A host acknowledges a termination request by
asserting STOP.
6. Once a sender requests a termination, the sender shall not change the state of STROBE until the recipient
acknowledges the request. Then, if STROBE is not in the asserted state, the sender shall return STROBE to
the asserted state. No data shall be transferred on this transition of STROBE.
7. A sender shall return STROBE to the asserted state whenever the sender detects a termination request
from the recipient. No data shall be transferred nor CRC calculated on this edge of DSTROBE.
8. Once a recipient requests a termination, the responder shall not change DMARDY from the negated state
for the remainder of an Ultra DMA burst.
9. A recipient shall ignore a STROBE edge when DMARQ is negated or STOP is asserted.
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6.5.4.4 Ultra DMA Data Transfers Timing
Table 27 and Table 28 define the timings associated with all phases of Ultra DMA bursts.
Table 27: Ultra DMA Data Burst Timing Requirements
Name
UDMA
Mode 0
(ns)
UDMA
Mode 1
(ns)
UDMA
Mode 2
(ns)
UDMA
Mode 3
(ns)
UDMA
Mode 4
(ns)
Measurement location
(See Note 2)
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
t2CYCTYP
240
160
120
90
60
Sender
tCYC
112
73
54
39
25
Note 3
t2CYC
230
153
115
86
57
Sender
tDS
15.0
10.0
7.0
7.0
5.0
Recipient
tDH
5.0
5.0
5.0
5.0
5.0
Recipient
tDVS
70.0
48.0
31.0
20.0
6.7
Sender
tDVH
6.2
6.2
6.2
6.2
6.2
Sender
tCS
15.0
10.0
7.0
7.0
5.0
Device
tCH
5.0
5.0
5.0
5.0
5.0
Device
tCVS
70.0
48.0
31.0
20.0
6.7
Host
tCVH
6.2
6.2
6.2
6.2
6.2
Host
tZFS
0
0
0
0
0
Device
tDZFS
70.0
48.0
31.0
20.0
6.7
Sender
tFS
230
200
170
130
120
Device
tLI
0
150
0
150
0
150
0
100
0
100
Note 4
tMLI
20
20
20
20
20
Host
tUI
0
0
0
0
0
Host
tAZ
10
10
10
10
10
Note 5
tZAH
20
20
20
20
20
Host
tZAD
0
0
0
0
0
Device
tENV
20
70
20
70
20
70
20
55
20
55
Host
tRFS
75
70
60
60
60
Sender
tRP
160
125
100
100
100
Recipient
tIORDYZ
20
20
20
20
20
Device
tZIORDY
0
0
0
0
0
Device
tACK
20
20
20
20
20
Host
tSS
50
50
50
50
50
Sender
Notes:
1. All timing measurement switching points (low to high and high to low) shall be taken at 1.5 V.
2. All signal transitions for a timing parameter shall be measured at the connector specified in the
measurement location column. For example, in the case of tRFS, both STROBE and DMARDY transitions
are measured at the sender connector.
3. The parameter tCYC shall be measured at the recipient’s connector farthest from the sender.
4. The parameter tLI shall be measured at the connector of the sender or recipient that is responding to an
incoming transition from the recipient or sender respectively. Both the incoming signal and the outgoing
response shall be measured at the same connector.
5. The parameter tAZ shall be measured at the connector of the sender or recipient that is driving the bus
but must release the bus the allow for a bus turnaround.
6. See the AC Timing requirements in Table 28: Ultra DMA Data Burst Timing Descriptions.
swissbit® Table 28: Ultra DMA Data Burst Timin Descri (ions 2cvcw= Ds DH Dvs aw cs CH cvs mm M Dst FS u MLI RP movz zwoRDv ACK www swisslm mm
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Table 28: Ultra DMA Data Burst Timing Descriptions
Name
Comment
Notes
t2CYCTYP
Typical sustained average two cycle time
tCYC
Cycle time allowing for asymmetry and clock variations (from STROBE edge to STROBE edge)
t2CYC
Two cycle time allowing for clock variations (from rising edge to next rising edge or from
falling edge to next falling edge of STROBE)
tDS
Data setup time at recipient (from data valid until STROBE edge)
2, 5
tDH
Data hold time at recipient (from STROBE edge until data may become invalid)
2, 5
tDVS
Data valid setup time at sender (from data valid until STROBE edge)
3
tDVH
Data valid hold time at sender (from STROBE edge until data may become invalid)
3
tCS
CRC word setup time at device
2
tCH
CRC word hold time device
2
tCVS
CRC word valid setup time at host (from CRC valid until DMACK negation)
3
tCVH
CRC word valid hold time at sender (from DMACK negation until CRC may become invalid)
3
tZFS
Time from STROBE output released-to-driving until the first transition of critical timing.
TDZFS
Time from data output released-to-driving until the first transition of critical timing.
TFS
First STROBE time (for device to first negate DSTROBE from STOP during a data in burst)
tLI
Limited interlock time
1
tMLI
Interlock time with minimum
1
tUI
Unlimited interlock time
1
tAZ
Maximum time allowed for output drivers to release (from asserted or negated)
tZAH
Minimum delay time required for output
tZAD
drivers to assert or negate (from released)
tENV
Envelope time (from DMACK to STOP and HDMARDY during data in burst initiation and
from DMACK to STOP during data out burst initiation)
tRFS
Ready-to-final-STROBE time (no STROBE edges shall be sent this long after negation of
-DMARDY)
tRP
Ready-to-pause time (that recipient shall wait to pause after negating DMARDY)
tIORDYZ
Maximum time before releasing IORDY
tZIORDY
Minimum time before driving IORDY
4
tACK
Setup and hold times for DMACK (before assertion or negation)
tSS
Time from STROBE edge to negation of DMARQ or assertion of STOP (when sender terminates
a burst)
Notes:
1. The parameters tUI, tMLI (in Figure 13: Ultra DMA Data-In Burst Device Termination Timing and Figure 14:
Ultra DMA Data-In Burst Host Termination Timing), and tLI indicate sender-to-recipient or recipient-to-
sender interlocks, i.e., one agent (either sender or recipient) is waiting for the other agent to respond
with a signal before proceeding. TUI is an unlimited interlock that has no maximum time value. TMLI is a
limited time-out that has a defined minimum. TLI is a limited time-out that has a defined maximum.
2. 80-conductor cabling shall be required in order to meet setup (tDS, tCS) and hold (tDH, tCH) times in modes
greater than 2.
3. Timing for tDVS, tDVH, tCVS and tCVH shall be met for lumped capacitive loads of 15 and 40 pF at the connector
where the Data and STROBE signals have the same capacitive load value. Due to reflections on the cable,
these timing measurements are not valid in a normally functioning system.
4. For all modes the parameter tZIORDY may be greater than tENV due to the fact that the host has a pull-up on
IORDY- giving it a known state when released.
5. The parameters tDS, and tDH for mode 5 are defined for a recipient at the end of the cable only in a
configuration with a single device located at the end of the cable. This could result in the minimum
values for tDS and tDH for mode 5 at the middle connector being 3.0 and 3.9 ns respectively.
swissbit® Table 29: Ultra DMA Sender and Recipient IC Timing Requirements SRISE SFALL WWW.SWiSSblem indus al@sw|ssh mm
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Table 29: Ultra DMA Sender and Recipient IC Timing Requirements
Name
Comments
UDMA
Mode 0
(ns)
UDMA
Mode 1
(ns)
UDMA
Mode 2
(ns)
UDMA
Mode 3
(ns)
UDMA
Mode4
(ns)
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
tDSIC
Recipient IC data setup time (from
data valid until STROBE edge)
(see note 2)
14.7
9.7
6.8
6.8
4.8
tDHIC
Recipient IC data hold time (from
STROBE edge until data may
become invalid) (see note 2)
4.8
4.8
4.8
4.8
4.8
tDVSIC
Sender IC data valid setup time
(from data valid until STROBE
edge) (see note 3)
72.9
50.9
33.9
22.6
9.5
tDVHIC
Sender IC data valid hold time
(from STROBE edge until data
may become invalid) (see note 3)
9.0
9.0
9.0
9.0
9.0
Notes:
1. All timing measurement switching points(low to high and high to low) shall be taken at 1.5 V.
2. The correct data value shall be captured by the recipient given input data with a slew rate of 0.4 V/ns rising and falling
and the input STROBE with a slew rate of 0.4 V/ns rising and falling at tDSIC and tDHIC timing (as measured through 1.5
V).
3. The parameters tDVSIC and tDVHIC shall be met for lumped capacitive loads of 15 and 40 pF at the IC where all signals
have the same capacitive load value. Noise that may couple onto the output signals from external sources has not been
included in these values.
Table 30: Ultra DMA AC Signal Requirements
Name
Comment
Min
[V/ns]
Max
[V/ns]
Notes
SRISE
Rising Edge Slew Rate for any signal
1.25
1
SFALL
Falling Edge Slew Rate for any signal
1.25
1
Note:
1. The sender shall be tested while driving an 18 inch long, 80 conductor cable with PVC insulation material. The signal
under test shall be cut at a test point so that it has not trace, cable or recipient loading after the test point. All other
signals should remain connected through to the recipient. The test point may be located at any point between the
sender’s series termination resistor and one half inch or less of conductor exiting the connector. If the test point is on
a cable conductor rather than the PCB, an adjacent ground conductor shall also be cut within one half inch of the
connector.
The test load and test points should then be soldered directly to the exposed source side connectors. The test loads
consist of a 15 pF or a 40 pF, 5%, 0.08 inch by 0.05 inch surface mount or smaller size capacitor from the test point to
ground. Slew rates shall be met for both capacitor values.
Measurements shall be taken at the test point using a <1 pF, >100 Kohm, 1 Ghz or faster probe and a 500 MHz or
faster oscilloscope. The average rate shall be measured from 20% to 80% of the settled VOH level with data
transitions at least 120 ns apart. The settled VOH level shall be measured as the average output high level under the
defined testing conditions from 100 nsec after 80% of a rising edge until 20% of the subsequent falling edge.
6.5.4.4.1 Initiating an Ultra DMA Data-In Burst
a) An Ultra DMA Data-In burst is initiated by following the steps lettered below. The timing diagram is
shown in Figure 10: Ultra DMA Data-In Burst Initiation Timing. The associated timing parameters are
specified in Table 27: Ultra DMA Data Burst Timing Requirements and are described in Table 28: Ultra DMA
Data Burst Timing Descriptions.
b) The following steps shall occur in the order they are listed unless otherwise specifically allowed:
c) The host shall keep DMACK in the negated state before an Ultra DMA burst is initiated.
d) The device shall assert DMARQ to initiate an Ultra DMA burst. After assertion of DMARQ the device shall not
negate DMARQ until after the first negation of DSTROBE.
e) Steps I, (d), and (e) may occur in any order or at the same time. The host shall assert STOP.
f) The host shall negate HDMARDY.
g) The host shall negate CS0, -CS1, DA2, DA1, and DA0. The host shall keep CS0, -CS1, DA2, DA1, and DA0
negated until after negating DMACK at the end of the burst.
h) Steps I, (d), and (e) shall have occurred at least tACK before the host asserts DMACK. The host shall keep
DMACK asserted until the end of an Ultra DMA burst.
i) The host shall release D[15:00] within tAZ after asserting DMACK.
j) The device may assert DSTROBE tZIORDY after the host has asserted DMACK. Once the device has driven
DSTROBE the device shall not release DSTROBE until after the host has negated DMACK at the end of an
Ultra DMA burst.
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k) The host shall negate STOP and assert HDMARDY within tENV after asserting DMACK. After negating STOP
and asserting HDMARDY, the host shall not change the state of either signal until after receiving the first
transition of DSTROBE from the device (i.e., after the first data word has been received).
l) The device shall drive D[15:00] no sooner than tZAD after the host has asserted DMACK, negated STOP, and
asserted HDMARDY.
m) The device shall drive the first word of the data transfer onto D[15:00]. This step may occur when the
device first drives D[15:00] in step (j).
n) To transfer the first word of data the device shall negate DSTROBE within tFS after the host has negated
STOP and asserted HDMARDY. The device shall negate DSTROBE no sooner than tDVS after driving the first
word of data onto D[15:00].
Figure 10: Ultra DMA Data-In Burst Initiation Timing
Notes: The definitions for the IORDY:-DDMARDY:DSTROBE, -IORD: -HDMARDY:HSTROBE, and IOWR:STOP signal lines
are not in effect until DMARQ and DMACK are asserted.
6.5.4.4.2 Sustaining an Ultra DMA Data-In Burst
An Ultra DMA Data-In burst is sustained by following the steps lettered below. The timing diagram is shown in
Figure 11: Sustained Ultra DMA Data-In Burst Timing. The timing parameters are specified in Table 27: Ultra DMA
Data Burst Timing Requirements and are described in Table 28: Ultra DMA Data Burst Timing Descriptions.
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The following steps shall occur in the order they are listed unless otherwise specifically allowed:
a) The device shall drive a data word onto D[15:00].
b) The device shall generate a DSTROBE edge to latch the new word no sooner than tDVS after changing the
state of D[15:00]. The device shall generate a DSTROBE edge no more frequently than tCYC for the selected
Ultra DMA mode. The device shall not generate two rising or two falling DSTROBE edges more frequently
than 2tcyc for the selected Ultra DMA mode.
c) The device shall not change the state of D[15:00] until at least tDVH after generating a DSTROBE edge to
latch the data.
d) The device shall repeat steps (a), (b), and (c) until the data transfer is complete or an Ultra DMA burst is
paused, whichever occurs first.
Figure 11: Sustained Ultra DMA Data-In Burst Timing
Notes: D[15:00] and DSTROBE signals are shown at both the host and the device to emphasize
that cable settling time as well as cable propagation delay shall not allow the data signals to
be considered stable at the host until some time after they are driven by the device.
6.5.4.4.3 Host Pausing an Ultra DMA Data-In Burst
The host pauses a Data-In burst by following the steps lettered below. A timing diagram is shown in Figure 12:
Ultra DMA Data-In Burst Host Pause Timing. The timing parameters are specified in Table 27: Ultra DMA Data Burst
Timing Requirements and are described in Table 28: Ultra DMA Data Burst Timing Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
a) The host shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been
transferred.
b) The host shall pause an Ultra DMA burst by negating HDMARDY.
c) The device shall stop generating DSTROBE edges within tRFS of the host negating HDMARDY.
d) If the host negates HDMARDY within tSR after the device has generated a DSTROBE edge, then the host
shall be prepared to receive zero or one additional data words. If the host negates HDMARDY greater
than tSR after the device has generated a DSTROBE edge, then the host shall be prepared to receive zero,
one or two additional data words. The additional data words are a result of cable round trip delay and tRFS
timing for the device.
e) The host shall resume an Ultra DMA burst by asserting HDMARDY.
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Figure 12: Ultra DMA Data-In Burst Host Pause Timing
Notes:
1. The host may assert STOP to request termination of the Ultra DMA burst no sooner than tRP after HDMARDY is
negated.
2. After negating HDMARDY, the host may receive zero, one, two, or three more data words from the device.
6.5.4.4.4 Device Terminating an Ultra DMA Data-In Burst
The device terminates an Ultra DMA Data-In burst by following the steps lettered below. The timing diagram is
shown in Figure 13: Ultra DMA Data-In Burst Device Termination Timing. The timing parameters are specified in
Table 27: Ultra DMA Data Burst Timing Requirements and are described in Table 28: Ultra DMA Data Burst Timing
Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
a) The device shall not pause an Ultra DMA burst until at least one data word of an Ultra
b) The device shall pause an Ultra DMA burst by not generating DSTROBE edges.
c) NOTE The host shall not immediately assert STOP to initiate Ultra DMA burst termination when the device
stops generating STROBE edges. If the device does not negate DMARQ, in order to initiate ULTRA DMA burst
termination, the host shall negate
d) The device shall resume an Ultra DMA burst by generating a DSTROBE edge.
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Figure 13: Ultra DMA Data-In Burst Device Termination Timing
Notes: The definitions for the STOP, HDMARDY, and DSTROBE signal lines are no longer in effect after DMARQ and
DMACK are negated.
6.5.4.4.5 Host Terminating an Ultra DMA Data-In Burst
The host terminates an Ultra DMA Data-In burst by following the steps lettered below. The timing
diagram is shown in Figure 14: Ultra DMA Data-In Burst Host Termination Timing. The timing
parameters are specified in Table 27: Ultra DMA Data Burst Timing Requirements and are
described in Table 28: Ultra DMA Data Burst Timing Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
a) The host shall not initiate Ultra DMA burst termination until at least one data word of an Ultra DMA burst
has been transferred.
b) The host shall initiate Ultra DMA burst termination by negating HDMARDY. The host shall continue to
negate HDMARDY until the Ultra DMA burst is terminated.
c) The device shall stop generating DSTROBE edges within tRFS of the host negating HDMARDY
d) If the host negates HDMARDY within tSR after the device has generated a DSTROBE edge, then the host
shall be prepared to receive zero or one additional data words. If the host negates HDMARDYgreater than
tSR after the device has generated a DSTROBE edge, then the host shall be prepared to receive zero, one or
two additional data words. The additional data words are a result of cable round trip delay and tRFS
timing for the device.
e) The host shall assert STOP no sooner than tRP after negating HDMARDY. The host shall not negate STOP
again until after the Ultra DMA burst is terminated.
f) The device shall negate DMARQ within tLI after the host has asserted STOP. The device shall not assert
DMARQ again until after the Ultra DMA burst is terminated.
g) If DSTROBE is negated, the device shall assert DSTROBE within tLI after the host has asserted STOP. No data
shall be transferred during this assertion. The host shall ignore this transition on DSTROBE. DSTROBE shall
remain asserted until the Ultra DMA burst is terminated.
h) The device shall release D[15:00] no later than tAZ after negating DMARQ.
i) The host shall drive DD D[15:00] no sooner than tZAH after the device has negated DMARQ. For this step, the
host may first drive D[15:00] with the result of its CRC calculation (see 6.5.4.5 ).
su.Iissbit® DMARQ (device) lu tum -DMACK 01°50 f ‘ZAH + tRP > ‘AZ ‘ a < tack="" d‘="" stop="" (host)="" kkk="" 4*="" ‘ack="" -h="" dmardv="" (host)="" ‘rfs="" ‘mli="" 4»="" 1—="" eu="" 4»="" dstrobe="" (device)="" tcvs="" data="" 015:000="" xxx="" a00,="" a01,="" a02,="" -c80.="" -c81="" www.5wissbil.mm="">
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j) If the host has not placed the result of its CRC calculation on D[15:00] since first driving D[15:00] during
(9), the host shall place the result of its CRC calculation on D[15:00] (see 6.5.4.5 ).
k) The host shall negate DMACK no sooner than tMLI after the device has asserted DSTROBE and negated
DMARQ and the host has asserted STOP and negated HDMARDY, and no sooner than tDVS after the host
places the result of its CRC calculation on D[15:00].
l) The device shall latch the host’s CRC data from D[15:00] on the negating edge of DMACK.
m) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If
a miscompare error occurs during one or more Ultra DMA burst for any one command, at the end of the
command, the device shall report the first error that occurred (see 6.5.4.5 ).
n) The device shall release DSTROBE within tIORDYZ after the host negates DMACK.
o) The host shall neither negate STOP nor assert HDMARDY until at least tACK after the host has negated
DMACK.
p) The host shall not assert IORD, -CS0, -CS1, DA2, DA1, or DA0 until at least tACK after negating DMACK.
Figure 14: Ultra DMA Data-In Burst Host Termination Timing
Notes: The definitions for the STOP, HDMARDY, and DSTROBE signal lines are no longer in effect after
DMARQ and DMACK are negated.
6.5.4.4.6 Initiating an Ultra DMA Data-Out Burst
An Ultra DMA Data-out burst is initiated by following the steps lettered below. The timing diagram
is shown in Figure 15: Ultra DMA Data-Out Burst Initiation Timing. The timing parameters are
specified in Table 27: Ultra DMA Data Burst Timing Requirements and are described in Table 28: Ultra DMA Data
Burst Timing Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
a) The host shall keep DMACK in the negated state before an Ultra DMA burst is initiated.
b) The device shall assert DMARQ to initiate an Ultra DMA burst.
c) Steps I, (d), and (e) may occur in any order or at the same time. The host shall assert STOP.
d) The host shall assert HSTROBE.
su.Iissbit® DMARQ (device) fl (U. —> -DMACK (host) (Acx few STOP (host) XXXX tZlORDY 4—» ‘u M + -DDMARDY ‘ (device) ------------------ .4. HSTROBE (host) M 'Dzrs P Data 4— luvs —><—> tow D15ID00 (host) tACK A00, A01, A02, -CSD, -CS1 www.5wi55bil.(om
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e) The host shall negate CS0, -CS1, DA2, DA1, and DA0. The host shall keep CS0, -CS1, DA2, DA1, and DA0
negated until after negating DMACK at the end of the burst.
f) Steps I, (d), and (e) shall have occurred at least tACK before the host asserts DMACK. The host shall keep
DMACK asserted until the end of an Ultra DMA burst.
g) The device may negate DDMARDY tZIORDY after the host has asserted DMACK. Once the device has negated
DDMARDY, the device shall not release DDMARDY until after the host has negated DMACK at the end of
an Ultra DMA burst.
h) The host shall negate STOP within tENV after asserting DMACK. The host shall not assert STOP until after the
first negation of HSTROBE.
i) The device shall assert DDMARDY within tLI after the host has negated STOP. After asserting DMARQ and
DDMARDY the device shall not negate either signal until after the first negation of HSTROBE by the host.
j) The host shall drive the first word of the data transfer onto D[15:00]. This step may occur any time during
Ultra DMA burst initiation.
k) To transfer the first word of data: the host shall negate HSTROBE no sooner than tUI after the device has
asserted DDMARDY. The host shall negate HSTROBE no sooner than tDVS after the driving the first word of
data onto D[15:00].
Figure 15: Ultra DMA Data-Out Burst Initiation Timing
Note: The definitions for the STOP, DDMARDY, and HSTROBE signal lines are not in effect until DMARQ
and DMACK are asserted.
6.5.4.4.7 Sustaining an Ultra DMA Data-Out Burst
An Ultra DMA Data-Out burst is sustained by following the steps lettered below. The timing diagram is shown in
Figure 16: Sustained Ultra DMA Data-Out Burst Timing. The associated timing parameters are specified in Table 27:
Ultra DMA Data Burst Timing Requirements and are described in Table 28: Ultra DMA Data Burst Timing
Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
a) The host shall drive a data word onto D[15:00].
su.Iissbit® lzcvc ‘cvc HSTROBE a! host \ ‘cvc tDvH lovmc fl bvs ‘Dvslc low ‘3va Data (015:000) W a! host HSTROBE at device Data (015:000) )OO< x="">O< at="" device="" www.5wi55bil.(om="">
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b) The host shall generate an HSTROBE edge to latch the new word no sooner than tDVS after changing the
state of D[15:00]. The host shall generate an HSTROBE edge no more frequently than tCYC for the selected
Ultra DMA mode. The host shall not generate two rising or falling HSTROBE edges more frequently than 2tcyc
for the selected Ultra DMA mode.
c) The host shall not change the state of D[15:00] until at least tDVH after generating an HSTROBE edge to latch
the data.
d) The host shall repeat steps (a), (b), and (c) until the data transfer is complete or an Ultra DMA burst is
paused, whichever occurs first.
Figure 16: Sustained Ultra DMA Data-Out Burst Timing
Note: Data (D15:D00) and HSTROBE signals are shown at both the device and the host to emphasize that cable
settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the
device until some time after they are driven by the host.
6.5.4.4.8 Device Pausing an Ultra DMA Data-Out Burst
The device pauses an Ultra DMA Data-Out burst by following the steps lettered below. The
timing diagram is shown in Figure 17: Ultra DMA Data-Out Burst Device Pause Timing. The
timing parameters are specified in Table 27: Ultra DMA Data Burst Timing Requirements and are
described in Table 28: Ultra DMA Data Burst Timing Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
a) The device shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been
transferred.
b) The device shall pause an Ultra DMA burst by negating DDMARDY.
c) The host shall stop generating HSTROBE edges within tRFS of the device negating DDMARDY.
d) If the device negates DDMARDY within tSR after the host has generated an HSTROBE edge, then the device
shall be prepared to receive zero or one additional data words. If the device negates DDMARDY greater
than tSR after the host has generated an HSTROBE edge, then the device shall be prepared to receive zero,
one or two additional data words. The additional data words are a result of cable round trip delay and tRFS
timing for the host.
e) The device shall resume an Ultra DMA burst by asserting DDMARDY.
su.Iissbit® <— tap="" dmarq="" (device)="" -dmack="" (host)="" stop="" (hos()="" -ddmardy="" (device)="" ths="" ,="" hstrobe="" (host)="" x="" x="" x="" data="" d15:doo="" (hos‘)="" xx="" xx="" xx="" xx="" xxxxxxx="" #4="" www.5wissbil.mm="" industrial@sw="" cm="">
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Figure 17: Ultra DMA Data-Out Burst Device Pause Timing
Notes:
1. The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than tRP after
-DDMARDY is negated.
2. After negating DDMARDY, the device may receive zero, one, two, or three more data words from the host.
6.5.4.4.9 Device Terminating an Ultra DMA Data-Out Burst
The device terminates an Ultra DMA Data-Out burst by following the steps lettered below. The timing diagram for
the operation is shown in Figure 18: Ultra DMA Data-Out Burst Device Termination Timing. The timing parameters
are specified in Table 27: Ultra DMA Data Burst Timing Requirements and are described in Table 28: Ultra DMA Data
Burst Timing Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
a) The device shall not initiate Ultra DMA burst termination until at least one data word of an Ultra DMA
burst has been transferred.
b) The device shall initiate Ultra DMA burst termination by negating DDMARDY.
c) The host shall stop generating an HSTROBE edges within tRFS of the device negating DDMARDY.
d) If the device negates DDMARDY within tSR after the host has generated an HSTROBE edge, then the device
shall be prepared to receive zero or one additional data words. If the device negates DDMARDY greater
than tSR after the host has generated anHSTROBE edge, then the device shall be prepared to receive zero,
one or two additional data words. The additional data words are a result of cable round trip delay and
tRFS timing for the host.
e) The device shall negate DMARQ no sooner than tRP after negating DDMARDY. The device shall not assert
DMARQ again until after the Ultra DMA burst is terminated.
f) The host shall assert STOP within tLI after the device has negated DMARQ. The host shall not negate STOP
again until after the Ultra DMA burst is terminated.
g) If HSTROBE is negated, the host shall assert HSTROBE within tLI after the device has negated DMARQ. No
data shall be transferred during this assertion. The device shall ignore this transition of HSTROBE. HSTROBE
shall remain asserted until the Ultra DMA burst is terminated.
h) The host shall place the result of its CRC calculation on D[15:00] (see 6.5.4.5 ).
i) The host shall negate DMACK no sooner than tMLI after the host has asserted HSTROBE and STOP and the
device has negated DMARQ and DDMARDY, and no sooner than tDVS after placing the result of its CRC
calculation on D[15:00].
j) The device shall latch the host’s CRC data from D[15:00] on the negating edge of DMACK.
k) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If
a miscompare error occurs during one or more Ultra DMA bursts for any one command.
su.Iissbit® Flgure 18: Ultra DMA Data-Out Burst Devlce Termlnallon Ylmlng < ‘l\="" dmarq="" (device)=""><7 tml.="" 4b="" -dmack="" (host)="" l="" m=""> ‘ ‘ACK > <7 (33="" 4,="" stop="" \m="" (host)="" ——="" 1*="" in="" 'iordvz="" -ddmardy_%="" (device)="" hstrobe="" (host)="">< w="" ‘cvs="" ‘cvh="" data="" d15:d00="" (host)="" ‘="" (acx="" "="" a00,="" a01,="" a02,="" -cso,="" -081="" w="" www.5wissbil.mm="" induslr="" @5="" 55h="" om="">
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Figure 18: Ultra DMA Data-Out Burst Device Termination Timing
Note: The definitions for the STOP, DDMARDY, and HSTROBE signal lines are no longer in effect after
DMARQ and DMACK are negated.
6.5.4.4.10 Host Terminating an Ultra DMA Data-Out Burst
Termination of an Ultra DMA Data-Out burst by the host is shown in Figure 19: Ultra DMA Data-Out Burst Host
Termination Timing while timing parameters are specified in Table 27: Ultra DMA Data Burst Timing Requirements
and timing parameters are described in Table 28: Ultra DMA Data Burst Timing Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
a) The host shall initiate termination of an Ultra DMA burst by not generating HSTROBE edges.
b) The host shall assert STOP no sooner than tSS after it last generated an HSTROBE edge. The host shall not
negate STOP again until after the Ultra DMA burst is terminated.
c) The device shall negate DMARQ within tLI after the host asserts STOP. The device shall not assert DMARQ
again until after the Ultra DMA burst is terminated.
d) The device shall negate DDMARDY within tLI after the host has negated STOP. The device shall not assert
DDMARDY again until after the Ultra DMA burst termination is complete.
e) If HSTROBE is negated, the host shall assert HSTROBE within tLI after the device has negated DMARQ. No
data shall be transferred during this assertion. The device shall ignore this transition on HSTROBE.
HSTROBE shall remain asserted until the Ultra DMA burst is terminated.
f) The host shall place the result of its CRC calculation on D[15:00] (see 6.5.4.5 ).
g) The host shall negate DMACK no sooner than tMLI after the host has asserted HSTROBE and STOP and the
device has negated DMARQ and DDMARDY, and no sooner than tDVS after placing the result of its CRC
calculation on D[15:00].
su.Iissbit® DMARQ (device) -DMACK (host) STOP (host) tRP -DDMARDY — ‘7 tLI j: IMLI 4*‘i tACK 4% O (IORDVZ (device) ‘Rrs .7 'u 4"— ‘MLI —N* (Aux j HSTROBE . ,. (host) —r"~—/ Data tcvs D15:DOD (hos!) X><>
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h) The device shall latch the host’s CRC data from D[15:00] on the negating edge of DMACK.
i) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If
a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the
command, the device shall report the first error that occurred (see 6.5.4.5 ).
j) The device shall release DDMARDY within tIORDYZ after the host has negated DMACK.
k) The host shall neither negate STOP nor negate HSTROBE until at least tACK after negating DMACK.
l) The host shall not assert IOWR, -CS0, -CS1, DA2, DA1, or DA0 until at least tACK after negating
-DMACK.
Figure 19: Ultra DMA Data-Out Burst Host Termination Timing
Notes: The definitions for the STOP, DDMARDY, and HSTROBE signal lines are no longer in effect after
DMARQ and DMACK are negated.
6.5.4.5 Ultra DMA CRC Calculation
The following is a list of rules for calculating CRC, determining if a CRC error has occurred during an Ultra DMA
burst, and reporting any error that occurs at the end of a command.
1. Both the host and the device shall have a 16-bit CRC calculation function.
2. Both the host and the device shall calculate a CRC value for each Ultra DMA burst.
3. The CRC function in the host and the device shall be initialized with a seed of 4ABAh at the beginning of
an Ultra DMA burst before any data is transferred.
4. For each STROBE transition used for data transfer, both the host and the device shall calculate a new CRC
value by applying the CRC polynomial to the current value of their individual CRC functions and the word
being transferred. CRC is not calculated for the return of STROBE to the asserted state after the Ultra DMA
burst termination request has been acknowledged.
5. At the end of any Ultra DMA burst the host shall send the results of its CRC calculation function to the
device on D[15:00] with the negation of DMACK.
swissbit® CRCINA = f12 RC|N12 = fl» XOR f9 XOR fie 3 = D02 XOR CRCOUT13 1= D10 XOR CRCOUT5 XOR f7 www.5wissblt.mm indus al@sw|ssh mm
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6. The device shall then compare the CRC data from the host with the calculated value in its own CRC
calculation function. If the two values do not match, the device shall save the error and report it at the
end of the command. A subsequent Ultra DMA burst for the same command that does not have a CRC error
shall not clear an error saved from a previous Ultra DMA burst in the same command. If a miscompare
error occurs during one or more Ultra DMA bursts for any one command, at the end of the command, the
device shall report the first error that occurred.
7. For READ DMA, WRITE DMA, READ DMA QUEUED, or WRITE DMA QUEUED commands:
When a CRC error is detected, it shall be reported by setting both ICRC and ABRT (bit 7 and bit 2 in the Error
register) to one. ICRC is defined as the “Interface CRC Error” bit. The host shall respond to this error by re-
issuing the command.
8. For a REQUEST SENSE packet command (see SPC T10/955D for definition of the REQUEST SENSE command):
When a CRC error is detected during transmission of sense data the device shall complete the command
and set CHK to one. The device shall report a Sense key of 0Bh (ABORTED COMMAND). The device shall
preserve the original sense data that was being returned when the CRC error occurred. The device shall
not report any additional sense data specific to the CRC error. The host device driver may retry the REQUEST
SENSE command or may consider this an unrecoverable error and retry the command that caused the
Check Condition.
9. For any packet command except a REQUEST SENSE command: If a CRC error is detected, the device shall
complete the command with CHK set to one. The device shall report a Sense key of 04h (HARDWARE
ERROR). The sense data supplied via a subsequent REQUEST SENSE command shall report an ASC/ASCQ value
of 08h/03h (LOGICAL UNIT COMMUNICATION CRC ERROR). Host drivers should retry the command that resulted
in a HARDWARE ERROR.
NOTE If excessive CRC errors are encountered while operating in Ultra mode 2 or 1, the host should select
a slower Ultra mode. Caution: CRC errors are detected and reported only while operating in an Ultra
mode.
10. A host may send extra data words on the last Ultra DMA burst of a data out command. If a device
determines that all data has been transferred for a command, the device shall terminate the burst. A
device may have already received more data words than were required for the command. These extra
words are used by both the host and the device to calculate the CRC, but, on an Ultra DMA data out burst,
the extra words shall be discarded by the device.
11. 11. The CRC generator polynomial is: G(X) = X16 + X12 + X5 + 1. Table 31 describes the equations for 16-bit
parallel generation of the resulting polynomial (based on a word boundary).
NOTE Since no bit clock is available, the recommended approach for calculating CRC is to use a word
clock derived from the bus strobe. The combinational logic is then equivalent to shifting sixteen bits
serially through the generator polynomial where D00 is shifted in first and D15 is shifted in last.
Table 31: Equations for parallel generation of an Ultra DMA CRC
CRCIN0 = f16
CRCIN8 = f8 XOR f13
CRCIN1 = f15
CRCIN9 = f7 XOR f12
CRCIN2 = f14
CRCIN10 = f6 XOR f11
CRCIN3 = f13
CRCIN11 = f5 XOR f10
CRCIN4 = f12
CRCIN12 = f4 XOR f9 XOR f16
CRCIN5 = f11 XOR f16
CRCIN13 = f3 XOR f8 XOR f15
CRCIN6 = f10 XOR f15
CRCIN14 = f2 XOR f7 XOR f14
CRCIN7 = f9 XOR f14
CRCIN15 = f1 XOR f6 XOR f13
f1 = D00 XOR CRCOUT15
f9 = D08 XOR CRCOUT7 XOR f5
f2 = D01 XOR CRCOUT14
f10 = D09 XOR CRCOUT6 XOR f6
f3 = D02 XOR CRCOUT13
f11 = D10 XOR CRCOUT5 XOR f7
f4 = D03 XOR CRCOUT12
f12 = D11 XOR CRCOUT4 XOR f1 XOR f8
f5 = D04 XOR CRCOUT11 XOR f1
f13 = D12 XOR CRCOUT3 XOR f2 XOR f9
f6 = D05 XOR CRCOUT10 XOR f2
f14 = D13 XOR CRCOUT2 XOR f3 XOR f10
f7 = D06 XOR CRCOUT9 XOR f3
f15 = D14 XOR CRCOUT1 XOR f4 XOR f11
f8 = D07 XOR CRCOUT8 XOR f4
f16 = D15 XOR CRCOUT0 XOR f5 XOR f12
Notes:
1. f=feedback
2. D[15:0] = Data to or from the bus
3. CRCOUT = 16-bit edge triggered result (current CRC)
4. CRCOUT[15:0] are sent on matching order bits of D[15:00]
An example of a CRC generator implementation is provided below in Figure 20: Ultra DMA Parallel CRC Generator
Example.
D 15:00 I —> Comblnatlonal Loglc CRCIN 15:00 [ 1. f1 -f16 Word Clock Edge Triggered Register Devrce CRCOUT[15:D] www.5wissbil.(om induslr @S ssh om SLUiSSbit®
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Figure 20: Ultra DMA Parallel CRC Generator Example
swissbit® rco www swisslm mm industnal@swussm am
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7 Card Configuration
The CompactFlash Memory Card is identified by information in the Card Information Structure (CIS). The Card has
four configuration registers (Table 32and Table 33).
Configuration Option Register
Pin Replacement Register
Card Configuration and Status Register
Socket and Copy Register
They are used to coordinate the I/O spaces and the Interrupt level of cards that are located in the system. In
addition, in I/O Card mode these registers provide a method for accessing status information that would normally
appear on dedicated pins in Memory Card mode.
The base address of the card configuration registers is 200h in the Attribute Memory space.
No write operation should be performed to the attribute memory area except for the configuration register
addresses. All other attribute memory locations are reserved. See 7.5
Attribute Memory Function.
Table 32: CompactFlash Memory Card Registers and Memory Space Decoding
-CE2
-CE1
-REG
-OE
-WE
A10
A9
A8-A4
A3
A2
A1
A0
Selected Space
1
1
X
X
X
X
X
XX
X
X
X
X
Standby
X
0
0
0
1
X
1
XX
X
X
X
0
Configuration Register Read
1
0
1
0
1
X
X
XX
X
X
X
X
Common Memory Read (8 bit D7 to D0)
0
1
1
0
1
X
X
XX
X
X
X
X
Common Memory Read (8 bit D15 to D8)
0
0
1
0
1
X
X
XX
X
X
X
0
Common Memory Read (16 bit D15 to D0)
X
0
0
1
0
X
1
XX
X
X
X
0
Configuration Register Write
1
0
1
1
0
X
X
XX
X
X
X
X
Common Memory Write (8 bit D7 to D0)
0
1
1
1
0
X
X
XX
X
X
X
X
Common Memory Write (8 bit D15 to D8)
0
0
1
1
0
X
X
XX
X
X
X
0
Common Memory Write (16 bit D15 to D0)
X
0
0
0
1
0
0
XX
X
X
X
0
Card Information Structure Read
1
0
0
1
0
0
0
XX
X
X
X
0
Invalid Access (CIS Write)
1
0
0
0
1
X
X
XX
X
X
X
1
Invalid Access (CIS Odd Byte Read)
1
0
0
1
0
X
X
XX
X
X
X
1
Invalid Access (CIS Odd Byte Write)
0
1
0
0
1
X
X
XX
X
X
X
X
Invalid Access (CIS Odd Byte Read)
0
1
0
1
0
X
X
XX
X
X
X
X
Invalid Access (CIS Odd Byte Write)
Table 33: CompactFlash Memory Card Configuration Registers Decoding
-CE2
-CE1
-REG
-OE
-WE
A10
A9
A8~A4
A3
A2
A1
A0
Selected Space
X
0
0
0
1
0
1
00
0
0
0
0
Configuration Option Register Read(200h)
X
0
0
1
0
0
1
00
0
0
0
0
Configuration Option Register Write(200h)
X
0
0
0
1
0
1
00
0
0
1
0
Card Status Register Read (202h)
X
0
0
1
0
0
1
00
0
0
1
0
Card Status Register Write (202h)
X
0
0
0
1
0
1
00
0
1
0
0
Pin Replacement Register Read (204h)
X
0
0
1
0
0
1
00
0
1
0
0
Pin Replacement Register Write (204h)
X
0
0
0
1
0
1
00
0
1
1
0
Socket and Copy Register Read (206h)
X
0
0
1
0
0
1
00
0
1
1
0
Socket and Copy Register Write (206h)
Note: The location of the Card Configuration Registers should always be read from the CIS since these locations
may vary in future products. No Writes should be performed to the Card Attribute Memory except to the Card
Configuration Register Addresses. All other attribute memory locations are reserved.
7.1 Configuration Option Register (200h in Attribute Memory)
The Configuration Option Register is used to configure the Card’s interface, address decoding and interrupt to the
Card (see Table 34).
7.1.1 SRESET
Setting the SRESET bit to ‘1’ and returning the bit ‘0’ places the CompactFlash Storage
Card in the Reset state. Setting this bit to ‘1’ is equivalent to asserting the RESET signal
except that the SRESET bit is not cleared. Returning the SRESET bit to ‘0’ leaves the
CompactFlash Storage Card in the same un-configured Reset state as after a power-up and
hardware reset.
This bit is set to ‘0’ at power-up and taking the Card through a hardware reset.
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7.1.2 LevlREQ
This bit is set to one (1) when Level Mode Interrupt is selected, and zero (0) when Pulse Mode is selected. Set to
zero (0) after Power Up.
7.1.3 Conf5 Conf0 (Configuration Index)
These bits are used to select the operation mode of the Card as shown in Table 35
.
This bit is set to ‘0’ after Power
Up.
Table 34: Configuration Option Register (default value: 00h)
Operation
D7
D6
D5
D4
D3
D2
D1
D0
R/W
SRESET
LevlREQ
Conf5
Conf4
Conf3
Conf2
Conf1
Conf0
Table 35: CompactFlash Memory Card Configurations
Conf5
Conf4
Conf3
Conf2
Conf1
Conf0
Mapping Mode
Card
Mode
Task File Register Address
0
0
0
0
0
0
Memory
Memory
0h Fh, 400h 7FFh
0
0
0
0
0
1
Contiguous I/O
I/O
xx0h xxFh
0
0
0
0
1
0
Primary I/O
I/O
1F0h 1F7h, 3F6h 3F7h
0
0
0
0
1
1
Secondary I/O
I/O
170h 177h, 376h 377h
7.2 CompactFlash Memory Card Configurations
The Card Configuration and Status Register contains information about the Card’s status (see Table 36).
7.2.1 Changed
Indicates that one or both of the Pin Replacement register (CRDY, or CWProt) bits are set to ‘1’. When the Changed
bit is set, -STSCHG (Pin 46) is held Low and if the SigChg bit is ‘1’ the Card is configured for the I/O interface.
7.2.2 SigChg
This bit is set and reset by the host to enable and disable a state-change signal from the Status Register (issued
on Status Changed pin 46). If no state change signal is desired, this bit should be set ‘0’ and pin 46 (-STSCHG) will
be held High while the Card is configured for I/O.
7.2.3 Iois8
The host sets this bit to ‘1’ if the Card is to be configured in 8 bit I/O Mode. The Card is always configured for both
8 and 16 bit I/O, so this bit is ignored.
7.2.4 PwrDwn
This bit indicates whether the Card is in the power saving mode or active mode. When the PwrDwn bit is set to ‘1’,
the Card enters power down mode. When set to ‘0’, the Card enters active mode. The READY value on Pin
Replacement Register becomes BUSY when this bit is changed. READY will not become Ready until the power state
requested has been entered. The Card automatically powers down when it is idle and powers back up when it
receives a command.
7.2.5 Int
This bit represents the internal state of the interrupt request. It is available whether or not the I/O interface has
been configured. It remains valid until the condition which caused the interrupt request has been serviced. If
interrupts are disabled by the IEN bit in the Device Control Register, this bit is ‘0’.
Table 36: Card Configuration and Status Register (default value: 00h)
Operation
D7
D6
D5
D4
D3
D2
D1
D0
Read
Changed
SigChg
IOIS8
0
0
PwrDwn
Int
0
Write
0
SigChg
IOIS8
0
0
PwrDwn
0
0
7.3 Pin Replacement Register (204h in Attribute Memory)
This register contains information on the state of the READY signal when configured in memory mode and the
IREQ signal in I/O mode. See Table 37
and Table 38.
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7.3.1 Cready
This bit is set to ‘1’ when the bit Rready changes state. This bit can also be written by the host.
7.3.2 CWProt
This bit is set to 1 when the bit RWProt changes state. This bit can also be written by the host.
7.3.3 Rready
This bit is used to determine the internal state of the Ready signal. In I/O mode it is used as an interrupt request.
When written, this bit acts as a mask (Mready) for writing the corresponding bit Cready.
7.3.4 Wprot
This bit is always ‘0’ since the CompactFlash Memory Card does not have a Write Protect switch. When written,
this bit acts as a mask for writing the corresponding CWProt bit.
7.3.5 Mready
This bit acts as a mask for writing the corresponding Cready bit.
7.3.6 MWProt
This bit when written acts as a mask for writing the corresponding CWProt bit.
Table 37: Pin Replacement Register (default value: 0Ch)
Operation
D7
D6
D5
D4
D3
D2
D1
D0
Read
0
0
Cready
CWProt
1
1
Rready
Wprot
Write
0
0
Cready
CWProt
0
0
Rready
MWProt
Table 38: Pin Replacement Changed Bit/Mask Bit Values
Initial Value of ‘C’ Status
Written by Host
Final ‘C’ Bit
Comments
‘C’ Bit
‘M’ Bit
0
X
0
0
Unchanged
1
X
0
1
Unchanged
X
0
1
0
Cleared by Host
X
1
1
1
Set by Host
7.4 Socket and Copy Register (206h in Attribute Memory)
This register contains additional configuration information which identifies the Card from other cards. This
register is always written by the system before writing the Configuration Option Register (see Table 39).
7.4.1 Drive #
This value can be used to address two different cards in the case of twin card configuration.
7.4.2 X
The socket number is ignored by the Card.
Table 39: Socket and Copy Register (default value: 00h)
Operation
D7
D6
D5
D4
D3
D2
D1
D0
Read
Reserved
0
0
Drive #
0
0
0
0
Write
0
0
0
Drive #
X
X
X
X
7.5 Attribute Memory Function
Attribute memory is a space where identification and configuration information are stored. Only 8 bit wide
accesses at even addresses can be performed in this area. The Card configuration registers are also located in the
Attribute Memory area, at base address 200h. Attribute memory is not accessible in True IDE mode of operation.
For the Attribute Memory Read function, signals REG and OE must be active and WE inactive during the cycle.
As in the Main Memory Read functions, the signals CE1 and CE2 control the even and odd Byte address, but only
the even Byte data is valid during the Attribute Memory access. Refer to Table 40
for signal states and bus
validity.
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Table 40: Attribute Memory Function
Function Mode
-REG
-CE2(1)
-CE1(1)
A10
A9
A0
-OE(1)
-WE(1)
D15 to D8
D7 to D0
Standby
X
H
H
X
X
X
X
X
High-Z
High-Z
Read Byte Access CIS (8 bits)
L
H
L
L
L
L
L
H
High-Z
Even Byte
Write Byte Access CIS (8 bits)
Invalid
L
H
L
L
L
L
H
L
Don’t Care
Even Byte
Read Byte Access
Configuration (8 bits)
L
H
L
L
H
L
L
H
High-Z
Even Byte
Write Byte Access
Configuration (8 bits)
L
H
L
L
H
L
H
L
Don’t Care
Even Byte
Read Byte Access
Configuration CF+ (8 bits)
L
H
L
X
X
L
L
H
High-Z
Even Byte
Read Word Access CIS (16
bits)
L
L
L
L
L
X
L
H
Not Valid
Even Byte
Write Word Access CIS (16
bits) Invalid
L
L
L
L
L
X
H
L
Don’t Care
Even Byte
Read Word Access
Configuration (16 bits)
L
L
L
L
H
X
L
H
Not Valid
Even Byte
Write Word Access
Configuration (16 bits)
L
L
L
L
H
X
H
L
Don’t Care
Even Byte
21 The CE signal or both the OE signal and the WE signal must be de-asserted between consecutive cycle operations.
7.6 I/O Transfer Function
The I/O transfer to or from the Card can be either 8 or 16 bits. When a 16 bit accessible port is addressed, the
IOIS16 signal is asserted by the Card, otherwise it is de-asserted. When a 16 bit transfer is attempted, and the
IOIS16 signal is not asserted, the system must generate a pair of 8 bit references to access the Word’s even and
odd Bytes. The Card permits both 8 and 16 bit accesses to all of its I/O addresses, so IOIS16 is asserted for all
addresses (see Table 41).
Table 41: I/O Function
Function Code
-REG
-CE2
-CE1
A0
-IORD
-IOWR
D15 to D8
D7 to D0
Standby Mode
X
H
H
X
X
X
High Z
High Z
Byte Input Access
L
H
L
L
L
H
High Z
Even Byte
(8 bits)
L
H
L
H
L
H
High Z
Odd Byte
Byte Output Access
L
H
L
L
H
L
Don’t Care
Even Byte
(8 bits)
L
H
L
H
H
L
Don’t Care
Odd Byte
Word Input Access (16 bits)
L
L
L
L
L
H
Odd Byte
Even Byte
Word Output Access (16 bits)
L
L
L
L
H
L
Odd Byte
Even Byte
I/O Read Inhibit
H
X
X
X
L
H
Don’t Care
Don’t Care
I/O Write Inhibit
H
X
X
X
H
L
High Z
High Z
High Byte Input Only (8 bits)
L
L
H
X
L
H
Odd Byte
High Z
High Byte Output Only (8 bits)
L
L
H
X
H
L
Odd Byte
Don’t Care
7.7 Common Memory Transfer Function
The Common Memory transfer to or from the Card permits both 8 or 16 bit access to all of the Common Memory
addresses (see Table 42).
Table 42: Common Memory Function
Function Code
-REG
-CE2
-CE1
A0
-OE
-WE
D15 to D8
D7 to D0
Standby Mode
X
H
H
X
X
X
High Z
High Z
Byte Read Access
H
H
L
L
L
H
High Z
Even Byte
(8 bits)
H
H
L
H
L
H
High Z
Odd Byte
Byte Write Access
H
H
L
L
H
L
Don’t Care
Even Byte
(8 bits)
H
H
L
H
H
L
Don’t Care
Odd Byte
Word Read Access (16 bits)
H
L
L
X
L
H
Odd Byte
Even Byte
Word Write Access (16 bits)
H
L
L
X
H
L
Odd Byte
Even Byte
Odd Byte Read Only (8 bits)
H
L
H
X
L
H
Odd Byte
High Z
Odd Byte Write Only (8 bits)
H
L
H
X
H
L
Odd Byte
Don’t Care
7.8 True IDE Mode I/O Function
The Card can be configured in a True IDE Mode of operation. It is configured in this mode only when the OE
signal is grounded by the host during the power off to power on cycle. In this True IDE Mode the PCMCIA protocol
and configuration are disabled and only I/O operations to the Task File and Data Register are allowed. No Memory
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or Attribute Registers are accessible to the host. The Set Feature Command can be used to put the device in 8 bit
Mode (see Table 43).
Removing and reinserting the Card while the host computer’s power is on will reconfigure the Card to PC Card ATA
mode.
Table 43: True IDE Mode I/O Function
Function Code
-CS1
-CS0
A2 to A0
-DMACK
-IORD
-IOWR
D15 to D8
D7 to D0
Invalid Mode
L
L
X
X
X
X
Undefined
In/Out
Undefined In/Out
L
X
X
L
L
X
Undefined Out
Undefined Out
L
X
X
L
X
L
Undefined In
Undefined In
X
L
X
L
L
X
Undefined Out
Undefined Out
X
L
X
L
X
L
Undefined In
Undefined In
Standby Mode
H
H
X
H
X
X
High Z
High Z
Task File Write
H
L
1h-7h
H
H
L
Don’t Care
Data In
Task File Read
H
L
1h-7h
H
L
H
High Z
Data Out
PIO Data Register Write
H
L
0
H
H
L
Odd-Byte In
Even-Byte In
DMA Data Register Write
H
L
X
L
H
L
Odd-Byte In
Even-Byte In
PIO Data Register Read
H
L
0
H
L
H
Odd-Byte Out
Even-Byte Out
DMA Data Register Read
H
H
X
L
L
H
Odd-Byte Out
Even-Byte Out
Control Register Write
L
H
6h
H
H
L
Don’t Care
Control In
Alternate Status Read
L
H
6h
H
L
H
High Z
Status Out
Drive Address
L
H
7h
H
L
H
High Z
Data Out
7.9 Host Configuration Requirements for Master/Slave or New Timing Modes
The CF Advanced Timing modes include PCMCIA PC Card style I/O modes that are faster than the original 250 ns
cycle time. These modes are not supported by the PCMCIA PC Card specification nor CF by cards based on revisions
of the CF specification before Revision 3.0. Hosts shall ensure that all cards accessed through a common electrical
interface are capable of operation at the desired, faster than 250 ns, I/O mode before configuring the interface for
that I/O mode.
Advanced Timing modes are PCMCIA PC Card style I/O modes that are 100 ns or faster, PC Card Memory modes that
are 100ns or faster, True IDE PIO Modes 5,6 and Multiword DMA Modes 3,4. These modes are permitted to be used
only when a single card is present and the host and card are connected directly, without a cable exceeding 0.15m
in length. Consequently, the host shall not configure a card into an Advanced Timing Mode if two cards are
sharing I/O lines, as in Master/Slave operation, nor if it is constructed such that a cable exceeding 0.15 meters is
required to connect the host to the card.
The load presented to the Host by cards supporting Ultra DMA is more controlled than that presented by other
CompactFlash cards. Therefore, the use of a card that does not support Ultra DMA in a Master/Slave arrangement
with a Ultra DMA card can affect the critical timing of the Ultra DMA transfers. The host shall not configure a card
into Ultra DMA mode when a card not supporting Ultra DMA is also present on the same interface
When the use of two cards on an interface is otherwise permitted, the host may use any mode that is supported
by both cards, but to achieve maximum performance it should use its highest performance mode that is also
supported by both cards.
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8 Software interface
8.1 CF-ATA Drive Register Set Definition and Protocol
The CompactFlash Memory Card can be configured as a high performance I/O device through:
Standard PC-AT disk I/O address spaces
o 1F0h-1F7h, 3F6h-3F7h (primary);
o 170h-177h, 376h-377h (secondary) with IRQ 14 (or other available IRQ).
Any system decoded 16 Byte I/O block using any available IRQ.
Memory space.
Communication to or from the Card is done using the Task File registers which provide all the necessary registers
for control and status information. The PCMCIA interface connects peripherals to the host using four-register
mapping methods. Table 44: I/O Configurations
is a detailed description of these methods:
Table 44: I/O Configurations
Standards Configurations
Config Index
I/O or Memory
Address
Description
0
Memory
0h-Fh, 400h-7FFh
Memory Mapped
1
I/O
xx0h-xxFh
I/O Mapped 16 Continuous Registers
2
I/O
1F0-1F7h, 3F6h-3F7h
Primary I/O Mapped
3
I/O
170-177h, 376h-377h
Secondary I/O Mapped
8.2 Memory Mapped Addressing
When the Card registers are accessed via memory references, the registers appear in the common memory space
window: 0-2Kbytes as shown in Table 45: Memory Mapped Decoding
.
This window accesses the Data Register
FIFO. It does not allow random access to the data buffer within the Card.
Register 0 is accessed with CE1 and CE2 Low, as a Word register on the combined Odd and Even Data Bus (D15 to
D0). It can also be accessed with CE1 Low and CE2 High, by a pair of Byte accesses to offset 0. The address space
of this Word register overlaps the address space of the Error and Feature Byte-wide registers at offset 1. When
accessed twice as Byte register with CE1 Low, the first Byte is the even Byte of the Word and the second is the
odd Byte. A Byte access to address 0 with CE1 High and CE2 Low accesses the Error (read) or Feature (write)
register.
Registers at offset 8, 9 and D are non-overlapping duplicates of the registers at offset 0 and 1. Register 8 is
equivalent to register 0, while register 9 accesses the odd Byte. Therefore, if the registers are Byte accessed in the
order 9 then 8 the data will be transferred odd Byte then even Byte. Repeated Byte accesses to register 8 or 0 will
access consecutive (even then odd) Bytes from the data buffer. Repeated Word accesses to register 8, 9 or 0 will
access consecutive Words from the data buffer, however repeated Byte accesses to register 9 are not supported.
Repeated alternating Byte accesses to registers 8 then 9 will access consecutive (even then odd) Bytes from the
data buffer.
Accesses to even addresses between 400h and 7FFh access register 8. Accesses to odd addresses between 400h
and 7FFh access register 9. This 1 kByte memory window to the data register is provided so that hosts can perform
memory-to-memory block moves to the data register when the register lies in memory space. Some hosts, such
as the X86 processors, must increment both the source and destination addresses when executing the memory-
to-memory block move instruction. Some PCMCIA socket adapters also have embedded auto incrementing address
logic.
A Word access to address at offset 8 will provide even data on the least significant Byte of the data bus, along
with odd data at offset 9 on the most significant Byte of the data bus.
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Table 45: Memory Mapped Decoding
-REG
A10
A9 to A4
A3
A2
A1
A0
Offset
-OE=0
-WE=0
1
0
X
0
0
0
0
0h
Even Data Register
Even Data Register
1
0
X
0
0
0
1
1h
Error Register
Feature Register
1
0
X
0
0
1
0
2h
Sector Count Register
Sector Count Register
1
0
X
0
0
1
1
3h
Sector Number Register
Sector Number Register
1
0
X
0
1
0
0
4h
Cylinder Low Register
Cylinder Low Register
1
0
X
0
1
0
1
5h
Cylinder High Register
Cylinder High Register
1
0
X
0
1
1
0
6h
Select Card/Head Register
Select Card/Head Register
1
0
X
0
1
1
1
7h
Status Register
Command Register
1
0
X
1
0
0
0
8h
Dup. Even Data Register
Dup. Even Data Register
1
0
X
1
0
0
1
9h
Dup. Odd Data Register
Dup. Odd Data Register
1
0
X
1
1
0
1
Dh
Dup. Error Register
Dup. Feature Register
1
0
X
1
1
1
0
Eh
Alternate Status Register
Device Control Register
1
0
X
1
1
1
1
Fh
Drive Address Register
Reserved
1
1
X
X
X
X
0
8h
Even Data Register
Even Data Register
1
1
X
X
X
X
1
9h
Odd Data Register
Odd Data Register
8.3 Contiguous I/O Mapped Addressing
When the system decodes a contiguous block of I/O registers to select the Card, the registers are accessed in the
block of I/O space decoded by the system as shown in Table 46
.
As for the Memory Mapped Addressing, register 0 is accessed with CE1 Low and CE2 Low (and A0 don’t Care) as a
Word register on the combined Odd and Even Data Bus (D15 to D0). This register may also be accessed with CE1
Low and CE2 High, by a pair of Byte accesses to offset 0. The address space of this Word register overlaps the
address space of the Error and Feature Byte-wide registers at offset 1. When accessed twice as Byte register with
CE1 Low, the first Byte is the even Byte of the Word and the second is the odd Byte. A Byte access to register 0 with
CE1 High and CE2 Low accesses the error (read) or feature (write) register.
Registers at offset 8, 9 and D are non-overlapping duplicates of the registers at offset 0 and 1. Register 8 is
equivalent to register 0, while register 9 accesses the odd Byte. Therefore, if the registers are Byte accessed in the
order 9 then 8 the data will be transferred odd Byte then even Byte. Repeated Byte accesses to register 8 or 0 will
access consecutive (even than odd) Bytes from the data buffer. Repeated Word accesses to register 8, 9 or 0 will
access consecutive Words from the data buffer, however repeated Byte accesses to register 9 are not supported.
Repeated alternating Byte accesses to registers 8 then 9 will access consecutive (even then odd) Bytes from the
data buffer.
Table 46: Contiguous I/O Decoding
-REG
A10 to A4
A3
A2
A1
A0
Offset
-IORD=0
-IOWR=0
0
X
0
0
0
0
0h
Even Data Register
Even Data Register
0
X
0
0
0
1
1h
Error Register
Feature Register
0
X
0
0
1
0
2h
Sector Count Register
Sector Count Register
0
X
0
0
1
1
3h
Sector Number Register
Sector Number Register
0
X
0
1
0
0
4h
Cylinder Low Register
Cylinder Low Register
0
X
0
1
0
1
5h
Cylinder High Register
Cylinder High Register
0
X
0
1
1
0
6h
Select Card/Head Register
Select Card/Head Register
0
X
0
1
1
1
7h
Status Register
Command Register
0
X
1
0
0
0
8h
Dup. Even Data Register
Dup. Even Data Register
0
X
1
0
0
1
9h
Dup. Odd Data Register
Dup. Odd Data Register
0
X
1
1
0
1
Dh
Dup. Error Register
Dup. Feature Register
0
X
1
1
1
0
Eh
Alternate Status Register
Device Control Register
0
X
1
1
1
1
Fh
Drive Address Register
Reserved
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8.4 I/O Primary and Secondary Address Configurations
When the system decodes the Primary and Secondary Address Configurations, the registers are accessed in the
block of I/O space as shown in Table 47
.
As for the Memory Mapped Addressing, register 0 is accessed with CE1 Low and –CE2 Low (and A0 don’t Care) as a
Word register on the combined Odd and Even Data Bus (D15 to D0). This register may also be accessed with CE1
Low and CE2 High, by a pair of Byte accesses to offset 0. The address space of this Word register overlaps the
address space of the Error and Feature Byte-wide registers at offset 1. When accessed twice as Byte register with
CE1 Low, the first Byte is the even Byte of the Word and the second is the odd Byte. A Byte access to register 0 with
CE1 High and CE2 Low accesses the error (read) or feature (write) register.
Table 47: Primary and Secondary I/O Decoding
-REG
A9 to A4
A3
A2
A1
A0
-IORD=0
-IOWR=0
0
1F(17)h
0
0
0
0
Even Data Register
Even Data Register
0
1F(17)h
0
0
0
1
Error Register
Feature Register
0
1F(17)h
0
0
1
0
Sector Count Register
Sector Count Register
0
1F(17)h
0
0
1
1
Sector Number Register
Sector Number Register
0
1F(17)h
0
1
0
0
Cylinder Low Register
Cylinder Low Register
0
1F(17)h
0
1
0
1
Cylinder High Register
Cylinder High Register
0
1F(17)h
0
1
1
0
Select Card/Head Register
Select Card/Head Register
0
1F(17)h
0
1
1
1
Status Register
Command Register
0
3F(37)h
0
1
1
0
Alternate Status Register
Device Control Register
0
3F(37)h
0
1
1
1
Drive Address Register
Reserved
8.5 True IDE Mode Addressing
When the Card is configured in the True IDE Mode, the I/O decoding is as shown in Table 48
.
Table 48: True IDE Mode I/O Decoding
-CS1
-CS0
A2
A1
A0
-DMACK
-IORD=0
-IOWR=0
1
0
0
0
0
1
PIO RD Data
PIO WR Data
1
1
X
X
X
0
DMA RD Data
DMA WR Data
1
0
0
0
1
1
Error Register
Features
1
0
0
1
0
1
Sector Count
Sector Count
1
0
0
1
1
1
Sector No.
Sector No.
1
0
1
0
0
1
Cylinder Low
Cylinder Low
1
0
1
0
1
1
Cylinder High
Cylinder High
1
0
1
1
0
1
Select Card/Head
Select Card/Head
1
0
1
1
1
1
Status
Command
0
1
1
1
0
1
Alt Status
Control Register
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9 CF-ATA Registers
The following section describes the hardware registers used by the host software to issue commands to the Card.
These registers are collectively referred to as the ‘task file’.
In accordance with the PCMCIA specification, each register that is located at an odd offset address can be accessed
in the PC Card Memory or PC Card I/O modes. The register can be addressed in two ways:
Using the normal register address.
Using the corresponding even address (normal address -1) when CE1 is High and CE2 Low, unless IOIS16
is High (not asserted by the card) and an I/O cycle is in progress. Register data are input or output on data
bus lines D15-D8.
In True IDE mode, the size of the transfer is based solely on the register being addressed. All registers are 8-bit
only except for the Data Register, which is normally 16 bits. However, they can be configured to be accessed in 8-
bit mode for non-DMA operations, by using a Set Features command (see
Section 10.20
).
9.1 Data Register
The Data register is located at address 1F0h [170h], offset 0h, 8h, and 9h.
The Data Register is a 16 bit register used to transfer data blocks between the Card data buffer and the Host. This
register overlaps the Error Register. Table 49
and Table 50
describe the combinations of Data register access and
explain the overlapped Data and Error/Feature Registers. Because of the overlapped registers, access to the 1F1h,
171h or offset 1 are not defined for Word (-CE2 and –CE1 set to ‘0’) operations, and are treated as accesses to the
Word Data Register. The duplicated registers at offsets 8, 9 and Dh have no restrictions on the operations that can
be performed.
Table 49: Data Register Access (Memory and I/O mode)
Data Register
-CE2
-CE1
A0
-REG(1)
Offset
Data Bus
Word Data Register
0
0
X
-
0h, 8h, 9h
D15 to D0
Even Data Register
1
0
0
-
0h, 8h
D7 to D0
Odd Data Register
1
0
1
-
9h
D7 to D0
Odd Data Register
0
1
X
-
8h, 9h
D15 to D8
Error/Feature Register
1
0
1
-
1h, Dh
D7 to D0
Error/Feature Register
0
1
X
-
1h
D15 to D8
Error/Feature Register
0
0
X
-
Dh
D15 to D8
22 REG signal is mode dependent. It must be Low when the Card operates in I/O Mode and High when it operates in
Memory Mode.
Table 50: Data Register Access (True IDE mode)
Data Register
-CS1
-CS0
A0
-DMACK
Offset
Data Bus
PIO Word Data Register
1
0
0
1
0h
D15 to D0
DMA Word Data Register
1
1
X
0
X
D15 to D0
PIO Byte Data Register (Selected Using Set
Features Command)
1
0
0
1
0h
D7 to D0
9.2 Error Register
The Error register is a read-only register, located at address 1F1h [171h], offset 1h, 0Dh.
This read only register contains additional information about the source of an error when an error is indicated in
bit 0 of the Status register. The bits are defined in Table 51
This register is accessed on data bits D15 to D8 during a
write operation to offset 0 with CE2 Low and CE1 High.
9.2.1 Bit 7 (BBK)
This bit is set when a Bad Block is detected.
9.2.2 Bit 6 (UNC)
This bit is set when an Uncorrectable Error is encountered.
9.2.3 Bit 5
This bit is ‘0’.
9.2.4 Bit 4 (IDNF)
This bit is set if the requested sector ID is in error or cannot be found.
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9.2.5 Bit 3
This bit is ‘0’.
9.2.6 Bit 2 (Abort)
This bit is set if the command has been aborted because of a Card status condition (Not Ready, Write Fault, etc.)
or when an invalid command has been issued.
9.2.7 Bit 1
This bit is ‘0’.
9.2.8 Bit 0 (AMNF)
This bit is set when there is a general error.
Table 51: Error Register
D7
D6
D5
D4
D3
D2
D1
D0
BBK
UNC
0
IDNF
0
ABRT
0
AMNF
9.3 Feature Register
The Feature register is a write-only register, located at address 1F1h [171h], offset 1h, Dh.
This write-only register provides information on features that the host can utilize. It is accessed on data bits D15
to D8 during a write operation to Offset 0 with CE2 Low and CE1 High.
9.4 Sector Count Register
The Sector Count register is located at address 1F2h [172h], offset 2h.
This register contains the number of sectors of data to be transferred on a read or write operation between the
host and Card. If the value in this register is zero, a count of 256 sectors is specified. If the command was
successful, this register is zero at completion. If not successfully completed, the register contains the number of
sectors that need to be transferred in order to complete the request. The default value is 01h.
9.5 Sector Number (LBA 7-0) Register
The Sector Number register is located at address 1F3h [173h], offset 3h.
This register contains the starting sector number or bits 7 to 0 of the Logical Block Address (LBA), for any data
access for the subsequent sector transfer command.
9.6 Cylinder Low (LBA 15-8) Register
The Cylinder Low register is located at address 1F4h [174h], offset 4h.
This register contains the least significant 8 bits of the starting cylinder address or bits 15 to 8 of the Logical Block
Address.
9.7 Cylinder High (LBA 23-16) Register
The Cylinder High register is located at address 1F5h [175h], offset 5h.
This register contains the most significant bits of the starting cylinder address or bits 23 to 16 of the Logical Block
Address.
9.8 Drive/Head (LBA 27-24) Register
The Driver/Head register is located at address 1F6h [176h], offset 6h.
The Drive/Head register is used to select the drive and head. It is also used to select LBA addressing instead of
cylinder/head/sector addressing. The bits are defined in Table 52
.
9.8.1 Bit 7
This bit is set to ‘1’.
9.8.2 Bit 6 (LBA)
LBA is a flag to select either Cylinder/Head/Sector (CHS) or Logical Block Address Mode (LBA). When LBA is set to ‘0’,
Cylinder/Head/Sector mode is selected. When LBA is set to’1’, Logical Block Address is selected. In Logical Block
Mode, the Logical Block Address is interpreted as follows:
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LBA7-LBA0: Sector Number Register D7 to D0
LBA15-LBA8: Cylinder Low Register D7 to D0
LBA23-LBA16: Cylinder High Register D7 to D0
LBA27-LBA24: Drive/Head Register bits HS3 to HS0
9.8.3 Bit 5
This bit is set to ‘1’.
9.8.4 Bit 4 (DRV)
DRV is the drive number. When DRV is ‘0’, drive/card 0 is selected (Master). When DRV is ‘1’, drive/card 1 is selected
(Slave). The Card is set to Card 0 or 1 using the copy field (Drive #) of the PCMCIA Socket & Copy configuration
register.
9.8.5 Bit 3 (HS3)
When operating in the Cylinder, Head, Sector mode, this is bit 3 of the head number. It is bit 27 in the Logical
Block Address mode.
9.8.6 Bit 2 (HS2)
When operating in the Cylinder, Head, Sector mode, this is bit 2 of the head number. It is bit 26 in the Logical
Block Address mode.
9.8.7 Bit 1 (HS1)
When operating in the Cylinder, Head, Sector mode, this is bit 1 of the head number. It is Bit 25 in the Logical
Block Address mode.
9.8.8 Bit 0 (HS0)
When operating in the Cylinder, Head, Sector mode, this is bit 0 of the head number. It is Bit 24 in the Logical
Block Address mode.
Table 52: Drive/Head Register
D7
D6
D5
D4
D3
D2
D1
D0
1
LBA
1
DRV
HS3
HS2
HS1
HS0
9.9 Status & Alternate Status Registers
The Status & Alternate Status registers are located at addresses 1F7h [177h] and 3F6h [376h], respectively. Offsets
are 7h and Eh.
These registers return the Card status when read by the host.
Reading the Status Register clears a pending interrupt. Reading the Auxiliary Status Register does not clear a
pending interrupt.
The Status Register should be accessed in Byte mode; in Word mode it is recommended that Alternate Status
Register is used. The status bits are described as follows
9.9.1 Bit 7 (BUSY)
The busy bit is set when only the Card can access the command register and buffer, The host is denied access. No
other bits in this register are valid when this bit is set to ‘1’.
9.9.2 Bit 6 (RDY)
This bit indicates whether the device is capable of performing CompactFlash Memory Card operations. This bit is
cleared at power up and remains cleared until the Card is ready to accept a command.
9.9.3 Bit 5 (DWF)