VTM48EF012T130A01 Datasheet by Vicor Corporation

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Rev. 1.2
7/2012
Page 1 of 17
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
vicorpower.com
VTM48EF012T130A01
VTM™
Current Multiplier
VIN = 26 to 55 V
VOUT = 0.7 to 1.4 V(NO LOAD)
IOUT = 130 A(NOM)
K = 1/40
PART NUMBER DESCRIPTION
VTM48EF012T130A01 -40 °C to 125 °C TJ
PRMTM
Regulator
PRPC TM
+IN
-IN
IF RE SG VC
-OUT
+OUT
Load
38 to 55
Vdc Input
Current
Sense
Enable/
Disable
Feedback
Voltage
Reference
Voltage
Control
PC
+IN
-IN
VC
+OUT1
+OUT2
-OUT1
-OUT2
PC
+IN
-IN
VC
+OUT1
+OUT2
-OUT1
-OUT2
Constant
Vc
CUS
®
S
NRTL
CUS
FEATURES
Optimized for VR12.0
40 Vdc to 1 Vdc 130 A current multiplier
- Operating from standard 48 V or 24 V PRM™ regulators
High efficiency (> 94 %) reduces system power
consumption
High density ( 443 A /in3)
Full Chip ” VI Chip®package enables surface mount,
low impedance interconnect to system board
Contains built-in protection features against:
- Overvoltage
- Overtemperature
Provides enable / disable control,
internal temperature monitoring
ZVS / ZCS resonant Sine Amplitude Converter topology
Less than 50ºC temperature rise at full load
in typical applications
TYPICAL APPLICATIONS
High End Computing Systems
Automated Test Equipment
High Density Power Supplies
Communications Systems
DESCRIPTION
The VI Chip®current multiplier is a high efficiency (> 94 %) Sine
Amplitude Converter™ (SAC™) operating from a 26 to 55 Vdc
primary bus to deliver an isolated output. The Sine Amplitude
Converter offers a low AC impedance beyond the bandwidth
of most downstream regulators; therefore capacitance normally
at the load can be located at the input to the Sine Amplitude
Converter. Since the K factor of the VTM48EF012T130A01 is
1/40 , the capacitance value can be reduced by a factor of 1600 ,
resulting in savings of board area, materials and total system cost.
The VTM48EF012T130A01 is provided in a VI Chip®package
compatible with standard pick-and-place and surface mount
assembly processes. The co-molded VI Chip®package provides
enhanced thermal management due to a large thermal
interface area and superior thermal conductivity. The high
conversion efficiency of the VTM48EF012T130A01 increases
overall system efficiency and lowers operating costs compared
to conventional approaches.
The VTM48EF012T130A01 enables the utilization of Factorized
Power Architecture™ which provides efficiency and size
benefits by lowering conversion and distribution losses and
promoting high density point of load conversion.
TYPICAL APPLICATION
VTM48EF012T130A01
VTM48EF012T130A01
5 g i E 5 g i E
Rev. 1.2
7/2012
Page 2 of 17
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
vicorpower.com
PRELIMINARY DATASHEET
VTM48EF012T130A01
ATTRIBUTE SYMBOL CONDITIONS / NOTES MIN TYP MAX UNIT
Input voltage range VIN No external VC applied 26 55 VDC
VC applied 0 55
VIN slew rate dVIN /dt 1 V/µs
VIN UV turn off VIN_UV Module latched shutdown, 18 26 V
No external VC applied, IOUT = 130 A
No Load power dissipation PNL
VIN = 40 V 1.5 5
W
VIN = 26 V to 55 V 6
VIN = 40 V, TC= 25 ºC 2.2 3.5
VIN = 26 V to 55 V, TC= 25 ºC 4.5
Inrush current peak IINRP VC enable, VIN = 40 V, COUT = 64400 µF, 7 11 A
RLOAD = 7 mΩ
DC input current IIN_DC 4.5 A
Transfer ratio K K = VOUT /V
IN, IOUT = 0 A 1/40 V/V
Output voltage VOUT VOUT = VIN K - IOUT ROUT, Section 11 V
30 °C < Tc< 100 °C, 130
Output current (average) IOUT_AVG
Iout_max = - (2/7) * Tc + 159 A
TC= 30 ºC 150
Output current (peak) IOUT_PK TPEAK < 10 ms, IOUT_AVG 130 A 195 A
Output power (average) POUT_AVG IOUT_AVG 130 A 178 W
Efficiency (ambient) ηAMB
VIN = 40 V, IOUT = 130 A 88.0 90.1
VIN = 26 V to 55 V, IOUT = 130 A 82.5 %
VIN = 40 V, IOUT = 65 A 91.0 92.5
VIN = 40 V, IOUT = 150 A 87 88.5
Efficiency (hot) ηHOT VIN = 40 V, TC= 100 °C, IOUT = 130 A 86.2 88.5 %
Efficiency (over load range) η20% 26 A < IOUT < 130 A 80 %
Output resistance (cold) ROUT_COLD TC= -40 °C, IOUT = 130 A
0.33 0.53 0.72 mΩ
Output resistance (ambient) ROUT_AMB TC= 25 °C, IOUT = 130 A 0.45 0.62 0.80 mΩ
Output resistance (hot) ROUT_HOT TC= 100 °C, IOUT = 130 A 0.58 0.72 0.94 mΩ
Switching frequency FSW 1.14 1.20 1.26 MHz
Output ripple frequency FSW_RP 2.28 2.40 2.52 MHz
Output voltage ripple VOUT_PP COUT = 0 F, IOUT = 130 A, VIN = 40 V, 125 175 mV
20 MHz BW, Section 11
Output inductance (parasitic) LOUT_PAR Frequency up to 30 MHz, 150 pH
Simulated J-lead model
Output capacitance (internal) COUT_INT Effective Value at 1 VOUT 350 µF
Output capacitance (external) COUT VTM Standalone Operation. 64400 µF
VIN pre-applied, VC enable
PROTECTION
Overvoltage lockout VIN_OVLO+Module latched shutdown 55.1 58.1 59.9 V
Overvoltage lockout TOVLO Effective internal RC filter 0.25 µs
response time constant
Output overcurrent trip IOCP N/A N/A N/A A
Short circuit protection trip current ISCP N/A A
Output overcurrent TOCP Effective internal RC filter (Integrative). N/A ms
response time constant
Short circuit protection response time TSCP From detection to cessation N/A µs
of switching (Instantaneous)
Thermal shutdown setpoint TJ_OTP 125 130 135 ºC
Reverse inrush current protection Reverse Inrush protection enabled for this product
1.0 ABSOLUTE MAXIMUM VOLTAGE RATINGS
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent
damage to the device.
2.0 ELECTRICAL CHARACTERISTICS
Specifications apply over all line and load conditions unless otherwise noted; Boldface specifications apply over the temperature
range of -40 °C < TJ< 125 °C (T-Grade); All other specifications are at TJ= 25 ºC unless otherwise noted.
MIN MAX UNIT
+ IN to - IN . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0 60 VDC
PC to - IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 20 VDC
TM to -IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 7 VDC
VC to - IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 20 VDC
MIN MAX UNIT
IM to - IN......................................................... 0 3.15 VDC
+ IN / - IN to + OUT / - OUT (hipot)................ 1500 VDC
+ IN / - IN to + OUT / - OUT (working)........... 60 VDC
+ OUT to - OUT............................................... -1.0 5.5 VDC
Rev. 1.2
7/2012
Page 3 of 17
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
vicorpower.com
VTM48EF012T130A01
SIGNAL TYPE STATE ATTRIBUTE SYMBOL CONDITIONS / NOTES MIN TYP MAX UNIT
External VC voltage VVC_EXT Required for start up, and operation
11.5 16.5 V
below 26 V. See Section 7.
VC = 11.5 V, VIN = 0 V 115 150
VC current draw IVC
VC = 11.5 V, VIN > 26 V 0 mA
VC = 16.5 V, VIN > 26 V 0
Steady Fault mode. VC > 11.5 V 60
ANALOG
VC internal diode rating DVC_INT 100 V
INPUT
VC internal resistor RVC-INT N/A kΩ
VC internal resistor TVC_COEFF N/A ppm/°C
temperature coefficient
Start Up
VC start up pulse VVC_SP Tpeak <18 ms 20 V
VC slew rate dVC/dt Required for proper start up; 0.02 0.25 V/µs
VC inrush current IINR_VC VC = 16.5 V, dVC/dt = 0.25 V/µs 1 A
VC to VOUT turn-on delay TON VIN pre-applied, PC floating, 500 µs
VC enable, CPC = 0 µF
Transitional VC to PC delay Tvc_pc VC = 11.5 V to PC high, VIN = 0 V, 75 125 µs
dVC/dt = 0.25 V/µs
Internal VC capacitance CVC_INT VC = 0 V 3.2 µF
Used to wake up powertrain circuit.
A minimum of 11.5 V must be applied indefinitely for VIN < 26 V
to ensure normal operation.
VC slew rate must be within range for a successful start.
PRM™ module VC can be used as valid wake-up signal source.
Internal Resistance used in “Adaptive Loop” compensation
VC voltage may be continuously applied
VTM CONTROL : VC
3.0 SIGNAL CHARACTERISTICS
Specifications apply over all line and load conditions unless otherwise noted; Boldface specifications apply over the temperature
range of -40 °C < TJ< 125 °C (T-Grade); All other specifications are at TJ= 25 °C unless otherwise noted.
SIGNAL TYPE STATE ATTRIBUTE SYMBOL CONDITIONS / NOTES MIN TYP MAX UNIT
PC voltage VPC 4.7 5 5.3 V
ANALOG Steady PC source current IPC_OP 2 mA
OUTPUT PC resistance (internal) RPC_INT Internal pull down resistor 50 150 400 kΩ
Start Up
PC source current IPC_EN 50 100 300 µA
PC capacitance (internal) CPC_INT Section 7 1000 pF
PC resistance (external) RPC_S 60 kΩ
Enable PC voltage VPC_EN 2 2.5 3 V
DIGITAL Disable PC voltage (disable) VPC_DIS 2 V
INPUT / OUPUT
PC pull down current IPC_PD 5.1 mA
Transitional PC disable time TPC_DIS_T 5 µs
PC fault response time TFR_PC From fault to PC = 2 V 100 µs
The PC pin enables and disables the VTM™ module.
When held below 2 V, the VTM module will be disabled.
PC pin outputs 5 V during normal operation. PC pin is equal to 2.5 V
during fault mode given VIN > 26 V or VC > 11.5 V.
After successful start up and under no fault condition, PC can be used as
a 5 V regulated voltage source with a 2 mA maximum current.
Module will shutdown when pulled low with an impedance
less than 400 Ω.
In an array of VTM modules, connect PC pin to synchronize start up.
PC pin cannot sink current and will not disable other modules
during fault mode.
PRIMARY CONTROL : PC
SIGNAL TYPE STATE ATTRIBUTE SYMBOL CONDITIONS / NOTES MIN TYP MAX UNIT
IM Voltage (No Load) VIM_NL TJ= 25 ºC, VIN = 40 V, IOUT = 0 A 0.1 0.15 0.3 V
IM Voltage (50%) VIM_50% TJ= 25 ºC, VIN = 40 V, IOUT = 65 A 0.45 V
ANALOG Steady IM Voltage (Full Load) VIM_FL TJ= 25 ºC, VIN = 40 V, IOUT = 130 A 0.91 V
OUTPUT IM Gain AIM TJ= 25 ºC, VIN = 40 V, IOUT > 65 A 7 mV/A
IM Resistance (External) RIM_EXT 2.5 MΩ
The IM pin voltage varies between 0.1 V and 0.91 V representing the
output current within ±25% under all operating line temperature
conditions between 50% and 100%.
The IM pin provides a DC analog voltage proportional to
the output current of the VTM module.
CURRENT MONITOR : IM
I VICDH‘
Rev. 1.2
7/2012
Page 4 of 17
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
vicorpower.com
PRELIMINARY DATASHEET
VTM48EF012T130A01
SIGNAL TYPE STATE ATTRIBUTE SYMBOL CONDITIONS / NOTES MIN TYP MAX UNIT
TM voltage VTM_AMB TJcontroller = 27 °C 2.95 3.00 3.05 V
ANALOG TM source current ITM 100 µA
OUTPUT Steady TM gain ATM 10 mV/°C
TM voltage ripple VTM_PP CTM = 0 F, VIN = 40 V, 120 200 mV
IOUT = 130 A
Disable TM voltage VTM_DIS 0 V
DIGITAL OUTPUT TM resistance (internal) RTM_INT Internal pull down resistor 25 40 50 kΩ
Transitional TM capacitance (external) CTM_EXT 50 pF
(FAULT FLAG) TM fault response time TFR_TM From fault to TM = 1.5 V 10 µs
The TM pin monitors the internal temperature of the VTM controller IC
within an accuracy of ±5 °C.
Can be used as a "Power Good" flag to verify that
the VTM module is operating.
The TM pin has a room temperature setpoint of 3 V
and approximate gain of 10 mV/°C.
Output drives Temperature Shutdown comparator
TEMPERATURE MONITOR : TM
4.0 TIMING DIAGRAM
12
7
VIN
1. Initiated VC pulse
2. Controller start
3. VIN ramp up
4. VIN = VOVLO
5. VIN ramp down no VC pulse
6. Overcurrent
7. Start up on short circuit
8. PC driven low
VOUT
PC
3 V
VC
NL
5 V
VOVLO
TM
VTM-AMB
c
Notes:
– Timing and voltage is not to scale
– Error pulse width is load dependent
a: VC slew rate (dVC/dt)
b: Minimum VC pulse rate
c: TOVLO
d: TOCP
e: Output turn on delay (TON)
f: PC disable time (TPC_DIS_T)
g: VC to PC delay (TVC_PC)
d
ISSP
IOUT
IOCP
VVC-EXT
345
6
a
b
8
g
ef
≥ 26 V
/ J “Vi 4:1:12. ; F 5;??? + —I— + + + + ++++++
Rev. 1.2
7/2012
Page 5 of 17
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
vicorpower.com
VTM48EF012T130A01
5.0 APPLICATION CHARACTERISTICS
The following values, typical of an application environment, are collected at TC= 25 ºC unless otherwise noted. See associated
figures for general trend data.
ATTRIBUTE SYMBOL CONDITIONS / NOTES TYP UNIT
No load power dissipation PNL VIN = 40 V, PC enabled 2.1 W
Efficiency (ambient) ηAMB VIN = 40 V, IOUT = 130 A 90.3 %
Efficiency (hot) ηHOT VIN = 40 V, IOUT = 130 A, TC= 100 ºC 88.7 %
Output resistance (cold) ROUT_COLD VIN = 40 V, IOUT = 130 A, TC= -40 ºC 0.5 mΩ
Output resistance (ambient) ROUT_AMB VIN = 40 V, IOUT = 130 A 0.6 mΩ
Output resistance (hot) ROUT_HOT VIN = 40 V, IOUT = 130 A, TC= 100 ºC 0.8 mΩ
Output voltage ripple VOUT_PP COUT = 0 F, IOUT = 130 A, VIN = 40 V,
142 mV
20 MHz BW, Section 12
VOUT transient (positive) VOUT_TRAN+IOUT_STEP = 0 A TO 130 A, VIN = 40 V,
40 mV
ISLEW = 36 A /us
VOUT transient (negative) VOUT_TRAN-IOUT_STEP = 130 A to 0 A, VIN = 40 V
60 mV
ISLEW = 23 A /us
No Load Power Dissipation vs. Line Voltage
Input Voltage (V)
Power Dissipation (W)
-40 °C 25 °C 100 °C
T :
CASE
1
2
3
4
5
6
26 29 32 35 38 41 43 46 49 52 55
Full Load Efficiency vs. TCASE
Case Temperature (°C)
Full Load Efficiency (%)
26 V 42 V 55 V
V :
IN
80
82
84
86
88
90
92
94
-40 -20 0 20 40 60 80 100
Efficiency & Power Dissipation -40 °C Case
Load Current (A)
Efficiency (%)
Power Dissipation (W)
26 V 42 V 55 V
V :
IN 26 V 42 V 55 V
72
76
80
84
88
92
96
0 153045607590105120135150
0
4
8
12
16
20
24
28
32
36
40
44
48
η
PD
Efficiency & Power Dissipation 25 °C Case
Load Current (A)
Efficiency (%)
Power Dissipation (W)
26 V 42 V 55 V
V :
IN 26 V 42 V 55 V
72
76
80
84
88
92
96
0 15 30 45 60 75 90 105 120 135 150
0
4
8
12
16
20
24
28
32
36
40
44
48
η
PD
Figure 1 — No load power dissipation vs. VIN Figure 2 — Full load efficiency vs. temperature
Figure 3 — Efficiency and power dissipation at –40 °C Figure 4 — Efficiency and power dissipation at 25 °C
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Rev. 1.2
7/2012
Page 6 of 17
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
vicorpower.com
PRELIMINARY DATASHEET
VTM48EF012T130A01
Figure 10 Start up from application of VIN ;
VC pre-applied COUT = 64400 µF
Output Current (A)
Safe Operating Area
Output Voltage (V)
0
20
40
60
80
100
120
140
160
180
200
220
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
< 30°C TCASE, 150 A Maximum Current Region
130 A Maximum Current Region
< 10 ms, 195 A Maximum Current Region
Limited by Power
Limited by ROUT
Limited by Power
< 10 ms, 195 A Maximum Current
< 30°C TCASE, 150 A Maximum Current
130 A Maximum Current Region
Figure 8 Safe operating area
Figure 9 Full load ripple, 100 µF CIN; No external COUT.Board
mounted module, scope setting : 20 MHz analog BW
Output Voltage Ripple vs. Load
Load Current (A)
V
RIPPLE
(mV
PK-PK
)
V :
IN 26 V 42 V 55 V
0
25
50
75
100
125
150
175
0 13 26 39 52 65 78 91 104 117 130
Figure 7 — VRIPPLE vs. IOUT ; No external COUT.Board mounted
module, scope setting: 20 MHz analog BW
Efficiency & Power Dissipation 100 °C Case
Load Current (A)
Efficiency (%)
Power Dissipation (W)
26 V 42 V 55 V
V :
IN 26 V 42 V 55 V
72
76
80
84
88
92
96
0 13263952657891104117130
0
4
8
12
16
20
24
28
32
36
40
44
48
η
PD
Case Temperature (ºC)
R
OUT
(mΩ)
ROUT vs. TCASE at VIN = 42 V
I :
OUT 65 A 130 A
0.40
0.45
0.50
0.55
0.60
0.65
0.70
0.75
0.80
-40 -20 0 20 40 60 80 100
Figure 5 — Efficiency and power dissipation at 100°C Figure 6 — ROUT vs. temperature
CH1 CH2 ‘ CH3 CH4 CH1 vc 7 o VIdIv CH3 vm,r 2 0 wmv Timehase 2 msldlv CH2 PC 5 0 V/dlv CH4 I.N a o A/div memwwwwwmwmmw WWWWWWWW Tlmebase 5 psldlv CH2 CH1 CH1 v0”. 200 mV/dlv CH2 low: so Aldw WHWWWW‘ CH1 v0”. 200 mVIdIv CH2 IoUT 50Aldw Tlmebase 5 us/dlv VIC
Rev. 1.2
7/2012
Page 7 of 17
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
vicorpower.com
VTM48EF012T130A01
Figure 13 — 130 A 0 A transient response:
CIN = 100 µF, no external COUT
Figure 12 0 A – 130 A transient response:
CIN = 100 µF, no external COUT
Figure 11 — Start up from application of VC;
VIN pre-applied COUT = 64400 µF
Load Current (A)
IM Voltage vs. Load at VIN = 42
IM (V)
T :
CASE -40 °C 25 °C 100 °C
0.00
0.25
0.50
0.75
1.00
1.25
13 26 39 52 65 78 91
104 117 130
Figure 14 IM voltage vs. load
TCASE (°C)
IM Voltage at 130 A Load vs. TCASE
IM (V)
V :
IN 26 V 42 V 55 V
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
-40 -20 0 20 40 60 80 100
Figure 16 Full load IM voltage vs. TCASE
Load Current (A)
IM voltage vs. Load at 25 °C Case
IM (V)
V :
IN -40 °C 25 °C 100 °C
13 26 39 52 65 78 91
104 117 130
0.0
0.3
0.5
0.8
1.0
Figure 15 IM voltage vs. load
32,25/[1 270] 21,75 / [0 355] 6,43 / [0 255] 32,5/[1130] 22,0 / [0.866] 6,73/[0165] 1 ] 4.31 ”0,294 14,5 / [0,512 32 75/ [1.239] 22 25/ [0.375] 5 93/ [0.275] VIC
Rev. 1.2
7/2012
Page 8 of 17
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
vicorpower.com
PRELIMINARY DATASHEET
VTM48EF012T130A01
ATTRIBUTE SYMBOL CONDITIONS / NOTES MIN TYP MAX UNIT
MECHANICAL
Length L 32.25 / [1.270] 32.5 / [1.280] 32.75 / [1.289] mm/[in]
Width W 21.75 / [0.856] 22.0 / [0.866] 22.25 / [0.876] mm/[in]
Height H 6.48 / [0.255] 6.73 / [0.265] 6.98 / [0.275] mm/[in]
Volume Vol No heat sink 4.81 / [0.294] cm3/[in3]
Weight W 14.5 / [0.512] g/[oz]
Nickel 0.51 2.03
Lead finish Palladium 0.02 0.15 µm
Gold 0.003 0.051
THERMAL
VTM48EF012T130A01 (T-Grade) -40 125 °C
Operating temperature TJ VTM48EF012M130A01 (M-Grade) N/A N/A °C
Thermal resistance φJC Isothermal heatsink and
1 °C/W
isothermal internal PCB
Thermal capacity 9 Ws/°C
ASSEMBLY
Peak compressive force Supported by J-lead only 6 lbs
applied to case (Z-axis) 5.41 lbs / in2
VTM48EF012T130A01 (T-Grade) -40 125 °C
Storage temperature TST VTM48EF012M130A01 (M-Grade) N/A N/A °C
Moisture sensitivity level MSL MSL 6, TOB = 4 hrs
MSL 5
ESDHBM
1000
ESD withstand
ESDCDM
400
VDC
SOLDERING
Peak temperature during reflow MSL 6, TOB = 4 hrs 245 °C
MSL 5 225 °C
Peak time above 245 °C 60 90 s
Peak heating rate during reflow 1.5 3 °C/s
Peak cooling rate post reflow 1.5 6 °C/s
SAFETY
Working voltage (IN – OUT) VIN_OUT 60 VDC
Isolation voltage (hipot) VHIPOT Applies to product built after
April, 2012 (post datecode 1219)
1500 VDC
Isolation capacitance CIN_OUT Unpowered unit 18000 20000 22000 pF
Isolation resistance RIN_OUT 10 MΩ
MTBF
MIL-HDBK-217 Plus Parts Count;
1.56 MHrs25ºC Ground Benign, Stationary,
Indoors / Computer Profile
Telcordia Issue 2 - Method I Case III; 5.44 MHrs
Ground Benign, Controlled
cTUVus
Agency approvals / standards cURus
CE Marked for Low Voltage Directive and RoHS Recast Directive, as applicable
Human Body Model,
"JEDEC JESD 22-A114D"
Charge Device Model,
"JEDEC JESD 22-C101-D"
6.0 GENERAL CHARACTERISTICS
Specifications apply over all line and load conditions unless otherwise noted; Boldface specifications apply over the temperature
range of -40 ºC < TJ< 125 ºC (T-Grade); All Other specifications are at TJ= 25 °C unless otherwise noted.
Rev. 1.2
7/2012
Page 9 of 17
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
vicorpower.com
VTM48EF012T130A01
7.0 USING THE CONTROL SIGNALS VC, PC, TM, IM
The VTM Control (VC) pin is an input pin which powers the
internal VCC circuitry when within the specified voltage range
of 11.5 V to 16.5 V. This voltage is required for VTM™ current
multiplier start up and must be applied as long as the input is
below 26 V. In order to ensure a proper start, the slew rate of
the applied voltage must be within the specified range.
Some additional notes on the using the VC pin:
In most applications, the VTM module will be powered
by an upstream PRM™ regulator which provides a 10 ms
VC pulse during start up. In these applications the VC pins
of the PRM module and VTM module should be tied together.
The VC voltage can be applied indefinitely allowing for
continuous operation down to 0 VIN.
The fault response of the VTM module is latching.
A positive edge on VC is required in order to restart the unit.
If VC is continuously applied the PC pin may be toggled to
restart the VTM module.
Primary Control (PC) pin can be used to accomplish the
following functions:
Delayed start: Upon the application of VC, the PC pin will
source a constant 100 µA current to the internal RC
network. Adding an external capacitor will allow further
delay in reaching the 2.5 V threshold for module start.
Auxiliary voltage source: Once enabled in regular
operational conditions (no fault), each VTM PC provides a
regulated 5 V, 2 mA voltage source.
Output disable: PC pin can be actively pulled down in order
to disable the module. Pull down impedance shall be lower
than 400 Ω.
Fault detection flag: The PC 5 V voltage source is internally
turned off as soon as a fault is detected. It is important to
notice that PC doesn’t have current sink capability. Therefore,
in an array, PC line will not be capable of disabling
neighboring modules if a fault is detected.
Fault reset: PC may be toggled to restart the unit if VC
is continuously applied.
Temperature Monitor (TM) pin provides a voltage
proportional to the absolute temperature of the converter
control IC.
It can be used to accomplish the following functions:
Monitor the control IC temperature: The temperature in
Kelvin is equal to the voltage on the TM pin scaled
by 100. (i.e. 3.0 V = 300 K = 27 ºC). If a heat sink is applied,
TM can be used to thermally protect the system.
Fault detection flag: The TM voltage source is internally
turned off as soon as a fault is detected. For system
monitoring purposes (microcontroller interface) faults are
detected on falling edges of TM signal.
Current Monitor (IM) pin provides a voltage proportional to
the output current of the VTM module. The nominal voltage
will vary between 0.15 V and 0.91 V over the output current
range of the VTM module (See Figures 14–16). The accuracy of
the IM pin will be within 25% under all line and temperature
conditions between 50% and 100% load.
8.0 START UP BEHAVIOR
Depending on the sequencing of the VC with respect to the
input voltage, the behavior during start up will vary as follows:
Normal operation (VC applied prior to VIN): In this case the
controller is active prior to ramping the input. When the
input voltage is applied, the VTM module output voltage
will track the input (See Figure 10). The inrush current is
determined by the input voltage rate of rise and output
capacitance. If the VC voltage is removed prior to the input
reaching 26 V, the VTM may shut down.
Stand-alone operation (VC applied after VIN): In this case the
VTM module output will begin to rise upon the application
of the VC voltage (See Figure 11). The Adaptive Soft Start
Circuit (See Section 11) may vary the ouput rate of rise in
order to limit the inrush current to its maximum level. When
starting into high capacitance, or a short, the output current
will be limited for a maximum of 120 µ/sec. After this period,
the Adaptive Soft Start Circuit will time out and the VTM
module may shut down. No restart will be attempted until
VC is re-applied or PC is toggled. The maximum output
capacitance is limited to 64400 µF in this mode of operation
to ensure a sucessful start.
9.0 THERMAL CONSIDERATIONS
VI Chip®products are multi-chip modules whose temperature
distribution varies greatly for each part number as well as with
the input / output conditions, thermal management and
environmental conditions. Maintaining the top of the
VTM48EF012T130A01 case to less than 100 ºC will keep all
junctions within the VI Chip®module below 125 ºC for most
applications.
The percent of total heat dissipated through the top surface
versus through the J-lead is entirely dependent on the
particular mechanical and thermal environment. The heat
dissipated through the top surface is typically 60%. The heat
dissipated through the J-lead onto the PCB board surface is
typically 40%. Use 100% top surface dissipation when
designing for a conservative cooling solution.
It is not recommended to use a VI Chip®module for an extended
period of time at full load without proper heat sinking.
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Rev. 1.2
7/2012
Page 10 of 17
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
vicorpower.com
PRELIMINARY DATASHEET
VTM48EF012T130A01
+VIN
PC
Temperature
Dependent
Voltage Source
2.5 V
100 A
5 V
40 K
1000 pF
10.5 V
3.1 V
Single Ended
Primary
Current Sensing
VREF
(127°C)
Enable
Synchronous
Rectification
Primary Stage &
Resonant Tank
PC Pull-Up
& Source
Over
Temperature
Protection
VC
IM
CIN
18 V
Power
Transformer
Q1
Q2
C1
C2
Q3
Primary
Gate
Drive
Secondary
Gate Drive
3 VMAX
240 AMAX
Gate Drive
Supply
Regulator
Supply
Enable
Adaptive
Soft Start
Enable
Q4
Cr Lr
VREF
0.01 F
1 K
2 mA
Modulator
Enable
150 K
VDD
DVC_INT
RVC_INT
-VIN
VIN
OVLO
UVLO Fault Logic
COUT
Left
J-lead
Right
J-lead
COUT
+VOUT
-VOUT
+VOUT
-VOUT
102
TM
10.0 VTM™ MODULE BLOCK DIAGRAM
:3
Rev. 1.2
7/2012
Page 11 of 17
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VTM48EF012T130A01
11.0 SINE AMPLITUDE CONVERTERTM POINT OF LOAD CONVERSION
The Sine Amplitude Converter (SAC™) uses a high frequency
resonant tank to move energy from input to output. (The
resonant tank is formed by Cr and leakage inductance Lr in the
power transformer windings as shown in the VTM™ Module
Block Diagram. See Section 10). The resonant LC tank,
operated at high frequency, is amplitude modulated as a
function of input voltage and output current. A small amount
of capacitance embedded in the input and output stages of
the module is sufficient for full functionality and is key to
achieving power density.
The VTM48EF012T130A01 SAC can be simplified into the
following model:At no load:
VOUT = VIN K (1)
K represents the “turns ratio” of the SAC.
Rearranging Eq (1):
K= VOUT (2)
VIN
In the presence of load, VOUT is represented by:
VOUT = VIN K – IOUT ROUT (3)
and IOUT is represented by:
IOUT =IIN –I
Q(4)
K
ROUT represents the impedance of the SAC, and is a function of
the RDSON of the input and output MOSFETs and the winding
resistance of the power transformer. IQrepresents the
quiescent current of the SAC control and gate drive circuitry.
The use of DC voltage transformation provides additional
interesting attributes. Assuming that ROUT = 0 Ωand IQ= 0 A,
Eq. (3) now becomes Eq. (1) and is essentially load
independent, resistor R is now placed in series with VIN as
shown in Figure 18.
The relationship between VIN and VOUT becomes:
VOUT = (VIN –I
IN R) K (5)
Substituting the simplified version of Eq. (4)
(IQis assumed = 0 A) into Eq. (5) yields:
VOUT = VIN K – IOUT R K2(6)
+
+
VOUT
COUT
VIN
V•I
K
+
+
CIN
IOUT
RCOUT
IQ
ROUT
RCIN
LIN = 5 nH
55 mA
1/40 • IOUT 1/40 • VIN
0.62 mΩ
RCIN
6.3 mΩ
78 pH
0.062 ΩRCOUT
65 µΩ
350 µF
LOUT = 150 pH
885 nF
IQ
LIN = 3.7 nH IOUT ROUT
VIN VOUT
R
SAC
K = 1/32
Vin Vout
+
VIN VOUT
R
SAC™
K = 1/40
Figure 18 – K = 1/40 Sine Amplitude Converter with series
input resistor
Figure 17 — VI Chip®product AC model
COUT
CIN
r \ RouT
Rev. 1.2
7/2012
Page 12 of 17
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
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PRELIMINARY DATASHEET
VTM48EF012T130A01
This is similar in form to Eq. (3), where ROUT is used to
represent the characteristic impedance of the SAC™. However,
in this case a real R on the input side of the SAC is effectively
scaled by K2with respect to the output.
Assuming that R = 1 Ω, the effective R as seen from the secondary
sideis 0.63 mΩ,withK= 1/40 as shown in Figure 18.
A similar exercise should be performed with the addition of a
capacitor or shunt impedance at the input to the SAC.
A switch in series with VIN is added to the circuit. This is
depicted in Figure 19.
A change in VIN with the switch closed would result in a
change in capacitor current according to the following
equation:
IC(t) = C dVIN (7)
dt
Assume that with the capacitor charged to VIN, the switch is
opened and the capacitor is discharged through the idealized
SAC. In this case,
IC=I
OUT K (8)
Substituting Eq. (1) and (8) into Eq. (7) reveals:
IOUT =CdVOUT (9)
K2dt
The equation in terms of the output has yielded a K2scaling
factor for C, specified in the denominator of the equation.
A K factor less than unity, results in an effectively larger
capacitance on the output when expressed in terms of the
input. With a K= 1/40 as shown in Figure 19, C=1 µF would
appear as C= 1600 µF when viewed
from the output.
Low impedance is a key requirement for powering a high-
current, low voltage load efficiently. A switching regulation
stage should have minimal impedance while simultaneously
providing appropriate filtering for any switched current. The
use of a SAC between the regulation stage and the point of
load provides a dual benefit of scaling down series impedance
leading back to the source and scaling up shunt capacitance or
energy storage as a function of its K factor squared. However,
the benefits are not useful if the series impedance of the SAC
is too high. The impedance of the SAC must be low, i.e. well
beyond the crossover frequency of the system.
A solution for keeping the impedance of the SAC low involves
switching at a high frequency. This enables small magnetic
components because magnetizing currents remain low. Small
magnetics mean small path lengths for turns. Use of low loss
core material at high frequencies also reduces core losses.
The two main terms of power loss in the VTMTM module are:
-No load power dissipation (PNL): defined as the power
used to power up the module with an enabled powertrain
at no load.
-Resistive loss (ROUT): refers to the power loss across
the VTMTM current multiplier modeled as pure resistive
impedance.
PDISSIPATED = PNL + PROUT (10)
Therefore,
POUT = PIN –P
DISSIPATED = PIN –P
NL –P
ROUT (11)
The above relations can be combined to calculate the overall
module efficiency:
η=POUT =PIN –P
NL –P
ROUT (12)
PIN PIN
=VIN IIN –P
NL –(I
OUT)2ROUT
VIN IIN
=1
(
PNL + (IOUT)2ROUT
)
VIN IIN
C
S
SAC
K = 1/32
Vin Vout
+
VIN VOUT
C
SACTM
K = 1/40
Figure 19 — Sine Amplitude Converter™ with input capacitor
S
Rev. 1.2
7/2012
Page 13 of 17
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
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VTM48EF012T130A01
12.0 INPUT AND OUTPUT FILTER DESIGN
A major advantage of a SAC™ system versus a conventional
PWM converter is that the former does not require large
functional filters. The resonant LC tank, operated at extreme
high frequency, is amplitude modulated as a function of input
voltage and output current and efficiently transfers charge
through the isolation transformer. A small amount of
capacitance embedded in the input and output stages of the
module is sufficient for full functionality and is key to achieving
high power density.
This paradigm shift requires system design to carefully evaluate
external filters in order to:
1.Guarantee low source impedance.
To take full advantage of the VTM™ current multiplier
dynamic response, the impedance presented to its input
terminals must be low from DC to approximately 5 MHz.
Input capacitance may be added to improve transient
performance or compensate for high source impedance.
2.Further reduce input and/or output voltage ripple without
sacrificing dynamic response.
Given the wide bandwidth of the VTM module, the source
response is generally the limiting factor in the overall
system response. Anomalies in the response of the source
will appear at the output of the VTM module multiplied by
its K factor.
3.Protect the module from overvoltage transients imposed
by the system that would exceed maximum ratings and
cause failures.
The VI Chip®module input/output voltage ranges must
not be exceeded. An internal overvoltage lockout function
prevents operation outside of the normal operating input
range. Even during this condition, the powertrain is
exposed to the applied voltage and power MOSFETs must
withstand it.
13.0 CAPACITIVE FILTERING CONSIDERATIONS
FOR A SINE AMPLITUDE CONVERTERTM
It is important to consider the impact of adding input and
output capacitance to a Sine Amplitude Converter on the
system as a whole. Both the capacitance value and the
effective impedance of the capacitor must be considered.
A Sine Amplitude Converter has a DC ROUT value which has
already been discussed in section 11. The AC ROUT of the
SAC contains several terms:
Resonant tank impedance
Input lead inductance and internal capacitance
Output lead inductance and internal capacitance
The values of these terms are shown in the behavioral model in
section 11. It is important to note on which side of the
transformer these impedances appear and how they reflect
across the transformer given the K factor.
The overall AC impedance varies from model to model. For
most models it is dominated by DC ROUT value from DC to
beyond 500 KHz. The behavioral model in section 11 should be
used to approximate the AC impedance of the specific model.
Any capacitors placed at the output of the VTM reflect back to
the input of the VTM module by the square of the K factor (Eq.
9) with the impedance of the VTM module appearing in series.
It is very important to keep this in mind when using a PRM™
regulator to power the VTM module. Most PRM modules have
a limit on the maximum amount of capacitance that can be
applied to the output. This capacitance includes both the PRM
output capacitance and the VTM module output capacitance
reflected back to the input. In PRM remote sense applications,
it is important to consider the reflected value of VTM module
output capacitance when designing and compensating the
PRM control loop.
Capacitance placed at the input of the VTM module appear to
the load reflected by the K factor with the impedance of the
VTM module in series. In step-down ratios, the effective
capacitance is increased by the K factor. The effective ESR of
the capacitor is decreased by the square of the K factor, but
the impedance of the module appears in series. Still, in most
step-down VTM modules an electrolytic capacitor placed at the
input of the module will have a lower effective impedance
compared to an electrolytic capacitor placed at the output. This
is important to consider when placing capacitors at the output
of the module. Even though the capacitor may be placed at
the output, the majority of the AC current will be sourced from
the lower impedance, which in most cases will be the module.
This should be studied carefully in any system design using a
module. In most cases, it should be clear that electrolytic
output capacitors are not necessary to design a stable,
well-bypassed system.
For further detafls see AN:016 Using BCMQ Bus Converters in H\ h Power Arra s
Rev. 1.2
7/2012
Page 14 of 17
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
vicorpower.com
PRELIMINARY DATASHEET
VTM48EF012T130A01
VIN VOUT
+
DC
ZIN_EQ1
ZIN_EQ2
ZOUT_EQ1
ZOUT_EQ2
Load
VTM™1
RO_1
VTM™2
RO_2
VTM™n
RO_n
ZOUT_EQn
ZIN_EQn
Figure 20 — VTM™ current multiplier array
14.0 CURRENT SHARING
The SAC™ topology bases its performance on efficient transfer
of energy through a transformer without the need of closed
loop control. For this reason, the transfer characteristic can be
approximated by an ideal current multiplier with some resistive
drop and positive temperature coefficient.
This type of characteristic is close to the impedance
characteristic of a DC power distribution system, both in
behavior (AC dynamic) and absolute value (DC dynamic).
When connected in an array with the same K factor, the VTM
module will inherently share the load current (typically 5%)
with parallel units according to the equivalent impedance
divider that the system implements from the power source to
the point of load.
Some general recommendations to achieve matched array
impedances:
Dedicate common copper planes within the PCB
to deliver and return the current to the modules.
Provide the PCB layout as symmetric as possible.
Apply same input / output filters (if present) to each unit.
For further details see AN:016 Using BCM® Bus Converters
in High Power Arrays.
15.0 FUSE SELECTION
In order to provide flexibility in configuring power systems
VI Chip®products are not internally fused. Input line fusing
of VI Chip®products is recommended at system level to provide
thermal protection in case of catastrophic failure.
The fuse shall be selected by closely matching system
requirements with the following characteristics:
Current rating (usually greater than maximum current
of VTM module)
Maximum voltage rating (usually greater than the maximum
possible input voltage)
Ambient temperature
Nominal melting I2t
16.0 REVERSE INRUSH CURRENT PROTECTION
The VTM48EF012T130A01 provides reverse inrush protection
which prevents reverse current flow until the input voltage is
high enough to first establish current flow in the forward
direction. In the event that there is a DC voltage present on the
output before the VTM module is powered up, this feature
protects sensitive loads from excessive dV/dT during power up
as shown in Figure 21.
If a voltage is present at the output of the VTM module which
satisfies the condition VOUT > VIN • K after a successful power
up the energy will be transferred from secondary to primary.
The input to output ratio of the VTM module will be
maintained. The VTM module will continue to operate in
reverse as long as the input and output voltages are within the
specified range. The VTM48EF012T130A01 has not been
qualified for continuous reverse operation.
VC
VIN
Supply
TM
PC
VOUT
VIN
VOUT
Supply
ABCD EFG H
A: VOUT supply > 0 V
B: VC to -IN > 11.5 V controller wakes-up, PC & TM pulled
high, reverse inrush protection blocks VOUT supplying VIN
C: VIN supply ramps up
D: VIN > VOUT /K, powertrain starts in normal mode
E: VIN supply ramps down
F: VIN > VOUT /K, powertrain transfers reverse energy
G: VOUT ramps down, VIN follows
H: VC turns off
R
VIN
R
Supply
+
_
PC
VC
TM
-Out
+Out
-In
+In
IM
VTM™
Current Multiplier
Figure 21 — Reverse inrush protection
shields the signais. See AN2005 FPA Printed Circuit Board Layout Guidelines an O
Rev. 1.2
7/2012
Page 15 of 17
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
vicorpower.com
VTM48EF012T130A01
17.0 LAYOUT CONSIDERATIONS
The VTM48EF012T130A01 requires equal current density along
the output J-leads to achieve rated efficiency and output power
level. The negative output J-leads are not connected internally
and must be connected on the board as close to the VTMT™
current multiplier as possible. The layout must also prevent the
high output current of the VTM48EF012T130A01 from
interfering with the input-referenced signals.
To achieve these requirements, the following layout guidelines
are recommended:
The total current path length from any point on the V+OUT
J-leads to the corresponding point on the V-OUT J-leads should
be equal (see Figure 22) .
Use vias along the negative output J-leads to connect the
negative output to a common power plane.
Use sufficient copper weight and number of layers to carry
the output current to the load or to the output connectors.
Be sure to include enough vias along both the positive and
negative J leads to distribute the current among the layers
of the PCB.
Do not run input-referenced signal traces (VC, PC, TM
and IM) between the layers of the secondary outputs.
Run the input-referenced signal traces (VC, PC, TM and IM)
such that V-IN shields the signals. See AN:005 FPA Printed
Circuit Board Layout Guidelines for more details.
Equalizing the current paths is most easily accomplished by
centering the VTM module output J-leads between the output
connections of the PCB and by designing the board such that
the layout is symmetric from both sides of the output and from
the front and back ends of the output as shown in Figures 23
and 24.
Figure 22 — Equal current path
Figure 23 — Symmetric layout
Figure 24 — Symmetric layout
TOP VIEW (COMPONENT SIDE) BOTTOM VIEW 22.0 “m m E a 5 11.0 n m u m rrw‘fl mm H H . ‘ msmmfl F < 3="" ,="" 3="" loan="" 2="" h="" 2="" h="" (a:="" fl.="" m="" chck="" here="" to="" view="" omgma‘="" weehencz‘="" drawing="" on="" the="" vwmr="" webswte="">
Rev. 1.2
7/2012
Page 16 of 17
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
vicorpower.com
PRELIMINARY DATASHEET
VTM48EF012T130A01
inch
mm
NOTES:
1. DIMENSIONS ARE .
2. UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE:
.X / [.XX] = +/-0.25 / [.01]; .XX / [.XXX] = +/-0.13 / [.005]
3. PRODUCT MARKING ON TOP SURFACE
DXF and PDF files are available on vicorpower.com
17.1 MECHANICAL DRAWING
inch
mm
NOTES:
1. DIMENSIONS ARE .
2. UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE:
.X / [.XX] = +/-0.25 / [.01]; .XX / [.XXX] = +/-0.13 / [.005]
3. PRODUCT MARKING ON TOP SURFACE
DXF and PDF files are available on vicorpower.com
17.2 RECOMMENDED LAND PATTERN
Bottom View
4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
Signal
Name Designation
+In M2, M1
–In M4, M3
IM N3
TM N4
VC N2
PC N1
+Out A3-L3, A2-L2
–Out A4-L4, A1-L1
Click here to view original mechanical drawing on the Vicor website.
Customer Service: (ustserv@vlcorgower,com Technica‘ Support: appsfivlcorpowemom VICD
Rev. 1.2
7/2012
Page 17 of 17
VI CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
vicorpower.com
VTM48EF012T130A01
Vicor’s comprehensive line of power solutions includes high density AC-DC and DC-DC modules and
accessory components, fully configurable AC-DC and DC-DC power supplies, and complete custom power
systems.
Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for its use. Vicor makes no
representations or warranties with respect to the accuracy or completeness of the contents of this publication. Vicor reserves the right to make changes
to any products, specifications, and product descriptions at any time without notice. Information published by Vicor has been checked and is believed to
be accurate at the time it was printed; however, Vicor assumes no responsibility for inaccuracies. Testing and other quality controls are used to the extent
Vicor deems necessary to support Vicor’s product warranty. Except where mandated by government requirements, testing of all parameters of each
product is not necessarily performed.
Specifications are subject to change without notice.
Vicor’s Standard Terms and Conditions
All sales are subject to Vicor’s Standard Terms and Conditions of Sale, which are available on Vicor’s webpage or upon request.
Product Warranty
In Vicor’s standard terms and conditions of sale, Vicor warrants that its products are free from non-conformity to its Standard Specifications (the “Express
Limited Warranty”). This warranty is extended only to the original Buyer for the period expiring two (2) years after the date of shipment and is not
transferable.
UNLESS OTHERWISE EXPRESSLY STATED IN A WRITTEN SALES AGREEMENT SIGNED BY A DULY AUTHORIZED VICOR SIGNATORY, VICOR DISCLAIMS ALL
REPRESENTATIONS, LIABILITIES, AND WARRANTIES OF ANY KIND (WHETHER ARISING BY IMPLICATION OR BY OPERATION OF LAW) WITH RESPECT TO
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PURPOSE, INFRINGEMENT OF ANY PATENT, COPYRIGHT, OR OTHER INTELLECTUAL PROPERTY RIGHT, OR ANY OTHER MATTER.
This warranty does not extend to products subjected to misuse, accident, or improper application, maintenance, or storage. Vicor shall not be liable for
collateral or consequential damage. Vicor disclaims any and all liability arising out of the application or use of any product or circuit and assumes no
liability for applications assistance or buyer product design. Buyers are responsible for their products and applications using Vicor products and
components. Prior to using or distributing any products that include Vicor components, buyers should provide adequate design, testing and operating
safeguards.
Vicor will repair or replace defective products in accordance with its own best judgment. For service under this warranty, the buyer must contact Vicor to
obtain a Return Material Authorization (RMA) number and shipping instructions. Products returned without prior authorization will be returned to the
buyer. The buyer will pay all charges incurred in returning the product to the factory. Vicor will pay all reshipment charges if the product was defective
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VICOR’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR
WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL COUNSEL OF VICOR CORPORATION. As used herein, life support devices or
systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly
used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical
component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
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Vicor and its subsidiaries own Intellectual Property (including issued U.S. and Foreign Patents and pending patent applications) relating to the products
described in this data sheet. No license, whether express, implied, or arising by estoppel or otherwise, to any intellectual property rights is granted by this
document. Interested parties should contact Vicor's Intellectual Property Department.
The products described on this data sheet are protected by the following U.S. Patents Numbers:
5,945,130; 6,403,009; 6,710,257; 6,911,848; 6,930,893; 6,934,166; 6,940,013; 6,969,909; 7,038,917; 7,145,186; 7,166,898; 7,187,263;
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email
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