STM32L15xx(6, 8, B) Datasheet by STMicroelectronics

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This is information on a product in full production.
April 2016 DocID17659 Rev 12 1/133
STM32L151x6/8/B
STM32L152x6/8/B
Ultra-low-power 32-bit MCU ARM®-based Cortex®-M3,
128KB Flash, 16KB SRAM, 4KB EEPROM, LCD, USB, ADC, DAC
Datasheet - production data
Features
Ultra-low-power platform
1.65 V to 3.6 V power supply
-40°C to 85°C/105°C temperature range
0.3 µA Standby mode (3 wakeup pins)
0.9 µA Standby mode + RTC
0.57 µA Stop mode (16 wakeup lines)
1.2 µA Stop mode + RTC
9 µA Low-power run mode
214 µA/MHz Run mode
10 nA ultra-low I/O leakage
< 8 µs wakeup time
Core: ARM® Cortex®-M3 32-bit CPU
From 32 kHz up to 32 MHz max
1.25 DMIPS/MHz (Dhrystone 2.1)
Memory protection unit
Reset and supply management
Ultra-safe, low-power BOR (brownout
reset) with 5 selectable thresholds
Ultra-low-power POR/PDR
Programmable voltage detector (PVD)
Clock sources
1 to 24 MHz crystal oscillator
32 kHz oscillator for RTC with calibration
High Speed Internal 16 MHz factory-
trimmed RC (+/- 1%)
Internal low-power 37 kHz RC
Internal multispeed low-power 65 kHz to
4.2 MHz
PLL for CPU clock and USB (48 MHz)
Pre-programmed bootloader
USART supported
Development support
Serial wire debug supported
JTAG and trace supported
Up to 83 fast I/Os (73 I/Os 5V tolerant), all
mappable on 16 external interrupt vectors
Memories
Up to 128 Kbytes Flash memory with ECC
Up to 16 Kbytes RAM
Up to 4 Kbytes of true EEPROM with ECC
80-byte backup register
LCD Driver (except STM32L151x/6/8/B
devices) for up to 8x40 segments
Support contrast adjustment
Support blinking mode
Step-up converter on board
Rich analog peripherals (down to 1.8 V)
12-bit ADC 1 Msps up to 24 channels
12-bit DAC 2 channels with output buffers
2x ultra-low-power-comparators
(window mode and wake up capability)
DMA controller 7x channels
8x peripheral communication interfaces
1x USB 2.0 (internal 48 MHz PLL)
3x USARTs (ISO 7816, IrDA)
2x SPIs 16 Mbit/s
2x I2Cs (SMBus/PMBus)
10x timers: 6x 16-bit with up to 4 IC/OC/PWM
channels, 2x 16-bit basic timers, 2x watchdog
timers (independent and window)
Up to 20 capacitive sensing channels
supporting touchkey, linear and rotary touch
sensors
CRC calculation unit, 96-bit unique ID
Table 1. Device summary
Reference Part number
STM32L151x6/8/B
STM32L151CB, STM32L151C8,
STM32L151C6, STM32L151RB,
STM32L151R8, STM32L151R6,
STM32L151VB, STM32L151V8
STM32L152x6/8/B
STM32L152CB, STM32L152C8,
STM32L152C6, STM32L152RB,
STM32L152R8, STM32L152R6,
STM32L152VB, STM32L152V8
LQFP100 14 × 14 mm
LQFP64 10 × 10 mm
LQFP48 7 × 7 mm
UFBGA100 7 × 7 mm
TFBGA64 5 × 5 mm
UFQFPN48 7 × 7 mm
www.st.com
Contents STM32L151x6/8/B STM32L152x6/8/B
2/133 DocID17659 Rev 12
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.2 Ultra-low-power device continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.1 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.2 Shared peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.3 Common system strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 ARM® Cortex®-M3 core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3 Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.3.4 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5 Low power real-time clock and backup registers . . . . . . . . . . . . . . . . . . . 23
3.6 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.7 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.8 DMA (direct memory access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.9 LCD (liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.10 ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.10.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.10.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.11 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.12 Ultra-low-power comparators and reference voltage . . . . . . . . . . . . . . . . 26
3.13 Routing interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.14 Touch sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.15 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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3.15.1 General-purpose timers (TIM2, TIM3, TIM4, TIM9, TIM10 and TIM11) . 28
3.15.2 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.15.3 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.15.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.15.5 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.16 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.16.1 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.16.2 Universal synchronous/asynchronous receiver transmitter (USART) . . 29
3.16.3 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.16.4 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.17 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 30
3.18 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.1.7 Optional LCD power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.1.8 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.3.2 Embedded reset and power control block characteristics . . . . . . . . . . . 54
6.3.3 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.3.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.3.5 Wakeup time from Low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Contents STM32L151x6/8/B STM32L152x6/8/B
4/133 DocID17659 Rev 12
6.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.3.11 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.3.15 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.3.16 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.3.17 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.3.18 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
6.3.19 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.3.20 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
6.3.21 LCD controller (STM32L152xx only) . . . . . . . . . . . . . . . . . . . . . . . . . . 104
7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
7.1 LQFP100 14 x 14 mm, 100-pin low-profile quad flat package
information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
7.2 LQFP64 10 x 10 mm, 64-pin low-profile quad flat package information . 108
7.3 LQFP48 7 x 7 mm, 48-pin low-profile quad flat package information . . . .111
7.4 UFQFPN48 7 x 7 mm, 0.5 mm pitch, package information . . . . . . . . . . .114
7.5 UFBGA100 7 x 7 mm, 0.5 mm pitch, ultra thin fine-pitch
ball grid array package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
7.6 TFBGA64 5 x 5 mm, 0.5 mm pitch, thin fine-pitch ball
grid array package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
7.7 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
7.7.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
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STM32L151x6/8/B STM32L152x6/8/B List of tables
6
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Ultra-low-power STM32L151x6/8/B and STM32L152x6/8/B device features and
peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Functionalities depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . 15
Table 4. CPU frequency range depending on dynamic voltage scaling . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. Working mode-dependent functionalities (from Run/active down to standby) . . . . . . . . . . 17
Table 6. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 7. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 8. STM32L151x6/8/B and STM32L152x6/8/B pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 9. Alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 10. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 11. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 12. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 13. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 14. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 15. Embedded internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 16. Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 17. Current consumption in Run mode, code with data processing running from Flash. . . . . . 58
Table 18. Current consumption in Run mode, code with data processing running from RAM . . . . . . 59
Table 19. Current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 20. Current consumption in Low power run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 21. Current consumption in Low power sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 22. Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 23. Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 66
Table 24. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 25. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 26. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 27. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 28. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 29. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 30. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 31. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 32. MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 33. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 34. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 35. Flash memory and data EEPROM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 36. Flash memory, data EEPROM endurance and data retention . . . . . . . . . . . . . . . . . . . . . . 78
Table 37. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 38. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 39. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 40. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 41. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 42. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 43. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 44. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 45. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 46. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 47. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
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6/133 DocID17659 Rev 12
Table 48. SCL frequency (fPCLK1= 32 MHz, VDD = VDD_I2C = 3.3 V). . . . . . . . . . . . . . . . . . . . . . . . 88
Table 49. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 50. USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 51. USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 52. USB: full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 53. ADC clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 54. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 55. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 56. Maximum source impedance RAIN max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 57. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 58. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 59. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 60. Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 61. Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 62. LCD controller characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 63. LQPF100 14 x 14 mm, 100-pin low-profile quad flat package mechanical data . . . . . . . 106
Table 64. LQFP64 10 x 10 mm, 64-pin low-profile quad flat package mechanical data. . . . . . . . . . 108
Table 65. LQFP48 7 x 7 mm, 48-pin low-profile quad flat package mechanical data. . . . . . . . . . . . 112
Table 66. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . 115
Table 67. UFBGA100 7 x 7 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . 117
Table 68. UFBGA100 7 x 7 mm, 0.5 mm pitch, recommended PCB design rules . . . . . . . . . . . . . . 118
Table 69. TFBGA64 5 x 5 mm, 0.5 mm pitch, package mechanical data. . . . . . . . . . . . . . . . . . . . . 120
Table 70. TFBGA64 5 x 5 mm, 0.5 mm pitch, recommended PCB design rules . . . . . . . . . . . . . . . 121
Table 71. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 72. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 73. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
DocID17659 Rev 12 7/133
STM32L151x6/8/B STM32L152x6/8/B List of figures
8
List of figures
Figure 1. Ultra-low-power STM32L151x6/8/B and STM32L152x6/8/B block diagram. . . . . . . . . . . . 13
Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 3. STM32L15xVx UFBGA100 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 4. STM32L15xVx LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 5. STM32L15xRx TFBGA64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 6. STM32L15xRx LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 7. STM32L15xCx LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 8. STM32L15xCx UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 9. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 10. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 11. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 12. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 13. Optional LCD power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 14. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 15. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 16. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 17. HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 18. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 19. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 20. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 21. I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 22. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 23. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 24. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 25. USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 26. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 27. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 28. Maximum dynamic current consumption on VREF+ supply pin during ADC
conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 29. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . . 98
Figure 30. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . . 98
Figure 31. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 32. LQFP100 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 105
Figure 33. LQPF100 14 x 14 mm, 100-pin low-profile quad flat package recommended footprint . . 107
Figure 34. LQFP100 14 x 14 mm, 100-pin package top view example . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 35. LQFP64 10 x 10 mm, 64-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 108
Figure 36. LQFP64 10 x 10 mm, 64-pin low-profile quad flat package recommended footprint . . . . 109
Figure 37. LQFP64 10 x 10 mm, 64-pin low-profile quad flat package top view example . . . . . . . . . 110
Figure 38. LQFP48 7 x 7 mm, 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 111
Figure 39. LQFP48 7 x 7 mm, 48-pin low-profile quad flat recommended footprint. . . . . . . . . . . . . . 112
Figure 40. LQFP48 7 x 7 mm, 48-pin low-profile quad flat package top view example . . . . . . . . . . . 113
Figure 41. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 42. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package recommended footprint . . . . . . . . . . . . . . 115
Figure 43. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package top view example . . . . . . . . . . . . . . . . . . 116
Figure 44. UFBGA100, 7 x 7 mm, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 45. UFBGA100 7 x 7 mm, 0.5 mm pitch, package recommended footprint . . . . . . . . . . . . . . 118
Figure 46. UFBGA100 7 x 7 mm, 0.5 mm pitch, package top view example. . . . . . . . . . . . . . . . . . . 119
Figure 47. TFBGA64 5 x 5 mm, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
List of figures STM32L151x6/8/B STM32L152x6/8/B
8/133 DocID17659 Rev 12
Figure 48. TFBGA64, 5 x 5 mm, 0.5 mm pitch, recommended footprint . . . . . . . . . . . . . . . . . . . . . . 121
Figure 49. TFBGA64 5 x 5 mm, 0.5 mm pitch, package top view example . . . . . . . . . . . . . . . . . . . . 122
Figure 50. Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
DocID17659 Rev 12 9/133
STM32L151x6/8/B STM32L152x6/8/B Introduction
48
1 Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32L151x6/8/B and STM32L152x6/8/B ultra-low-power ARM® Cortex®-M3 based
microcontrollers product line.
The ultra-low-power STM32L151x6/8/B and STM32L152x6/8/B family includes devices in 3
different package types: from 48 to 100 pins. Depending on the device chosen, different sets
of peripherals are included, the description below gives an overview of the complete range
of peripherals proposed in this family.
These features make the ultra-low-power STM32L151x6/8/B and STM32L152x6/8/B
microcontroller family suitable for a wide range of applications:
Medical and handheld equipment
Application control and user interface
PC peripherals, gaming, GPS and sport equipment
Alarm systems, Wired and wireless sensors, Video intercom
Utility metering
This STM32L151x6/8/B and STM32L152x6/8/B datasheet should be read in conjunction
with the STM32L1xxxx reference manual (RM0038).
The document "Getting started with STM32L1xxxx hardware development” AN3216 gives a
hardware implementation overview. Both documents are available from the
STMicroelectronics website www.st.com.
For information on the ARM® Cortex®-M3 core please refer to the Cortex®-M3 Technical
Reference Manual, available from the www.arm.com website.
Figure 1 shows the general block diagram of the device family.
Caution: This datasheet does not apply to STM32L15xx6/8/B-A covered by a separate datasheet.
CERTIFIED USB Cdr't'e')?‘ Intelligent Processors by ARM‘ I POWERED
Description STM32L151x6/8/B STM32L152x6/8/B
10/133 DocID17659 Rev 12
2 Description
The ultra-low-power STM32L151x6/8/B and STM32L152x6/8/B devices incorporate the
connectivity power of the universal serial bus (USB) with the high-performance ARM®
Cortex®-M3 32-bit RISC core operating at 32 MHz frequency (33.3 DMIPS), a memory
protection unit (MPU), high-speed embedded memories (Flash memory up to 128 Kbytes
and RAM up to 16 Kbytes) and an extensive range of enhanced I/Os and peripherals
connected to two APB buses.
All the devices offer a 12-bit ADC, 2 DACs and 2 ultra-low-power comparators, six general-
purpose 16-bit timers and two basic timers, which can be used as time bases.
Moreover, the STM32L151x6/8/B and STM32L152x6/8/B devices contain standard and
advanced communication interfaces: up to two I2Cs and SPIs, three USARTs and a USB.
The STM32L151x6/8/B and STM32L152x6/8/B devices offer up to 20 capacitive sensing
channels to simply add touch sensing functionality to any application.
They also include a real-time clock and a set of backup registers that remain powered in
Standby mode.
Finally, the integrated LCD controller (except STM32L151x6/8/B devices) has a built-in LCD
voltage generator that allows to drive up to 8 multiplexed LCDs with contrast independent of
the supply voltage.
The ultra-low-power STM32L151x6/8/B and STM32L152x6/8/B devices operate from a 1.8
to 3.6 V power supply (down to 1.65 V at power down) with BOR and from a 1.65 to 3.6 V
power supply without BOR option. It is available in the -40 to +85 °C temperature range,
extended to 105°C in low power dissipation state. A comprehensive set of power-saving
modes allows the design of low-power applications.
DocID17659 Rev 12 11/133
STM32L151x6/8/B STM32L152x6/8/B Description
48
2.1 Device overview
Table 2. Ultra-low-power STM32L151x6/8/B and STM32L152x6/8/B device features and
peripheral counts
Peripheral STM32L15xCx STM32L15xRx STM32L15xVx
Flash (Kbytes) 32 64 128 32 64 128 64 128
Data EEPROM (Kbytes) 4
RAM (Kbytes) 10 10 16 10 10 16 10 16
Timers
General-
purpose 6
Basic 2
Communication
interfaces
SPI 2
I2C2
USART 3
USB 1
GPIOs 37 51 83
12-bit synchronized ADC
Number of channels
1
14 channels
1
20 channels
1
24 channels
12-bit DAC
Number of channels
2
2
LCD (STM32L152xx Only)
COM x SEG 4x18 4x32
8x28
4x44
8x40
Comparator 2
Capacitive sensing channels 13 20
Max. CPU frequency 32 MHz
Operating voltage 1.8 V to 3.6 V (down to 1.65 V at power-down) with BOR option
1.65 V to 3.6 V without BOR option
Operating temperatures Ambient temperatures: –40 to +85 °C
Junction temperature: –40 to + 105 °C
Packages LQFP48, UFQFPN48 LQFP64, BGA64 LQFP100, BGA100
Description STM32L151x6/8/B STM32L152x6/8/B
12/133 DocID17659 Rev 12
2.2 Ultra-low-power device continuum
The ultra-low-power STM32L151x6/8/B and STM32L152x6/8/B devices are fully pin-to-pin
and software compatible. Besides the full compatibility within the family, the devices are part
of STMicroelectronics microcontrollers ultra-low-power strategy which also includes
STM8L101xx and STM8L15xx devices. The STM8L and STM32L families allow a
continuum of performance, peripherals, system architecture and features.
They are all based on STMicroelectronics ultra-low leakage process.
Note: The ultra-low-power STM32L and general-purpose STM32Fxxxx families are pin-to-pin
compatible. The STM8L15xxx devices are pin-to-pin compatible with the STM8L101xx
devices. Please refer to the STM32F and STM8L documentation for more information on
these devices.
2.2.1 Performance
All families incorporate highly energy-efficient cores with both Harvard architecture and
pipelined execution: advanced STM8 core for STM8L families and ARM® Cortex®-M3 core
for STM32L family. In addition specific care for the design architecture has been taken to
optimize the mA/DMIPS and mA/MHz ratios.
This allows the ultra-low-power performance to range from 5 up to 33.3 DMIPs.
2.2.2 Shared peripherals
STM8L15xxx and STM32L1xxxx share identical peripherals which ensure a very easy
migration from one family to another:
Analog peripherals: ADC, DAC and comparators
Digital peripherals: RTC and some communication interfaces
2.2.3 Common system strategy
To offer flexibility and optimize performance, the STM8L15xx and STM32L1xxxx families
use a common architecture:
Same power supply range from 1.65 V to 3.6 V, (1.65 V at power down only for
STM8L15xx devices)
Architecture optimized to reach ultra-low consumption both in low power modes and
Run mode
Fast startup strategy from low power modes
Flexible system clock
Ultrasafe reset: same reset strategy including power-on reset, power-down reset,
brownout reset and programmable voltage detector.
2.2.4 Features
ST ultra-low-power continuum also lies in feature compatibility:
More than 10 packages with pin count from 20 to 144 pins and size down to 3 x 3 mm
Memory density ranging from 4 to 384 Kbytes
mxctcx, mam mum mxcwz, mm»; mmm E
DocID17659 Rev 12 13/133
STM32L151x6/8/B STM32L152x6/8/B Functional overview
48
3 Functional overview
Figure 1 shows the block diagram.
Figure 1. Ultra-low-power STM32L151x6/8/B and STM32L152x6/8/B block diagram
1. AF = alternate function on I/O port pin.
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Functional overview STM32L151x6/8/B STM32L152x6/8/B
14/133 DocID17659 Rev 12
3.1 Low power modes
The ultra-low-power STM32L151x6/8/B and STM32L152x6/8/B devices support dynamic
voltage scaling to optimize its power consumption in run mode. The voltage from the internal
low-drop regulator that supplies the logic can be adjusted according to the system’s
maximum operating frequency and the external voltage supply:
In Range 1 (VDD range limited to 1.71-3.6 V), the CPU runs at up to 32 MHz (refer to
Table 17 for consumption).
In Range 2 (full VDD range), the CPU runs at up to 16 MHz (refer to Table 17 for
consumption)
In Range 3 (full VDD range), the CPU runs at up to 4 MHz (generated only with the
multispeed internal RC oscillator clock source). Refer to Table 17 for consumption.
Seven low power modes are provided to achieve the best compromise between low power
consumption, short startup time and available wakeup sources:
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
Sleep mode power consumption: refer to Table 19.
Low power run mode
This mode is achieved with the multispeed internal (MSI) RC oscillator set to the
minimum clock (65 kHz), execution from SRAM or Flash memory, and internal
regulator in low power mode to minimize the regulator's operating current. In the Low
power run mode, the clock frequency and the number of enabled peripherals are both
limited.
Low power run mode consumption: refer to Table 20: Current consumption in Low
power run mode.
Low power sleep mode
This mode is achieved by entering the Sleep mode with the internal voltage regulator in
Low power mode to minimize the regulator’s operating current. In the Low power sleep
mode, both the clock frequency and the number of enabled peripherals are limited; a
typical example would be to have a timer running at 32 kHz.
When wakeup is triggered by an event or an interrupt, the system reverts to the run
mode with the regulator on.
Low power sleep mode consumption: refer to Table 21: Current consumption in Low
power sleep mode.
Stop mode with RTC
Stop mode achieves the lowest power consumption while retaining the RAM and
register contents and real time clock. All clocks in the VCORE domain are stopped, the
PLL, MSI RC, HSI RC and HSE crystal oscillators are disabled. The LSE or LSI is still
running. The voltage regulator is in the low power mode.
The device can be woken up from Stop mode by any of the EXTI line, in 8 µs. The EXTI
line source can be one of the 16 external lines. It can be the PVD output, the
Comparator 1 event or Comparator 2 event (if internal reference voltage is on), it can
be the RTC alarm(s), the USB wakeup, the RTC tamper events, the RTC timestamp
event or the RTC wakeup.
Stop mode without RTC
Stop mode achieves the lowest power consumption while retaining the RAM and
register contents. All clocks are stopped, the PLL, MSI RC, HSI and LSI RC, LSE and
DocID17659 Rev 12 15/133
STM32L151x6/8/B STM32L152x6/8/B Functional overview
48
HSE crystal oscillators are disabled. The voltage regulator is in the low power mode.
The device can be woken up from Stop mode by any of the EXTI line, in 8 µs. The EXTI
line source can be one of the 16 external lines. It can be the PVD output, the
Comparator 1 event or Comparator 2 event (if internal reference voltage is on). It can
also be wakened by the USB wakeup.
Stop mode consumption: refer to Table 22: Typical and maximum current
consumptions in Stop mode.
Standby mode with RTC
Standby mode is used to achieve the lowest power consumption and real time clock.
The internal voltage regulator is switched off so that the entire VCORE domain is
powered off. The PLL, MSI RC, HSI RC and HSE crystal oscillators are also switched
off. The LSE or LSI is still running. After entering Standby mode, the RAM and register
contents are lost except for registers in the Standby circuitry (wakeup logic, IWDG,
RTC, LSI, LSE Crystal 32K osc, RCC_CSR).
The device exits Standby mode in 60 µs when an external reset (NRST pin), an IWDG
reset, a rising edge on one of the three WKUP pins, RTC alarm (Alarm A or Alarm B),
RTC tamper event, RTC timestamp event or RTC Wakeup event occurs.
Standby mode without RTC
Standby mode is used to achieve the lowest power consumption. The internal voltage
regulator is switched off so that the entire VCORE domain is powered off. The PLL, MSI,
RC, HSI and LSI RC, HSE and LSE crystal oscillators are also switched off. After
entering Standby mode, the RAM and register contents are lost except for registers in
the Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE Crystal 32K osc,
RCC_CSR).
The device exits Standby mode in 60 µs when an external reset (NRST pin) or a rising
edge on one of the three WKUP pin occurs.
Standby mode consumption: refer to Table 23.
Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering the
Stop or Standby mode.
Table 3. Functionalities depending on the operating power supply range
Operating power
supply range
Functionalities depending on the operating power supply range
DAC and ADC
operation USB Dynamic voltage
scaling range I/O operation
VDD = 1.65 to 1.71 V Not functional Not functional Range 2 or
Range 3
Degraded speed
performance
VDD = 1.71 to 1.8 V(1) Not functional Not functional
Range 1,
Range 2 or
Range 3
Degraded speed
performance
VDD = 1.8 to 2.0 V(1) Conversion time
up to 500 Ksps Not functional
Range 1,
Range 2 or
Range 3
Degraded speed
performance
Functional overview STM32L151x6/8/B STM32L152x6/8/B
16/133 DocID17659 Rev 12
VDD = 2.0 to 2.4 V Conversion time
up to 500 Ksps Functional(2)
Range 1,
Range 2 or
Range 3
Full speed operation
VDD = 2.4 to 3.6 V Conversion time
up to 1 Msps Functional(2)
Range 1,
Range 2 or
Range 3
Full speed operation
1. The CPU frequency changes from initial to final must respect "FCPU initial < 4*FCPU final" to limit VCORE
drop due to current consumption peak when frequency increases. It must also respect 5 µs delay between
two changes. For example to switch from 4.2 MHz to 32 MHz, you can switch from 4.2 MHz to 16 MHz,
wait 5 µs, then switch from 16 MHz to 32 MHz.
2. Should be USB compliant from I/O voltage standpoint, the minimum VDD is 3.0 V.
Table 4. CPU frequency range depending on dynamic voltage scaling
CPU frequency range Dynamic voltage scaling range
16 MHz to 32 MHz (1ws)
32 kHz to 16 MHz (0ws) Range 1
8 MHz to 16 MHz (1ws)
32 kHz to 8 MHz (0ws) Range 2
2.1 MHz to 4.2 MHz (1ws)
32 kHz to 2.1 MHz (0ws) Range 3
Table 3. Functionalities depending on the operating power supply range (continued)
Operating power
supply range
Functionalities depending on the operating power supply range
DAC and ADC
operation USB Dynamic voltage
scaling range I/O operation
DocID17659 Rev 12 17/133
STM32L151x6/8/B STM32L152x6/8/B Functional overview
48
Table 5. Working mode-dependent functionalities (from Run/active down to standby)
Ips Run/Active Sleep
Low-
power
Run
Low-
power
Sleep
Stop Standby
Wakeup
capability
Wakeup
capability
CPU Y - Y - - - - -
Flash Y Y Y Y - - - -
RAM Y Y Y Y Y - - -
Backup Registers Y Y Y Y Y - Y -
EEPROM Y - Y Y Y - - -
Brown-out rest
(BOR) YYYYYYY-
DMA Y Y Y Y - - - -
Programmable
Voltage Detector
(PVD)
YYYYYYY-
Power On Reset
(POR) YYYYYYY-
Power Down Rest
(PDR) YYYYY-Y-
High Speed
Internal (HSI) YY------
High Speed
External (HSE) YY------
Low Speed Internal
(LSI) YYYYY-Y-
Low Speed
External (LSE) YYYYY-Y-
Multi-Speed
Internal (MSI) YYYY----
Inter-Connect
Controller YYYY----
RTC Y Y Y Y Y Y Y -
RTC Tamper Y Y Y Y Y Y Y Y
Auto Wakeup
(AWU) YYYYYYYY
LCD Y Y Y Y Y - - -
USB Y Y - - - Y - -
USART Y Y Y Y Y (1) --
SPI Y Y Y Y - - - -
I2C Y Y Y Y - (1) --
ADC Y Y - - - - - -
Functional overview STM32L151x6/8/B STM32L152x6/8/B
18/133 DocID17659 Rev 12
3.2 ARM® Cortex®-M3 core with MPU
The ARM® Cortex®-M3 processor is the industry leading processor for embedded systems.
It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM® Cortex®-M3 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
The memory protection unit (MPU) improves system reliability by defining the memory
attributes (such as read/write access permissions) for different memory regions. It provides
up to eight different regions and an optional predefined background region.
Owing to its embedded ARM core, the STM32L151x6/8/B and STM32L152x6/8/B devices
are compatible with all ARM tools and software.
DAC Y Y Y Y Y - - -
Temperature
sensor YYYYY---
Comparators Y Y Y Y Y Y - -
16-bit and 32-bit
Timers YYYY----
IWDG Y Y Y Y Y Y Y Y
WWDG Y Y Y Y - - - -
Touch sensing Y - - - - - - -
Systick Timer Y Y Y Y - - - -
GPIOs Y Y Y Y Y Y - 3 Pins
Wakeup time to
Run mode 0 µs 0.36 µs 3 µs 32 µs < 8 µs 50 µs
Consumption
VDD=1.8V to 3.6V
(Typ)
Do w n to
214 µA/MHz
(from Flash)
D o w n t o
50 µA/MHz
(from Flash)
Down to
9 µA
Down to
4.4 µA
0.5 µA (No
RTC) VDD=1.8V
0.3 µA (No RTC)
VDD=1.8V
1.4 µA (with
RTC) VDD=1.8V
1 µA (with RTC)
VDD=1.8V
0.5 µA (No
RTC) VDD=3.0V
0.3 µA (No RTC)
VDD=3.0V
1.6 µA (with
RTC) VDD=3.0V
1.3 µA (with
RTC) VDD=3.0V
1. The startup on communication line wakes the CPU which was made possible by an EXTI, this induces a delay before
entering run mode.
Table 5. Working mode-dependent functionalities (from Run/active down to standby) (continued)
Ips Run/Active Sleep
Low-
power
Run
Low-
power
Sleep
Stop Standby
Wakeup
capability
Wakeup
capability
DocID17659 Rev 12 19/133
STM32L151x6/8/B STM32L152x6/8/B Functional overview
48
Nested vectored interrupt controller (NVIC)
The ultra-low-power STM32L151x6/8/B and STM32L152x6/8/B devices embed a nested
vectored interrupt controller able to handle up to 45 maskable interrupt channels (not
including the 16 interrupt lines of Cortex®-M3) and 16 priority levels.
Closely coupled NVIC gives low-latency interrupt processing
Interrupt entry vector table address passed directly to the core
Closely coupled NVIC core interface
Allows early processing of interrupts
Processing of late arriving, higher-priority interrupts
Support for tail-chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
3.3 Reset and supply management
3.3.1 Power supply schemes
VDD = 1.65 to 3.6 V: external power supply for I/Os and the internal regulator.
Provided externally through VDD pins.
VSSA, VDDA = 1.65 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs
and PLL (minimum voltage to be applied to VDDA is 1.8 V when the ADC is used).
VDDA and VSSA must be connected to VDD and VSS, respectively.
3.3.2 Power supply supervisor
The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset
(PDR) that can be coupled with a brownout reset (BOR) circuitry.
The device exists in two versions:
The version with BOR activated at power-on operates between 1.8 V and 3.6 V.
The other version without BOR operates between 1.65 V and 3.6 V.
After the VDD threshold is reached (1.65 V or 1.8 V depending on the BOR which is active or
not at power-on), the option byte loading process starts, either to confirm or modify default
thresholds, or to disable the BOR permanently: in this case, the VDD min value becomes
1.65 V (whatever the version, BOR active or not, at power-on).
When BOR is active at power-on, it ensures proper operation starting from 1.8 V whatever
the power ramp-up phase before it reaches 1.8 V. When BOR is not active at power-up, the
power ramp-up should guarantee that 1.65 V is reached on VDD at least 1 ms after it exits
the POR area.
Functional overview STM32L151x6/8/B STM32L152x6/8/B
20/133 DocID17659 Rev 12
Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To
reduce the power consumption in Stop mode, it is possible to automatically switch off the
internal reference voltage (VREFINT) in Stop mode. The device remains in reset mode when
VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for any external
reset circuit.
Note: The start-up time at power-on is typically 3.3 ms when BOR is active at power-up, the start-
up time at power-on can be decreased down to 1 ms typically for devices with BOR inactive
at power-up.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD/VDDA power supply and compares it to the VPVD threshold. This PVD offers 7 different
levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An
interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when
VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate
a warning message and/or put the MCU into a safe state. The PVD is enabled by software.
3.3.3 Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR) and power down.
MR is used in Run mode (nominal regulation)
LPR is used in the Low-power run, Low-power sleep and Stop modes
Power down is used in Standby mode. The regulator output is high impedance, the
kernel circuitry is powered down, inducing zero consumption but the contents of the
registers and RAM are lost are lost except for the standby circuitry (wakeup logic,
IWDG, RTC, LSI, LSE crystal 32K osc, RCC_CSR).
3.3.4 Boot modes
At startup, boot pins are used to select one of three boot options:
Boot from Flash memory
Boot from System Memory
Boot from embedded RAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART1 or USART2. See STM32™ microcontroller system memory boot mode
AN2606 for details.
DocID17659 Rev 12 21/133
STM32L151x6/8/B STM32L152x6/8/B Functional overview
48
3.4 Clock management
The clock controller distributes the clocks coming from different oscillators to the core and
the peripherals. It also manages clock gating for low power modes and ensures clock
robustness. It features:
Clock prescaler: to get the best trade-off between speed and current consumption, the
clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler
Safe clock switching: clock sources can be changed safely on the fly in run mode
through a configuration register.
Clock management: to reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
Master clock source: three different clock sources can be used to drive the master
clock:
1-24 MHz high-speed external crystal (HSE), that can supply a PLL
16 MHz high-speed internal RC oscillator (HSI), trimmable by software, that can
supply a PLL
Multispeed internal RC oscillator (MSI), trimmable by software, able to generate 7
frequencies (65.5 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.1 MHz, 4.2 MHz)
with a consumption proportional to speed, down to 750 nA typical. When a
32.768 kHz clock source is available in the system (LSE), the MSI frequency can
be trimmed by software down to a ±0.5% accuracy.
Auxiliary clock source: two ultra-low-power clock sources that can be used to drive
the LCD controller and the real-time clock:
32.768 kHz low-speed external crystal (LSE)
37 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.
The LSI clock can be measured using the high-speed internal RC oscillator for
greater precision.
RTC and LCD clock sources: the LSI, LSE or HSE sources can be chosen to clock
the RTC and the LCD, whatever the system clock.
USB clock source: the embedded PLL has a dedicated 48 MHz clock output to supply
the USB interface.
Startup clock: after reset, the microcontroller restarts by default with an internal
2.1 MHz clock (MSI). The prescaler ratio and clock source can be changed by the
application program as soon as the code execution starts.
Clock security system (CSS): this feature can be enabled by software. If a HSE clock
failure occurs, the master clock is automatically switched to HSI and a software
interrupt is generated if enabled.
Clock-out capability (MCO: microcontroller clock output): it outputs one of the
internal clocks for external use by the application.
Several prescalers allow the configuration of the AHB frequency, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and
the APB domains is 32 MHz. See Figure 2 for details on the clock tree.
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Functional overview STM32L151x6/8/B STM32L152x6/8/B
22/133 DocID17659 Rev 12
Figure 2. Clock tree
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DocID17659 Rev 12 23/133
STM32L151x6/8/B STM32L152x6/8/B Functional overview
48
3.5 Low power real-time clock and backup registers
The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain
the second, minute, hour (12/24 hour), week day, date, month, year, in BCD (binary-coded
decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are made
automatically. The RTC provides a programmable alarm and programmable periodic
interrupts with wakeup from Stop and Standby modes.
The programmable wakeup time ranges from 120 µs to 36 hours
Stop mode consumption with LSI and Auto-wakeup: 1.2 µA (at 1.8 V) and 1.4 µA (at
3.0 V)
Stop mode consumption with LSE, calendar and Auto-wakeup: 1.3 µA (at 1.8V), 1.6 µA
(at 3.0 V)
The RTC can be calibrated with an external 512 Hz output, and a digital compensation
circuit helps reduce drift due to crystal deviation.
There are twenty 32-bit backup registers provided to store 80 bytes of user application data.
They are cleared in case of tamper detection.
3.6 GPIOs (general-purpose inputs/outputs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions, and can be individually
remapped using dedicated AFIO registers. All GPIOs are high current capable. The
alternate function configuration of I/Os can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/O registers. The I/O controller is
connected to the AHB with a toggling speed of up to 16 MHz.
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 23 edge detector lines used to generate
interrupt/event requests. Each line can be individually configured to select the trigger event
(rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 83 GPIOs can be connected
to the 16 external interrupt lines. The 7 other lines are connected to RTC, PVD, USB or
Comparator events.
Functional overview STM32L151x6/8/B STM32L152x6/8/B
24/133 DocID17659 Rev 12
3.7 Memories
The STM32L151x6/8/B and STM32L152x6/8/B devices have the following features:
Up to 16 Kbytes of embedded RAM accessed (read/write) at CPU clock speed with 0
wait states. With the enhanced bus matrix, operating the RAM does not lead to any
performance penalty during accesses to the system bus (AHB and APB buses).
The non-volatile memory is divided into three arrays:
32, 64 or 128 Kbytes of embedded Flash program memory
4 Kbytes of data EEPROM
Options bytes
The options bytes are used to write-protect the memory (with 4 Kbytes granularity)
and/or readout-protect the whole memory with the following options:
Level 0: no readout protection
Level 1: memory readout protection, the Flash memory cannot be read from or
written to if either debug features are connected or boot in RAM is selected
Level 2: chip readout protection, debug features (Cortex®-M3 JTAG and serial
wire) and boot in RAM selection disabled (JTAG fuse)
The whole non-volatile memory embeds the error correction code (ECC) feature.
3.8 DMA (direct memory access)
The flexible 7-channel, general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management, avoiding the generation of interrupts when the controller
reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with software trigger
support for each channel. Configuration is done by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose timers
and ADC.
3.9 LCD (liquid crystal display)
The LCD drives up to 8 common terminals and 44 segment terminals to drive up to 320
pixels.
Internal step-up converter to guarantee functionality and contrast control irrespective of
VDD. This converter can be deactivated, in which case the VLCD pin is used to provide
the voltage to the LCD
Supports static, 1/2, 1/3, 1/4 and 1/8 duty
Supports static, 1/2, 1/3 and 1/4 bias
Phase inversion to reduce power consumption and EMI
Up to 8 pixels can be programmed to blink
Unneeded segments and common pins can be used as general I/O pins
LCD RAM can be updated at any time owing to a double-buffer
The LCD controller can operate in Stop mode
DocID17659 Rev 12 25/133
STM32L151x6/8/B STM32L152x6/8/B Functional overview
48
3.10 ADC (analog-to-digital converter)
A 12-bit analog-to-digital converters is embedded into STM32L151x6/8/B and
STM32L152x6/8/B devices with up to 24 external channels, performing conversions in
single-shot or scan mode. In scan mode, automatic conversion is performed on a selected
group of analog inputs.
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
The events generated by the general-purpose timers (TIMx) can be internally connected to
the ADC start trigger and injection trigger, to allow the application to synchronize A/D
conversions and timers. An injection mode allows high priority conversions to be done by
interrupting a scan mode which runs in as a background task.
The ADC includes a specific low power mode. The converter is able to operate at maximum
speed even if the CPU is operating at a very low frequency and has an auto-shutdown
function. The ADC’s runtime and analog front-end current consumption are thus minimized
whatever the MCU operating mode.
3.10.1 Temperature sensor
The temperature sensor (TS) generates a voltage VSENSE that varies linearly with
temperature.
The temperature sensor is internally connected to the ADC_IN16 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode, see Table 58:
Temperature sensor calibration values.
3.10.2 Internal voltage reference (VREFINT)
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the
ADC and Comparators. VREFINT is internally connected to the ADC_IN17 input channel. It
enables accurate monitoring of the VDD value (when no external voltage, VREF+, is
available for ADC). The precise voltage of VREFINT is individually measured for each part by
ST during production test and stored in the system memory area. It is accessible in read-
only mode see Table 16: Embedded internal reference voltage.
3.11 DAC (digital-to-analog converter)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs. The chosen design structure is composed of integrated
resistor strings and an amplifier in non-inverting configuration.
Functional overview STM32L151x6/8/B STM32L152x6/8/B
26/133 DocID17659 Rev 12
This dual digital Interface supports the following features:
two DAC converters: one for each output channel
left or right data alignment in 12-bit mode
synchronized update capability
noise-wave generation
triangular-wave generation
dual DAC channels’ independent or simultaneous conversions
DMA capability for each channel (including the underrun interrupt)
external triggers for conversion
input reference voltage VREF+
Eight DAC trigger inputs are used in the STM32L151x6/8/B and STM32L152x6/8/B devices.
The DAC channels are triggered through the timer update outputs that are also connected
to different DMA channels.
3.12 Ultra-low-power comparators and reference voltage
The STM32L151x6/8/B and STM32L152x6/8/B devices embed two comparators sharing
the same current bias and reference voltage. The reference voltage can be internal or
external (coming from an I/O).
one comparator with fixed threshold
one comparator with rail-to-rail inputs, fast or slow mode. The threshold can be one of
the following:
DAC output
External I/O
Internal reference voltage (VREFINT) or VREFINT submultiple (1/4, 1/2, 3/4)
Both comparators can wake up from Stop mode, and be combined into a window
comparator.
The internal reference voltage is available externally via a low power / low current output
buffer (driving current capability of 1 µA typical).
3.13 Routing interface
This interface controls the internal routing of I/Os to TIM2, TIM3, TIM4 and to the
comparator and reference voltage output.
3.14 Touch sensing
The STM32L151x6/8/B and STM32L152x6/8/B devices provide a simple solution for adding
capacitive sensing functionality to any application. These devices offer up to 20 capacitive
sensing channels distributed over 10 analog I/O groups. Only software capacitive sensing
acquisition mode is supported.
Capacitive sensing technology is able to detect the presence of a finger near a sensor which
is protected from direct touch by a dielectric (glass, plastic, ...). The capacitive variation
introduced by the finger (or any conductive object) is measured using a proven
DocID17659 Rev 12 27/133
STM32L151x6/8/B STM32L152x6/8/B Functional overview
48
implementation based on a surface charge transfer acquisition principle. It consists of
charging the sensor capacitance and then transferring a part of the accumulated charges
into a sampling capacitor until the voltage across this capacitor has reached a specific
threshold. The capacitive sensing acquisition only requires few external components to
operate.
Reliable touch sensing functionality can be quickly and easily implemented using the free
STM32L1xx STMTouch touch sensing firmware library.
3.15 Timers and watchdogs
The ultra-low-power STM32L151x6/8/B and STM32L152x6/8/B devices include six general-
purpose timers, two basic timers and two watchdog timers.
Table 6 compares the features of the general-purpose and basic timers.
Table 6. Timer feature comparison
Timer Counter
resolution
Counter
type
Prescaler
factor
DMA request
generation
Capture/compare
channels
Complementary
outputs
TIM2,
TIM3,
TIM4
16-bit
Up,
down,
up/down
Any integer
between 1
and 65536
Yes 4 No
TIM9 16-bit Up
Any integer
between 1
and 65536
No 2 No
TIM10,
TIM11 16-bit Up
Any integer
between 1
and 65536
No 1 No
TIM6,
TIM7 16-bit Up
Any integer
between 1
and 65536
Yes 0 No
Functional overview STM32L151x6/8/B STM32L152x6/8/B
28/133 DocID17659 Rev 12
3.15.1 General-purpose timers (TIM2, TIM3, TIM4, TIM9, TIM10 and TIM11)
There are six synchronizable general-purpose timers embedded in the STM32L151x6/8/B
and STM32L152x6/8/B devices (see Table 6 for differences).
TIM2, TIM3, TIM4
These timers are based on a 16-bit auto-reload up/down-counter and a 16-bit prescaler.
They feature 4 independent channels each for input capture/output compare, PWM or one-
pulse mode output. This gives up to 12 input captures/output compares/PWMs on the
largest packages.
The TIM2, TIM3, TIM4 general-purpose timers can work together or with the TIM10, TIM11
and TIM9 general-purpose timers via the Timer Link feature for synchronization or event
chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers
can be used to generate PWM outputs.
TIM2, TIM3, TIM4 all have independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
TIM10, TIM11 and TIM9
These timers are based on a 16-bit auto-reload up-counter and a 16-bit prescaler. They
include a 16-bit prescaler. TIM10 and TIM11 feature one independent channel, whereas
TIM9 has two independent channels for input capture/output compare, PWM or one-pulse
mode output. They can be synchronized with the TIM2, TIM3, TIM4 full-featured general-
purpose timers.
They can also be used as simple time bases and be clocked by the LSE clock source
(32.768 kHz) to provide time bases independent from the main CPU clock.
3.15.2 Basic timers (TIM6 and TIM7)
These timers are mainly used for DAC trigger generation. They can also be used as generic
16-bit time bases.
3.15.3 SysTick timer
This timer is dedicated to the OS, but could also be used as a standard downcounter. It is
based on a 24-bit down-counter with autoreload capability and a programmable clock
source. It features a maskable system interrupt generation when the counter reaches 0.
3.15.4 Independent watchdog (IWDG)
The independent watchdog is based on a 12-bit down-counter and 8-bit prescaler. It is
clocked from an independent 37 kHz internal RC and, as it operates independently of the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes. The counter
can be frozen in debug mode.
DocID17659 Rev 12 29/133
STM32L151x6/8/B STM32L152x6/8/B Functional overview
48
3.15.5 Window watchdog (WWDG)
The window watchdog is based on a 7-bit down-counter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
3.16 Communication interfaces
3.16.1 I²C bus
Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support
standard and fast modes.
They support dual slave addressing (7-bit only) and both 7- and 10-bit addressing in master
mode. A hardware CRC generation/verification is embedded.
They can be served by DMA and they support SM Bus 2.0/PM Bus.
3.16.2 Universal synchronous/asynchronous receiver transmitter (USART)
All USART interfaces are able to communicate at speeds of up to 4 Mbit/s. They provide
hardware management of the CTS and RTS signals and are ISO 7816 compliant. They
support IrDA SIR ENDEC and have LIN Master/Slave capability.
All USART interfaces can be served by the DMA controller.
3.16.3 Serial peripheral interface (SPI)
Up to two SPIs are able to communicate at up to 16 Mbits/s in slave and master modes in
full-duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes.
Both SPIs can be served by the DMA controller.
3.16.4 Universal serial bus (USB)
The STM32L151x6/8/B and STM32L152x6/8/B devices embed a USB device peripheral
compatible with the USB full speed 12 Mbit/s. The USB interface implements a full speed
(12 Mbit/s) function interface. It has software-configurable endpoint setting and supports
suspend/resume. The dedicated 48 MHz clock is generated from the internal main PLL (the
clock source must use a HSE crystal oscillator).
Functional overview STM32L151x6/8/B STM32L152x6/8/B
30/133 DocID17659 Rev 12
3.17 CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
3.18 Development support
Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG JTMS and JTCK pins are shared with SWDAT and SWCLK, respectively, and a
specific sequence on the JTMS pin is used to switch between JTAG-DP and SW-DP.
The JTAG port can be permanently disabled with a JTAG fuse.
Embedded Trace Macrocell™
The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the
STM32L151x6/8/B and STM32L152x6/8/B device through a small number of ETM pins to
an external hardware trace port analyzer (TPA) device. The TPA is connected to a host
computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and
data flow activity can be recorded and then formatted for display on the host computer
running debugger software. TPA hardware is commercially available from common
development tool vendors. It operates with third party debugger software tools.
DocID17659 Rev 12 31/133
STM32L151x6/8/B STM32L152x6/8/B Pin descriptions
48
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Figure 4. STM32L15xVx LQFP100 pinout
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DocID17659 Rev 12 33/133
STM32L151x6/8/B STM32L152x6/8/B Pin descriptions
48
Figure 5. STM32L15xRx TFBGA64 ballout
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Pin descriptions STM32L151x6/8/B STM32L152x6/8/B
34/133 DocID17659 Rev 12
Figure 6. STM32L15xRx LQFP64 pinout
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Figure 7. STM32L15xCx LQFP48 pinout
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DocID17659 Rev 12 35/133
STM32L151x6/8/B STM32L152x6/8/B Pin descriptions
48
Figure 8. STM32L15xCx UFQFPN48 pinout
1. This figure shows the package top view.
633?
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Pin descriptions STM32L151x6/8/B STM32L152x6/8/B
36/133 DocID17659 Rev 12
Table 7. Legend/abbreviations used in the pinout table
Name Abbreviation Definition
Pin name Unless otherwise specified in brackets below the pin name, the pin function
during and after reset is the same as the actual pin name
Pin type
S Supply pin
I Input only pin
I/O Input / output pin
I/O structure
FT 5 V tolerant I/O
TC Standard 3.3 V I/O
B Dedicated BOOT0 pin
RST Bidirectional reset pin with embedded weak pull-up resistor
Notes Unless otherwise specified by a note, all I/Os are set as floating inputs during
and after reset
Pin
functions
Alternate
functions Functions selected through GPIOx_AFR registers
Additional
functions Functions directly selected/enabled through peripheral registers
DocID17659 Rev 12 37/133
STM32L151x6/8/B STM32L152x6/8/B Pin descriptions
48
Table 8. STM32L151x6/8/B and STM32L152x6/8/B pin definitions
Pins
Pin name
Pin type(1)
I/O structure
Main
function(2)
(after reset)
Pins functions
LQFP100
LQFP64
TFBGA64
UFBGA100
LQFP48 or UFQFPN48
Alternate functions Additional
functions
1 - - B2 - PE2 I/O FT PE2 TRACECLK/LCD_SEG38/
TIM3_ETR -
2 - - A1 - PE3 I/O FT PE3 TRACED0/LCD_SEG39/
TIM3_CH1 -
3 - - B1 - PE4 I/O FT PE4 TRACED1/TIM3_CH2 -
4 - - C2 - PE5 I/O FT PE5 TRACED2/TIM9_CH1 -
5 - - D2 - PE6-WKUP3 I/O FT PE6 TRACED3/TIM9_CH2 WKUP3
61B2E21 V
LCD(3) SV
LCD --
72A2C12 PC13-
WKUP2 I/O FT PC13 -
RTC_TAMP1/
RTC_TS/
RTC_OUT/
WKUP2
83A1D13 PC14-
OSC32_IN(4) I/O TC PC14 - OSC32_IN
94B1E14
PC15-
OSC32_OUT
(4)
I/O TC PC15 - OSC32_OUT
10 - - F2 - VSS_5 S- V
SS_5 --
11 - - G2 - VDD_5 S- V
DD_5 --
12 5 C1 F1 5 PH0-
OSC_IN(5) I/O TC PH0 - OSC_IN
13 6 D1 G1 6 PH1-
OSC_OUT I/O TC PH1 - OSC_OUT
14 7 E1 H2 7 NRST I/O RST NRST - -
15 8 E3 H1 - PC0 I/O FT PC0 LCD_SEG18 ADC_IN10/
/COMP1_INP
16 9 E2 J2 - PC1 I/O FT PC1 LCD_SEG19 ADC_IN11/
COMP1_INP
17 10 F2 J3 - PC2 I/O FT PC2 LCD_SEG20 ADC_IN12/
COMP1_INP
18 11 -(6) K2 - PC3 I/O TC PC3 LCD_SEG21 ADC_IN13/
COMP1_INP
Pin descriptions STM32L151x6/8/B STM32L152x6/8/B
38/133 DocID17659 Rev 12
19 12 F1 J1 8 VSSA S- V
SSA --
20 - - K1 - VREF- S- V
REF- --
21 - G1
(6) L1 - VREF+ S- V
REF+ --
22 13 H1 M1 9 VDDA S- V
DDA --
23 14 G2 L2 10 PA0-WKUP1 I/O FT PA0 USART2_CTS/
TIM2_CH1_ETR
WKUP1/
ADC_IN0/
COMP1_INP
24 15 H2 M2 11 PA1 I/O FT PA1 USART2_RTS/
TIM2_CH2/LCD_SEG0
ADC_IN1/
COMP1_INP
25 16 F3 K3 12 PA2 I/O FT PA2 USART2_TX/TIM2_CH3/
TIM9_CH1/LCD_SEG1
ADC_IN2/
COMP1_INP
26 17 G3 L3 13 PA3 I/O TC PA3 USART2_RX/TIM2_CH4/
TIM9_CH2/LCD_SEG2
ADC_IN3/
COMP1_INP
27 18 C2 E3 - VSS_4 S- V
SS_4 --
28 19 D2 H3 - VDD_4 S- V
DD_4 --
29 20 H3 M3 14 PA4 I/O TC PA4 SPI1_NSS/USART2_CK
ADC_IN4/
DAC_OUT1/
COMP1_INP
30 21 F4 K4 15 PA5 I/O TC PA5 SPI1_SCK/
TIM2_CH1_ETR
ADC_IN5/
DAC_OUT2/
COMP1_INP
31 22 G4 L4 16 PA6 I/O FT PA6 SPI1_MISO/TIM3_CH1/
LCD_SEG3/TIM10_CH1
ADC_IN6
/COMP1_INP
32 23 H4 M4 17 PA7 I/O FT PA7 SPI1_MOSI//TIM3_CH2/
LCD_SEG4/TIM11_CH1
ADC_IN7/
COMP1_INP
33 24 H5 K5 - PC4 I/O FT PC4 LCD_SEG22 ADC_IN14/
COMP1_INP
34 25 H6 L5 - PC5 I/O FT PC5 LCD_SEG23 ADC_IN15/
COMP1_INP
Table 8. STM32L151x6/8/B and STM32L152x6/8/B pin definitions (continued)
Pins
Pin name
Pin type(1)
I/O structure
Main
function(2)
(after reset)
Pins functions
LQFP100
LQFP64
TFBGA64
UFBGA100
LQFP48 or UFQFPN48
Alternate functions Additional
functions
DocID17659 Rev 12 39/133
STM32L151x6/8/B STM32L152x6/8/B Pin descriptions
48
35 26 F5 M5 18 PB0 I/O TC PB0 TIM3_CH3/LCD_SEG5
ADC_IN8/
COMP1_INP/
VREF_OUT
36 27 G5 M6 19 PB1 I/O FT PB1 TIM3_CH4/LCD_SEG6
ADC_IN9/
COMP1_INP/
VREF_OUT
37 28 G6 L6 20 PB2 I/O FT PB2/BOOT1 BOOT1 -
38 - - M7 - PE7 I/O TC PE7 - ADC_IN22/
COMP1_INP
39 - - L7 - PE8 I/O TC PE8 - ADC_IN23/
COMP1_INP
40 - - M8 - PE9 I/O TC PE9 TIM2_CH1_ETR ADC_IN24/
COMP1_INP
41 - - L8 - PE10 I/O TC PE10 TIM2_CH2 ADC_IN25/
COMP1_INP
42 - - M9 - PE11 I/O FT PE11 TIM2_CH3 -
43 - - L9 - PE12 I/O FT PE12 TIM2_CH4/SPI1_NSS -
44 - - M10 - PE13 I/O FT PE13 SPI1_SCK -
45 - - M11 - PE14 I/O FT PE14 SPI1_MISO -
46 - - M12 - PE15 I/O FT PE15 SPI1_MOSI -
47 29 G7 L10 21 PB10 I/O FT PB10 I2C2_SCL/USART3_TX/
TIM2_CH3/LCD_SEG10 -
48 30 H7 L11 22 PB11 I/O FT PB11 I2C2_SDA/USART3_RX/
TIM2_CH4/LCD_SEG11 -
49 31 D6 F12 23 VSS_1 S- V
SS_1 --
50 32 E6 G12 24 VDD_1 S- V
DD_1 --
51 33 H8 L12 25 PB12 I/O FT PB12
SPI2_NSS/I2C2_SMBA/
USART3_CK/
LCD_SEG12/TIM10_CH1
ADC_IN18/
COMP1_INP
52 34 G8 K12 26 PB13 I/O FT PB13
SPI2_SCK/USART3_CTS/
LCD_SEG13/
TIM9_CH1
ADC_IN19/
COMP1_INP
Table 8. STM32L151x6/8/B and STM32L152x6/8/B pin definitions (continued)
Pins
Pin name
Pin type(1)
I/O structure
Main
function(2)
(after reset)
Pins functions
LQFP100
LQFP64
TFBGA64
UFBGA100
LQFP48 or UFQFPN48
Alternate functions Additional
functions
Pin descriptions STM32L151x6/8/B STM32L152x6/8/B
40/133 DocID17659 Rev 12
53 35 F8 K11 27 PB14 I/O FT PB14
SPI2_MISO/
USART3_RTS/
LCD_SEG14//TIM9_CH2
ADC_IN20/
COMP1_INP
54 36 F7 K10 28 PB15 I/O FT PB15 SPI2_MOSI/LCD_SEG15/
TIM11_CH1
ADC_IN21/
COMP1_INP/
RTC_REFIN
55 - - K9 - PD8 I/O FT PD8 USART3_TX/
LCD_SEG28 -
56 - - K8 - PD9 I/O FT PD9 USART3_RX/
LCD_SEG29 -
57 - - J12 - PD10 I/O FT PD10 USART3_CK/
LCD_SEG30 -
58 - - J11 - PD11 I/O FT PD11 USART3_CTS/
LCD_SEG31 -
59 - - J10 - PD12 I/O FT PD12
TIM4_CH1/
USART3_RTS/
LCD_SEG32
-
60 - - H12 - PD13 I/O FT PD13 TIM4_CH2/LCD_SEG33 -
61 - - H11 - PD14 I/O FT PD14 TIM4_CH3/LCD_SEG34 -
62 - - H10 - PD15 I/O FT PD15 TIM4_CH4/LCD_SEG35 -
63 37 F6 E12 - PC6 I/O FT PC6 TIM3_CH1/LCD_SEG24 -
64 38 E7 E11 - PC7 I/O FT PC7 TIM3_CH2/LCD_SEG25 -
65 39 E8 E10 - PC8 I/O FT PC8 TIM3_CH3/LCD_SEG26 -
66 40 D8 D12 - PC9 I/O FT PC9 TIM3_CH4/LCD_SEG27 -
67 41 D7 D11 29 PA8 I/O FT PA8 USART1_CK/MCO/
LCD_COM0 -
68 42 C7 D10 30 PA9 I/O FT PA9 USART1_TX/LCD_COM1 -
69 43 C6 C12 31 PA10 I/O FT PA10 USART1_RX/LCD_COM2 -
70 44 C8 B12 32 PA11 I/O FT PA11 USART1_CTS/
SPI1_MISO USB_DM
Table 8. STM32L151x6/8/B and STM32L152x6/8/B pin definitions (continued)
Pins
Pin name
Pin type(1)
I/O structure
Main
function(2)
(after reset)
Pins functions
LQFP100
LQFP64
TFBGA64
UFBGA100
LQFP48 or UFQFPN48
Alternate functions Additional
functions
DocID17659 Rev 12 41/133
STM32L151x6/8/B STM32L152x6/8/B Pin descriptions
48
71 45 B8 A12 33 PA12 I/O FT PA12 USART1_RTS/
SPI1_MOSI USB_DP
72 46 A8 A11 34 PA13 I/O FT JTMS-
SWDIO JTMS-SWDIO -
73 - - C11 - PH2 I/O FT PH2 - -
74 47 D5 F11 35 VSS_2 S- V
SS_2 --
75 48 E5 G11 36 VDD_2 S- V
DD_2 --
76 49 A7 A10 37 PA14 I/O FT JTCK
-SWCLK JTCK-SWCLK -
77 50 A6 A9 38 PA15 I/O FT JTDI
TIM2_CH1_ETR/PA15/
SPI1_NSS/
LCD_SEG17
-
78 51 B7 B11 - PC10 I/O FT PC10 USART3_TX/LCD_SEG28
/LCD_SEG40/LCD_COM4 -
79 52 B6 C10 - PC11 I/O FT PC11 USART3_RX/LCD_SEG29
/LCD_SEG41/LCD_COM5 -
80 53 C5 B10 - PC12 I/O FT PC12 USART3_CK/LCD_SEG30
/LCD_SEG42/LCD_COM6 -
81 - - C9 - PD0 I/O FT PD0 SPI2_NSS/TIM9_CH1 -
82 - - B9 - PD1 I/O FT PD1 SPI2_SCK -
83 54 B5 C8 - PD2 I/O FT PD2 TIM3_ETR/LCD_SEG31/
LCD_SEG43/LCD_COM7 -
84 - - B8 - PD3 I/O FT PD3 USART2_CTS/
SPI2_MISO -
85 - - B7 - PD4 I/O FT PD4 USART2_RTS/
SPI2_MOSI -
86 - - A6 - PD5 I/O FT PD5 USART2_TX -
87 - - B6 - PD6 I/O FT PD6 USART2_RX -
88 - - A5 - PD7 I/O FT PD7 USART2_CK/TIM9_CH2 -
89 55 A5 A8 39 PB3 I/O FT JTDO
TIM2_CH2/PB3/
SPI1_SCK/LCD_SEG7/
JTDO
COMP2_INM
Table 8. STM32L151x6/8/B and STM32L152x6/8/B pin definitions (continued)
Pins
Pin name
Pin type(1)
I/O structure
Main
function(2)
(after reset)
Pins functions
LQFP100
LQFP64
TFBGA64
UFBGA100
LQFP48 or UFQFPN48
Alternate functions Additional
functions
Pin descriptions STM32L151x6/8/B STM32L152x6/8/B
42/133 DocID17659 Rev 12
90 56 A4 A7 40 PB4 I/O FT NJTRST
TIM3_CH1/PB4/
SPI1_MISO/LCD_SEG8/
NJTRST
COMP2_INP
91 57 C4 C5 41 PB5 I/O FT PB5 I2C1_SMBA/TIM3_CH2/
SPI1_MOSI/LCD_SEG9 COMP2_INP
92 58 D3 B5 42 PB6 I/O FT PB6 I2C1_SCL/TIM4_CH1/
USART1_TX
93 59 C3 B4 43 PB7 I/O FT PB7 I2C1_SDA/TIM4_CH2/
USART1_RX
PVD_IN
94 60 B4 A4 44 BOOT0 I B BOOT0 - -
95 61 B3 A3 45 PB8 I/O FT PB8 TIM4_CH3/I2C1_SCL/
LCD_SEG16/TIM10_CH1 -
96 62 A3 B3 46 PB9 I/O FT PB9 TIM4_CH4/I2C1_SDA/
LCD_COM3/TIM11_CH1 -
97 - - C3 - PE0 I/O FT PE0 TIM4_ETR/LCD_SEG36/
TIM10_CH1 -
98 - - A2 - PE1 I/O FT PE1 LCD_SEG37/TIM11_CH1 -
99 63 D4 D3 47 VSS_3 S- V
SS_3 --
100 64 E4 C4 48 VDD_3 S- V
DD_3 --
1. I = input, O = output, S = supply.
2. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower
number of peripheral that is included. For example, if a device has only one SPI and two USARTs, they will be called SPI1
and USART1 & USART2, respectively. Refer to Table 2 on page 11.
3. Applicable to STM32L152xx devices only. In STM32L151xx devices, this pin should be connected to VDD.
4. The PC14 and PC15 I/Os are only configured as OSC32_IN/OSC32_OUT when the LSE oscillator is on (by setting the
LSEON bit in the RCC_CSR register). The LSE oscillator pins OSC32_IN/OSC32_OUT can be used as general-purpose
PC14/PC15 I/Os, respectively, when the LSE oscillator is off (after reset, the LSE oscillator is off). The LSE has priority over
the GPIO function. For more details, refer to Using the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15 port pins
section in the STM32L1xxxx reference manual (RM0038).
5. The PH0 and PH1 I/Os are only configured as OSC_IN/OSC_OUT when the HSE oscillator is on (by setting the HSEON bit
in the RCC_CR register). The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose PH0/PH1 I/Os,
respectively, when the HSE oscillator is off (after reset, the HSE oscillator is off). The HSE has priority over the GPIO
function.
6. Unlike in the LQFP64 package, there is no PC3 in the TFBGA64 package. The VREF+ functionality is provided instead.
Table 8. STM32L151x6/8/B and STM32L152x6/8/B pin definitions (continued)
Pins
Pin name
Pin type(1)
I/O structure
Main
function(2)
(after reset)
Pins functions
LQFP100
LQFP64
TFBGA64
UFBGA100
LQFP48 or UFQFPN48
Alternate functions Additional
functions
Memory mapping STM32L151x6/8/B STM32L152x6/8/B
48/133 DocID17659 Rev 12
5 Memory mapping
The memory map is shown in Figure 9.
Figure 9. Memory map
RESERVED
X
X
X
X#
X
X#
X
X
X
X#
X
X
X#
X#
X
X
!0"MEMORYSPACE
#2#
X
4)-
2ESERVED
X
X
X
X
X
X
4)-
4)-
24#
77$'
)7$'
RESERVED
30)
53!24
53!24
393#&'
4)-
4)-
RESERVED
!$#
RESERVED
53!24
RESERVED
X
X
X#
X
X
RESERVED
RESERVED
30)
)#
X
X#
072
4)-
)#
RESERVED
%84)
RESERVED
2##
&LASH)NTERFACE
RESERVED
RESERVED
RESERVED
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Figure 10. Pin loading conditions Figure 11. Pin input voltage
DocID17659 Rev 12 49/133
STM32L151x6/8/B STM32L152x6/8/B Electrical characteristics
104
6 Electrical characteristics
6.1 Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
6.1.1 Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes. Based on characterization, the minimum and maximum
values refer to sample tests and represent the mean value plus or minus three times the
standard deviation (mean±3σ).
Please refer to device ErrataSheet for possible latest changes of electrical characteristics.
6.1.2 Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.6 V (for the
1.65 V VDD 3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).
6.1.3 Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4 Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 10.
6.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 11.
Figure 10. Pin loading conditions Figure 11. Pin input voltage
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Electrical characteristics STM32L151x6/8/B STM32L152x6/8/B
50/133 DocID17659 Rev 12
6.1.6 Power supply scheme
Figure 12. Power supply scheme
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DocID17659 Rev 12 51/133
STM32L151x6/8/B STM32L152x6/8/B Electrical characteristics
104
6.1.7 Optional LCD power supply scheme
Figure 13. Optional LCD power supply scheme
1. Option 1: LCD power supply is provided by a dedicated VLCD supply source, VSEL switch is open.
2. Option 2: LCD power supply is provided by the internal step-up converter, VSEL switch is closed, an
external capacitance is needed for correct behavior of this converter.
6.1.8 Current consumption measurement
Figure 14. Current consumption measurement scheme
MS32462V1
VDD1/2/.../N
N x 100 nF
+ 1 x 10 μF
Step-up
Converter
VSS1/2/.../N
VDD
100 nF
VLCD
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Electrical characteristics STM32L151x6/8/B STM32L152x6/8/B
52/133 DocID17659 Rev 12
6.2 Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 10: Voltage characteristics,
Table 11: Current characteristics, and Table 12: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Table 10. Voltage characteristics
Symbol Ratings Min Max Unit
VDD–VSS
External main supply voltage
(including VDDA and VDD)(1)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
–0.3 4.0
V
VIN(2)
2. VIN maximum must always be respected. Refer to Tab le 11 for maximum allowed injected current values.
Input voltage on five-volt tolerant pin VSS 0.3 VDD+4.0
Input voltage on any other pin VSS 0.3 4.0
|ΔVDDx| Variations between different VDD power pins - 50
mV
|VSSX VSS| Variations between all different ground pins(3)
3. Include VREF- pin.
-50
VREF+ VDDA Allowed voltage difference for VREF+ > VDDA -0.4V
VESD(HBM)
Electrostatic discharge voltage
(human body model) see Section 6.3.11 -
Table 11. Current characteristics
Symbol Ratings Max. Unit
IVDDΣTotal current into VDD/VDDA power lines (source)(1)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
80
mA
IVSSΣTotal current out of VSS ground lines (sink)(1) 80
IIO
Output current sunk by any I/O and control pin 25
Output current sourced by any I/O and control pin - 25
IINJ(PIN) (2)
2. Negative injection disturbs the analog performance of the device. See note in Section 6.3.17.
Injected current on five-volt tolerant I/O(3)
3. Positive current injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. IINJ(PIN)
must never be exceeded. Refer to Table 10 for maximum allowed input voltage values.
-5/+0
Injected current on any other pin (4)
4. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. IINJ(PIN)
must never be exceeded. Refer to Table 10: Voltage characteristics for the maximum allowed input voltage
values.
± 5
ΣIINJ(PIN) Total injected current (sum of all I/O and control pins)(5)
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).
± 25
DocID17659 Rev 12 53/133
STM32L151x6/8/B STM32L152x6/8/B Electrical characteristics
104
6.3 Operating conditions
6.3.1 General operating conditions
Table 12. Thermal characteristics
Symbol Ratings Value Unit
TSTG Storage temperature range –65 to +150 °C
TJMaximum junction temperature 150 °C
Table 13. General operating conditions
Symbol Parameter Conditions Min Max Unit
fHCLK Internal AHB clock frequency - 0 32
MHzfPCLK1 Internal APB1 clock frequency - 0 32
fPCLK2 Internal APB2 clock frequency - 0 32
VDD Standard operating voltage
BOR detector disabled 1.65 3.6
V
BOR detector enabled,
at power on 1.8 3.6
BOR detector disabled, after
power on 1.65 3.6
VDDA(1)
Analog operating voltage
(ADC and DAC not used) Must be the same voltage as
VDD(2)
1.65 3.6
V
Analog operating voltage
(ADC or DAC used) 1.8 3.6
VIN
Input voltage on FT pins(3)
Input voltage on BOOT0 pin
Input voltage on any other pin
2.0 V VDD 3.6 V
1.65 V VDD 2.0 V
–0.3
–0.3
0
–0.3
5.5
5.25
5.5
VDD+0.3
V
PD
Power dissipation at
TA = 85 °C(4) BGA100 package - 339 mW
TA Temperature range
Maximum power dissipation –40 85
°C
Low power dissipation(5) –40 105
TJ Junction temperature range -40 °C TA 105°C –40 105 °C
1. When the ADC is used, refer to Table 54: ADC characteristics.
2. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and
VDDA can be tolerated during power-up and operation.
3. To sustain a voltage higher than VDD+0.3 V, the internal pull-up/pull-down resistors must be disabled.
4. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJ max (see Table 12: Thermal characteristics
on page 53).
5. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJ max (see Table 12:
Thermal characteristics on page 53).
Electrical characteristics STM32L151x6/8/B STM32L152x6/8/B
54/133 DocID17659 Rev 12
6.3.2 Embedded reset and power control block characteristics
The parameters given in the following table are derived from the tests performed under the
ambient temperature condition summarized in the following table.
Table 14. Embedded reset and power control block characteristics
Symbol Parameter Conditions Min Typ Max Unit
tVDD(1)
VDD rise time rate
BOR detector enabled 0 -
µs/V
BOR detector disabled 0 - 1000
VDD fall time rate
BOR detector enabled 20 -
BOR detector disabled 0 - 1000
TRSTTEMPO(1) Reset temporization
VDD rising, BOR enabled - 2 3.3
ms
VDD rising, BOR disabled(2) 0.4 0.7 1.6
VPOR/PDR
Power on/power down reset
threshold
Falling edge 1 1.5 1.65
V
Rising edge 1.3 1.5 1.65
VBOR0 Brown-out reset threshold 0
Falling edge 1.67 1.7 1.74
V
Rising edge 1.69 1.76 1.8
VBOR1 Brown-out reset threshold 1
Falling edge 1.87 1.93 1.97
Rising edge 1.96 2.03 2.07
VBOR2 Brown-out reset threshold 2
Falling edge 2.22 2.30 2.35
Rising edge 2.31 2.41 2.44
VBOR3 Brown-out reset threshold 3
Falling edge 2.45 2.55 2.60
Rising edge 2.54 2.66 2.7
VBOR4 Brown-out reset threshold 4
Falling edge 2.68 2.8 2.85
Rising edge 2.78 2.9 2.95
DocID17659 Rev 12 55/133
STM32L151x6/8/B STM32L152x6/8/B Electrical characteristics
104
VPVD0
Programmable voltage detector
threshold 0
Falling edge 1.8 1.85 1.88
V
Rising edge 1.88 1.94 1.99
VPVD1 PVD threshold 1
Falling edge 1.98 2.04 2.09
Rising edge 2.08 2.14 2.18
VPVD2 PVD threshold 2
Falling edge 2.20 2.24 2.28
Rising edge 2.28 2.34 2.38
VPVD3 PVD threshold 3
Falling edge 2.39 2.44 2.48
Rising edge 2.47 2.54 2.58
VPVD4 PVD threshold 4
Falling edge 2.57 2.64 2.69
Rising edge 2.68 2.74 2.79
VPVD5 PVD threshold 5
Falling edge 2.77 2.83 2.88
Rising edge 2.87 2.94 2.99
VPVD6 PVD threshold 6
Falling edge 2.97 3.05 3.09
Rising edge 3.08 3.15 3.20
Vhyst Hysteresis voltage
BOR0 threshold - 40 -
mV
All BOR and PVD thresholds
excepting BOR0 -100-
1. Guaranteed by characterization results.
2. Valid for device version without BOR at power up. Please see option "T" in Ordering information scheme for more details.
Table 14. Embedded reset and power control block characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit
Electrical characteristics STM32L151x6/8/B STM32L152x6/8/B
56/133 DocID17659 Rev 12
6.3.3 Embedded internal reference voltage
The parameters given in the following table are based on characterization results, unless
otherwise specified.
Table 15. Embedded internal reference voltage calibration values
Calibration value name Description Memory address
VREFINT_CAL Raw data acquired at
temperature of 30 °C, VDDA= 3 V 0x1FF8 0078-0x1FF8 0079
Table 16. Embedded internal reference voltage
Symbol Parameter Conditions Min Typ Max Unit
VREFINT out(1) Internal reference voltage – 40 °C < TJ < +105 °C 1.202 1.224 1.242 V
IREFINT
Internal reference current
consumption - - 1.4 2.3 µA
TVREFINT Internal reference startup time - - 2 3 ms
VVREF_MEAS
VDDA and VREF+voltage during
VREFINT factory measure - 2.99 3 3.01 V
AVREF_MEAS
Accuracy of factory-measured VREF
value (2)
Including uncertainties
due to ADC and
VDDA/VREF+ values
--±5 mV
TCoeff(3) Temperature coefficient –40 °C < TJ < +105 °C - 25 100 ppm/°C
ACoeff(3) Long-term stability 1000 hours, T= 25 °C - - 1000 ppm
VDDCoeff(3) Voltage coefficient 3.0 V < VDDA < 3.6 V - - 2000 ppm/V
TS_vrefint(3)(4) ADC sampling time when reading the
internal reference voltage -510-µs
TADC_BUF(3) Startup time of reference voltage
buffer for ADC ---10µs
IBUF_ADC(3) Consumption of reference voltage
buffer for ADC - - 13.5 25 µA
IVREF_OUT(3) VREF_OUT output current(5) ---1µA
CVREF_OUT(3) VREF_OUT output load - - - 50 pF
ILPBUF(3) Consumption of reference voltage
buffer for VREF_OUT and COMP - - 730 1200 nA
VREFINT_DIV1(3) 1/4 reference voltage - 24 25 26
% VREFINT
VREFINT_DIV2(3) 1/2 reference voltage - 49 50 51
VREFINT_DIV3(3) 3/4 reference voltage - 74 75 76
1. Tested in production.
2. The internal VREF value is individually measured in production and stored in dedicated EEPROM bytes.
3. Guaranteed by characterization results.
4. Shortest sampling time can be determined in the application by multiple iterations.
5. To guarantee less than 1% VREF_OUT deviation.
DocID17659 Rev 12 57/133
STM32L151x6/8/B STM32L152x6/8/B Electrical characteristics
104
6.3.4 Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code. The current consumption is measured as described in Figure 14: Current
consumption measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to Dhrystone 2.1 code.
The current consumption values are derived from the tests performed under ambient
temperature TA=25°C and VDD supply voltage conditions summarized in Table 13: General
operating conditions, unless otherwise specified. The MCU is placed under the following
conditions:
The MCU is placed under the following conditions:
VDD = 3.6 V
All I/O pins are configured in analog input mode.
All peripherals are disabled except when explicitly mentioned
The Flash memory access time, 64-bit access and prefetch is adjusted depending on
fHCLK frequency and voltage range to provide the best CPU performance.
When the peripherals are enabled fAPB1 = fAPB2 = fAHB
When PLL is ON, the PLL inputs are equal to HSI = 16 MHz (if internal clock is used) or
HSE = 16 MHz (if HSE bypass mode is used).
The HSE user clock applied to OSC_IN input follows the characteristics specified in
Table 26: High-speed external user clock characteristics.
Electrical characteristics STM32L151x6/8/B STM32L152x6/8/B
58/133 DocID17659 Rev 12
Table 17. Current consumption in Run mode, code with data processing running from Flash
Symbol Parameter Conditions fHCLK Typ
Max(1)
Unit
55 °C 85 °C 105 °C
IDD (Run
from
Flash)
Supply
current in
Run mode,
code
executed
from Flash
fHSE = fHCLK
up to 16 MHz,
included
fHSE = fHCLK/2
above 16 MHz
(PLL ON)(2)
Range 3,
VCORE=1.2 V
VOS[1:0] = 11
1 MHz 270 400 400 400
µA2 MHz 470 600 600 600
4 MHz 890 1025 1025 1025
Range 2,
VCORE=1.5 V
VOS[1:0] = 10
4 MHz 1 1.3 1.3 1.3
mA
8 MHz 2 2.5 2.5 2.5
16 MHz 3.9 5 5 5
Range 1,
VCORE=1.8 V
VOS[1:0] = 01
8 MHz 2.16 3 3 3
16 MHz 4.8 5.5 5.5 5.5
32 MHz 9.6 11 11 11
HSI clock source
(16 MHz)
Range 2,
VCORE=1.5 V
VOS[1:0] = 10
16 MHz 4 5 5 5
Range 1,
VCORE=1.8 V
VOS[1:0] = 01
32 MHz 9.4 11 11 11
MSI clock, 65 kHz Range 3,
VCORE=1.2 V
VOS[1:0] = 11
65 kHz 0.05 0.085 0.09 0.1
MSI clock, 524 kHz 524 kHz 0.15 0.185 0.19 0.2
MSI clock, 4.2 MHz 4.2 MHz 0.9 1 1 1
1. Guaranteed by characterization results, unless otherwise specified.
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).
DocID17659 Rev 12 59/133
STM32L151x6/8/B STM32L152x6/8/B Electrical characteristics
104
Table 18. Current consumption in Run mode, code with data processing running from RAM
Symbol Parameter Conditions fHCLK Typ
Max(1)
Unit
55 °C 85 °C 105 °C
IDD (Run
from
RAM)
Supply current
in Run mode,
code executed
from RAM,
Flash switched
off
fHSE = fHCLK
up to 16 MHz,
included
fHSE = fHCLK/2
above 16 MHz
(PLL ON)(2)
Range 3,
VCORE=1.2 V
VOS[1:0] = 11
1 MHz 200 300 300 300
µA2 MHz 380 500 500 500
4 MHz 720 860 860 860(3)
Range 2,
VCORE=1.5 V
VOS[1:0] = 10
4 MHz 0.9 1 1 1
mA
8 MHz 1.65 2 2 2
16 MHz 3.2 3.7 3.7 3.7
Range 1,
VCORE=1.8 V
VOS[1:0] = 01
8 MHz 2 2.5 2.5 2.5
16 MHz 4 4.5 4.5 4.5
32 MHz 7.7 8.5 8.5 8.5
HSI clock source
(16 MHz)
Range 2,
VCORE=1.5 V
VOS[1:0] = 10
16 MHz 3.3 3.8 3.8 3.8
Range 1,
VCORE=1.8 V
VOS[1:0] = 01
32 MHz 7.8 9.2 9.2 9.2
MSI clock, 65 kHz Range 3,
VCORE=1.2 V
VOS[1:0] = 11
65 kHz 40 60 60 80
µAMSI clock, 524 kHz 524 kHz 110 140 140 160
MSI clock, 4.2 MHz 4.2 MHz 700 800 800 820
1. Guaranteed by characterization results, unless otherwise specified.
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).
3. Tested in production.
Electrical characteristics STM32L151x6/8/B STM32L152x6/8/B
60/133 DocID17659 Rev 12
Table 19. Current consumption in Sleep mode
Symbol Parameter Conditions fHCLK Typ
Max(1)
Unit
55 °C 85 °C 105 °C
IDD
(Sleep)
Supply
current in
Sleep
mode,
code
executed
from RAM,
Flash
switched
OFF
fHSE = fHCLK up to
16 MHz included,
fHSE = fHCLK/2
above 16 MHz (PLL
ON)(2)
Range 3,
VCORE=1.2 V
VOS[1:0] = 11
1 MHz 80 140 140 140
µA
2 MHz 150 210 210 210
4 MHz 280 330 330 330(3)
Range 2,
VCORE=1.5 V
VOS[1:0] = 10
4 MHz 280 400 400 400
8 MHz 450 550 550 550
16 MHz 900 1050 1050 1050
Range 1,
VCORE=1.8 V
VOS[1:0] = 01
8 MHz 550 650 650 650
16 MHz 1050 1200 1200 1200
32 MHz 2300 2500 2500 2500
HSI clock source
(16 MHz)
Range 2,
VCORE=1.5 V
VOS[1:0] = 10
16 MHz 1000 1100 1100 1100
Range 1,
VCORE=1.8 V
VOS[1:0] = 01
32 MHz 2300 2500 2500 2500
MSI clock, 65 kHz Range 3,
VCORE=1.2 V
VOS[1:0] = 11
65 kHz 30 50 50 60
MSI clock, 524 kHz 524 kHz 50 70 70 80
MSI clock, 4.2 MHz 4.2 MHz 200 240 240 250
Supply
current in
Sleep
mode,
code
executed
from Flash
fHSE = fHCLK up to
16 MHz included,
fHSE = fHCLK/2
above 16 MHz (PLL
ON)(2)
Range 3,
VCORE=1.2 V
VOS[1:0] = 11
1 MHz 80 140 140 140
µA
2 MHz 150 210 210 210
4 MHz 290 350 350 350
Range 2,
VCORE=1.5 V
VOS[1:0] = 10
4 MHz 300 400 400 400
8 MHz 500 600 600 600
16 MHz 1000 1100 1100 1100
Range 1,
VCORE=1.8 V
VOS[1:0] = 01
8 MHz 550 650 650 650
16 MHz 1050 1200 1200 1200
32 MHz 2300 2500 2500 2500
HSI clock source
(16 MHz)
Range 2,
VCORE=1.5 V
VOS[1:0] = 10
16 MHz 1000 1100 1100 1100
Range 1,
VCORE=1.8 V
VOS[1:0] = 01
32 MHz 2300 2500 2500 2500
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STM32L151x6/8/B STM32L152x6/8/B Electrical characteristics
104
IDD
(Sleep)
Supply
current in
Sleep
mode,
code
executed
from Flash
MSI clock, 65 kHz
Range 3,
VCORE=1.2V
VOS[1:0] = 11
65 kHz 40 70 70 80
µA
MSI clock, 524 kHz 524 kHz 60 90 90 100
MSI clock, 4.2 MHz 4.2 MHz 210 250 250 260
1. Guaranteed by characterization results, unless otherwise specified.
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register)
3. Tested in production
Table 19. Current consumption in Sleep mode (continued)
Symbol Parameter Conditions fHCLK Typ
Max(1)
Unit
55 °C 85 °C 105 °C
Electrical characteristics STM32L151x6/8/B STM32L152x6/8/B
62/133 DocID17659 Rev 12
Table 20. Current consumption in Low power run mode
Symbol Parameter Conditions Typ Max
(1) Unit
IDD (LP
Run)
Supply
current in
Low power
run mode
All
peripherals
OFF, code
executed
from RAM,
Flash
switched
OFF, VDD
from 1.65 V
to 3.6 V
MSI clock, 65 kHz
fHCLK = 32 kHz
TA = -40 °C to 25 °C 9 12
µA
TA = 85 °C 17.5 24
TA = 105 °C 31 46
MSI clock, 65 kHz
fHCLK = 65 kHz
TA = -40 °C to 25 °C 14 17
TA = 85 °C 22 29
TA = 105 °C 35 51
MSI clock, 131 kHz
fHCLK = 131 kHz
TA = -40 °C to 25 °C 37 42
TA = 55 °C 37 42
TA = 85 °C 37 42
TA = 105 °C 48 65
All
peripherals
OFF, code
executed
from Flash,
VDD from
1.65 V to
3.6 V
MSI clock, 65 kHz
fHCLK = 32 kHz
TA = -40 °C to 25 °C 24 32
TA = 85 °C 33 42
TA = 105 °C 48 64
MSI clock, 65 kHz
fHCLK = 65 kHz
TA = -40 °C to 25 °C 31 40
TA = 85 °C 40 48
TA = 105 °C 54 70
MSI clock, 131 kHz
fHCLK = 131 kHz
TA = -40 °C to 25 °C 48 58
TA = 55 °C 54 63
TA = 85 °C 56 65
TA = 105 °C 70 90
IDD Max
(LP
Run)(2)
Max allowed
current in
Low power
run mode
VDD from
1.65 V to
3.6 V
- - - 200
1. Guaranteed by characterization results, unless otherwise specified.
2. This limitation is related to the consumption of the CPU core and the peripherals that are powered by the regulator.
Consumption of the I/Os is not included in this limitation.
DocID17659 Rev 12 63/133
STM32L151x6/8/B STM32L152x6/8/B Electrical characteristics
104
Table 21. Current consumption in Low power sleep mode
Symbol Parameter Conditions Typ Max
(1)
1. Guaranteed by characterization results, unless otherwise specified.
Unit
IDD (LP
Sleep)
Supply
current in
Low power
sleep
mode
All
peripherals
OFF, VDD
from 1.65 V
to 3.6 V
MSI clock, 65 kHz
fHCLK = 32 kHz
Flash OFF
TA = -40 °C to 25 °C 4.4 -
µA
MSI clock, 65 kHz
fHCLK = 32 kHz
Flash ON
TA = -40 °C to 25 °C 17.5 25
TA = 85 °C 22 27
TA = 105 °C 31 39
MSI clock, 65 kHz
fHCLK = 65 kHz,
Flash ON
TA = -40 °C to 25 °C 18 26
TA = 85 °C 23 28
TA = 105 °C 31 40
MSI clock, 131 kHz
fHCLK = 131 kHz,
Flash ON
TA = -40 °C to 25 °C 22 30
TA = 55 °C 24 32
TA = 85 °C 26 34
TA = 105 °C 34 45
TIM9 and
USART1
enabled,
Flash ON,
VDD from
1.65 V to
3.6 V
MSI clock, 65 kHz
fHCLK = 32 kHz
TA = -40 °C to 25 °C 17.5 25
TA = 85 °C 22 27
TA = 105 °C 31 39
MSI clock, 65 kHz
fHCLK = 65 kHz
TA = -40 °C to 25 °C 18 26
TA = 85 °C 23 28
TA = 105 °C 31 40
MSI clock, 131 kHz
fHCLK = 131 kHz
TA = -40 °C to 25 °C 22 30
TA = 55 °C 24 32
TA = 85 °C 26 34
TA = 105 °C 34 45
IDD Max
(LP Sleep)
Max
allowed
current in
Low power
Sleep
mode
VDD from
1.65 V to
3.6 V
---200
Electrical characteristics STM32L151x6/8/B STM32L152x6/8/B
64/133 DocID17659 Rev 12
Table 22. Typical and maximum current consumptions in Stop mode
Symbol Parameter Conditions Typ
(1)
Max
(1)(2) Unit
IDD (Stop
with RTC)
Supply current
in Stop mode
with RTC
enabled
RTC clocked by LSI,
regulator in LP mode,
HSI and HSE OFF
(no independent
watchdog)
LCD
OFF
TA = -40°C to 25°C
VDD = 1.8 V 1.2 2.75
µA
TA = -40°C to 25°C 1.4 4
TA = 55°C 2.6 6
TA= 85°C 4.8 10
TA = 105°C 10.2 23
LCD ON
(static
duty)(3)
TA = -40°C to 25°C 3.3 6
TA = 55°C 4.5 8
TA= 85°C 6.6 12
TA = 105°C 13.6 27
LCD ON
(1/8
duty)(4)
TA = -40°C to 25°C 7.7 10
TA = 55°C 8.6 12
TA= 85°C 10.7 16
TA = 105°C 19.8 40
RTC clocked by LSE
external clock (32.768
kHz), regulator in LP
mode, HSI and HSE
OFF (no independent
watchdog)
LCD
OFF
TA = -40°C to 25°C 1.6 4
TA = 55°C 2.7 6
TA= 85°C 4.8 10
TA = 105°C 10.3 23
LCD ON
(static
duty)(3)
TA = -40°C to 25°C 3.6 6
TA = 55°C 4.6 8
TA= 85°C 6.7 12
TA = 105°C 10.9 23
LCD ON
(1/8
duty)(4)
TA = -40°C to 25°C 7.6 10
TA = 55°C 8.6 12
TA= 85°C 10.7 16
TA = 105°C 19.8 40
RTC clocked by LSE
(no independent
watchdog)(5)
LCD
OFF
TA = -40°C to 25°C
VDD = 1.8 V 1.45 -
TA = -40°C to 25°C
VDD = 3.0 V 1.9 -
TA = -40°C to 25°C
VDD = 3.6 V 2.2 -
DocID17659 Rev 12 65/133
STM32L151x6/8/B STM32L152x6/8/B Electrical characteristics
104
IDD (Stop)
Supply current
in Stop mode
(RTC
disabled)
Regulator in LP mode, HSI and
HSE OFF, independent
watchdog and LSI enabled
TA = -40°C to 25°C 1.1 2.2
µA
Regulator in LP mode, LSI, HSI
and HSE OFF (no independent
watchdog)
TA = -40°C to 25°C 0.5 0.9
TA = 55°C 1.9 5
TA= 85°C 3.7 8
TA = 105°C 8.9 20(6)
IDD (WU
from Stop)
RMS (root
mean square)
supply current
during wakeup
time when
exiting from
Stop mode
MSI = 4.2 MHz
VDD = 3.0 V
TA = -40°C to 25°C
2-
mA
MSI = 1.05 MHz 1.45 -
MSI = 65 kHz(7) 1.45 -
1. The typical values are given for VDD = 3.0 V and max values are given for VDD = 3.6 V, unless otherwise
specified.
2. Guaranteed by characterization results, unless otherwise specified
3. LCD enabled with external VLCD, static duty, division ratio = 256, all pixels active, no LCD connected
4. LCD enabled with external VLCD, 1/8 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD
connected.
5. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY)
with two 6.8pF loading capacitors.
6. Tested in production
7. When MSI = 64 kHz, the RMS current is measured over the first 15 µs following the wakeup event. For the
remaining time of the wakeup period, the current is similar to the Run mode current.
Table 22. Typical and maximum current consumptions in Stop mode (continued)
Symbol Parameter Conditions Typ
(1)
Max
(1)(2) Unit
Electrical characteristics STM32L151x6/8/B STM32L152x6/8/B
66/133 DocID17659 Rev 12
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in the following table. The MCU
is placed under the following conditions:
all I/O pins are in input mode with a static value at VDD or VSS (no load)
all peripherals are disabled unless otherwise mentioned
the given value is calculated by measuring the current consumption
with all peripherals clocked off
with only one peripheral clocked on
Table 23. Typical and maximum current consumptions in Standby mode
Symbol Parameter Conditions Typ(1) Max
(1)(2) Unit
IDD
(Standby
with RTC)
Supply current in Standby
mode with RTC enabled
RTC clocked by LSI (no
independent watchdog)
TA = -40 °C to 25 °C
VDD = 1.8 V 0.9 -
µA
TA = -40 °C to 25 °C 1.1 1.8
TA = 55 °C 1.42 2.5
TA= 85 °C 1.87 3
TA = 105 °C 2.78 5
RTC clocked by LSE (no
independent watchdog)(3)
TA = -40 °C to 25 °C
VDD = 1.8 V 1-
TA = -40 °C to 25 °C 1.33 2.9
TA = 55 °C 1.59 3.4
TA= 85 °C 2.01 4.3
TA = 105 °C 3.27 6.3
IDD
(Standby)
Supply current in Standby
mode with RTC disabled
Independent watchdog
and LSI enabled TA = -40 °C to 25 °C 1.1 1.6
Independent watchdog
and LSI OFF
TA = -40 °C to 25 °C 0.3 0.55
TA = 55 °C 0.5 0.8
TA = 85 °C 1 1.7
TA = 105 °C 2.5 4(4)
IDD (WU
from
Standby)
RMS supply current during
wakeup time when exiting
from Standby mode
-VDD = 3.0 V
TA = -40 °C to 25 °C 1-
1. The typical values are given for VDD = 3.0 V and max values are given for VDD = 3.6 V, unless otherwise specified.
2. Guaranteed by characterization results, unless otherwise specified.
3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8pF
loading capacitors.
4. Tested in production.
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STM32L151x6/8/B STM32L152x6/8/B Electrical characteristics
104
Table 24. Peripheral current consumption(1)
Peripheral
Typical consumption, VDD = 3.0 V, TA = 25 °C
Unit
Range 1,
VCORE=1.8 V
VOS[1:0] = 01
Range 2,
VCORE=1.5 V
VOS[1:0] = 10
Range 3,
VCORE=1.2 V
VOS[1:0] = 11
Low power
sleep and run
APB1
TIM2 13 10.5 8 10.5
µA/MHz
(fHCLK)
TIM3 14 12 9 12
TIM4 12.5 10.5 8 11
TIM6 5.5 4.5 3.5 4.5
TIM7 5.5 5 3.5 4.5
LCD 5.553.55
WWDG 4 3.5 2.5 3.5
SPI2 5.5 5 4 5
USART2 9 8 5.5 8.5
USART3 10.5 9 6 8
I2C1 8.5 7 5.5 7.5
I2C2 8.5 7 5.5 6.5
USB 12.5 10 6.5 10
PWR 4.5 4 3 3.5
DAC 9 7.5 6 7
COMP 4.5 4 3.5 4.5
APB2
SYSCFG & RI 3 2.5 2 2.5
µA/MHz
(fHCLK)
TIM9 9 7.5 6 7
TIM10 6.5 5.5 4.5 5.5
TIM11 7 6 4.5 5.5
ADC(2) 11.5 9.5 8 9
SPI1 5 4.5 3 4
USART197.567.5
Electrical characteristics STM32L151x6/8/B STM32L152x6/8/B
68/133 DocID17659 Rev 12
AHB
GPIOA 5 4.5 3.5 4
µA/MHz
(fHCLK)
GPIOB 5 4.5 3.5 4.5
GPIOC 5 4.5 3.5 4.5
GPIOD 5 4.5 3.5 4.5
GPIOE 5 4.5 3.5 4.5
GPIOH 4 4 3 3.5
CRC 1 0.5 0.5 0.5
FLASH 13 11.5 9 18.5
DMA1 12 10 8 10.5
All enabled 166 138 106 130
IDD (RTC) 0.47
µA
IDD (LCD) 3.1
IDD (ADC)(3) 1450
IDD (DAC)(4) 340
IDD (COMP1) 0.16
IDD (COMP2)
Slow mode 2
Fast mode 5
IDD (PVD / BOR)(5) 2.6
IDD (IWDG) 0.25
1. Data based on differential IDD measurement between all peripherals OFF an one peripheral with clock enabled, in the
following conditions: fHCLK = 32 MHz (Range 1), fHCLK = 16 MHz (Range 2), fHCLK = 4 MHz (Range 3), fHCLK = 64kHz
(Low power run/sleep), fAPB1 = fHCLK, fAPB2 = fHCLK, default prescaler value for each peripheral. The CPU is in Sleep
mode in both cases. No I/O pins toggling.
2. HSI oscillator is OFF for this measure.
3. Data based on a differential IDD measurement between ADC in reset configuration and continuous ADC conversion (HSI
consumption not included).
4. Data based on a differential IDD measurement between DAC in reset configuration and continuous DAC conversion of
VDD/2. DAC is in buffered mode, output is left floating.
5. Including supply current of internal reference voltage.
Table 24. Peripheral current consumption(1) (continued)
Peripheral
Typical consumption, VDD = 3.0 V, TA = 25 °C
Unit
Range 1,
VCORE=1.8 V
VOS[1:0] = 01
Range 2,
VCORE=1.5 V
VOS[1:0] = 10
Range 3,
VCORE=1.2 V
VOS[1:0] = 11
Low power
sleep and run
DocID17659 Rev 12 69/133
STM32L151x6/8/B STM32L152x6/8/B Electrical characteristics
104
6.3.5 Wakeup time from Low power mode
The wakeup times given in the following table are measured with the MSI RC oscillator. The
clock source used to wake up the device depends on the current operating mode:
Sleep mode: the clock source is the clock that was set before entering Sleep mode
Stop mode: the clock source is the MSI oscillator in the range configured before
entering Stop mode
Standby mode: the clock source is the MSI oscillator running at 2.1 MHz
All timings are derived from tests performed under ambient temperature and VDD supply
voltage conditions summarized in Table 13.
Table 25. Low-power mode wakeup timings
Symbol Parameter Conditions Typ Max(1)
1. Guaranteed by characterization results, unless otherwise specified
Unit
tWUSLEEP Wakeup from Sleep mode fHCLK = 32 MHz 0.36 -
µs
tWUSLEEP_LP
Wakeup from Low power
sleep mode
fHCLK = 262 kHz
fHCLK = 262 kHz
Flash enabled 32 -
fHCLK = 262 kHz
Flash switched OFF 34 -
tWUSTOP
Wakeup from Stop mode,
regulator in Run mode fHCLK = fMSI = 4.2 MHz 8.2 -
Wakeup from Stop mode,
regulator in low power
mode
fHCLK = fMSI = 4.2 MHz
Voltage Range 1 and 2 8.2 9.3
fHCLK = fMSI = 4.2 MHz
Voltage Range 3 7.8 11.2
fHCLK = fMSI = 2.1 MHz 10 12
fHCLK = fMSI = 1.05 MHz 15.5 20
fHCLK = fMSI = 524 kHz 29 35
fHCLK = fMSI = 262 kHz 53 63
fHCLK = fMSI = 131 kHz 105 118
fHCLK = MSI = 65 kHz 210 237
tWUSTDBY
Wakeup from Standby
mode
FWU bit = 1
fHCLK = MSI = 2.1 MHz 50 103
Wakeup from Standby
mode
FWU bit = 0
fHCLK = MSI = 2.1 MHz 2.5 3.2 ms
Electrical characteristics STM32L151x6/8/B STM32L152x6/8/B
70/133 DocID17659 Rev 12
6.3.6 External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO. The
external clock signal has to respect the I/O characteristics in Section 6.3.13. However, the
recommended clock input waveform is shown in Figure 15: High-speed external clock
source AC timing diagram.
Figure 15. High-speed external clock source AC timing diagram
Table 26. High-speed external user clock characteristics(1)
1. Guaranteed by design.
Symbol Parameter Conditions Min Typ Max Unit
fHSE_ext
User external clock source
frequency
CSS is on or
PLL is used 1
832MHz
CSS is off, PLL
not used 0
VHSEH OSC_IN input pin high level voltage
-
0.7VDD -V
DD V
VHSEL OSC_IN input pin low level voltage VSS -0.3V
DD
tw(HSEH)
tw(HSEL)
OSC_IN high or low time 12 - -
ns
tr(HSE)
tf(HSE)
OSC_IN rise or fall time - - 20
Cin(HSE) OSC_IN input capacitance - - 2.6 - pF
DuCy(HSE) Duty cycle - 45 - 55 %
ILOSC_IN Input leakage current VSS VIN VDD --±1µA
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DocID17659 Rev 12 71/133
STM32L151x6/8/B STM32L152x6/8/B Electrical characteristics
104
Low-speed external user clock generated from an external source
The characteristics given in the following table result from tests performed using a low-
speed external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 13.
Figure 16. Low-speed external clock source AC timing diagram
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 1 to 24 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 28. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
Table 27. Low-speed external user clock characteristics(1)
1. Guaranteed by design.
Symbol Parameter Conditions Min Typ Max Unit
fLSE_ext
User external clock source
frequency
-
1 32.768 1000 kHz
VLSEH
OSC32_IN input pin high level
voltage 0.7VDD -V
DD
V
VLSEL
OSC32_IN input pin low level
voltage VSS -0.3V
DD
tw(LSEH)
tw(LSEL)
OSC32_IN high or low time 465 - -
ns
tr(LSE)
tf(LSE)
OSC32_IN rise or fall time - - 10
CIN(LSE) OSC32_IN input capacitance - - 0.6 - pF
DuCy(LSE) Duty cycle - 45 - 55 %
ILOSC32_IN Input leakage current VSS VIN VDD --±1µA
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Electrical characteristics STM32L151x6/8/B STM32L152x6/8/B
72/133 DocID17659 Rev 12
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 17). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2. Refer to the application note AN2867 “Oscillator design guide for ST
microcontrollers” available from the ST website www.st.com.
Table 28. HSE oscillator characteristics(1)(2)
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Guaranteed by characterization results.
Symbol Parameter Conditions Min Typ Max Unit
fOSC_IN Oscillator frequency - 1 24 MHz
RFFeedback resistor - 200 - kΩ
C
Recommended load
capacitance versus
equivalent serial resistance
of the crystal (RS)(3)
3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a
humid environment, due to the induced leakage and the bias condition change. However, it is
recommended to take this point into account if the MCU is used in tough humidity conditions.
RS = 30 Ω -20 - pF
IHSE HSE driving current VDD= 3.3 V, VIN = VSS
with 30 pF load -- 3 mA
IDD(HSE)
HSE oscillator power
consumption
C = 20 pF
fOSC = 16 MHz -- 2.5 (startup)
0.7 (stabilized)
mA
C = 10 pF
fOSC = 16 MHz -- 2.5 (startup)
0.46 (stabilized)
gmOscillator transconductance Startup 3.5 - - mA
/V
tSU(HSE)
(4)
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer.
Startup time VDD is stabilized - 1 - ms
DocID17659 Rev 12 73/133
STM32L151x6/8/B STM32L152x6/8/B Electrical characteristics
104
Figure 17. HSE oscillator circuit diagram
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 29. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
Table 29. LSE oscillator characteristics (fLSE = 32.768 kHz)(1)
1. Guaranteed by characterization results.
Symbol Parameter Conditions Min Typ Max Unit
fLSE
Low speed external oscillator
frequency - - 32.768 - kHz
RFFeedback resistor - - 1.2 - MΩ
C(2)
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator
design guide for ST microcontrollers”.
Recommended load capacitance
versus equivalent serial
resistance of the crystal (RS)(3)
3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with
small RS value for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details.
RS = 30 kΩ-8 -pF
ILSE LSE driving current VDD = 3.3 V, VIN = VSS --1.1µA
IDD (LSE)
LSE oscillator current
consumption
VDD = 1.8 V - 450 -
nAVDD = 3.0 V - 600 -
VDD = 3.6V - 750 -
gmOscillator transconductance - 3 - - µA/V
tSU(LSE)(4) Startup time VDD is stabilized - 1 - s
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Note: For CL1 and CL2, it is recommended to use high-quality ceramic capacitors in the 5 pF to
15 pF range selected to match the requirements of the crystal or resonator (see Figure 18 ).
CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load
capacitance which is the series combination of CL1 and CL2.
Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray
where Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically,
it is between 2 pF and 7 pF.
Caution: To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended
to use a resonator with a load capacitance CL 7 pF. Never use a resonator with a load
capacitance of 12.5 pF.
Example: if a resonator is chosen with a load capacitance of CL = 6 pF and Cstray = 2 pF,
then CL1 = CL2 = 8 pF.
Figure 18. Typical application with a 32.768 kHz crystal
4. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized
32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary
significantly with the crystal manufacturer.
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6.3.7 Internal clock source characteristics
The parameters given in the following table are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 13.
High-speed internal (HSI) RC oscillator
Low-speed internal (LSI) RC oscillator
Table 30. HSI oscillator characteristics
Symbol Parameter Conditions Min Typ Max Unit
fHSI Frequency VDD = 3.0 V - 16 - MHz
TRIM(1)(2)
1. The trimming step differs depending on the trimming code. It is usually negative on the codes which are
multiples of 16 (0x00, 0x10, 0x20, 0x30...0xE0).
HSI user-trimmed
resolution
Trimming code is not a multiple of 16 - ± 0.4 0.7 %
Trimming code is a multiple of 16 - - ± 1.5 %
ACCHSI(2)
2. Guaranteed by characterization results.
Accuracy of the
factory-calibrated
HSI oscillator
VDDA = 3.0 V, TA = 25 °C -1(3)
3. Tested in production.
-1
(3) %
VDDA = 3.0 V, TA = 0 to 55 °C -1.5 - 1.5 %
VDDA = 3.0 V, TA = -10 to 70 °C -2 - 2 %
VDDA = 3.0 V, TA = -10 to 85 °C -2.5 - 2 %
VDDA = 3.0 V, TA = -10 to 105 °C -4 - 2 %
VDDA = 1.65 V to 3.6 V
TA = -40 to 105 °C -4 - 3 %
tSU(HSI)(2) HSI oscillator
startup time - - 3.7 6 µs
IDD(HSI)(2) HSI oscillator
power consumption - - 100 140 µA
Table 31. LSI oscillator characteristics
Symbol Parameter Min Typ Max Unit
fLSI(1)
1. Tested in production.
LSI frequency 26 38 56 kHz
DLSI(2)
2. This is a deviation for an individual part, once the initial frequency has been measured.
LSI oscillator frequency drift
0°C TA 85°C -10 - 4 %
tsu(LSI)(3)
3. Guaranteed by design.
LSI oscillator startup time - - 200 µs
IDD(LSI)(3) LSI oscillator power consumption - 400 510 nA
Electrical characteristics STM32L151x6/8/B STM32L152x6/8/B
76/133 DocID17659 Rev 12
Multi-speed internal (MSI) RC oscillator
Table 32. MSI oscillator characteristics
Symbol Parameter Condition Typ Max Unit
fMSI
Frequency after factory calibration, done at
VDD= 3.3 V and TA = 25 °C
MSI range 0 65.5 -
kHz
MSI range 1 131 -
MSI range 2 262 -
MSI range 3 524 -
MSI range 4 1.05 -
MHzMSI range 5 2.1 -
MSI range 6 4.2 -
ACCMSI Frequency error after factory calibration - ±0.5 - %
DTEMP(MSI)(1) MSI oscillator frequency drift
0 °C TA 85 °C -±3-%
DVOLT(MSI)(1) MSI oscillator frequency drift
1.65 V VDD 3.6 V, TA = 25 °C --2.5%/V
IDD(MSI)(2) MSI oscillator power consumption
MSI range 0 0.75 -
µA
MSI range 1 1 -
MSI range 2 1.5 -
MSI range 3 2.5 -
MSI range 4 4.5 -
MSI range 5 8 -
MSI range 6 15 -
tSU(MSI) MSI oscillator startup time
MSI range 0 30 -
µs
MSI range 1 20 -
MSI range 2 15 -
MSI range 3 10 -
MSI range 4 6 -
MSI range 5 5 -
MSI range 6,
Voltage range 1
and 2
3.5 -
MSI range 6,
Voltage range 3 5-
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104
6.3.8 PLL characteristics
The parameters given in Table 33 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 13.
tSTAB(MSI)(2) MSI oscillator stabilization time
MSI range 0 - 40
µs
MSI range 1 - 20
MSI range 2 - 10
MSI range 3 - 4
MSI range 4 - 2.5
MSI range 5 - 2
MSI range 6,
Voltage range 1
and 2
-2
MSI range 3,
Voltage Range 3 -3
fOVER(MSI) MSI oscillator frequency overshoot
Any range to
range 5 -4
MHz
Any range to
range 6 -6
1. This is a deviation for an individual part, once the initial frequency has been measured.
2. Guaranteed by characterization results.
Table 32. MSI oscillator characteristics (continued)
Symbol Parameter Condition Typ Max Unit
Table 33. PLL characteristics
Symbol Parameter
Value
Unit
Min Typ Max(1)
1. Guaranteed by characterization results.
fPLL_IN
PLL input clock(2)
2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT
.
2- 24MHz
PLL input clock duty cycle 45 - 55 %
fPLL_OUT PLL output clock 2 - 32 MHz
tLOCK
Worst case PLL lock time
PLL input = 2 MHz
PLL VCO = 96 MHz
- 100 130 µs
Jitter Cycle-to-cycle jitter - - ± 600 ps
IDDA(PLL) Current consumption on VDDA - 220 450
µA
IDD(PLL) Current consumption on VDD - 120 150
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78/133 DocID17659 Rev 12
6.3.9 Memory characteristics
The characteristics are given at TA = -40 to 105 °C unless otherwise specified.
RAM memory
Flash memory and data EEPROM
Table 34. RAM and hardware registers
Symbol Parameter Conditions Min Typ Max Unit
VRM Data retention mode(1)
1. Minimum supply voltage without losing data stored in RAM (in Stop mode or under Reset) or in hardware
registers (only in Stop mode).
STOP mode (or RESET) 1.65 - - V
Table 35. Flash memory and data EEPROM characteristics
Symbol Parameter Conditions Min Typ Max(1)
1. Guaranteed by design.
Unit
VDD
Operating voltage
Read / Write / Erase -1.65-3.6V
tprog
Programming / erasing time for
byte / word / double word / half-
page
Erasing - 3.28 3.94
ms
Programming - 3.28 3.94
IDD
Average current during whole
program/erase operation
TA = 25 °C, VDD = 3.6 V
-300-µA
Maximum current (peak) during
program/erase operation -1.52.5mA
Table 36. Flash memory, data EEPROM endurance and data retention
Symbol Parameter Conditions
Value
Unit
Min(1)
1. Guaranteed by characterization results.
Typ Max
NCYC(2)
Cycling (erase / write)
Program memory TA = -40°C to
105 °C
10 --
kcycles
Cycling (erase / write)
EEPROM data memory 300 - -
tRET(2)
2. Characterization is done according to JEDEC JESD22-A117.
Data retention (program memory) after
10 kcycles at TA = 85 °C
TRET = +85 °C
30 - -
years
Data retention (EEPROM data memory)
after 300 kcycles at TA = 85 °C 30 - -
Data retention (program memory) after
10 kcycles at TA = 105 °C
TRET = +105 °C
10 - -
Data retention (EEPROM data memory)
after 300 kcycles at TA = 105 °C 10 - -
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6.3.10 EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 37. They are based on the EMS levels and classes
defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
Corrupted program counter
Unexpected reset
Critical data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the oscillator pins for 1
second.
Table 37. EMS characteristics
Symbol Parameter Conditions Level/
Class
VFESD
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
VDD = 3.3 V, LQFP100, TA = +25 °C,
fHCLK = 32 MHz
conforms to IEC 61000-4-2
2B
VEFTB
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD = 3.3 V, LQFP100, TA = +25
°C,
fHCLK = 32 MHz
conforms to IEC 61000-4-4
4A
Electrical characteristics STM32L151x6/8/B STM32L152x6/8/B
80/133 DocID17659 Rev 12
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
6.3.11 Electrical sensitivity characteristics
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Table 38. EMI characteristics
Symbol Parameter Conditions Monitored
frequency band
Max vs. frequency range
Unit
4 MHz
voltage
Range 3
16 MHz
voltage
Range 2
32 MHz
voltage
Range 1
SEMI Peak level
VDD = 3.3 V,
TA = 25 °C,
LQFP100 package
compliant with IEC
61967-2
0.1 to 30 MHz 3 -6 -5
dBµV30 to 130 MHz 18 4 -7
130 MHz to 1GHz 15 5 -7
SAE EMI Level 2.5 2 1 -
Table 39. ESD absolute maximum ratings
Symbol Ratings Conditions Packages Class Maximum
value(1) Unit
VESD(HBM)
Electrostatic discharge voltage
(human body model)
TA = +25 °C, conforming to
JESD22-A114 All 2 2000
V
VESD(CDM)
Electrostatic discharge voltage
(charge device model)
TA = +25 °C, conforming to
JESD22-C101 All III 500
1. Guaranteed by characterization results.
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104
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.
6.3.12 I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard pins) should be avoided during normal product operation.
However, in order to give an indication of the robustness of the microcontroller in cases
when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error, out of spec current
injection on adjacent pins or other functional failure (for example reset, oscillator frequency
deviation, LCD levels, etc.).
The test results are given in Table 41.
Note: It is recommended to add a Schottky diode (pin to ground) to analog pins which may
potentially inject negative currents.
Table 40. Electrical sensitivities
Symbol Parameter Conditions Class
LU Static latch-up class TA = +105 °C conforming to JESD78A II level A
Table 41. I/O current injection susceptibility
Symbol Description
Functional susceptibility
Unit
Negative
injection
Positive
injection
IINJ
Injected current on all 5 V tolerant (FT) pins -5 +0
mA
Injected current on any other pin -5 +5
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82/133 DocID17659 Rev 12
6.3.13 I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 42 are derived from tests
performed under conditions summarized in Table 13. All I/Os are CMOS and TTL compliant.
Table 42. I/O static characteristics
Symbol Parameter Conditions Min Typ Max Unit
VIL Input low level voltage - - - - 0.3VDD(1)
V
VIH Input high level voltage
Standard I/O
0.7 VDD
--
FT I/O - -
Vhys
I/O Schmitt trigger voltage
hysteresis(2)
Standard I/O - 10% VDD(3) -
FT I/O - 5% VDD(4) -
Ilkg Input leakage current (5)
VSS VIN VDD
I/Os with LCD --±50
nA
VSS VIN VDD
I/Os with analog
switches
--±50
VSS VIN VDD
I/Os with analog
switches and LCD
--±50
VSS VIN VDD
I/Os with USB --TBD
FT I/O
VDD VIN 5V --TBD
VSS VIN VDD
Standard I/Os --±50
RPU Weak pull-up equivalent resistor(6)(1) VIN = VSS 30 45 60 kΩ
RPD Weak pull-down equivalent resistor(6) VIN = VDD 30 45 60 kΩ
CIO I/O pin capacitance - - - 5 - pF
1. Tested in production
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization.
3. With a minimum of 200 mV. Based on characterization results.
4. With a minimum of 100 mV. Based on characterization results.
5. The max. value may be exceeded if negative current is injected on adjacent pins.
6. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
MOS/NMOS contribution to the series resistance is minimum (~10% order).
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Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA (with the non-standard VOL/VOH specifications given in Table 43.
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
IVDDΣ (see Table 11).
The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
IVSSΣ (see Table 11).
Output voltage levels
Unless otherwise specified, the parameters given in Table 43 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 13. All I/Os are CMOS and TTL compliant.
Table 43. Output voltage characteristics
Symbol Parameter Conditions Min Max Unit
VOL(1)(2) Output low level voltage for an I/O pin IIO = 8 mA
2.7 V < VDD < 3.6 V
-0.4
V
VOH(3)(2) Output high level voltage for an I/O pin 2.4 -
VOL (1)(4) Output low level voltage for an I/O pin IIO = 4 mA
1.65 V < VDD < 2.7 V
-0.45
VOH (3)(4) Output high level voltage for an I/O pin VDD-0.45 -
VOL(1)(4) Output low level voltage for an I/O pin IIO = 20 mA
2.7 V < VDD < 3.6 V
-1.3
VOH(3)(4) Output high level voltage for an I/O pin VDD-1.3 -
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 11 and the sum of
IIO (I/O ports and control pins) must not exceed IVSS.
2. Tested in production.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 11 and the sum
of IIO (I/O ports and control pins) must not exceed IVDD.
4. Guaranteed by characterization results.
Electrical characteristics STM32L151x6/8/B STM32L152x6/8/B
84/133 DocID17659 Rev 12
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 19 and
Table 44, respectively.
Unless otherwise specified, the parameters given in Table 44 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 13.
Table 44. I/O AC characteristics(1)
OSPEEDRx
[1:0] bit
value(1)
Symbol Parameter Conditions Min Max(2) Unit
00
fmax(IO)out Maximum frequency(3) CL = 50 pF, VDD = 2.7 V to 3.6 V - 400
kHz
CL = 50 pF, VDD = 1.65 V to 2.7 V - 400
tf(IO)out
tr(IO)out
Output rise and fall time
CL = 50 pF, VDD = 2.7 V to 3.6 V - 625
ns
CL = 50 pF, VDD = 1.65 V to 2.7 V - 625
01
fmax(IO)out Maximum frequency(3) CL = 50 pF, VDD = 2.7 V to 3.6 V - 2
MHz
CL = 50 pF, VDD = 1.65 V to 2.7 V - 1
tf(IO)out
tr(IO)out
Output rise and fall time
CL = 50 pF, VDD = 2.7 V to 3.6 V - 125
ns
CL = 50 pF, VDD = 1.65 V to 2.7 V - 250
10
Fmax(IO)out Maximum frequency(3) CL = 50 pF, VDD = 2.7 V to 3.6 V - 10
MHz
CL = 50 pF, VDD = 1.65 V to 2.7 V - 2
tf(IO)out
tr(IO)out
Output rise and fall time
CL = 50 pF, VDD = 2.7 V to 3.6 V - 25
ns
CL = 50 pF, VDD = 1.65 V to 2.7 V - 125
11
Fmax(IO)out Maximum frequency(3) CL = 50 pF, VDD = 2.7 V to 3.6 V - 50
MHz
CL = 50 pF, VDD = 1.65 V to 2.7 V - 8
tf(IO)out
tr(IO)out
Output rise and fall time
CL = 30 pF, VDD = 2.7 V to 3.6 V - 5
ns
CL = 50 pF, VDD = 1.65 V to 2.7 V - 30
-t
EXTIpw
Pulse width of external
signals detected by the
EXTI controller
-8-
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the STM32L151x6/8/B and STM32L152x6/8/B
reference manual for a description of GPIO Port configuration register.
2. Guaranteed by design.
3. The maximum frequency is defined in Figure 19.
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104
Figure 19. I/O AC characteristics definition
6.3.14 NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 45).
Unless otherwise specified, the parameters given in Table 45 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 13.
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Table 45. NRST pin characteristics
Symbol Parameter Conditions Min Typ Max Unit
VIL(NRST)(1)
1. Guaranteed by design.
NRST input low level voltage - - - 0.8
V
VIH(NRST)(1) NRST input high level voltage - 1.4 -
VOL(NRST)(1) NRST output low level
voltage
IOL = 2 mA
2.7 V < VDD < 3.6 V --
0.4
IOL = 1.5 mA
1.65 V < VDD < 2.7 V --
Vhys(NRST)(1) NRST Schmitt trigger voltage
hysteresis --10%V
DD(2)
2. 200 mV minimum value
mV
RPU
Weak pull-up equivalent
resistor(3)
3. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance is around 10%.
VIN = VSS 30 45 60 kΩ
VF(NRST)(1) NRST input filtered pulse - - - 50 ns
VNF(NRST)(1) NRST input not filtered pulse - 350 - ns
Electrical characteristics STM32L151x6/8/B STM32L152x6/8/B
86/133 DocID17659 Rev 12
Figure 20. Recommended NRST pin protection
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 45. Otherwise the reset will not be taken into account by the device.
6.3.15 TIM timer characteristics
The parameters given in Table 46 are guaranteed by design.
Refer to Section 6.3.13: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
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Table 46. TIMx(1) characteristics
1. TIMx is used as a general term to refer to the TIM2, TIM3 and TIM4 timers.
Symbol Parameter Conditions Min Max Unit
tres(TIM) Timer resolution time
-1-t
TIMxCLK
fTIMxCLK = 32 MHz 31.25 - ns
fEXT
Timer external clock
frequency on CH1 to CH4
-0f
TIMxCLK/2 MHz
fTIMxCLK = 32 MHz 0 16 MHz
ResTIM Timer resolution - - 16 bit
tCOUNTER
16-bit counter clock
period when internal clock
is selected (timer’s
prescaler disabled)
- 1 65536 tTIMxCLK
fTIMxCLK = 32 MHz 0.0312 2048 µs
tMAX_COUNT Maximum possible count
- - 65536 × 65536 tTIMxCLK
fTIMxCLK = 32 MHz - 134.2 s
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104
6.3.16 Communication interfaces
I2C interface characteristics
The STM32L151x6/8/B and STM32L152x6/8/B product line I2C interface meets the
requirements of the standard I2C communication protocol with the following restrictions:
SDA and SCL are not “true” open-drain I/O pins. When configured as open-drain, the PMOS
connected between the I/O pin and VDD is disabled, but is still present.
The I2C characteristics are described in Table 47. Refer also to Section 6.3.12: I/O current
injection characteristics for more details on the input/output alternate function characteristics
(SDA and SCL).
Table 47. I2C characteristics
Symbol Parameter
Standard mode I2C(1)
1. Guaranteed by design.
Fast mode I2C(1)(2)
2. fPCLK1 must be at least 2 MHz to achieve standard mode I²C frequencies. It must be at least 4 MHz to
achieve fast mode I²C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum I²C fast
mode clock.
Unit
Min Max Min Max
tw(SCLL) SCL clock low time 4.7 - 1.3 -
µs
tw(SCLH) SCL clock high time 4.0 - 0.6 -
tsu(SDA) SDA setup time 250 - 100 -
ns
th(SDA) SDA data hold time 0 - 0 900(3)
3. The maximum Data hold time has only to be met if the interface does not stretch the low period of SCL
signal.
tr(SDA)
tr(SCL)
SDA and SCL rise time - 1000 20 + 0.1Cb300
tf(SDA)
tf(SCL)
SDA and SCL fall time - 300 - 300
th(STA) Start condition hold time 4.0 - 0.6 -
µs
tsu(STA)
Repeated Start condition
setup time 4.7 - 0.6 -
tsu(STO) Stop condition setup time 4.0 - 0.6 - μs
tw(STO:STA)
Stop to Start condition time
(bus free) 4.7 - 1.3 - μs
Cb
Capacitive load for each bus
line - 400 - 400 pF
PPPPP
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88/133 DocID17659 Rev 12
Figure 21. I2C bus AC waveforms and measurement circuit
1. RS = series protection resistors
2. RP = pull-up resistors
3. VDD_I2C = I2C bus supply
4. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
Table 48. SCL frequency (fPCLK1= 32 MHz, VDD = VDD_I2C = 3.3 V)(1)(2)
1. RP = External pull-up resistance, fSCL = I2C speed.
2. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the
tolerance on the achieved speed is ±2%. These variations depend on the accuracy of the external
components used to design the application.
fSCL (kHz)
I2C_CCR value
RP = 4.7 kΩ
400 0x801B
300 0x8024
200 0x8035
100 0x00A0
50 0x0140
20 0x0320
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STM32L151x6/8/B STM32L152x6/8/B Electrical characteristics
104
SPI characteristics
Unless otherwise specified, the parameters given in the following table are derived from
tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 13.
Refer to Section 6.3.12: I/O current injection characteristics for more details on the
input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
Table 49. SPI characteristics(1)
1. The characteristics above are given for voltage Range 1.
Symbol Parameter Conditions Min Max(2)
2. Guaranteed by characterization results.
Unit
fSCK
1/tc(SCK)
SPI clock frequency
Master mode - 16
MHz
Slave mode - 16
Slave transmitter - 12(3)
3. The maximum SPI clock frequency in slave transmitter mode is given for an SPI slave input clock duty
cycle (DuCy(SCK)) ranging between 40 to 60%.
tr(SCK)(2)
tf(SCK)(2)
SPI clock rise and fall
time Capacitive load: C = 30 pF - 6 ns
DuCy(SCK) SPI slave input clock duty
cycle Slave mode 30 70 %
tsu(NSS) NSS setup time Slave mode 4tHCLK -
ns
th(NSS) NSS hold time Slave mode 2tHCLK -
tw(SCKH)(2)
tw(SCKL)(2) SCK high and low time Master mode tSCK/2
5
tSCK/2+
3
tsu(MI)(2)
Data input setup time
Master mode 5 -
tsu(SI)(2) Slave mode 6 -
th(MI)(2)
Data input hold time
Master mode 5 -
th(SI)(2) Slave mode 5 -
ta(SO)(4)
4. Min time is for the minimum time to drive the output and max time is for the maximum time to validate the
data.
Data output access time Slave mode 0 3tHCLK
tv(SO) (2) Data output valid time Slave mode - 33
tv(MO)(2) Data output valid time Master mode - 6.5
th(SO)(2)
Data output hold time
Slave mode 17 -
th(MO)(2) Master mode 0.5 -
Electrical characteristics STM32L151x6/8/B STM32L152x6/8/B
90/133 DocID17659 Rev 12
Figure 22. SPI timing diagram - slave mode and CPHA = 0
Figure 23. SPI timing diagram - slave mode and CPHA = 1(1)
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
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DocID17659 Rev 12 91/133
STM32L151x6/8/B STM32L152x6/8/B Electrical characteristics
104
Figure 24. SPI timing diagram - master mode(1)
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
USB characteristics
The USB interface is USB-IF certified (full speed).
Table 50. USB startup time
Symbol Parameter Max Unit
tSTARTUP(1)
1. Guaranteed by design.
USB transceiver startup time 1 µs
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Electrical characteristics STM32L151x6/8/B STM32L152x6/8/B
92/133 DocID17659 Rev 12
Figure 25. USB timings: definition of data signal rise and fall time
Table 51. USB DC electrical characteristics
Symbol Parameter Conditions Min.(1)
1. All the voltages are measured from the local ground potential.
Max.(1) Unit
Input levels
VDD USB operating voltage(2)
2. To be compliant with the USB 2.0 full speed electrical specification, the USB_DP (D+) pin should be pulled
up with a 1.5 kΩ resistor to a 3.0-to-3.6 V voltage range.
-3.03.6V
VDI(3)
3. Guaranteed by characterization results.
Differential input sensitivity I(USB_DP, USB_DM) 0.2 -
VVCM(3) Differential common mode range Includes VDI range 0.8 2.5
VSE(3) Single ended receiver threshold - 1.3 2.0
Output levels
VOL(4)
4. Tested in production.
Static output level low RL of 1.5 kΩ to 3.6 V(5)
5. RL is the load connected on the USB drivers.
-0.3
V
VOH(4) Static output level high RL of 15 kΩ to VSS(5) 2.8 3.6
Table 52. USB: full speed electrical characteristics
Driver characteristics(1)
1. Guaranteed by design.
Symbol Parameter Conditions Min Max Unit
trRise time(2)
2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
CL = 50 pF 420ns
tfFall Time(2) CL = 50 pF 4 20 ns
trfm Rise/ fall time matching tr/tf90 110 %
VCRS Output signal crossover voltage 1.3 2.0 V
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DocID17659 Rev 12 93/133
STM32L151x6/8/B STM32L152x6/8/B Electrical characteristics
104
6.3.17 12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 54 are guaranteed by design.
Table 53. ADC clock frequency
Symbol Parameter Conditions Min Max Unit
fADC
ADC clock
frequency
Voltage
Range 1 &
2
2.4 V VDDA 3.6 V
VREF+ = VDDA
0.480
16
MHz
VREF+ < VDDA
VREF+ > 2.4 V 8
VREF+ < VDDA
VREF+ 2.4 V 4
1.8 V VDDA 2.4 V
VREF+ = VDDA 8
VREF+ < VDDA 4
Voltage Range 3 4
Table 54. ADC characteristics
Symbol Parameter Conditions Min Typ Max Unit
VDDA Power supply - 1.8 - 3.6 V
VREF+ Positive reference voltage
2.4 V VDDA 3.6 V
VREF+ must be below
or equal to VDDA
1.8(1) -V
DDA V
VREF- Negative reference voltage - - VSSA -V
IVDDA
Current on the VDDA input
pin - - 1000 1450 µA
IVREF(2) Current on the VREF input
pin
Peak -
400
700 µA
Average - 450 µA
VAIN Conversion voltage range(3) -0
(4) -V
REF+ V
fS
12-bit sampling rate
Direct channels 0.03 - 1
Msps
Multiplexed channels 0.03 - 0.76
10-bit sampling rate
Direct channels 0.03 - 1.07
Msps
Multiplexed channels 0.03 - 0.8
8-bit sampling rate
Direct channels 0.03 - 1.23
Msps
Multiplexed channels 0.03 - 0.89
6-bit sampling rate
Direct channels 0.03 - 1.45
Msps
Multiplexed channels 0.03 - 1
Electrical characteristics STM32L151x6/8/B STM32L152x6/8/B
94/133 DocID17659 Rev 12
tSSampling time(5)
Direct channels
2.4 V VDDA 3.6 V 0.25 - -
µs
Multiplexed channels
2.4 V VDDA 3.6 V 0.56 - -
Direct channels
1.8 V VDDA 2.4 V 0.56 - -
Multiplexed channels
1.8 V VDDA 2.4 V 1- -
- 4 - 384 1/fADC
tCONV
Total conversion time
(including sampling time)
fADC = 16 MHz 1 - 24.75 µs
-
4 to 384 (sampling
phase) +12 (successive
approximation)
1/fADC
CADC
Internal sample and hold
capacitor
Direct channels -
16
-
pF
Multiplexed channels - -
fTRIG
External trigger frequency
Regular sequencer
12-bit conversions - - Tconv+1 1/fADC
6/8/10-bit conversions - - Tconv 1/fADC
fTRIG
External trigger frequency
Injected sequencer
12-bit conversions - - Tconv+2 1/fADC
6/8/10-bit conversions - - Tconv+1 1/fADC
RAIN Signal source impedance(5) ---50κΩ
tlat
Injection trigger conversion
latency
fADC = 16 MHz 219 - 281 ns
-3.5-4.51/f
ADC
tlatr
Regular trigger conversion
latency
fADC = 16 MHz 156 - 219 ns
-2.5-3.51/f
ADC
tSTAB Power-up time - - - 3.5 µs
1. The VREF+ input can be grounded iif neither the ADC nor the DAC are used (this allows to shut down an
external voltage reference).
2. The current consumption through VREF is composed of two parameters:
- one constant (max 300 µA)
- one variable (max 400 µA), only during sampling time + 2 first conversion pulses.
So, peak consumption is 300+400 = 700 µA and average consumption is 300 + [(4 sampling + 2) /16] x 400
= 450 µA at 1Msps
3. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on
the package. Refer to Section 4: Pin descriptions for further details.
4. VSSA must be tied to ground.
5. See Table 56: Maximum source impedance RAIN max for RAIN limitation.
Table 54. ADC characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit
DocID17659 Rev 12 95/133
STM32L151x6/8/B STM32L152x6/8/B Electrical characteristics
104
Table 55. ADC accuracy(1)(2)
Symbol Parameter Test conditions Min(3) Typ Max(3) Unit
ET Total unadjusted error
2.4 V VDDA 3.6 V
2.4 V VREF+ 3.6 V
fADC = 8 MHz, RAIN = 50
TA = -40 to 105 °C
-24
LSB
EO Offset error - 1 2
EG Gain error - 1.5 3.5
ED Differential linearity error - 1 2
EL Integral linearity error - 1.7 3
ENOB Effective number of bits 2.4 V VDDA 3.6 V
VDDA = VREF+
fADC = 16 MHz, RAIN = 50
TA = -40 to 105 °C
1 kHz Finput 100 kHz
9.2 10 - bits
SINAD Signal-to-noise and
distortion ratio 57.5 62 -
dB
SNR Signal-to-noise ratio 57.5 62 -
THD Total harmonic distortion -74 -75 -
ET Total unadjusted error
2.4 V VDDA 3.6 V
1.8 V VREF+ 2.4 V
fADC = 4 MHz, RAIN = 50
TA = -40 to 105 °C
-46.5
LSB
EO Offset error - 2 4
EG Gain error - 4 6
ED Differential linearity error - 1 2
EL Integral linearity error - 1.5 3
ET Total unadjusted error
1.8 V VDDA 2.4 V
1.8 V VREF+ 2.4 V
fADC = 4 MHz, RAIN = 50
TA = -40 to 105 °C
-23
LSB
EO Offset error - 1 1.5
EG Gain error - 1.5 2
ED Differential linearity error - 1 2
EL Integral linearity error - 1 1.5
1. ADC DC accuracy values are measured after internal calibration.
2. ADC accuracy vs. negative injection current: Injecting a negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.12 does not affect the ADC
accuracy.
3. Guaranteed by characterization results.
Electrical characteristics STM32L151x6/8/B STM32L152x6/8/B
96/133 DocID17659 Rev 12
Figure 26. ADC accuracy characteristics
Figure 27. Typical connection diagram using the ADC
1. Refer to Table 56: Maximum source impedance RAIN max for the value of RAIN and Table 54: ADC
characteristics for the value of CADC
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
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