KSZ8091RNA,RND Datasheet by Microchip Technology

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2016 Microchip Technology Inc. DS00002298A-page 1
Features
Single-Chip 10BASE-T/100BASE-TX IEEE 802.3
Compliant Ethernet Transceiver
RMII V1.2 Interface Support with a 50 MHz Refer-
ence Clock Output to MAC, and an Option to
Input a 50 MHz Reference Clock
RMII Back-to-Back Mode Support for a 100 Mbps
Copper Repeater
MDC/MDIO Management Interface for PHY Reg-
ister Configuration
Programmable Interrupt Output
LED Outputs for Link and Activity Status Indica-
tion
On-Chip Termination Resistors for the Differential
Pairs
Baseline Wander Correction
HP Auto MDI/MDI-X to Reliably Detect and Cor-
rect Straight-Through and Crossover Cable Con-
nections with Disable and Enable Option
Auto-Negotiation to Automatically Select the
Highest Link-Up Speed (10/100 Mbps) and
Duplex (Half/Full)
Energy Efficient Ethernet (EEE) Support with
Low-Power Idle (LPI) Mode for 100BASE-TX and
Transmit Amplitude Reduction with 10BASE-TE
Option
Wake-on-LAN (WoL) Support with Either Magic
Packet, Link Status Change, or Robust Custom-
Packet Detection
• LinkMD® TDR-Based Cable Diagnostics to Iden-
tify Faulty Copper Cabling
HBM ESD Rating (6 kV)
Parametric NAND Tree Support for Fault Detec-
tion Between Chip I/Os and the Board
Loopback Modes for Diagnostics
Power-Down and Power-Saving Modes
Single 3.3V Power Supply with VDD I/O Options
for 1.8V, 2.5V, or 3.3V
Built-In 1.2V Regulator for Core
Available in 24-Pin (4 mm × 4 mm) QFN Package
Target Applications
Game Consoles
IP Phones
IP Set-Top Boxes
•IP TVs
•LOM
• Printers
KSZ8091RNA/RND
10BASE-T/100BASE-TX PHY
with RMII and EEE Support
KSZ8091RNA/RND
DS00002298A-page 2 2016 Microchip Technology Inc.
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2016 Microchip Technology Inc. DS00002298A-page 3
KSZ8091RNA/RND
Table of Contents
1.0 Introduction ..................................................................................................................................................................................... 4
2.0 Pin Description and Configuration .................................................................................................................................................. 5
3.0 Functional Description .................................................................................................................................................................. 10
4.0 Register Descriptions .................................................................................................................................................................... 29
5.0 Operational Characteristics ........................................................................................................................................................... 45
6.0 Electrical Characteristics ............................................................................................................................................................... 46
7.0 Timing Diagrams ........................................................................................................................................................................... 48
8.0 Reset Circuit ................................................................................................................................................................................. 52
9.0 Reference Circuits — LED Strap-In Pins ...................................................................................................................................... 53
10.0 Reference Clock - Connection and Selection ............................................................................................................................. 54
11.0 Magnetic - Connection and Selection ......................................................................................................................................... 55
12.0 Package Outline .......................................................................................................................................................................... 57
Appendix A: Data Sheet Revision History ........................................................................................................................................... 58
The Microchip Web Site ...................................................................................................................................................................... 59
Customer Change Notification Service ............................................................................................................................................... 59
Customer Support ............................................................................................................................................................................... 59
Product Identification System ............................................................................................................................................................. 60
KSZ8091RNA/RND
DS00002298A-page 4 2016 Microchip Technology Inc.
1.0 INTRODUCTION
1.1 General Description
The KSZ8091RNA is a single-supply 10BASE-T/100BASE-TX Ethernet physical-layer transceiver for transmission and
reception of data over standard CAT-5 unshielded twisted pair (UTP) cable.
The KSZ8091RNA is a highly integrated PHY solution. It reduces board cost and simplifies board layout by using on-
chip termination resistors for the differential pairs and by integrating a low-noise regulator to supply the 1.2V core, and
by offering a flexible 1.8/2.5/3.3V digital I/O interface.
The KSZ8091RNA offers the Reduced Media Independent Interface (RMII) for direct connection with RMII-compliant
Ethernet MAC processors and switches.
As the power-up default, the KSZ8091RNA uses a 25 MHz crystal to generate all required clocks, including the 50 MHz
RMII reference clock output for the MAC. The KSZ8091RND takes in the 50 MHz RMII reference clock as the power-
up default.
Energy Efficient Ethernet (EEE) provides further power saving during idle traffic periods and Wake-On-LAN (WOL) pro-
vides a mechanism for the KSZ8091RNA to wake up a system that is in standby power mode.
The KSZ8091RNA and KSZ8091RND are available in 24-pin, lead-free QFN packages.
FIGURE 1-1: SYSTEM BLOCK DIAGRAM
KSZ8091RNA/RND
MAGNETICS
RJ-45
CONNECTOR
MEDIA TYPES:
10BASE-T
100BASE-TX
ON-CHIP TERMINATION
RESISTORS
RMII
MDC/MDIO
MANAGEMENT
XO XI
25MHz
XTAL
22pF
22pF
10/100Mbps
RMII MAC
50MHz
REF_CLK
PME_N
(SYSTEM
POWER
CIRCUIT)
MUMUUU CEEEEE 333333 flflflflflfl
2016 Microchip Technology Inc. DS00002275A-page 5
KSZ8091RNA/RND
2.0 PIN DESCRIPTION AND CONFIGURATION
FIGURE 2-1: 24-PIN 4 MM X 4 MM QFN ASSIGNMENT (TOP VIEW)
1
2
3
4
5
6
18
17
16
15
14
13
24 23 22 21 20 19
78910 11 12
PADDLE GROUND
(ON BOTTOM OF CHIP)
VDD_1.2
VDDA_3.3
RXM
RXP
TXM
TXP
INTRP/
PME_N2
RXER/
PME_EN
REF_CLK
CRS_DV/
PHYAD[1:0]
VDDIO
RXD0
RST#
LED0/PME_N1
/
ANEN_SPEED
GND
TXD1
TXD0
TXEN
XO
XI
REXT
MDIO
MDC
RXD1
KSZ8091RNA/RND
DS00002275A-page 6 2016 Microchip Technology Inc.
TABLE 2-1: SIGNALS - KSZ8091RNA/RND
Pin
Number Pin
Name
Type
Note
2-1 Description
1VDD_1.2 P 1.2V Core VDD (power supplied by KSZ8091RNA/KSZ8091RND). Decouple
with 2.2 µF and 0.1 µF capacitors to ground.
2VDDA_3.3 P 3.3V analog VDD.
3RXM I/O Physical receive or transmit signal (– differential).
4RXP I/O Physical receive or transmit signal (+ differential).
5TXM I/O Physical transmit or receive signal (– differential).
6TXP I/O Physical transmit or receive signal (+ differential).
7XO O Crystal Feedback for 25 MHz Crystal. This pin is a no connect if an oscillator
or external clock source is used.
8XI I
RMII – 25 MHz Mode: 25 MHz ±50 ppm Crystal/Oscillator/External Clock
Input
RMII – 50 MHz Mode: 50 MHz ±50 ppm Oscillator/External Clock Input
For unmanaged mode (power-up default setting),
KSZ8091RNA takes in the 25 MHz crystal/clock on this pin.
KSZ8091RND takes in the 50 MHz clock on this pin.
After power-up, both the KSZ8091RNA and KSZ8091RND can be pro-
grammed to either the 25 MHz mode or 50 MHz mode using PHY Register
1Fh, Bit [7].
See REF_CLK (Pin 16).
9REXT I Set PHY Transmit Output Current
Connect a 6.49 k resistor to ground on this pin.
10 MDIO Ipu/
Opu
Management Interface (MII) Data I/O. This pin has a weak pull-up, is open-
drain, and requires an external 1.0 k pull-up resistor.
11 MDC Ipu Management Interface (MII) Clock Input. This clock pin is synchronous to
the MDIO data pin.
12 RXD1 Ipd/O RMII Receive Data Output[1] (Note 2-2).
13 RXD0 Ipu/O RMII Receive Data Output[0] (Note 2-2).
14 VDDIO P 3.3V, 2.5V, or 1.8V digital VDD.
15 CRS_DV /
PHYAD[1:0] Ipd/O
RMII Mode: Carrier Sense/Receive Data Valid output
Config Mode: The pull-up/pull-down value is latched as PHYAD[1:0] at the
de-assertion of reset.
See the Strap-In Options - KSZ8091RNA/RND section for details.
2016 Microchip Technology Inc. DS00002275A-page 7
KSZ8091RNA/RND
16 REF_CLK Ipd/O
RMII – 25 MHz Mode: This pin provides the 50 MHz RMII reference clock
output to the MAC.
RMII – 50 MHz Mode: This pin is a no connect.
For unmanaged mode (power-up default setting):
KSZ8091RNA is in RMII – 25 MHz mode and outputs the 50 MHz RMII
reference clock on this pin.
KSZ8091RND is in RMII – 50 MHz mode and does not use this pin.
After power-up, both KSZ8091RNA and KSZ8091RND can be programmed
to either 25 MHz mode or 50 MHz mode using PHY Register 1Fh, Bit [7].
See also XI (Pin 8).
17 RXER /
PME_EN Ipd/O
RMII Mode: RMII Receive Error Output
Config Mode: The pull-up/pull-down value is latched as PME_EN at the de-
assertion of reset. See the Strap-In Options - KSZ8091RNA/RND section for
details.
18 INTRP/
PME_N2
Ipu/
Opu
Interrupt Output: Programmable interrupt output, with Register 1Bh as the
Interrupt Control/Status register, for programming the interrupt conditions
and reading the interrupt status. Register 1Fh, Bit [9] sets the interrupt output
to active low (default) or active high.
PME_N Output: Programmable PME_N output (pin option 2). When
asserted low, this pin signals that a WOL event has occurred.
This pin has a weak pull-up and is an open-drain.
For Interrupt (when active low) and PME functions, this pin requires an
external 1.0 k pull-up resistor to VDDIO (digital VDD).
19 TXEN I RMII Transmit Enable Input
20 TXD0 I RMII Transmit Data Input[0] (Note 2-3)
21 TXD1 I/O RMII Mode: RMII Transmit Data Input[1] (Note 2-3)
NAND Tree Mode: NAND Tree Output
22 GND GND Ground
TABLE 2-1: SIGNALS - KSZ8091RNA/RND (CONTINUED)
Pin
Number Pin
Name
Type
Note
2-1 Description
KSZ8091RNA/RND
DS00002275A-page 8 2016 Microchip Technology Inc.
Note 2-1 P = power supply
GND = ground
I = input
O = output
I/O = bi-directional
Ipu = Input with internal pull-up (see Electrical Characteristics for value).
Ipd = Input with internal pull-down (see Electrical Characteristics for value).
Ipu/O = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset;
output pin otherwise.
Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset;
output pin otherwise.
Ipu/Opu = Input with internal pull-up (see Electrical Characteristics for value) and output with internal
pull-up (see Electrical Characteristics for value).
Note 2-2 RMII RX Mode: The RXD[1:0] bits are synchronous with the 50 MHz RMII Reference Clock. For each
clock period in which CRS_DV is asserted, two bits of recovered data are sent by the PHY to the
MAC.
Note 2-3 RMII TX Mode: The TXD[1:0] bits are synchronous with the 50 MHz RMII Reference Clock. For each
clock period in which TXEN is asserted, two bits of data are received by the PHY from the MAC.
23
LED0/
PME_N1/
ANEN_SPEED
Ipu/O
LED Output: Programmable LED0 output
PME_N Output: Programmable PME_N Output (pin option 1). When
asserted low, this pin signals that a WOL event has occurred. In this mode,
this pin has a weak pull-up, is an open-drain, and requires an external
1.0 k pull-up resistor to VDDIO (digital VDD).
Config Mode: Latched as Auto-Negotiation enable (Register 0h, Bit [12]) and
Speed (Register 0h, Bit [13]) at the de-assertion of reset. See the Strapping
Options section for details.
The LED0 pin is programmable using Register 1Fh, Bits [5:4], and is defined
as follows:
LED Mode = [00]
Link/Activity Pin State LED Definition
No Link High OFF
Link Low ON
Activity Toggle Blinking
LED Mode = [01]
Link/Activity Pin State LED Definition
No Link High OFF
Link Low ON
LED Mode = [10], [11]‘ Reserved
24 RST# Ipu Chip Reset (Active Low)
PADDLE GND GND Ground
TABLE 2-1: SIGNALS - KSZ8091RNA/RND (CONTINUED)
Pin
Number Pin
Name
Type
Note
2-1 Description
lpu/O : Inpu: wxl inlerna‘ puhup (see Elecmoal Characlensfics for va‘ue) during powerrup/resel,
2016 Microchip Technology Inc. DS00002275A-page 9
KSZ8091RNA/RND
2.1 Strap-In Options - KSZ8091RNA/RND
The PHYAD[1:0] and PME_EN strap-in pins are latched at the de-assertion of reset. In some systems, the RMII MAC
receive input pins may drive high/low during power-up or reset, and consequently cause the PHYAD[1:0] and PME_EN
strap-in pins, shared pin with the RMII CRS_DV and RXER signals respectively, to be latched to the unintended high/
low state. In this case, an external pull-up (4.7 k) or pull-down (1.0 k) should be added on the PHYAD[1:0] and
PME_EN strap-in pins to ensure that the intended value is strapped-in correctly.
Note 2-4 Ipu/O = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset;
output pin otherwise.
Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset;
output pin otherwise.
TABLE 2-2: STRAP-IN OPTIONS - KSZ8091RNA/RND
Pin Number Pin Name Type
Note 2-4 Description
15 PHYAD[1:0] Ipd/O
The PHY Address is latched at the de-assertion of reset and is con-
figurable to either one of the following two values:
Pull-up = PHY Address is set to 00011b (3h)
Pull-down (default) = PHY Address is set to 00000b (0h)
PHY Address 0 is assigned by default as the broadcast PHY
address, but it can be assigned as a unique PHY address after writ-
ing a ‘1’ to Register 16h, Bit [9].
PHY Address bits [4:2] are set to 000 by default.
17 PME_EN Ipd/O
PME Output for Wake-On-LAN
Pull-up = Enable
Pull-down (default) = Disable
At the de-assertion of reset, this pin value is latched into Register
16h, Bit [15].
23 ANEN_SPEED Ipu/O
Auto-Negotiation Enable and Speed Mode
Pull-up (default) = Enable Auto-Negotiation and set 100 Mbps Speed
Pull-down = Disable Auto-Negotiation and set 10 Mbps Speed
At the de-assertion of reset, this pin value is latched into Register 0h,
Bit [12] for Auto-Negotiation enable/disable, Register 0h, Bit [13] for
the Speed select, and Register 4h (Auto-Negotiation Advertisement)
for the Speed capability support.
KSZ8091RNA/RND
DS00002298A-page 10 2016 Microchip Technology Inc.
3.0 FUNCTIONAL DESCRIPTION
The KSZ8091RNA is an integrated single 3.3V supply Fast Ethernet transceiver. It is fully compliant with the IEEE 802.3
Specification, and reduces board cost and simplifies board layout by using on-chip termination resistors for the two dif-
ferential pairs and by integrating the regulator to supply the 1.2V core.
On the copper media side, the KSZ8091RNA supports 10BASE-T and 100BASE-TX for transmission and reception of
data over a standard CAT-5 unshielded twisted pair (UTP) cable, and HP Auto MDI/MDI-X for reliable detection of and
correction for straight-through and crossover cables.
On the MAC processor side, the KSZ8091RNA offers the Reduced Media Independent Interface (RMII) for direct con-
nection with RMII-compliant Ethernet MAC processors and switches
The MII management bus option gives the MAC processor complete access to the KSZ8091RNA control and status
registers. Additionally, an interrupt pin eliminates the need for the processor to poll for PHY status change.
As the power-up default, the KSZ8091RNA uses a 25 MHz crystal to generate all required clocks, including the 50 MHz
RMII reference clock output for the MAC. The KSZ8091RND version uses the 50 MHz RMII reference clock as the
power-up default.
The KSZ8091RNA/RND is used to refer to both KSZ8091RNA and KSZ8091RND versions in this datasheet.
3.1 10BASE-T/100BASE-TX Transceiver
3.1.1 100BASE-TX TRANSMIT
The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B encoding, scrambling, NRZ-to-NRZI
conversion, and MLT3 encoding and transmission.
The circuitry starts with a parallel-to-serial conversion, which converts the MII/RMII data from the MAC into a 125 MHz
serial bit stream. The data and control stream is then converted into 4B/5B coding and followed by a scrambler. The
serialized data is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. The output
current is set by an external 6.49 k 1% resistor for the 1:1 transformer ratio.
The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude
balance, overshoot, and timing jitter. The wave-shaped 10BASE-T output is also incorporated into the 100BASE-TX
transmitter.
3.1.2 100BASE-TX RECEIVE
The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and
clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.
The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted
pair cable. Because the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust
its characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on
comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization.
This is an ongoing process and self-adjusts against environmental changes such as temperature variations.
Next, the equalized signal goes through a DC-restoration and data-conversion block. The DC-restoration circuit com-
pensates for the effect of baseline wander and improves the dynamic range. The differential data-conversion circuit con-
verts MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock-recovery circuit extracts the 125 MHz clock from the edges of the NRZI signal. This recovered clock is then
used to convert the NRZI signal to NRZ format. This signal is sent through the de-scrambler, then the 4B/5B decoder.
Finally, the NRZ serial data is converted to MII/RMII format and provided as the input data to the MAC.
3.1.3 SCRAMBLER/DE-SCRAMBLER (100BASE-TX ONLY)
The scrambler spreads the power spectrum of the transmitted signal to reduce electromagnetic interference (EMI) and
baseline wander. The de-scrambler recovers the scrambled signal.
3.1.4 10BASE-T TRANSMIT
The 10BASE-T drivers are incorporated with the 100BASE-TX drivers to allow for transmission using the same mag-
netic. The drivers perform internal wave-shaping and pre-emphasis, and output 10BASE-T signals with a typical ampli-
tude of 2.5V peak for standard 10BASE-T mode and 1.75V peak for energy-efficient 10BASE-Te mode. The 10BASE-
T/10BASE-Te signals have harmonic contents that are at least 27 dB below the fundamental frequency when driven by
an all-ones Manchester-encoded signal.
2016 Microchip Technology Inc. DS00002298A-page 11
KSZ8091RNA/RND
3.1.5 10BASE-T RECEIVE
On the receive side, input buffer and level detecting squelch circuits are used. A differential input receiver circuit and a
phase-locked loop (PLL) performs the decoding function. The Manchester-encoded data stream is separated into clock
signal and NRZ data. A squelch circuit rejects signals with levels less than 400 mV, or with short pulse widths, to prevent
noise at the RXP and RXM inputs from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL
locks onto the incoming signal and the KSZ8091RNA/RND decodes a data frame. The receive clock is kept active
during idle periods between data receptions.
3.1.6 PLL CLOCK SYNTHESIZER
The KSZ8091RNA/RND in RMII – 25 MHz Clock mode generates all internal clocks and all external clocks for system
timing from an external 25 MHz crystal, oscillator, or reference clock. For the KSZ8091RNA/RND in RMII – 50 MHz
clock mode, these clocks are generated from an external 50 MHz oscillator or system clock.
3.1.7 AUTO-NEGOTIATION
The KSZ8091RNA/RND conforms to the auto-negotiation protocol, defined in Clause 28 of the IEEE 802.3 Specifica-
tion.
Auto-negotiation allows unshielded twisted pair (UTP) link partners to select the highest common mode of operation.
During auto-negotiation, link partners advertise capabilities across the UTP link to each other and then compare their
own capabilities with those they received from their link partners. The highest speed and duplex setting that is common
to the two link partners is selected as the mode of operation.
The following list shows the speed and duplex operation mode from highest to lowest priority.
Priority 1: 100BASE-TX, full-duplex
Priority 2: 100BASE-TX, half-duplex
Priority 3: 10BASE-T, full-duplex
Priority 4: 10BASE-T, half-duplex
If Auto-Negotiation is not supported or the KSZ8091RNA/RND link partner is forced to bypass Auto-Negotiation, then
the KSZ8091RNA/RND sets its operating mode by observing the signal at its receiver. This is known as parallel detec-
tion, which allows the KSZ8091RNA/RND to establish a link by listening for a fixed signal protocol in the absence of the
Auto-Negotiation advertisement protocol.
Auto-Negotiation is enabled by either hardware pin strapping (ANEN_SPEED, Pin 23) or software (Register 0h, Bit [12]).
By default, Auto-Negotiation is enabled after power-up or hardware reset. After that, Auto-Negotiation can be enabled
or disabled by Register 0h, Bit [12]. If Auto-Negotiation is disabled, the speed is set by Register 0h, Bit [13], and the
duplex is set by Register 0h, Bit [8].
The auto-negotiation link-up process is shown in Figure 3-1.
/
KSZ8091RNA/RND
DS00002298A-page 12 2016 Microchip Technology Inc.
FIGURE 3-1: AUTO-NEGOTIATION FLOW CHART
3.2 RMII Data Interface
The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). It pro-
vides a common interface between physical layer and MAC layer devices, and has the following key characteristics:
Pin count is 8 pins (3 pins for data transmission, 4 pins for data reception, and 1 pin for the 50 MHz reference
clock).
10 Mbps and 100 Mbps data rates are supported at both half- and full-duplex.
Data transmission and reception are independent and belong to separate signal groups.
Transmit data and receive data are each 2 bits wide, a dibit.
START AUTO-NEGOTIATION
FORCE LINK SETTING
LISTEN FOR 10BASE-T
LINK PULSES
LISTEN FOR 100BASE-TX
IDLES
ATTEMPT AUTO-
NEGOTIATION
LINK MODE SET
BYPASS AUTO-NEGOTIATION
AND SET LINK MODE
LINK MODE SET?
PARALLEL
OPERATION
NO
YES
YES
NO
JOIN FLOW
2016 Microchip Technology Inc. DS00002298A-page 13
KSZ8091RNA/RND
3.2.1 RMII SIGNAL DEFINITION
Table 3-1 describes the MII signals. Refer to Clause 22 of the IEEE 802.3 Specification for detailed information.
3.2.1.1 Reference Clock (REF_CLK)
REF_CLK is a continuous 50MHz clock that provides the timing reference for TXEN, TXD[1:0], CRS_DV, RXD[1:0], and
RX_ER.
For RMII – 25 MHz Clock Mode, the KSZ8091RNA/RND generates and outputs the 50 MHz RMII REF_CLK to the MAC
at REF_CLK (Pin 16).
For RMII – 50 MHz Clock Mode, the KSZ8091RNA/RND takes in the 50 MHz RMII REF_CLK from the MAC or system
board at XI (Pin 8) and leaves the REF_CLK (Pin 16) as no connect.
3.2.1.2 Transmit Enable (TXEN)
TXEN indicates that the MAC is presenting dibits on TXD[1:0] for transmission. It is asserted synchronously with the first
dibit of the preamble and remains asserted while all dibits to be transmitted are presented on the RMII. It is negated
before the first REF_CLK following the final dibit of a frame.
TXEN transitions synchronously with respect to REF_CLK.
3.2.1.3 Transmit Data[1:0] (TXD[1:0])
When TXEN is asserted, TXD[1:0] are the data dibits presented by the MAC and accepted by the PHY for transmission.
When TXEN is de-asserted, the MAC drives TXD[1:0] to either 00 for the idle state (non-EEE mode) or 01 for the LPI
state (EEE mode).
TXD[1:0] transitions synchronously with respect to REF_CLK
3.2.1.4 Carrier Sense/Receive Data Valid (CRS_DV)
The PHY asserts CRS_DV when the receive medium is non-idle. It is asserted asynchronously when a carrier is
detected. This happens when squelch is passed in 10 Mbps mode, and when two non-contiguous 0s in 10 bits are
detected in 100 Mbps mode. Loss of carrier results in the de-assertion of CRS_DV.
While carrier detection criteria are met, CRS_DV remains asserted continuously from the first recovered dibit of the
frame through the final recovered dibit. It is negated before the first REF_CLK that follows the final dibit. The data on
RXD[1:0] is considered valid after CRS_DV is asserted. However, because the assertion of CRS_DV is asynchronous
relative to REF_CLK, the data on RXD[1:0] is 00 until receive signals are properly decoded.
3.2.1.5 Receive Data[1:0] (RXD[1:0])
For each clock period in which CRS_DV is asserted, RXD[1:0] transfers a dibit of recovered data from the PHY.
When CRS_DV is de-asserted, the PHY drives RXD[1:0] to either 00 for the idle state (non-EEE mode) or 01 for the LPI
state (EEE mode).
RXD[1:0] transitions synchronously with respect to REF_CLK.
TABLE 3-1: RMII SIGNAL DEFINITION
RMII Signal
Name
Direction with Respect to
PHY, KSZ8091RNA/RND
Signal
Direction with
Respect to MAC Description
REF_CLK
Output (25 MHz clock
mode)/
<no connect> (50 MHz
clock mode)
Input/
Input or
<no connect>
Synchronous 50 MHz reference clock for receive,
transmit, and control interface
TXEN Input Output Transmit Enable
TXD[1:0] Input Output Transmit Data[1:0]
CRS_DV Output Input Carrier Sense/Receive Data Valid
RXD[1:0] Output Input Receive Data[1:0]
RXER Output Input, or (not
required) Receive Error
l l
KSZ8091RNA/RND
DS00002298A-page 14 2016 Microchip Technology Inc.
3.2.1.6 Receive Error (RXER)
When CRS_DV is asserted, RXER is asserted for one or more REF_CLK periods to indicate that a symbol error (for
example, a coding error that a PHY can detect that may otherwise be undetectable by the MAC sub-layer) is detected
somewhere in the frame that is being transferred from the PHY to the MAC.
RXER transitions synchronously with respect to REF_CLK.
3.2.1.7 Collision Detection (COL)
The MAC regenerates the COL signal of the MII from TXEN and CRS_DV.
3.2.2 RMII SIGNAL DIAGRAM – 25/50 MHZ CLOCK MODE
The KSZ8091RNA/RND RMII pin connections to the MAC for 25 MHz clock mode are shown in Figure 3-2. The con-
nections for 50 MHz clock mode are shown in Figure 3-3.
3.2.2.1 RMII – 25 MHz Clock Mode
The KSZ8091RNA is configured to RMII – 25 MHz clock mode after it is powered up or hardware reset with the following:
A 25 MHz crystal connected to XI, XO (Pins 8, 7), or an external 25 MHz clock source (oscillator) connected to XI
The KSZ8091RND can optionally be configured to RMII – 25 MHz clock mode after it is powered up or hardware reset
and software programmed with the following:
A 25 MHz crystal connected to XI, XO (Pins 8, 7), or an external 25 MHz clock source (oscillator) connected to XI
Register 1Fh, Bit [7] programmed to ‘1’ to select RMII – 25 MHz clock mode
3.2.2.2 RMII – 50 MHz Clock Mode
The KSZ8091RND is configured to RMII – 50 MHz clock mode after it is powered up or hardware reset with the follow-
ing:
An external 50 MHz clock source (oscillator) connected to XI (Pin 8)
The KSZ8091RNA can optionally be configured to RMII – 50 MHz clock mode after it is powered up or hardware reset
and software programmed with the following:
An external 50 MHz clock source (oscillator) connected to XI (Pin 8)
Register 1Fh, Bit [7] programmed to ‘1’ to select RMII – 50 MHz clock mode
FIGURE 3-2: KSZ8091RNA/RND RMII INTERFACE (RMII – 25 MHZ CLOCK MODE)
'
KSZ8091RNA/RND
CRS_DV
RXD[1:0]
RXER
TXD[1:0]
RMII MAC
CRS_DV
RXD[1:0]
TXD[1:0]
RX_ER
REF_CLK REF_CLK
TXEN TX_EN
XO XI
25MHz
XTAL
22pF 22pF
XM TXP/T TxD
2016 Microchip Technology Inc. DS00002298A-page 15
KSZ8091RNA/RND
FIGURE 3-3: KSZ8091RNA/RND RMII INTERFACE (RMII – 50 MHZ CLOCK MODE)
3.3 Back-to-Back Mode – 100 Mbps Copper Repeater
Two KSZ8091RNA/RND devices can be connected back-to-back to form a 100BASE-TX copper repeater.
FIGURE 3-4: KSZ8091RNA/RND TO KSZ8091RNA/RND BACK-TO-BACK COPPER REPEATER
KSZ8091RNA/RND
CRS_DV
RXD[1:0]
RXER
TXD[1:0]
RMII MAC
CRS_DV
RXD[1:0]
TXD[1:0]
RX_ER
REF_CLK
TXEN TX_EN
XI
50MHz
OSC
KSZ8091RNA/RND
(COPPER MODE)
RXP/RXM
TXP/TXM
RxD
TxD
RxD
TxD
OSC
XI
XI
50MHz
TXP/TXM
RXP/RXM
(COPPER MODE)
KSZ8091RNA/RND
MDC/
MDIO
KSZ8091RNA/RND
DS00002298A-page 16 2016 Microchip Technology Inc.
3.3.1 RMII BACK-TO-BACK MODE
In RMII back-to-back mode, a KSZ8091RNA/RND interfaces with another KSZ8091RNA/RND to provide a complete
100 Mbps copper repeater solution.
The KSZ8091RNA/RND devices are configured to RMII back-to-back mode after power-up or reset, and software pro-
gramming, with the following:
A common 50 MHz reference clock connected to XI (Pin 8) of both KSZ8091RNA/RND devices.
Register 1Fh, Bit [7] programmed to ‘1’ to select RMII – 50 MHz clock mode for KSZ8091RNA.
(KSZ8091RND is set to RMII – 50 MHz clock mode as the default after power up or hardware reset).
Register 16h, Bits [6] and [1] programmed to ‘1’ and ‘1’, respectively, to enable RMII back-to-back mode.
RMII signals connected as shown in Table 3-2.
3.4 MII Management (MIIM) Interface
The KSZ8091RNA/RND supports the IEEE 802.3 MII management interface, also known as the Management Data
Input/Output (MDIO) interface. This interface allows an upper-layer device, such as a MAC processor, to monitor and
control the state of the KSZ8091RNA/RND. An external device with MIIM capability is used to read the PHY status and/
or configure the PHY settings. More details about the MIIM interface can be found in Clause 22.2.4 of the IEEE 802.3
Specification.
The MIIM interface consists of the following:
A physical connection that incorporates the clock line (MDC) and the data line (MDIO).
A specific protocol that operates across the physical connection mentioned earlier, which allows the external con-
troller to communicate with one or more PHY devices.
A 32-register address space for direct access to IEEE-defined registers and vendor-specific registers, and for indi-
rect access to MMD addresses and registers. See the Register Descriptions section.
The KSZ8091RNA/RND supports only two unique PHY addresses. The PHYAD[1:0] strapping pin is used to select
either 0h or 3h as the unique PHY address for the KSZ8091RNA/RND device.
PHY Address 0h is defined as the broadcast PHY address according to the IEEE 802.3 Specification, and can be used
to read/write to a single PHY device, or write to multiple PHY devices simultaneously. For the KSZ8091RNA/RND, PHY
Address 0h defaults to the broadcast PHY address after power-up, but PHY Address 0h can be disabled as the broad-
cast PHY address using software to assign it as a unique PHY address.
For applications that require two KSZ8091RNA/RND PHYs to share the same MDIO interface with one PHY set to
Address 0h and the other PHY set to Address 3h, use PHY Address 0h (defaults to broadcast after power-up) to set
both PHYs’ Register 16h, Bit [9] to ‘1’ to assign PHY Address 0h as a unique (non-broadcast) PHY address.
The MIIM interface can operates up to a maximum clock speed of 10 MHz MAC clock.
Table 3-3 shows the MII management frame format for the KSZ8091RNA/RND.
TABLE 3-2: RMII SIGNAL CONNECTION FOR RMII BACK-TO-BACK MODE (100 BASE-TX
COPPER REPEATER)
KSZ8091RNA/RND (100BASE-TX Copper)
[Device 1] KSZ8091RNA/RND (100BASE-TX Copper)
[Device 2]
Pin Name Pin Number Pin Type Pin Name Pin Number Pin Type
CRSDV 15 Output TXEN 19 Input
RXD1 12 Output TXD1 21 Input
RXD0 13 Output TXD0 20 Input
TXEN 19 Input CRSDV 15 Output
TXD1 21 Input RXD1 12 Output
TXD0 20 Input RXD0 13 Output
2016 Microchip Technology Inc. DS00002298A-page 17
KSZ8091RNA/RND
3.5 Interrupt (INTRP)
INTRP (Pin 18) is an optional interrupt signal that is used to inform the external controller that there has been a status
update to the KSZ8091RNA/RND PHY register. Bits [15:8] of Register 1Bh are the interrupt control bits to enable and
disable the conditions for asserting the INTRP signal. Bits [7:0] of Register 1Bh are the interrupt status bits to indicate
which interrupt conditions have occurred. The interrupt status bits are cleared after reading Register 1Bh.
Bit [9] of Register 1Fh sets the interrupt level to active high or active low. The default is active low.
The MII management bus option gives the MAC processor complete access to the KSZ8091RNA/RND control and sta-
tus registers. Additionally, an interrupt pin eliminates the need for the processor to poll the PHY for status change.
3.6 HP Auto MDI/MDI-X
HP Auto MDI/MDI-X configuration eliminates the need to decide whether to use a straight cable or a crossover cable
between the KSZ8091RNA/RND and its link partner. This feature allows the KSZ8091RNA/RND to use either type of
cable to connect with a link partner that is in either MDI or MDI-X mode. The auto-sense function detects transmit and
receive pairs from the link partner and assigns transmit and receive pairs to the KSZ8091RNA/RND accordingly.
HP Auto MDI/MDI-X is enabled by default. It is disabled by writing a ‘1’ to Register 1Fh, bit [13]. MDI and MDI-X mode
is selected by Register 1Fh, bit [14] if HP Auto MDI/MDI-X is disabled.
An isolation transformer with symmetrical transmit and receive data paths is recommended to support Auto MDI/MDI-X.
Table 3-4 shows how the IEEE 802.3 Standard defines MDI and MDI-X.
3.6.1 STRAIGHT CABLE
A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. Figure 3-5 shows
a typical straight cable connection between a NIC card (MDI device) and a switch or hub (MDI-X device).
TABLE 3-3: MII MANAGEMENT FRAME FORMAT FOR THE KSZ8091RNA/RND
Preamble Start of
Frame
Read/
Write OP
Code
PHY
Address
Bits[4:0]
REG
Address
Bits[4:0] TA Data Bits[15:0] Idle
Read 32 1’s 01 10 000AA RRRRR Z0 DDDDDDDD_DDDDDDDD Z
Write 32 1’s 01 01 000AA RRRRR 10 DDDDDDDD_DDDDDDDD Z
TABLE 3-4: MDI/MDI-X PIN DESCRIPTION
MDI MDI-X
RJ-45 Pin Signal RJ-45 Pin Signal
1 TX+ 1 RX+
2TX–2RX
3 RX+ 3 TX+
6 RX– 6 TX–
KSZ8091RNA/RND
DS00002298A-page 18 2016 Microchip Technology Inc.
3.6.2 CROSSOVER CABLE
A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device.
Figure 3-6 shows a typical crossover cable connection between two switches or hubs (two MDI-X devices).
3.7 Loopback Mode
The KSZ8091RNA/RND supports the following loopback operations to verify analog and/or digital data paths.
FIGURE 3-5: TYPICAL STRAIGHT CABLE CONNECTION
FIGURE 3-6: TYPICAL CROSSOVER CABLE CONNECTION
RECEIVE PAIR
TRANSMIT PAIR
RECEIVE PAIR
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
TRANSMIT PAIR
MODULAR CONNECTOR
(RJ-45)
NIC
STRAIGHT
CABLE
10/100 ETHERNET
MEDIA DEPENDENT INTERFACE
10/100 ETHERNET
MEDIA DEPENDENT INTERFACE
MODULAR CONNECTOR
(RJ-45)
HUB
(REPEATER OR SWITCH)
2016 Microchip Technology Inc. DS00002298A-page 19
KSZ8091RNA/RND
Local (digital) loopback
Remote (analog) loopback
3.7.1 LOCAL (DIGITAL) LOOPBACK
This loopback mode checks the MII/RMII transmit and receive data paths between the KSZ8091RNA/RND and the
external MAC, and is supported for both speeds (10/100 Mbps) at full-duplex.
The loopback data path is shown in Figure 3-7.
1. The MII/RMII MAC transmits frames to the KSZ8091RNA/RND.
2. Frames are wrapped around inside the KSZ8091RNA/RND.
3. The KSZ8091RNA/RND transmits frames back to the MII/RMII MAC.
4. Except the frames back to the RMII MAC, the transmit frames also go out from the copper port.
The following programming action and register settings are used for local loopback mode:
For 10/100 Mbps loopback:
Set Register 0h,
Bit [14] = 1 // Enable local loopback mode
Bit [13] = 0/1 // Select 10 Mbps/100 Mbps speed
Bit [12] = 0 // Disable auto-negotiation
Bit [8] = 1 // Select full-duplex mode
3.7.2 REMOTE (ANALOG) LOOPBACK
This loopback mode checks the line (differential pairs, transformer, RJ-45 connector, Ethernet cable) transmit and
receive data paths between the KSZ8091RNA/RND and its link partner, and is supported for 100BASE-TX full-duplex
mode only.
The loopback data path is shown in Figure 3-8.
1. The Fast Ethernet (100BASE-TX) PHY link partner transmits frames to the KSZ8091RNA/RND.
2. Frames are wrapped around inside the KSZ8091RNA/RND.
3. The KSZ8091RNA/RND transmits frames back to the Fast Ethernet (100BASE-TX) PHY link partner.
FIGURE 3-7: LOCAL (DIGITAL) LOOPBACK
RMII
MAC
RMII
AFE
(ANALOG)
KSZ8091RNA/RND
PCS
(DIGITAL)
KSZ8091RNA/RND
DS00002298A-page 20 2016 Microchip Technology Inc.
The following programming steps and register settings are used for remote loopback mode:
1. Set Register 0h,L
Bits [13] = 1 // Select 100 Mbps speed
Bit [12] = 0 // Disable auto-negotiation
Bit [8] = 1 // Select full-duplex mode
Or just auto-negotiate and link up at 100BASE-TX full-duplex mode with the link partner.
2. Set Register 1Fh,
Bit [2] = 1 // Enable remote loopback mode
3.8 LinkMD® Cable Diagnostic
The LinkMD function uses time-domain reflectometry (TDR) to analyze the cabling plant for common cabling problems.
These include open circuits, short circuits, and impedance mismatches.
LinkMD works by sending a pulse of known amplitude and duration down the MDI or MDI-X pair, then analyzing the
shape of the reflected signal to determine the type of fault. The time duration for the reflected signal to return provides
the approximate distance to the cabling fault. The LinkMD function processes this TDR information and presents it as
a numerical value that can be translated to a cable distance.
LinkMD is initiated by accessing register 1Dh, the LinkMD Cable Diagnostic register, in conjunction with Register 1Fh,
the PHY Control 2 Register. The latter register is used to disable Auto MDI/MDI-X and to select either MDI or MDI-X as
the cable differential pair for testing.
3.8.1 USAGE
The following is a sample procedure for using LinkMD with Registers 1Dh and 1Fh:
1. Disable auto MDI/MDI-X by writing a ‘1’ to Register 1Fh, bit [13].
2. Start cable diagnostic test by writing a ‘1’ to Register 1Dh, bit [15]. This enable bit is self-clearing.
3. Wait (poll) for Register 1Dh, bit [15] to return a ‘0’, and indicating cable diagnostic test is completed.
4. Read cable diagnostic test results in Register 1Dh, bits [14:13]. The results are as follows:
00 = normal condition (valid test)
01 = open condition detected in cable (valid test)
10 = short condition detected in cable (valid test)
11 = cable diagnostic test failed (invalid test)
FIGURE 3-8: REMOTE (ANALOG) LOOPBACK
RJ-45
RJ-45
CAT-5
(UTP)
100BASE-TX
LINK PARTNER
AFE
(ANALOG)
PCS
(DIGITAL) RMII
2016 Microchip Technology Inc. DS00002298A-page 21
KSZ8091RNA/RND
The ‘11’ case, invalid test, occurs when the device is unable to shut down the link partner. In this instance, the test is
not run because it would be impossible for the device to determine if the detected signal is a reflection of the signal
generated or a signal from another source.
5. Get distance to fault by concatenating Register 1Dh, bits [8:0] and multiplying the result by a constant of 0.38.
The distance to the cable fault can be determined by the following formula:
EQUATION 3-1:
D (distance to cable fault) is expressed in meters.
Concatenated value of Registers 1Dh bits [8:0] should be converted to decimal before multiplying by 0.38.
The constant (0.38) may be calibrated for different cabling conditions, including cables with a velocity of propagation
that varies significantly from the norm.
3.9 NAND Tree Support
The KSZ8091RNA/RND provides parametric NAND tree support for fault detection between chip I/Os and board. The
NAND tree is a chain of nested NAND gates in which each KSZ8091RNA/RND digital I/O (NAND tree input) pin is an
input to one NAND gate along the chain. At the end of the chain, the TXD1 pin provides the output for the nested NAND
gates.
The NAND tree test process includes:
Enabling NAND tree mode
Pulling all NAND tree input pins high
Driving each NAND tree input pin low, sequentially, according to the NAND tree pin order
Checking the NAND tree output to make sure there is a toggle high-to-low or low-to-high for each NAND tree input
driven low
Table 3-5 list the NAND tree pin order for KSZ8091RNA/RND.
TABLE 3-5: NAND TREE TEST PIN ORDER FOR KSZ8091RNA/RND
Pin Number Pin Name NAND Tree Description
10 MDIO Input
11 MDC Input
12 RXD1 Input
13 RXD0 Input
15 CRS_DV Input
16 REF_CLK Input
18 INTRP Input
19 TXEN Input
23 LED0 Input
20 TXD0 Input
21 TXD1 Output
DDistance to cable fault in meters0.38 Register 1Dh, bits[8:0]=
KSZ8091RNA/RND
DS00002298A-page 22 2016 Microchip Technology Inc.
3.9.1 NAND TREE I/O TESTING
Use the following procedure to check for faults on the KSZ8091RNA/RND digital I/O pin connections to the board:
1. Enable NAND tree mode by setting Register 16h, Bit [5] to ‘1’.
2. Use board logic to drive all KSZ8091RNA/RND NAND tree input pins high.
3. Use board logic to drive each NAND tree input pin, in KSZ8091RNA/RND NAND tree pin order, as follows:
a) Toggle the first pin (MDIO) from high to low, and verify that the TXD1 pin switches from high to low to indicate
that the first pin is connected properly.
b) Leave the first pin (MDIO) low.
c) Toggle the second pin (MDC) from high to low, and verify that the TXD1 pin switches from low to high to
indicate that the second pin is connected properly.
d) Leave the first pin (MDIO) and the second pin (MDC) low.
e) Toggle the third pin (RXD1) from high to low, and verify that the TXD1 pin switches from high to low to indi-
cate that the third pin is connected properly.
f) Continue with this sequence until all KSZ8091RNA/RND NAND tree input pins have been toggled.
Each KSZ8091RNA/RND NAND tree input pin must cause the TXD1 output pin to toggle high-to-low or low-to-high to
indicate a good connection. If the TXD1 pin fails to toggle when the KSZ8091RNA/RND input pin toggles from high to
low, the input pin has a fault.
3.10 Power Management
The KSZ8091RNA/RND incorporates a number of power-management modes and features that provide methods to
consume less energy. These are discussed in the following sections.
3.10.1 POWER-SAVING MODE
Power-saving mode is used to reduce the transceiver power consumption when the cable is unplugged. It is enabled
by writing a ‘1’ to Register 1Fh, Bit [10], and is in effect when Auto-Negotiation mode is enabled and the cable is dis-
connected (no link).
In this mode, the KSZ8091RNA/RND shuts down all transceiver blocks, except for the transmitter, energy detect, and
PLL circuits.
By default, power-saving mode is disabled after power-up.
3.10.2 ENERGY-DETECT POWER-DOWN MODE
Energy-detect power-down (EDPD) mode is used to further reduce transceiver power consumption when the cable is
unplugged. It is enabled by writing a ‘0’ to Register 18h, Bit [11], and is in effect when Auto-Negotiation mode is enabled
and the cable is disconnected (no link).
EDPD mode works with the PLL off (set by writing a ‘1’ to Register 10h, Bit [4] to automatically turn the PLL off in EDPD
mode) to turn off all KSZ8091RNA/RND transceiver blocks except the transmitter and energy-detect circuits.
Power can be reduced further by extending the time interval between transmissions of link pulses to check for the pres-
ence of a link partner. The periodic transmission of link pulses is needed to ensure the KSZ8091RNA/RND and its link
partner, when operating in the same low-power state and with Auto MDI/MDI-X disabled, can wake up when the cable
is connected between them.
By default, EDPD mode is disabled after power-up.
3.10.3 POWER-DOWN MODE
Power-down mode is used to power down the KSZ8091RNA/RND device when it is not in use after power-up. It is
enabled by writing a ‘1’ to Register 0h, Bit [11].
In this mode, the KSZ8091RNA/RND disables all internal functions except the MII management interface. The
KSZ8091RNA/RND exits (disables) power-down mode after Register 0h, Bit [11] is set back to ‘0’.
3.10.4 SLOW-OSCILLATOR MODE
Slow-oscillator mode is used to disconnect the input reference crystal/clock on XI (Pin 8) and select the on-chip slow
oscillator when the KSZ8091RNA/RND device is not in use after power-up. It is enabled by writing a ‘1’ to Register 11h,
Bit [5].
2016 Microchip Technology Inc. DS00002298A-page 23
KSZ8091RNA/RND
Slow-oscillator mode works in conjunction with power-down mode to put the KSZ8091RNA/RND device in the lowest
power state, with all internal functions disabled except the MII management interface. To properly exit this mode and
return to normal PHY operation, use the following programming sequence:
1. Disable slow-oscillator mode by writing a ‘0’ to Register 11h, Bit [5].
2. Disable power-down mode by writing a ‘0’ to Register 0h, Bit [11].
3. Initiate software reset by writing a ‘1’ to Register 0h, Bit [15].
3.11 Energy Efficient Ethernet (EEE)
The KSZ8091RNA/RND implements Energy Efficient Ethernet (EEE) as described in the IEEE Standard 802.3az for
100BASE-TX copper signaling by the two differential pairs (analog side) and according to the multi-source agreement
(MSA) of collaborating Fast Ethernet chip vendors for the RMII (digital side). The MSA agreement is based on the IEEE
Standard’s EEE implementation for the 100 Mbps Media Independent Interface (MII). The IEEE Standard is defined
around an EEE-compliant MAC on the host side and an EEE-compliant link partner on the line side that support special
signaling associated with EEE. EEE saves power by keeping the AC signal on the copper Ethernet cable at approxi-
mately 0V peak-to-peak as often as possible during periods of no traffic activity, while maintaining the link-up status.
This is referred to as low-power idle (LPI) mode or state.
During LPI mode, the copper link responds automatically when it receives traffic and resumes normal PHY operation
immediately, without blockage of traffic or loss of packet. This involves exiting LPI mode and returning to normal
100 Mbps operating mode. Wake-up time is <30 µs for 100BASE-TX.
The LPI state is controlled independently for transmit and receive paths, allowing the LPI state to be active (enabled) for:
Transmit cable path only
Receive cable path only
Both transmit and receive cable paths
The KSZ8091RNA/RND has the EEE function disabled as the power-up default setting. To enable the EEE function for
100 Mbps mode, use the following programming sequence:
1. Enable 100 Mbps EEE mode advertisement by writing a ‘1’ to MMD address 7h, Register 3Ch, bit [1].
2. Restart auto-negotiation by writing a ‘1’ to standard Register 0h, bit [9].
For standard (non-EEE) 10BASE-T mode, normal link pulses (NLPs) with long periods of no AC signal transmission are
used to maintain the link during the idle period when there is no traffic activity. To save more power, the KSZ8091RNA/
RND provides the option to enable 10BASE-Te mode, which saves additional power by reducing the transmitted signal
amplitude from 2.5V to 1.75V. To enable 10BASE-Te mode, write a ‘1’ to standard Register 13h, bit [4].
During LPI mode, refresh transmissions are used to maintain the link; power savings occur in quiet periods. Approxi-
mately every 20 to 22 milliseconds, a refresh transmission of 200 to 220 microseconds is sent to the link partner. The
refresh transmissions and quiet periods are shown in Figure 3-9.
FIGURE 3-9: LPI MODE (REFRESH TRANSMISSIONS AND QUIET PERIODS)
ACTIVE
DATA/
IDLE
SLEEP
REFRESH
QUIET QUIET QUIET
REFRESH
WAKE
IDLE
DATA/
IDLE
LOW-POWER ACTIVE
TS TQ TR TW_PHY
TW_SYSTEM
mmm >C>C>
KSZ8091RNA/RND
DS00002298A-page 24 2016 Microchip Technology Inc.
3.11.1 TRANSMIT DIRECTION CONTROL (MAC-TO-PHY)
The KSZ8091RNA/RND enters LPI mode for the transmit direction when its attached EEE-compliant RMII MAC de-
asserts TXEN and sets TXD[1:0] to 01. The KSZ8091RNA/RND remains in the LPI transmit state while the RMII MAC
maintains the states of these signals. When the RMII MAC changes any of the TXEN or TX data signals from their LPI
state values, the KSZ8091RNA/RND exits the LPI transmit state.
Figure 3-10 shows the LPI transition for MII (100 Mbps) transmit.
3.11.2 RECEIVE DIRECTION CONTROL (PHY-TO-MAC)
The KSZ8091RNA/RND enters LPI mode for the receive direction when it receives the /P/ code bit pattern (Sleep/
Refresh) from its EEE-compliant link partner. It then de-asserts CRS_DV and drives RXD[1:0] to 01. The KSZ8091RNA/
RND remains in the LPI receive state while it continues to receive the refresh from its link partner, so it will continue to
maintain and drive the LPI output states for the RMII receive signals to inform the attached EEE-compliant RMII MAC
that it is in the LPI receive state. When the KSZ8091RNA/RND receives a non /P/ code bit pattern (non-refresh), it exits
the LPI receive state and sets the CRS_DV and RX data signals to set a normal frame or normal idle.
Figure 3-11 shows the LPI transition for RMII (100 Mbps) receive.
3.11.3 REGISTERS ASSOCIATED WITH EEE
The following registers are provided for EEE configuration and management:
Standard Register 13h - AFE Control 4 (to enable 10BASE-Te mode)
MMD address 1h, Register 0h - PMA/PMD Control 1 (to enable LPI)
MMD address 1h, Register 1h - PMA/PMD Status 1 (for LPI status)
MMD address 3h, Register 0h - EEE PCS Control 1 (to stop RXC clock for KSZ8091MNX only)
MMD address 7h, Register 3Ch - EEE Advertisement
MMD address 7h, Register 3Dh - EEE Link Partner Advertisement
FIGURE 3-10: LPI TRANSITION - RMII (100 MBPS) TRANSMIT
FIGURE 3-11: LPI TRANSITION - RMII (100 MBPS) RECEIVE
REF_CLK
TXEN
TXD[1:0] XX XX 00 00
01 01
DATA IDLE ASSERT LPI IDLE PREAMBLE
WAKE
TIME
REF_CLK
CRS_DV
RXD[1:0] XX XX 00 00
01 01
DATA IDLE ASSERT LPI IDLE PREAMBLE
2016 Microchip Technology Inc. DS00002298A-page 25
KSZ8091RNA/RND
3.12 Wake-On-LAN
Wake-On-LAN (WOL) is normally a MAC-based function to wake up a host system (for example, an Ethernet end
device, such as a PC) that is in standby power mode. Wake-up is triggered by receiving and detecting a special packet
(commonly referred to as the “magic packet”) that is sent by the remote link partner. The KSZ8091RNA/RND can per-
form the same WOL function if the MAC address of its associated MAC device is entered into the KSZ8091RNA/RND
PHY Registers for magic-packet detection. When the KSZ8091RNA/RND detects the magic packet, it wakes up the host
by driving its power management event (PME) output pin low.
By default, the WOL function is disabled. It is enabled by setting the enabling bit and configuring the associated registers
for the selected PME wake-up detection method.
The KSZ8091RNA/RND provides three methods to trigger a PME wake-up:
Magic-packet detection
•Customized-packet detection
Link status change detection
3.12.1 MAGIC-PACKET DETECTION
The magic packet’s frame format starts with 6 bytes of 0xFFh and is followed by 16 repetitions of the MAC address of
its associated MAC device (local MAC device).
When the magic packet is detected from its link partner, the KSZ8091RNA/RND asserts its PME output pin low.
The following MMD address 1Fh registers are provided for magic-packet detection:
Magic-packet detection is enabled by writing a ‘1’ to MMD address 1Fh, Register 0h, bit [6]
The MAC address (for the local MAC device) is written to and stored in MMD address 1Fh, Registers 19h – 1Bh
The KSZ8091RNA/RND does not generate the magic packet. The magic packet must be provided by the external sys-
tem.
3.12.2 CUSTOMIZED-PACKET DETECTION
The customized packet has associated register/bit masks to select which byte, or bytes, of the first 64 bytes of the packet
to use in the CRC calculation. After the KSZ8091RNA/RND receives the packet from its link partner, the selected bytes
for the received packet are used to calculate the CRC. The calculated CRC is compared to the expected CRC value
that was previously written to and stored in the KSZ8091RNA/RND PHY Registers. If there is a match, the
KSZ8091RNA/RND asserts its PME output pin low.
Four customized packets are provided to support four types of wake-up scenarios. A dedicated set of registers is used
to configure and enable each customized packet.
The following MMD Registers are provided for customized-packet detection:
Each of the four customized packets is enabled via MMD address 1Fh, Register 0h,
- Bit [2] // For customized packets, type 0
- Bit [3] // For customized packets, type 1
- Bit [4] // For customized packets, type 2
- Bit [5] // For customized packets, type 3
Masks to indicate which of the first 64-bytes to use in the CRC calculation are set in:
- MMD address 1Fh, Registers 1h – 4h // For customized packets, type 0
- MMD address 1Fh, Registers 7h – Ah // For customized packets, type 1
- MMD address 1Fh, Registers Dh – 10h // For customized packets, type 2
- MMD address 1Fh, Registers 13h – 16h // For customized packets, type 3
32-bit expected CRCs are written to and stored in:
- MMD address 1Fh, Registers 5h – 6h // For customized packets, type 0
- MMD address 1Fh, Registers Bh – Ch // For customized packets, type 1
- MMD address 1Fh, Registers 11h – 12h // For customized packets, type 2
- MMD address 1Fh, Registers 17h – 18h // For customized packets, type 3
FIE? 4—1 4—1
KSZ8091RNA/RND
DS00002298A-page 26 2016 Microchip Technology Inc.
3.12.3 LINK STATUS CHANGE DETECTION
If link status change detection is enabled, the KSZ8091RNA/RND asserts its PME output pin low whenever there is a
link status change, using the following MMD Address 1Fh register bits and their enabled (1) or disabled (0) settings:
MMD address 1Fh, Register 0h, bit [0] // For link-up detection
MMD address 1Fh, Register 0h, bit [1] // For link-down detection
The PME output signal is available on either INTRP/PME_N2 (Pin 18) or LED0/PME_N1 (pin 23), and is enabled using
standard Register 16h, Bit [15]. MMD Address 1Fh, Register 0h, Bits [15:14] defines and selects the output functions
for Pins 18 and 23.
The PME output is active low and requires a 1 k pull-up to the VDDIO supply. When asserted, the PME output is
cleared by disabling the register bit that enabled the PME trigger source (magic packet, customized packet, link status
change).
3.13 Reference Circuit for Power and Ground Connections
The KSZ8091RNA/RND is a single 3.3V supply device with a built-in regulator to supply the 1.2V core. The power and
ground connections are shown in Figure 3-12 and Table 3-6 for 3.3V VDDIO.
FIGURE 3-12: KSZ8091RNA/RND POWER AND GROUND CONNECTIONS
TABLE 3-6: KSZ8091RNA/RND POWER PIN DESCRIPTION
Power Pin Pin Number Description
VDD_1.2 1 Decouple with 2.2 µF and 0.1 µF capacitors to ground.
VDDA_3.3 2 Connect to board’s 3.3V supply through a ferrite bead.
Decouple with 22 µF and 0.1 µF capacitors to ground.
VDDIO 47 Connect to board’s 3.3V supply for 3.3V VDDIO.
Decouple with 22 µF and 0.1 µF capacitors to ground.
VDDIO
KSZ8091RNA/RND
GND
3.3V
VDDA_3.3
0.1μF
1
VDD_1.2
2
FERRITE
BEAD
14
22
PADDLE
2.2μF
0.1μF22μF
0.1μF22μF
2016 Microchip Technology Inc. DS00002298A-page 27
KSZ8091RNA/RND
3.14 Typical Current/Power Consumption
Table 3-7, Table 3-8, and Ta b l e 3 - 9 show typical values for current consumption by the transceiver (VDDA_3.3) and dig-
ital I/O (VDDIO) power pins, and typical values for power consumption by the KSZ8091RNA/RND device for the indi-
cated nominal operating voltages. These current and power consumption values include the transmit driver current and
on-chip regulator current for the 1.2V core.
TABLE 3-7: TYPICAL CURRENT/POWER CONSUMPTION (VDDA_3.3 = 3.3V, VDDIO = 3.3V)
Condition 3.3V Transceiver
(VDDA_3.3) 3.3V Digital I/Os
(VDDIO) Total Chip Power
100BASE-TX Link-up (no traffic) 34 mA 12 mA 152 mW
100BASE-TX Full-duplex @ 100% utilization 34 mA 13 mA 155 mW
10BASE-T Link-up (no traffic) 14 mA 11 mA 82.5 mW
10BASE-T Full-duplex @ 100% utilization 30 mA 11 mA 135 mW
EEE 100 Mbps Link-up mode
(transmit and receive in LPI state with no traffic)
13 mA 10 mA 75.9 mW
Power-saving mode (Reg. 1Fh, Bit [10] = 1) 13 mA 10 mA 75.9 mW
EDPD mode (Reg. 18h, Bit [11] = 0) 10 mA 10 mA 66 mW
EDPD mode (Reg. 18h, Bit [11] = 0) and
PLL off (Reg. 10h, Bit [4] = 1)
3.77 mA 1.54 mA 17.5 mW
Software power-down mode (Reg. 0h, Bit [11] =1) 2.59 mA 1.51 mA 13.5 mW
Software power-down mode (Reg. 0h, Bit [11] =1)
and slow-oscillator mode (Reg. 11h, Bit [5] =1)
1.36 mA 0.45 mA 5.97 mW
TABLE 3-8: TYPICAL CURRENT/POWER CONSUMPTION (VDDA_3.3 = 3.3V, VDDIO = 2.5V)
Condition 3.3V Transceiver
(VDDA_3.3) 2.5V Digital I/Os
(VDDIO) Total Chip Power
100BASE-TX Link-up (no traffic) 34 mA 11 mA 140 mW
100BASE-TX Full-duplex @ 100% utilization 34 mA 12 mA 142 mW
10BASE-T Link-up (no traffic) 15 mA 10 mA 74.5 mW
10BASE-T Full-duplex @ 100% utilization 27 mA 10 mA 114 mW
EEE 100 Mbps Link-up mode
(transmit and receive in LPI state with no traffic)
13 mA 10 mA 67.9 mW
Power-saving mode (Reg. 1Fh, Bit [10] = 1) 13 mA 10 mA 67.9 mW
EDPD mode (Reg. 18h, Bit [11] = 0) 11 mA 10 mA 61.3 mW
EDPD mode (Reg. 18h, Bit [11] = 0) and
PLL off (Reg. 10h, Bit [4] = 1)
3.55 mA 1.35 mA 15.1 mW
Software power-down mode (Reg. 0h, Bit [11] =1) 2.29 mA 1.34 mA 10.9 mW
Software power-down mode (Reg. 0h, Bit [11] =1)
and slow-oscillator mode (Reg. 11h, Bit [5] =1)
1.15 mA 0.29 mA 4.52 mW
TABLE 3-9: TYPICAL CURRENT/POWER CONSUMPTION (VDDA_3.3 = 3.3V, VDDIO = 1.8V)
Condition 3.3V Transceiver
(VDDA_3.3) 1.8V Digital I/Os
(VDDIO) Total Chip Power
100BASE-TX Link-up (no traffic) 34 mA 11 mA 132 mW
100BASE-TX Full-duplex @ 100% utilization 34 mA 12 mA 134 mW
10BASE-T Link-up (no traffic) 15 mA‘ 9 mA 65.7 mW
10BASE-T Full-duplex @ 100% utilization 27 mA 9 mA 105 mW
KSZ8091RNA/RND
DS00002298A-page 28 2016 Microchip Technology Inc.
EEE 100 Mbps Link-up mode
(transmit and receive in LPI state with no traffic)
13 mA 9 mA 59.1 mW
Power-saving mode (Reg. 1Fh, Bit [10] = 1) 13 mA 9 mA 59.1 mW
EDPD mode (Reg. 18h, Bit [11] = 0) 11 mA 9 mA 52.5 mW
EDPD mode (Reg. 18h, Bit [11] = 0) and
PLL off (Reg. 10h, Bit [4] = 1)
4.05 mA 1.21 mA 15.5 mW
Software power-down mode (Reg. 0h, Bit [11] =1) 2.79 mA 1.21 mA 11.4 mW
Software power-down mode (Reg. 0h, Bit [11] =1)
and slow-oscillator mode (Reg. 11h, Bit [5] =1)
1.65 mA 0.19 mA 5.79 mW
TABLE 3-9: TYPICAL CURRENT/POWER CONSUMPTION (VDDA_3.3 = 3.3V, VDDIO = 1.8V)
Condition 3.3V Transceiver
(VDDA_3.3) 1.8V Digital I/Os
(VDDIO) Total Chip Power
2016 Microchip Technology Inc. DS00002298A-page 29
KSZ8091RNA/RND
4.0 REGISTER DESCRIPTIONS
The register space within the KSZ8091RNA/RND consists of two distinct areas.
Standard registers // Direct register access
MDIO manageable device (MMD) registers // Indirect register access
The KSZ8091RNA/RND supports the following standard registers.
4.1 Register Map
TABLE 4-1: STANDARD REGISTERS SUPPORTED BY KSZ8091RNA/RND
Register Number (hex) Description
IEEE Defined Registers
0h Basic Control
1h Basic Status
2h PHY Identifier 1
3h PHY Identifier 2
4h Auto-Negotiation Advertisement
5h Auto-Negotiation Link Partner Ability
6h Auto-Negotiation Expansion
7h Auto-Negotiation Next Page
8h Auto-Negotiation Link Partner Next Page Ability
9h - Ch Reserved
Dh MMD Access - Control
Eh MMD Access - Register/Data
Fh Reserved
Vendor Specific Registers
10h Digital Reserved Control
11h AFE Control 1
12h Reserved
13h AFE Control 4
14h Reserved
15h RXER Counter
16h Operation Mode Strap Override
17h Operation Mode Strap Status
18h Expanded Control
19h - 1Ah Reserved
1Bh Interrupt Control/Status
1Ch Reserved
1Dh LinkMD Cable Diagnostic
1Eh PHY Control 1
1Fh PHY Control 2
KSZ8091RNA/RND
DS00002298A-page 30 2016 Microchip Technology Inc.
The KSZ8091RNA/RND supports the following MMD device addresses and their associated register addresses, which
make up the indirect MMD registers.
TABLE 4-2: MMD REGISTERS SUPPORTED BY KSZ8091RNA/RND
Device Address
(Hex) Register Address
(Hex) Description
1h 0h PMA/PMD Control 1
1h PMA/PMD Status 1
7h 3Ch EEE Advertisement
3Dh EEE Link Partner Advertisement
1Ch 4h DSP 10BASE-T/10BASE-Te Control
1Fh
0h Wake-On-LAN – Control
1h Wake-On-LAN – Customized Packet, Type 0, Mask 0
2h Wake-On-LAN – Customized Packet, Type 0, Mask 1
3h Wake-On-LAN – Customized Packet, Type 0, Mask 2
4h Wake-On-LAN – Customized Packet, Type 0, Mask 3
5h Wake-On-LAN – Customized Packet, Type 0, Expected CRC 0
6h Wake-On-LAN – Customized Packet, Type 0, Expected CRC 1
7h Wake-On-LAN – Customized Packet, Type 1, Mask 0
8h Wake-On-LAN – Customized Packet, Type 1, Mask 1
9h Wake-On-LAN – Customized Packet, Type 1, Mask 2
Ah Wake-On-LAN – Customized Packet, Type 1, Mask 3
Bh Wake-On-LAN – Customized Packet, Type 1, Expected CRC 0
Ch Wake-On-LAN – Customized Packet, Type 1, Expected CRC 1
Dh Wake-On-LAN – Customized Packet, Type 2, Mask 0
Eh Wake-On-LAN – Customized Packet, Type 2, Mask 1
Fh Wake-On-LAN – Customized Packet, Type 2, Mask 2
10h Wake-On-LAN – Customized Packet, Type 2, Mask 3
11h Wake-On-LAN – Customized Packet, Type 2, Expected CRC 0
12h Wake-On-LAN – Customized Packet, Type 2, Expected CRC 1
13h Wake-On-LAN – Customized Packet, Type 3, Mask 0
14h Wake-On-LAN – Customized Packet, Type 3, Mask 1
15h Wake-On-LAN – Customized Packet, Type 3, Mask 2
16h Wake-On-LAN – Customized Packet, Type 3, Mask 3
17h Wake-On-LAN – Customized Packet, Type 3, Expected CRC 0
18h Wake-On-LAN – Customized Packet, Type 3, Expected CRC 1
19h Wake-On-LAN – Magic Packet, MAC-DA-0
1Ah Wake-On-LAN – Magic Packet, MAC-DA-1
1Bh Wake-On-LAN – Magic Packet, MAC-DA-2
2016 Microchip Technology Inc. DS00002298A-page 31
KSZ8091RNA/RND
4.2 Standard Registers
Standard registers provide direct read/write access to a 32-register address space, as defined in Clause 22 of the IEEE
802.3 Specification. Within this address space, the first 16 registers (Registers 0h to Fh) are defined according to the
IEEE specification, while the remaining 16 registers (Registers 10h to 1Fh) are defined specific to the PHY vendor.
TABLE 4-3: IEEE DEFINED REGISTER DESCRIPTIONS
Address Name Description Mode
Note 4-1 Default
Register 0h – Basic Control
0.15 Reset
1 = Software reset
0 = Normal operation
This bit is self-cleared after a ‘1’ is written to it.
RW/SC 0
0.14 Loopback 1 = Loopback mode
0 = Normal operation RW 0
0.13 Speed Select
1 = 100 Mbps
0 = 10 Mbps
This bit is ignored if auto-negotiation is enabled
(Register 0.12 = 1).
RW
Set by the ANEN_SPEED
strapping pin.
See the Strap-In Options -
KSZ8091RNA/RND sec-
tion for details.
0.12 Auto-Negoti-
ation Enable
1 = Enable auto-negotiation process
0 = Disable auto-negotiation process
If enabled, the auto-negotiation result over-
rides the settings in Registers 0.13 and 0.8.
RW
Set by the ANEN_SPEED
strapping pin.
See the Strap-In Options -
KSZ8091RNA/RND sec-
tion for details.
0.11 Power-Down
1 = Power-down mode
0 = Normal operation
If software reset (Register 0.15) is used to exit
power-down mode (Register 0.11 = 1), two
software reset writes (Register 0.15 = 1) are
required. The first write clears power-down
mode; the second write resets the chip and re-
latches the pin strap-in pin values.
RW 0
0.10 Isolate 1 = Electrical isolation of PHY from RMII
0 = Normal operation RW 0
0.9 Restart Auto-
Negotiation
1 = Restart auto-negotiation process
0 = Normal operation.
This bit is self-cleared after a ‘1’ is written to it.
RW/SC 0
0.8 Duplex Mode 1 = Full-duplex
0 = Half-duplex RW 1
0.7 Collision Test 1 = Enable COL test
0 = Disable COL test RW 0
0.6:0 Reserved Reserved RO 000_0000
Register 1h - Basic Status
1.15 100BASE-T4 1 = T4 capable
0 = Not T4 capable RO 0
1.14 100BASE-TX
Full-Duplex
1 = Capable of 100 Mbps full-duplex
0 = Not capable of 100 Mbps full-duplex RO 1
1.13 100BASE-TX
Half-Duplex
1 = Capable of 100 Mbps half-duplex
0 = Not capable of 100 Mbps half-duplex RO 1
1.12 10BASE-T
Full-Duplex
1 = Capable of 10 Mbps full-duplex
0 = Not capable of 10 Mbps full-duplex RO 1
1.11 10BASE-T
Half-Duplex
1 = Capable of 10 Mbps half-duplex
0 = Not capable of 10 Mbps half-duplex RO 1
KSZ8091RNA/RND
DS00002298A-page 32 2016 Microchip Technology Inc.
1.10:7 Reserved Reserved RO 000_0
1.6 No Preamble 1 = Preamble suppression
0 = Normal preamble RO 1
1.5
Auto-Negoti-
ation Com-
plete
1 = Auto-negotiation process completed
0 = Auto-negotiation process not completed RO 0
1.4 Remote Fault 1 = Remote fault
0 = No remote fault RO/LH 0
1.3 Auto-Negoti-
ation Ability
1 = Can perform auto-negotiation
0 = Cannot perform auto-negotiation RO 1
1.2 Link Status 1 = Link is up
0 = Link is down RO/LL 0
1.1 Jabber
Detect
1 = Jabber detected
0 = Jabber not detected (default is low) RO/LH 0
1.0 Extended
Capability 1 = Supports extended capability registers RO 1
Register 2h - PHY Identifier 1
2.15:0 PHY ID
Number
Assigned to the 3rd through 18th bits of the
Organizationally Unique Identifier (OUI). KEN-
DIN Communication’s OUI is 0010A1 (hex).
RO 0022h
Register 3h - PHY Identifier 2
3.15:10 PHY ID Num-
ber
Assigned to the 19th through 24th bits of the
Organizationally Unique Identifier (OUI). KEN-
DIN Communication’s OUI is 0010A1 (hex).
RO 0001_01
3.9:4 Model Num-
ber Six-bit manufacturer’s model number RO 01_0110
3.3:0 Revision
Number Four-bit manufacturer’s revision number RO Indicates silicon
revision.
Register 4h - Auto-Negotiation Advertisement
4.15 Next Page 1 = Next page capable
0 = No next page capability RW 1
4.14 Reserved Reserved RO 0
4.13 Remote Fault 1 = Remote fault supported
0 = No remote fault RW 0
4.12 Reserved Reserved RO 0
4.11:10 Pause
[00] = No pause
[10] = Asymmetric pause
[01] = Symmetric pause
[11] = Asymmetric and symmetric pause
RW 00
4.9 100BASE-T4 1 = T4 capable
0 = No T4 capability RO 0
4.8 100BASE-TX
Full-Duplex
1 = 100 Mbps full-duplex capable
0 = No 100 Mbps full-duplex capability RW
Set by the ANEN_SPEED
strapping pin.
See the Strap-In Options -
KSZ8091RNA/RND sec-
tion for details.
TABLE 4-3: IEEE DEFINED REGISTER DESCRIPTIONS (CONTINUED)
Address Name Description Mode
Note 4-1 Default
2016 Microchip Technology Inc. DS00002298A-page 33
KSZ8091RNA/RND
4.7 100BASE-TX
Half-Duplex
1 = 100 Mbps half-duplex capable
0 = No 100 Mbps half-duplex capability RW
Set by the ANEN_SPEED
strapping pin.
See the Strap-In Options -
KSZ8091RNA/RND sec-
tion for details.
4.6 10BASE-T
Full-Duplex
1 = 10 Mbps full-duplex capable
0 = No 10 Mbps full-duplex capability RW 1
4.5 10BASE-T
Half-Duplex
1 = 10 Mbps half-duplex capable
0 = No 10 Mbps half-duplex capability RW 1
4.4:0 Selector
Field [00001] = IEEE 802.3 RW 0_0001
Register 5h - Auto-Negotiation Link Partner Ability
5.15 Next Page 1 = Next page capable
0 = No next page capability RO 0
5.14 Acknowledge 1 = Link code word received from partner
0 = Link code word not yet received RO 0
5.13 Remote Fault 1 = Remote fault detected
0 = No remote fault RO 0
5.12 Reserved Reserved RO 0
5.11:10 Pause
[00] = No pause
[10] = Asymmetric pause
[01] = Symmetric pause
[11] = Asymmetric and symmetric pause
RO 00
5.9 100BASE-T4 1 = T4 capable
0 = No T4 capability RO 0
5.8 100BASE-TX
Full-Duplex
1 = 100 Mbps full-duplex capable
0 = No 100 Mbps full-duplex capability RO 0
5.7 100BASE-TX
Half-Duplex
1 = 100 Mbps half-duplex capable
0 = No 100 Mbps half-duplex capability RO 0
5.6 10BASE-T
Full-Duplex
1 = 10 Mbps full-duplex capable
0 = No 10 Mbps full-duplex capability RO 0
5.5 10BASE-T
Half-Duplex
1 = 10 Mbps half-duplex capable
0 = No 10 Mbps half-duplex capability RO 0
5.4:0 Selector
Field [00001] = IEEE 802.3 RO 0_0001
Register 6h - Auto-Negotiation Expansion
6.15:5 Reserved Reserved RO 0000_0000_000
6.4
Parallel
Detection
Fault
1 = Fault detected by parallel detection
0 = No fault detected by parallel detection RO/LH 0
6.3
Link Partner
Next Page
Able
1 = Link partner has next page capability
0 = Link partner does not have next page
capability
RO 0
6.2 Next Page
Able
1 = Local device has next page capability
0 = Local device does not have next page
capability
RO 1
6.1 Page
Received
1 = New page received
0 = New page not received yet RO/LH 0
TABLE 4-3: IEEE DEFINED REGISTER DESCRIPTIONS (CONTINUED)
Address Name Description Mode
Note 4-1 Default
KSZ8091RNA/RND
DS00002298A-page 34 2016 Microchip Technology Inc.
6.0
Link Partner
Auto-Negoti-
ation Able
1 = Link partner has auto-negotiation capability
0 = Link partner does not have auto-negotia-
tion capability
RO 0
Register 7h - Auto-Negotiation Next Page
7.15 Next Page 1 = Additional next pages will follow
0 = Last page RW 0
7.14 Reserved Reserved RO 0
7.13 Message
Page
1 = Message page
0 = Unformatted page RW 1
7.12 Acknowl-
edge2
1 = Will comply with message
0 = Cannot comply with message RW 0
7.11 Toggle
1 = Previous value of the transmitted link code
word equaled logic 1
0 = Logic 0
RO 0
7.10:0 Message
Field 11-bit wide field to encode 2048 messages RW 000_0000_0001
Register 8h - Auto-Negotiation Link Partner Next Page Ability
8.15 Next Page 1 = Additional next pages will follow
0 = Last page RO 0
8.14 Acknowledge 1 = Successful receipt of link word
0 = No successful receipt of link word RO 0
8.13 Message
Page
1 = Message page
0 = Unformatted page RO 0
8.12 Acknowl-
edge2
1 = Can act on the information
0 = Cannot act on the information RO 0
8.11 Toggle
1 = Previous value of transmitted link code
word equal to logic 0
0 = Previous value of transmitted link code
word equal to logic 1
RO 0
8.10:0 Message
Field 11-bit wide field to encode 2048 messages RO 000_0000_0000
Register Dh - MMD Access - Control
D.15:14
MMD –
Operation
Mode
For the selected MMD device address (bits
[4:0] of this register), these two bits select one
of the following register or data operations and
the usage for MMD Access – Register/Data
(Reg. Eh).
00 = Register
01 = Data, no post increment
10 = Data, post increment on reads and writes
11 = Data, post increment on writes only
RW 00
D.13:5 Reserved Reserved RW 00_0000_000
D.4:0
MMD –
Device
Address
These five bits set the MMD device address. RW 0_0000
TABLE 4-3: IEEE DEFINED REGISTER DESCRIPTIONS (CONTINUED)
Address Name Description Mode
Note 4-1 Default
2016 Microchip Technology Inc. DS00002298A-page 35
KSZ8091RNA/RND
Note 4-1 RW = Read/Write; RO = Read Only; SC = Self-Cleared; LH = Latch High; LL = Latch Low.
Register Eh - MMD Access - Register/Data
E.15:0
MMD –
Register/
Data
For the selected MMD device address (Reg.
Dh, bits [4:0]),
When Reg. Dh, bits [15:14] = 00, this register
contains the read/write register address for the
MMD device address.
Otherwise, this register contains the read/write
data value for the MMD device address and its
selected register address.
See also Reg. Dh, bits [15:14], for descriptions
of post increment reads and writes of this reg-
ister for data operation.
RW 0000_0000_0000_
0000
TABLE 4-4: VENDOR SPECIFIC REGISTER DESCRIPTIONS
Address Name Description Mode
Note 4-1 Default
Register 10h – Digital Reserved Control
10.15:5 Reserved Reserved RW 0000_0000_000
10.4 PLL Off
1 = Turn PLL off automatically in EDPD mode
0 = Keep PLL on in EDPD mode.
See also Register 18h, Bit [11] for EDPD mode
RW 0
10.3:0 Reserved Reserved RW 0000
Register 11h – AFE Control 1
11.15:6 Reserved Reserved RW 0000_0000_00
11.5
Slow-Oscilla-
tor Mode
Enable
Slow-oscillator mode is used to disconnect the
input reference crystal/clock on the XI pin and
select the on-chip slow oscillator when the
KSZ8091RNA/RND device is not in use after
power-up.
1 = Enable
0 = Disable
This bit automatically sets software power-down to
the analog side when enabled.
RW 0
11.4:0 Reserved Reserved RW 0_0000
Register 13h – AFE Control 4
13.15:5 Reserved Reserved RW 0000_0000_00
13.4 10BASE-Te
Mode
1 = EEE 10BASE-Te (1.75V TX amplitude) and
also set MMD Address 1Ch, Register 4h, Bit [13] to
‘0’.
0 = Standard 10BASE-T (2.5V TX amplitude) and
also set MMD Address 1Ch, Register 4h, Bit [13] to
‘1’
RW 0
13.3:0 Reserved Reserved RW 0_0000
Register 15h – RXER Counter
15.15:0 RXER
Counter Receive error counter for symbol error frames RO/SC 0000h
TABLE 4-3: IEEE DEFINED REGISTER DESCRIPTIONS (CONTINUED)
Address Name Description Mode
Note 4-1 Default
KSZ8091RNA/RND
DS00002298A-page 36 2016 Microchip Technology Inc.
Register 16h – Operation Mode Strap Override
16.15 PME Enable
PME for Wake-on-LAN
1 = Enable
0 = Disable
This bit works in conjunction with MMD Address
1Fh, Reg. 0h, Bits [15:14] to define the output for
pins 18 and 23.
RW
Set by the PME_EN
strapping pin.
See the Strapping
Options section for
details.
16.14:11 Reserved Reserved RW 000_0
16.10 Reserved Reserved RO 0
16.9
B-
CAST_OFF
Override
1 = Override to disable broadcast (default setting)
for PHY Address 0
If bit is ‘1’, PHY Address 0 is non-broadcast.
RW 0
16.8:7 Reserved Reserved RW 0_0
16.6 RMII B-to-B
Override
1 = Override strap-in for RMII back-to-back mode
(also set Bit 1 of this register to ‘1’). RW 0
16.5 NAND Tree
Override 1 = Override to enable NAND tree mode. RW 0
16.4:2 Reserved Reserved RW 0_00
16.1 RMII
Override 1 = Override to enable RMII mode. RW 1
16.0 Reserved Reserved RW 0
Register 17h - Operation Mode Strap Status
17.15 Reserved Reserved RO
17.14:13
PHYAD[1:0]
Strap-In Sta-
tus
[00] = Strap to PHY Address 00000b (0h)
[11] = Strap to PHY Address 00011b (3h)
The KSZ8091RNA/RND supports PHY addresses
0h and 3h only.
RO
Set by the
PHYAD[1:0] strap-
ping pin.
See the Strapping
Options section for
details.
17.12:2 Reserved Reserved RO
17.1 RMII Strap-In
Status 1 = Strap to RMII mode RO
17.0 Reserved Reserved RO
Register 18h - Expanded Control
18.15:12 Reserved Reserved RW 0000
18.11 EDPD
Disabled
Energy-detect power-down mode
1 = Disable
0 = Enable
See also Register 10h, Bit [4] for PLL off.
RW 1
18.10:0 Reserved Reserved RW 0000
Register 1Bh – Interrupt Control/Status
1B.15 Jabber Inter-
rupt Enable
1 = Enable jabber interrupt
0 = Disable jabber interrupt RW 0
1B.14
Receive
Error Inter-
rupt Enable
1 = Enable receive error interrupt
0 = Disable receive error interrupt RW 0
TABLE 4-4: VENDOR SPECIFIC REGISTER DESCRIPTIONS (CONTINUED)
Address Name Description Mode
Note 4-1 Default
2016 Microchip Technology Inc. DS00002298A-page 37
KSZ8091RNA/RND
1B.13
Page
Received
Interrupt
Enable
1 = Enable page received interrupt
0 = Disable page received interrupt RW 0
1B.12
Parallel
Detect Fault
Interrupt
Enable
1 = Enable parallel detect fault interrupt
0 = Disable parallel detect fault interrupt RW 0
1B.11
Link Partner
Acknowl-
edge Inter-
rupt Enable
1 = Enable link partner acknowledge interrupt
0 = Disable link partner acknowledge interrupt RW 0
1B.10
Link-Down
Interrupt
Enable
1= Enable link-down interrupt
0 = Disable link-down interrupt RW 0
1B.9
Remote Fault
Interrupt
Enable
1 = Enable remote fault interrupt
0 = Disable remote fault interrupt RW 0
1B.8
Link-Up
Interrupt
Enable
1 = Enable link-up interrupt
0 = Disable link-up interrupt RW 0
1B.7 Jabber
Interrupt
1 = Jabber occurred
0 = Jabber did not occur RO/SC 0
1B.6
Receive
Error
Interrupt
1 = Receive error occurred
0 = Receive error did not occur RO/SC 0
1B.5
Page
Receive
Interrupt
1 = Page receive occurred
0 = Page receive did not occur RO/SC 0
1B.4
Parallel
Detect Fault
Interrupt
1 = Parallel detect fault occurred
0 = Parallel detect fault did not occur RO/SC 0
1B.3
Link Partner
Acknowl-
edge Inter-
rupt
1 = Link partner acknowledge occurred
0 = Link partner acknowledge did not occur RO/SC 0
1B.2 Link-Down
Interrupt
1 = Link-down occurred
0 = Link-down did not occur RO/SC 0
1B.1 Remote Fault
Interrupt
1 = Remote fault occurred
0 = Remote fault did not occur RO/SC 0
1B.0 Link-Up
Interrupt
1 = Link-up occurred
0 = Link-up did not occur RO/SC 0
Register 1Dh – LinkMD Control/Status
1D.15
Cable Diag-
nostic Test
Enable
1 = Enable cable diagnostic test. After test has
completed, this bit is self-cleared.
0 = Indicates cable diagnostic test (if enabled) has
completed and the status information is valid for
read.
RW/SC 0
TABLE 4-4: VENDOR SPECIFIC REGISTER DESCRIPTIONS (CONTINUED)
Address Name Description Mode
Note 4-1 Default
KSZ8091RNA/RND
DS00002298A-page 38 2016 Microchip Technology Inc.
1D.14:13
Cable Diag-
nostic Test
Result
[00] = Normal condition
[01] = Open condition has been detected in cable
[10] = Short condition has been detected in cable
[11] = Cable diagnostic test has failed
RO 00
1D.12 Short Cable
Indicator
1 = Short cable (<10 meter) has been detected by
LinkMD RO 0
1D.11:9 Reserved Reserved RW 000
1D.8:0 Cable Fault
Counter Distance to fault RO 0_0000_0000
Register 1Eh – PHY Control 1
1E.15:10 Reserved Reserved RO 0000_00
1E.9
Enable
Pause (Flow
Control)
1 = Flow control capable
0 = No flow control capability RO 0
1E.8 Link Status 1 = Link is up
0 = Link is down RO 0
1E.7 Polarity
Status
1 = Polarity is reversed
0 = Polarity is not reversed RO —
1E.6 Reserved Reserved RO 0
1E.5 MDI/MDI-X
State
1 = MDI-X
0 = MDI RO —
1E.4 Energy
Detect
1 = Signal present on receive differential pair
0 = No signal detected on receive differential pair RO 0
1E.3 PHY Isolate 1 = PHY in isolate mode
0 = PHY in normal operation RW 0
1E.2:0
Operation
Mode
Indication
[000] = Still in auto-negotiation
[001] = 10BASE-T half-duplex
[010] = 100BASE-TX half-duplex
[011] = Reserved
[100] = Reserved
[101] = 10BASE-T full-duplex
[110] = 100BASE-TX full-duplex
[111] = Reserved
RO 000
Register 1Fh – PHY Control 2
1F.15 HP_MDIX 1 = HP Auto MDI/MDI-X mode
0 = Microchip Auto MDI/MDI-X mode RW 1
1F.14 MDI/MDI-X
Select
When Auto MDI/MDI-X is disabled,
1 = MDI-X mode
Transmit on RXP, RXM (Pins 5, 4) and
Receive on TXP, TXM (Pins 7, 6)
0 = MDI mode
Transmit on TXP, TXM (Pins 7, 6) and
Receive on RXP, RXM (Pins 5, 4)
RW 0
1F.13 Pair Swap
Disable
1 = Disable Auto MDI/MDI-X
0 = Enable Auto MDI/MDI-X RW 0
1F.12 Reserved Reserved RW 0
1F.11 Force Link
1 = Force link pass
0 = Normal link operation
This bit bypasses the control logic and allows the
transmitter to send a pattern even if there is no link.
RW 0
TABLE 4-4: VENDOR SPECIFIC REGISTER DESCRIPTIONS (CONTINUED)
Address Name Description Mode
Note 4-1 Default
2016 Microchip Technology Inc. DS00002298A-page 39
KSZ8091RNA/RND
Note 4-1 RW = Read/Write; RO = Read Only; SC = Self-Cleared.
4.3 MMD Registers
MMD registers provide indirect read/write access to up to 32 MMD Device Addresses with each device supporting up
to 65,536 16-bit registers, as defined in Clause 22 of the IEEE 802.3 Specification. The KSZ8091RNA/RND, however,
uses only a small fraction of the available registers. See the MMD Register Descriptions section for a list of supported
MMD device addresses and their associated register addresses.
The following two standard registers serve as the portal registers to access the indirect MMD registers.
Standard register Dh – MMD Access – Control
Standard register Eh – MMD Access – Register/Data
1F.10 Power
Saving
1 = Enable power saving
0 = Disable power saving RW 0
1F.9 Interrupt
Level
1 = Interrupt pin active high
0 = Interrupt pin active low RW 0
1F.8 Enable
Jabber
1 = Enable jabber counter
0 = Disable jabber counter RW 1
1F.7
RMII Refer-
ence Clock
Select
1 = For KSZ8091RNA, clock input to XI (Pin 8) is
50 MHz for RMII – 50 MHz Clock Mode.
For KSZ8091RND, clock input to XI (Pin 8) is
25 MHz for RMII – 25 MHz Clock Mode.
0 = For KSZ8091RNA, clock input to XI (Pin 8) is
25 MHz for RMII – 25 MHz Clock Mode.
For KSZ8091RND, clock input to XI (Pin 8) is
50 MHz for RMII – 50 MHz Clock Mode.
RW 0
1F.6 Reserved Reserved RW 0
1F.5:4 LED Mode
[00] = LED0: Link/Activity
[01] = LED0: Link
[10], [11] = Reserved
RW 00
1F.3 Disable
Transmitter
1 = Disable transmitter
0 = Enable transmitter RW 0
1F.2 Remote
Loopback
1 = Remote (analog) loopback is enabled
0 = Normal mode RW 0
1F.1 Reserved Reserved RW 0
1F.0 Disable Data
Scrambling
1 = Disable scrambler
0 = Enable scrambler RW 0
TABLE 4-5: PORTAL REGISTERS (ACCESS TO INDIRECT MMD REGISTERS)
Address Name Description Mode Default
Register Dh - MMD Access - Control
D.15:14
MMD –
Operation
Mode
For the selected MMD device address (bits [4:0] of
this register), these two bits select one of the fol-
lowing register or data operations and the usage
for MMD Access – Register/Data (Reg. Eh).
00 = Register
01 = Data, no post increment
10 = Data, post increment on reads and writes
11 = Data, post increment on writes only
RW 00
D.13:5 Reserved Reserved RW 00_0000_000
TABLE 4-4: VENDOR SPECIFIC REGISTER DESCRIPTIONS (CONTINUED)
Address Name Description Mode
Note 4-1 Default
KSZ8091RNA/RND
DS00002298A-page 40 2016 Microchip Technology Inc.
Examples:
MMD Register Write
Write MMD – Device Address 1Fh, Register 0h = 0001h to enable link-up detection to trigger PME for WOL.
1. Write Register Dh with 001Fh // Set up register address for MMD – Device Address 1Fh.
2. Write Register Eh with 0000h // Select register 0h of MMD – Device Address 1Fh.
3. Write Register Dh with 401Fh // Select register data for MMD – Device Address 1Fh, Register 0h.
4. Write Register Eh with 0001h // Write value 0001h to MMD – Device Address 1Fh, Register 0h.
MMD Register Read
Read MMD – Device Address 1Fh, Register 19h – 1Bh for the magic packet’s MAC address
1. Write Register Dh with 001Fh // Set up register address for MMD – Device Address 1Fh.
2. Write Register Eh with 0019h // Select Register 19h of MMD – Device Address 1Fh.
3. Write Register Dh with 801Fh // Select register data for MMD – Device Address 1Fh, Register 19h
// with post increments
4. Read Register Eh // Read data in MMD – Device Address 1Fh, Register 19h.
5. Read Register Eh // Read data in MMD – Device Address 1Fh, Register 1Ah.
6. Read Register Eh // Read data in MMD – Device Address 1Fh, Register 1Bh.
D.4:0
MMD –
Device
Address
These five bits set the MMD device address. RW 0_0000
Register Eh - MMD Access - Register/Data
E.15:0
MMD –
Register/
Data
For the selected MMD device address (Reg. Dh,
bits [4:0]),
When Reg. Dh, bits [15:14] = 00, this register con-
tains the read/write register address for the MMD
device address.
Otherwise, this register contains the read/write
data value for the MMD device address and its
selected register address.
See also Reg. Dh, bits [15:14], for descriptions of
post increment reads and writes of this register for
data operation.
RW 0000_0000_0000_
0000
TABLE 4-6: MMD REGISTER DESCRIPTIONS
Address Name Description Mode Default
MMD Address 1h, Register 0h – PMA/PMD Control 1
1.0.15:13 Reserved Reserved RW 000
1.0.12 LPI enable Lower Power Idle enable RW 0
1.0.11:0 Reserved Reserved RW 0000_0000_0000
MMD Address 1h, Register 1h – PMA/PMD Status 1
1.1.15:9 Reserved Reserved RO 0000_000
1.1.8 LPI State
Entered
1 = PMA/PMD has entered LPI state
0 = PMA/PMD has not entered LPI state RO/LH 0
1.1.7:4 Reserved Reserved RO 0000
1.1.3 LPI State
Indication
1 = PMA/PMD is currently in LPI state
0 = PMA/PMD is currently not in LPI state RO 0
1.1.2:0 Reserved Reserved RO 000
TABLE 4-5: PORTAL REGISTERS (ACCESS TO INDIRECT MMD REGISTERS) (CONTINUED)
Address Name Description Mode Default
2016 Microchip Technology Inc. DS00002298A-page 41
KSZ8091RNA/RND
MMD Address 7h, Register 3Ch – EEE Advertisement
7.3C.15:3 Reserved Reserved RO 0000_0000_0000_0
7.3C.2 1000BASE-T
EEE Capable 0 = 1000 Mbps EEE is not supported RO 0
7.3C.1 100BASE-TX
EEE Capable
1 = 100 Mbps EEE capable
0 = No 100 Mbps EEE capability
This bit is set to ‘0’ as the default after power-up or
reset. Set this bit to ‘1’ to enable 100 Mbps EEE
mode.
RW 0
7.3C.0 Reserved Reserved RO 0
MMD Address 7h, Register 3Dh – EEE Link Partner Advertisement
7.3D.15:3 Reserved Reserved RO 0000_0000_0000_0
7.3D.2 1000BASE-T
EEE Capable
1 = 1000 Mbps EEE capable
0 = No 1000 Mbps EEE capability RO 0
7.3D.1 100BASE-TX
EEE Capable
1 = 100 Mbps EEE capable
0 = No 100 Mbps EEE capability RO 0
7.3D.0 Reserved Reserved RO 0
MMD Address 1Ch, Register 4h – DSP 10BASE-T/10BASE-Te Control
1C.4.15 Reserved Reserved RW 0
1C.4.14 Reserved Reserved RO 0
1C.4.13
DSP
10BASE-T/
10BASE-Te
Mode Select
1 = Standard 10BASE-T (2.5V TX amplitude) and
also set Standard R0BASEegister 13h, Bit [4] to ‘0’.
0 = EEE 10BASE-Te (1.75V TX amplitude) and
also set Standard Register 13h, Bit [4] to ‘1’.
RW 1
1C.4.12 Reserved Reserved RW 0
1C.4.11:0 Reserved Reserved RO 0000_0000_0000
MMD Address 1Fh, Register 0h – Wake-On-LAN – Control
1F.0.15:14 PME Output
Select
These two bits work in conjunction with Reg. 16h,
Bit [15] for PME enable to define the output for Pins
18 and 23.
INTRP/PME_N2 (Pin 18)
00 = INTRP output
01 = PME_N2 output
10 = INTRP and PME_N2 output
11 = Reserved
LED0/PME_N1 (Pin 23)
00 = PME_N1 output
01 = LED0 output
10 = LED0 output
11 = PME_N1 output
RW 00
1F.0.13:7 Reserved Reserved RO 00_0000_0
1F.0.6
Magic Packet
Detect
Enable
1 = Enable magic-packet detection
0 = Disable magic-packet detection RW 0
1F.0.5
Custom-
Packet Type
3 Detect
Enable
1 = Enable custom-packet, Type 3 detection
0 = Disable custom-packet, Type 3 detection RW 0
TABLE 4-6: MMD REGISTER DESCRIPTIONS (CONTINUED)
Address Name Description Mode Default
KSZ8091RNA/RND
DS00002298A-page 42 2016 Microchip Technology Inc.
1F.0.4
Custom-
Packet Type
2 Detect
Enable
1 = Enable custom-packet, Type 2 detection
0 = Disable custom-packet, Type 2 detection RW 0
1F.0.3
Custom-
Packet Type
1 Detect
Enable
1 = Enable custom-packet, Type 1 detection
0 = Disable custom-packet, Type 1 detection RW 0
1F.0.2
Custom-
Packet Type
0 Detect
Enable
1 = Enable custom-packet, Type 0 detection
0 = Disable custom-packet, Type 0 detection RW 0
1F.0.1
Link-Down
Detect
Enable
1 = Enable link-down detection
0 = Disable link-down detection RW 0
1F.0.0
Link-Up
Detect
Enable
1 = Enable link-up detection
0 = Disable link-up detection RW 0
MMD Address 1Fh, Register 1h – Wake-On-LAN – Customized Packet, Type 0, Mask 0
MMD Address 1Fh, Register 7h – Wake-On-LAN – Customized Packet, Type 1, Mask 0
MMD Address 1Fh, Register Dh – Wake-On-LAN – Customized Packet, Type 2, Mask 0
MMD Address 1Fh, Register 13h – Wake-On-LAN – Customized Packet, Type 3, Mask 0
1F.1.15:0
1F.7.15:0
1F.D.15:0
1F.13.15:0
Custom
Packet Type
X Mask 0
This register selects the bytes in the first 16 bytes
of the packet (bytes 1 thru 16) that will be used for
CRC calculation.
For each bit in this register,
1 = Byte is selected for CRC calculation
0 = Byte is not selected for CRC calculation
The register-bit to packet-byte mapping is as fol-
lows:
Bit [15]: byte-16
... : ...
Bit [1]: byte-2
Bit [0]: byte-1
RW 0000_0000_0000_
0000
MMD Address 1Fh, Register 2h – Wake-On-LAN – Customized Packet, Type 0, Mask 1
MMD Address 1Fh, Register 8h – Wake-On-LAN – Customized Packet, Type 1, Mask 1
MMD Address 1Fh, Register Eh – Wake-On-LAN – Customized Packet, Type 2, Mask 1
MMD Address 1Fh, Register 14h – Wake-On-LAN – Customized Packet, Type 3, Mask 1
1F.2.15:0
1F.8.15:0
1F.E.15:0
1F.14.15:0
Custom
Packet Type
X Mask 1
This register selects the bytes in the second 16
bytes of the packet (bytes 17 thru 32) that will be
used for CRC calculation.
For each bit in this register,
1 = Byte is selected for CRC calculation
0 = Byte is not selected for CRC calculation
The register-bit to packet-byte mapping is as fol-
lows:
Bit [15]: byte-32
... : ...
Bit [1]: byte-18
Bit [0]: byte-17
RW 0000_0000_0000_
0000
TABLE 4-6: MMD REGISTER DESCRIPTIONS (CONTINUED)
Address Name Description Mode Default
2016 Microchip Technology Inc. DS00002298A-page 43
KSZ8091RNA/RND
MMD Address 1Fh, Register 3h – Wake-On-LAN – Customized Packet, Type 0, Mask 2
MMD Address 1Fh, Register 9h – Wake-On-LAN – Customized Packet, Type 1, Mask 2
MMD Address 1Fh, Register Fh – Wake-On-LAN – Customized Packet, Type 2, Mask 2
MMD Address 1Fh, Register 15h – Wake-On-LAN – Customized Packet, Type 3, Mask 2
1F.3.15:0
1F.9.15:0
1F.F.15:0
1F.15.15:0
Custom
Packet Type
X Mask 2
This register selects the bytes in the third 16 bytes
of the packet (bytes 33 thru 48) that will be used for
CRC calculation.
For each bit in this register,
1 = Byte is selected for CRC calculation
0 = Byte is not selected for CRC calculation
The register-bit to packet-byte mapping is as fol-
lows:
Bit [15]: byte-48
... : ...
Bit [1]: byte-34
Bit [0]: byte-33
RW 0000_0000_0000_
0000
MMD Address 1Fh, Register 4h – Wake-On-LAN – Customized Packet, Type 0, Mask 3
MMD Address 1Fh, Register Ah – Wake-On-LAN – Customized Packet, Type 1, Mask 3
MMD Address 1Fh, Register 10h – Wake-On-LAN – Customized Packet, Type 2, Mask 3
MMD Address 1Fh, Register 16h – Wake-On-LAN – Customized Packet, Type 3, Mask 3
1F.4.15:0
1F.A.15:0
1F.10.15:0
1F.16.15:0
Custom
Packet Type
X Mask 3
This register selects the bytes in the fourth 16 bytes
of the packet (bytes 49 thru 64) that will be used for
CRC calculation.
For each bit in this register,
1 = Byte is selected for CRC calculation
0 = Byte is not selected for CRC calculation
The register-bit to packet-byte mapping is as fol-
lows:
Bit [15]: byte-64
... : ...
Bit [1]: byte-50
Bit [0]: byte-49
RW 0000_0000_0000_
0000
MMD Address 1Fh, Register 5h – Wake-On-LAN – Customized Packet, Type 0, Expected CRC 0
MMD Address 1Fh, Register Bh – Wake-On-LAN – Customized Packet, Type 1, Expected CRC 0
MMD Address 1Fh, Register 11h – Wake-On-LAN – Customized Packet, Type 2, Expected CRC 0
MMD Address 1Fh, Register 17h – Wake-On-LAN – Customized Packet, Type 3, Expected CRC 0
1F.5.15:0
1F.B.15:0
1F.11.15:0
1F.17.15:0
Custom
Packet Type
X CRC 0
This register stores the lower two bytes for the
expected CRC.
Bit [15:8] = Byte 2 (CRC [15:8])
Bit [7:0] = Byte 1 (CRC [7:0])
The upper two bytes for the expected CRC are
stored in the following register.
RW 0000_0000_0000_
0000
MMD Address 1Fh, Register 6h – Wake-On-LAN – Customized Packet, Type 0, Expected CRC 1
MMD Address 1Fh, Register Ch – Wake-On-LAN – Customized Packet, Type 1, Expected CRC 1
MMD Address 1Fh, Register 12h – Wake-On-LAN – Customized Packet, Type 2, Expected CRC 1
MMD Address 1Fh, Register 18h – Wake-On-LAN – Customized Packet, Type 3, Expected CRC 1
1F.6.15:0
1F.C.15:0
1F.12.15:0
1F.18.15:0
Custom
Packet Type
X CRC 1
This register stores the upper two bytes for the
expected CRC.
Bit [15:8] = Byte 4 (CRC [31:24])
Bit [7:0] = Byte 3 (CRC [23:16])
The lower two bytes for the expected CRC are
stored in the previous register.
RW 0000_0000_0000_
0000
TABLE 4-6: MMD REGISTER DESCRIPTIONS (CONTINUED)
Address Name Description Mode Default
KSZ8091RNA/RND
DS00002298A-page 44 2016 Microchip Technology Inc.
Note 4-1 RW = Read/Write; RO = Read Only; LH = Latch High.
MMD Address 1Fh, Register 19h – Wake-On-LAN – Magic Packet, MAC-DA-0
1F.19.15:0 Magic Packet
MAC-DA-0
This register stores the lower two bytes of the des-
tination MAC address for the magic packet.
Bit [15:8] = Byte 2 (MAC Address [15:8])
Bit [7:0] = Byte 1 (MAC Address [7:0])
The upper four bytes of the destination MAC
address are stored in the following two registers.
RW 0000_0000_0000_
0000
MMD Address 1Fh, Register 1Ah – Wake-On-LAN – Magic Packet, MAC-DA-1
1F.1A.15:0 Magic Packet
MAC-DA-1
This register stores the middle two bytes of the
destination MAC address for the magic packet.
Bit [15:8] = Byte 4 (MAC Address [31:24])
Bit [7:0] = Byte 3 (MAC Address [23:16])
The lower two bytes and upper two bytes of the
destination MAC address are stored in the previous
and following registers, respectively.
RW 0000_0000_0000_
0000
MMD Address 1Fh, Register 1Bh – Wake-On-LAN – Magic Packet, MAC-DA-2
1F.1B.15:0 Magic Packet
MAC-DA-2
This register stores the upper two bytes of the des-
tination MAC address for the magic packet.
Bit [15:8] = Byte 6 (MAC Address [47:40])
Bit [7:0] = Byte 5 (MAC Address [39:32])
The lower four bytes of the destination MAC
address are stored in the previous two registers.
RW 0000_0000_0000_
0000
TABLE 4-6: MMD REGISTER DESCRIPTIONS (CONTINUED)
Address Name Description Mode Default
2016 Microchip Technology Inc. DS00002298A-page 45
KSZ8091RNA/RND
5.0 OPERATIONAL CHARACTERISTICS
5.1 Absolute Maximum Ratings*
Supply Voltage (VIN)
(VDD_1.2).................................................................................................................................................... –0.5V to +1.8V
(VDDIO, VDDA_3.3) ...................................................................................................................................... –0.5V to +5.0V
Input Voltage (all inputs)............................................................................................................................ –0.5V to +5.0V
Output Voltage (all outputs)....................................................................................................................... –0.5V to +5.0V
Lead Temperature (soldering, 10s) ....................................................................................................................... +260°C
Storage Temperature (TS) ...................................................................................................................... –55°C to +150°C
*Exceeding the absolute maximum rating may damage the device. Stresses greater than the absolute maximum rating
may cause permanent damage to the device. Operation of the device at these or any other conditions above those spec-
ified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect
reliability.
5.2 Operating Ratings**
Supply Voltage
(VDDIO_3.3, VDDA_3.3) ........................................................................................................................ +3.135V to +3.465V
(VDDIO_2.5) ........................................................................................................................................ +2.375V to +2.625V
(VDDIO_1.8) ........................................................................................................................................ +1.710V to +1.890V
Ambient Temperature
(TA Commercial)........................................................................................................................................... 0°C to +70°C
(TA Industrial) ........................................................................................................................................... –40°C to +85°C
Maximum Junction Temperature (TJ max.) ........................................................................................................... +125°C
Thermal Resistance (JA)..............................................................................................................................+49.22°C/W
Thermal Resistance (JC) .............................................................................................................................+25.65°C/W
**The device is not guaranteed to function outside its operating ratings.
Note: Do not drive input signals without power supplied to the device.
‘Dm 33V ‘002 33V
KSZ8091RNA/RND
DS00002298A-page 46 2016 Microchip Technology Inc.
6.0 ELECTRICAL CHARACTERISTICS
TA = 25°C. Specification is for packaged product only.
TABLE 6-1: ELECTRICAL CHARACTERISTICS
Parameters Symbol Min. Typ. Max. Units Note
Supply Current (VDDIO, VDDA_3.3 = 3.3V), Note 6-1
10BASE-T IDD1_3.3V 41 mA Full-duplex traffic @ 100% utilization
100BASE-TX IDD2_3.3V 47 mA Full-duplex traffic @ 100% utilization
EEE (100 Mbps) Mode IDD3_3.3V —23—mA
TX and RX paths in LPI state with no
traffic
EDPD Mode IDD4_3.3V —20—mA Ethernet cable disconnected
(Reg. 18h.11 = 0)
Power-Down Mode IDD5_3.3V —4—mA Software power-down
(Reg. 0h.11 = 1)
CMOS Level Inputs
Input High Voltage VIH
2.0 — V VDDIO = 3.3V
1.8 — V VDDIO = 2.5V
1.3 — V VDDIO = 1.8V
Input Low Voltage VIL
——0.8V V
DDIO = 3.3V
——0.7V V
DDIO = 2.5V
——0.5V V
DDIO = 1.8V
Input Current |IIN|—10µA V
IN = GND ~ VDDIO
CMOS Level Outputs
Output High Voltage VOH
2.4 — V VDDIO = 3.3V
2.0 — V VDDIO = 2.5V
1.5 — V VDDIO = 1.8V
Output Low Voltage VOL
——0.4V V
DDIO = 3.3V
——0.4V V
DDIO = 2.5V
——0.3V V
DDIO = 1.8V
Output Tri-State Leakage |IOZ|—10µA —
LED Output
Output Drive Current ILED 8 mA LED0 pin
All Pull-Up/Pull-Down Pins (including Strap-In Pins)
Internal Pull-Up Resistance pu
30 45 73 kVDDIO = 3.3V
39 61 102 kVDDIO = 2.5V
48 99 178 kVDDIO = 1.8V
Internal Pull-Down
Resistance pd
26 43 79 kVDDIO = 3.3V
34 59 113 kVDDIO = 2.5V
53 99 200 kVDDIO = 1.8V
100BASE-TX Transmit (measured differentially after 1:1 transformer)
Peak Differential Output
Voltage VO0.95 — 1.05 V 100 termination across differential
output
Output Voltage Imbalance VIMB —— 2 %
100 termination across differential
output
Rise/Fall Time tr/tf3—5ns —
Rise/Fall Time Imbalance 0 0.5 ns
Duty Cycle Distortion ±0.25 ns
Overshoot — — 5 %
2016 Microchip Technology Inc. DS00002298A-page 47
KSZ8091RNA/RND
Note 6-1 Current consumption is for the single 3.3V supply KSZ8091RNA/RND device only, and includes the
transmit driver current and the 1.2V supply voltage (VDD_1.2) that are supplied by the KSZ8091RNA/
RND.
Output Jitter 0.7 ns Peak-to-peak
10BASE-T Transmit (measured differentially after 1:1 transformer)
Peak Differential Output
Voltage VP2.2 2.8 V 100 termination across differential
output
Jitter Added 3.5 ns Peak-to-peak
Rise/Fall Time tr/tf—25—ns —
10BASE-T Receive
Squelch Threshold VSQ 400 mV 5 MHz square wave
Transmitter - Drive Setting
Reference Voltage of ISET VSET —0.65— V R(I
SET) = 6.49 k
REF_CLK Output
50 MHz RMII Clock Output
Jitter ——300ps
Peak-to-peak
(Applies only to RMII - 25 MHz Clock
Mode)
100 Mbps Mode - Industrial Applications Parameters
Link Loss Reaction
(Indication) Time tllr —4.4— µs
Link loss detected at receive differen-
tial inputs to PHY signal indication
time for each of the following:
1. For LED mode 01, Link LED output
changes from low (link-up) to high
(link-down).
3. INTRP pin asserts for link-down
status change.
TABLE 6-1: ELECTRICAL CHARACTERISTICS (CONTINUED)
Parameters Symbol Min. Typ. Max. Units Note
KSZ8091RNA/RND
DS00002298A-page 48 2016 Microchip Technology Inc.
7.0 TIMING DIAGRAMS
7.1 RMII Timing
FIGURE 7-1: RMII TIMING – DATA RECEIVED FROM RMII
FIGURE 7-2: RMII TIMING – DATA INPUT TO RMII
TABLE 7-1: RMII TIMING PARAMETERS – KSZ8091RNA/RND (25 MHZ INPUT TO XI PIN, 50 MHZ
OUTPUT FROM REF_CLK PIN)
Parameter Description Min. Typ. Max. Units
tCYC Clock Cycle 20 ns
t1Setup Time 4 ns
2WH Hold Time 2 ns
tOD Output Delay 7 10 13 ns
TABLE 7-2: RMII TIMING PARAMETERS – KSZ8091RNA/RND (50 MHZ INPUT TO XI PIN)
Parameter Description Min. Typ. Max. Units
tCYC Clock Cycle 20 ns
t1Setup Time 4 ns
2WH Hold Time 2 ns
tOD Output Delay 8 11 13 ns
tCYC
REF_CLK
TXEN
TXD[1:0]
t1
t2
TRANSMIT TIMING
tCYC
REF_CLK
CRS_DV
RXD[1:0]
RXER
tOD
RECEIVE TIMING
||||||||||||| |||||||||||| D EU ‘BTE ‘FLPW lPw lCTD lcm
2016 Microchip Technology Inc. DS00002298A-page 49
KSZ8091RNA/RND
7.2 Auto-Negotiation Timing
FIGURE 7-3: AUTO-NEGOTIATION FAST LINK PULSE (FLP) TIMING
TABLE 7-3: AUTO-NEGOTIATION FAST LINK PULSE TIMING PARAMETERS
Parameter Description Min. Typ. Max. Units
tBTB FLP burst to FLP burst 8 16 24 ms
tFLPW FLP burst width 2 ms
tPW Clock/Data pulse width 100 ns
tCTD Clock pulse to data pulse 55.5 64 69.5 µs
tCTC Clock pulse to clock pulse 111 128 139 µs
Number of clock/data pulses per FLP burst 17 33
t
PW
t
PW
t
FLPW
TX+/TX-
TX+/TX-
FLP
BURST
FLP
BURST
t
BTB
t
CTD
t
CTC
CLOCK
PULSE
CLOCK
PULSE
DATA
PULSE
DATA
PULSE
1mm 1mm 1mm
KSZ8091RNA/RND
DS00002298A-page 50 2016 Microchip Technology Inc.
7.3 MDC/MDIO Timing
FIGURE 7-4: MDC/MDIO TIMING
TABLE 7-4: MDC/MDIO TIMING PARAMETERS
Parameter Description Min. Typ. Max. Units
fcMDC Clock Frequency 2.5 10 MHz
tPMDC period 400 ns
tMD1 MDIO (PHY input) setup to rising edge of MDC 10 ns
tMD2 MDIO (PHY input) hold from rising edge of MDC 4 ns
tMD3 MDIO (PHY output) delay from rising edge of MDC 5 222 ns
VALID
DATA
MDIO
(PHY INPUT)
VALID
DATA
MDC
MDIO
(PHY OUTPUT)
VALID
DATA
t
MD1
t
MD2
t
P
t
MD3
++|~fi ‘VR Dmo VDDA 33 'cs 'cH 1Re The supply voILage (V and V 3) powerrup waveform should be mono‘onic. The 300 us mxmmum rise fime \s
2016 Microchip Technology Inc. DS00002298A-page 51
KSZ8091RNA/RND
7.4 Power-Up/Reset Timing
The KSZ8091RNA/RND reset timing requirement is summarized in Figure 7-5 and Table 7-5.
The supply voltage (VDDIO and VDDA_3.3) power-up waveform should be monotonic. The 300 µs minimum rise time is
from 10% to 90%.
For warm reset, the reset (RST#) pin should be asserted low for a minimum of 500 µs. The strap-in pin values are read
and updated at the de-assertion of reset.
After the de-assertion of reset, wait a minimum of 100 µs before starting programming on the MIIM (MDC/MDIO) inter-
face.
FIGURE 7-5: POWER-UP/RESET TIMING
TABLE 7-5: POWER-UP/RESET TIMING PARAMETERS
Parameter Description Min. Typ. Max. Units
tVR Supply voltage (VDDIO, VDDA_3.3) rise time 300 µs
tSR Stable supply voltage (VDDIO, VDDA_3.3) to reset
high
10 — ms
tCS Configuration setup time 5 ns
tCH Configuration hold time 5 ns
tRC Reset to strap-in pin output 6 ns
t
CS
t
CH
t
VR
t
SR
STRAP-IN/
OUTPUT PIN
STRAP-IN
VALUE
RST#
SUPPLY
VOLTAGES
t
RC
KSZ8091RNA/RND
DS00002298A-page 52 2016 Microchip Technology Inc.
8.0 RESET CIRCUIT
Figure 8-1 shows a reset circuit recommended for powering up the KSZ8091RNA/RND if reset is triggered by the power
supply.
FIGURE 8-1: RECOMMENDED RESET CIRCUIT
Figure 8-2 shows a reset circuit recommended for applications where reset is driven by another device (for example,
the CPU or an FPGA). The reset out RST_OUT_n from CPU/FPGA provides the warm reset after power up reset. D2
is used if using different VDDIO between the switch and CPU/FPGA, otherwise, the different VDDIO will fight each other.
If different VDDIO have to use in a special case, a low VF (<0.3V) diode is required (for example, Vishay’s BAT54,
MSS1P2L and so on), or a level shifter device can be used too. If Ethernet device and CPU/FPGA use same VDDIO
voltage, D2 can be removed to connect both devices directly. Usually, Ethernet device and CPU/FPGA should use same
VDDIO voltage.
FIGURE 8-2: RECOMMENDED RESET CIRCUIT FOR CPU/FPGA RESET OUTPUT
VDDIO
D1: 1N4148
D1 R 10kΩ
KSZ8091RNA/RND
RST#
C 10μF
VDDIO
KSZ8091RNA/RND D1 R 10kΩ
RST#
C 10μF
D2
CPU/FPGA
RST_OUT_N
D1, D2: 1N4148
Jag kg;
2016 Microchip Technology Inc. DS00002298A-page 53
KSZ8091RNA/RND
9.0 REFERENCE CIRCUITS — LED STRAP-IN PINS
The pull-up, float, and pull-down reference circuits for the LED1/SPEED and LED0/PME_N1/NWAYEN strap-in pins are
shown in Figure 9-1 for 3.3V and 2.5V VDDIO.
FIGURE 9-1: REFERENCE CIRCUITS FOR LED STRAPPING PINS
For 1.8V VDDIO, LED indication support is not recommended due to the low voltage. Without the LED indicator, the
ANEN_SPEED strap-in pin is functional with a 4.7 k pull-up to 1.8V VDDIO or float for a value of ‘1’, and with a 1.0 k
pull-down to ground for a value of ‘0’.
If using RJ45 jacks with integrated LEDs and 1.8V VDDIO, a level shifting is required from LED 3.3V to 1.8V. For example,
use a bipolar transistor or a level shift device.
LED PIN
220Ω
4.7kΩ
PULL_UP
KSZ8091RNA/RND
VDDIO = 3.3V, 2.5V
LED PIN
220Ω
FLOAT
KSZ8091RNA/RND
VDDIO = 3.3V, 2.5V
LED PIN
220Ω
PULL-DOWN
KSZ8091RNA/RND
VDDIO = 3.3V, 2.5V
1kΩ
:I I—T—I: 160 ppm for ovenemperamre crystal. |:||:
KSZ8091RNA/RND
DS00002298A-page 54 2016 Microchip Technology Inc.
10.0 REFERENCE CLOCK - CONNECTION AND SELECTION
A crystal or external clock source, such as an oscillator, is used to provide the reference clock for the KSZ8091RNA/
RND. For the KSZ8091RNA/RND in all operating modes and for the KSZ8091RND in RMII - 25 MHz Clock Mode, the
reference clock is 25 MHz. The reference clock connections to XI (Pin 8) and XO (Pin 7), and the reference clock selec-
tion criteria, are provided in Figure 10-1 and Table 10-1.
FIGURE 10-1: 25 MHZ CRYSTAL/OSCILLATOR REFERENCE CLOCK CONNECTION
Note 10-1 ±60 ppm for overtemperature crystal.
For the KSZ8091RNA/RND in RMII - 50 MHz Clock Mode, the reference clock is 50 MHz. The reference clock connec-
tions to XI (Pin 8), and the reference clock selection criteria are provided in Figure 10-2 and Table 10-2.
TABLE 10-1: 25 MHZ CRYSTAL/REFERENCE CLOCK SELECTION CRITERIA
Characteristics Value
Frequency 25 MHz
Frequency Tolerance (max.); Note 10-1 ±50 ppm
Crystal Series Resistance (typ.) 40
Crystal Load Capacitance (typ.) 16 pF
FIGURE 10-2: 50 MHZ OSCILLATOR REFERENCE CLOCK CONNECTION
TABLE 10-2: 50 MHZ OSCILLATOR/REFERENCE CLOCK SELECTION CRITERIA
Characteristics Value
Frequency 50 MHz
Frequency Tolerance (max.) ±50 ppm
NC
XI
XO
25MHz OSC
±50ppm
XI
XO
25MHz XTAL
±50ppm
22pF
22pF
NC
XI
XO
50MHz OSC
±50PPM
2016 Microchip Technology Inc. DS00002298A-page 55
KSZ8091RNA/RND
11.0 MAGNETIC - CONNECTION AND SELECTION
A 1:1 isolation transformer is required at the line interface. Use one with integrated common-mode chokes for designs
exceeding FCC requirements.
The KSZ8091RNA/RND design incorporates voltage-mode transmit drivers and on-chip terminations.
With the voltage-mode implementation, the transmit drivers supply the common-mode voltages to the two differential
pairs. Therefore, the two transformer center tap pins on the KSZ8091RNA/RND side should not be connected to any
power supply source on the board; instead, the center tap pins should be separated from one another and connected
through separate 0.1 µF common-mode capacitors to ground. Separation is required because the common-mode volt-
age is different between transmitting and receiving differential pairs.
Figure 11-1 shows the typical magnetic interface circuit for the KSZ8091RNA/RND.
FIGURE 11-1: TYPICAL MAGNETIC INTERFACE CIRCUIT
Table 11-1 lists recommended magnetic characteristics.
TABLE 11-1: MAGNETICS SELECTION CRITERIA
Parameter Value Test Conditions
Turns Ratio 1 CT : 1 CT
Open-Circuit Inductance (min.) 350 µH 100 mV, 100 kHz, 8 mA
Insertion Loss (max.) –1.1 dB 100 kHz to 100 MHz
HIPOT (min.) 1500 VRMS
1
2
3
7
8
4
5
6
4 x 75Ω
1000pF/2kV
RJ-45 CONNECTOR
CHASSIS GROUND
(2 x 0.1μF)
TXP
TXM
RXP
RXM
KSZ8091RNA/RND
SIGNAL GROUND
KSZ8091RNA/RND
DS00002298A-page 56 2016 Microchip Technology Inc.
Table 11-2 is a list of compatible single-port magnetics with separated transformer center tap pins on the PHY chip side
that can be used with the KSZ8091RNA/RND.
TABLE 11-2: COMPATIBLE SINGLE-PORT 10/100 MAGNETICS
Manufacturer Part Number Temperature Range Magnetic + RJ-45
Bel Fuse S558-5999-U7 0°C to 70°C No
Bel Fuse SI-46001-F 0°C to 70°C Yes
Bel Fuse SI-50170-F 0°C to 70°C Yes
Delta LF8505 0°C to 70°C No
HALO HFJ11-2450E 0°C to 70°C Yes
HALO TG110-E055N5 –40°C to 85°C No
LANKom LF-H41S-1 0°C to 70°C No
Pulse H1102 0°C to 70°C No
Pulse H1260 0°C to 70°C No
Pulse HX1188 –40°C to 85°C No
Pulse J00-0014 0°C to 70°C Yes
Pulse JX0011D21NL –40°C to 85°C Yes
TDK TLA-6T718A 0°C to 70°C Yes
Transpower HB726 0°C to 70°C No
Wurth/Midcom 000-7090-37R-LF1 –40°C to 85°C No
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2016 Microchip Technology Inc. DS00002298A-page 57
KSZ8091RNA/RND
12.0 PACKAGE OUTLINE
FIGURE 12-1: 24-LEAD QFN 4 MM X 4 MM PACKAGE
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging.
KSZ8091RNA/RND
DS00002298A-page 58 2016 Microchip Technology Inc.
APPENDIX A: DATA SHEET REVISION HISTORY
TABLE A-1: REVISION HISTORY
Revision Section/Figure/Entry Correction
DS00002298A (11-03-16)
Converted Micrel data sheet KSZ8091RNA/RND to
Microchip DS00002298A. Minor text changes
throughout.
Title Updated title to “10BASE-T/100BASE-TX PHY with
RMII and EEE Support”.
Section 2-1, Table 2-2,
Strap-In Options -
KSZ8091RNA/RND
Table updated to reflect original document.
Product Identification Sys-
tem, Page 60.
Change Special Attributes values from 25 MHz
input to 25 MHz input/50 MHz output for
KSZ8091RNAxx parts.
2016 Microchip Technology Inc. DS00002298A-page 59
KSZ8091RNA/RND
THE MICROCHIP WEB SITE
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files and information easily available to customers. Accessible by using your favorite Internet browser, the web site con-
tains the following information:
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Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive
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To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notifi-
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CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels:
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales
offices are also available to help customers. A listing of sales offices and locations is included in the back of this docu-
ment.
Technical support is available through the web site at: http://microchip.com/support
PART NO. X T 41x 41x
KSZ8091RNA/RND
DS00002298A-page 60 2016 Microchip Technology Inc.
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device: KSZ8091
Interface: R = RMII
Package: N = 24-pin QFN
Special Attribute: A = 25 MHz In/50 MHz Out Clock Mode
D = 50 MHz In/50 MHz Out Clock Mode
Temperature: CA = 0C to +70C (Commercial)
IA = –40C to +85C (Industrial)
Media Type: Blank = Tube
TR = Tape & Reel
Examples:
a) KSZ8091RNACA
RMII Interface
24-pin QFN
25 MHz/50 MHz Input
Tube
Commercial Temperature
b) KSZ8091RNAIA
RMII Interface
24-pin QFN
25 MHz/50 MHz Input
Tube
Industrial Temperature
c) KSZ8091RNDCA
RMII Interface
24-pin QFN
50 MHz Input
Tube
Commercial Temperature
d) KSZ8091RNDIA
RMII Interface
24-pin QFN
50_MHz Input
Tube
Industrial Temperature
e) KSZ8091RNDCA-TR
RMII Interface
24-pin QFN
50 MHz Input
Commercial Temperature
Tape & Reel
f) KSZ8091RNDIA-TR
RMII Interface
24-pin QFN
PART NO. X X
PackageInterface
Device
XX
Temperature
X
Special
Attribute
XX
Media
Type
YSTEM
2016 Microchip Technology Inc. DS00002298A-page 61
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be
superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO
REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR
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The Microchip name and logo, the Microchip logo, AnyRate, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo,
Kleer, LANCheck, LINK MD, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC,
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Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial
Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless
DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their respective companies.
© 2016, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-1062-1
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
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Microchip received ISO/TS-16949:2009 certification for its worldwide
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QUALITYMANAGEMENTS
YSTEM
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== ISO/TS16949==
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DS00002298A-page 62 2016 Microchip Technology Inc.
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Fax: 63-2-634-9069
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Taiwan - Kaohsiung
Tel: 886-7-213-7828
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
EUROPE
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Dusseldorf
Tel: 49-2129-3766400
Germany - Karlsruhe
Tel: 49-721-625370
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Italy - Venice
Tel: 39-049-7625286
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Poland - Warsaw
Tel: 48-22-3325737
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Worldwide Sales and Service
06/23/16

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