CYRF9935 Datasheet by Cypress Semiconductor Corp

View All Related Products | Download PDF Datasheet
39me >5: L8 cmccoEEoom: “oz A 'i
CYRF9935
WirelessUSB™ NX 2.4 GHz
Low Power Radio
Cypress Semiconductor Corporation 198 Champion Court San Jose,CA 95134-1709 408-943-2600
Document Number: 001-88748 Rev. *G Revised May 9, 2017
WirelessUSB™ NX 2.4 GHz Low Power Radio
Key Features
RF channel – 126 (2400 MHz~2525 MHz)
Programmable Data Rate – 2 Mbps/250 Kbps
Power Supply Range – 1.9 V to 3.6 V
Ultra low power operation
TX Current 12 mA at 0 dBm output power
RX Current 15 mA at 2 Mbps data rate
RX Current 14 mA at 250 Kbps data rate
Idle current 26 µA (Idle-I mode)
Sleep current 900 nA
Programmable TX Output Power:
+4 dBm
0 dBm
–8 dBm
–14 dBm
–20 dBm
Sensitivity (0.1%BER):
–93 dBm at 250 kbps
–82 dBm at 2 Mbps
Digital RSSI
Programmable Payload length – 1 to 32 bytes
Programmable Multi-Level FIFO
3 Levels of 32 bytes each
6 Levels of 16 bytes each
Automatic Packet Acknowledgement
Automatic Packet Resend
8/16 bit hardware CRC
Up to 8 Pipes for 1:8 Star Network
4-pin Hardware SPI Interface
±60 ppm 16 MHz crystal
Compact 24-pin 4 × 4 mm QFN package
Applications
Wireless mouse, keyboard, gamepad and presenter
Wireless audio and VoRF
Remote controller
Home automation
Wireless sensor network
Radio Controlled (R/C) Toy
Block Diagram
SCK
SPI_nSS
SPI
Baseband
MISO
MOSI
IRQ
MODE
Register
Map
TX FIFO
RX FIFO
Baseband
Engine
(Framer)
GFSK
Modulator
GFSK
Demodulator
X
X
Transmitter
Receiver
Power
Management
Frequency
Synthesizer
VDD_LDO
VDD_PA
GND
VIN
XIN
XOUT
ANT1
ANT2
PA
LNA
Not recommended for new designs
CYPRESS smmm m munnow A E 29me 30: L8 vmvcmEEoomL “oz
CYRF9935
Document Number: 001-88748 Rev. *G Page 2 of 47
Contents
General Description .........................................................3
Pin Configuration ............................................................. 3
Pin Descriptions ...............................................................4
Functional Overview ........................................................ 5
Power on Reset ........................................................... 5
External Reset .............................................................5
Interrupt .......................................................................5
RF Pins ........................................................................ 5
RF Channel .................................................................5
Transmit Power control ...............................................6
RSSI Operation ........................................................... 7
Power Management ..........................................................8
Idle-I Mode ..................................................................9
Sleep Mode ................................................................. 9
Transmit Mode ..........................................................10
Receive Mode ........................................................... 10
Idle II Mode ................................................................ 10
Baseband Engine ...........................................................10
Packet Format ........................................................... 10
Preamble ................................................................... 10
Address .....................................................................11
Packet Control Word ................................................. 13
Broadcast Address ....................................................13
Auto-Retransmit Mode ..............................................14
Data Packet Loss ......................................................17
ACK Packet Loss ......................................................18
FIFO Control .................................................................... 19
Overview ...................................................................19
TX FIFO Access ........................................................ 19
RX FIFO Access ........................................................ 21
SPI Command ................................................................. 21
SPI Timing .................................................................21
Command List ........................................................... 22
SPI Status in Command Phase ................................. 23
SPI Command for Register Read and Write ............. 23
SPI Command for RX FIFO Access .......................... 23
SPI Command for TX FIFO Access .......................... 24
Register Sets ................................................................... 26
Indirect Registers ...................................................... 31
Application Circuit .......................................................... 33
Absolute Maximum Ratings .......................................... 35
Operating Range ............................................................. 35
Electrical Specifications ................................................ 35
Power Consumption .................................................. 35
General RF Conditions .............................................. 36
Transmitter Operation ............................................... 36
Receiver Operation ................................................... 37
Crystal Specification .................................................. 37
DC Characteristics .................................................... 38
Power-On Reset ........................................................ 38
Ordering Information ...................................................... 39
Ordering Code Definitions ......................................... 39
Packaging Information ................................................... 40
Acronyms ........................................................................ 41
Document Conventions ................................................. 41
Units of Measure ....................................................... 41
Document History Page ................................................. 42
Sales, Solutions, and Legal Information ...................... 47
Worldwide Sales and Design Support ....................... 47
Products .................................................................... 47
PSoC® Solutions ...................................................... 47
Cypress Developer Community ................................. 47
Technical Support ..................................................... 47
Not recommended for new designs
A 3158.39 V J '1 u unnnaw €9on >>oc Lou— UovcoEEooE Hoz
CYRF9935
Document Number: 001-88748 Rev. *G Page 3 of 47
General Description
CYRF9935 is a low power radio transceiver operating in the
world wide 2.4–2.5 GHz ISM band. The transceiver contains fully
integrated receiver, transmitter, frequency synthesizer and
baseband engine. Internal voltage regulators ensure good
immunity to power supply noise and wide power supply voltage
range.
CYRF9935 offers a high data rate of 2 Mbps. It enables burst
transmission to reduce the average power consumption. In
addition, the built-in automatic acknowledgement, automatic
re-send and low power consumption in Idle-I mode, are very
useful features for low power wireless applications.
Pin Configuration
Figure 1. 24-pin QFN Pinout (Top View)
QFN
(Top View)
MISO
Test2
VDD_LDO
GND
1
2
3
4
5
6
18
17
16
15
14
13
GND
GND
24
23
22
21
20
19
SCK
MOSI
MODE
SPI_nSS
VIN
7
8
9
10
11
12
VIN
GND
GND
RST_n
Test1
XOUT
VDD_PA
VIN
ANT1
ANT2
GND
IRQ
XIN
Not recommended for new designs
{EMPRESS ' mmnznmmumw Not recommended for new designs
CYRF9935
Document Number: 001-88748 Rev. *G Page 4 of 47
Pin Descriptions
Pin Name Function Description
1 MISO Digital Output SPI data output [1]
2RST_n
[2] Digital Input Chip reset pin. Active low.
3 Test1 -- Reserved for factory test. Do not connect.
4 Test2 -- Reserved for factory test. Do not connect.
5 VDD_LDO Power Output Internal digital supply output (1.8 V) for de-coupling purpose only and cannot be
loaded.
6GND Power Ground
7VIN
[3] Power Input Power supply (+1.9 VDC ~ +3.6 VDC)
8 XOUT Analog Output Crystal pin 2
9 XIN Analog Input Crystal pin 1
10 GND Power Ground
11 GND Power Ground
12 VIN [3] Power Input Power supply (+1.9 VDC ~ +3.6 VDC)
13 VDD_PA Analog Output Power supply output (+1.8 Vdc) for the internal Power Amplifier, for de-coupling
purpose only and cannot be loaded.
14 ANT1 RF Antenna interface pin 1
15 ANT2 RF Antenna interface pin 2
16 GND Power Ground
17 GND Power Ground
18 VIN [3] Power Input Power supply (+1.9 VDC ~ +3.6 VDC)
19 GND Power Ground
20 SPI_nSS Digital Input SPI chip select. Active low.
21 MODE Digital Input Chip enable activates RX mode. Active high.
22 MOSI Digital Input SPI data input
23 SCK Digital Input SPI clock input
24 IRQ Digital Output Interrupt pin. Active low (default). Can be programmed to active high by
setting internal register (address: 0x02).
Not recommended for new designs
unlknw Elfififiss' A 9‘ 29me 26: L8 cmvcmEEooE 62
CYRF9935
Document Number: 001-88748 Rev. *G Page 5 of 47
Functional Overview
Power on Reset
Power on reset is initiated when the voltage on VIN reaches
1.9 V. It takes 50 ms for the power on reset event to complete.
After power on reset the radio registers will have default values
(refer to Register Sets on page 26) and the radio will be in Idle-I
mode. In this mode the radio consumes 26 µA current.
External Reset
CYRF9935 can also be reset anytime by driving the RST_n pin
low for a period greater than 5 µs. The reset signal should be
followed by a period of inactivity on the SPI or any other input to
the radio for about 1.5 milliseconds. This is required for the
crystal oscillator to start-up.
External reset is an atomic command (it cannot be interrupted)
and will interrupt any other activity on the chip.
Interrupt
In CYRF9935 the interrupt is provided through the IRQ pin. The
interrupt can be configured as active low or active high, by
clearing or setting bit 7 of direct register 0x02 respectively. Upon
reset, it is configured as active low.
There are six interrupt sources in CYRF9935. These interrupts
can be enabled or disabled by configuring bits 5:0 of direct
register 0x02 (refer to Register Sets on page 26). Table 1
describes the different interrupts that are available.
If an interrupt is enabled the IRQ pin reflects the state of the
corresponding interrupt source in the register 0x01 (refer to
Register Sets on page 26). The IRQ pin remains asserted till the
interrupt is cleared. To clear an interrupt set the corresponding
bit in status register.
RF Pins
The CYRF9935 has two RF pins, ANT1 and ANT2, which are
used for differential RF input/output. For optimum performance,
an LC network (called a matching network) matches WUSB-NX
to a conventional 50-ohm antenna.
The traces to ANT1 and ANT2 pins are RF traces and should be
short and direct.
The LC values of the matching network should not be modified
from those shown in the Application Circuit on page 33. In
addition to matching, they provide attenuation of undesired
transmit harmonics. These components should have good
high-frequency characteristics, signified by Q factor within the
manufacturer datasheets.
On the other side of the matching network is an antenna with
50 Ohm impedance. This trace also should be short, if possible.
However, in many cases, the antenna needs to be placed in a
more optimum position on the PCB, so some additional trace
length may be necessary. In such cases, the characteristic
impedance of trace should also be 50 Ohm.
There should be a solid ground plane on the underside of the
matching network. The solid ground plane should extend all the
way to the ground pad vias (at the center of the device) on one
side and should extend to the 50 Ohm transmission line that
connects to the antenna on the other side.
RF Channel
The RF channel frequency determines the center of the channel
used. The channel occupies a bandwidth of less than 1 MHz at
250 kbps and a bandwidth of less than 2 MHz at 2 Mbps.
CYRF9935 can operate on frequencies from 2.400 GHz to 2.525
GHz. The programming resolution of the RF channel frequency
setting is 1MHz.
At 2 Mbps the channel occupies a bandwidth wider than the
resolution of the RF channel frequency setting. To ensure
non-overlapping channels in 2 Mbps mode, the channel spacing
must be 2 MHz or more. At 250 kbps the occupied channel
bandwidth is the same or lower than the resolution of the RF
channel frequency setting.
Table 1. Interrupt Sources
Interrupt source Description Bit in Register 0x02 for enabling or
disabling interrupt
Bit in Register 0x01 (Status) that
reflects the state of interrupt
RX_DR RX data ready 5 5
TX_DS TX data sent 4 4
TX_MAX_ARSC Maximum retry reached 3 3
TX_FIFO Change in TX FIFO state to
the state selected by the
TX_FIFO_STA_SEL bits in
register 0x28
2 1
RX_FIFO RX FIFO not empty 1 0
RSSI RSSI refresh done 0 2
Matching network Antenna
50 Ohm line
ANT1
ANT2
CYRF9935
Not recommended for new designs
mm A 9‘ mcgmmv >>mc L2 UmvcmEEooE Hoz E
CYRF9935
Document Number: 001-88748 Rev. *G Page 6 of 47
The RF channel frequency is set by the register 0x00 according
to the following formula:
Frequency = 2400 + Channel [MHz]
The transmitter and the receiver must be programmed with the
same RF channel frequency to communicate with each other.
Transmit Power control
CYRF9935 supports 5 transmit power levels, which are +4 dBm,
0 dBm, –8 dBm, –14 dBm and –20 dBm.The +4 dBm power
output is set using the indirect register 0x04 bit 7 (see Indirect
Registers on page 31 for instructions on using the indirect
registers). The other four power levels can be set using the bits
4:3 of direct register 0x03.
The table below summarizes the power levels available.
Table 2. RF channel frequency
Channel Number (Decimal) Frequency
02400 MHz
12401 MHz
22402 MHz
32403 MHz
42404 MHz
52405 MHz
……. …….
125 2525 MHz
Table 2. RF channel frequency (continued)
Channel Number (Decimal) Frequency
Table 3. Registers Table for Channel Setting
Address (Hex) Name Bits Init RW Description
0x00 Channel 6:0 0101000 R/W RF Channel Number
Table 4. For 4 dbm setting
Indirect Register
Address (Hex) Mnemonic Bit Reset Value Type Description
0x04 PA4DBM 7 0 R/W Enable PA 4 dBm output power.
1: PA output power 4dBm
0: PA output power depends on RF_PWR setting
in direct register 0x03.
Reserved 6:0 0010001 ROnly ‘0010001’ allowed
Table 5. For Other power settings
Address (Hex) Mnemonic Bit Reset Value Type Description
0x03 RF_PWR 3:2 00 R/W RF output power
00: –20 dBm
01: –14 dBm
10: –8 dBm
11: 0 dBm
Not recommended for new designs
unlknw Elfififiss' A 9‘ 29me 26: L8 cmvcmEEooE 62
CYRF9935
Document Number: 001-88748 Rev. *G Page 7 of 47
RSSI Operation
CYRF9935 supports two types of RSSI measurements namely,
RSSI Refresh and Packet RSSI.
RSSI Refresh is used to implement “Channel Assessment”. This
means RSSI Refresh can be used to assess whether a channel
is clean or not. It is useful to search a clean channel for
Frequency Hopping Spread Spectrum implementations. RSSI
Refresh requires the user to specify the RF channel for RSSI
measurement in the Channel field of register 0x00 prior to RSSI
measurements. RSSI Refresh is enabled by setting
AUTO_RSSI_EN or RSSI_REFRESH bit fields of register 0x20.
When AUTO_RSSI_EN is set, CYRF9935 evaluates RSSI
continuously until AUTO_RSSI_EN is cleared. With
RSSI_REFRESH enabled, CYRF9935 evaluates RSSI only
once, after which RSSI_REFRESH will be cleared automatically.
During RSSI evaluation, the RSSI result is updated onto the
RSSI_VAL_MSB and RSSI_VAL_LSB bit fields of register 0x20.
The RSSI value format is shown as below:
For example, when you start a RSSI refresh and get the value “0110_0101” from the register 0x20. The real RSSI value is “01011”.
Packet RSSI can be used to estimate the distance between TXer and RXer. CYRF9935 evaluates RSSI after the address field in
packet being received is matched. We can use R_RX_PAYLOAD command to get the Packet RSSI if RSSI_AUTO_EN is set.
Table 6. RSSI value format
MSB LSB
Bit 3 Bit 2 Bit 1 Bit 0 Bit 6
Table 7. Registers Table for RSSI Operation
Address (Hex) Mnemonic Bits Init RW Description
0x00 Channel 6:0 0101000 R/W RF channel
0x20 RSSI_VAL_LSB 6 0 R/W RSSI LSB (Bit 0) Value
This value is updated by RSSI Refresh function
AUTO_RSSI_ EN 5 0 R/W AUTO RSSI Enable
0: AUTO RSSI Disable
1: AUTO RSSI Enable
RSSI_REFRESH 4 0 R/W RSSI Refresh
Set to 1 to start RSSI refresh. The bit is auto cleared
when RSSI Refresh is done. RSSI Refresh value will
update in RSSI_VAL_MSB and RSSI_VAL_LSB
RSSI_VAL_MSB 3:0 0R/W RSSI MSB (Bit 4–1) Value
This value is updated by RSSI Refresh function
Not recommended for new designs
A cyPRgss ii u mm 99me >>mc L8 vmvcmEEoomL “oz
CYRF9935
Document Number: 001-88748 Rev. *G Page 8 of 47
Power Management
CYRF9935 has a built in state machine that controls the transition between the various operating states/modes of the radio. The state
machine takes input from the various register settings, MODE pin and internal signals. The state diagram is shown in the figure below
and conditions under which the state transition happens is explained in the table below.
Figure 2. State Diagram
Idle I
(~26 uA)
RX Settling
<=130 uS
TX Settling
<=130 uS
Idle II
(~700 uA)
Receive (RX)
(14~15 mA)
Transmit (TX)
(6~15 mA)
Sleep
(~900nA)
Power off
24
8
5
7
6
9
11
14
15
10
12
13
3
Externally observable
mode
Intermediate
mode
Reset
16
RST_n = 0 from any state
1
Not recommended for new designs
{EMPRESS ' mmnznmmumw Not recommended for new designs
CYRF9935
Document Number: 001-88748 Rev. *G Page 9 of 47
Idle-I Mode
After power up, CYRF9935 is by default in Idle-I Mode. It will
leave the state when the sleep command (Register 0x23 bit 1
i.e. PCEN is set) is received or MCU requests to proceed
transmit or receive. In this state, the radio typically consumes
26 µA of current. This state helps in minimizing average current
consumption without compromising on start up time.
Sleep Mode
On Sleep Mode, CYRF9935 only consumes 900 nA of current.
This mode enables the device to offer ultra-low power
consumption. The chip enters the Sleep Mode when Register
0x23 bit 1 (PCEN) is set. The following points describe the
behavior of the device in Sleep mode:
Register values are maintained
Registers can be accessed over SPI
FIFO content is maintained
FIFO content cannot be accessed
CYRF9935 returns to Idle-I Mode when register 0x23 bit 1
(PCEN) is cleared. At this moment, the micro-controller should
wait until the crystal is stable before further SPI Access. The wait
can be either 1500 µs or 150 µs. Waiting for 1500 µs is
necessary if an external crystal used. If you want to reduce the
wait time to 150 µs, a stable clock source, like an oscillator, is
required.
Table 8. States transfer and conditions
Current Mode Next Mode Path Condition
Power Off Reset 1When going from Power Off to Reset, VIN is ramped from 0 V to 1.9 V, RST_n =1. Idle-I
is reached after a delay of < 50 ms (required for internal POR to be de-asserted) and
<1.5 ms (required for crystal startup)
Reset Idle-I 2When going from Reset to Idle-I mode, RST_n line is released and is internally pulled high.
Sleep Idle-I 3Register 0x23 bit 1 is set to value ‘0’ (Note it takes <1.5 ms for crystal startup before
reaching Idle-I)
Idle-I Sleep 4Register 0x23 bit 1 is set to value ‘1’
Idle-I Transmit 5–6 TX FIFO not empty (by writing to TX FIFO with W_TX_PAYLOAD SPI command) TX
circuitry takes ~130 µs to settle
Transmit Tx Settling 7Transmitting next Data Packet on the same TX channel
While switching between TX channels
Transmit Receive 13–10 After a TX packet is sent with Auto ACK enabled
With Auto ACK disabled, a TX packet is sent and RX request is asserted
Transmit Idle-I 8TX FIFO is empty with Auto ACK disabled
13-10-11 With Auto ACK enabled, after receiving the ACK packet and there is no data in the TX
FIFO.
Idle-I Receive 9–10 Mode pin is asserted or Register 0x00 bit 1 is set to value ‘1’
Receive Transmit 12-6 With Auto ACK enabled, TXer receives an ACK packet and TX FIFO is not empty.
With Auto ACK enabled, TXer doesn’t receive the ACK packet and retransmit is required.
With Auto ACK enabled RXer receives a packet correctly & is going to send ACK packet.
With Auto ACK disabled, RX operation is terminated and TX FIFO not empty.
Receive Idle-I 11 With Auto ACK enabled TXer receives an ACK packet, TX FIFO empty and new receive
is not requested.
With Auto ACK disabled the receiver operation is terminated and TX FIFO is empty.
12-6-8 With Auto ACK enabled, after transmitting the ACK packet, TX FIFO is empty and new
receive is not requested.
Receive Idle-II 14 With Auto ACK enabled, TXer times out without receiving ACK.
Idle-II Idle-I 15 If Register 0x01 bit 3 =1 i.e. TX_MAX_ARSC Flag is cleared
Any mode Reset 16 RST_n is pulled low for more than 5 µs
Note: RST_n line has an internal pull-up resistor which will pulls it high, hence the user does not need to pull RST_n high.
Not recommended for new designs
mm A 9‘ mcgmmv >5: L2 UmvcmEEooE Hoz
CYRF9935
Document Number: 001-88748 Rev. *G Page 10 of 47
Transmit Mode
In Transmit Mode, CYRF9935 typically consumes 12 mA of
current. It quits Idle-I Mode and enters Transmit Mode when
there is data in FIFO waiting for transmit. During the transition to
Transmit Mode, the radio cannot transmit data immediately
because RF Circuit is not stable. The transition period is referred
to as TX settling time. CYRF9935 has a short TX settling time of
130 µs.
Note: When CYRF9935 detects Sleep command (Register 0x23
bit 1 i.e. PCEN is set) on Transmit Mode, it will not enter Sleep
Mode until the data in FIFO is sent out completely.
Receive Mode
In Receive Mode, CYRF9935 typically consumes 15 mA of
current. It quits Idle-I mode and enters Receive Mode when it
captures a command, either MODE pin is asserted or RX_ON
i.e. bit 7 in register 0x01 is set. During the transition to Receive
Mode, the radio cannot receive data immediately because RF
Circuit is not stable. The transition period is referred to as RX
settling time. CYRF9935 has a short RX settling time of 130 µs.
Note: When CYRF9935 detects Sleep command in Receive
Mode, it will not enter Sleep Mode until the current packet receive
finishes or Receive Mode is terminated by de-asserting MODE
pin.
Idle II Mode
After transmitting with automatic acknowledgement (AUTO
ACK) enabled the device goes in to receive mode. If an ACK is
not received after exhausting the maximum number of retries the
radio enters idle-II mode. The device goes to idle I mode on
clearing the TX_MAX_ARSC flag (i.e. setting register 0X01
bit 3 = 1).
Baseband Engine
Packet Format
Preamble
The preamble length can be configured from 4~16 bits by writing appropriate value to indirect register 0x01.
The preamble pattern is dependent upon the MSB of the group address. For example the preamble pattern (16 bit setting) will be
1010101010101010 if the MSB of the group address is 1. Similarly the preamble pattern will be 0101010101010101 for a group
address with MSB 0. Preamble is automatically inserted ahead of the transmitted packet and removed from the received packet by
the baseband engine.
Table 9. Registers Table for Sleep Enable
Address (Hex) Mnemonic Bits Init RW Description
0x23 PCEN 1 0 R/W Power Control Enable,
Set to 1 to enter Sleep mode.
Table 10. Data Packet Format
Preamble Address Control Word Data Payload CRC
4~16 bits 4~6
B
y
tes
10
Bit
s0~32 Bytes 1~2 Bytes
Table 11. Register Table for Preamble
Indirect Register
Address (Hex) Mnemonic Bit Reset Value Type Description
0x01 Reserved 7:2 001000 ROnly ‘001000’ allowed
PAL 1:0 11 R/W Preamble length for TX
00: 4 bits
01: 8 bits
10: 12 bits
11: 16 bits
Table 12. Register Table for CRC Control
Address (Hex) Mnemonic Bits Init RW Description
0x03 CRCEN 1 1 R/W Set to 1 to enable CRC.
CRCLNG 0 1 R/W 0: 1-byte CRC
1: 2-byte CRC
Not recommended for new designs
{EMPRESS ' mznnmmmunnnw Not recommended for new designs
CYRF9935
Document Number: 001-88748 Rev. *G Page 11 of 47
Address
Address field consists of Group Address, Destination Pipe
Address and Source Pipe Address. Table 13 shows the
construction of Address field. The length of Group Address is
programmable from 2 bytes to 4 bytes. Both Destination Pipe
Address and Source Pipe Address are one byte in length.
When a data packet is sent by TXer, Destination Pipe Address
is obtained from ADDR_P1 or ADDR_P2 etc. depending on the
pipe number used in the W_TX_PAYLOAD or
W_ACK_PAYLOAD commands. Source Pipe Address is
obtained from the register ADDR_DEV.
Source pipe address in the ACK packet send by the RXer is just
a copy of the Destination Pipe Address in the received packet
and vice versa.
Figure 3 on page 12 shows how to set addresses to work in 8:1
communication. All of TXers and RXer have the same Group
Address 0xE1, 0xE2, 0xE3 and 0xE4. RXer can receive the
packets coming from TXer1, TXer2…to TXer8. RXer has Device
Pipe Address 0x00. Device Pipe Address in both TXer1 and
TXer8 are configured with 0x01 and 0x08 respectively.
ADDR_P1 on the TXers is set to 0x00 which is the Device Pipe
Address for the RXer. Similarly the ADDR_P1 to ADDR_P8 on
the RXer are set to the Device Pipe Addresses on TXer1 to
TXer8 respectively. For example when TXer1 sends the data
packet to RXer, Destination Pipe Address is 0x00 from
ADDR_P1. TXer1’s Source Pipe Address is 0x01 from
ADDR_DEV. When RXer received the data packet from TXer1,
it returns ACK packet in which the Source Pipe Address is 0x00
and the destination is the same as the received packet’s Source
Pipe Address. The same behaviour is followed when TXer8
wants to send the data packet to RXer.
Note: 0xAA and 0x55 are not valid values for GROUP_ADDR_3.
These patterns are similar to the patterns used for the preamble
and may result in communication failure or high Packet Error
Rate.
Table 13. Address Field Format
Group Address Destination Pipe Address Source Pipe Address
2~4 Bytes 1-Byte 1-Byte
Table 14. Registers Table for Address control
Address (Hex) Mnemonic Bits Init RW Description
0x03 ADDRLNG 6:5 01(B) R/W Group Address length
00: invalid
01: 2 bytes
10: 3 bytes
11: 4 bytes
0x09 GROUP_ADDR_0 7:0 0xE7 R/W Group Address byte 0
0x0A GROUP_ADDR_1 7:0 0xE7 R/W Group Address byte 1
0x0B GROUP_ADDR_2 7:0 0xE7 R/W Group Address byte 2
0x0C GROUP_ADDR_3 7:0 0xE7 R/W Group Address byte 3
0x0D ADDR_DEV 7:0 0xE7 R/W Device PIPE Address
0x0E ADDR_P1 7:0 0x00 R/W PIPE 1 Address
0x0F ADDR_P2 7:0 0x00 R/W PIPE 2 Address
0x10 ADDR_P3 7:0 0x00 R/W PIPE 3 Address
0x11 ADDR_P4 7:0 0x00 R/W PIPE 4 Address
0x12 ADDR_P5 7:0 0x00 R/W PIPE 5 Address
0x13 ADDR_P6 7:0 0x00 R/W PIPE 6 Address
0x14 ADDR_P7 7:0 0x00 R/W PIPE 7 Address
0x15 ADDR_P8 7:0 0x00 R/W PIPE 8 Address
Not recommended for new designs
A E €9me >>mc L8 vmvcmEEoomL “oz
CYRF9935
Document Number: 001-88748 Rev. *G Page 12 of 47
Figure 3. Concept of address field applied to the 8:1 communication
RXer
0
TXer
1
TXer
2
TXer
3
TXer
4
TXer
5
TXer
6
TXer
7
TXer
8
All Rxer and Txers, Group Address is the same.
(0x09, 0x0A, 0xB, 0x0C) = 0xE1, 0xE2, 0xE3, 0xE4
RXer Address Setting
ADDR_DEV(0x0D) = 0x00
ADDR_P1 (0x0E) = 0x01
ADDR_P2 (0x0F) = 0x02
ADDR_P3 (0x10) = 0x03
ADDR_P4 (0x11) = 0x04
ADDR_P5 (0x12) = 0x05
ADDR_P6 (0x13) = 0x06
ADDR_P7 (0x14) = 0x07
ADDR_P8 (0x15) = 0x08
TXer1 Address Setting
ADDR_DEV(0x0D) = 0x01
ADDR_P1 (0x0E) = 0x00
TXer8 Address Setting
ADDR_DEV(0x0D) = 0x08
ADDR_P1 (0x0E) = 0x00
Data Packet Address
[E1, E2, E3, E4, 00, 01]
ACK Packet Address
[E1, E2, E3, E4, 01, 00]
Data Packet Address
[E1, E2, E3, E4, 00, 08]
ACK Packet Address
[E1, E2, E3, E4, 08, 00]
Not recommended for new designs
nlnuw EIERESS A E wcgwoc 26: L8 coccoEEoom: “oz
CYRF9935
Document Number: 001-88748 Rev. *G Page 13 of 47
Packet Control Word
Packet Control Word is a 10 bit field which is automatically attached to the transmitting packet and removed from the received packet
by the radio’s baseband engine.
Payload Length
Payload length is a 6 bit field which is attached if DPL is 1 (refer Register Sets on page 26). It represents the payload length for the
data packet. A value of 000000 means 0 byte data payload is carried while a value of 000001 means 1 bytes data payload are carried
and so on (values in excess of 100000 are not valid).
PID
The PID is a 3-bit value that ranges from 1~7 and is incremented by 1 for every new packet. For every packet received, if the PID is
same as last packet and computed CRC is not same as the previous packet, it is assumed a new packet is received. If both the PID
and CRC for the received packet is same as the previous packet then the current packet is assumed to be a re-transmission of the
previous packet. PID is always 0 for Auto-ACK packet.
NOACK
The NOACK is a 1 bit field which is inserted to the transmitted packet if DPL is enabled (refer Register Sets on page 26). If NOACK
is set to 0 then an ACK packet will be exchanged between the receiver and the transmitter, if an error free payload packet was
transmitted. For an Auto-ACK packet or broadcast packet the NOACK is set to 1.
Data Payload
Length is programmable 0 to 32 bytes.
CRC
CRC is an error detection mechanism provided to validate the data correctness of a received packet. CRC length is programmable
to be either 1 or 2 bytes long. The CRC value is calculated over the packet control word and payload. The CRC is automatically
calculated and appended to the transmitted packet. On the receiver side the CRC is removed from the received packet by the
baseband engine. The received packet will be ignored if CRC mismatch happens. The number of bytes in CRC field is set by CRCLNG
bit in direct register 0x03 (refer to Register Sets on page 26).
The polynomial for 1 byte CRC is X8 + X2 + X + 1, with an initial value of 0xFF.
The polynomial for 2 byte CRC is X16 + X12 + X5 + 1, with an initial value of 0xFFFF.
Broadcast Address
CYRF9935 can transmit and receive broadcast packets. The bit-field BCEN must be set to enable the function for a RXer. To transmit
a broadcast packet, W_TX_PAYLOAD SPI command is used and the TX Pipe Number in the command is set with 0 to indicate this
is a broadcast packet. You can use R_RX_PAYLOAD SPI command to receive the broadcast packet if RX Pipe Number in the
command is set to 0. The broadcast address is 0xE7, 0x39, 0xCE, 0x73, 0x9C depending on the address length (ADDRLNG register)
setting. The address must be reserved for the broadcast use. In a broadcast packet, both Destination Pipe Address and Source Pipe
Address are not attached.
Table 15. Packet Control Word Format
Payload Length PID NOACK
6 bits 3 bits 1 bit
Table 16. Registers Table for Broadcast Enable
Address (Hex) Mnemonic Bits Init RW Description
0x23 BCEN 0 0 R/W Broadcasting Listening Enable
0: Broadcasting packets are ignored.
1: Broadcasting packet can be received.
Not recommended for new designs
{EMPRESS ' Emlznninmmxnnnnw Not recommended for new designs
CYRF9935
Document Number: 001-88748 Rev. *G Page 14 of 47
Auto-Retransmit Mode
CYRF9935 supports Auto-retransmit mode. In this mode, a TXer will re-transmit the packet if it does not receive the ACK packet from
a RXer. Before enabling Auto-retransmit mode, the following registers should be configured appropriately.
Register 0x05 - bit fields in this register are used to enable Auto-Retransmission mode on each pipe for both TXer and RXer.
Register 0x07 bit field AAWD (Auto-ACK Wait Delay) - TXer will wait for ACK packet arrival for an interval after the packet is sent.
AAWD is used to configure the time interval. The interval starts counting at the end of packet transmission. The interval must be
larger than 130 µs + the time required to complete the reception of the ACK packet. If TXer cannot receive ACK packet within the
interval, TXer terminates RX mode immediately.
Register 0x07 bit field RSD (Resend Delay) – Idle time between the end of AAWD and the beginning of retransmit.
Register 0x08 bit field ARSC (Auto Resend Count) – The register is used to configure the maximum number of times to resend the
same packet.
Register 0x08 bit field ARS_CNT (Auto Resend Counting) – The register displays how many times the packet was retransmitted.
In addition to the register setting appropriately, the user should use the correct SPI command to start the Auto-retransmit mode. In
W_TX_PAYLOAD command, bit 7 of the first data byte which is behind the command must be set “0” to command CYRF9935 to send
the packet with Auto-Retransmit mechanism.
Table 17. Registers Table for Broadcast Address
ADDRLNG Broadcast Address Length Broadcast Address
2 Bytes 30xE7, 0x39, 0xCE
3 Bytes 40xE7, 0x39, 0xCE, 0x73
4 Bytes 50xE7, 0x39, 0xCE, 0x73, 0x9C
Table 18. Registers Table for Auto-Retransmission Mode
Address (Hex) Mnemonic Bits Init RW Description
0x05 AA_P8 7 0 R/W Enable Auto-ACK for PIPE 8
AA_P7 6 0 R/W Enable Auto-ACK for PIPE 7
AA_P6 5 0 R/W Enable Auto-ACK for PIPE 6
AA_P5 4 0 R/W Enable Auto-ACK for PIPE 5
AA_P4 3 0 R/W Enable Auto-ACK for PIPE 4
AA_P3 2 0 R/W Enable Auto-ACK for PIPE 3
AA_P2 1 0 R/W Enable Auto-ACK for PIPE 2
AA_P1 0 0 R/W Enable Auto-ACK for PIPE 1
0x07 AAWD 7:4 0000 R/W Auto-ACK Wait Delay
Values in unit of 250 s. (0000 for 250 s)
RSD 3:0 0000 R/W Resend Delay:
1st resend: AAWD + RSD
2nd resend: AAWD + (2 × RSD)
3rd resend: AAWD + (3 × RSD)
4th resend: AAWD + RSD
5th resend: AAWD + (2 × RSD) And so on.
Values in unit of 250 s. (0000 for 0 s)
0x08 ARSC 7:4 0000 R/W Setting the maximum Auto Resend Count
ARS_CNT 3:0 0000 RAuto Resend Count
Not recommended for new designs
A CIEBESS‘ ‘ J '1 nlnnw wcgwoc Em: L8 coccoEEoom: “oz §+
CYRF9935
Document Number: 001-88748 Rev. *G Page 15 of 47
Timing Diagram of Auto-Retransmit Mode
Figure 4. Timing Diagram of typical radio transmit and receive operation
TXer SPI
Idle-I
TXer Mode
W_TX_
PAYLOAD
PLL
Settling TX PLL
Settling RX Idle-I
TXer IRQ
[R Register]
IRQ: TX_DS
Idle-I PLL
Settling RX PLL
Settling TX Idle-IRXer Mode
RXer Mode
RXer SPI [R Register]
IRQ: RX_DR
RXer IRQ
Ttx_pll
Trx_pll
Ttx_oa
Ttx_oa
Trx_irq
Trx_irq
Not recommended for new designs
magma—u 26: L8 UmvcmEEooE 52 nlnuw EXERESS A 2‘
CYRF9935
Document Number: 001-88748 Rev. *G Page 16 of 47
Table 19. Timing Characteristics
Item Description Min Typ Max
Ttx_pll TX PLL Settling Time
PLL turns on because of the assertion of SPI W_TX_PAYLOAD
130 µs
Ttx_oa Transmit Data On Air
It depends on the address length, packet length, data rate, CRC length and
so on. Please refer to the Packet Format on page 10 for details. The below
equation can be used to calculate the time for transmission of a packet.
(Preamble length + Address length + Control Word length + Data Payload
length + CRC length) x (1/Data Rate)
For example, for a packet having 16 bits preamble, 24 bits Address, 10 bits
Control Word, 40 bits Data Payload and 16 bits CRC with 2 Mbps data rate:
Ttx_oa = (16+24+10+40+16)/(1/2M) = 53 µs
– – –
Trx_pll RX PLL Settling Time
PLL turns on when MODE pin is asserted or bit 7 of register 0x00 is set
130 µs
Trx_irq RX IRQ Assertion Time
The delay from the time the packet is received to IRQ assertion.
0 – –
Not recommended for new designs
aCYPRESS‘ ' EulEnnEnluvnunlnuw Data Loss Not recommended for new designs
CYRF9935
Document Number: 001-88748 Rev. *G Page 17 of 47
Data Packet Loss
The figure below shows CYRF9935 behavior if RXer loses the data packet which is sent by TXer. “Data On Air” represents the transmit
sequence on the air including Data Packet and ACK Packet. In the diagram, there are several tags which are used to depict the real
scenario during the data packet loss. These are explained below:
1. Data packet is sent by TXer
2. Data packet is interfered with, hence RXer cannot receive the same
3. RXer doesn’t transmit ACK packet on the air
4. TXer aborts the receive and waits for AAWD and then for RSD
5. TXer resends Data packet
6. RXer receives the data packet correctly
7. RXer sends ACK packet on the air
8. TXer receives ACK packet.
9. TXer IRQ asserted because the packet is sent successfully.
Figure 5. Data Packet Loss Scenario
Table 20. Data Packet Loss
Item Description Min Typ Max
TAAWD Time for ACK packet wait delay. Please refer to Register 0x07. (Note 4) – – –
TRSD Time for resend delay. Please refer to Register 0x07 – – –
TXer SPI
TXer Modes
W_TX_
PAYLOAD
TX RX
RX
TX RX
TX
Data On Air
TX_DS
TXer IRQ
R_RX_PAYLOAD
RX_DR
RXer SPI
RXer IRQ
Data
Packet
Loss
Trx_pll Ttx_pll
TAAWD TRSD
Rxer Modes
Data
Packet Data Packet ACK
Packet
[1] [2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
Not recommended for new designs
A IE 39on >5: L8 vovcoEEoom: “oz
CYRF9935
Document Number: 001-88748 Rev. *G Page 18 of 47
ACK Packet Loss
The diagram below shows CYRF9935 behavior if TXer loses the ACK packet which is sent by RXer. “Data On Air” represents the
transmit sequence on the air including Data Packet and ACK Packet. In the diagram, there are several tags which are used to depict
the scenario during the data packet loss. These are explained below:
1. Data Packet is sent by TXer
2. Data Packet is received correctly by RXer
3. RXer IRQ asserted to indicate that data is ready in FIFO
4. RXer sends ACK packet on the air
5. ACK packet is interfered with
6. TXer aborts the receive and waits for AAWD and then for RSD
7. TXer resends Data Packet
8. RXer doesn’t assert IRQ because the same data packet is received
9. RXer sends ACK packet on the air
10.TXer receives ACK packet
11.TXer IRQ asserted because the packet is sent successfully
Figure 6. ACK Packet Loss Scenario
TXer SPI
TX Modes
W_TX_
PAYLOAD
TX RX
RX
TX RX
TX
RX Modes
TX_DS
TXer IRQ
R_RX_PAYLOAD
RX_DR
RXer SPI
RXer IRQ
TAAWD TRSD
TX RX
IRQ Assertion is inhibited because the
same packet received
Data Packet ACK
Packet
Data On Air Data Packet
[1]
[2]
[3]
[4]
[5]
ACK
Packet
Loss
[6]
[7] [9]
[8]
[10]
[11]
Not recommended for new designs
wcgwoc 26: L8 coccoEEoom: “oz x‘x nlnnw CYPRESS ii A
CYRF9935
Document Number: 001-88748 Rev. *G Page 19 of 47
FIFO Control
Overview
In CYRF9935, there are TX FIFO and RX FIFO to store the transmit data and the receive data respectively. Both TX FIFO and RX FIFO
can be programmed in either 3 blocks or 6 blocks configuration. In case of a 3-block configuration each block can store 32 bytes of
data whereas in case of a 6-block configuration each block can store 16 bytes of data.
TX FIFO Access
We can access TX FIFO with SPI Commands, W_TX_PAYLOAD or W_ACK_PAYLOAD. Figure 7 shows how to use the SPI
commands to transmit data in Data Packet and ACK Packet. When a TXer wants to send Data Packet, W_TX_PAYLOAD is available
to fill the transmit data into TX FIFO. W_ACK_PAYLOAD is available for RXer to fill the transmit data into TX FIFO. The data in TX
FIFO of RXer will be attached to ACK packet.
Figure 7. TX FIFO Access with SPI Commands
Table 21. Registers Table for FIFO Configuration
Address (Hex) Mnemonic Bits Init RW Description
0x1E TX_FIFO_CONFIG 6 0 R/W 0: 3 Blocks, 32-Byte in each block
1: 6 Blocks, 16-Byte in each block
0x1F RX_FIFO_CONFIG 6 0 R/W 0: 3 Blocks, 32-Byte in each block
1: 6 Blocks, 16-Byte in each block
TXer SPI
TX Modes
W_TX_PAYLOAD
TX
RX
RX
RX Modes
W_ACK_PAYLOAD
RXer SPI
TX
Data Packet
Data On Air
Transmit Data is ready
Transmit Data is ready in TX FIFO
ACK
Packet Data Packet
W_TX_PAYLOAD
RX
TXer FIFO
Status
Data Clear
Transmit Data is ready for ACK Packet
RXer FIFO
Status
Data Clear
Not recommended for new designs
29me >5: L8 umucmEEooE goz
CYRF9935
Document Number: 001-88748 Rev. *G Page 20 of 47
Please keep the following in mind when accessing TX FIFO.
In non-Auto-Retransmit Mode, data in TX FIFO will be cleared immediately when the data is sent
For a TXer, data in TX FIFO will be held until ACK is received or re-transmit is terminated if Auto-Retransmit Mode is enabled
For a RXer, data in TX FIFO will be held until a new data packet is received in the same pipe, if auto-ACK with ACK payload is enabled
The current TX FIFO write is aborted if the written data size is more than TX FIFO block size
The current TX FIFO write is also aborted if no free blocks are available to store the data
We can monitor TX FIFO status through the registers
At least, one byte data write is required
Table 22. Registers Table for FIFO Status
Address (Hex) Mnemonic Bits Init RW Description
0x01 TX_FIFO_STATE 1 1 R/W This bit is set when the FIFO state matches the configuration
selected by the TX_FIFO_STA_SEL bits in register 28.
This bit is automatically cleared when the condition is not true
and cannot be cleared by writing into the register.
Refer to Table 23 for TX FIFO State explanation.
0x1F RX_FIFO_NOT_EMPTY 0 0 R/W 1 indicates the RX_FIFO is not empty.
Automatically cleared when RX_FIFO is empty.
0x28 TX_FIFO_STA_SEL 1:0 00 R/W TX FIFO state selection:
00: TX_FIFO_EMPTY.
01: TX_FIFO_FULL.
10: TX_FIFO_NOT_EMPTY.
11: TX_FIFO_NOT_FULL.
Refer to Table 23 for TX FIFO State explanation.
Table 23. TX FIFO State Explanation
TX_FIFO_STA_SEL TX_FIFO_STATE Output Definition
00 TX FIFO Empty Status
0: One of the blocks in TX FIFO has data
1: All blocks in TX FIFO are empty
01 TX FIFO Full Status
0: At least one of the blocks in TX FIFO is empty
1: All blocks in the TX FIFO are full
10 TX FIFO Not Empty Status
0: All blocks are empty
1: At least one block has data
11 TX FIFO Not Full Status
0: All blocks have data.
1: At least one block is empty in TX FIFO
Not recommended for new designs
EulEnnEn m Inuulnnw CYPRESS‘ A V J '1 $9me 26: L8 UmvcmEEoom: “oz T. . x m f ......... H ,- J m Km < 33x;="" \="" x="" “‘="" k="" bmw="" §=""> SS ‘S> $8 ‘3) ‘ m )Im an! xfi 15:. FF) an m M ED {nan = ‘9 IMFFWX -”X~X&)’*X”<>< h="" .cei="">
CYRF9935
Document Number: 001-88748 Rev. *G Page 21 of 47
RX FIFO Access
We can access RX FIFO with SPI command, R_RX_PAYLOAD. We use the SPI command to read data from RX FIFO while IRQ is
asserted and RX_DR status bit is set. In CYRF9935, RXer will not receive the packets when RX FIFO is full.
SPI Command
SPI Timing
In general, a SPI Command consists of a command and data part in that order. The command part is used to represent the purpose
of the SPI command. For example, in Figure 8, C7–C0 is the command part. D0, D1, D2, and so on are defined as the data part.
Figure 8. SPI Read Timing
Figure 9. SPI Write Timing
Figure 10. SPI Timing Requirement
SPI_nSS
SCK
MOSI
MISO
SPI_nSS
SCK
MOSI
MISO
SPI_SS
CLK
MOSI
MISO
TSCKH
TSCKL
TSSS TSSH
TSSU TSHD
TSDO
TSDO1
TSDO2
TSCK
TSS_SU
Not recommended for new designs
{EMPRESS ' mmnznmmumw _{ —<>< 00aaaaaah="" 01aaaaaah="" me,="" 1="" not="" recommended="" for="" new="" designs="">
CYRF9935
Document Number: 001-88748 Rev. *G Page 22 of 47
Command List
Tab le 2 5 shows all of the commands that CYRF9935 supports. Data Command Word defines the data in command part of SPI
command. Command Length defines the length in the data phase.
Table 24. SPI Characteristics
Symbol Description Minimum Maximum Units
Tssu Data setup time 5 ns
T
shd
Data hold time 2 ns
T
sdo
SPI_nSS to data valid 60 ns
T
sckl
SCK low time 40 ns
T
sckh
SCK high time 40 ns
T
sck
SCK frequency 8 MHz
Tr_spi SCK rise and fall time 35 ns
T
sss
SPI_nSS to SCK setup 30 ns
T
ssh
SCK to SPI_nSS hold 20 ns
Tss_hd SPI_nSS inactive time 50 ns
Table 25. Command List
Command name Command Word Data Length Description
R_REGISTER 00AAAAAA [5] 1 byte Read register value.
Refer to Table 27 on page 23.
W_REGISTER 01AAAAAA [5] 1 byte Write register value.
Refer to Table 28 on page 23.
R_RX_PAYLOAD 10000000 3 to 34 bytes Read RX_FIFO content.
Refer to Table 29 on page 23.
W_TX_PAYLOAD 101PDDDD [6, 7] 2 to 33 bytes Write TX_FIFO content.
Refer to Table 31 on page 24.
W_ACK_PAYLOAD 1110PDDD [6, 8] 1 to 32 bytes Write ACK data payload to TX_FIFO.
Refer to Section Table 32 on page 24.
REUSE_TX_PAYLOAD 11010000 1 byte The data in TX FIFO is reused.
Refer to Section Table 33 on page 24.
FLUSH_TX_FIFO 11000101 None Flush TX_FIFO
FLUSH_RX_FIFO 11000100 None FLUSH_RX_FIFO command clears bit 0 (RX_FIFO_NOT_EMPTY) of
register 0x01 and bits 0–5 of register 0x1f. The RX_FIFO contents are
not valid after this command.
NOP 11111111 None No operation
Not recommended for new designs
{EMPRESS ' mmnznmmumw Not recommended for new designs
CYRF9935
Document Number: 001-88748 Rev. *G Page 23 of 47
SPI Status in Command Phase
When a command is issued the radio always outputs the register 0x01 value. This helps the MCU to get the radio status without having
to ask for it specifically. The NOP command can be used to read radio status without performing operation.
SPI Command for Register Read and Write
There are two SPI commands that are used to access the radio register. R_REGISTER is used to read the content of a register.
W_REGISTER is used to write data to any register.
SPI Command for RX FIFO Access
There are two commands, R_RX_PAYLOAD and FLUSH_RX_FIFO to handle RX FIFO access. When CYRF9935 receives a data
packet, the data will be stored into RX FIFO. R_RX_PAYLOAD command is used to read the data from the RX FIFO. FLUSH_RX_FIFO
command clears bit 0 (RX_FIFO_NOT_EMPTY) of register 0x01 and bits 0–5 of register 0x1f. The RX_FIFO contents are not valid
after this command.
Table 26. SPI Command for NOP
Byte Num. Phases B7 B6 B5 B4 B3 B2 B1 B0 Note
Byte 1 Command 11111111 –
Table 27. SPI Command for Register Read
Byte Num. Phases B7 B6 B5 B4 B3 B2 B1 B0 Note
Byte 1 Command 0 0 Register Address
Byte 2 Data Register Content
Table 28. SPI Command for Register Write
Byte Num. Phases B7 B6 B5 B4 B3 B2 B1 B0 Note
Byte 1 Command 0 1 Register Address
Byte 2 Data Register Content
Table 29. SPI Command for R_RX_PAYLOAD
Byte Num. Phases B7 B6 B5 B4 B3 B2 B1 B0 Note
Byte 1 Command 10000000
Byte 2 Data Packet RSSI RX Pipe Number Note 9, 10
Byte 3 Data Reserved Data Length Note 11
Byte 4–35 Data Read Data from RX FIFO
Table 30. SPI Command for FLUSH_RX_FIFO
Byte Num. Phases B7 B6 B5 B4 B3 B2 B1 B0 Note
Byte 1 Command 11000100 –
Not recommended for new designs
{EMPRESS ' zuuznmmmnnnnw Not recommended for new designs
CYRF9935
Document Number: 001-88748 Rev. *G Page 24 of 47
SPI Command for TX FIFO Access
There are four commands, W_TX_PAYLOAD, W_ACK_PAYLOAD, REUSE_TX_PAYLOAD and FLUSH_TX_FIFO to handle TX FIFO
access. TX FIFO Access on page 19 introduces how to use W_TX_PAYLOAD command and W_ACK_PAYLOAD command.
REUSE_TX_PAYLOAD command is useful when CYRF9935 cannot proceed to retransmit the packet because the resend count has
reached the maximum value. We can use this command to reuse data from previous packet. The data which is held in TX FIFO is
sent again. The FLUSH_TX_FIFO command is used to flush/clear the contents of the TX FIFO.
Table 31. SPI Command for W_TX_PAYLOAD
Byte Num. Phases B7 B6 B5 B4 B3 B2 B1 B0 Note
Byte 1 Command 1 0 1 P TX Pipe Number Note 12
Byte 2 Data Note
13
RF Channel (Note 14) Note 13, 14
Byte 3–34 Data Write Data to TX FIFO
Table 32. SPI Command for W_ACK_PAYLOAD
Byte Num. Phases B7 B6 B5 B4 B3 B2 B1 B0 Note
Byte 1 Command 1110PACK Pipe Number Note 15, 16
Byte 2–33 Data Write Data to TX FIFO
Table 33. SPI Command for REUSE_TX_PAYLOAD
Byte Num. Phases B7 B6 B5 B4 B3 B2 B1 B0 Note
Byte 1 Command 11010000
Byte 2 Data Note
13
RF Channel Refer to Table 31 on page 24.
Table 34. SPI Command for FLUSH_TX_FIFO
Byte Num. Phases B7 B6 B5 B4 B3 B2 B1 B0 Note
Byte 1 Command 11000101 –
Not recommended for new designs
A 01.58539 ‘ a '1 unlknw 29me 26: L8 cmvcmEEooE #oZ
CYRF9935
Document Number: 001-88748 Rev. *G Page 25 of 47
*Very Important – Further explanation to Pipe Number Setting for SPI Command *
In R_RX_PAYLOAD and W_TX_PAYLOAD commands, there are 4-bits to represent the pipe number. In both cases, a value 0
indicates broadcast packet transmission. Any values between 1 and 8 for this field will initiate data transfer on the corresponding pipe.
But for, W_ACK_PAYLOAD only 3-bit pipe numbers are applicable and the command does not support the broadcast packet. The
value 0–7 indicates to send the packet to Pipe 1–8. The table below explains the case.
Table 35. Pipe Number Setting
CYRF9935 Pipe Number R_RX_PAYLOAD RX
Pipe Number
W_TX_PAYLOAD TX
Pipe Number
W_ACK_PAYLOAD ACK
Pipe Number
Broadcast Address 0 0 Not Available
1 1 1 0
2 2 2 1
3 3 3 2
4 4 4 3
5 5 5 4
6 6 6 5
7 7 7 6
8 8 8 7
Not recommended for new designs
{EMPRESS ' mznnmmmmnw Not recommended for new designs
CYRF9935
Document Number: 001-88748 Rev. *G Page 26 of 47
Register Sets
Address
(Hex) Mnemonic Bit Reset Value Type Description
0x00 RXON 7 0 R/W Enables and disables RX mode
0: RX operation is controlled by MODE pin state
1: Enter RX mode regardless of MODE pin status
Note: CYRF9935 enters RX mode while either RXON bit is
set or MODE Pin is asserted. The radio transitions from RX
to Idle-I if both RXON is cleared and MODE pin is driven low.
Channel 6:0 0101000 R/W RF channel
This field sets the channel on the RXer while listening for
packets, sending ACK packets and measuring channel
RSSI.
0x01 Reserved 7:6 00 R/W Only ‘00’ allowed
RX_DR 5 0 R/W Received Data Ready
The bit is set when a data packet is received.
Write 1 to Clear
TX_DS 4 0 R/W Transmitter Data Sent Successfully
This bit is set when a data packet is transmitted
successfully.
Write 1 to Clear
TX_MAX_ARSC 3 0 R/W Transmitter Maximum Auto Resend Count
Write 1 to clear this bit.
This bit also gets cleared when using either
REUSE_TX_PAYLOAD or FLUSH_TX_FIFO command.
This bit is set when the packet is retransmitted for the number
of times in the ARSC register. The bit must be cleared to
continue the communication while TX_DT is asserted.
RSSI_REFRESH_DONE 2 0 R/W RSSI Value Refresh
Write 1 to Clear
The bit is set after RSSI update is complete.
TX_FIFO_STATE 1 1 R/W This bit is set when the FIFO state matches the
configuration selected by the TX_FIFO_STA_SEL bits in
register 28.
This bit is automatically cleared when the condition is not
true and cannot be cleared by writing into the register.
Refer to Table 23 on page 20 for TX FIFO State explanation.
RX_FIFO_NOT_EMPTY 0 0 R/W RX FIFO Not Empty
Auto Clear if RX FIFO is empty.
This bit is set when RX_FIFO is not empty.
0x02 IRQ_LVL 7 0 R/W IRQ Pin logic drive level
0: Active Low
1: Active High
Reserved 6 0 R/W Only ‘0’ allowed.
RX_DR_IRQEN 5 1 R/W IRQ Enable for Receive Data Ready
If this bit is set, IRQ Pin is asserted when a packet is
received.
TX_DS_IRQEN 4 1 R/W IRQ Enable for Transmitter Data Send
If this bit is set, IRQ Pin is asserted after a packet is sent.
TX_MAX_ARSC_IRQEN 3 0 R/W IRQ Enable for Transmitter Maximum Resend Count
If this bit is set, IRQ Pin is asserted when the retransmit
count reaches ARSC setting.
Not recommended for new designs
{EMPRESS ' Eulennznmmunmnw Not recommended for new designs
CYRF9935
Document Number: 001-88748 Rev. *G Page 27 of 47
TX_FIFO_IRQEN 2 0 R/W IRQ Enable for TX_FIFO Empty
If this bit is set, IRQ Pin is asserted when the TX_FIFO is
empty.
RX_FIFO_IRQEN 1 0 R/W IRQ Enable for RX_FIFO Empty
If this bit is set, IRQ Pin is asserted when the RX_FIFO is
empty.
RSSI_IRQEN 0 0 R/W IRQ Enable for RSSI Refresh
If this bit is set, IRQ Pin is asserted when RSSI Refresh is
complete.
0x03 Reserved 7 0 R/W Only ‘0’ allowed.
ADDRLNG 6:5 01 R/W Group Address Length
00: Invalid
01: 2 bytes
10: 3 bytes
11: 4 bytes
DR 4 1 R/W Data Rate
0: 250 kbps
1: 2 Mbps
RF_PWR 3:2 00 R/W RF output power
00: –20 dBm
01: –14 dBm
10: –8 dBm
11: 0 dBm
CRCEN 1 1 R/W Enable/Disable CRC
1: Enable CRC
0: Disable CRC
CRCLNG 0 1 R/W 0: 1-byte CRC
1: 2-byte CRC
0x04 EN_P8 7 1 R/W Enable PIPE 8
EN_P7 6 1 R/W Enable PIPE 7
EN_P6 5 1 R/W Enable PIPE 6
EN_P5 4 1 R/W Enable PIPE 5
EN_P4 3 1 R/W Enable PIPE 4
EN_P3 2 1 R/W Enable PIPE 3
EN_P2 1 1 R/W Enable PIPE 2
EN_P1 0 1 R/W Enable PIPE 1
0x05 AA_P8 7 0 R/W Enable Auto-ACK for PIPE 8
AA_P7 6 0 R/W Enable Auto-ACK for PIPE 7
AA_P6 5 0 R/W Enable Auto-ACK for PIPE 6
AA_P5 4 0 R/W Enable Auto-ACK for PIPE 5
AA_P4 3 0 R/W Enable Auto-ACK for PIPE 4
AA_P3 2 0 R/W Enable Auto-ACK for PIPE 3
AA_P2 1 0 R/W Enable Auto-ACK for PIPE 2
AA_P1 0 0 R/W Enable Auto-ACK for PIPE 1
0x06 DP_P8 7 0 R/W Enable Dynamic Payload Length for PIPE 8
DP_P7 6 0 R/W Enable Dynamic Payload Length for PIPE 7
DP_P6 5 0 R/W Enable Dynamic Payload Length for PIPE 6
Register Sets (continued)
Address
(Hex) Mnemonic Bit Reset Value Type Description
Not recommended for new designs
:iCYPRESS' ' Eulennznmmunmnw Not recommended for new designs
CYRF9935
Document Number: 001-88748 Rev. *G Page 28 of 47
DP_P5 4 0 R/W Enable Dynamic Payload Length for PIPE 5
DP_P4 3 0 R/W Enable Dynamic Payload Length for PIPE 4
DP_P3 2 0 R/W Enable Dynamic Payload Length for PIPE 3
DP_P2 1 0 R/W Enable Dynamic Payload Length for PIPE 2
DP_P1 0 0 R/W Enable Dynamic Payload Length for PIPE 1
0x07 AAWD 7:4 0000 R/W Auto-ACK Wait Delay
Increments in unit of 250 s.
(0000 for 1 × 250 µs
0001 for 2 × 250 µs
.
.
.
1111 for 16 × 250 µs)
RSD 3:0 0000 R/W Resend Delay (accumulated over each resend):
1st resend: AAWD + RSD
2nd resend: AAWD + (2 × RSD)
3rd resend: AAWD + (3 × RSD)
4th resend: AAWD + RSD
5th resend: AAWD + (2 × RSD)
And so on.
Values in unit of 250 s. (0000 for 0 s)
0x08 ARSC 7:4 0000 R/W Sets the maximum Auto Resend Count
ARS_CNT 3:0 0000 RAuto Resend Count
0x09 GROUP_ADDR_0 7:0 0xE7 R/W Group Address byte 0
0x0A GROUP_ADDR_1 7:0 0xE7 R/W Group Address byte 1
0x0B GROUP_ADDR_2 7:0 0xE7 R/W Group Address byte 2
0x0C GROUP_ADDR_3 7:0 0xE7 R/W Group Address byte 3
0x0D ADDR_DEV 7:0 0xE7 R/W Device PIPE Address
0x0E ADDR_P1 7:0 0x00 R/W PIPE 1 Address
0x0F ADDR_P2 7:0 0x00 R/W PIPE 2 Address
0x10 ADDR_P3 7:0 0x00 R/W PIPE 3 Address
0x11 ADDR_P4 7:0 0x00 R/W PIPE 4 Address
0x12 ADDR_P5 7:0 0x00 R/W PIPE 5 Address
0x13 ADDR_P6 7:0 0x00 R/W PIPE 6 Address
0x14 ADDR_P7 7:0 0x00 R/W PIPE 7 Address
0x15 ADDR_P8 7:0 0x00 R/W PIPE 8 Address
0x16 Reserved 7:6 00 R/W Only ‘00’ allowed
PKT_LNG_P1 5:0 000000 R/W Packet Length for Pipe 1
This register sets the packet length for Pipe 1 if “Dynamic
Payload Length” function is disabled.
000000: Invalid
000001: 1 bytes
000010: 2 bytes
:
100000: 32 bytes
Others: Invalid
0x17 Reserved 7:6 00 R/W Only ‘00’ allowed
Register Sets (continued)
Address
(Hex) Mnemonic Bit Reset Value Type Description
Not recommended for new designs
{EMPRESS ' zuuznmmmnnnnw Not recommended for new designs
CYRF9935
Document Number: 001-88748 Rev. *G Page 29 of 47
PKT_LNG_P2 5:0 00000 R/W Packet Length for Pipe 2
This register sets the packet length for Pipe 2 if “Dynamic
Payload Length” function is disabled.
000000: Invalid
000001: 1 bytes
000010: 2 bytes
:
100000: 32 bytes
Others: Invalid
0x18 Reserved 7:6 00 R/W Only ’00’ allowed
PKT_LNG_P3 5:0 00000 R/W Packet Length for Pipe 3
This register sets the packet length for Pipe 3 if “Dynamic
Payload Length” function is disabled.
000000: Invalid
000001: 1 bytes
000010: 2 bytes
:
100000: 32 bytes
Others: Invalid
0x19 Reserved 7:6 00 R/W Only ‘00’ allowed
PKT_LNG_P4 5:0 00000 R/W Packet Length for Pipe 4
This register sets the packet length for Pipe 4 if “Dynamic
Payload Length” function is disabled.
000000: Invalid
000001: 1 bytes
000010: 2 bytes
:
100000: 32 bytes
Others: Invalid
0x1A Reserved 7:6 00 R/W Only ‘00’ allowed
PKT_LNG_P5 5:0 00000 R/W Packet Length for Pipe 5
This register sets the packet length for Pipe 5 if “Dynamic
Payload Length” function is disabled.
000000: Invalid
000001: 1 bytes
000010: 2 bytes
:
100000: 32 bytes
Others: Invalid
0x1B Reserved 7:6 00 R/W Only ‘00’ allowed
PKT_LNG_P6 5:0 00000 R/W Packet Length for Pipe 6
This register sets the packet length for Pipe 6 if “Dynamic
Payload Length” function is disabled.
000000: Invalid
000001: 1 bytes
000010: 2 bytes
:
100000: 32 bytes
Others: Invalid
0x1C Reserved 7:6 00 R/W Only ’ 00’ allowed
Register Sets (continued)
Address
(Hex) Mnemonic Bit Reset Value Type Description
Not recommended for new designs
:iCYPRESS' ' Eulennznmmunmnw Not recommended for new designs
CYRF9935
Document Number: 001-88748 Rev. *G Page 30 of 47
PKT_LNG_P7 5:0 00000 R/W Packet Length for Pipe 7
This register sets the packet length for Pipe 7 if “Dynamic
Payload Length” function is disabled.
000000: Invalid
000001: 1 bytes
000010: 2 bytes
:
100000: 32 bytes
Others: Invalid
0x1D Reserved 7:6 00 R/W Only ‘00’ allowed
PKT_LNG_P8 5:0 00000 R/W Packet Length for Pipe 8
This register sets the packet length for Pipe 8 if “Dynamic
Payload Length” function is disabled.
000000: Invalid
000001: 1 bytes
000010: 2 bytes
:
100000: 32 bytes
Others: Invalid
0x1E Reserved 7 0 R/W Only ‘0’ allowed
TX_FIFO_CONFIG 6 0 R/W 0: 3 Blocks, 32-Byte in each block
1: 6 Blocks, 16-Byte in each block
TX_FIFO_0_EMPTY 5 1 R 1: Indicates the TX_FIFO_0 is empty
TX_FIFO_1_EMPTY 4 1 R Indicates the TX_FIFO_1 is empty
TX_FIFO_2_EMPTY 3 1 R Indicates the TX_FIFO_2 is empty
TX_FIFO_3_EMPTY 2 1 R Indicates the TX_FIFO_3 is empty
TX_FIFO_4_EMPTY 1 1 R Indicates the TX_FIFO_4 is empty
TX_FIFO_5_EMPTY 0 1 R Indicates the TX_FIFO_5 is empty
0x1F Reserved 7 0 R/W Only ‘0’ allowed
RX_FIFO_CONFIG 6 0 R/W 0: 3 Blocks, 32-Byte in each block
1: 6 Blocks, 16-Byte in each block
RX_FIFO_0_N_EMPTY 5 0 R 1: Indicates the RX_FIFO_0 is not empty
RX_FIFO_1_ N_EMPTY 4 0 R Indicates the RX_FIFO_1 is not empty
RX_FIFO_2_ N_EMPTY 3 0 R Indicates the RX_FIFO_2 is not empty
RX_FIFO_3_ N_EMPTY 2 0 R Indicates the RX_FIFO_3 is not empty
RX_FIFO_4_ N_EMPTY 1 0 R Indicates the RX_FIFO_4 is not empty
RX_FIFO_5_ N_EMPTY 0 0 R Indicates the RX_FIFO_5 is not empty
0x20 Reserved 7 0 R/W Only ‘0’ allowed
RSSI_VAL_LSB 6 0 R/W RSSI LSB (Bit 0) Value
This bit is updated by RSSI Refresh function
AUTO_RSSI_ EN 5 0 R/W AUTO RSSI Enable
0: AUTO RSSI Disable
1: AUTO RSSI Enable
RSSI_REFRESH 4 0 R/W RSSI Refresh
1: Start RSSI refresh. The bit is automatically cleared when
RSSI Refresh is done. RSSI Refresh updates the following
fields, RSSI_VAL_MSB and RSSI_VAL_LSB
RSSI_VAL_MSB 3:0 0 R/W RSSI MSB (Bit 5-1) Value
This value is updated by RSSI Refresh function
Register Sets (continued)
Address
(Hex) Mnemonic Bit Reset Value Type Description
Not recommended for new designs
{EMPRESS ' Emlznninmmxnnnnw Not recommended for new designs
CYRF9935
Document Number: 001-88748 Rev. *G Page 31 of 47
Indirect Registers
CYRF9935 has a set of registers which can only be accessed
through indirect addressing, hereafter referred to as indirect
registers. These registers are accessed through the direct
registers 0x3E (for addressing) and 0x3F (for reading / writing
values). The below sections describe how to read or write these
registers.
Reading from an Indirect Register
Following steps are used to read from an indirect register.
Issue the address for the indirect register by writing it to the
direct register 0x3E
The contents of the corresponding indirect register can be read
from the direct register 0x3F
Example for reading an indirect register 0x00
write 0x00 to direct register 0x3E
read register 0x3F
Writing to an Indirect Register
Following steps are used to write to an indirect register.
Issue the address for the indirect register by writing it to the
direct register 0x3E
Write the value (to be written to the indirect register) to the direct
register 0x3F
Example for writing an indirect register 0x00 with a value 0x10
write 0x00 to direct register 0x3E
write 0x10 to direct register 0x3F
0x21 Reserved 7:0 00000100 R/W Only ‘00000100’ allowed
0x22 Reserved 7:3 00000 R/W Only ‘00000’ allowed
STATE 2:0 001 RInternal state indication
000: Sleep
001: Idle-I
100: RX (ACK waiting)
101: RX (Normal)
110: RX (Packet receiving)
010: TX (ACK sending)
011: TX (Normal)
111: Invalid
0x23 Reserved 7:2 000000 R/W Only ‘000000’ allowed
PCEN 1 0 R/W Power Control Enable,
Set to 1 to enter Sleep mode.
BCEN 0 0 R/W Broadcast packet Listening Enable
0: Broadcast packets are ignored.
1: Broadcast packet can be received.
0x24~0x27 Reserved 7:0 11000010 R/W Only ‘11000010’ allowed
0x28 Reserved 7:2 000000 R/W Only ‘000000’ allowed
TX_FIFO_STA_SEL 1:0 00 R/W TX FIFO state selection
00: TX_FIFO_EMPTY.
01: TX_FIFO_FULL.
10: TX_FIFO_NOT_EMPTY.
11: TX_FIFO_NOT_FULL.
0x29~0x3B Reserved 7:0 00000000 R/W Only ‘00000000’ allowed
0x3C DRAFT_REG 7:0 00000000 R/W Draft register
0x3D CHIP_ID 7:0 10100001 RChip indication code
0x3E INDIR_ADDR 7:0 00000000 R/W Indirect register: address
0x3F INDIR_DATA 7:0 10101000 R/W Indirect register: data
Register Sets (continued)
Address
(Hex) Mnemonic Bit Reset Value Type Description
Not recommended for new designs
$9me 26: L8 umvcmEEooE 62 unlknw 521.5339 A 9‘
CYRF9935
Document Number: 001-88748 Rev. *G Page 32 of 47
The following table provides a list of indirect registers (with addresses and acceptable values) which can be read / written in WUSB-NX:
Caution: Using addresses and values that are not documented in the table above will lead to CYRF9935 device exhibiting undefined
behaviour.
Table 36. Indirect register sets
Address (Hex) Mnemonic Bit Reset Value Type Description
0x00 DIRECT 7 1 R/W 0: direct mode.
1: burst mode.
CHNNUM 6:0 0101000 RCurrently used RF channel number.
CHNNUM: 0 ~ 125
RF Freq. = 2400+ CHNNUM MHz
0x01 Reserved 7:2 001000 ROnly ‘001000’ allowed
PAL 1:0 11 R/W Preamble length for TX
00: 4 bits
01: 8 bits
10: 12 bits
11: 16 bits
0x04 PA4DBM 7 0 R/W Enable PA 4 dBm output power.
1: PA output power 4 dBm
0: PA output power depends on RF_PWR setting
in direct address 0x03.
Reserved 6:0 0010001 ROnly ‘0010001’ allowed
Not recommended for new designs
€9me >>mc L8 vmvcmEEoomL “oz %
CYRF9935
Document Number: 001-88748 Rev. *G Page 33 of 47
Application Circuit
Figure 11. CYRF9935 schematic for RF layouts with single ended 50 RF output
NOTE1: Mount R1 only if the antenna does
not have a return path to GND.
NOTE2: Do not mount R6
NOTE3: Do not mount R5
NOTE4: Mount either C16 ot C17.
Mount C16 if you want to use PIFA antennae.
Mount C17 if you want to use SMA connector.
Do not mount both C16 and C17
NOTE1
NOTE4
WUSB-NX_IRQ
SPI_CLK
SPI_MOSI
RX_ENABLE
SPI_SS
SPI_MISO
RESET_n
3.3V
3.3V3.3V
1.8V
C18
5 pF
C7
1uF
R2
0
C17
10 pF
C11
2.2nF
C14
36pF
C10
22pF
C15
12pF
R3 1M
C16
10 pF
WUSB-NX
U1
MISO
1
RST_N
2
Test1
3
Test2
4
VDD_LDO
5
GND
6
VIN 18
GND 17
GND 16
ANT2 15
ANT1 14
VDD_PA 13
GND 25
IRQ 24
SCK 23
MOSI 22
MODE 21
SPI_SS 20
GND 19
VIN
7
XOUT
8
XIN
9
GND
10
GND
11
VIN
12
ANT1PIFA
2
1
3
4
R1
20K
J5
SMA_PCB_Edge
Shield2 2
RF_SIG 1
Shield3 3
Shield4 4
Shield5 5
C4
1uF
C9
2.2nF
C1
22pF
C2
2.2nF
L3
3.9nH
Y1
16MHz
L2
5.6nH
C8
22pF
L1 3.9nH
C5
1pF
C6
22pF
NOTE2
RESET_n
3.3V 1.8V 3.3V
TP3
TEST POINT
1
TP2
TEST POINT
1
R6
10k_NL
TP1
TEST POINT
1
NOTE3
SPI_SS
SPI_CLK
SPI_MOSIRX_ENABLE
WUSB-NX_IRQ
SPI_MISO
RESET_n
3.3V
J4 CYRF_XTND_CONN
12
J2
CURRENT SHUNT
1
2
J3
CYRF_LEGACY_CONN
12
34
56
78
910
L4 3.3nH
C12
22pF
C13
1uF
R5
0_NL
Note: MISO pin on the PSoC must be configured in pull-up mode to achieve low current consumption in Idle-I and Sleep
modes. If using any other controller an external pull-up may be required.
Not recommended for new designs
{EMPRESS ' Eulinnznmmunmnw Not recommended for new designs
CYRF9935
Document Number: 001-88748 Rev. *G Page 34 of 47
Table 37. Recommended components (BOM) in CYRF9935 with antenna matching network
Component Description Value Tolerance
ANT1 PIFA_ANTENNA
C1, C6, C8,
C10, C12
Chip capacitor 22 pF 5%
C2, C9, C11 Chip capacitor 2.2 nF 10%
C3 Chip capacitor 5 pF 10%
C4, C7, C13 Chip capacitor 1 uF 20%
C5 Chip capacitor 1 pF 10%
C15 Chip capacitor 12 pF 5%
C14 Chip capacitor 36 pF 5%
C16, C17 Chip capacitor 10 pF 10%
J2 CONN HEADER
J3 CONN HEADER
J4 CONN HEADER
J5 CONN HEADER
L1, L3 Chip inductor 3.9 nH 5%
L2 Chip inductor 5.6 nH 5%
L4 Chip inductor 3.3 nH 5%
R1 Resistor 20 KOhm 1%
R2 Resistor 0 Ohm 1%
R3 Resistor 1 MOhm 1%
R5 Resistor 0 Ohm 1%
R6 Resistor 10 KOhm 1%
TP1, TP2 TEST POINT
TP3 TEST POINT
U1 CYRF9935
Y1 Crystal, CL = 12 pF, ESR < 100 16 MHz, 12 pF
Not recommended for new designs
{EMPRESS ' Eulinnznmmunmnw Not recommended for new designs
CYRF9935
Document Number: 001-88748 Rev. *G Page 35 of 47
Note: Stress exceeding one or more of the limiting values may cause permanent damage to CYRF9935.
Electrical Specifications
Absolute Maximum Ratings
Parameter Description Minimum Maximum
Vin_Max Supply Voltage VIN –0.4 V 3.6 V
GND GND 0 V
Vin_Max Input voltages –0.4 V VIN + 0.4
Vo_Max Output voltage VSS to VIN VSS to VIN
TPD Total Power Dissipation (T
A = 85 °C)–60 mW
TSTG_AMAX Storage temperature range 55 °C 125 °C
Operating Range
Parameter Description Minimum Maximum
Vin Supply Voltage (VIN) 1.9 V 3.6 V
TO Operating temperature range 0 °C 70 °C
Power Consumption
Parameter Description Min Typ Max Units
Idle modes
Idd_slpr Supply current at Sleep Mode [17] –900–nA
Idd_idle1 Supply current at Idle-I Mode 26 A
Idd_idle2 Supply current at Idle-II Mode 800 A
Transmit
Idd_tx0+4 Supply current at TX Mode @ 4 dBm [18] –15–mA
Idd_tx0 Supply current at TX Mode @ 0 dBm [18] –12–mA
Idd_tx6 Supply current at TX Mode @ –8 dBm [18] –8.5–mA
Idd_tx12 Supply current at TX Mode @ –14 dBm [18] –7–mA
Idd_tx18 Supply current at TX Mode @ –20 dBm [18] –6.3–mA
Receive
Idd_rx Supply current (2 Mbps) 15 mA
Idd_rx Supply current (250 kbps) 14 mA
Not recommended for new designs
{EMPRESS ' mznnmmmunnnw Not recommended for new designs
CYRF9935
Document Number: 001-88748 Rev. *G Page 36 of 47
General RF Conditions
Parameter Description Min Typ Max Units Notes
F_op Operating frequency 2400 2525 MHz
Fstep RF channel frequency programming resolution 1MHz
XTAL Crystal frequency 16 MHz
Df2avg Frequency deviation @ 2 Mbps 290 kHz
Df1avg Frequency deviation @ 250 kbps 155 kHz
Ts Air data rate 250 2000 kbps
Transmitter Operation
Parameter Description Min Typ Max Units Notes
Pavh0 Maximum output power 0 +4 dBm Note 19
Pop_acc RF power control accuracy ±4 dB
BW_20dB_2M 20dB bandwidth with modulated carrier (2 Mbps) 1800 2300 kHz
BW_20dB_250K 20dB bandwidth with modulated carrier (250 kbps) 900 1000 kHz
IBS_2 1st adjacent channel transmit power 2 MHz (2 Mbps) –20 dBc
IBS_3 2nd adjacent channel transmit power 4 MHz (2 Mbps) –50 dBc
IBS_2 1st adjacent channel transmit power 1 MHz (250 kbps) –30 dBc
IBS_3 2nd adjacent channel transmit power 2 MHz (250 kbps) –45 dBc
Not recommended for new designs
{EMPRESS ' mmnznmmumw Not recommended for new designs
CYRF9935
Document Number: 001-88748 Rev. *G Page 37 of 47
Receiver Operation
Parameter Description Min Typ Max Units Notes
Rxmax-sig Maximum received signal power at < 0.1% BER 0 dBm
RxSbase Sensitivity (0.1%BER) @ 2 Mbps –82 dBm
RxSbase Sensitivity (0.1%BER) @ 250 kbps –93 dBm
CI_cochannel C/I Co-channel (2 Mbps) 11 dBc Note 20
CI_1 Adjacent channel selectivity C/I 2 MHz (2 Mbps) 4 dBc Note 20
CI_2 Adjacent channel selectivity C/I 4 MHz (2 Mbps) –26 dBc Note 20
CI_3 Adjacent channel selectivity C/I 6 MHz (2 Mbps) –32 dBc Note 20
CI_image C/I image (2 Mbps) –25 dBc Note 20
CI_cochannel C/I Co-channel (250 kbps) 7dBc Note 20
CI_1 Adjacent channel selectivity C/I 1 MHz (250 kbps) 4 dBc Note 20
CI_2 Adjacent channel selectivity C/I 2 MHz (250 kbps) –17 dBc Note 20
CI_3 Adjacent channel selectivity C/I 3 MHz (250 kbps) –35 dBc Note 20
CI_image C/I image (250 kbps) –25 dBc Note 20
Crystal Specification
Parameter Description Min Typ Max Units Notes
XTAL Crystal Frequency 16 MHz
XTAL_PPM To l e r a n c e +/-60 ppm
Co Equivalent parallel capacitance (C0) 1.5 7.0 pF
Ls Equivalent serial inductance (LS) 30 mH Note 21, 22
Cl Load capacitance (CL) 8 12 16 pF
ESR Equivalent Series resistance (ESR) 100 Ohm
Not recommended for new designs
unlknw Elfiflfiss' A 9‘ 29me 26: L8 cmvcmEEooE #oZ
CYRF9935
Document Number: 001-88748 Rev. *G Page 38 of 47
DC Characteristics
Parameter Description Min Typ Max Units Notes
Vih HIGH level input voltage (VIH) 0.7 × VIN VIN V
Vil LOW level input voltage (VIL) VSS 0.3 × VIN V
Voh HIGH level output voltage (VOH) VIN – 0.3 VIN V
Vol LOW level output voltage (VOL)–0.3V
Power-On Reset
Parameter Description Min Typical Max Units Notes
PS_IPEAK Power ramp up time 100 ms Note 23
Trpw Power on reset 50 ms Note 24
Not recommended for new designs
A E wcgwoc Em: L8 coccoEEoom: “oz
CYRF9935
Document Number: 001-88748 Rev. *G Page 39 of 47
Ordering Information
Ordering Code Definitions
Ordering Code Package Temperature Range Comments
CYRF9935-24LQXC 24-pin (4 × 4 × 0.55 mm) Sawn QFN Commercial This part is not recommended
for new designs (NRND)
Temperature Range:
C = Commercial
Pb-free
Package Type:
LQ = 24-pin QFN (Sawn Type)
No of pins in package / KGD Level:
24 = 24 pins
Part Number
Marketing Code: RF = Wireless (radio frequency) product line
Company ID: CY = Cypress
CY 9935 - 24RF CLQ X
Not recommended for new designs
CYPRESS means.) In Inunlnuw V‘EW ovus MAX ‘io DMAX TOP vwa 5mg 4001010 2A 19 ‘ O <3 \pw="" ‘="" nor="" 2="" a="" +1="" 8="" 5=""><3 7=""><2 t="" notes="" :="" |="" @="" hatch="" \s="" solderaele="" exposed="" metal,="" 2="" reference="" jedec="" #="" m0i248="" 3="" package="" we‘ght="" :="" 29="" i="" 3="" mg="" 4="" all="" d‘mens‘ons="" are="" \n="" m‘lumeters="" bottom="" v‘ew="" t7;="" 65:0‘m4‘l="" m="" i="" m="" t="" 0.50:0="" 05="" £="" {="" 015:0="" m="" «a="" 40tojd="" not="" recommended="" for="" new="" designs="">
CYRF9935
Document Number: 001-88748 Rev. *G Page 40 of 47
Packaging Information
Figure 12. 24-pin QFN (4 × 4 × 0.55 mm) LQ24A 2.65 × 2.65 E-Pad (Sawn) Package Outline, 001-13937
Not recommended for new designs
{EMPRESS ' mmnznmmumw Not recommended for new designs
CYRF9935
Document Number: 001-88748 Rev. *G Page 41 of 47
Acronyms Document Conventions
Units of Measure
Table 38. Acronyms Used in this Document
Acronym Description
AACK Auto-Acknowledge
AAWD Auto ACK Wait Delay
ACK Acknowledge
ARSC Auto Resend Count
DPL Dynamic Payload
ESR Equivalent Series Resistance
FIFO First In First Out
I/O Input/Output
LSB Least Significant Bit
MCU Microcontroller Unit
MISO Master In Slave Out
MSB Most Significant Bit
NRND Not recommended for new designs
PLL Phased Locked Loop
QFN Quad Flat No-lead
RF Radio Frequency
RSD Resend Delay
R/W Read/Write
RX Receive
RXer Receiver
SCK Serial Clock
SPI Serial Peripheral Interface
TX Transmit
TXer Transmitter
VoRF Voice over Radio Frequency
Table 39. Units of Measure
Symbol Unit of Measure
°C degree Celsius
dBm decibel-milliwatt
GHz gigahertz
kHz kilohertz
MHz megahertz
Mmegaohm
µA microampere
Fmicrofarad
mA milliampere
mH millihenry
mm millimeter
ms millisecond
mW milliwatt
nA nanoampere
nH nanohenry
ns nanosecond
ohm
%percent
ppm parts per million
pF picofarad
Vvolt
Not recommended for new designs
29me 26: L8 cmvcmEEooE #oZ u unlknw Elfiflfiss' A 1‘
CYRF9935
Document Number: 001-88748 Rev. *G Page 42 of 47
Document History Page
Document Title: CYRF9935, WirelessUSB™ NX 2.4 GHz Low Power Radio
Document Number: 001-88748
Revision ECN No. Orig. of
Change
Submission
Date Description of Change
** 4184206 DEJO 11/08/2013 New data sheet.
*A 4202840 DEJO 11/26/2013 Updated Pin Descriptions:
Added Note 3 and referred the same note in pins 7, 12 and 18.
Updated Power Management:
Updated Figure 2.
Updated Table 8:
Updated Condition corresponding to Path 1 and also added one more
condition.
Updated Condition corresponding to Path 3.
Replaced CE with Mode in Condition corresponding to Path 8-9.
Added details corresponding to Path 15.
Added a Note below the table.
Updated Sleep Mode:
Updated description.
*B 4220889 ANKC 12/15/2013 Updated Block Diagram.
Updated Pin Descriptions:
Updated Note 3 (Removed “of 3.3 V”).
Updated Functional Overview:
Updated Interrupt:
Updated Table 1 (Replaced “TX_MT” with “TX_MAX_ARSC”).
Updated RF Pins:
Updated description.
Updated RF Channel:
Updated description.
Updated Transmit Power control:
Updated Table 4 (Replaced “Address” with “Indirect Register Address”).
Updated RSSI Operation:
Updated description.
Updated Power Management:
Updated Figure 2.
Updated Tabl e 8 (Updated “Path” column, replaced “Undefined” with “Reset”).
Updated Idle-I Mode:
Updated description.
Updated Sleep Mode:
Updated description.
Updated Transmit Mode:
Updated description.
Updated SPI Command:
Updated SPI Timing:
Updated Figure 10.
Updated Table 22:
Removed Tcd, Tcdz parameters and their details.
Replaced “CSN” with “SPI_nSS”.
Updated “Symbol” column.
Updated SPI Command for TX FIFO Access:
Updated Table 31 (Updated details of Byte 2).
Updated Absolute Maximum Ratings:
Included “Parameter” column and renamed the existing “Parameter” column
as “Description”.
Replaced “VCC” with “VIN”.
Replaced “VSS” with “GND”.
Not recommended for new designs
29me 26: L8 cmvcmEEooE #oZ
CYRF9935
Document Number: 001-88748 Rev. *G Page 43 of 47
*B (Cont.) 4220889 ANKC 12/15/2013 Updated Operating Range:
Included “Parameter” column and renamed the existing “Parameter” column
as “Description”.
Replaced “VCC” with “VIN”.
Updated Electrical Specifications:
Updated Power Consumption:
Included “Parameter” column and renamed the existing “Item” column as
“Description”.
Updated General RF Conditions:
Included “Parameter” column and renamed the existing “Item” column as
“Description”.
Changed maximum value of “Operating frequency” from 2480 to 2525.
Removed “Non-overlapping channel spacing (2 Mbps)”, “Non-overlapping
channel spacing (250 kbps)” and their details.
Updated Transmitter Operation:
Included “Parameter” column and renamed the existing “Item” column as
“Description”.
Removed “RF power control range” and its details.
Updated Receiver Operation:
Included “Parameter” column and renamed the existing “Item” column as
“Description”.
Removed “Sensitivity degration @ LNA low gain mode” and its details.
Updated Crystal Specification:
Included “Parameter” column and renamed the existing “Item” column as
“Description”.
Updated DC Characteristics:
Included “Parameter” column and renamed the existing “Item” column as
“Description”.
Replaced “VCC” with “VIN”.
Updated Power-On Reset:
Included “Parameter” column and renamed the existing “Item” column as
“Description”.
*C 4341593 ANKC 04/15/2014 Changed status from Preliminary to Final.
Updated Key Features.
Updated Pin Configuration:
Updated Figure 1.
Updated Pin Descriptions.
Updated Functional Overview:
Removed Clock frequency measurement.
Updated RF Pins:
Updated description.
Updated Transmit Power control:
Updated description.
Updated Table 5.
Updated RSSI Operation:
Updated description.
Updated Table 7.
Updated Power Management:
Updated description.
Updated Table 8.
Updated Sleep Mode:
Updated description.
Updated Transmit Mode:
Updated description.
Updated Receive Mode:
Updated description.
Document History Page (continued)
Document Title: CYRF9935, WirelessUSB™ NX 2.4 GHz Low Power Radio
Document Number: 001-88748
Revision ECN No. Orig. of
Change
Submission
Date Description of Change
Not recommended for new designs
$9me 26: L8 umvcmEEooE 62 unlknw £2,153.39 A 2‘
CYRF9935
Document Number: 001-88748 Rev. *G Page 44 of 47
*C (cont.) 4341593 ANKC 04/15/2014 Updated Baseband Engine:
Updated Packet Format:
Updated Preamble:
Updated description.
Updated Address:
Updated description.
Updated Packet Control Word:
Updated Payload Length:
Updated description.
Updated CRC:
Updated description.
Updated Auto-Retransmit Mode:
Updated Table 18.
Updated Table 19.
Updated Timing Diagram of Auto-Retransmit Mode:
Updated Figure 4.
Updated Data Packet Loss:
Updated description.
Updated ACK Packet Loss:
Updated description.
Renamed “FIFO Handle and Control” as FIFO Control.
Updated Overview:
Updated description.
Updated TX FIFO Access:
Updated description.
Updated Table 23.
Updated SPI Command:
Updated SPI Timing:
Updated Table 24.
Updated Command List:
Updated Table 25:
Updated details in “Description” column for R_REGISTER, W_REGISTER,
R_RX_PAYLOAD, W_TX_PAYLOAD, W_ACK_PAYLOAD, and
REUSE_TX_PAYLOAD commands.
Added Notes 7, 8, and 6.
Referred Notes 7, 6 in “Command Word” of W_TX_PAYLOAD commands.
Referred Notes 8, 6 in “Command Word” of W_ACK_PAYLOAD command.
Updated SPI Command for Register Read and Write:
Updated description.
Updated SPI Command for RX FIFO Access:
Updated Note 9 referred in Table 29.
Updated SPI Command for TX FIFO Access:
Updated Table 33.
Updated Register Sets:
Updated details in “Description” column for 0x03 address.
Updated details in “Description” column for 0x05 address.
Updated details in “Description” column for 0x08 address.
Updated details in “Bit”, “Reset Value”, “Description” columns for 0x21 address.
Updated details in “Description” column for 0x3C address.
Updated Application Circuit:
Updated Figure 11.
Updated Table 37.
Document History Page (continued)
Document Title: CYRF9935, WirelessUSB™ NX 2.4 GHz Low Power Radio
Document Number: 001-88748
Revision ECN No. Orig. of
Change
Submission
Date Description of Change
Not recommended for new designs
29me 26: L8 cmvcmEEooE 62
CYRF9935
Document Number: 001-88748 Rev. *G Page 45 of 47
*C (cont.) 4341593 ANKC 04/15/2014 Updated Electrical Specifications:
Updated Power Consumption:
Updated typical value of Idd_idle2 parameter.
Updated description of Idd_tx6, Idd_tx12, Idd_tx18 parameters.
Updated General RF Conditions:
Updated minimum value of F_op parameter.
Updated typical value of Df2avg parameter.
Updated typical value of Df1avg parameter.
Updated Transmitter Operation:
Updated maximum value of BW_20dB_2M parameter.
Updated Receiver Operation:
Updated Note 20 referred in Notes column.
*D 4529727 DEJO 10/28/2014 Updated Functional Overview:
Updated RF Channel:
Updated Table 2:
Replaced “126” with “125” in “Channel Number (Decimal)” column.
Updated Transmit Power control:
Updated Table 4:
Replaced “address” with “register” in “Description” column.
Updated Baseband Engine:
Updated Packet Control Word:
Updated PID:
Updated description.
Updated NOACK:
Updated description.
Updated Auto-Retransmit Mode:
Updated description.
Updated Table 18:
Replaced “AA” with “Auto-ACK” in “Description” column corresponding to
“0x05” address.
Updated SPI Command:
Updated Command List:
Updated Table 25:
Added Note 5 and referred the same note in “00AAAAAA” and “01AAAAAA”
in “Command Word” column.
Updated SPI Command for TX FIFO Access:
Updated Table 33:
Removed row corresponding to “Byte 3–34”.
Updated Register Sets:
Updated details in “Description” column for bit 1 of 0x01 address.
Replaced “AA” with “Auto-ACK” in “Description” column for 0x05 address.
Replaced “PIPI” with “PIPE” in “Description” column for 0x13, 0x14, and 0x15
addresses.
Updated Indirect Registers:
Updated Table 36:
Updated details in “Description” column for bit 6:0 of 0x00 address.
Removed row corresponding to 0x0B address.
Completing Sunset Review.
Document History Page (continued)
Document Title: CYRF9935, WirelessUSB™ NX 2.4 GHz Low Power Radio
Document Number: 001-88748
Revision ECN No. Orig. of
Change
Submission
Date Description of Change
Not recommended for new designs
$9me 26: L8 umvcmEEooE 62 unlknw £2,153.39 A 2‘
CYRF9935
Document Number: 001-88748 Rev. *G Page 46 of 47
*E 4616502 DEJO 01/21/2015 Updated Functional Overview:
Updated Interrupt:
Updated Table 1:
Updated details in “Description” column for TX_DS Interrupt source.
Updated details in “Description” column for TX_FIFO Interrupt source.
Updated FIFO Control:
Updated TX FIFO Access:
Updated Table 22:
Updated details in “Description” column for 0x01 address.
Updated details in “Description” column for 0x28 address.
Updated SPI Command:
Updated SPI Status in Command Phase:
Updated description.
Added Ta bl e 26.
Updated SPI Command for RX FIFO Access:
Updated description.
Added Ta bl e 30.
Updated SPI Command for TX FIFO Access:
Updated description.
Updated Table 31:
Updated Note 13 referred in Ta b le 31 .
Updated Table 33:
Updated Note 13 referred in Ta b le 33 .
Added Ta bl e 34.
Updated Register Sets:
Updated details in “Description” column for bit 1 of 0x01 address.
*F 5216464 UTSV 04/11/2016 Updated Ordering Information:
No change in part numbers.
Added a column “Comments” and added “This part is not recommended for
new designs (NRND)” in the column.
Updated to new template.
*G 5731626 SGUP 05/09/2017 Added watermark “Not recommended for new designs” across the document.
Updated to new template.
Document History Page (continued)
Document Title: CYRF9935, WirelessUSB™ NX 2.4 GHz Low Power Radio
Document Number: 001-88748
Revision ECN No. Orig. of
Change
Submission
Date Description of Change
Not recommended for new designs
CYPRESS smmn m vaunnow A :i @9me 3m: L8 vmvcmEEooE “oz
Document Number: 001-88748 Rev. *G Revised May 9, 2017 Page 47 of 47
CYRF9935
© Cypress Semiconductor Corporation, 2013–2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
ARM® Cortex® Microcontrollers cypress.com/arm
Automotive cypress.com/automotive
Clocks & Buffers cypress.com/clocks
Interface cypress.com/interface
Internet of Things cypress.com/iot
Memory cypress.com/memory
Microcontrollers cypress.com/mcu
PSoC cypress.com/psoc
Power Management ICs cypress.com/pmic
Touch Sensing cypress.com/touch
USB Controllers cypress.com/usb
Wireless Connectivity cypress.com/wireless
PSoC® Solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Forums | WICED IOT Forums | Projects | Video | Blogs |
Training | Components
Technical Support
cypress.com/support
Not recommended for new designs

Products related to this Datasheet

NO WARRANTY
IC RF TXRX ISM>1GHZ 24UFQFN