MD1822 Datasheet by Microchip Technology

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6‘ MICRDCHIP MD1822
2018 Microchip Technology Inc. DS20005706A-page 1
MD1822
Features
Mixed Inversion MOSFET Driver
6 ns Rise and Fall Time
2A Peak Output Source-and-Sink Current
1.8V to 5V Input CMOS Compatible
5V to 10V Total Supply Voltage
Smart Logic Threshold
Low-Jitter Design
Four Matched Channels
Drives Two P-Channel and Two N-Channel
MOSFETs
Outputs can swing below Ground
Low-Inductance, Quad-Flat No-Lead Package
High-Performance, Thermally Enhanced
Packaging
Applications
Medical Ultrasound Imaging
Piezoelectric Transducer Drivers
Non-Destructive Testing
PIN Diode Driver
CCD Clock Driver/Buffer
High-Speed Level Translator
General Description
The MD1822 is a high-speed, four-channel MOSFET
driver designed to drive high-voltage P-channel and
N-channel MOSFETs for medical ultrasound
applications and other applications requiring a high-
output current for a capacitive load. The high-speed
input stage of the MD1822 can operate from a 1.8V to
5V logic interface with an optimum operating input
signal range of 1.8V to 3.3V. An adaptive threshold
circuit is used to set the level translator switch
threshold to the average of the input logic 0 and
logic 1 levels. The input logic levels may be ground
referenced even though the driver is putting out bipolar
signals. The level translator uses a proprietary circuit,
which provides DC coupling together with high-speed
operation.
The output stage of the MD1822 has separate power
connections, enabling the output signal L and H levels
to be chosen independently from the supply voltages
used for the majority of the circuit. As an example, the
input logic levels may be 0V and 1.8V, the control logic
may be powered by +5V and –5V, and the output L and
H levels may be varied anywhere over the range of –5V
to +5V. The output stage is capable of peak currents of
up to ±2A, depending on the supply voltages used and
load capacitance present. The PE pin serves a dual
purpose. First, its logic H level is used to compute the
threshold voltage level for the channel input level
translators. (See Figure 3-1.) Second, when PE is low,
the outputs are disabled, with the A and C outputs high
and the B and D outputs low. This assists in properly
precharging the AC coupling capacitors that may be
used in series in the gate drive circuit of an external
PMOS and NMOS transistor pair.
Package Type
16-lead QFN
(Top view)
1
See Table 2-1 for pin information.
High-Speed 4-Channel MOSFET Driver with Two Inverting
and Two Non-Inverting Outputs
PE
INA
INB OUTB
VDD VH
INC
IND
OUTC
OUTD
GND VSS VL
MD1822
INB
VDD
OUTC
OUTD
GND
Level
Shifter
VH
PE
INA
VSS VL
OUTB
OUTA
VDD VH
INC
IND
SUB
VSS VL
Level
Shifter
Level
Shifter
Level
Shifter
Level
Shifter
VDD VH
VSS VL
VDD VH
VSS VL
MD1822
OUTA
MD1822
DS20005706A-page 2 2018 Microchip Technology Inc.
Functional Block Diagrams
1:1... NM MN T _ I___ H M L: H». ME
2018 Microchip Technology Inc. DS20005706A-page 3
MD1822
Typical Application Circuit
3.3V CMOS
Logic Inputs
OUTA
OUTB
OUTC
OUTD
+10V
0.1µF
VDD VH
+10V
VSS VL
GND
INA
INB
INC
IND
PE
MD1822
PIN
10nF
10nF
+100V
HVOUT
-100V
+3.3V
NIN
DMP
0.47µF
TC6320
0.47µF
0.47µF
TC6320
10nF
10nF
RIN PE w S‘NK RSDURCE ‘S‘NK ISINK ISOURCE
MD1822
DS20005706A-page 4 2018 Microchip Technology Inc.
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
Logic Supply Voltage, VDD–VSS ........................................................................................................... –0.5V to +12.5V
Output High Supply Voltage, VH ................................................................................................... VL–0.5V to VDD+0.5V
Output Low Supply Voltage, VL.....................................................................................................VSS–0.5V to VH+0.5V
Low-Side Supply Voltage, VSS .................................................................................................................. –6V to +0.5V
Logic Input Levels ................................................................................................................... VSS–0.5V to GND +5.5V
Maximum Junction Temperature, TJ ................................................................................................................... +125°C
Operating Ambient Temperature, TA ..................................................................................................... –20°C to +85°C
Storage Temperature, TS ..................................................................................................................... –65°C to +150°C
Power Dissipation (Thermal Resistance, JA = 55 °C/W) (Note 2):
16-lead QFN ................................................................................................................................................ 2.2W
ESD Rating (Note 1) .................................................................................................................................ESD Sensitive
Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions above those
indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Note 1: Device is ESD sensitive. Handling precautions are recommended.
2: Mounted on a 1 oz. four-layer 3” x 4” PCB
DC ELECTRICAL CHARACTERISTICS
Electrical Specifications: VH = VDD = 10V, VL = VSS = GND = 0V, VPE = 3.3V, TA = 25°C
Parameter Sym. Min. Typ. Max. Unit Conditions
Logic Supply Voltage VDDVSS 4.75 11.5 V4V VDD 11.5V
Low-Side Supply Voltage VSS –5.5 0 V
Output High Supply Voltage VHVSS+2 VDD V
Output Low Supply Voltage VLVSS VDD–4 V
VDD Quiescent Current IDDQ 60 μANo input transitions, PE = 0
VH Quiescent Current IHQ 2 μA
VDD Quiescent Current IDDQ 1 mA No input transitions, PE = 1
VH Quiescent Current IHQ 2 μA
VDD Average Current IDD 4 mA One channel on at 5 MHz, no load
VH Average Current IH10 mA
Input Logic Voltage High VIH VPE–0.3 VPE V
For logic inputs INA, INB, INC, and
IND
Input Logic Voltage Low VIL 0 0.3 V
Input Logic Current High IIH 1 μA
Input Logic Current Low IIL 1 μA
PE Input logic Voltage High VIH 1.7 3.3 5.25 V
For logic input PEPE Input Logic Voltage Low VIL 0 0.3 V
PE Input Impedance to GND RIN_PE 100 — k
Logic Input Capacitance CIN 5 10 pF ISINK = 50 mA
Output Sink Resistance RSINK 1.5 ISOURCE = 50 mA
Output Source Resistance RSOURCE 2
Peak Output Sink Current ISINK 2 — A
Peak Output Source Current ISOURCE 2 — A
PErON
AC ELECTRICAL CHARACTERISTICS
Electrical Specifications: VH = VDD = 10V, VL = VSS = GND = 0V, VPE = 3.3V, TA = 25°C unless otherwise indicated.
Parameter Sym. Min. Typ. Max. Unit Conditions
Input or PE Rise and Fall Time tirf — — 10 ns Logic input edge speed require-
ment
Propagation Delay when Output is
from Low to High tPLH 6.5 ns
CLOAD = 1000 pF (see Timing
Diagram), input signal rise/fall
time 2 ns
Propagation Delay when Output is
from High to Low tPHL 6.5 ns
Output Rise Time tr 7 ns
Output Fall Time tf 7 ns
Rise and Fall Time Matching l tr–tf l 1 ns
For each channel
Propagation Low to High and High
to Low Matching l tPLH–tPHL l 1 ns
Propagation Delay Matching tdm ±2 ns Device to device delay match
PE On Time tPE–ON — — 5 µs VPE = 1.7V–5.25V,
VDD = 7.5V–11.5V,
–20°C–85°C
PE Off-Time tPE–OFF — — 4 µs
TEMPERATURE SPECIFICATIONS
Parameter Sym. Min. Typ. Max. Units Conditions
TEMPERATURE RANGE
Maximum Junction Temperature TJ +125 °C
Operating Ambient Temperature TA–20 +85 °C
Storage Temperature TS–65 +150 °C
PACKAGE THERMAL RESISTANCE
16-lead QFN JA 55 °C/W
2018 Microchip Technology Inc. DS20005706A-page 5
MD1822
MD1822
DS20005706A-page 6 2018 Microchip Technology Inc.
Timing Diagram
0V
3.3V
IN
tPLH
10%
90%
50%
0V
10V
50%
OUT
tPHL
tr
90%
10%
tf
TABLE 1-1: TRUTH FUNCTION TABLE
Logic Input Output
PE INA INB OUTA OUTB
H L H VHVH
H L L VHVL
H H H VLVH
H H L VLVL
L X X VHVL
PE INC IND OUTC OUTD
H L H VHVH
H L L VHVL
H H H VLVH
H H L VLVL
L X X VHVL
2018 Microchip Technology Inc. DS20005706A-page 7
MD1822
2.0 PIN DESCRIPTION
The details on the pins of MD1822 are listed on
Table 2-1. See Package Type for the location of pins.
TABLE 2-1: PIN FUNCTION TABLE
Pin Number Pin Name Description
1INB Logic input
2VDD High-side supply voltage
3VSS Low-side supply voltage. VSS is also connected to the IC substrate. It is required to
connect to the most negative potential of voltage supplies.
4INC Logic input
5IND Logic input
6 GND Logic input ground reference
7VL Supply voltage for N-channel output stage
8OUTC Output driver
9OUTD Output driver
10, 11 VH Supply voltage for P-channel output stage
12 OUTA Output driver
13 OUTB Output driver
14 VL Supply voltage for N-channel output stage
15 PE Power enable logic input. When PE is high, it sets the input logic threshold. When PE is
low, all outputs are at default state (See Ta b le 1-1.) and the IC is in Standby mode.
16 INA Logic input
Substrate The IC substrate is internally connected to the thermal pad. The thermal pad and VSS
must be connected externally.
MD1822 Delay vs Temperature MD1322 r a. t, vs Temperature
MD1822
DS20005706A-page 8 2018 Microchip Technology Inc.
3.0 APPLICATION INFORMATION
For proper operation of the MD1822, low-inductance
bypass capacitors should be used on the various
supply pins. The GND pin should be connected to the
logic ground. The INA, INB, INC, IND and PE pins
should be connected to a logic source with a swing of
GND to PE, where PE is from 1.8V to 5V. Good trace
practices should be followed corresponding to the
desired operating speed. The internal circuitry of the
MD1822 is capable of operating up to 100 MHz, with
the primary speed limitation being the loading effects of
the load capacitance. Because of this speed and the
high transient currents that result in capacitive loads,
the bypass capacitors should be as close to the chip
pins as possible. Unless the load specifically requires
bipolar drive, the VSS and VL pins should have
low-inductance feed-through connections directly to a
ground plane. If these voltages are not zero, then they
need bypass capacitors in a manner similar to the
positive power supplies. The power connection VDD
should have a ceramic bypass capacitor to the ground
plane with short leads and decoupling components to
prevent resonance in the powerleads.
VPE
VTH
0
0.5
1.0
1.5
2.0
1.0 2.0 3.0 4.0 5.00
VPE/2
FIGURE 3-1: VTH/VPE Graph.
MD1822 Delay vs Temperature MD1822 t
r
& t
f
vs Temperature
MD1822 Delay vs V
DD
MD1822 t
r
& t
f
vs V
DD
Delay Time (ns)
tPLH
tPHL
Temperature (OC)
-50 0 50 125
9
8
7
6
5
4
3
Time (ns)
tr tf
Temperature (OC)
-50 0 50 125
9
8
7
6
5
4
3
Delay Time (ns)
tPLH
tPHL
VDD Voltage (V)
5 8 10 12
12
10
8
6
4
2
0
Time (ns)
tr
tf
VDD Voltage (V)
5 8 10 12
12
10
8
6
4
2
0
FIGURE 3-2: Rise/Fall times, propagation delay vs. VDD voltage and Temperature.
The voltages of VH and VL decide the output signal
levels. These two pins can draw fast transient currents
of up to 2A, so they should be provided with an
appropriate bypass capacitor located next to the chip
pins. A ceramic capacitor of up to 1 µF may be
appropriate, with a series ferrite bead to prevent
resonance in the power supply lead coming to the
capacitor. Pay particular attention to minimizing trace
lengths, current loop area and using sufficient trace
width to reduce inductance. Surface-mount
components are highly recommended. Since the
output impedance of this driver is very low, in some
cases, it may be desirable to add a small series
resistance in series with the output signal to obtain
better waveform transitions at the load terminals. This
will reduce the output voltage slew rate at the terminals
of a capacitive load.
2018 Microchip Technology Inc. DS20005706A-page 9
MD1822
Make sure that parasitic couplings are minimized from
the output to the input signal terminals. The parasitic
feedback may cause oscillations or spurious waveform
shapes on the edges of signal transitions. Since the
input operates with signals down to 1.8V, even small
coupled voltages may cause problems. The use of a
solid ground plane and good power and signal layout
practices will prevent this problem. Be careful that a
circulating ground return current from a capacitive load
cannot react with common inductance to cause noise
voltages in the input logic circuitry.
NNN
MD1822
DS20005706A-page 10 2018 Microchip Technology Inc.
4.0 PACKAGING INFORMATION
4.1 Package Marking Information
Legend: XX...X Product Code or Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for product code or customer-specific information. Package may or
not include the corporate logo.
3
e
3
e
16-lead QFN
XXXXX
XYWW
NNN
Example
182
2815
232
16-Lead QFN Package Outline (K6) 3.00x3.00mm body, 1.00mm height (max), 0.50mm pitch ‘ D m 0.... ¥ 01 k 7 lmuxhuu ., *5 {mm U U 1 ‘ a Hm. T “mm. mm) LB + E J. hD T n TOE WI 9 . L N / .. m... . m “WmmmmmmWNW“ Wm WWW .mmmamm mmmmmmm m WWW 2 Depending on ma mat/m annanmmmmg, a mawmm 0/0 15mm Mom (L 1! may us press”! 3 we may nu mme man may be elmsrmumtsd ar square Symbu‘ ‘ A ‘ A1 MIN 0.00 0.00 0.10 2.85“ 1.50 2.05' 1 50 0.201 0.00 0° Dimension 0.20 0.50 (mm) NOM 0.90 0.02 REF 0.25 3.00 1.65 a 00 1 65 55c 0.307 » - MAX 100 0.05 0.30 3.15' 1.00 115' 1 00 0.45 0.15 14° JEDEC Regulmnon M0220 Vanunon vsau, [55119 K. June 2006 - This dmnsmn 5 m1 Wsmfiefl m the 45050 mm 1 m: mmensm mm mm me JEDEC mwmg Drawing: not to sale
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
2018 Microchip Technology Inc. DS20005706A-page 11
MD1822
MD1822
DS20005706A-page 12 2018 Microchip Technology Inc.
NOTES:
2018 Microchip Technology Inc. DS20005706A-page 13
MD1822
APPENDIX A: REVISION HISTORY
Revision A (October 2018)
Converted Supertex Doc# DSFP-MD1822 to
Microchip DS20005706A
Changed the package marking format
Changed the quantity of the K6 package from
3000/Reel to 3300/Reel
Made minor text changes throughout the
document
PART NO. f v 1“ a Env \x
MD1822
DS20005706A-page 14 2018 Microchip Technology Inc.
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.
Example:
a) MD1822K6-G: High-Speed 4-Channel MOSFET
Driver with Two Inverting and Two
Non-Inverting Outputs, 16-lead (3x3)
VQFN, 3300/Reel
PART NO.
Device
Device: MD1822 = High-Speed 4-Channel MOSFET Driver
with Two Inverting and Two Non-Inverting
Outputs
Package: K6 = 16-lead (3x3) VQFN
Environmental: G = Lead (Pb)-free/RoHS-compliant Package
Media Type: (blank) = 3300/Reel for a K6 Package
XX
Package
-
X - X
Environmental
Media Type
Options
YSTEM
2018 Microchip Technology Inc. DS20005706A-page 15
Information contained in this publication regarding device
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and may be superseded by updates. It is your responsibility to
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© 2018, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-3755-0
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DS20005706A-page 16 2018 Microchip Technology Inc.
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