STM32F401xD, STM32F401xE Datasheet by STMicroelectronics

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This is information on a product in full production.
January 2015 DocID025644 Rev 3 1/135
STM32F401xD STM32F401xE
ARM® Cortex®-M4 32b MCU+FPU, 105 DMIPS,
512KB Flash/96KB RAM, 11 TIMs, 1 ADC, 11 comm. interfaces
Datasheet - production data
Features
Core: ARM® 32-bit Cortex®-M4 CPU with
FPU, Adaptive real-time accelerator (ART
Accelerator™) allowing 0-wait state execution
from Flash memory, frequency up to 84 MHz,
memory protection unit,
105 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1),
and DSP instructions
Memories
up to 512 Kbytes of Flash memory
up to 96 Kbytes of SRAM
Clock, reset and supply management
1.7 V to 3.6 V application supply and I/Os
POR, PDR, PVD and BOR
4-to-26 MHz crystal oscillator
Internal 16 MHz factory-trimmed RC
32 kHz oscillator for RTC with calibration
Internal 32 kHz RC with calibration
Power consumption
Run: 146 µA/MHz (peripheral off)
Stop (Flash in Stop mode, fast wakeup
time): 42 µA Typ @ 25C; 65 µA max
@25 °C
Stop (Flash in Deep power down mode,
fast wakeup time): down to 10 µA @ 25 °C;
30 µA max @25 °C
Standby: 2.4 µA @25 °C / 1.7 V without
RTC; 12 µA @85 °C @1.7 V
–V
BAT supply for RTC: 1 µA @25 °C
1×12-bit, 2.4 MSPS A/D converter: up to 16
channels
General-purpose DMA: 16-stream DMA
controllers with FIFOs and burst support
Up to 11 timers: up to six 16-bit, two 32-bit
timers up to 84 MHz, each with up to four
IC/OC/PWM or pulse counter and quadrature
(incremental) encoder input, two watchdog
timers (independent and window) and a
SysTick timer
Debug mode
Serial wire debug (SWD) & JTAG
interfaces
–Cortex
®-M4 Embedded Trace Macrocell™
Up to 81 I/O ports with interrupt capability
Up to 78 fast I/Os up to 42 MHz
All I/O ports are 5 V-tolerant
Up to 12 communication interfaces
Up to 3 x I2C interfaces (SMBus/PMBus)
Up to 3 USARTs (2 x 10.5 Mbit/s,
1 x 5.25 Mbit/s), ISO 7816 interface, LIN,
IrDA, modem control)
Up to 4 SPIs (up to 42Mbit/s at
fCPU = 84 MHz), SPI2 and SPI3 with muxed
full-duplex I2S to achieve audio class
accuracy via internal audio PLL or external
clock
SDIO interface
Advanced connectivity: USB 2.0 full-speed
device/host/OTG controller with on-chip
PHY
CRC calculation unit
96-bit unique ID
RTC: subsecond accuracy, hardware calendar
All packages (WLCSP49, LQFP64/100,
UFQFPN48, UFBGA100) are ECOPACK®2
Table 1. Device summary
Reference Part number
STM32F401xD STM32F401CD,
STM32F401RD, STM32F401VD
STM32F401xE STM32F401CE,
STM32F401RE, STM32F401VE
LQFP100 (14 × 14 mm)
LQFP64 (10 × 10 mm)
UFQFPN48
(7 × 7 mm)
UFBGA100
(7 × 7 mm)
WLCSP49
(3.06 x 3.06 mm)
)%*$
www.st.com
Contents STM32F401xD STM32F401xE
2/135 DocID025644 Rev 3
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 Compatibility with STM32F4 series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1 ARM® Cortex®-M4 with FPU core with embedded Flash and SRAM . . . 15
3.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 15
3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 16
3.6 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.7 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.8 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.9 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 18
3.10 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.11 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.12 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.13 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.14 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.14.1 Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.14.2 Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.15 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.15.1 Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.15.2 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.15.3 Regulator ON/OFF and internal power supply supervisor availability . . 25
3.16 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 25
3.17 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.18 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.19 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.19.1 Advanced-control timers (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.19.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
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3.19.3 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.19.4 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.19.5 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.20 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.21 Universal synchronous/asynchronous receiver transmitters (USART) . . 29
3.22 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.23 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.24 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.25 Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . . . . 31
3.26 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 31
3.27 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.28 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.29 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.30 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.31 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.3.2 VCAP1/VCAP2 external capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.3.3 Operating conditions at power-up/power-down (regulator ON) . . . . . . . 63
6.3.4 Operating conditions at power-up / power-down (regulator OFF) . . . . . 63
6.3.5 Embedded reset and power control block characteristics . . . . . . . . . . . 64
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6.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.3.7 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.3.11 PLL spread spectrum clock generation (SSCG) characteristics . . . . . . 84
6.3.12 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.3.14 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 89
6.3.15 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.3.16 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.3.17 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.3.18 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.3.19 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
6.3.20 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
6.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.3.22 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.3.23 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.3.24 SD/SDIO MMC card host interface (SDIO) characteristics . . . . . . . . . 113
6.3.25 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
7 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
7.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
7.1.1 WLCSP49, 3.06 x 3.06 mm, 0.4 mm pitch wafer level chip
size package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
7.1.2 UFQFPN48, 7 x 7 mm, 0.5 mm pitch package . . . . . . . . . . . . . . . . . . 119
7.1.3 LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package . . . . . . . . 122
7.1.4 LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package . . . . . . 125
7.1.5 UFBGA100, 7 x 7 mm, 0.5 mm pitch package . . . . . . . . . . . . . . . . . . 128
7.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
7.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
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STM32F401xD STM32F401xE List of tables
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List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. STM32F401xD/xE features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Regulator ON/OFF and internal power supply supervisor availability. . . . . . . . . . . . . . . . . 25
Table 4. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 5. Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 6. USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 7. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 8. STM32F401xD/xE pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 9. Alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 10. STM32F401xD register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 11. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 12. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 13. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 14. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 15. Features depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 16. VCAP1/VCAP2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 17. Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 63
Table 18. Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 63
Table 19. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 20. Typical and maximum current consumption, code with data processing (ART
accelerator disabled) running from SRAM - VDD = 1.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 21. Typical and maximum current consumption, code with data processing (ART
accelerator disabled) running from SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 22. Typical and maximum current consumption in run mode, code with data processing
(ART accelerator enabled except prefetch) running from Flash memory- VDD = 1.7 V. . . 67
Table 23. Typical and maximum current consumption in run mode, code with data processing
(ART accelerator enabled except prefetch) running from Flash memory - VDD = 3.3 V . . 67
Table 24. Typical and maximum current consumption in run mode, code with data processing
(ART accelerator disabled) running from Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 25. Typical and maximum current consumption in run mode, code with data processing
(ART accelerator enabled with prefetch) running from Flash memory . . . . . . . . . . . . . . . . 68
Table 26. Typical and maximum current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 27. Typical and maximum current consumptions in Stop mode - VDD=1.8 V . . . . . . . . . . . . . . 69
Table 28. Typical and maximum current consumption in Stop mode - VDD=3.3 V. . . . . . . . . . . . . . . 70
Table 29. Typical and maximum current consumption in Standby mode - VDD=1.8 V . . . . . . . . . . . . 70
Table 30. Typical and maximum current consumption in Standby mode - VDD=3.3 V . . . . . . . . . . . . 70
Table 31. Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . . 71
Table 32. Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 33. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 34. Low-power mode wakeup timings(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 35. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 36. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 37. HSE 4-26 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 38. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 39. HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 40. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 41. Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 42. PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
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Table 43. SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 44. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 45. Flash memory programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 46. Flash memory programming with VPP voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 47. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 48. EMS characteristics for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 49. EMI characteristics for WLCSP49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 50. EMI characteristics for LQFP100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 51. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 52. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 53. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 54. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 55. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 56. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 57. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 58. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 59. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 60. SCL frequency (fPCLK1= 42 MHz, VDD = VDD_I2C = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 61. SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 62. I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 63. USB OTG FS startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 64. USB OTG FS DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 65. USB OTG FS electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 66. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 67. ADC accuracy at fADC = 18 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 68. ADC accuracy at fADC = 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 69. ADC accuracy at fADC = 36 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 70. ADC dynamic accuracy at fADC = 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 109
Table 71. ADC dynamic accuracy at fADC = 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 109
Table 72. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 73. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 74. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 75. Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 76. Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 77. Dynamic characteristics: SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 78. RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 79. STM32F401xCE WLCSP49 wafer level chip size package mechanical data. . . . . . . . . . 116
Table 80. WLCSP49 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . . 118
Table 81. UFQFPN48, 7 x 7 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . 119
Table 82. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package mechanical data . . . . . . . . . 123
Table 83. LQPF100, 14 x 14 mm, 100-pin low-profile quad flat package mechanical data . . . . . . . 126
Table 84. UFBGA100, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 85. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 86. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 87. Device order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 88. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
DocID025644 Rev 3 7/135
STM32F401xD STM32F401xE List of figures
8
List of figures
Figure 1. Compatible board design for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 2. Compatible board design for LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 3. STM32F401xD/xE block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 4. Multi-AHB matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 5. Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 20
Figure 6. PDR_ON control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 7. Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 8. Startup in regulator OFF: slow VDD slope -
power-down reset risen after VCAP_1/VCAP_2 stabilization. . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 9. Startup in regulator OFF mode: fast VDD slope -
power-down reset risen before VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 10. STM32F401xD/xE WLCSP49 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 11. STM32F401xD/xE UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 12. STM32F401xD/xE LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 13. STM32F401xD/xE LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 14. STM32F401xD/xE UFBGA100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 15. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 16. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 17. Input voltage measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 18. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 19. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 20. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 21. Typical VBAT current consumption (LSE and RTC ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 22. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 23. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 24. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 25. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 26. ACCHSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 27. ACCLSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 28. PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 29. PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 30. FT I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 31. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 32. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 33. I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 34. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 35. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 36. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 37. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 38. I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 39. USB OTG FS timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . 106
Figure 40. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 41. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 42. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 111
Figure 43. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 111
Figure 44. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 45. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 46. WLCSP49 wafer level chip size package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
List of figures STM32F401xD STM32F401xE
8/135 DocID025644 Rev 3
Figure 47. WLCSP49 0.4 mm pitch wafer level chip size recommended footprint . . . . . . . . . . . . . . 117
Figure 48. Example of WLCSP49 marking (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 49. UFQFPN48, 7 x 7 mm, 0.5 mm pitch, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 50. UFQFPN48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 51. Example of UFQFPN48 marking (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 52. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 122
Figure 53. LQFP64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 54. Example of LQFP64 marking (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure 55. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 125
Figure 56. LQFP100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 57. Example of LQPF100 marking (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 58. UFBGA100, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure 59. Recommended PCB design rules for pads (0.5 mm-pitch BGA) . . . . . . . . . . . . . . . . . . . 129
Figure 60. Example of UFBGA100 marking (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Cortex . InleHIgent Processors by ARM OWERED
DocID025644 Rev 3 9/135
STM32F401xD STM32F401xE Introduction
54
1 Introduction
This datasheet provides the description of the STM32F401xD/xE line of microcontrollers.
The STM32F401xD/xE datasheet should be read in conjunction with RM0368 reference
manual which is available from the STMicroelectronics website www.st.com. It includes all
information concerning Flash memory programming.
For information on the Cortex-M4 core, please refer to the Cortex-M4 programming
manual (PM0214) available from www.st.com.
Description STM32F401xD STM32F401xE
10/135 DocID025644 Rev 3
2 Description
The STM32F401XD/XE devices are based on the high-performance ARM® Cortex® -M4 32-
bit RISC core operating at a frequency of up to 84 MHz. Its Cortex®-M4 core features a
Floating point unit (FPU) single precision which supports all ARM single-precision data-
processing instructions and data types. It also implements a full set of DSP instructions and
a memory protection unit (MPU) which enhances application security.
The STM32F401xD/xE incorporate high-speed embedded memories (512 Kbytes of Flash
memory, 96 Kbytes of SRAM), and an extensive range of enhanced I/Os and peripherals
connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix.
All devices offer one 12-bit ADC, a low-power RTC, six general-purpose 16-bit timers
including one PWM timer for motor control, two general-purpose 32-bit timers. They also
feature standard and advanced communication interfaces.
Up to three I2Cs
Up to four SPIs
Two full duplex I2Ss. To achieve audio class accuracy, the I2S peripherals can be
clocked via a dedicated internal audio PLL or via an external clock to allow
synchronization.
Three USARTs
SDIO interface
USB 2.0 OTG full speed interface
Refer to for the peripherals available for each part number.
The STM32F401xD/xE operate in the –40 to +105 °C temperature range from a 1.7 (PDR
OFF) to 3.6 V power supply. A comprehensive set of power-saving mode allows the design
of low-power applications.
These features make the STM32F401xD/xE microcontrollers suitable for a wide range of
applications:
Motor drive and application control
Medical equipment
Industrial applications: PLC, inverters, circuit breakers
Printers, and scanners
Alarm systems, video intercom, and HVAC
Home audio appliances
Mobile phone sensor hub
Figure 3 shows the general block diagram of the devices.
DocID025644 Rev 3 11/135
STM32F401xD STM32F401xE Description
54
Table 2. STM32F401xD/xE features and peripheral counts
Peripherals STM32F401xD STM32F401xE
Flash memory in Kbytes 384 512
SRAM in Kbytes System 96
Timers
General-
purpose 7
Advanced-
control 1
Communication
interfaces
SPI/ I2S 3/2 (full duplex) 4/2 (full
duplex) 3/2 (full duplex) 4/2 (full
duplex)
I2C3
USART 3
SDIO - 1 - 1
USB OTG FS 1
GPIOs 36 50 81 36 50 81
12-bit ADC
Number of channels
1
10 16 10 16
Maximum CPU frequency 84 MHz
Operating voltage 1.7 to 3.6 V
Operating temperatures
Ambient temperatures: –40 to +85 °C/–40 to +105 °C
Junction temperature: –40 to + 125 °C
Package WLCSP49
UFQFPN48 LQFP64 UFBGA100
LQFP100
WLCSP49
UFQFPN48 LQFP64 UFBGA100
LQFP100
Description STM32F401xD STM32F401xE
12/135 DocID025644 Rev 3
2.1 Compatibility with STM32F4 series
The STM32F401xD/xE are fully software and feature compatible with the STM32F4 series
(STM32F42x, STM32F43x, STM32F41x, STM32F405 and STM32F407)
The STM32F401xD/xE can be used as drop-in replacement of the other STM32F4 products
but some slight changes have to be done on the PCB board.
Figure 1. Compatible board design for LQFP100 package
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DocID025644 Rev 3 13/135
STM32F401xD STM32F401xE Description
54
Figure 2. Compatible board design for LQFP64 package
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Description STM32F401xD STM32F401xE
14/135 DocID025644 Rev 3
Figure 3. STM32F401xD/xE block diagram
1. The timers connected to APB2 are clocked from TIMxCLK up to 84 MHz, while the timers connected to APB1 are clocked
from TIMxCLK up to 42 MHz.
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STM32F401xD STM32F401xE Functional overview
54
3 Functional overview
3.1 ARM® Cortex®-M4 with FPU core with embedded Flash and
SRAM
The ARM® Cortex®-M4 with FPU processor is the latest generation of ARM processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
MCU implementation, with a reduced pin count and low-power consumption, while
delivering outstanding computational performance and an advanced response to interrupts.
The ARM® Cortex®-M4 with FPU 32-bit RISC processor features exceptional code-
efficiency, delivering the high-performance expected from an ARM core in the memory size
usually associated with 8- and 16-bit devices. The processor supports a set of DSP
instructions which allow efficient signal processing and complex algorithm execution. Its
single precision FPU (floating point unit) speeds up software development by using
metalanguage development tools, while avoiding saturation.
The STM32F401xD/xE devices are compatible with all ARM tools and software.
Figure 3 shows the general block diagram of the STM32F401xD/xE.
Note: Cortex®-M4 with FPU is binary compatible with Cortex®-M3.
3.2 Adaptive real-time memory accelerator (ART Accelerator™)
The ART Accelerator™ is a memory accelerator which is optimized for STM32 industry-
standard ARM® Cortex®-M4 with FPU processors. It balances the inherent performance
advantage of the ARM® Cortex®-M4 with FPU over Flash memory technologies, which
normally requires the processor to wait for the Flash memory at higher frequencies.
To release the processor full 105 DMIPS performance at this frequency, the accelerator
implements an instruction prefetch queue and branch cache, which increases program
execution speed from the 128-bit Flash memory. Based on CoreMark benchmark, the
performance achieved thanks to the ART accelerator is equivalent to 0 wait state program
execution from Flash memory at a CPU frequency up to 84 MHz.
3.3 Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to 8 protected areas that can in turn be divided
up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4
gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
Functional overview STM32F401xD STM32F401xE
16/135 DocID025644 Rev 3
3.4 Embedded Flash memory
The devices embed 512 Kbytes of Flash memory available for storing programs and data.
3.5 CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a software
signature during runtime, to be compared with a reference signature generated at link-time
and stored at a given memory location.
3.6 Embedded SRAM
All devices embed:
96 Kbytes of system SRAM which can be accessed (read/write) at CPU clock speed
with 0 wait states
3.7 Multi-AHB bus matrix
The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs) and the slaves
(Flash memory, RAM, AHB and APB peripherals) and ensures a seamless and efficient
operation even when several high-speed peripherals work simultaneously.
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DocID025644 Rev 3 17/135
STM32F401xD STM32F401xE Functional overview
54
Figure 4. Multi-AHB matrix
3.8 DMA controller (DMA)
The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8
streams each. They are able to manage memory-to-memory, peripheral-to-memory and
memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals,
support burst transfer and are designed to provide the maximum peripheral bandwidth
(AHB/APB).
The two DMA controllers support circular buffer management, so that no specific code is
needed when the controller reaches the end of the buffer. The two DMA controllers also
have a double buffering feature, which automates the use and switching of two memory
buffers without requiring any special code.
Each stream is connected to dedicated hardware DMA requests, with support for software
trigger on each stream. Configuration is made by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals:
SPI and I2S
I2C
USART
General-purpose, basic and advanced-control timers TIMx
SD/SDIO/MMC host interface
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18/135 DocID025644 Rev 3
3.9 Nested vectored interrupt controller (NVIC)
The devices embed a nested vectored interrupt controller able to manage 16 priority levels,
and handle up to 62 maskable interrupt channels plus the 16 interrupt lines of the
Cortex®-M4 with FPU.
Closely coupled NVIC gives low-latency interrupt processing
Interrupt entry vector table address passed directly to the core
Allows early processing of interrupts
Processing of late arriving, higher-priority interrupts
Support tail chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.
3.10 External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 21 edge-detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 81 GPIOs can be connected
to the 16 external interrupt lines.
3.11 Clocks and startup
On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The
16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy at 25 °C. The
application can then select as system clock either the RC oscillator or an external 4-26 MHz
clock source. This clock can be monitored for failure. If a failure is detected, the system
automatically switches back to the internal RC oscillator and a software interrupt is
generated (if enabled). This clock source is input to a PLL thus allowing to increase the
frequency up to 84 MHz. Similarly, full interrupt management of the PLL clock entry is
available when necessary (for example if an indirectly used external oscillator fails).
Several prescalers allow the configuration of the two AHB buses, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB
buses is 84 MHz while the maximum frequency of the high-speed APB domains is 84 MHz.
The maximum allowed frequency of the low-speed APB domain is 42 MHz.
The devices embed a dedicated PLL (PLLI2S) which allows to achieve audio class
performance. In this case, the I2S master clock can generate all standard sampling
frequencies from 8 kHz to 192 kHz.
DocID025644 Rev 3 19/135
STM32F401xD STM32F401xE Functional overview
54
3.12 Boot modes
At startup, boot pins are used to select one out of three boot options:
Boot from user Flash
Boot from system memory
Boot from embedded SRAM
The boot loader is located in system memory. It is used to reprogram the Flash memory by
using either USART1(PA9/10), USART2(PD5/6), USB OTG FS in device mode (PA11/12)
through DFU (device firmware upgrade), I2C1(PB6/7), I2C2(PB10/3), I2C3(PA8/PB4),
SPI1(PA4/5/6/7), SPI2(PB12/13/14/15) or SPI3(PA15, PC10/11/12).
For more detailed information on the bootloader, refer to Application Note: AN2606,
STM32™ microcontroller system memory boot mode.
3.13 Power supply schemes
VDD = 1.7 to 3.6 V: external power supply for I/Os with the internal supervisor
(POR/PDR) disabled, provided externally through VDD pins. Requires the use of an
external power supply supervisor connected to the VDD and PDR_ON pins.
VDD = 1.8 to 3.6 V: external power supply for I/Os and the internal regulator (when
enabled), provided externally through VDD pins.
VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs
and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively, with
decoupling technique.
VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
Refer to Figure 18: Power supply scheme for more details.
EJ—
Functional overview STM32F401xD STM32F401xE
20/135 DocID025644 Rev 3
3.14 Power supply supervisor
3.14.1 Internal reset ON
This feature is available for VDD operating voltage range 1.8 V to 3.6 V.
The internal power supply supervisor is enabled by holding PDR_ON high.
The device has an integrated power-on reset (POR) / power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry. At power-on, POR is always active, and
ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is
reached, the option byte loading process starts, either to confirm or modify default
thresholds, or to disable BOR permanently. Three BOR thresholds are available through
option bytes.
The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or
VBOR, without the need for an external reset circuit.
The device also features an embedded programmable voltage detector (PVD) that monitors
the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be
generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
3.14.2 Internal reset OFF
This feature is available only on packages featuring the PDR_ON pin. The internal power-on
reset (POR) / power-down reset (PDR) circuitry is disabled by setting the PDR_ON pin to
low.
An external power supply supervisor should monitor VDD and should maintain the device in
reset mode as long as VDD is below a specified threshold. PDR_ON should be connected to
this external power supply supervisor. Refer to Figure 5: Power supply supervisor
interconnection with internal reset OFF.
Figure 5. Power supply supervisor interconnection with internal reset OFF(1)
1. The PRD_ON pin is only available in the WLCSP49 and UFBGA100 packages.
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DocID025644 Rev 3 21/135
STM32F401xD STM32F401xE Functional overview
54
The VDD specified threshold, below which the device must be maintained under reset, is
1.7 V (see Figure 6).
A comprehensive set of power-saving mode allows to design low-power applications.
When the internal reset is OFF, the following integrated features are no longer supported:
The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled.
The brownout reset (BOR) circuitry must be disabled.
The embedded programmable voltage detector (PVD) is disabled.
VBAT functionality is no more available and VBAT pin should be connected to VDD.
3.15 Voltage regulator
The regulator has four operating modes:
Regulator ON
Main regulator mode (MR)
Low power regulator (LPR)
– Power-down
Regulator OFF
3.15.1 Regulator ON
On packages embedding the BYPASS_REG pin, the regulator is enabled by holding
BYPASS_REG low. On all other packages, the regulator is always enabled.
Figure 6. PDR_ON control with internal reset OFF
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Functional overview STM32F401xD STM32F401xE
22/135 DocID025644 Rev 3
There are three power modes configured by software when the regulator is ON:
MR is used in the nominal regulation mode (With different voltage scaling in Run)
In Main regulator mode (MR mode), different voltage scaling are provided to reach the
best compromise between maximum frequency and dynamic power consumption.
LPR is used in the Stop modes
The LP regulator mode is configured by software when entering Stop mode.
Power-down is used in Standby mode.
The Power-down mode is activated only when entering in Standby mode. The regulator
output is in high impedance and the kernel circuitry is powered down, inducing zero
consumption. The contents of the registers and SRAM are lost.
Depending on the package, one or two external ceramic capacitors should be connected on
the VCAP_1 and VCAP_2 pins. The VCAP_2 pin is only available for the LQFP100 and
UFBGA100 packages.
All packages have the regulator ON feature.
3.15.2 Regulator OFF
The Regulator OFF is available only on the UFBGA100, which features the BYPASS_REG
pin. The regulator is disabled by holding BYPASS_REG high. The regulator OFF mode
allows to supply externally a V12 voltage source through VCAP_1 and VCAP_2 pins.
Since the internal voltage scaling is not managed internally, the external voltage value must
be aligned with the targeted maximum frequency. Refer to Table 14: General operating
conditions.
The two 2.2 µF VCAP ceramic capacitors should be replaced by two 100 nF decoupling
capacitors. Refer to Figure 18: Power supply scheme.
When the regulator is OFF, there is no more internal monitoring on V12. An external power
supply supervisor should be used to monitor the V12 of the logic power domain. PA0 pin
should be used for this purpose, and act as power-on reset on V12 power domain.
In regulator OFF mode, the following features are no more supported:
PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power
domain which is not reset by the NRST pin.
As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As
a consequence, PA0 and NRST pins must be managed separately if the debug
connection under reset or pre-reset is required.
DocID025644 Rev 3 23/135
STM32F401xD STM32F401xE Functional overview
54
Figure 7. Regulator OFF
The following conditions must be respected:
VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection
between power domains.
If the time for VCAP_1 and VCAP_2 to reach V12 minimum value is faster than the time for
VDD to reach 1.7 V, then PA0 should be kept low to cover both conditions: until VCAP_1
and VCAP_2 reach V12 minimum value and until VDD reaches 1.7 V (see Figure 8).
Otherwise, if the time for VCAP_1 and VCAP_2 to reach V12 minimum value is slower
than the time for VDD to reach 1.7 V, then PA0 could be asserted low externally (see
Figure 9).
If VCAP_1 and VCAP_2 go below V12 minimum value and VDD is higher than 1.7 V, then a
reset must be asserted on PA0 pin.
Note: The minimum value of V12 depends on the maximum frequency targeted in the application
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Functional overview STM32F401xD STM32F401xE
24/135 DocID025644 Rev 3
Figure 8. Startup in regulator OFF: slow VDD slope -
power-down reset risen after VCAP_1/VCAP_2 stabilization
1. This figure is valid whatever the internal reset mode (ON or OFF).
Figure 9. Startup in regulator OFF mode: fast VDD slope -
power-down reset risen before VCAP_1/VCAP_2 stabilization
1. This figure is valid whatever the internal reset mode (ON or OFF).
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STM32F401xD STM32F401xE Functional overview
54
3.15.3 Regulator ON/OFF and internal power supply supervisor availability
3.16 Real-time clock (RTC) and backup registers
The backup domain includes:
The real-time clock (RTC)
20 backup registers
The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain
the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binary-
coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are
performed automatically. The RTC features a reference clock detection, a more precise
second source clock (50 or 60 Hz) can be used to enhance the calendar precision. The RTC
provides a programmable alarm and programmable periodic interrupts with wakeup from
Stop and Standby modes. The sub-seconds value is also available in binary format.
It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power
RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC
has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz
output to compensate for any natural quartz deviation.
Two alarm registers are used to generate an alarm at a specific time and calendar fields can
be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit
programmable binary auto-reload downcounter with programmable resolution is available
and allows automatic wakeup and periodic alarms from every 120 µs to every 36 hours.
A 20-bit prescaler is used for the time base clock. It is by default configured to generate a
time base of 1 second from a clock at 32.768 kHz.
The backup registers are 32-bit registers used to store 80 bytes of user application data
when VDD power is not present. Backup registers are not reset by a system, a power reset,
or when the device wakes up from the Standby mode (see Section 3.17: Low-power
modes).
Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes,
hours, day, and date.
Table 3. Regulator ON/OFF and internal power supply supervisor availability
Package Regulator ON Regulator OFF Power supply
supervisor ON
Power supply
supervisor OFF
UFQFPN48 Yes No Yes No
WLCSP49 Yes No Yes
PDR_ON set to VDD
Yes
PDR_ON external
control(1)
LQFP64 Yes No Yes No
LQFP100 Yes No Yes No
UFBGA100
Yes
BYPASS_REG set to
VSS
Yes
BYPASS_REG set to
VDD
Yes
PDR_ON set to VDD
Yes
PDR_ON external
control (1)
1. Refer to Section 3.14: Power supply supervisor
Functional overview STM32F401xD STM32F401xE
26/135 DocID025644 Rev 3
The RTC and backup registers are supplied through a switch that is powered either from the
VDD supply when present or from the VBAT pin.
3.17 Low-power modes
The devices support three low-power modes to achieve the best compromise between low
power consumption, short startup time and available wakeup sources:
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
Stop mode
The Stop mode achieves the lowest power consumption while retaining the contents of
SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low-power mode.
The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line
source can be one of the 16 external lines, the PVD output, the RTC alarm/ wakeup/
tamper/ time stamp events).
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.2 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, the SRAM and register contents are lost except for registers in the
backup domain when selected.
The device exits the Standby mode when an external reset (NRST pin), an IWDG reset,
a rising edge on the WKUP pin, or an RTC alarm/ wakeup/ tamper/time stamp event
occurs.
Standby mode is not supported when the embedded voltage regulator is bypassed and
the 1.2 V domain is controlled by an external power.
3.18 VBAT operation
The VBAT pin allows to power the device VBAT domain from an external battery, an external
super-capacitor, or from VDD when no external battery and an external super-capacitor are
present.
VBAT operation is activated when VDD is not present.
The VBAT pin supplies the RTC and the backup registers.
Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events
do not exit it from VBAT operation. When PDR_ON pin is not connected to VDD (internal
Reset OFF), the VBAT functionality is no more available and VBAT pin should be connected
to VDD.
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STM32F401xD STM32F401xE Functional overview
54
3.19 Timers and watchdogs
The devices embed one advanced-control timer, seven general-purpose timers and two
watchdog timers.
All timer counters can be frozen in debug mode.
Table 4 compares the features of the advanced-control and general-purpose timers.
3.19.1 Advanced-control timers (TIM1)
The advanced-control timer (TIM1) can be seen as three-phase PWM generators
multiplexed on 4 independent channels. It has complementary PWM outputs with
programmable inserted dead times. It can also be considered as a complete general-
purpose timer. Its 4 independent channels can be used for:
Input capture
Output compare
PWM generation (edge- or center-aligned modes)
One-pulse mode output
Table 4. Timer feature comparison
Timer
type Timer Counter
resolution
Counter
type
Prescaler
factor
DMA
request
generation
Capture/
compare
channels
Complementary
output
Max.
interface
clock
(MHz)
Max.
timer
clock
(MHz)
Advanced-
control TIM1 16-bit
Up,
Down,
Up/down
Any
integer
between 1
and
65536
Yes 4 Yes 84 84
General
purpose
TIM2,
TIM5 32-bit
Up,
Down,
Up/down
Any
integer
between 1
and
65536
Yes 4 No 42 84
TIM3,
TIM4 16-bit
Up,
Down,
Up/down
Any
integer
between 1
and
65536
Yes 4 No 42 84
TIM9 16-bit Up
Any
integer
between 1
and
65536
No 2 No 84 84
TIM1
0,
TIM11
16-bit Up
Any
integer
between 1
and
65536
No 1 No 84 84
Functional overview STM32F401xD STM32F401xE
28/135 DocID025644 Rev 3
If configured as standard 16-bit timers, it has the same features as the general-purpose
TIMx timers. If configured as a 16-bit PWM generator, it has full modulation capability (0-
100%).
The advanced-control timer can work together with the TIMx timers via the Timer Link
feature for synchronization or event chaining.
TIM1 supports independent DMA request generation.
3.19.2 General-purpose timers (TIMx)
There are seven synchronizable general-purpose timers embedded in the
STM32F401xD/xE (see Table 4 for differences).
TIM2, TIM3, TIM4, TIM5
The STM32F401xD/xE devices are 4 full-featured general-purpose timers: TIM2, TIM5,
TIM3, and TIM4.The TIM2 and TIM5 timers are based on a 32-bit auto-reload
up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16-
bit auto-reload up/downcounter and a 16-bit prescaler. They all feature four
independent channels for input capture/output compare, PWM or one-pulse mode
output. This gives up to 15 input capture/output compare/PWMs.
The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the
other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the
Timer Link feature for synchronization or event chaining.
Any of these general-purpose timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are
capable of handling quadrature (incremental) encoder signals and the digital outputs
from 1 to 4 hall-effect sensors.
TIM9, TIM10 and TIM11
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM10 and TIM11 feature one independent channel, whereas TIM9 has two
independent channels for input capture/output compare, PWM or one-pulse mode
output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured
general-purpose timers. They can also be used as simple time bases.
3.19.3 Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes.
3.19.4 Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
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STM32F401xD STM32F401xE Functional overview
54
3.19.5 SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
downcounter. It features:
A 24-bit downcounter
Autoreload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source.
3.20 Inter-integrated circuit interface (I2C)
Up to three I2C bus interfaces can operate in multimaster and slave modes. They can
support the standard (up to 100 kHz) and fast (up to 400 kHz) modes. The I2C bus
frequency can be increased up to 1 MHz. For more details about the complete solution,
please contact your local ST sales representative.They also support the 7/10-bit addressing
mode and the 7-bit dual addressing mode (as slave). A hardware CRC
generation/verification is embedded.
They can be served by DMA and they support SMBus 2.0/PMBus.
The devices also include programmable analog and digital noise filters (see Table 5).
3.21 Universal synchronous/asynchronous receiver transmitters
(USART)
The devices embed three universal synchronous/asynchronous receiver transmitters
(USART1, USART2 and USART6).
These three interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN Master/Slave capability. The USART1 and USART6 interfaces are able to
communicate at speeds of up to 10.5 Mbit/s. The USART2 interface communicates at up to
5.25 bit/s.
USART1 and USART2 also provide hardware management of the CTS and RTS signals,
Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All
interfaces can be served by the DMA controller.
Table 5. Comparison of I2C analog and digital filters
Analog filter Digital filter
Pulse width of
suppressed spikes 50 ns Programmable length from 1 to 15 I2C peripheral clocks
Functional overview STM32F401xD STM32F401xE
30/135 DocID025644 Rev 3
3.22 Serial peripheral interface (SPI)
The devices feature up to four SPIs in slave and master modes in full-duplex and simplex
communication modes. SPI1 and SPI4 can communicate at up to 42 Mbit/s, SPI2 and SPI3
can communicate at up to 21 Mbit/s. The 3-bit prescaler gives 8 master mode frequencies
and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification
supports basic SD Card/MMC modes. All SPIs can be served by the DMA controller.
The SPI interface can be configured to operate in TI mode for communications in master
mode and slave mode.
3.23 Inter-integrated sound (I2S)
Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available. They can be
operated in master or slave mode, in full duplex and simplex communication modes and
can be configured to operate with a 16-/32-bit resolution as an input or output channel.
Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of
the I2S interfaces is/are configured in master mode, the master clock can be output to the
external DAC/CODEC at 256 times the sampling frequency.
All I2Sx can be served by the DMA controller.
3.24 Audio PLL (PLLI2S)
The devices feature an additional dedicated PLL for audio I2S application. It allows to
achieve error-free I2S sampling clock accuracy without compromising on the CPU
performance.
The PLLI2S configuration can be modified to manage an I2S sample rate change without
disabling the main PLL (PLL) used for the CPU.
The audio PLL can be programmed with very low error to obtain sampling rates ranging
from 8 kHz to 192 kHz.
In addition to the audio PLL, a master clock input pin can be used to synchronize the I2S
flow with an external PLL (or Codec output).
Table 6. USART feature comparison
USART
name
Standard
features
Modem
(RTS/CTS) LIN SPI
master irDA Smartcard
(ISO 7816)
Max. baud
rate in Mbit/s
(oversampling
by 16)
Max. baud
rate in Mbit/s
(oversampling
by 8)
APB
mapping
USART1 X X X X X X 5.25 10.5
APB2
(max.
84 MHz)
USART2 X X X X X X 2.62 5.25
APB1
(max.
42 MHz)
USART6 X N.A X X X X 5.25 10.5
APB2
(max.
84 MHz)
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STM32F401xD STM32F401xE Functional overview
54
3.25 Secure digital input/output interface (SDIO)
An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System
Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.
The interface allows data transfer at up to 48 MHz, and is compliant with the SD Memory
Card Specification Version 2.0.
The SDIO Card Specification Version 2.0 is also supported with two different databus
modes: 1-bit (default) and 4-bit.
The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack
of MMC4.1 or previous.
In addition to SD/SDIO/MMC, this interface is fully compliant with the CE-ATA digital
protocol Rev1.1.
3.26 Universal serial bus on-the-go full-speed (OTG_FS)
The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated
transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and
with the OTG 1.0 specification. It has software-configurable endpoint setting and supports
suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock
that is generated by a PLL connected to the HSE oscillator. The major features are:
Combined Rx and Tx FIFO size of 320 × 35 bits with dynamic FIFO sizing
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
4 bidirectional endpoints
8 host channels with periodic OUT support
HNP/SNP/IP inside (no need for any external resistor)
For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
3.27 General-purpose input/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
The I/O configuration can be locked if needed by following a specific sequence in order to
avoid spurious writing to the I/Os registers.
Fast I/O handling allowing maximum I/O toggling up to 84 MHz.
3.28 Analog-to-digital converter (ADC)
One 12-bit analog-to-digital converter is embedded and shares up to 16 external channels,
performing conversions in the single-shot or scan mode. In scan mode, automatic
conversion is performed on a selected group of analog inputs.
Functional overview STM32F401xD STM32F401xE
32/135 DocID025644 Rev 3
The ADC can be served by the DMA controller. An analog watchdog feature allows very
precise monitoring of the converted voltage of one, some or all selected channels. An
interrupt is generated when the converted voltage is outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1,
TIM2, TIM3, TIM4 or TIM5 timer.
3.29 Temperature sensor
The temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally
connected to the ADC_IN16 input channel which is used to convert the sensor output
voltage into a digital value. Refer to the reference manual for additional information.
As the offset of the temperature sensor varies from chip to chip due to process variation, the
internal temperature sensor is mainly suitable for applications that detect temperature
changes instead of absolute temperatures. If an accurate temperature reading is needed,
then an external temperature sensor part should be used.
3.30 Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could
be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with
SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.
3.31 Embedded Trace Macrocell™
The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the
STM32F401xD/xE through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. The TPA is connected to a host computer using any high-speed
channel available. Real-time instruction and data flow activity can be recorded and then
formatted for display on the host computer that runs the debugger software. TPA hardware
is commercially available from common development tool vendors.
The Embedded Trace Macrocell operates with third party debugger software tools.
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DocID025644 Rev 3 33/135
STM32F401xD STM32F401xE Pinouts and pin description
54
4 Pinouts and pin description
Figure 10. STM32F401xD/xE WLCSP49 pinout
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Pinouts and pin description STM32F401xD STM32F401xE
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Figure 11. STM32F401xD/xE UFQFPN48 pinout
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STM32F401xD STM32F401xE Pinouts and pin description
54
Figure 12. STM32F401xD/xE LQFP64 pinout
1. The above figure shows the package top view.
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Pinouts and pin description STM32F401xD STM32F401xE
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Figure 13. STM32F401xD/xE LQFP100 pinout
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DocID025644 Rev 3 37/135
STM32F401xD STM32F401xE Pinouts and pin description
54
Figure 14. STM32F401xD/xE UFBGA100 pinout
1. This figure shows the package top view
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Pinouts and pin description STM32F401xD STM32F401xE
38/135 DocID025644 Rev 3
Table 7. Legend/abbreviations used in the pinout table
Name Abbreviation Definition
Pin name Unless otherwise specified in brackets below the pin name, the pin function during and after
reset is the same as the actual pin name
Pin type
S Supply pin
I Input only pin
I/O Input/ output pin
I/O structure
FT 5 V tolerant I/O
B Dedicated BOOT0 pin
NRST Bidirectional reset pin with embedded weak pull-up resistor
Notes Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset
Alternate
functions Functions selected through GPIOx_AFR registers
Additional
functions Functions directly selected/enabled through peripheral registers
Table 8. STM32F401xD/xE pin definitions
Pin Number
Pin name
(function
after reset)(1)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
UQFN48
WLCSP49
LQFP64
LQFP100
UFBGA100
- - - 1 B2 PE2 I/O FT - SPI4_SCK, TRACECLK,
EVENTOUT -
- - - 2 A1 PE3 I/O FT - TRACED0, EVENTOUT -
- - - 3 B1 PE4 I/O FT - SPI4_NSS, TRACED1,
EVENTOUT -
- - - 4 C2 PE5 I/O FT - SPI4_MISO, TIM9_CH1,
TRACED2, EVENTOUT -
- - - 5 D2 PE6 I/O FT - SPI4_MOSI, TIM9_CH2,
TRACED3, EVENTOUT -
- - - - D3 VSS S - - - -
----C4 VDD S- - - -
1 B7 1 6 E2 VBAT S - - - -
2 D5 2 7 C1 PC13 I/O FT (2) (3) EVENTOUT, RTC_TAMP1,
RTC_OUT, RTC_TS
DocID025644 Rev 3 39/135
STM32F401xD STM32F401xE Pinouts and pin description
54
3C73 8 D1
PC14-
OSC32_IN
(PC14)
I/O FT
(2) (3)
(4) EVENTOUT OSC32_IN
4C64 9 E1
PC15-
OSC32_OUT
(PC15)
I/O FT
(2) (3)
(4) EVENTOUT OSC32_OUT
- - - 10 F2 VSS S - - - -
---11G2 VDD S- - - -
5D75 12F1PH0-OSC_IN
(PH0) I/O FT (4) EVENTOUT OSC_IN
6D66 13G1
PH1-
OSC_OUT
(PH1)
I/O FT (4) EVENTOUT OSC_OUT
7 E7 7 14 H2 NRST I/O FT - EVENTOUT -
- - 8 15 H1 PC0 I/O FT - EVENTOUT ADC1_IN10
- - 9 16 J2 PC1 I/O FT - EVENTOUT ADC1_IN11
- - 10 17 J3 PC2 I/O FT - SPI2_MISO, I2S2ext_SD,
EVENTOUT ADC1_IN12
- - 11 18 K2 PC3 I/O FT - SPI2_MOSI/I2S2_SD,
EVENTOUT ADC1_IN13
---19- VDD S- - - -
8 E6 12 20 - VSSA/VREF- S - - - -
- - - - J1 VSSA S - - - -
- - - - K1 VREF- S - - - -
9 - 13 - - VDDA/VREF+ S - - - -
---21L1 VREF+ S- - - -
- F7 - 22 M1 VDDA S - - - -
10 F6 14 23 L2 PA0 I/O FT (5)
USART2_CTS,
TIM2_CH1/TIM2_ETR,
TIM5_CH1, EVENTOUT
ADC1_IN0, WKUP
11 G7 15 24 M2 PA1 I/O FT - USART2_RTS, TIM2_CH2,
TIM5_CH2, EVENTOUT ADC1_IN1
12 E5 16 25 K3 PA2 I/O FT -
USART2_TX, TIM2_CH3,
TIM5_CH3, TIM9_CH1,
EVENTOUT
ADC1_IN2
Table 8. STM32F401xD/xE pin definitions (continued)
Pin Number
Pin name
(function
after reset)(1)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
UQFN48
WLCSP49
LQFP64
LQFP100
UFBGA100
Pinouts and pin description STM32F401xD STM32F401xE
40/135 DocID025644 Rev 3
13 E4 17 26 L3 PA3 I/O FT -
USART2_RX, TIM2_CH4,
TIM5_CH4, TIM9_CH2,
EVENTOUT
ADC1_IN3
- - 18 27 - VSS S - - - -
- - 19 28 - VDD S - - - -
----E3BYPASS_
REG IFT - - -
14 G6 20 29 M3 PA4 I/O FT -
SPI1_NSS,
SPI3_NSS/I2S3_WS,
USART2_CK, EVENTOUT
ADC1_IN4
15 F5 21 30 K4 PA5 I/O FT -
SPI1_SCK,
TIM2_CH1/TIM2_ETR,
EVENTOUT
ADC1_IN5
16 F4 22 31 L4 PA6 I/O FT - SPI1_MISO, TIM1_BKIN,
TIM3_CH1, EVENTOUT ADC1_IN6
17 F3 23 32 M4 PA7 I/O FT - SPI1_MOSI, TIM1_CH1N,
TIM3_CH2, EVENTOUT ADC1_IN7
- - 24 33 K5 PC4 I/O FT - EVENTOUT ADC1_IN14
- - 25 34 L5 PC5 I/O FT - EVENTOUT ADC1_IN15
18 G5 26 35 M5 PB0 I/O FT - TIM1_CH2N, TIM3_CH3,
EVENTOUT ADC1_IN8
19 G4 27 36 M6 PB1 I/O FT - TIM1_CH3N, TIM3_CH4,
EVENTOUT ADC1_IN9
20 G3 28 37 L6 PB2 I/O FT - EVENTOUT BOOT1
- - - 38 M7 PE7 I/O FT - TIM1_ETR, EVENTOUT -
- - - 39 L7 PE8 I/O FT - TIM1_CH1N, EVENTOUT -
- - - 40 M8 PE9 I/O FT - TIM1_CH1, EVENTOUT -
- - - 41 L8 PE10 I/O FT - TIM1_CH2N, EVENTOUT -
- - - 42 M9 PE11 I/O FT - SPI4_NSS, TIM1_CH2,
EVENTOUT -
- - - 43 L9 PE12 I/O FT - SPI4_SCK, TIM1_CH3N,
EVENTOUT -
- - - 44 M10 PE13 I/O FT - SPI4_MISO, TIM1_CH3,
EVENTOUT -
Table 8. STM32F401xD/xE pin definitions (continued)
Pin Number
Pin name
(function
after reset)(1)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
UQFN48
WLCSP49
LQFP64
LQFP100
UFBGA100
DocID025644 Rev 3 41/135
STM32F401xD STM32F401xE Pinouts and pin description
54
- - - 45 M11 PE14 I/O FT - SPI4_MOSI, TIM1_CH4,
EVENTOUT -
- - - 46 M12 PE15 I/O FT - TIM1_BKIN, EVENTOUT -
21 E3 29 47 L10 PB10 I/O FT -
SPI2_SCK/I2S2_CK,
I2C2_SCL, TIM2_CH3,
EVENTOUT
-
- - - - K9 PB11 I/O FT - EVENTOUT -
22 G2 30 48 L11 VCAP1 S - - - -
23 D3 31 49 F12 VSS S - - - -
24 F2 32 50 G12 VDD S - - - -
25 E2 33 51 L12 PB12 I/O FT -
SPI2_NSS/I2S2_WS,
I2C2_SMBA, TIM1_BKIN,
EVENTOUT
-
26 G1 34 52 K12 PB13 I/O FT - SPI2_SCK/I2S2_CK,
TIM1_CH1N, EVENTOUT -
27 F1 35 53 K11 PB14 I/O FT - SPI2_MISO, I2S2ext_SD,
TIM1_CH2N, EVENTOUT -
28 E1 36 54 K10 PB15 I/O FT - SPI2_MOSI/I2S2_SD,
TIM1_CH3N, EVENTOUT RTC_REFIN
- - - 55 - PD8 I/O FT - EVENTOUT -
- - - 56 K8 PD9 I/O FT - EVENTOUT -
- - - 57 J12 PD10 I/O FT - EVENTOUT -
- - - 58 J11 PD11 I/O FT - EVENTOUT -
- - - 59 J10 PD12 I/O FT - TIM4_CH1, EVENTOUT -
- - - 60 H12 PD13 I/O FT - TIM4_CH2, EVENTOUT -
- - - 61 H11 PD14 I/O FT - TIM4_CH3, EVENTOUT -
- - - 62 H10 PD15 I/O FT - TIM4_CH4, EVENTOUT -
- - 37 63 E12 PC6 I/O FT -
I2S2_MCK, USART6_TX,
TIM3_CH1, SDIO_D6,
EVENTOUT
-
- - 38 64 E11 PC7 I/O FT -
I2S3_MCK, USART6_RX,
TIM3_CH2, SDIO_D7,
EVENTOUT
-
Table 8. STM32F401xD/xE pin definitions (continued)
Pin Number
Pin name
(function
after reset)(1)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
UQFN48
WLCSP49
LQFP64
LQFP100
UFBGA100
Pinouts and pin description STM32F401xD STM32F401xE
42/135 DocID025644 Rev 3
- - 39 65 E10 PC8 I/O FT - USART6_CK, TIM3_CH3,
SDIO_D0, EVENTOUT -
- - 40 66 D12 PC9 I/O FT -
I2S_CKIN, I2C3_SDA,
TIM3_CH4, SDIO_D1,
MCO_2, EVENTOUT
-
29 D1 41 67 D11 PA8 I/O FT -
I2C3_SCL, USART1_CK,
TIM1_CH1, OTG_FS_SOF,
MCO_1, EVENTOUT
-
30 D2 42 68 D10 PA9 I/O FT - I2C3_SMBA, USART1_TX,
TIM1_CH2, EVENTOUT OTG_FS_VBUS
31 C2 43 69 C12 PA10 I/O FT - USART1_RX, TIM1_CH3,
OTG_FS_ID, EVENTOUT -
32 C1 44 70 B12 PA11 I/O FT -
USART1_CTS, USART6_TX,
TIM1_CH4, OTG_FS_DM,
EVENTOUT
-
33 C3 45 71 A12 PA12 I/O FT -
USART1_RTS, USART6_RX,
TIM1_ETR, OTG_FS_DP,
EVENTOUT
-
34 B3 46 72 A11 PA13 (JTMS-
SWDIO) I/O FT - JTMS-SWDIO, EVENTOUT -
---73C11 VCAP2 S- - - -
35 B1 47 74 F11 VSS S - - - -
36 - 48 75 G11 VDD S - - - -
-B2- - - VDD S - - - -
37 A1 49 76 A10 PA14 (JTCK-
SWCLK) I/O FT - JTCK-SWCLK, EVENTOUT -
38 A2 50 77 A9 PA15 (JTDI) I/O FT -
JTDI, SPI1_NSS,
SPI3_NSS/I2S3_WS,
TIM2_CH1/TIM2_ETR, JTDI,
EVENTOUT
-
- - 51 78 B11 PC10 I/O FT - SPI3_SCK/I2S3_CK,
SDIO_D2, EVENTOUT -
- - 52 79 C10 PC11 I/O FT - I2S3ext_SD, SPI3_MISO,
SDIO_D3, EVENTOUT -
- - 53 80 B10 PC12 I/O FT - SPI3_MOSI/I2S3_SD,
SDIO_CK, EVENTOUT -
- - - 81 C9 PD0 I/O FT - EVENTOUT -
Table 8. STM32F401xD/xE pin definitions (continued)
Pin Number
Pin name
(function
after reset)(1)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
UQFN48
WLCSP49
LQFP64
LQFP100
UFBGA100
DocID025644 Rev 3 43/135
STM32F401xD STM32F401xE Pinouts and pin description
54
- - - 82 B9 PD1 I/O FT - EVENTOUT -
- - 54 83 C8 PD2 I/O FT - TIM3_ETR, SDIO_CMD,
EVENTOUT -
- - - 84 B8 PD3 I/O FT - SPI2_SCK/I2S2_CK,
USART2_CTS, EVENTOUT -
- - - 85 B7 PD4 I/O FT - USART2_RTS, EVENTOUT -
- - - 86 A6 PD5 I/O FT - USART2_TX, EVENTOUT -
- - - 87 B6 PD6 I/O FT - SPI3_MOSI/I2S3_SD,
USART2_RX, EVENTOUT -
- - - 88 A5 PD7 I/O FT - USART2_CK, EVENTOUT -
39 A3 55 89 A8 PB3
(JTDO-SWO) I/O FT -
JTDO-SWO, SPI1_SCK,
SPI3_SCK/I2S3_CK,
I2C2_SDA, TIM2_CH2,
EVENTOUT
-
40 A4 56 90 A7 PB4
(NJTRST) I/O FT -
NJTRST, SPI1_MISO,
SPI3_MISO, I2S3ext_SD,
I2C3_SDA, TIM3_CH1,
EVENTOUT
-
41 B4 57 91 C5 PB5 I/O FT -
SPI1_MOSI,
SPI3_MOSI/I2S3_SD,
I2C1_SMBA, TIM3_CH2,
EVENTOUT
-
42 C4 58 92 B5 PB6 I/O FT - I2C1_SCL, USART1_TX,
TIM4_CH1, EVENTOUT -
43 D4 59 93 B4 PB7 I/O FT - I2C1_SDA, USART1_RX,
TIM4_CH2, EVENTOUT -
44 A5 60 94 A4 BOOT0 I B - - VPP
45 B5 61 95 A3 PB8 I/O FT -
I2C1_SCL, TIM4_CH3,
TIM10_CH1, SDIO_D4,
EVENTOUT
-
46 C5 62 96 B3 PB9 I/O FT -
SPI2_NSS/I2S2_WS,
I2C1_SDA, TIM4_CH4,
TIM11_CH1, SDIO_D5,
EVENTOUT
-
- - - 97 C3 PE0 I/O FT - TIM4_ETR, EVENTOUT -
- - - 98 A2 PE1 I/O FT - EVENTOUT -
Table 8. STM32F401xD/xE pin definitions (continued)
Pin Number
Pin name
(function
after reset)(1)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
UQFN48
WLCSP49
LQFP64
LQFP100
UFBGA100
Pinouts and pin description STM32F401xD STM32F401xE
44/135 DocID025644 Rev 3
47 A6 63 99 - VSS S - - - -
- B6 - - H3 PDR_ON I FT - - -
48 A7 64 100 - VDD S - - - -
1. Function availability depends on the chosen device.
2. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3
mA), the use of GPIOs PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF.
- These I/Os must not be used as a current source (e.g. to drive an LED).
3. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after
reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC
register description sections in the STM32F401xx reference manual.
4. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).
5. If the device is delivered in an UFBGA100 and the BYPASS_REG pin is set to VDD (Regulator off/internal reset ON mode),
then PA0 is used as an internal Reset (active low)
Table 8. STM32F401xD/xE pin definitions (continued)
Pin Number
Pin name
(function
after reset)(1)
Pin type
I/O structure
Notes
Alternate functions Additional
functions
UQFN48
WLCSP49
LQFP64
LQFP100
UFBGA100
(En
Pinouts and pin description STM32F401xD STM32F401xE
45/135 DocID025644 Rev 3
Table 9. Alternate function mapping
Port
AF00 AF01 AF02 AF03 AF04 AF05 AF06 AF07 AF08 AF09 AF10 AF11 AF12 AF13 AF14 AF15
SYS_AF TIM1/TIM2 TIM3/
TIM4/ TIM5
TIM9/
TIM10/
TIM11
I2C1/I2C2/
I2C3
SPI1/SPI2/
I2S2/SPI3/
I2S3/SPI4
SPI2/I2S2/
SPI3/ I2S3
SPI3/I2S3/
USART1/
USART2
USART6 I2C2/
I2C3 OTG1_FS SDIO
Port A
PA0 - TIM2_CH1/
TIM2_ETR TIM5_CH1 - - - - USART2_
CTS -- -----
EVENT
OUT
PA1 - TIM2_CH2 TIM5_CH2 - - - - USART2_
RTS -- -----
EVENT
OUT
PA2 - TIM2_CH3 TIM5_CH3 TIM9_CH1 - - - USART2_
TX -- -----
EVENT
OUT
PA3 - TIM2_CH4 TIM5_CH4 TIM9_CH2 - - USART2_
RX -- -----
EVENT
OUT
PA4 - - - - - SPI1_NSS SPI3_NSS/
I2S3_WS
USART2_
CK -- -----
EVENT
OUT
PA5 - TIM2_CH1/
TIM2_ETR ---SPI1_SCK- --------
EVENT
OUT
PA6 - TIM1_BKIN TIM3_CH1 - - SPI1_
MISO ---------
EVENT
OUT
PA7 - TIM1_CH1N TIM3_CH2 - - SPI1_
MOSI ------
- - - EVENT
OUT
PA8 MCO_1 TIM1_CH1 - - I2C3_SCL - - USART1_
CK --
OTG_FS_
SOF -- - - EVENT
OUT
PA9 - TIM1_CH2 - - I2C3_
SMBA --
USART1_
TX --
OTG_FS_
VBUS -----
EVENT
OUT
PA10 - TIM1_CH3 - - - - - USART1_
RX --
OTG_FS_I
D----
EVENT
OUT
PA11 - TIM1_CH4 - - - - - USART1_
CTS
USART6_
TX -OTG_FS_
DM ----
EVENT
OUT
PA12 - TIM1_ETR - - - - - USART1_
RTS
USART6_
RX -OTG_FS_
DP ----
EVENT
OUT
PA13 JTMS_
SWDIO ----- - --------
EVENT
OUT
PA14 JTCK_
SWCLK ----- - --------
EVENT
OUT
PA15 JTDI TIM2_CH1/
TIM2_ETR ---SPI1_NSS
SPI3_NSS/
I2S3_WS --- -----
EVENT
OUT
m En
STM32F401xD STM32F401xE Pinouts and pin description
DocID025644 Rev 3 46/135
Port B
PB0 - TIM1_CH2N TIM3_CH3 - - - - - - - - - - - - EVENT
OUT
PB1 - TIM1_CH3N TIM3_CH4 - - - - - - - - - - - - EVENT
OUT
PB2 - - - - - - - - - - - - - - - EVENT
OUT
PB3 JTDO-
SWO TIM2_CH2 - - - SPI1_SCK SPI3_SCK/
I2S3_CK - - I2C2_SDA - - - - - EVENT
OUT
PB4 JTRST - TIM3_CH1 - - SPI1_
MISO SPI3_MISO I2S3ext_S
D-I2C3_SDA - - - --
EVENT
OUT
PB5 - - TIM3_CH2 - I2C1_
SMBA
SPI1
_MOSI
SPI3_MOSI/
I2S3_SD --- -----
EVENT
OUT
PB6 - - TIM4_CH1 - I2C1_SCL - - USART1_
TX -- -----
EVENT
OUT
PB7 - - TIM4_CH2 - I2C1_SDA - - USART1_
RX -- -----
EVENT
OUT
PB8 - - TIM4_CH3 TIM10_CH1 I2C1_SCL - - - - - - - SDIO_
D4 --
EVENT
OUT
PB9 - - TIM4_CH4 TIM11_CH1 I2C1_SDA SPI2_NSS/I
2S2_WS ------
SDIO_
D5 --
EVENT
OUT
PB10 - TIM2_CH3 - - I2C2_SCL SPI2_SCK/I
2S2_CK ---------
EVENT
OUT
PB12 - TIM1_BKIN - - I2C2_
SMBA
SPI2_NSS/I
2S2_WS ---------
EVENT
OUT
PB13 - TIM1_CH1N - - - SPI2_SCK/I
2S2_CK ---------
EVENT
OUT
PB14 - TIM1_CH2N - - - SPI2_MISO I2S2ext_SD - - - - - - - - EVENT
OUT
PB15 RTC_
REFN TIM1_CH3N - - - SPI2_MOSI
/I2S2_SD ---------
EVENT
OUT
Table 9. Alternate function mapping (continued)
Port
AF00 AF01 AF02 AF03 AF04 AF05 AF06 AF07 AF08 AF09 AF10 AF11 AF12 AF13 AF14 AF15
SYS_AF TIM1/TIM2 TIM3/
TIM4/ TIM5
TIM9/
TIM10/
TIM11
I2C1/I2C2/
I2C3
SPI1/SPI2/
I2S2/SPI3/
I2S3/SPI4
SPI2/I2S2/
SPI3/ I2S3
SPI3/I2S3/
USART1/
USART2
USART6 I2C2/
I2C3 OTG1_FS SDIO
0 En
Pinouts and pin description STM32F401xD STM32F401xE
47/135 DocID025644 Rev 3
Port C
PC0 - - - - - - - - - - - - - - - EVENT
OUT
PC1 - - - - - - - - - - - - - - - EVENT
OUT
PC2 - - - - - SPI2_
MISO I2S2ext_SD - - - - - - - - EVENT
OUT
PC3 - - - - - SPI2_MOSI
/I2S2_SD ---------
EVENT
OUT
PC4 - - - - - - - - - - - - - - - EVENT
OUT
PC5 - - - - - - - - - - - - - - - EVENT
OUT
PC6 - -- TIM3_CH1 - - I2S2_MCK - - USART6_
TX ---
SDIO_
D6 --
EVENT
OUT
PC7 - TIM3_CH2 - - - I2S3_MCK - USART6_
RX ---
SDIO_
D7 --
EVENT
OUT
PC8 - - TIM3_CH3 - - - - - USART6_
CK ---
SDIO_
D0 --
EVENT
OUT
PC9 MCO_2 - TIM3_CH4 - I2C3_SDA I2S_CKIN - - - - - - SDIO_
D1 --
EVENT
OUT
PC10 - - - - - - SPI3_SCK/
I2S3_CK --- --
SDIO_
D2 --
EVENT
OUT
PC11 - - - - - I2S3ext_
SD SPI3_MISO - - - - - SDIO_
D3 --
EVENT
OUT
PC12 - - - - - - SPI3_MOSI/
I2S3_SD --- --
SDIO_
CK --
EVENT
OUT
PC13 - - - - - - - - - - - - - - - EVENT
OUT
PC14 - - - - - - - - - - - - - - - EVENT
OUT
PC15 - - - - - - - - - - - - - - - EVENT
OUT
Table 9. Alternate function mapping (continued)
Port
AF00 AF01 AF02 AF03 AF04 AF05 AF06 AF07 AF08 AF09 AF10 AF11 AF12 AF13 AF14 AF15
SYS_AF TIM1/TIM2 TIM3/
TIM4/ TIM5
TIM9/
TIM10/
TIM11
I2C1/I2C2/
I2C3
SPI1/SPI2/
I2S2/SPI3/
I2S3/SPI4
SPI2/I2S2/
SPI3/ I2S3
SPI3/I2S3/
USART1/
USART2
USART6 I2C2/
I2C3 OTG1_FS SDIO
0 En
STM32F401xD STM32F401xE Pinouts and pin description
DocID025644 Rev 3 48/135
Port D
PD0 - - - - - - - - - - - - - - - EVENT
OUT
PD1 - - - - - - - - - - - - - - - EVENT
OUT
PD2 - - TIM3_ETR - - - - - - - - - SDIO_
CMD --
EVENT
OUT
PD3 - - - - - SPI2_SCK/
I2S2_CK -USART2_
CTS -- - - - - - - EVENT
OUT
PD4 - - - - - - - USART2_
RTS ------
EVENT
OUT
PD5 - - - - - - - USART2_
TX -- -----
EVENT
OUT
PD6 - - - - - SPI3_MOSI
/I2S3_SD -USART2_
RX -- -----
EVENT
OUT
PD7 - - - - - - - USART2_
CK -- -----
EVENT
OUT
PD8 - - - - - - - - - - - - - - - EVENT
OUT
PD9 - - - - - - - - - - - - - - - EVENT
OUT
PD10 - - - - - - - - - - - - - - - EVENT
OUT
PD11 - - - - - - - - - - - - - - - EVENT
OUT
PD12 - - TIM4_CH1 - - - - - - - - - - - - EVENT
OUT
PD13 - - TIM4_CH2 - - - - - - - - - - - - EVENT
OUT
PD14 - - TIM4_CH3 - - - - - - - - - - - - EVENT
OUT
PD15 - - TIM4_CH4 - - - - - - - - - - - - EVENT
OUT
Table 9. Alternate function mapping (continued)
Port
AF00 AF01 AF02 AF03 AF04 AF05 AF06 AF07 AF08 AF09 AF10 AF11 AF12 AF13 AF14 AF15
SYS_AF TIM1/TIM2 TIM3/
TIM4/ TIM5
TIM9/
TIM10/
TIM11
I2C1/I2C2/
I2C3
SPI1/SPI2/
I2S2/SPI3/
I2S3/SPI4
SPI2/I2S2/
SPI3/ I2S3
SPI3/I2S3/
USART1/
USART2
USART6 I2C2/
I2C3 OTG1_FS SDIO
“En
Pinouts and pin description STM32F401xD STM32F401xE
49/135 DocID025644 Rev 3
Port E
PE0 - - TIM4_ETR - - - - - - - - - - - - EVENT
OUT
PE1 - TIM1_CH2N - - - - - - - - - - - - - EVENT
OUT
PE2 TRACECL
K----SPI4_SCK- --------
EVENT
OUT
PE3 TRACED0 - - - - - - - - - - - - - - EVENT
OUT
PE4 TRACED1 - - - - SPI4_NSS - - - - - - - - - EVENT
OUT
PE5 TRACED2 - - TIM9_CH1 - SPI4_MISO - - - - - - - - - EVENT
OUT
PE6 TRACED3 - - TIM9_CH2 - SPI4_MOSI - - - - - - - - - EVENT
OUT
PE7 - TIM1_ETR - - - - - - - - - - - - - EVENT
OUT
PE8 - TIM1_CH1N - - - - - - - - - - - - - EVENT
OUT
PE9 - TIM1_CH1 - - - - - - - - - - - - - EVENT
OUT
PE10 - TIM1_CH2N - - - - - - - - - - - - - EVENT
OUT
PE11 - TIM1_CH2 - - - SPI4_NSS - - - - - - - - - EVENT
OUT
PE12 - TIM1_CH3N - - - SPI4_SCK - - - - - - - - - EVENT
OUT
PE13 - TIM1_CH3 - - - SPI4_MISO - - - - - - - - - EVENT
OUT
PE14 - TIM1_CH4 - - - SPI4_MOSI - - - - - - - - - EVENT
OUT
PE15 - TIM1_BKIN - - - - - - - - - - - - - EVENT
OUT
Table 9. Alternate function mapping (continued)
Port
AF00 AF01 AF02 AF03 AF04 AF05 AF06 AF07 AF08 AF09 AF10 AF11 AF12 AF13 AF14 AF15
SYS_AF TIM1/TIM2 TIM3/
TIM4/ TIM5
TIM9/
TIM10/
TIM11
I2C1/I2C2/
I2C3
SPI1/SPI2/
I2S2/SPI3/
I2S3/SPI4
SPI2/I2S2/
SPI3/ I2S3
SPI3/I2S3/
USART1/
USART2
USART6 I2C2/
I2C3 OTG1_FS SDIO
1 En
STM32F401xD STM32F401xE Pinouts and pin description
DocID025644 Rev 3 50/135
Port H
PH0 - - - - - - - - - - - - - - - EVENT
OUT
PH1 - - - - - - - - - - - - - - - EVENT
OUT
Table 9. Alternate function mapping (continued)
Port
AF00 AF01 AF02 AF03 AF04 AF05 AF06 AF07 AF08 AF09 AF10 AF11 AF12 AF13 AF14 AF15
SYS_AF TIM1/TIM2 TIM3/
TIM4/ TIM5
TIM9/
TIM10/
TIM11
I2C1/I2C2/
I2C3
SPI1/SPI2/
I2S2/SPI3/
I2S3/SPI4
SPI2/I2S2/
SPI3/ I2S3
SPI3/I2S3/
USART1/
USART2
USART6 I2C2/
I2C3 OTG1_FS SDIO
DocID025644 Rev 3 51/135
STM32F401xD STM32F401xE Memory mapping
54
5 Memory mapping
The memory map is shown in Figure 15.
Figure 15. Memory map
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Memory mapping STM32F401xD STM32F401xE
52/135 DocID025644 Rev 3
Table 10. STM32F401xD register boundary addresses
Bus Boundary address Peripheral
0xE010 0000 - 0xFFFF FFFF Reserved
Cortex®-M4 0xE000 0000 - 0xE00F FFFF Cortex-M4 internal peripherals
0x5004 0000 - 0xDFFF FFFF Reserved
AHB2 0x5000 0000 - 0x5003 FFFF USB OTG FS
AHB1
0x4002 6800 - 0x4FFF FFFF Reserved
0x4002 6400 - 0x4002 67FF DMA2
0x4002 6000 - 0x4002 63FF DMA1
0x4002 5000 - 0x4002 4FFF Reserved
0x4002 3C00 - 0x4002 3FFF Flash interface register
0x4002 3800 - 0x4002 3BFF RCC
0x4002 3400 - 0x4002 37FF Reserved
0x4002 3000 - 0x4002 33FF CRC
0x4002 2000 - 0x4002 2FFF Reserved
0x4002 1C00 - 0x4002 1FFF GPIOH
0x4002 1400 - 0x4002 1BFF Reserved
0x4002 1000 - 0x4002 13FF GPIOE
0x4002 0C00 - 0x4002 0FFF GPIOD
0x4002 0800 - 0x4002 0BFF GPIOC
0x4002 0400 - 0x4002 07FF GPIOB
0x4002 0000 - 0x4002 03FF GPIOA
DocID025644 Rev 3 53/135
STM32F401xD STM32F401xE Memory mapping
54
APB2
0x4001 4C00- 0x4001 FFFF Reserved
0x4001 4800 - 0x4001 4BFF TIM11
0x4001 4400 - 0x4001 47FF TIM10
0x4001 4000 - 0x4001 43FF TIM9
0x4001 3C00 - 0x4001 3FFF EXTI
0x4001 3800 - 0x4001 3BFF SYSCFG
0x4001 3400 - 0x4001 37FF SPI4/I2S4
0x4001 3000 - 0x4001 33FF SPI1
0x4001 2C00 - 0x4001 2FFF SDIO
0x4001 2400 - 0x4001 2BFF Reserved
0x4001 2000 - 0x4001 23FF ADC1
0x4001 1800 - 0x4001 1FFF Reserved
0x4001 1400 - 0x4001 17FF USART6
0x4001 1000 - 0x4001 13FF USART1
0x4001 0800 - 0x4001 0FFF Reserved
0x4001 0400 - 0x4001 07FF TIM8
0x4001 0000 - 0x4001 03FF TIM1
0x4000 7400 - 0x4000 FFFF Reserved
Table 10. STM32F401xD register boundary addresses (continued)
Bus Boundary address Peripheral
Memory mapping STM32F401xD STM32F401xE
54/135 DocID025644 Rev 3
APB1
0x4000 7000 - 0x4000 73FF PWR
0x4000 6000 - 0x4000 6FFF Reserved
0x4000 5C00 - 0x4000 5FFF I2C3
0x4000 5800 - 0x4000 5BFF I2C2
0x4000 5400 - 0x4000 57FF I2C1
0x4000 4800 - 0x4000 53FF Reserved
0x4000 4400 - 0x4000 47FF USART2
0x4000 4000 - 0x4000 43FF I2S3ext
0x4000 3C00 - 0x4000 3FFF SPI3 / I2S3
0x4000 3800 - 0x4000 3BFF SPI2 / I2S2
0x4000 3400 - 0x4000 37FF I2S2ext
0x4000 3000 - 0x4000 33FF IWDG
0x4000 2C00 - 0x4000 2FFF WWDG
0x4000 2800 - 0x4000 2BFF RTC & BKP Registers
0x4000 1000 - 0x4000 27FF Reserved
0x4000 0C00 - 0x4000 0FFF TIM5
0x4000 0800 - 0x4000 0BFF TIM4
0x4000 0400 - 0x4000 07FF TIM3
0x4000 0000 - 0x4000 03FF TIM2
Table 10. STM32F401xD register boundary addresses (continued)
Bus Boundary address Peripheral
firm
DocID025644 Rev 3 55/135
STM32F401xD STM32F401xE Electrical characteristics
114
6 Electrical characteristics
6.1 Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
6.1.1 Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3 σ).
6.1.2 Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the
1.7 V VDD 3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ±2 σ).
6.1.3 Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4 Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 16.
Figure 16. Pin loading conditions
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Electrical characteristics STM32F401xD STM32F401xE
56/135
6.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 17.
Figure 17. Input voltage measurement
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6).
VBAT , aim ,m>3 T U
DocID025644 Rev 3 57/135
STM32F401xD STM32F401xE Electrical characteristics
114
6.1.6 Power supply scheme
Figure 18. Power supply scheme
1. To connect PDR_ON pin, refer to Section 3.14: Power supply supervisor.
2. The 4.7 µF ceramic capacitor must be connected to one of the VDD pin.
3. VCAP_2 pad is only available on LQFP100 and UFBGA100 packages.
4. VDDA=VDD and VSSA=VSS.
Caution: Each power supply pair (VDD/VSS, VDDA/VSSA ...) must be decoupled with filtering ceramic
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure good operation of the
device. It is not recommended to remove filtering capacitors to reduce PCB size or cost.
This might cause incorrect operation of the device.
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Electrical characteristics STM32F401xD STM32F401xE
58/135
6.1.7 Current consumption measurement
Figure 19. Current consumption measurement scheme
6.2 Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 11: Voltage characteristics,
Table 12: Current characteristics, and Table 13: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
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Table 11. Voltage characteristics
Symbol Ratings Min Max Unit
VDD–VSS
External main supply voltage (including VDDA, VDD and
VBAT)(1)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
–0.3 4.0
V
VIN
Input voltage on FT pins(2)
2. VIN maximum value must always be respected. Refer to Table 12 for the values of the maximum allowed
injected current.
VSS–0.3 VDD+4.0
Input voltage on any other pin VSS–0.3 4.0
Input voltage for BOOT0 VSS 9.0
|ΔVDDx| Variations between different VDD power pins - 50
mV
|VSSX VSS| Variations between all the different ground pins - 50
VESD(HBM) Electrostatic discharge voltage (human body model)
see Section 6.3.14:
Absolute maximum
ratings (electrical
sensitivity)
DocID025644 Rev 3 59/135
STM32F401xD STM32F401xE Electrical characteristics
114
Table 12. Current characteristics
Symbol Ratings Max. Unit
ΣIVDD Total current into sum of all VDD_x power lines (source)(1) 160
mA
Σ IVSS Total current out of sum of all VSS_x ground lines (sink)(1) -160
IVDD Maximum current into each VDD_x power line (source)(1) 100
IVSS Maximum current out of each VSS_x ground line (sink)(1) -100
IIO
Output current sunk by any I/O and control pin 25
Output current sourced by any I/O and control pin -25
ΣIIO
Total output current sunk by sum of all I/O and control pins (2) 120
Total output current sourced by sum of all I/Os and control pins(2) -120
IINJ(PIN) (3) Injected current on FT pins (4)
–5/+0
Injected current on NRST and B pins (4)
ΣIINJ(PIN) Total injected current (sum of all I/O and control pins)(5) ±25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.
3. Negative injection disturbs the analog performance of the device. See note in Section 6.3.20: 12-bit ADC characteristics.
4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum
value.
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and
negative injected currents (instantaneous values).
Table 13. Thermal characteristics
Symbol Ratings Value Unit
TSTG Storage temperature range –65 to +150
°C
TJMaximum junction temperature 125
TLEAD
Maximum lead temperature during soldering
(WLCSP49, LQFP64/100, UFQFPN48,
UFBGA100)
see note (1)
1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (ROHS
directive 2011/65/EU, July 2011).
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6.3 Operating conditions
6.3.1 General operating conditions
Table 14. General operating conditions
Symbol Parameter Conditions Min Typ Max Unit
fHCLK Internal AHB clock frequency
Power Scale3: Regulator ON,
VOS[1:0] bits in PWR_CR register = 0x01 0-60
MHz
Power Scale2: Regulator ON,
VOS[1:0] bits in PWR_CR register = 0x10 0 - 84
fPCLK1 Internal APB1 clock frequency 0 - 42
fPCLK2 Internal APB2 clock frequency 0 - 84
VDD Standard operating voltage 1.7(1) -3.6
V
VDDA
(2)(3)
Analog operating voltage
(ADC limited to 1.2 M samples)
Must be the same potential as VDD(4)
1.7(1) -2.4
Analog operating voltage
(ADC limited to 2.4 M samples) 2.4 - 3.6
VBAT Backup operating voltage 1.65 - 3.6
V12
Regulator ON: 1.2 V internal
voltage on VCAP_1/VCAP_2 pins
VOS[1:0] bits in PWR_CR register = 0x01
Max frequency 60 MHz 1.08(5) 1.14 1.20(5)
VOS[1:0] bits in PWR_CR register = 0x10
Max frequency 84 MHz 1.20(5) 1.26 1.32(5)
V12
Regulator OFF: 1.2 V external
voltage must be supplied on
VCAP_1/VCAP_2 pins
Max. frequency 60 MHz. 1.1 1.14 1.2
Max. frequency 84 MHz. 1.2 1.26 1.32
VIN
Input voltage on RST and FT
pins(6)
2 V VDD 3.6 V –0.3 - 5.5
VDD 2 V –0.3 - 5.2
Input voltage on BOOT0 pin 0 - 9
PD
Maximum allowed package
power dissipation for suffix 7(7)
UFQFPN48 - - 625
mW
WLCSP49 - - 392
LQFP64 - - 313
LQFP100 - - 465
UFBGA100 - - 323
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STM32F401xD STM32F401xE Electrical characteristics
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TA
Ambient temperature for 6
suffix version
Maximum power dissipation –40 - 85
°C
Low power dissipation(8) –40 - 105
Ambient temperature for 7
suffix version
Maximum power dissipation –40 - 105
Low power dissipation(8) –40 - 125
TJ Junction temperature range
6 suffix version –40 - 105
7 suffix version –40 - 125
1. VDD/VDDA minimum value of 1.7 V with the use of an external power supply supervisor (refer to Section 3.14.2: Internal
reset OFF).
2. When the ADC is used, refer to Table 66: ADC characteristics.
3. If VREF+ pin is present, it must respect the following condition: VDDA-VREF+ < 1.2 V.
4. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA
can be tolerated during power-up and power-down operation.
5. Guaranteed by test in production
6. To sustain a voltage higher than VDD+0.3, the internal Pull-up and Pull-Down resistors must be disabled
7. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax.
8. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax.
Table 14. General operating conditions (continued)
Symbol Parameter Conditions Min Typ Max Unit
Table 15. Features depending on the operating power supply range
Operating
power
supply
range
ADC
operation
Maximum
Flash
memory
access
frequency
with no wait
states
(fFlashmax)
Maximum Flash
memory access
frequency with
wait states (1)(2)
I/O operation
Clock output
frequency on
I/O pins(3)
Possible
Flash
memory
operations
VDD =1.7 to
2.1 V(4)
Conversion
time up to
1.2 Msps
20 MHz(5) 84 MHz with 4
wait states
No I/O
compensation up to 30 MHz
8-bit erase
and program
operations
only
VDD = 2.1 to
2.4 V
Conversion
time up to
1.2 Msps
22 MHz 84 MHz with 3
wait states
No I/O
compensation up to 30 MHz
16-bit erase
and program
operations
VDD = 2.4 to
2.7 V
Conversion
time up to
2.4 Msps
24 MHz 84 MHz with 3
wait states
I/O
compensation
works
up to 48 MHz
16-bit erase
and program
operations
VDD = 2.7 to
3.6 V(6)
Conversion
time up to
2.4 Msps
30 MHz 84 MHz with 2
wait states
I/O
compensation
works
–up to
84 MHz
when VDD =
3.0 to 3.6 V
–up to
48 MHz
when VDD =
2.7 to 3.0 V
32-bit erase
and program
operations
EXT
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6.3.2 VCAP1/VCAP2 external capacitors
Stabilization for the main regulator is achieved by connecting external capacitor CEXT to the
VCAP1 and VCAP2 pin. For packages supporting only 1 VCAP pin, the 2 CEXT capacitors
are replaced by a single capacitor.
CEXT is specified in Table 16.
Figure 20. External capacitor CEXT
1. Legend: ESR is the equivalent series resistance.
1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is
required.
2. Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here does not impact the
execution speed from Flash memory since the ART accelerator allows to achieve a performance equivalent to 0 wait state
program execution.
3. Refer to for frequencies vs. external load.
4. VDD/VDDA minimum value of 1.7 V, with the use of an external power supply supervisor (refer to Section 3.14.2: Internal
reset OFF).
5. Prefetch is not available. Refer to AN3430 application note for details on how to adjust performance and power.
6. The voltage range for the USB full speed embedded PHY can drop down to 2.7 V. However the electrical characteristics of
D- and D+ pins will be degraded between 2.7 and 3 V.
Table 16. VCAP1/VCAP2 operating conditions(1)
1. When bypassing the voltage regulator, the two 2.2 µF VCAP capacitors are not required and should be
replaced by two 100 nF decoupling capacitors.
Symbol Parameter Conditions
CEXT Capacitance of external capacitor with available
VCAP1 and VCAP2 pins 2.2 µF
ESR ESR of external capacitor with available VCAP1 and
VCAP2 pins < 2 Ω
CEXT Capacitance of external capacitor with a single VCAP
pin available 4.7 µF
ESR ESR of external capacitor with a single VCAP pin
available < 1 Ω
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6.3.3 Operating conditions at power-up/power-down (regulator ON)
Subject to general operating conditions for TA.
Table 17. Operating conditions at power-up / power-down (regulator ON)
6.3.4 Operating conditions at power-up / power-down (regulator OFF)
Subject to general operating conditions for TA.
Note: This feature is only available for UFBGA100 package.
Symbol Parameter Min Max Unit
tVDD
VDD rise time rate 20
µs/V
VDD fall time rate 20
Table 18. Operating conditions at power-up / power-down (regulator OFF)(1)
1. To reset the internal logic at power-down, a reset must be applied on pin PA0 when VDD reach below
1.08 V.
Symbol Parameter Conditions Min Max Unit
tVDD
VDD rise time rate Power-up 20
µs/V
VDD fall time rate Power-down 20
tVCAP
VCAP_1 and VCAP_2 rise time rate Power-up 20
VCAP_1 and VCAP_2 fall time rate Power-down 20
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6.3.5 Embedded reset and power control block characteristics
The parameters given in Table 19 are derived from tests performed under ambient
temperature and VDD supply voltage @ 3.3V.
Table 19. Embedded reset and power control block characteristics
Symbol Parameter Conditions Min Typ Max Unit
VPVD
Programmable voltage
detector level selection
PLS[2:0]=000 (rising edge) 2.09 2.14 2.19
V
PLS[2:0]=000 (falling edge) 1.98 2.04 2.08
PLS[2:0]=001 (rising edge) 2.23 2.30 2.37
PLS[2:0]=001 (falling edge) 2.13 2.19 2.25
PLS[2:0]=010 (rising edge) 2.39 2.45 2.51
PLS[2:0]=010 (falling edge) 2.29 2.35 2.39
PLS[2:0]=011 (rising edge) 2.54 2.60 2.65
PLS[2:0]=011 (falling edge) 2.44 2.51 2.56
PLS[2:0]=100 (rising edge) 2.70 2.76 2.82
PLS[2:0]=100 (falling edge) 2.59 2.66 2.71
PLS[2:0]=101 (rising edge) 2.86 2.93 2.99
PLS[2:0]=101 (falling edge) 2.65 2.84 3.02
PLS[2:0]=110 (rising edge) 2.96 3.03 3.10
PLS[2:0]=110 (falling edge) 2.85 2.93 2.99
PLS[2:0]=111 (rising edge) 3.07 3.14 3.21
PLS[2:0]=111 (falling edge) 2.95 3.03 3.09
VPVDhyst(2) PVD hysteresis - 100 - mV
VPOR/PDR
Power-on/power-down
reset threshold
Falling edge 1.60(1) 1.68 1.76
V
Rising edge 1.64 1.72 1.80
VPDRhyst(2) PDR hysteresis - 40 - mV
VBOR1
Brownout level 1
threshold
Falling edge 2.13 2.19 2.24
V
Rising edge 2.23 2.29 2.33
VBOR2
Brownout level 2
threshold
Falling edge 2.44 2.50 2.56
Rising edge 2.53 2.59 2.63
VBOR3
Brownout level 3
threshold
Falling edge 2.75 2.83 2.88
Rising edge 2.85 2.92 2.97
VBORhyst(2) BOR hysteresis - 100 - mV
TRSTTEMPO
(2)(3) POR reset timing 0.5 1.5 3.0 ms
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6.3.6 Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 19: Current consumption
measurement scheme.
All the run-mode current consumption measurements given in this section are performed
with a reduced code that gives a consumption equivalent to CoreMark code.
Typical and maximum current consumption
The MCU is placed under the following conditions:
All I/O pins are in input mode with a static value at VDD or VSS (no load).
All peripherals are disabled except if it is explicitly mentioned.
The Flash memory access time is adjusted to both fHCLK frequency and VDD ranges
(refer to Table 15: Features depending on the operating power supply range).
The voltage scaling is adjusted to fHCLK frequency as follows:
Scale 3 for fHCLK 60 MHz
Scale 2 for 60 MHz < fHCLK 84 MHz
The system clock is HCLK, fPCLK1 = fHCLK/2, and fPCLK2 = fHCLK.
External clock is 4 MHz and PLL is on
The maximum values are obtained for VDD = 3.6 V and a maximum ambient
temperature (TA), and the typical values for TA= 25 °C and VDD = 3.3 V unless
otherwise specified.
IRUSH(2)
InRush current on
voltage regulator power-
on (POR or wakeup from
Standby)
- 160 200 mA
ERUSH(2)
InRush energy on
voltage regulator power-
on (POR or wakeup from
Standby)
VDD = 1.7 V, TA = 105 °C,
IRUSH = 171 mA for 31 µs --5.4µC
1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
2. Guaranteed by design, not tested in production.
3. The reset timing is measured from the power-on (POR reset or wakeup from VBAT) to the instant when first
instruction is fetched by the user application code.
Table 19. Embedded reset and power control block characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit
‘ VDD
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Table 20. Typical and maximum current consumption, code with data processing (ART
accelerator disabled) running from SRAM - VDD = 1.7 V
Symbol Parameter Conditions fHCLK
(MHz)
Typ Max(1)
Unit
TA=
25 °C TA= 25 °C TA=85 °C TA=105 °C
IDD
Supply current
in Run mode
External clock,
all peripherals
enabled(2)(3)
84 21.8 23.1 24.1 25.3(4)
mA
60 15.8 16.5 17.5 18.7
40 11.4 11.9 12.9 13.9
20 6.0 6.3 7.3 8.3
External clock,
all peripherals
disabled(3)
84 12.7 13.5 14.5 16.3(4)
60 9.2 10.5 11.5 12.8
40 6.7 7.1 8.1 9.1
20 3.6 3.8 4.8 5.8
1. Guaranteed by characterization, not tested in production unless otherwise specified
2. When analog peripheral blocks such as ADC, HSE, LSE, HSI, or LSI are ON, an additional power consumption has to be
considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA for the
analog part.
4. Tested in production.
Table 21. Typical and maximum current consumption, code with data processing (ART
accelerator disabled) running from SRAM
Symbol Parameter Conditions fHCLK
(MHz) Typ
Max(1)
Unit
TA= 25 °C TA=85 °C TA=105 °C
IDD
Supply current
in Run mode
External clock,
all peripherals
enabled(2)(3)
84 22.0 23.1 24.1 25.3
mA
60 16.0 16.9 17.9 19.8
40 11.6 12.1 13.1 14.1
20 6.2 6.5 7.5 8.5
External clock,
all peripherals
disabled(3)
84 12.9 14.0 15.0 16.3
60 9.5 10.5 11.5 12.8
40 6.9 7.3 8.3 9.3
20 3.8 4.0 5.0 6.0
1. Guaranteed by characterization, not tested in production unless otherwise specified
2. When analog peripheral blocks such as ADC, HSE, LSE, HSI, or LSI are ON, an additional power consumption has to be
considered.
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA for the
analog part.
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STM32F401xD STM32F401xE Electrical characteristics
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Table 22. Typical and maximum current consumption in run mode, code with data processing
(ART accelerator enabled except prefetch) running from Flash memory- VDD = 1.7 V
Symbol Parameter Conditions fHCLK
(MHz) Typ
Max(1)
Unit
TA =
25 °C
TA =
85 °C
TA =
105 °C
IDD
Supply current
in Run mode
External clock,
all peripherals enabled(2)(3)
84 23.2 24.5 25.6 26.6
mA
60 15.1 16.3 17.4 18.4
40 10.8 12.1 13.2 14.2
30 8.8 10.0 11.1 12.2
20 6.9 8.0 9.0 10.1
External clock,
all peripherals disabled(3)
84 12.3 13.6 14.7 15.7
60 8.2 9.4 10.5 11.5
40 6.0 7.3 8.3 9.4
30 4.9 6.2 7.2 8.3
20 4.0 5.1 6.1 7.2
1. Guaranteed by characterization, not tested in production unless otherwise specified.
2. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only
while the ADC is ON (ADON bit is set in the ADC_CR2 register).
3. When the ADC is ON (ADON bit set in the ADC_CR2), add an additional power consumption of 1.6mA per ADC for the
analog part.
Table 23. Typical and maximum current consumption in run mode, code with data processing
(ART accelerator enabled except prefetch) running from Flash memory - VDD = 3.3 V
Symbol Parameter Conditions fHCLK
(MHz) Typ
Max(1)
Unit
TA =
25 °C
TA =
85 °C
TA =
105 °C
IDD
Supply current
in Run mode
External clock,
all peripherals enabled(2)(3)
84 23.4 24.7 25.8 26.8
mA
60 15.3 16.5 17.6 18.6
40 11.0 12.3 13.4 14.4
30 9.0 10.2 11.3 12.4
20 7.1 8.2 9.2 10.3
External clock,
all peripherals disabled(3)
84 12.5 13.8 14.9 15.9
60 8.4 9.6 10.7 11.7
40 6.2 7.5 8.5 9.6
30 5.1 6.4 7.4 8.5
20 4.2 5.3 6.3 7.4
1. Guaranteed by characterization, not tested in production unless otherwise specified.
2. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only
while the ADC is ON (ADON bit is set in the ADC_CR2 register).
3. When the ADC is ON (ADON bit set in the ADC_CR2), add an additional power consumption of 1.6mA per ADC for the
analog part.
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.
Table 24. Typical and maximum current consumption in run mode, code with data processing
(ART accelerator disabled) running from Flash memory
Symbol Parameter Conditions fHCLK
(MHz) Typ
Max(1)
Unit
TA =
25 °C
TA =
85 °C
TA =
105 °C
IDD
Supply current
in Run mode
External clock,
all peripherals enabled(2)(3)
84 31.1 32.2 34.3 36.3
mA
60 21.7 22.1 23.2 24.2
40 15.5 16.1 17.1 18.1
30 12.6 13.1 14.1 15.1
20 9.8 10.1 11.1 12.1
External clock,
all peripherals disabled(3)
84 20.2 21.3 23.4 25.4
60 14.9 15.3 16.3 17.3
40 10.6 11.2 12.2 13.3
30 8.8 9.2 10.2 11.2
20 6.9 7.2 8.2 9.2
1. Guaranteed by characterization, not tested in production unless otherwise specified.
2. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only
while the ADC is ON (ADON bit is set in the ADC_CR2 register).
3. When the ADC is ON (ADON bit set in the ADC_CR2), add an additional power consumption of 1.6mA per ADC for the
analog part.
Table 25. Typical and maximum current consumption in run mode, code with data processing
(ART accelerator enabled with prefetch) running from Flash memory
Symbol Parameter Conditions fHCLK
(MHz) Typ
Max(1)
Unit
TA =
25 °C
TA =
85 °C
TA =
105 °C
IDD
Supply current
in Run mode
External clock,
all peripherals enabled(2)(3)
84 32.5 33.3 34.3 35.4
mA
60 22.2 23.3 24.3 25.3
40 16.0 17.1 18.1 19.2
30 12.9 14.1 15.1 16.1
20 10.2 11.1 12.1 13.1
External clock,
all peripherals disabled(3)
84 21.6 22.4 23.5 24.5
60 15.3 16.4 17.4 18.4
40 11.2 12.3 13.3 14.3
30 9.0 10.2 11.2 12.3
20 7.3 8.2 9.2 10.2
1. Guaranteed by characterization, not tested in production unless otherwise specified.
2. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only
while the ADC is ON (ADON bit is set in the ADC_CR2 register).
3. When the ADC is ON (ADON bit set in the ADC_CR2), add an additional power consumption of 1.6mA per ADC for the
analog part.
DD 0m
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STM32F401xD STM32F401xE Electrical characteristics
114
Table 26. Typical and maximum current consumption in Sleep mode
Symbol Parameter Conditions fHCLK
(MHz) Typ
Max(1)
Unit
TA =
25 °C
TA =
85 °C
TA =
105 °C
IDD
Supply current
in Sleep mode
External clock,
all peripherals enabled(2)(3)
84 16.6 17.4 18.4 19.5
mA
60 10.8 11.2 12.3 13.3
40 8.3 9.0 10.0 11.0
30 6.8 7.1 8.1 9.1
20 5.9 6.1 7.1 8.1
External clock,
all peripherals disabled(3)(4)
84 5.3 6.1 7.1 8.2
60 3.7 4.1 5.1 6.1
40 2.9 3.1 4.1 5.1
30 2.7 3.1 4.1 5.1
20 2.7 3.1 4.1 5.1
1. Guaranteed by characterization, not tested in production unless otherwise specified.
2. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only
while the ADC is ON (ADON bit is set in the ADC_CR2 register).
3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA for the
analog part.
4. Same current consumption for fHCLK at 30 MHz and 20 MHz due to VCO running slower at 30 MHz.
Table 27. Typical and maximum current consumptions in Stop mode - VDD=1.8 V
Symbol Parameter Conditions
Typ Max(1)
Unit
TA =
25 °C
TA =
25 °C
TA =
85 °C
TA =
105 °C
IDD_STOP
Main regulator usage Flash in Stop mode, all
oscillators OFF, no
independent watchdog
109 135 440 650
µA
Low power regulator usage 41 65 310 530(2)
Main regulator usage Flash in Deep power
down mode, all oscillators
OFF, no independent
watchdog
72 95 345 530
Low power regulator usage 12 36 260 510(2)
Low power low voltage regulator usage 10 27 230 460
1. Guaranteed by characterization, not tested in production.
2. Guaranteed by test in production.
DD 3013} (3)
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Table 28. Typical and maximum current consumption in Stop mode - VDD=3.3 V
Symbol Parameter Conditions
Typ Max(1)
Unit
TA =
25 °C
TA =
25 °C
TA =
85 °C
TA =
105 °C
IDD_STOP
Main regulator usage Flash in Stop mode, all
oscillators OFF, no
independent watchdog
111 140 450 670
µA
Low power regulator usage 42 65 330 560
Main regulator usage Flash in Deep power
down mode, all oscillators
OFF, no independent
watchdog
73 100 360 560
Low power regulator usage 12 36 270 520
Low power low voltage regulator usage 10 28 230 470
1. Guaranteed by characterization, not tested in production.
Table 29. Typical and maximum current consumption in Standby mode - VDD=1.8 V
Symbol Parameter Conditions
Typ(1) Max(2)
Unit
TA =
25 °C
TA =
25 °C
TA =
85 °C
TA =
105 °C
IDD_STBY Supply current in
Standby mode
Low-speed oscillator (LSE) and RTC ON 2.4 4.0 12.0 24.0 µA
RTC and LSE OFF 1.8 3.0(3) 11.0 23.0(3)
1. When the PDR is OFF (internal reset is OFF), the typical current consumption is reduced by 1.2 µA.
2. Guaranteed by characterization, not tested in production unless otherwise specified.
3. Guaranteed by test in production.
Table 30. Typical and maximum current consumption in Standby mode - VDD=3.3 V
Symbol Parameter Conditions
Typ(1) Max(2)
Unit
TA =
25 °C
TA =
25 °C
TA =
85 °C
TA =
105 °C
IDD_STBY Supply current in
Standby mode
Low-speed oscillator (LSE) and RTC ON 2.8 5.0 14.0 28.0 µA
RTC and LSE OFF 2.1 4.0(3) 13.0 27.0(3)
1. When the PDR is OFF (internal reset is OFF), the typical current consumption is reduced by 1.2 µA.
2. Guaranteed by characterization, not tested in production unless otherwise specified.
3. Guaranteed by test in production.
VBAT VBAT l' {H
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STM32F401xD STM32F401xE Electrical characteristics
114
Figure 21. Typical VBAT current consumption (LSE and RTC ON)
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 54: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
Table 31. Typical and maximum current consumptions in VBAT mode
Symbol Parameter Conditions(1)
Typ Max(2)
Unit
TA = 25 °C TA =
85 °C
TA =
105 °C
VBAT =
1.7 V
VBAT=
2.4 V
VBAT =
3.3 V VBAT = 3.6 V
IDD_VBAT
Backup
domain supply
current
Low-speed oscillator (LSE) and RTC ON 0.66 0.76 0.97 3.0 5.0
µA
RTC and LSE OFF 0.1 0.1 0.1 2.0 4.0
1. Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values.
2. Guaranteed by characterization, not tested in production.
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Electrical characteristics STM32F401xD STM32F401xE
72/135
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption (see Table 33: Peripheral current
consumption), the I/Os used by an application also contribute to the current consumption.
When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O
pin circuitry and to charge/discharge the capacitive load (internal or external) connected to
the pin:
where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDD is the MCU supply voltage
fSW is the I/O switching frequency
C is the total capacitance seen by the I/O pin: C = CINT+ CEXT
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
ISW VDD fSW C××=
DocID025644 Rev 3 73/135
STM32F401xD STM32F401xE Electrical characteristics
114
Table 32. Switching output I/O current consumption
Symbol Parameter Conditions(1)
1. CS is the PCB board capacitance including the pad pin. CS = 7 pF (estimated value).
I/O toggling
frequency (fSW)Typ Unit
IDDIO I/O switching
current
VDD = 3.3 V
C = CINT
2 MHz 0.05
mA
8 MHz 0.15
25 MHz 0.45
50 MHz 0.85
60 MHz 1.00
84 MHz 1.40
VDD = 3.3 V
CEXT = 0 pF
C = CINT + CEXT + CS
2 MHz 0.10
8 MHz 0.35
25 MHz 1.05
50 MHz 2.20
60 MHz 2.40
84 MHz 3.55
VDD = 3.3 V
CEXT =10 pF
C = CINT + CEXT + CS
2 MHz 0.20
8 MHz 0.65
25 MHz 1.85
50 MHz 2.45
60 MHz 4.70
84 MHz 8.80
VDD = 3.3 V
CEXT = 22 pF
C = CINT + CEXT + CS
2 MHz 0.25
8 MHz 1.00
25 MHz 3.45
50 MHz 7.15
60 MHz 11.55
VDD = 3.3 V
CEXT = 33 pF
C = CINT + CEXT + CS
2 MHz 0.32
8 MHz 1.27
25 MHz 3.88
50 MHz 12.34
Electrical characteristics STM32F401xD STM32F401xE
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On-chip peripheral current consumption
The MCU is placed under the following conditions:
At startup, all I/O pins are in analog input configuration.
All peripherals are disabled unless otherwise mentioned.
The ART accelerator is ON.
Voltage Scale 2 mode selected, internal digital voltage V12 = 1.26 V.
HCLK is the system clock at 84 MHz. fPCLK1 = fHCLK/2, and fPCLK2 = fHCLK.
The given value is calculated by measuring the difference of current consumption
with all peripherals clocked off
with only one peripheral clocked on
Ambient operating temperature is 25 °C and VDD=3.3 V.
Table 33. Peripheral current consumption
Peripheral IDD (typ) Unit
AHB1
(up to 84MHz)
GPIOA 1.55
µA/MHz
GPIOB 1.55
GPIOC 1.55
GPIOD 1.55
GPIOE 1.55
GPIOH 1.55
CRC 0.36
DMA1 20.24
DMA2 21.07
APB1
(up to 42MHz)
TIM2 11.19
µA/MHz
TIM3 8.57
TIM4 8.33
TIM5 11.19
PWR 0.71
USART2 3.33
I2C1/2/3 3.10
SPI2(1) 2.62
SPI3(1) 2.86
I2S2 1.90
I2S3 1.67
WWDG 0.71
AHB2
(up to 84MHz) OTG_FS 23.93 µA/MHz
DocID025644 Rev 3 75/135
STM32F401xD STM32F401xE Electrical characteristics
114
6.3.7 Wakeup time from low-power modes
The wakeup times given in Table 34 are measured starting from the wakeup event trigger up
to the first instruction executed by the CPU:
For Stop or Sleep modes: the wakeup event is WFE.
WKUP (PA0) pin is used to wakeup from Standby, Stop and Sleep modes.
All timings are derived from tests performed under ambient temperature and VDD=3.3 V.
APB2
(up to 84MHz)
TIM1 5.71
µA/MHz
TIM9 2.86
TIM10 1.79
TIM11 2.02
ADC1(2) 2.98
SPI1 1.19
USART1 3.10
USART6 2.86
SDIO 5.95
SPI4 1.31
SYSCFG 0.71
1. I2SMOD bit set in SPI_I2SCFGR register, and then the I2SE bit set to enable I2S peripheral.
2. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6
mA for the analog part.
Table 33. Peripheral current consumption (continued)
Peripheral IDD (typ) Unit
Table 34. Low-power mode wakeup timings(1)
Symbol Parameter Min(1) Typ(1) Max(1) Unit
tWUSLEEP(2) Wakeup from Sleep mode - 4 6
CPU
clock
cycle
tWUSTOP(2)
Wakeup from Stop mode, usage of main regulator - 13.5 14.5
µs
Wakeup from Stop mode, usage of main regulator, Flash
memory in Deep power down mode -105111
Wakeup from Stop mode, regulator in low power mode - 21 33
Wakeup from Stop mode, regulator in low power mode,
Flash memory in Deep power down mode - 113 130
tWUSTDBY(2)(3) Wakeup from Standby mode - 314 407 µs
1. Guaranteed by characterization, not tested in production.
2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first instruction.
3. tWUSTDBY maximum value is given at –40 °C.
Electrical characteristics STM32F401xD STM32F401xE
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6.3.8 External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 54. However, the recommended clock input
waveform is shown in Figure 22.
The characteristics given in Table 35 result from tests performed using an high-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 14.
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The
external clock signal has to respect the Table 54. However, the recommended clock input
waveform is shown in Figure 23.
The characteristics given in Table 36 result from tests performed using an low-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 14.
Table 35. High-speed external user clock characteristics
Symbol Parameter Conditions Min Typ Max Unit
fHSE_ext
External user clock source
frequency(1) 1-50MHz
VHSEH OSC_IN input pin high level voltage 0.7VDD -V
DD V
VHSEL OSC_IN input pin low level voltage VSS -0.3V
DD
tw(HSE)
tw(HSE)
OSC_IN high or low time(1)
1. Guaranteed by design, not tested in production.
5--
ns
tr(HSE)
tf(HSE)
OSC_IN rise or fall time(1) --10
Cin(HSE) OSC_IN input capacitance(1) -5-pF
DuCy(HSE) Duty cycle 45 - 55 %
ILOSC_IN Input leakage current VSS VIN VDD --±1µA
DocID025644 Rev 3 77/135
STM32F401xD STM32F401xE Electrical characteristics
114
Figure 22. High-speed external clock source AC timing diagram
Table 36. Low-speed external user clock characteristics
Symbol Parameter Conditions Min Typ Max Unit
fLSE_ext
User External clock source
frequency(1) - 32.768 1000 kHz
VLSEH
OSC32_IN input pin high level
voltage 0.7VDD -V
DD V
VLSEL OSC32_IN input pin low level voltage VSS -0.3V
DD
tw(LSE)
tf(LSE)
OSC32_IN high or low time(1) 450 - -
ns
tr(LSE)
tf(LSE)
OSC32_IN rise or fall time(1) --50
Cin(LSE) OSC32_IN input capacitance(1) -5-pF
DuCy(LSE) Duty cycle 30 - 70 %
ILOSC32_IN Input leakage current VSS VIN VDD --±1µA
1. Guaranteed by design, not tested in production.
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Electrical characteristics STM32F401xD STM32F401xE
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Figure 23. Low-speed external clock source AC timing diagram
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 37. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 24). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
Table 37. HSE 4-26 MHz oscillator characteristics(1)
1. Guaranteed by design, not tested in production.
Symbol Parameter Conditions Min Typ Max Unit
fOSC_IN Oscillator frequency 4 - 26 MHz
RFFeedback resistor - 200 - kΩ
IDD HSE current consumption
VDD=3.3 V,
ESR= 30 Ω,
CL=5 pF @25 MHz
-450-
µA
VDD=3.3 V,
ESR= 30 Ω,
CL=10 pF @25 MHz
-530-
Gm_crit_max Maximum critical crystal gmStartup - - 1 mA/V
tSU(HSE)(2)
2. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
Startup time VDD is stabilized - 2 - ms
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DocID025644 Rev 3 79/135
STM32F401xD STM32F401xE Electrical characteristics
114
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 24. Typical application with an 8 MHz crystal
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 38. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Table 38. LSE oscillator characteristics (fLSE = 32.768 kHz) (1)
1. Guaranteed by design, not tested in production.
Symbol Parameter Conditions Min Typ Max Unit
RFFeedback resistor - 18.4 - MΩ
IDD LSE current consumption - - 1 µA
Gm_crit_max Maximum critical crystal gmStartup - - 0.56 µA/V
tSU(LSE)(2)
2. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized
32.768 kHz oscillation is reached. This value is guaranteed by characterization and not tested in
production. It is measured for a standard crystal resonator and it can vary significantly with the crystal
manufacturer.
startup time VDD is stabilized - 2 - s
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Electrical characteristics STM32F401xD STM32F401xE
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Figure 25. Typical application with a 32.768 kHz crystal
6.3.9 Internal clock source characteristics
The parameters given in Table 39 and Table 40 are derived from tests performed under
ambient temperature and VDD supply voltage conditions summarized in Table 14.
High-speed internal (HSI) RC oscillator
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Table 39. HSI oscillator characteristics (1)
1. VDD = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
fHSI Frequency - 16 - MHz
ACCHSI
Accuracy of the HSI
oscillator
User-trimmed with the RCC_CR
register(2)
2. Guaranteed by design, not tested in production
--1%
Factory-
calibrated
TA = –40 to 105 °C(3)
3. Guaranteed by characterization, not tested in production
–8 - 4.5 %
TA = –10 to 85 °C(3) –4 - 4 %
TA = 25 °C –1 - 1 %
tsu(HSI)(2) HSI oscillator
startup time -2.24µs
IDD(HSI)(2) HSI oscillator
power consumption -6080µA
{H
DocID025644 Rev 3 81/135
STM32F401xD STM32F401xE Electrical characteristics
114
Figure 26. ACCHSI versus temperature
1. Guaranteed by characterization, not tested in production.
Low-speed internal (LSI) RC oscillator
Table 40. LSI oscillator characteristics (1)
1. VDD = 3 V, TA = –40 to 105 °C unless otherwise specified.
Symbol Parameter Min Typ Max Unit
fLSI(2)
2. Guaranteed by characterization, not tested in production.
Frequency 17 32 47 kHz
tsu(LSI)(3)
3. Guaranteed by design, not tested in production.
LSI oscillator startup time - 15 40 µs
IDD(LSI)(3) LSI oscillator power consumption - 0.4 0.6 µA
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Electrical characteristics STM32F401xD STM32F401xE
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Figure 27. ACCLSI versus temperature
6.3.10 PLL characteristics
The parameters given in Table 41 and Table 42 are derived from tests performed under
temperature and VDD supply voltage conditions summarized in Table 14.
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Table 41. Main PLL characteristics
Symbol Parameter Conditions Min Typ Max Unit
fPLL_IN PLL input clock(1) 0.95(2) 12.10MHz
fPLL_OUT PLL multiplier output clock 24 - 84 MHz
fPLL48_OUT
48 MHz PLL multiplier output
clock -4875MHz
fVCO_OUT PLL VCO output 192 - 432 MHz
tLOCK PLL lock time
VCO freq = 192 MHz 75 - 200
µs
VCO freq = 432 MHz 100 - 300
Jitter(3)
Cycle-to-cycle jitter
System clock
84 MHz
RMS - 25 -
ps
peak
to
peak
-±150 -
Period Jitter
RMS - 15 -
peak
to
peak
-±200 -
DocID025644 Rev 3 83/135
STM32F401xD STM32F401xE Electrical characteristics
114
IDD(PLL)(4) PLL power consumption on VDD VCO freq = 192 MHz
VCO freq = 432 MHz
0.15
0.45 -0.40
0.75
mA
IDDA(PLL)(4) PLL power consumption on
VDDA
VCO freq = 192 MHz
VCO freq = 432 MHz
0.30
0.55 -0.40
0.85
1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared
between PLL and PLLI2S.
2. Guaranteed by design, not tested in production.
3. The use of 2 PLLs in parallel could degraded the Jitter up to +30%.
4. Guaranteed by characterization, not tested in production.
Table 41. Main PLL characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit
Table 42. PLLI2S (audio PLL) characteristics
Symbol Parameter Conditions Min Typ Max Unit
fPLLI2S_IN PLLI2S input clock(1) 0.95(2) 12.10
MHzfPLLI2S_OUT PLLI2S multiplier output clock - - 216
fVCO_OUT PLLI2S VCO output 192 - 432
tLOCK PLLI2S lock time
VCO freq = 192 MHz 75 - 200
µs
VCO freq = 432 MHz 100 - 300
Jitter(3)
Master I2S clock jitter
Cycle to cycle at
12.288 MHz on
48 KHz period,
N=432, R=5
RMS - 90 -
peak
to
peak
- ±280 -
ps
Average frequency of
12.288 MHz
N = 432, R = 5
on 1000 samples
-90 -
WS I2S clock jitter Cycle to cycle at 48 KHz
on 1000 samples - 400 -
IDD(PLLI2S)(4) PLLI2S power consumption on
VDD
VCO freq = 192 MHz
VCO freq = 432 MHz
0.15
0.45 -0.40
0.75
mA
IDDA(PLLI2S)(4) PLLI2S power consumption on
VDDA
VCO freq = 192 MHz
VCO freq = 432 MHz
0.30
0.55 -0.40
0.85
1. Take care of using the appropriate division factor M to have the specified PLL input clock values.
2. Guaranteed by design, not tested in production.
3. Value given with main PLL running.
4. Guaranteed by characterization, not tested in production.
Electrical characteristics STM32F401xD STM32F401xE
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6.3.11 PLL spread spectrum clock generation (SSCG) characteristics
The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic
interferences(see Table 49: EMI characteristics for WLCSP49). It is available only on the
main PLL.
Equation 1
The frequency modulation period (MODEPER) is given by the equation below:
fPLL_IN and fMod must be expressed in Hz.
As an example:
If fPLL_IN = 1 MHz, and fMOD = 1 kHz, the modulation depth (MODEPER) is given by
equation 1:
Equation 2
Equation 2 allows to calculate the increment step (INCSTEP):
fVCO_OUT must be expressed in MHz.
With a modulation depth (md) = ±2 % (4 % peak to peak), and PLLN = 240 (in MHz):
An amplitude quantization error may be generated because the linear modulation profile is
obtained by taking the quantized values (rounded to the nearest integer) of MODPER and
INCSTEP. As a result, the achieved modulation depth is quantized. The percentage
quantized modulation depth is given by the following formula:
As a result:
Table 43. SSCG parameters constraint
Symbol Parameter Min Typ Max(1) Unit
fMod Modulation frequency - - 10 KHz
md Peak modulation depth 0.25 - 2 %
MODEPER * INCSTEP - - 215-1 -
1. Guaranteed by design, not tested in production.
MODEPER round fPLL_IN 4f
Mod
×()[]=
MODEPER round 106410
3
×()[]250==
INCSTEP round 215 1()md PLLN××()100 5×MODEPER×()[]=
INCSTEP round 215 1()2 240××()100 5×250×()[]126md(quantitazed)%==
mdquantized% MODEPER INCSTEP×100×5×()215 1()PLLN×()=
mdquantized%250126×100×5×()215 1()240×()2,002%(peak)==
DocID025644 Rev 3 85/135
STM32F401xD STM32F401xE Electrical characteristics
114
Figure 28 and Figure 29 show the main PLL output clock waveforms in center spread and
down spread modes, where:
F0 is fPLL_OUT nominal.
Tmode is the modulation period.
md is the modulation depth.
Figure 28. PLL output clock waveforms in center spread mode
Figure 29. PLL output clock waveforms in down spread mode
6.3.12 Memory characteristics
Flash memory
The characteristics are given at TA = 40 to 105 °C unless otherwise specified.
The devices are shipped to customers with the Flash memory erased.
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Table 44. Flash memory characteristics
Symbol Parameter Conditions Min Typ Max Unit
IDD Supply current
Write / Erase 8-bit mode, VDD = 1.7 V - 5 -
mAWrite / Erase 16-bit mode, VDD = 2.1 V - 8 -
Write / Erase 32-bit mode, VDD = 3.3 V - 12 -
Electrical characteristics STM32F401xD STM32F401xE
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Table 45. Flash memory programming
Symbol Parameter Conditions Min(1) Typ Max(1)
1. Guaranteed by characterization, not tested in production.
Unit
tprog Word programming time Program/erase parallelism
(PSIZE) = x 8/16/32 -16100
(2)
2. The maximum programming time is measured after 100K erase operations.
µs
tERASE16KB Sector (16 KB) erase time
Program/erase parallelism
(PSIZE) = x 8 - 400 800
ms
Program/erase parallelism
(PSIZE) = x 16 - 300 600
Program/erase parallelism
(PSIZE) = x 32 - 250 500
tERASE64KB Sector (64 KB) erase time
Program/erase parallelism
(PSIZE) = x 8 - 1200 2400
ms
Program/erase parallelism
(PSIZE) = x 16 - 700 1400
Program/erase parallelism
(PSIZE) = x 32 - 550 1100
tERASE128KB Sector (128 KB) erase time
Program/erase parallelism
(PSIZE) = x 8 -24
s
Program/erase parallelism
(PSIZE) = x 16 -1.32.6
Program/erase parallelism
(PSIZE) = x 32 -12
tME Mass erase time
Program/erase parallelism
(PSIZE) = x 8 -816
s
Program/erase parallelism
(PSIZE) = x 16 -5.511
Program/erase parallelism
(PSIZE) = x 32 -48
Vprog Programming voltage
32-bit program operation 2.7 - 3.6 V
16-bit program operation 2.1 - 3.6 V
8-bit program operation 1.7 - 3.6 V
Table 46. Flash memory programming with VPP voltage
Symbol Parameter Conditions Min(1) Typ Max(1) Unit
tprog Double word programming
TA = 0 to +40 °C
VDD = 3.3 V
VPP = 8.5 V
- 16 100(2) µs
tERASE16KB Sector (16 KB) erase time - 230 -
mstERASE64KB Sector (64 KB) erase time - 490 -
tERASE128KB Sector (128 KB) erase time - 875 -
tME Mass erase time - 1.750 - s
DocID025644 Rev 3 87/135
STM32F401xD STM32F401xE Electrical characteristics
114
Table 47. Flash memory endurance and data retention
6.3.13 EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant
with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 48. They are based on the EMS levels and classes
defined in application note AN1709.
Vprog Programming voltage 2.7 - 3.6 V
VPP VPP voltage range 7 - 9 V
IPP
Minimum current sunk on
the VPP pin 10 - - mA
tVPP(3) Cumulative time during
which VPP is applied - - 1 hour
1. Guaranteed by design, not tested in production.
2. The maximum programming time is measured after 100K erase operations.
3. VPP should only be connected during programming/erasing.
Symbol Parameter Conditions
Value
Unit
Min(1)
1. Guaranteed by characterization, not tested in production.
NEND Endurance TA = –40 to +85 °C (6 suffix versions)
TA =40 to +105 °C (7 suffix versions) 10 kcycles
tRET Data retention
1 kcycle(2) at TA = 85 °C
2. Cycling performed over the whole temperature range.
30
Years1 kcycle(2) at TA = 105 °C 10
10 kcycles(2) at TA = 55 °C 20
Table 46. Flash memory programming with VPP voltage (continued)
Symbol Parameter Conditions Min(1) Typ Max(1) Unit
Electrical characteristics STM32F401xD STM32F401xE
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When the application is exposed to a noisy environment, it is recommended to avoid pin
exposition to disturbances. The pins showing a middle range robustness are: PA0, PA1,
PA2, on LQFP100 packages and PDR_ON on WLCSP49.
As a consequence, it is recommended to add a serial resistor (1 kΩ maximum) located as
close as possible to the MCU to the pins exposed to noise (connected to tracks longer than
50 mm on PCB).
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
Corrupted program counter
Unexpected reset
Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Table 48. EMS characteristics for LQFP100 package
Symbol Parameter Conditions Level/
Class
VFESD
Voltage limits to be applied on any I/O pin
to induce a functional disturbance
VDD = 3.3 V, LQFP100, WLCSP49,
TA = +25 °C, fHCLK = 84 MHz,
conforms to IEC 61000-4-2
2B
VEFTB
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD = 3.3 V, LQFP100, WLCSP49,
TA = +25 °C, fHCLK = 84 MHz,
conforms to IEC 61000-4-4
4A
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STM32F401xD STM32F401xE Electrical characteristics
114
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application,
executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2
standard which specifies the test board and the pin loading.
6.3.14 Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Table 49. EMI characteristics for WLCSP49
Symbol Parameter Conditions Monitored
frequency band
Max vs.
[fHSE/fCPU]Unit
8/84 MHz
SEMI Peak level VDD = 3.6 V, TA = 25 °C, conforming to
IEC61967-2
0.1 to 30 MHz -4
dBµV30 to 130 MHz -4
130 MHz to 1 GHz -2
SAE EMI Level 1.5 -
Table 50. EMI characteristics for LQFP100
Symbol Parameter Conditions Monitored
frequency band
Max vs.
[fHSE/fCPU]Unit
8/84 MHz
SEMI Peak level VDD = 3.6 V, TA = 25 °C, conforming to
IEC61967-2
0.1 to 30 MHz 19
dBµV30 to 130 MHz 19
130 MHz to 1 GHz 11
SAE EMI Level 3.5 -
Electrical characteristics STM32F401xD STM32F401xE
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Static latchup
Two complementary static tests are required on six parts to assess the latchup
performance:
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latchup standard.
6.3.15 I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibilty to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (>5
LSB TUE), out of conventional limits of induced leakage current on adjacent pins
(out of –5 µA/+0 µA range), or other functional failure (for example reset, oscillator
frequency deviation).
Negative induced leakage current is caused by negative injection and positive induced
leakage current by positive injection.
The test results are given in Table 53.
Table 51. ESD absolute maximum ratings
Symbol Ratings Conditions Class Maximum
value(1) Unit
VESD(HBM)
Electrostatic discharge
voltage (human body model)
TA = +25 °C conforming to JESD22-
A114 2 2000
V
VESD(CDM)
Electrostatic discharge
voltage (charge device
model)
TA = +25 °C conforming to
ANSI/ESD STM5.3.1 II 400
1. Guaranteed by characterization, not tested in production.
Table 52. Electrical sensitivities
Symbol Parameter Conditions Class
LU Static latch-up class TA = +105 °C conforming to JESD78A II level A
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STM32F401xD STM32F401xE Electrical characteristics
114
Note: It is recommended to add a Schottky diode (pin to ground) to analog pins which may
potentially inject negative currents.
6.3.16 I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 54 are derived from tests
performed under the conditions summarized in Table 14. All I/Os are CMOS and TTL
compliant.
Table 53. I/O current injection susceptibility(1)
1. NA = not applicable.
Symbol Description
Functional susceptibility
Unit
Negative
injection
Positive
injection
IINJ
Injected current on BOOT0 pin –0 NA
mA
Injected current on NRST pin –0 NA
Injected current on PB3, PB4, PB5, PB6,
PB7, PB8, PB9, PC13, PC14, PC15, PH1,
PDR_ON, PC0, PC1,PC2, PC3, PD1,
PD5, PD6, PD7, PE0, PE2, PE3, PE4,
PE5, PE6
–0 NA
Injected current on any other FT pin –5 NA
Injected current on any other pins –5 +5
Table 54. I/O static characteristics
Symbol Parameter Conditions Min Typ Max Unit
VIL
FT, and NRST I/O input low
level voltage 1.7 VVDD3.6 V - -
0.35VDD–0.04(1)
V
0.3VDD(2)
BOOT0 I/O input low level
voltage
1.75 VVDD 3.6 V,
-40 °CTA 105 °C --
0.1VDD+0.1
1.7 VVDD 3.6 V,
0 °CTA 105 °C --
VIH
FT and NRST I/O input high
level voltage(5) 1.7 VVDD3.6 V
0.45VDD+0.3(1) --
V
0.4VDD(2)
BOOT0 I/O input high level
voltage
1.75 VVDD 3.6 V,
-40 °CTA 105 °C 0.17VDD+0.7(1) --
1.7 VVDD 3.6 V,
0 °CTA 105 °C
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All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements for FT I/Os is shown in Figure 30.
VHYS
FT and NRST I/O input
hysteresis 1.7 VVDD3.6 V - 10%
VDD(3) -V
BOOT0 I/O input hysteresis
1.75 VVDD 3.6 V,
-40 °CTA 105 °C -100 -mV
1.7 VVDD 3.6 V,
0 °CTA 105 °C
Ilkg
I/O input leakage current (4) VSS VIN VDD --±1
µA
I/O FT input leakage current (5) VIN = 5 V - - 3
RPU
Weak pull-up
equivalent
resistor(6)
All pins
except for
PA10
(OTG_FS_ID
)VIN = VSS
30 40 50
kΩ
PA10
(OTG_FS_ID
)
710 14
RPD
Weak pull-down
equivalent
resistor(7)
All pins
except for
PA10
(OTG_FS_ID
)VIN = VDD
30 40 50
PA10
(OTG_FS_ID
)
710 14
CIO(8) I/O pin capacitance - - 5 - pF
1. Guaranteed by design, not tested in production.
2. Guaranteed by test in production.
3. With a minimum of 200 mV.
4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins, Refer to Table 53: I/O
current injection susceptibility
5. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled. Leakage could be
higher than the maximum value, if negative current is injected on adjacent pins.Refer to Table 53: I/O current injection
susceptibility
6. Pull-up resistors are designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the
series resistance is minimum (~10% order).
7. Pull-down resistors are designed with a true resistance in series with a switchable NMOS. This NMOS contribution to the
series resistance is minimum (~10% order).
8. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization, not tested in production.
Table 54. I/O static characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit
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STM32F401xD STM32F401xE Electrical characteristics
114
Figure 30. FT I/O input characteristics
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA (with a relaxed VOL/VOH) except PC13, PC14 and PC15 which can
sink or source up to ±3mA. When using the PC13 to PC15 GPIOs in output mode, the
speed should not exceed 2 MHz with a maximum load of 30 pF.
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2. In particular:
The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
ΣIVDD (see Table 12).
The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
ΣIVSS (see Table 12).
Output voltage levels
Unless otherwise specified, the parameters given in Table 55 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 14. All I/Os are CMOS and TTL compliant.
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Electrical characteristics STM32F401xD STM32F401xE
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Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 31 and ,
respectively.
Unless otherwise specified, the parameters given in Table 56 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 14.
Table 55. Output voltage characteristics
Symbol Parameter Conditions Min Max Unit
VOL(1)
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 12.
and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
Output low level voltage for an I/O pin CMOS port(2)
IIO = +8 mA
2.7 V VDD 3.6 V
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
-0.4
V
VOH(3)
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 12 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.
Output high level voltage for an I/O pin VDD–0.4 -
VOL (1) Output low level voltage for an I/O pin TTL port(2)
IIO =+8 mA
2.7 V VDD 3.6 V
-0.4
V
VOH (3) Output high level voltage for an I/O pin 2.4 -
VOL(1) Output low level voltage for an I/O pin IIO = +20 mA
2.7 V VDD 3.6 V
-1.3
(4)
4. Guaranteed by characterization results, not tested in production.
V
VOH(3) Output high level voltage for an I/O pin VDD–1.3(4) -
VOL(1) Output low level voltage for an I/O pin IIO = +6 mA
1.8 V VDD 3.6 V
-0.4
(4)
V
VOH(3) Output high level voltage for an I/O pin VDD–0.4(4) -
VOL(1) Output low level voltage for an I/O pin IIO = +4 mA
1.7 V VDD 3.6 V
-0.4
(5)
5. Guaranteed by design, not tested in production..
V
VOH(3) Output high level voltage for an I/O pin VDD–0.4(5) -
Table 56. I/O AC characteristics(1)(2)
OSPEEDRy
[1:0] bit
value(1)
Symbol Parameter Conditions Min Typ Max Unit
00
fmax(IO)out Maximum frequency(3)
CL = 50 pF, VDD 2.70 V - - 4
MHz
CL = 50 pF, VDD 1.7 V - - 2
CL = 10 pF, VDD 2.70 V - - 8
CL = 10 pF, VDD 1.7 V - - 4
tf(IO)out/
tr(IO)out
Output high to low level fall
time and output low to high
level rise time
CL = 50 pF, VDD = 1.7 V to
3.6 V --100ns
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STM32F401xD STM32F401xE Electrical characteristics
114
01
fmax(IO)out Maximum frequency(3)
CL = 50 pF, VDD 2.70 V - - 25
MHz
CL = 50 pF, VDD 1.7 V - - 12.5
CL = 10 pF, VDD 2.70 V - - 50
CL = 10 pF, VDD 1.7 V - - 20
tf(IO)out/
tr(IO)out
Output high to low level fall
time and output low to high
level rise time
CL = 50 pF, VDD 2.7 V - - 10
ns
CL = 50 pF, VDD 1.7 V - - 20
CL = 10 pF, VDD 2.70 V - - 6
CL = 10 pF, VDD 1.7 V - - 10
10
fmax(IO)out Maximum frequency(3)
CL = 40 pF, VDD 2.70 V - - 50(4)
MHz
CL = 40 pF, VDD 1.7 V - - 25
CL = 10 pF, VDD 2.70 V - - 100(4)
CL = 10 pF, VDD 1.7 V - - 50(4)
tf(IO)out/
tr(IO)out
Output high to low level fall
time and output low to high
level rise time
CL = 40 pF, VDD 2.70 V - - 6
ns
CL = 40 pF, VDD 1.7 V - - 10
CL = 10 pF, VDD 2.70 V - - 4
CL = 10 pF, VDD 1.7 V - - 6
11
Fmax(IO)out Maximum frequency(3)
CL = 30 pF, VDD 2.70 V - - 100(4)
MHz
CL = 30 pF, VDD 1.7 V - - 50(4)
CL = 10 pF, VDD 2.70 V - - 180(4)
CL = 10 pF, VDD 1.7 V - - 100(4)
tf(IO)out/
tr(IO)out
Output high to low level fall
time and output low to high
level rise time
CL = 30 pF, VDD 2.70 V - - 4
ns
CL = 30 pF, VDD 1.7 V - - 6
CL = 10 pF, VDD 2.70 V - - 2.5
CL = 10 pF, VDD 1.7 V - - 4
-t
EXTIpw
Pulse width of external signals
detected by the EXTI
controller
10 - - ns
1. Guaranteed by characterization, not tested in production.
2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F4xx reference manual for a description of
the GPIOx_SPEEDR GPIO port output speed register.
3. The maximum frequency is defined in Figure 31.
4. For maximum frequencies above 50 MHz and VDD > 2.4 V, the compensation cell should be used.
Table 56. I/O AC characteristics(1)(2) (continued)
OSPEEDRy
[1:0] bit
value(1)
Symbol Parameter Conditions Min Typ Max Unit
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Figure 31. I/O AC characteristics definition
6.3.17 NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 54).
Unless otherwise specified, the parameters given in Table 57 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 14. Refer to Table 54: I/O static characteristics for the values of VIH and VIL for
NRST pin.
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Table 57. NRST pin characteristics
Symbol Parameter Conditions Min Typ Max Unit
RPU
Weak pull-up equivalent
resistor(1) VIN = VSS 30 40 50 kΩ
VF(NRST)(2) NRST Input filtered pulse - - 100 ns
VNF(NRST)(2) NRST Input not filtered pulse VDD > 2.7 V 300 - - ns
TNRST_OUT Generated reset pulse duration Internal Reset
source 20 - - µs
1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance must be minimum (~10% order).
2. Guaranteed by design, not tested in production.
DD
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STM32F401xD STM32F401xE Electrical characteristics
114
Figure 32. Recommended NRST pin protection
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 57. Otherwise the reset is not taken into account by the device.
6.3.18 TIM timer characteristics
The parameters given in Table 58 are guaranteed by design.
Refer to Section 6.3.16: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
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Table 58. TIMx characteristics(1)(2)
1. TIMx is used as a general term to refer to the TIM1 to TIM11 timers.
2. Guaranteed by design, not tested in production.
Symbol Parameter Conditions(3)
3. The maximum timer frequency on APB1 is 42 MHz and on APB2 is up to 84 MHz, by setting the TIMPRE
bit in the RCC_DCKCFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = HCKL, otherwise
TIMxCLK >= 4x PCLKx.
Min Max Unit
tres(TIM) Timer resolution time
AHB/APBx prescaler=1
or 2 or 4, fTIMxCLK =
84 MHz
1-
tTIMxCLK
11.9 - ns
AHB/APBx prescaler>4,
fTIMxCLK = 84 MHz
1-
tTIMxCLK
11.9 - ns
fEXT Timer external clock
frequency on CH1 to CH4 fTIMxCLK = 84 MHz
0fTIMxCLK/2 MHz
042MHz
ResTIM Timer resolution - 16/32 bit
tCOUNTER
16-bit counter clock
period when internal clock
is selected
fTIMxCLK = 84 MHz 0.0119 780 µs
tMAX_COUNT Maximum possible count
with 32-bit counter
-65536 ×
65536 tTIMxCLK
fTIMxCLK = 84 MHz -51.1S
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6.3.19 Communications interfaces
I2C interface characteristics
The I2C interface meets the requirements of the standard I2C communication protocol with
the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-
drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is
disabled, but is still present.
The I2C characteristics are described in Table59. Refer also to Section 6.3.16: I/O port
characteristics for more details on the input/output alternate function characteristics (SDA
and SCL).
The I2C bus interface supports standard mode (up to 100 kHz) and fast mode (up to 400
kHz). The I2C bus frequency can be increased up to 1 MHz. For more details about the
complete solution, please contact your local ST sales representative.
Table 59. I2C characteristics
Symbol Parameter
Standard mode I2C(1)
1. Guaranteed by design, not tested in production.
Fast mode I2C(1)(2)
2. fPCLK1 must be at least 2 MHz to achieve standard mode I2C frequencies. It must be at least 4 MHz to
achieve fast mode I2C frequencies, and a multiple of 10 MHz to reach the 400 kHz maximum I2C fast mode
clock.
Unit
Min Max Min Max
tw(SCLL) SCL clock low time 4.7 - 1.3 -
µs
tw(SCLH) SCL clock high time 4.0 - 0.6 -
tsu(SDA) SDA setup time 250 - 100 -
ns
th(SDA) SDA data hold time 0 - 0 900(3)
3. The maximum data hold time has only to be met if the interface does not stretch the low period of SCL
signal.
tr(SDA)
tr(SCL)
SDA and SCL rise time - 1000 300
tf(SDA)
tf(SCL)
SDA and SCL fall time - 300 - 300
th(STA) Start condition hold time 4.0 - 0.6 -
µs
tsu(STA)
Repeated Start condition
setup time 4.7 - 0.6 -
tsu(STO) Stop condition setup time 4.0 - 0.6 - µs
tw(STO:STA)
Stop to Start condition time
(bus free) 4.7 - 1.3 - µs
Cb
Capacitive load for each bus
line - 400 - 400 pF
DD7I2 PC bus ‘w(SCLL) 14—>1 ‘r(SCL) Rs PCLK1
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STM32F401xD STM32F401xE Electrical characteristics
114
Figure 33. I2C bus AC waveforms and measurement circuit
1. RS = series protection resistor.
2. RP = external pull-up resistor.
3. VDD_I2C is the I2C bus power supply.
Table 60. SCL frequency (fPCLK1= 42 MHz, VDD = VDD_I2C = 3.3 V)(1)(2)
1. RP = External pull-up resistance, fSCL = I2C speed
2. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the
tolerance on the achieved speed is ±2%. These variations depend on the accuracy of the external
components used to design the application.
fSCL (kHz)
I2C_CCR value
RP = 4.7 kΩ
400 0x8019