EMC1704 Datasheet by Microchip Technology

View All Related Products | Download PDF Datasheet
MICROCHIP h curren nd temper tiers 07 He that Ca ALERT ened an THERM — Arm para\|e\ diode s \m rnal mperamre m — :1" curacy (-5 ALERT THERM
EMC1704 DATASHEET DS20005239A
Datasheet
PRODUCT FEATURES
EMC1704
High-Side Current-Sense and Multiple
1°C Temperature Monitor
General Description
The EMC1704 is a combination high-side current sensing
device with precision temperature measurement. It
measures the voltage developed across an external sense
resistor to represent the high-side current of a battery or
voltage regulator. It also measures the source voltage and
uses these measured values to present a proportional
power calculation. The EMC1704 contains additional bi-
directional peak detection circuitry to flag instantaneous
current spikes with programmable time duration and
magnitude threshold. Finally, the EMC1704 includes up to
three (3) external diode channels and an internal
temperature sensor for temperature measurement.
The temperature measurement includes advanced features
such as Resistance Error Correction (REC), Beta
Compensation (to support CPU diodes requiring the
BJT/transistor model including 45nm and 65nm
processors), and automatic diode type detection.
Both current sensing and temperature monitoring include
two tiers of protection: one that can be masked and causes
the ALERT pin to be asserted, and the other that cannot be
masked and causes the THERM pin to be asserted.
Applications
Notebook and Desktop Computers
Industrial
Power Management Systems
Embedded Applications
Features
High-side current sensor
Bi-directional current measurement
Measures source voltage and indicates power ratio
1% current measurement accuracy
Integrated over 82ms to 2.6sec with 11-bit resolution
3V to 24V bus voltage range
Independent hardware set instantaneous current peak
detector (EMC1704-2 only)
Software controls to program time duration and
magnitude threshold
Power supply options
Bus or separately powered for low voltage operation
Wide temperature operating range: -40°C to +85°C
Up to three external temperature monitors
1°C accuracy (20°C < TDIODE < 110°C) with 0.125°C
resolution
Ideality factor setting
Support for 45nm and 65nm CPU diodes requiring the
BJT/transistor model w/ beta compensation
Determines external diode type and optimal settings
Resistance Error Correction
Anti-parallel diode support for additional diode options
Internal temperature monitor
±C accuracy (-5°C < TA < 85°C)
ALERT and THERM outputs for temperature, voltage,
and out-of-current limit reporting
SMBus 2.0 interface
Pin-selectable SMBus Address
Block Read and Write
General Purpose I/O
Available in a RoHS Compliant Package: 14-pin SOIC
(EMC1704-1) or 16-pin 4mm x 4mm QFN (EMC1704-2)
Block Diagram
Analog
Mux
External
Temp
Diodes
Internal
Temp
Diode
SMBus
Slave
Protocol
DP1
DN1
SMCLK
SMDATA
DP2 / DN3
DN2 / DP3 ADDR_SEL
Anti-
parallel
diode
SENSE+
SENSE-
GPIO
DUR_SEL*
TH_SEL*
Peak
Detection
* EMC1704-2 only
Voltage and
Temp Registers
Configuration
11-15 bit
??? ADC
13 - 15 bit
??? ADC Current Registers
Current Limits
Voltage and
Temp Limits
THERM
ALERTPower Register
Q Mlcnacmp
REEL SIZE IS 4,000 PIECES
This product meets the halogen maximum concentration values per IEC61249-2-21
For RoHS compliance and environmental information, please visit www.smsc.com/rohs
Please contact your SMSC sales representative for additional documentation related to this product
such as application notes, anomaly sheets, and design guidelines.
ORDERING NUMBER PACKAGE FEATURES
EMC1704-1-YZT-TR 14-pin SOIC
(Lead-free ROHS compliant)
Up to three external diodes, current
sensor, software set peak detector
EMC1704-2-AP-TR 16-pin 4mm x 4mm QFN
(Lead-free ROHS compliant)
Up to three external diodes, current
sensor, hardware/software set peak
detector
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
DS20005239A 2 EMC1704
DATASHEET
Ordering Information:
DS20005239A 3 EMC1704
DATASHEET
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be
superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO
REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of
Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implic-
itly or otherwise, under any Microchip intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32
logo, rfPIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and
other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MTP, SEEVAL and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM,
MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-
Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
A more complete list of registered trademarks and common law trademarks owned by Standard Microsystems Corporation (“SMSC”)
is available at: www.smsc.com. The absence of a trademark (name, logo, etc.) from the list does not constitute a waiver of any
intellectual property rights that SMSC has established in any of its trademarks.
All other trademarks mentioned herein are property of their respective companies.
© 2013, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN:
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
6‘ MICRDEHIF
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
EMC1704 4 DS20005239A
DATASHEET
Table of Contents
Chapter 1 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chapter 2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2 SMBus Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Chapter 3 Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1 System Management Bus Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1.1 SMBus Start Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1.2 SMBus Address and RD / WR Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1.3 SMBus ACK and NACK Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1.4 SMBus Stop Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1.5 SMBus Time-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1.6 SMBus and I2C Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2 SMBus Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.1 Write Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.2 Read Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.3 Send Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.4 Receive Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.5 Block Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.6 Block Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.7 Alert Response Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Chapter 4 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.1 Source Monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1.1 Current Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1.2 Voltage Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1.3 Power Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.1.4 Current Peak Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.2 VDD Biasing Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.4 ALERT Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.4.1 ALERT Pin Interrupt Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.4.2 ALERT Pin Comparator Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.5 THERM Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.6 Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.6.1 Resistance Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.6.2 Beta Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.6.3 Ideality Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.6.4 Dynamic Averaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.7 Diode Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.7.1 Anti-Parallel Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.7.2 Diode Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Chapter 5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.1 Data Read Interlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.2 Block Mode Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.3 Temperature Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.4 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.5 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.6 Conversion Rate Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Q MICFIDCHIF
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
DS20005239A 5 EMC1704
DATASHEET
5.7 Temperature Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.8 One-Shot Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.9 Tcrit Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.10 External Diode Fault Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.11 Channel Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.12 Consecutive Alert Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.13 Beta Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.14 External Diode Ideality Factor Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.15 High Limit Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.16 Low Limit Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.17 Crit Limit Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.18 Averaging Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.19 Voltage Sampling Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.20 Current Sense Sampling Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.21 Peak Detection Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.22 Sense Voltage Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.23 Source Voltage Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.24 Power Ratio Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.25 VSENSE Limit Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.26 Source Voltage Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.27 Critical Voltage Limit Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.28 GPIO Config and Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.29 Product Features Register (EMC1704-2 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.30 Product ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.31 SMSC ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.32 Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Chapter 6 Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.1 EMC1704-1 Package Drawing (14-Pin SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.2 EMC1704-2 Package Drawing (16-Pin QFN 4mm x 4mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.3 EMC1704 Package Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Chapter 7 Datasheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
MICFIDCHIF
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
EMC1704 6 DS20005239A
DATASHEET
List of Figures
Figure 1.1 EMC1704-1 Pin Diagram 14-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 1.2 EMC1704-2 Pin Diagram 16-Pin QFN 4mm x 4mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3.1 SMBus Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 4.1 EMC1704 System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 4.2 Peak Detection Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 4.3 Diode Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 6.1 14-Pin SOIC Package Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 6.2 14-Pin SOIC Package Drawings Detail “A” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 6.3 14-Pin SOIC Recommended PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 6.4 14-Pin SOIC Dimensions and Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 6.5 16-Pin QFN 4mm x 4mm Package Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 6.6 16-Pin QFN 4mm x 4mm Dimensions and Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 6.7 16-Pin QFN 4mm x 4mm PCB Footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 6.8 EMC1704-1 Package Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 6.9 EMC1704-2 Package Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Q MICFIDCHIF
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
DS20005239A 7 EMC1704
DATASHEET
List of Tables
Table 1.1 Pin Description for EMC1704-X. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 1.2 Pin Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 2.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 2.2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 2.3 SMBus Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3.1 ADDR_SEL Resistor Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 3.2 Protocol Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 3.3 Write Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 3.4 Read Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 3.5 Send Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 3.6 Receive Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 3.7 Block Write Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 3.8 Block Read Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 3.9 Alert Response Address Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 4.1 TH_SEL Resistor Setting (EMC1704-2 only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 4.2 DUR_SEL Resistor Setting (EMC1704-2 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 4.3 Dynamic Averaging Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 5.1 Register Set in Hexadecimal Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 5.2 Temperature Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 5.3 Temperature Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 5.4 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 5.5 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 5.6 Conversion Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 5.7 Conversion Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 5.8 Temperature Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 5.9 One-Shot Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 5.10 Tcrit Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 5.11 External Diode Fault Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 5.12 Channel Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 5.13 Consecutive Alert Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 5.14 Consecutive ALERT / THERM Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 5.15 Beta Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 5.16 Beta Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 5.17 Ideality Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 5.18 Ideality Factor Look-Up Table (Diode Model) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 5.19 High Limit Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 5.20 Low Limit Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 5.21 Crit Limit Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 5.22 Filter Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 5.23 Averaging Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 5.24 Voltage Sampling Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 5.25 Voltage Queue Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 5.26 Voltage Averaging Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 5.27 Current Sense Sampling Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 5.28 Sense Queue Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 5.29 Current Sense Averaging Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 5.30 Current Sensing Sampling Time Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 5.31 Total Sampling Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 5.32 Current Sensing Range (Full Scale Range) Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 5.33 Peak Detection Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 5.34 PEAK_DET_TH[3:0] Bit Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 5.35 PEAK_DET_DUR[3:0] Bit Decode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Mlcnocmp
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
EMC1704 8 DS20005239A
DATASHEET
Table 5.36 Sense Voltage Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 5.37 VSENSE Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 5.38 Source Voltage Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 5.39 Power Ratio Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 5.40 VSENSE Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 5.41 Source Voltage Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 5.42 Critical Voltage Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 5.43 GPIO Config and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 5.44 Product Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 5.45 Product ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 5.46 Manufacturer ID Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 5.47 Revision Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 7.1 Customer Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Q MICFIDCHIF
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
DS20005239A 9 EMC1704
DATASHEET
Chapter 1 Pin Description
Figure 1.1 EMC1704-1 Pin Diagram 14-Pin SOIC
6‘ MICFIDCHIF ALERT THERM
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
EMC1704 10 DS20005239A
DATASHEET
Figure 1.2 EMC1704-2 Pin Diagram 16-Pin QFN 4mm x 4mm
Table 1.1 Pin Description for EMC1704-X
PIN
NUMBER
EMC1704-1
PIN
NUMBER
EMC1704-2 PIN NAME PIN FUNCTION PIN TYPE
2 1 VDD Positive power supply voltage Power (24V)
3 2 DP1 External Diode 1 positive (anode)
connection
AIO (2V)
4 3 DN1 External Diode 1 negative (cathode)
connection
AIO (2V)
5 4 DP2 / DN3 External Diode 2 positive (anode)
connection and External Diode 3
negative (cathode) connection
AIO (2V)
6 5 DN2 / DP3 External Diode 2 negative (cathode)
connection and External Diode 3
positive (anode) connection
AIO (2V)
7 6 ADDR_SEL Selects SMBus Address AI
EMC1704
16-QFN
2
3
4
5
6
7
12
11
10
DP1
DN1
VDD SMCLK
SMDATA
8
9
1
16
15
14
13
DN2 / DP3
DP2 / DN3
GPIO
ADDR_SEL
SENSE+
SENSE-
GND
THERM
TH_SEL
DUR_SEL
ALERT
Q MICFIDCHIF THERM ALERT
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
DS20005239A 11 EMC1704
DATASHEET
The pin types are described in Table 1.2. All pins labeled with (5V) are 5V tolerant. All pins labeled
with (24V) are 24V tolerant.
8 7 GPIO GPI - General Purpose Input DI (5V)
GPO - Open Drain General Purpose
output
OD (5V)
9 8 GND Ground Power
10 9 THERM Active low output - requires pull-up
resistor
OD (5V)
11 10 ALERT Active low output - requires pull-up
resistor
OD (5V)
12 11 SMDATA SMBus data input/output - requires
external pull-up resistor
DIOD (5V)
13 12 SMCLK SMBus clock input - requires
external pull-up resistor
DI (5V)
n/a 13 DUR_SEL Selects peak detector duration AI
n/a 14 TH_SEL Selects peak detector threshold AI
14 15 SENSE- Negative current sense measurement
point
AI (24V)
1 16 SENSE+ Positive current sense measurement
point
AI (24V)
Table 1.2 Pin Types
PIN TYPE DESCRIPTION
Power This pin is used to supply power or ground to the device.
AI Analog Input - this pin is used as an input for analog
signals.
AIO Analog Input / Output - this pin is used as an I/O for
analog signals.
OD Open Drain Digital Output - this pin is used as a digital
output. It is open drain and requires a pull-up resistor.
This pin is 5V tolerant.
DI Digital Input - this pin is used for digital inputs. This pin is
5V tolerant.
DIOD Open Drain Digital Input / Output - this pin is bi-directional.
It is open drain and requires a pull-up resistor. This pin is
5V tolerant.
Table 1.1 Pin Description for EMC1704-X (continued)
PIN
NUMBER
EMC1704-1
PIN
NUMBER
EMC1704-2 PIN NAME PIN FUNCTION PIN TYPE
6‘ MICRDCHIFI ALERT THERM
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
EMC1704 12 DS20005239A
DATASHEET
Chapter 2 Electrical Characteristics
Note 2.1 Stresses at or above those values listed could cause permanent damage to the device.
This is a stress rating only, and functional operation of the device at any other condition
above those indicated in the operation sections of this specification is not implied.
Prolonged stresses above the stated operating levels and below the Absolute Maximum
Ratings may degrade device performance and lead to permanent damage.
Note 2.2 All voltages are relative to ground.
Note 2.3 The Package Power Dissipation specification assumes a thermal via design with the
thermal landing be soldered to the PCB ground plane with four 12 mil vias (where
applicable).
Note 2.4 Junction to Ambient (JA) is dependent on the design of the thermal vias. Without thermal
vias and a thermal landing, the JA is approximately 60°C/W (EMC1704-2) including
localized PCB temperature increase.
Table 2.1 Absolute Maximum Ratings
Voltage on 5V tolerant pins -0.3 to 5.5 V
Voltage on 2V tolerant pins -0.3 to 2 V
Voltage on VDD, SENSE- and SENSE+ pins -0.3 to 26 V
Voltage on any other pin to GND -0.3 to 4 V
Voltage between Sense pins ( |(SENSE+ - SENSE-)| ) < 6 V
Package Power Dissipation 0.5W up to TA = 85°C W
Junction to Ambient (JA) (SOIC package) 78 °C/W
Junction to Ambient (JA) (QFN16 package) 58 °C/W
Operating Ambient Temperature Range -40 to 85 °C
Storage Temperature Range -55 to 150 °C
ESD Rating - SMCLK, SMDATA, ALERT, THERM pins - HBM 4000 V
ESD Rating - All other pins - HBM 2000 V
6‘ MICRDCHIP lrug voka ALERT ALERT THERM
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
DS20005239A 13 EMC1704
DATASHEET
2.1 Electrical Specifications
Table 2.2 Electrical Specifications
VDD = VBUS = 3V TO 24V, VPULLUP = 3V TO 5.5V, TA = -40°C TO 85°C,
ALL TYPICAL VALUES AT VDD = VPULLUP = 3.3V, VBUS = 12V, AND TA = 27°C UNLESS OTHERWISE NOTED.
CHARACTERISTIC SYMBOL MIN TYP MAX UNIT CONDITIONS
DC POWER
Supply Voltage VDD 324V
VDD Pin Supply
Current IDD
610 750 uA
Temp conversions at 0.0625
conversions / second,
dynamic averaging disabled
current sense active
650 950 uA
Temp conversions at 4
conversions / second,
dynamic averaging disabled
current sense active
950 1100 uA
Temp conversions at 8
conversions / second,
dynamic averaging enabled
current sense active
VDD Pin Supply
Current
IDD_
T_STANDBY
750 uA
Temp conversions disabled
(TMEAS / STOP = ‘1’)
current sense active
VDD Pin Supply
Current
IDD_ALL_
STANDBY
470 580 uA
Temp conversions disabled
(TMEAS / STOP = ‘1’)
Current sense disabled
(IMEAS / STOP = ‘1’)
SENSE+ Pin Bias
Current ISENSE+
90 uA VSENSE = 0V, VDD = 3V to 24V,
Current sense active
15 uA VSENSE = 0V, VDD = 3V to 24V,
current sense disabled
10 20 uA VDD = 0V
SENSE- Pin Bias
Current ISENSE-
10 uA VSENSE = 0V, VDD = 3V to 24V,
Current sense active
10 uA VSENSE = 0V, VDD = 3V to 24V,
current sense disabled
0uAV
DD = 0V
Pull-up Voltage VPULLUP 35.5V
Pull-up voltage for SMBus,
GPIO, ALERT, and THERM pins
Leakage Current (±)
ILEAK 5uA
ALERT, THERM, and GPIO
pins,
SMDATA and SMCLK pins
powered or unpowered,
TA < 85°C
6‘ MICRDCHIFI
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
EMC1704 14 DS20005239A
DATASHEET
CURRENT SENSE
Common Mode
Voltage VCM 324V
Voltage on SENSE+ and/or
SENSE- pins, referenced to
Ground
Differential Mode
Voltage VDIFF -6 +6 V Voltage between SENSE+ and
SENSE- pins
Full Scale Range (±)
(see Section 5.20)
FSR
0 10 mV 1 LSB = 4.885uV
0 20 mV 1 LSB = 9.77uV
0 40 mV 1 LSB = 19.54uV
0 80 mV 1 LSB = 39.08uV
Total Measurement
Error (±)
VSENSE
_ERR
0.5 1 % Total Error, FSR = 80mV
3%
Total Error, FSR = 10mV to
40mV
Offset Error (±) VSENSE
_OFF
3 LSB Offset Error, FSR = 80mV
Power Supply
Rejection
VSENSE
_PSR
-120 dB FSR = 10mV to 80mV,
3V < VDD < 24V
Common Mode
Rejection
VSENSE
_CMR
-110 dB FSR = 10mV to 80mV,
3V < VBUS < 24V
SOURCE VOLTAGE
Full Scale Voltage FSV 3 23.9883 V Voltage on SENSE+ pin
Total Measurement
Error (±)
(see Section 4.1.2)
VSOURCE
_ERR
0.2 0.5 %
POWER RATIO
Full Scale Range 0 100 % 1 LSB = 1.53m%
Total Measurement
Error (±)
PRATIO
_ERR
1.6 % FSR = 80mV
3 % FSR = 10mV to 40mV
CURRENT SENSE PEAK DETECTION
Peak Detector
Threshold Range VTH 10 85 mV Programmable via TH_SEL pin
(EMC1704-2 only)
Peak Detector
Duration Range TDUR 1 4096 ms Programmable via DUR_SEL
pin (EMC1704-2 only)
VSENSE Peak
Detection tFILTER 5us
Table 2.2 Electrical Specifications (continued)
VDD = VBUS = 3V TO 24V, VPULLUP = 3V TO 5.5V, TA = -40°C TO 85°C,
ALL TYPICAL VALUES AT VDD = VPULLUP = 3.3V, VBUS = 12V, AND TA = 27°C UNLESS OTHERWISE NOTED.
CHARACTERISTIC SYMBOL MIN TYP MAX UNIT CONDITIONS
6‘ MICRDCHIP
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
DS20005239A 15 EMC1704
DATASHEET
APPLICATION NOTE: The EMC1704 is trimmed at the 80mV range for best accuracy.
Threshold Accuracy
(±) VTH_ERR 25% V
TH = 80mV
EXTERNAL TEMPERATURE MONITORS
Temperature
Accuracy (±)
0.25 1 °C +20°C < TDIODE < +110°C
0°C < TA < 85°C
0.5 2 °C -40°C < TDIODE < 127°C
Temperature
Resolution 0.125 °C
Diode Decoupling
Capacitor CFILTER 2200 2700 pF Connected across external
diode, CPU, GPU, or AMD diode
Series Resistance
Canceled RSERIES 100 Ohm Sum of series resistance in both
DP and DN lines
INTERNAL TEMPERATURE MONITOR
Temperature
Accuracy (±)
0.25 1 °C -5°C < TA < 85°C
C-40°C < T
A < 85°C
Temperature
Resolution
0.125 °C
CONVERSION TIMES
First Conversion
Ready tCONV_T 180 300 ms
Time after power up before
temperature and voltage
measurements updated and
PRATIO updated
SMBus Delay tSMB_D 25 ms
Time before SMBus
communications should be sent
by host
DIGITAL I/O PINS (SMCLK, SMDATA, THERM, ALERT, GPIO)
Input High Voltage VIH 2.0 V
SMCLK, SMDATA, and GPIO
pins,
OD pins pulled up to VPULLUP
Input Low Voltage VIL 0.8 V
Output Low Voltage VOL 0.4 V OD pin pulled to VPULLUP
4 mA current sink
Table 2.2 Electrical Specifications (continued)
VDD = VBUS = 3V TO 24V, VPULLUP = 3V TO 5.5V, TA = -40°C TO 85°C,
ALL TYPICAL VALUES AT VDD = VPULLUP = 3.3V, VBUS = 12V, AND TA = 27°C UNLESS OTHERWISE NOTED.
CHARACTERISTIC SYMBOL MIN TYP MAX UNIT CONDITIONS
6‘ MICRDCHIFI
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
EMC1704 16 DS20005239A
DATASHEET
2.2 SMBus Electrical Specifications
Table 2.3 SMBus Electrical Specifications
VDD= VBUS = 3V to 24V, VPULLUP = 3V to 5.5V, TA = -40°C to 85°C Typical values are at TA = 27°C unless
otherwise noted.
CHARACTERISTIC SYMBOL MIN TYP MAX UNITS CONDITIONS
SMBUS INTERFACE
Input Capacitance CIN 410 pF
SMBUS TIMING
Clock Frequency fSMB 10 400 kHz
Spike Suppression tSP 50 ns
Bus Free Time Start to
Stop tBUF 1.3 us
Setup Time: Start tSU:STA 0.6 us
Setup Time: Stop tSU:STO 0.6 us
Data Hold Time tHD:DAT 0us
Data Setup Time tSU:DAT 0.6 us
Clock Low Period tLOW 1.3 us
Clock High Period tHIGH 0.6 us
Clock/Data Fall time tFALL 300 ns Min = 20+0.1CLOAD ns
Clock/Data Rise time tRISE 300 ns Min = 20+0.1CLOAD ns
Capacitive Load CLOAD 400 pF Total per bus line
Q MICRDCHIP
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
DS20005239A 17 EMC1704
DATASHEET
Chapter 3 Communications
3.1 System Management Bus Interface Protocol
The EMC1704 communicates with a host controller, such as an SMSC SIO, through the SMBus. The
SMBus is a two-wire serial communication protocol between a computer host and its peripheral
devices. A detailed timing diagram is shown in Figure 3.1. Stretching of the SMCLK signal is supported;
however, the EMC1704 will not stretch the clock signal.
3.1.1 SMBus Start Bit
The SMBus Start bit is defined as a transition of the SMBus Data line from a logic ‘1’ state to a logic
‘0’ state while the SMBus Clock line is in a logic ‘1’ state.
3.1.2 SMBus Address and RD / WR Bit
The SMBus Address Byte consists of the 7-bit client address followed by a 1-bit RD / WR indicator. If
this RD / WR bit is a logic ‘0’, the SMBus host is writing data to the client device. If this RD / WR bit
is a logic ‘1’, the SMBus host is reading data from the client device.
The EMC1704 SMBus address is determined by a single resistor connected between ground and the
ADDR_SEL pin as shown in Table 3 . 1 .
Figure 3.1 SMBus Timing Diagram
Table 3.1 ADDR_SEL Resistor Setting
RESISTOR (5%) SMBUS ADDRESS RESISTOR (5%) SMBUS ADDRESS
0 1001_100(r/w) 1600 0101_000(r/w)
100 1001_101(r/w) 2000 0101_001(r/w)
180 1001_110(r/w) 2700 0101_010(r/w)
300 1001_111(r/w) 3600 0101_011(r/w)
430 1001_000(r/w) 5600 0101_100(r/w)
SMDATA
SMCLK
TBUF
PS S - Start Condition P - Stop Condition PS
THIGH
TLOW THD:STA TSU:STO
THD:STA THD:DAT
TSU:DAT TSU:STA
TFALL
TRISE
Q MICFIDCHIP ALERT
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
EMC1704 18 DS20005239A
DATASHEET
All SMBus Data bytes are sent most significant bit first and composed of 8-bits of information.
3.1.3 SMBus ACK and NACK Bits
The SMBus client will acknowledge all data bytes that it receives (as well as the client address if it
matches and the ARA address if the ALERT pin is asserted). This is done by the client device pulling
the SMBus Data line low after the 8th bit of each byte that is transmitted.
The host will NACK (not acknowledge) the data received from the client by holding the SMBus data
line high after the 8th data bit has been sent.
3.1.4 SMBus Stop Bit
The SMBus Stop bit is defined as a transition of the SMBus Data line from a logic ‘0’ state to a logic
‘1’ state while the SMBus clock line is in a logic ‘1’ state. When the EMC1704 detects an SMBus Stop
bit, and it has been communicating with the SMBus protocol, it will reset its client interface and prepare
to receive further communications.
3.1.5 SMBus Time-out
The EMC1704 includes an SMBus time-out feature. Following a 30ms period of inactivity on the
SMBus, the device will time-out and reset the SMBus interface.
The time-out functionality defaults to disabled and can be enabled by writing to the TIMEOUT bit (see
Section 5.12).
3.1.6 SMBus and I2C Compliance
The major differences between SMBus and I2C devices are highlighted here. For complete compliance
information, refer to the SMBus 2.0 specification.
1. Minimum frequency for SMBus communications is 10kHz.
2. The client protocol will reset if the clock is held at a logic ‘0’ for longer than 30ms. This time-out
functionality is disabled by default.
3. The client protocol will reset if both the clock and data lines are held at a logic ‘1’ for longer than
150us. This function is disabled by default.
4. I2C devices do not support the Alert Response Address functionality (which is optional for SMBus).
560 1001_001(r/w) 9100 0101_100(r/w)
750 1001_010(r/w) 20000 0101_101(r/w)
1270 1001_011(r/w) Open 0011_000(r/w)
Table 3.1 ADDR_SEL Resistor Setting (continued)
RESISTOR (5%) SMBUS ADDRESS RESISTOR (5%) SMBUS ADDRESS
Q MICROCHIF
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
DS20005239A 19 EMC1704
DATASHEET
3.2 SMBus Protocols
The EMC1704 is SMBus 2.0 compatible and supports Send Byte, Read Byte, Receive Byte, Write
Byte, Block Read, and Block Write as valid protocols. It will respond to the Alert Response Address
protocol but is not in full compliance.
All of the protocols listed below use the convention in Table 3.2.
3.2.1 Write Byte
The Write Byte is used to write one byte of data to the registers, as shown in Tab le 3.3:
3.2.2 Read Byte
The Read Byte protocol is used to read one byte of data from the registers, as shown in Ta b l e 3 . 4 .
3.2.3 Send Byte
The Send Byte protocol is used to set the internal address register pointer to the correct address
location. No data is transferred during the Send Byte protocol, as shown in Tab le 3.5.
3.2.4 Receive Byte
The Receive Byte protocol is used to read data from a register when the internal register address
pointer is known to be at the right location (e.g. set via Send Byte). This is used for consecutive reads
Table 3.2 Protocol Format
DATA SENT
TO DEVICE
DATA SENT TO
THE HOST
# of bits sent # of bits sent
Table 3.3 Write Byte Protocol
START
SLAVE
ADDRESS WR ACK
REGISTER
ADDRESS ACK
REGISTER
DATA ACK STOP
1 -> 0 YYYY_YYY 0 0 XXh 0 XXh 0 0 -> 1
Table 3.4 Read Byte Protocol
START SLAVE
ADDRESS
WR ACK Register
Address
ACK START Slave
Address
RD ACK Register
Data
NACK STOP
1 -> 0 YYYY_YYY 0 0 XXh 0 0 -> 1 YYYY_YYY 1 0 XXh 1 0 -> 1
Table 3.5 Send Byte Protocol
START
SLAVE
ADDRESS WR ACK
REGISTER
ADDRESS ACK STOP
1 -> 0 YYYY_YYY 0 0 XXh 0 0 -> 1
G MICFIDCHIP ALERT ALERT
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
EMC1704 20 DS20005239A
DATASHEET
of the same register, as shown in Tab l e 3.6 .
3.2.5 Block Write
The Block Write is used to write multiple data bytes to a group of contiguous registers, as shown in
Table 3.7. It is an extension of the Write Byte Protocol.
3.2.6 Block Read
The Block Read is used to read multiple data bytes from a group of contiguous registers, as shown in
Table 3.8. It is an extension of the Read Byte Protocol.
3.2.7 Alert Response Address
The ALERT output can be used as a processor interrupt or as an SMBus Alert when configured to
operate as an interrupt.
When it detects that the ALERT pin is asserted, the host will send the Alert Response Address (ARA)
to the general address of 0001_100xb. All devices with active interrupts will respond with their client
address, as shown in Tab le 3 .9.
Table 3.6 Receive Byte Protocol
START
SLAVE
ADDRESS RD ACK REGISTER DATA NACK STOP
1 -> 0 YYYY_YYY 1 0 XXh 1 0 -> 1
Table 3.7 Block Write Protocol
START
SLAVE
ADDRESS WR ACK
REGISTER
ADDRESS ACK
REGISTER
DATA ACK
1 ->0 YYYY_YYY 0 0 XXh 0 XXh 0
REGISTER
DATA ACK
REGISTER
DATA ACK . . .
REGISTER
DATA ACK STOP
XXh 0 XXh 0 . . . XXh 0 0 -> 1
Table 3.8 Block Read Protocol
START SLAVE
ADDRESS
WR ACK REGISTER
ADDRESS
ACK START SLAVE
ADDRESS
RD ACK REGISTER
DATA
1->0 YYYY_YYY 0 0 XXh 0 1 ->0 YYYY_YYY 1 0 XXh
ACK REGISTER
DATA
ACK REGISTER
DATA
ACK REGISTER
DATA
ACK . . . REGISTER
DATA
NACK STOP
0 XXh 0 XXh 0 XXh 0 . . . XXh 1 0 -> 1
Table 3.9 Alert Response Address Protocol
START
ALERT
RESPONSE
ADDRESS RD ACK
DEVICE
ADDRESS NACK STOP
Q MICRDCHIP ALERT ALERT
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
DS20005239A 21 EMC1704
DATASHEET
The EMC1704 will respond to the ARA in the following way if the ALERT pin is asserted.
1. Send Slave Address and verify that full slave address was sent (i.e. the SMBus communication
from the device was not prematurely stopped due to a bus contention event).
2. Set the MASK bit to clear the ALERT pin.
1 -> 0 0001_100 1 0 YYYY_YYY 1 0 -> 1
Table 3.9 Alert Response Address Protocol
Q MICFIDCHIFI ALERT
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
EMC1704 22 DS20005239A
DATASHEET
Chapter 4 General Description
The EMC1704 is a combination high-side current sensing device with precision voltage and
temperature measurement capabilities. It measures the voltage developed across an external sense
resistor to represent the high-side current of a battery or voltage regulator. The EMC1704 also
measures the source voltage and uses these measured values to present a proportional power
calculation. The EMC1704 contains additional bi-directional peak detection circuitry to flag
instantaneous current spikes with programmable time duration and magnitude thresholds. Finally, the
EMC1704 includes up to three (3) external diode channels and an internal diode for temperature
measurement.
The EMC1704 current-sense measurement converts differential input voltage measured across an
external sense resistor to a proportional output voltage. This voltage is digitized using a variable
resolution (13-bit to 15-bit) Sigma-Delta ADC and transmitted via the SMBus or I2C protocol. The
current range allows for large variations in measured current with high accuracy and low voltage drop
across the resistor.
The supply voltage is also measured and stored. When combined with the sense resistor voltage
measurement the power provided from the source can be determined. Programmable limits on both
voltage and current levels are used to generate an interrupt.
The EMC1704 has two levels of monitoring. The first provides a maskable ALERT signal to the host
when the measured temperatures or voltages meet or exceed user programmable limits. This allows
the EMC1704 to be used as an independent thermal watchdog to warn the host of temperature hot
spots without direct control by the host. The second level of monitoring provides a non maskable
interrupt on the THERM pin if the measured values meet or exceed a second programmable limit.
The temperature measurement includes advanced features such as Resistance Error Correction
(REC), Beta Compensation (to support CPU diodes requiring the BJT/transistor model including 45nm
and 65nm processors) and automatic diode type detection. These features combine to provide a robust
solution for complex environmental monitoring applications.
A system diagram is shown in Figure 4.1.
G MICFIDCHIP a? 1 Opmonal i N An‘l-para‘le‘ 1 made ALERT ALERT THERM
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
DS20005239A 23 EMC1704
DATASHEET
4.1 Source Monitoring
The EMC1704 includes circuitry for both source current sensing and source voltage measurement.
From these measurements, a ratiometric value corresponding to the power delivered at the SENSE+
pin is provided.
4.1.1 Current Measurement
The EMC1704 includes a high-side current sensing circuit. This circuit measures the voltage, VSENSE,
induced across a fixed external current sense resistor, RSENSE, and stores a representative voltage as
a signed 11-bit number in the Sense Voltage Registers (see Section 5.22).
This circuitry is able to measure the direction of current flow (from SENSE+ to SENSE- or from
SENSE- to SENSE+). Current flowing from SENSE+ to SENSE- is defined as positive current. Current
flowing from SENSE- to SENSE+ is defined as negative.
The EMC1704 contains user programmable bipolar Full Scale Sense Ranges (FSSR) of ±10mV,
±20mV, ±40mV, or ±80mV (see Section 5.20). The default for this setting is ±80mV.
Each VSENSE measurement is averaged over a user programmable time (see Section 5.20). It is
compared against programmable high and low limits (see Section 5.25). If VSENSE exceeds (or drops
below) the respective limits, the ALERT pin may be asserted (the default operation is to enable current
sense interrupts on the ALERT pin).
The EMC1704 also contains user programmable current peak detection circuitry (see Section 4.1.4)
that will assert the THERM pin if a current spike is detected larger than the programmed threshold and
of longer duration than the programmed time. This circuitry is independent of VSENSE.
Figure 4.1 EMC1704 System Diagram
EMC1704
Host
DP1
DN1
SMDATA
SMCLK
GPIO
ALERT
DP2 / DN3
DN2 / DP3
2N3904 typ.
2N3904 typ.
THERM
Optional
Anti-parallel
Diode
VDD
ADDR_SEL
TH_SEL**
DUR_SEL**
** EMC1704-2 only
GND
VDD*
* Can either be DC Supply voltage or a separate supply
DC Load
DC Supply
Sense Resistor
SENSE-SENSE+
3.0V to 5.5V
Q MICFIDCHIP THERM ALERT
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
EMC1704 24 DS20005239A
DATASHEET
Full Scale Current (FSC) can be calculated from:
Actual source current through RSENSE can then be calculated using:
For example: Suppose the system is drawing 1.65A through a 10m resistor and the FSR is set for
20mV. Therefore, by Equation [1], the FSC is 2A.
For a positive voltage the Sense Voltage Registers are read, ignoring the lower four bits since they are
always zero, as 69_8h (0110_1001_1000b or 1688d) which is 82.5% of the full scale source current.
This results in a calculated source current of 1.649A using Equation [2].
For a negative voltage the Sense Voltage Registers are read as 96_8h, also ignoring the lower four
bits since they are always zero. To calculate source current the binary value is first converted from
two’s complement by inverting the bits and adding one:
96_8h = 1001_0110_1000b. Inverting equals 0110_1001_0111b (69_7h) and adding one gives
0110_1001_1000b (69_8h).
This results in the same calculated value as in the positive voltage case.
4.1.2 Voltage Measurement
Source voltage is measured on the supply side of the RSENSE resistor (SENSE+) and stored as an
unsigned 11-bit number in the Source Voltage Registers as VSOURCE (see Section 5.23).
Each VSOURCE measurement is averaged over a user programmable time (see Section 5.6 and
Section 5.19). The measurement is delayed by the programmed conversion rate. VSOURCE is
compared against programmable high, low, and critical limits (see Section 5.15, Section 5.16, and
Section 5.17). If the value meets or exceeds the high limits or drops below the low limits, the ALERT
pin may be asserted (default is to enable this function). If the value meets or exceeds the critical limit,
the THERM pin will be asserted (see Section 5.27).
Full Scale Voltage (FSV) is given by the maximum value of the Source Voltage Registers:
where:
[1]
FSC is the Full-Scale Current
FSR, the Full Scale Range, is either
10mV, 20mV, 40mV or 80mV (see
Section 5.20)
RSENSE is the external sense resistor
value
where:
[2]
ISOURCE is the actual source current
FSC is the Full-Scale Current value
(from Equation [1])
VSENSE is the value read from the Sense
Voltage Registers, ignoring the four
lowest bits which are always zero (see
Section 5.22)
where:
[3]
FSV is the Full-Scale Voltage (a
constant)
FSC FSR
RSENSE
---------------------
=
ISOURCE FSC VSENSE
2047
---------------------=
FSV 23.9883V=
Q MICFIDCHIP
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
DS20005239A 25 EMC1704
DATASHEET
Actual source voltage at the SENSE+ pin can be calculated using:
For example: Suppose that the actual source voltage is 10.65V. The Source Voltage Registers are read
as VSOURCE = 71_Ah (0111_0001_1010b or 1818d) which is 44.4% of the full scale source voltage.
This results in a calculated source voltage of 10.65V using Equation [4].
Note that the actual source voltage may also be determined by scaling each bit set by the indicated
bit weighting as described in Section 5.23.
4.1.3 Power Calculation
The EMC1704 may be used to determine the average power provided at the source side of RSENSE
(SENSE+) using the value, PRATIO, contained in the Power Ratio Registers (see Section 5.24). The
value represents the % of maximum calculable power.
PRATIO is mathematically generated by multiplying the absolute values of VSENSE and VSOURCE (see
Section 4.1.1 and Section 4.1.2) and stored as a shifted 16-bit unsigned number. PRATIO is updated
whenever either VSENSE or VSOURCE is updated.
Full Scale Power can be calculated from:
Actual power drawn from the source can be calculated using:
where:
[4]
Source Voltage is the voltage at the
SENSE+ pin
FSV is the Full-Scale Voltage (from
Equation [3])
VSOURCE is the digital value read from
the Source Voltage Registers. Note that
the lowest five bits are always zero (see
Section 5.23)
where:
[5]
FSP is the Full-Scale Power
FSC is the Full-Scale Current (from
Equation [1])
FSV is the Full-Scale Voltage (from
Equation [3])
where:
[6]
PSOURCE is the actual power
provided by the source
measured at SENSE+
FSP is the Full-Scale Power
(from Equation [5])
PRATIO is the value read from
the Power Ratio Registers
(see Section 5.24)
Source Voltage FSV VSOURCE
4 094
--------------------------=
FSP FSC FSV=
PSOURCE FSP PRATIO
65 535
-------------------=
Q MICFIDCHIFI THERM THERM ALERT ALERT ALERT ALERT
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
EMC1704 26 DS20005239A
DATASHEET
For example: Suppose that the actual source voltage is 10.65V and the source current through a 10m
resistor is 1.65A. The FSC value is 2A per Equation [1]; thus, the expected power is 17.573W which
is 36.6% of the FSP value.
Reading the Power Ratio Registers will report PRATIO as 24,003d (0101_1101_1100_0011b or
5D_C3h), which is 36.6% of the full scale source power. This results in a calculated source power of
17.6W.
4.1.4 Current Peak Detection
The EMC1704-2 includes a hardware set instantaneous current peak detector (this circuitry is also
available in the EMC1704-1 but must be configured via SMBus). The peak detector threshold and
duration values may also be set via the SMBus.
The peak detector supports detection of current spikes that occur faster than the minimum current
sensing conversion time. This allows quick reaction to events requiring system-level response. The
circuitry compares the measured current against a user-defined threshold value and user-defined time
duration. If the measured current exceeds the threshold, an internal timer is started. If the timer
reaches the programmed duration, the THERM pin is asserted (see Figure 4.2 for an example of peak
current detection) and the PEAK status bit set.
The THERM pin will remain asserted until the Peak is no longer detected at which point it will be
released. The PEAK status bit will likewise be cleared.
The Peak Detection circuitry may also assert the ALERT pin. In this case, the ALERT pin must be
configured to operate in Comparator mode. If the ALERT pin is configured to operate in Interrupt mode,
the Peak Detection circuitry will not cause the ALERT pin to be asserted.
The Peak Detection circuitry includes filtering (tFILTER). When the instantaneous current exceeds the
threshold, it must drop below the threshold for a period of time greater than tFILTER before the timer is
reset. The Peak Detection circuitry works for current flowing in either direction through the sense
resistor (RSENSE).
APPLICATION NOTE: The Peak Detector circuitry works independently of the current measurement integration.
6‘ MICFIDCHIFI
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
DS20005239A 27 EMC1704
DATASHEET
The peak detector threshold is determined upon device power up by the value of the resistor
connected between the TH_SEL pin and ground (for EMC1704-2 only) or via the SMBus. The resistor
selects one of 16 different VSENSE measurement limits (from 10mV to 85mV) as shown in Table 4.1.
The peak detector duration is determined upon device power up by the value of the resistor between
the DUR_SEL pin and ground (for EMC1704-2 only) or via the SMBus. The resistor selects one of 16
different time durations from 1 ms to 4.096s as shown in Ta b l e 4 . 2 .
Figure 4.2 Peak Detection Example
Table 4.1 TH_SEL Resistor Setting (EMC1704-2 only)
RESISTOR (5%)
PEAK DETECTION
THRESHOLD RESISTOR (5%)
PEAK DETECTION
THRESHOLD
0 10mV 1600 50mV
100 15mV 2000 55mV
180 20mV 2700 60mV
300 25mV 3600 65mV
430 30mV 5600 70mV
560 35mV 9100 75mV
750 40mV 20000 80mV
1270 45mV Open 85mV
THERM Pin
Peak
Detector
Threshold
t < tFILTER
t > tFILTER
t < tDURATION t > tDURATION
t < tFILTER
t > tFILTER
Q MICFIDCHIP ALERT THERM ALERT THERM ALERT THERM ALERT VPULLU ALERT
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
EMC1704 28 DS20005239A
DATASHEET
4.2 VDD Biasing Options
The wide device operating voltage range allows the EMC1704 to be powered from either the source
voltage or an external supply. The EMC1704 contains circuitry to detect the voltage supply level on
the VDD pin and enable an internal regulator as necessary.
4.3 Modes of Operation
The EMC1704 has multiple modes of operation as described here:
Fully Active - In this mode of operation, the device is measuring all temperature channels, source
voltage, and sense voltage. All data is updated at the end of the respective conversion and the
limits are checked. Writing to the One-Shot register will have no effect.
Current Sense only - In this mode of operation, the device is measuring source voltage and sense
voltage only. The temperature data is not updated. VSOURCE and VSENSE data are updated at the
end of the respective conversion and the limits are checked. Writing to the One-Shot register will
update the temperature measurements. This one-shot measurement may cause the ALERT or
THERM pins to be asserted if the measured temperature violates the respective limits.
Temperature only - In this mode of operation, the device is measuring the temperature channels
only. VSOURCE and VSENSE data are not updated. The temperature data is updated at the end of
the conversion and the limits are checked. Writing to the One-Shot register will update VSOURCE
and VSENSE. This one-shot measurement may cause the ALERT or THERM pins to be asserted if
the measured voltage or current sense readings meet or exceed the respective limits.
Standby (Stop) - In this mode of operation, the majority of circuitry is powered down to reduce
supply current. The temperature, source voltage, and sense voltage measurements are not
updated and the limits are not checked. In this mode of operation, the SMBus is fully active and
the part will return requested data. Writing to the One-Shot register (see Section 5.8) will enable
the device to update all measurement channels (temperature, VSOURCE, and VSENSE). This one-
shot measurement may cause the ALERT or THERM pins to be asserted if any of the measured
values violate their respective limits. Once all the channels are updated, the device will return to
the Standby mode.
4.4 ALERT Output
The ALERT pin is an open drain output and requires a pull-up resistor to VPULLUP and has two modes
of operation: Interrupt mode and Comparator mode. The mode of the ALERT output is selected via
Table 4.2 DUR_SEL Resistor Setting (EMC1704-2 only)
RESISTOR (5%)
PEAK DETECTION MINIMUM
DURATION
(TDURATION) RESISTOR (5%)
PEAK DETECTION MINIMUM
DURATION
(TDURATION)
0 1ms 1600 384ms
100 5ms 2000 512ms
180 26 ms 2700 768ms
300 51 ms 3600 1024ms
430 77 ms 5600 1536ms
560 102ms 9100 2048ms
750 128ms 20000 3072ms
1270 256ms Open 4096ms
Q MICFIDCHIFI ALERT ALERT ALERT ALERT 2 ALERT ALERT 2 ALERT ALERT ALERT ALERT ALERT ALERT ALERT ALERT ALERT ALERT ALERT ALERT ALERT ALERT ALERT ALERT W W THERM THERM THERM THERM THERM
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
DS20005239A 29 EMC1704
DATASHEET
the ALERT / COMP bit in the Configuration Register (see Section 5.5).
The ALERT pin modes apply to the High Limit only for all channels. The Low Limits and diode faults
will always cause the ALERT pin to behave as if it were in Interrupt mode.
The ALERT pin is used as an interrupt signal or as an SMBus Alert signal that allows an SMBus slave
to communicate an error condition to the master. One or more SMBus Alert outputs can be hard-wired
together.
4.4.1 ALERT Pin Interrupt Mode
When configured to operate in Interrupt mode, the ALERT pin asserts low when an out-of-limit
measurement (> high limit or < low limit) is detected on any temperature measurement and the
consecutive alert queue has been filled. The ALERT pin will also be asserted if a diode fault is
detected.
Additionally, the ALERT pin may be asserted if the measured current or the source voltage are out of
limit (> high limit or < low limit).
The ALERT pin will remain asserted as long as an out-of-limit condition remains. Once the out-of-limit
condition has been removed, the ALERT pin will remain asserted until the appropriate status bits are
cleared. The pin can be masked by setting the MASK_ALL bit. Once the ALERT pin has been masked,
it will be de-asserted and remain de-asserted until the MASK_ALL bit is cleared by the user. Any
interrupt conditions that occur while the ALERT pin is masked will update the Status Register normally.
When the ALERT pin is configured to operate in Interrupt mode, the Peak Detector circuitry will not
generate interrupts when a current peak is detected.
4.4.2 ALERT Pin Comparator Mode
When the ALERT pin is configured to operate in Comparator mode, it will be asserted if any of the
measured temperatures meets or exceeds the respective high limit. The ALERT pin will remain
asserted until all temperatures drop below the corresponding high limit minus the Tcrit Hysteresis
value.
Additionally, the ALERT pin may be asserted if the measured current or the source voltage meet or
exceed their respective high limit. The ALERT pin will remain asserted until the measured values drop
below the corresponding high limit minus the Vcrit Hysteresis value (see Section 5.27).
When the ALERT pin is asserted in Comparator mode, the corresponding high limit status bits will be
set. Reading these bits will not clear them until the ALERT pin is deasserted. Once the ALERT pin is
deasserted, the status bits will be automatically cleared.
The MASK_ALL (see Section 5.5) bit will not block the ALERT pin in this mode; however, individual
mask bits (see Section 5.11) will control the respective events that will assert the ALERT pin.
When the ALERT pin is configured to operate in Comparator mode and the Peak Detector circuitry is
linked to the ALERT pin, an interrupt will be generated when a current peak is detected (see
Section 5.19).
4.5 THERM Output
The THERM output is asserted independently of the ALERT output and cannot be masked. Whenever
any of the measured temperatures meets or exceeds the user programmed Tcrit Limit values for the
programmed number of consecutive measurements, the THERM output is asserted. Once it has been
asserted, it will remain asserted until all measured temperatures drops below the Tcrit Limit minus the
Tcrit Hysteresis (also programmable).
Additionally, the THERM pin will be asserted if the current sense Peak Detection circuitry has detected
a current spike (see Section 4.1.4). The THERM pin will remain asserted so long as the Peak Detection
circuitry continues to detect excessive instantaneous current (greater than the programmed threshold).
As well, the THERM pin will be asserted if the measured current or source voltage meet or exceed
the user programmed Vcrit Limit values. In this case, the THERM pin will remain asserted until all
measured voltages drop below the Vcrit Limit minus the Vcrit Hysteresis (see Section 5.27).
Q MICFIDCHIFI ALERT THERM
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
EMC1704 30 DS20005239A
DATASHEET
4.6 Temperature Measurement
The EMC1704 can monitor the temperature of up to three externally connected diodes. Each external
diode channel is configured with Resistance Error Correction and Beta Compensation based on user
settings and system requirements.
The EMC1704 also measures the internal or ambient temperature.
The device contains programmable High, Low, and Tcrit limits for all measured temperature channels.
If the measured temperature drops below the Low limit or above the High limit, the ALERT pin can be
asserted (based on user settings). If the measured temperature meets or exceeds the Tcrit limit, the
THERM pin is asserted unconditionally, providing two tiers of temperature detection.
4.6.1 Resistance Error Correction
The EMC1704 includes active Resistance Error Correction to remove the effect of up to 100 ohms of
series resistance. Without this automatic feature, voltage developed across the parasitic resistance in
the remote diode path causes the temperature to read higher than what the true temperature is. The
error induced by parasitic resistance is approximately +0.7°C per ohm. Sources of series resistance
include bulk resistance in the remote temperature transistor junctions, series resistance in the CPU
resistance due to off-board connections, and resistance in the printed circuit board traces and package
leads. Resistance Error Correction in the EMC1704 eliminates the need to characterize and
compensate for parasitic resistance in the remote diode path.
The Resistance Error Correction can be disabled for each channel.
APPLICATION NOTE: When measuring AMD diodes, disable REC.
4.6.2 Beta Compensation
The forward current gain, or beta, of a transistor is not constant as emitter currents change. The
variation in beta causes an error in temperature reading. Compensating for this error is also known as
implementing the BJT or transistor model for temperature measurement.
For discrete transistors configured with the collector and base shorted together, the beta is generally
sufficiently high such that the percent change in beta variation is very small. For example, a 10%
variation in beta for two forced emitter currents with a transistor whose ideal beta is 50 would contribute
approximately 0.25°C error at 100°C. However for substrate transistors where the base-emitter junction
is used for temperature measurement and the collector is tied to the substrate, the proportional beta
variation will cause large error. For example, a 10% variation in beta for two forced emitter currents
with a transistor whose ideal beta is 0.5 would contribute approximately 8.25°C error at 100°C.
The Beta Compensation circuitry in the EMC1704 corrects for this beta variation to eliminate any error
which would normally be induced. It automatically detects the appropriate beta setting to use and will
properly recognize and measure a discrete diode.
4.6.3 Ideality Factor
The EMC1704 is designed for external diodes with an ideality factor of 1.008. Not all external diodes,
processor or discrete, will have this exact value. This variation of the ideality factor introduces error in
the temperature measurement which must be corrected for. This correction is typically done using
programmable offset registers. Since an ideality factor mismatch introduces an error that is a function
of temperature, this correction is only accurate within a small range of temperatures. To provide
maximum flexibility to the user, the EMC1704 provides a register for each external diode where the
ideality factor of the diode used may be programmed to eliminate errors across all temperatures.
APPLICATION NOTE: When monitoring a substrate transistor or CPU diode and beta compensation is enabled, the
Ideality Factor should not be adjusted. Beta Compensation automatically corrects for most
ideality errors.
Q MICFIDCHIP IIIIIIIIII llllllllll |||||||||| \\\\\\\\\
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
DS20005239A 31 EMC1704
DATASHEET
4.6.4 Dynamic Averaging
The EMC1704 supports dynamic averaging. When enabled, this feature changes the conversion time
for all channels based on the selected conversion rate. This essentially increases the averaging factor
as shown in Table 4.3. The benefits of Dynamic Averaging are improved noise rejection due to the
longer integration time as well as less random variation on the temperature measurement.
4.7 Diode Connections
For the EMC1704, all of the external diode channels support any of the diode connections shown in
Figure 4.3.
4.7.1 Anti-Parallel Diodes
The EMC1704 supports connecting two external diodes to the DN2 / DP3 and DP2 / DN3 pins. This
second diode is connected in an anti-parallel configuration with respect to the first diode. When the
external diode 2 channel is measured, the anti-parallel diode will be reverse biased. Likewise, when
the External Diode 3 channel is measured, the first diode will be reverse biased. CPU diodes should
not be used with anti-parallel diode connections.
Table 4.3 Dynamic Averaging Behavior
CONVERSION RATE
AVERAGING FACTOR (RELATIVE TO 11-BIT CONVERSION)
DYNAMIC AVERAGING
ENABLED
DYNAMIC AVERAGING
DISABLED
< 1 / sec 16x 1x
1 / sec 8x 1x
2 / sec 4x 1x
4 / sec 2x 1x
8 / sec 1x 1x
Figure 4.3 Diode Connections
Local
Ground
to DP
Typical remote
substrate transistor
i.e. CPU substrate PNP
Typical remote
discrete PNP transistor
i.e. 2N3906
Typical remote
discrete NPN transistor
i.e. 2N3904
to DN
to DP
to DN
to DP
to DN
to
DP /
DN
to
DN /
DP
Anti-parallel diodes using
discrete NPN transistors
Diode 1Diode 2
MICFIDCHIP
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
EMC1704 32 DS20005239A
DATASHEET
4.7.2 Diode Faults
The EMC1704 actively detects an open and short condition on each measurement channel. When a
diode fault is detected, the temperature data MSByte is forced to a value of 80h and the FAULT bit is
set in the Status Register. When an external diode channel is configured to operate in APD mode, the
circuitry will detect independent open fault conditions; however, a short condition will be shared
between the APD channels.
Q MICFIDCHIP
High-Side Current-Sense and Multiple 1°C Temperature Monitor
DS20005239A 33 EMC1704
DATASHEET
Chapter 5 Register Description
The registers shown in Ta bl e 5 . 1 are accessible through the SMBus. An entry of ‘-’ indicates that the
bit is not used and will always read ‘0’.
Table 5.1 Register Set in Hexadecimal Order
REGISTER
ADDRESS R/W REGISTER NAME FUNCTION
DEFAULT
VALUE PAGE
00h R Internal Diode Data
High Byte
Stores the integer data for the
Internal Diode (mirrored at address
38h)
00h Page 38
01h R External Diode 1
Data High Byte
Stores the integer data for External
Diode 1 (mirrored at address 3Ah)
00h Page 38
02h R Status Stores the status bits for the
Internal Diode and External Diodes
(mirrored at address 34h)
00h Page 39
03h R/W Configuration Controls the general operation of
the device (mirrored at address
09h)
00h Page 40
04h R/W Conversion Rate Controls the conversion rate for
updating measurement data
(mirrored at address 0Ah)
06h
(4/sec)
Page 41
05h R/W Internal Diode High
Limit
Stores the 8-bit high limit for the
Internal Diode (mirrored at address
0Bh)
55h
(85°C)
Page 41
06h R/W Internal Diode Low
Limit
Stores the 8-bit low limit for the
Internal Diode (mirrored at address
0Ch)
80h
(-128°C)
Page 41
07h R/W External Diode 1
High Limit High Byte
Stores the integer portion of the
high limit for External Diode 1
(mirrored at register 0Dh)
55h
(85°C)
Page 41
08h R/W External Diode 1 Low
Limit High Byte
Stores the integer portion of the
low limit for External Diode 1
(mirrored at register 0Eh)
80h
(-128°C)
Page 41
09h R/W Configuration Controls the general operation of
the device (mirrored at address
03h)
00h Page 40
0Ah R/W Conversion Rate Controls the conversion rate for
updating measurement data
(mirrored at address 04h)
06h
(4/sec)
Page 41
0Bh R/W Internal Diode High
Limit
Stores the 8-bit high limit for the
Internal Diode (mirrored at address
05h)
55h
(85°C)
Page 41
0Ch R/W Internal Diode Low
Limit
Stores the 8-bit low limit for the
Internal Diode (mirrored at address
06h)
80h
(-128°C)
Page 41
Q MICFIDCHIP
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
EMC1704 34 DS20005239A
DATASHEET
0Dh R/W External Diode 1
High Limit High Byte
Stores the integer portion of the
high limit for External Diode 1
(mirrored at register 07h)
55h
(85°C)
Page 41
0Eh R/W External Diode 1 Low
Limit High Byte
Stores the integer portion of the
low limit for External Diode 1
(mirrored at register 08h)
80h
(-128°C)
Page 41
0Fh W One-Shot A write to this register initiates a
one-shot update.
00h Page 43
10h R External Diode 1
Data Low Byte
Stores the fractional data for
External Diode 1 (mirrored at
address 3Bh)
00h Page 38
13h R/W External Diode 1
High Limit Low Byte
Stores the fractional portion of the
high limit for External Diode 1
00h Page 41
14h R/W External Diode 1 Low
Limit Low Byte
Stores the fractional portion of the
low limit for External Diode 1
00h Page 41
15h R/W External Diode 2
High Limit High Byte
Stores the integer portion of the
high limit for External Diode 2
55h
(85°C)
Page 41
16h R/W External Diode 2 Low
Limit High Byte
Stores the integer portion of the
low limit for External Diode 2
80h
(-128°C)
Page 41
17h R/W External Diode 2
High Limit Low Byte
Stores the fractional portion of the
high limit External Diode 2
00h Page 41
18h R/W External Diode 2 Low
Limit Low Byte
Stores the fractional portion of the
low limit for External Diode 2
00h Page 41
19h R/W External Diode 1 Tcrit
Limit
Stores the 8-bit critical temperature
limit for External Diode 1
64h
(100°C)
Page 43
1Ah R/W External Diode 2 Tcrit
Limit
Stores the 8-bit critical temperature
limit for External Diode 2
64h
(100°C)
Page 43
1Bh R-C External Diode Fault Stores status bits indicating which
external diode detected a diode
fault
00h Page 44
1Fh R/W Channel Mask
Register
Controls the masking of individual
channels
00h Page 44
20h R/W Internal Diode Tcrit
Limit
Stores the 8-bit critical temperature
limit for the Internal Diode
64h
(100°C)
Page 43
21h R/W Tcrit Hysteresis Stores the 8-bit hysteresis value
that applies to all THERM limits
0Ah
(10°C)
Page 43
22h R/W Consecutive Alert Controls the number of out-of-limit
conditions that must occur before
an interrupt is asserted
70h Page 45
23h R External Diode 2
Data High Byte
Stores the integer data for External
Diode 2 (mirrored at register 3Ch)
00h Page 38
24h R External Diode 2
Data Low Byte
Stores the fractional data for
External Diode 2 (mirrored at
register 3Dh)
00h Page 38
Table 5.1 Register Set in Hexadecimal Order (continued)
REGISTER
ADDRESS R/W REGISTER NAME FUNCTION
DEFAULT
VALUE PAGE
Q MICFIDCHIP
High-Side Current-Sense and Multiple 1°C Temperature Monitor
DS20005239A 35 EMC1704
DATASHEET
25h R/W External Diode 1
Beta Configuration
Stores the Beta Compensation
circuitry settings for External Diode
1
10h Page 46
26h R/W External Diode 2
Beta Configuration
Stores the Beta Compensation
circuitry settings for External Diode
2
10h Page 46
27h R/W External Diode 1
Ideality Factor
Stores the ideality factor for
External Diode 1
12h
(1.008)
Page 47
28h R/W External Diode 2
Ideality Factor
Stores the ideality factor for
External Diode 2
12h
(1.008)
Page 47
29h R Internal Diode Data
Low Byte
Stores the fractional data for the
Internal Diode (mirrored at register
39h)
00h Page 38
2Ah R External Diode 3
High Byte
Stores the integer data for External
Diode 3 (mirrored at register 3Eh)
00h Page 38
2Bh R External Diode 3 Low
Byte
Stores the fractional data for
External Diode 3 (mirrored at
register 3Fh)
00h Page 38
2Ch R/W External Diode 3
High Limit High Byte
Stores the integer portion of the
high limit for External Diode 3
55h
(85°C)
Page 41
2Dh R/W External Diode 3 Low
Limit High Byte
Stores the integer portion of the
low limit for External Diode 3
80h
(-128°C)
Page 41
2Eh R/W External Diode 3
High Limit Low Byte
Stores the fractional portion of the
high limit for External Diode 3
00h Page 41
2Fh R/W External Diode 3 Low
Limit Low Byte
Stores the fractional portion of the
low limit for External Diode 3
00h Page 41
30h R/W External Diode 3 Tcrit
Limit
Stores the 8-bit critical temperature
limit for External Diode 3
64h
(100°C)
Page 43
31h R/W External Diode 3
Ideality Factor
Stores the ideality factor for
External Diode 3
12h
(1.008)
Page 47
34h R-C Status Stores the status bits for the
measured temperature channels,
Current Sense circuitry, and Peak
Detector circuitry.
00h Page 39
35h R-C High Limit Status Status bits for the High Limits 00h Page 48
36h R-C Low Limit Status Status bits for the Low Limits 00h Page 49
37h R-C Crit Limit Status Status bits for the Tcrit and Vcrit
Limits
00h Page 49
38h R Internal Diode High
Byte
Stores the integer data for the
Internal Diode
00h Page 38
39h R Internal Diode Low
Byte
Stores the fractional data for the
Internal Diode
00h Page 38
Table 5.1 Register Set in Hexadecimal Order (continued)
REGISTER
ADDRESS R/W REGISTER NAME FUNCTION
DEFAULT
VALUE PAGE
Q MICFIDCHIP
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
EMC1704 36 DS20005239A
DATASHEET
3Ah R External Diode 1
High Byte
Stores the integer data for External
Diode 1
00h Page 38
3Bh R External Diode 1 Low
Byte
Stores the fractional data for
External Diode 1
00h Page 38
3Ch R External Diode 2
High Byte
Stores the integer data for External
Diode 2
00h Page 38
3Dh R External Diode 2 Low
Byte
Stores the fractional data for
External Diode 2
00h Page 38
3Eh R External Diode 3
High Byte
Stores the integer data for External
Diode 3
00h Page 38
3Fh R External Diode 3 Low
Byte
Stores the fractional data for
External Diode 3
00h Page 38
40h R/W Averaging Control Controls the digital averaging
setting for the all external diode
channels
00h Page 50
Current Sense Control and Measurement
50h R/W Voltage Sampling
Configuration
Controls voltage sampling 80h Page 51
51h R/W Current Sense
Sampling
Configuration
Controls the current sensing
sampling and update times
03h Page 52
52h R/W Peak Detection
Config
Controls the peak detection
configuration
00h Page 53
54h R Sense Voltage High
Byte
Stores the voltage measured
across RSENSE
00h Page 55
55h R Sense Voltage Low
Byte
00h Page 55
58h R Source Voltage High
Byte
Stores voltage measured on the
source side of RSENSE
00h Page 56
59h R Source Voltage Low
Byte
00h Page 56
5Bh R Power Ratio High
Byte
Stores the power ratio value 00h Page 56
5Ch R Power Ratio Low
Byte
00h Page 56
Current Sense and Source Voltage Limits
60h R/W Sense Voltage High
Limit
Stores the high limit for VSENSE 7Fh Page 57
61h R/W Sense Voltage Low
Limit
Stores the low or negative limit for
the VSENSE voltage
80h Page 57
64h R/W Source Voltage High
Limit
Stores the high limit for the voltage
on the source side of RSENSE
FFh Page 57
Table 5.1 Register Set in Hexadecimal Order (continued)
REGISTER
ADDRESS R/W REGISTER NAME FUNCTION
DEFAULT
VALUE PAGE
Q MICFIDCHIP
High-Side Current-Sense and Multiple 1°C Temperature Monitor
DS20005239A 37 EMC1704
DATASHEET
5.1 Data Read Interlock
When any measurement channel high byte register is read (temperature or VSOURCE or VSENSE), the
corresponding low byte is copied into an internal ‘shadow’ register. The user is free to read the low
byte at any time and be guaranteed that it will correspond to the previously read high byte. Regardless
if the low byte is read or not, reading from the same high byte register again will automatically refresh
this stored low byte data.
5.2 Block Mode Support
All of the status and temperature data may be retrieved with a block read of 12 bytes starting at register
address 34h.
All of the voltage measurement, current sense data, and power information may be retrieved with a
block read of 6 bytes starting at register address 54h.
65h R/W Source Voltage Low
Limit
Stores the low limit for the voltage
on the source side of RSENSE
00h Page 57
66h R/W Sense Voltage Vcrit
Limit
Stores the critical limit for VSENSE 7Fh Page 58
68h R/W Source Voltage Vcrit
Limit
Stores the critical limit for the
voltage on the source side of
RSENSE
FFh Page 58
69h R/W Sense Vcrit
Hysteresis
Stores the hysteresis for the
VSENSE Vcrit limit
0Ah Page 58
6Ah R/W Source Voltage Vcrit
Hysteresis
Stores the hysteresis for the
source voltage Vcrit limits
0Ah Page 58
GPIO Controls
70h R/W GPIO Config
Register
Controls the GPIO pin 08h Page 58
FCh R Product Features Stores information about which pin
controlled product features are set
00h Page 59
FDh R Product ID Stores a fixed value that identifies
each product
3Bh Page 59
FEh R SMSC ID Stores a fixed value that
represents SMSC
5Dh Page 59
FFh R Revision Stores a fixed value that
represents the revision number
82h Page 60
Table 5.1 Register Set in Hexadecimal Order (continued)
REGISTER
ADDRESS R/W REGISTER NAME FUNCTION
DEFAULT
VALUE PAGE
Q MICFIDCHIP
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
EMC1704 38 DS20005239A
DATASHEET
5.3 Temperature Data Registers
As shown in Ta b l e 5 .2 , temperature data is stored as an 11-bit value with the high byte representing
the integer value and the low byte representing the fractional value left justified to occupy the MSBits.
Table 5.2 Temperature Data Registers
ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT
00h R Internal Diode
High Byte
Sign 64 32 16 8 4 2 1 00h
38h
29h R Internal Diode
Low Byte
0.5 0.25 0.125 - - - - - 00h
39h
01h R External
Diode1 High
Byte
Sign 64 32 16 8 4 2 1 00h
3Ah
10h R External
Diode1 Low
Byte
0.5 0.25 0.125 - - - - - 00h
3Bh
23h R External Diode
2 High Byte
Sign 64 32 16 8 4 2 1 00h
3Ch
24h R External Diode
2 Low Byte
0.5 0.25 0.125 - - - - - 00h
3Dh
2Ah R External Diode
3 High Byte
Sign 64 32 16 8 4 2 1 00h
3Eh
2Bh R External Diode
3 Low Byte
0.5 0.25 0.125 - - - - - 00h
3Fh
Table 5.3 Temperature Data Format
TEMPERATURE (°C) BINARY HEX (AS READ BY REGISTERS)
Diode Fault 1000_0000_000b 80_00h
-63.875 1100_0000_001b C0_20h
-63 1100_0001_000b C1_00h
-1 1111_1111_000b FF_00h
-0.125 1111_1111_111b FF_E0h
0 0000_0000_000b 00_00h
0.125 0000_0000_001b 00_20h
1 0000_0001_000b 01_00h
63 0011_1111_000b 3F_00h
Q MICFIDCHIP ALERT THERM THERM ALERT ALERT ALERT ALERT ALERT THERM
High-Side Current-Sense and Multiple 1°C Temperature Monitor
DS20005239A 39 EMC1704
DATASHEET
5.4 Status Register
The Status Register reports general error conditions. To identify specific channels, refer to
Section 5.10, Section 5.15, Section 5.16, and Section 5.17. The individual Status Register bits are
cleared when the appropriate High Limit, Low Limit, or Crit Limit status register has been read or
cleared.
Bit 7 - BUSY - This bit indicates that one of the ADCs is currently converting. This bit does not cause
either the ALERT or THERM pins to be asserted.
Bit 6 - PEAK - This bit is set when the Peak Detector circuitry has detected a current peak that is
greater than the programmed threshold for longer than the programmed duration. This bit is not sticky
and will be cleared when the condition has been removed. When set, the THERM pin or ALERT pin
(Comparator mode only) may be asserted (see Section 5.19).
Bit 5 - GPIO - This bit is set when the GPIO pin changes state when configured as a GPIO input.
When set, the ALERT pin is asserted. This bit will be sticky and is cleared when read.
Bit 4 - HIGH - This bit is set when any of the temperature channels meets or exceeds its programmed
high limit. This bit will also be set if the VSENSE or VSOURCE channels meet or exceed their respective
high limits. See the High Limit Status Register for specific channel information (Section 5.15). When
set, the ALERT pin is asserted.
Bit 3 - LOW - This bit is set when any of the temperature channels drops below its programmed low
limit. This bit will also be set if the VSENSE or VSOURCE channels drop below their respective low limits.
See the Low Limit Status Register for specific channel information (Section 5.16). When set, the
ALERT pin is asserted.
Bit 2 - FAULT - This bit is set when a diode fault is detected on any of the external diode channels.
See the External Diode Fault Register for specific channel information (Section 5.10). When set, the
ALERT pin is asserted.
Bit 1 - CRIT - This bit is set when any of the temperature channels meets or exceeds its programmed
Tcrit limit. This bit will also be set if the VSENSE or VSOURCE channels meet or exceed their respective
Vcrit limits (see the Section 5.17, "Crit Limit Status Register" for specific channel information). When
set, the THERM pin is asserted. This bit is not sticky and will be cleared when the error condition has
been removed.
64 0100_0000_000b 40_00h
65 0100_0001_000b 41_00h
127 0111_1111_000b 7F_00h
127.875 0111_1111_111b 7F_E0h
Table 5.4 Status Register
ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT
02h R Status BUSY PEAK GPIO HIGH LOW FAULT CRIT - 00h
34h
Table 5.3 Temperature Data Format (continued)
TEMPERATURE (°C) BINARY HEX (AS READ BY REGISTERS)
Q MICFIDCHIP ALERT ALERT ALERT ALERT ALERT ALERT ALERT
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
EMC1704 40 DS20005239A
DATASHEET
5.5 Configuration Register
The Configuration Register controls the basic operation of the device. This register is fully accessible
at either address.
Bit 7 - MASK_ALL - Masks the ALERT pin from asserting.
‘0’ (default) - The ALERT pin is not masked. If any of the appropriate status bits are set, the ALERT
pin will be asserted.
‘1’ - The ALERT pin is masked if configured in Interrupt mode (see Section 4.4.1, "ALERT Pin
Interrupt Mode"). The Status Registers will be updated normally.
Bit 6 - TMEAS / STOP - Controls Temperature measurement modes.
‘0’ (default) - The device is active, measuring all of the temperature channels.
‘1’ - The device is not measuring temperature channels. It will update all of the temperature
channels when a One-Shot command is given.
Bit 5 - ALERT/COMP - Controls the operation of the ALERT pin.
‘0’ (default) - The ALERT pin acts in Interrupt mode as described in Section 4.4.1.
‘1’ - The ALERT pin acts in Comparator mode as described in Section 4.4.2. In this mode the
MASK_ALL bit is ignored.
Bit 4 - DIS_REC1- Disables the Resistance Error Correction (REC) for External Diode 1.
‘0’ (default) - REC is enabled for External Diode 1.
‘1’ - REC is disabled for External Diode 1.
Bit 3 - DIS_REC2 - Disables the Resistance Error Correction (REC) for External Diode 2 and External
Diode 3.
‘0’ (default) - REC is enabled for External Diode 2 and External Diode 3.
‘1’ - REC is disabled for External Diode 2 and External Diode 3.
Bit 2 - IMEAS / STOP - Controls VSENSE and VSOURCE measurement modes.
‘0’ (default) - The device is measuring source voltage and sense voltage.
‘1’ -The device is not measuring the source voltage and sense voltage. It will update VSENSE and
VSOURCE registers when a One-Shot command is given.
Bit 1 - DAVG_DIS - Disables the dynamic averaging feature on all temperature channels.
‘0’ (default) - The dynamic averaging feature is enabled. All temperature channels will be converted
with an averaging factor that is based on the conversion rate as shown in Ta b l e 4 . 3 .
‘1’ - The dynamic averaging feature is disabled. All temperature channels will be converted with a
maximum averaging factor of 1x (equivalent to 11-bit conversion).
Bit 0 - DIS_APD - Disables the APD functionality on the DP2 / DN3 and DN3 / DP2 pins.
‘0’ (default) - APD functionality is enabled on the DP2 / DN3 and DN3 / DP2 pins.
‘1’ - APD functionality is disabled on the DP2 / DN3 and DN3 / DP3 pins. The External Diode 3
channel will not be measured.
Table 5.5 Configuration Register
ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT
03h R/W Configuration MASK_
ALL
TMEAS
/STOP
ALERT/
COMP
DIS_
REC1
DIS_
REC2
IMEAS
/STOP
DAVG_
DIS
DIS_
APD
00h
09h
Q MICFIDCHIP
High-Side Current-Sense and Multiple 1°C Temperature Monitor
DS20005239A 41 EMC1704
DATASHEET
5.6 Conversion Rate Register
The Conversion Rate Register controls how often the VSOURCE and temperature measurement
channels are updated and compared against the limits. This register is fully accessible at either
address.
Bits 2-0 - T_CONV[2:0] - Determines the conversion rate as shown in Ta bl e 5 . 7 . This conversion rate
applies to temperature measurement and source voltage measurement.
5.7 Temperature Limit Registers
Table 5.6 Conversion Rate Register
ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT
04h R/W Conversion
Rate
- - - - T_CONV[2:0] 06h
(4/sec)
0Ah
Table 5.7 Conversion Rate
T_CONV[2:0]
CONVERSION RATE210
000 1 per 16 sec
0 0 1 1 per 8 sec
0 1 0 1 per 4 sec
0 1 1 1 per 2 sec
1 0 0 1 per sec
101 2 per sec
1 1 0 4 per sec (default)
1 1 1 8 per sec
Table 5.8 Temperature Limit Registers
ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT
05h R/W Internal Diode
High Limit
Sign 64 32 16 8 4 2 1 55h
(85°C)
0Bh
06h R/W Internal Diode
Low Limit
Sign 64 32 16 8 4 2 1 80h
(-128°C)
0Ch
07h R/W External
Diode 1 High
Limit High
Byte
Sign 64 32 16 8 4 2 1 55h
(85°C)
0Dh
Q MICFIDCHIP ALERT ALERT
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
EMC1704 42 DS20005239A
DATASHEET
The device contains both high and low limits for the temperature channels. If the measured
temperature meets or exceeds the high limit, the corresponding status bit is set, and the ALERT pin
is asserted. Likewise, if the measured temperature is less than or equal to the low limit, the
corresponding status bit is set and the ALERT pin is asserted.
The limit registers with multiple addresses are fully accessible at either address.
13h R/W External
Diode 1 High
Limit Low
Byte
0.5 0.25 0.125 - - - - - 00h
08h R/W External
Diode 1 Low
Limit High
Byte
Sign 64 32 16 8 4 2 1 80h
(-128°C)
0Eh
14h R/W External
Diode 1 Low
Limit Low
Byte
0.5 0.25 0.125 - - - - - 00h
15h R/W External
Diode 2 High
Limit High
Byte
Sign 64 32 16 8 4 2 1 55h
(85°C)
16h R/W External
Diode 2 Low
Limit High
Byte
Sign 64 32 16 8 4 2 1 80h
(-128°C)
17h R/W External
Diode 2 High
Limit Low
Byte
0.5 0.25 0.125 - - - - - 00h
18h R/W External
Diode 2 Low
Limit Low
Byte
0.5 0.25 0.125 - - - - - 00h
2Ch R/W External
Diode 3 High
Limit High
Byte
Sign 64 32 16 8 4 2 1 55h
(85°C)
2Dh R/W External
Diode 3 Low
Limit High
Byte
Sign 64 32 16 8 4 2 1 80h
(-128°C)
2Eh R/W External
Diode 3 High
Limit Low
Byte
0.5 0.25 0.125 - - - - - 00h
2Fh R/W External
Diode 3 Low
Limit Low
Byte
0.5 0.25 0.125 - - - - - 00h
Table 5.8 Temperature Limit Registers (continued)
ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT
Q MICFIDCHIP THERM ALERT THERM THERM
High-Side Current-Sense and Multiple 1°C Temperature Monitor
DS20005239A 43 EMC1704
DATASHEET
When the device is Standby or Current Sense only mode, updating the limit registers will have no effect
until the next conversion cycle occurs. This conversion cycle can be initiated via a write to the One-
Shot Register or by clearing the TMEAS_STOP bit in the Configuration Register (see Section 5.5).
5.8 One-Shot Register
Writing to the One-Shot register will automatically update those channels that are not currently
measured. If the device is Fully Active, writing to this register will have no effect. If the IMEAS_STOP
bit is set, writing to this register will update the VSENSE and VSOURCE voltage measurements. If the
TMEAS_STOP bit is set, writing to this register will update all of the temperature channel
measurements.
5.9 Tcrit Limit Registers
The Tcrit Limit Registers are used to determine whether a critical thermal event has occurred. If the
measured temperature meets or exceeds the Tcrit Limit, the THERM pin is asserted.
Unlike the ALERT pin, the THERM pin cannot be masked. Additionally, the THERM pin will be released
once the temperature drops below the corresponding threshold minus the Tcrit Hysteresis.
Table 5.9 One-Shot Register
ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT
0Fh W One-Shot Writing to this register initiates a single conversion cycle. Data
is not stored and always reads 00h
00h
Table 5.10 Tcrit Limit Registers
ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT
19h R/W External
Diode 1 Tcrit
Limit
Sign 64 32 16 8 4 2 1 64h
(100°C)
1Ah R/W External
Diode 2 Tcrit
Limit
Sign 64 32 16 8 4 2 1 64h
(100°C)
20h R/W Internal Diode
Tc r it L i mi t
Sign 64 32 16 8 4 2 1 64h
(100°C)
21h R/W Tcrit
Hysteresis
-643216 8 421 0Ah
(10°C)
30h R/W External
Diode 3 Tcrit
Limit
Sign 64 32 16 8 4 2 1 64h
(100°C)
Q MICFIDCHIP ALERT THERM ALERT THERM ALERT ALERT ALERT THERM ALERT ALERT ALERT THERM ALERT ALERT ALERT ALERT ALERT
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
EMC1704 44 DS20005239A
DATASHEET
5.10 External Diode Fault Register
The External Diode Fault Register indicates which of the external diodes caused the FAULT bit in the
Status Register to be set. This register is cleared when it is read.
Bit 3 - E3FLT - This bit is set if the External Diode 3 channel reported a diode fault.
Bit 2 - E2FLT - This bit is set if the External Diode 2 channel reported a diode fault.
Bit 1 - E1FLT - This bit is set if the External Diode 1 channel reported a diode fault.
5.11 Channel Mask Register
The Channel Mask Register controls individual channel masking. When a channel is masked, the
ALERT pin will not be asserted when the masked channel reads a diode fault or out-of-limit error. The
channel mask does not mask the THERM pin.
Bit 7 - VSENSE_MASK - Masks the ALERT pin from asserting when the VSENSE value meets or
exceeds the high limit or drops below the low limit. This bit will have no effect on the THERM pin
functionality.
‘0’ (default) - The VSENSE voltage channel will cause the ALERT pin to be asserted (if enabled).
‘1’ - The VSENSE voltage channel will not cause the ALERT pin to be asserted (if enabled).
Bit 6 - VSRC_MASK - Masks the ALERT pin from asserting when the VSOURCE value meets or
exceeds the high limit or drops below the low limit. This bit will have no effect on the THERM pin
functionality.
‘0’ (default) - The VSOURCE voltage channel will cause the ALERT pin to be asserted (if enabled).
‘1’ - The VSOURCE voltage channel will not cause the ALERT pin to be asserted (if enabled).
BIt 5 - PEAK_MASK - Masks the ALERT pin from asserting when the Peak Detector circuitry detects
a current spike. This bit will have no effect on the THERM pin functionality.
‘0’ (default) - The Peak Detector circuitry will cause the ALERT pin to be asserted (if enabled).
‘1’ - The Peak Detector circuitry will not cause the ALERT pin to be asserted (if enabled).
Bit 3 - E3MASK - Masks the ALERT pin from asserting when the External Diode 3 channel is out-of-
limit or reports a diode fault.
‘0’ (default) - The External Diode 3 channel will cause the ALERT pin to be asserted if it is out-of-
limit or reports a diode fault.
‘1’ - The External Diode 3 channel will not cause the ALERT pin to be asserted if it is out-of-limit
or reports a diode fault.
Table 5.11 External Diode Fault Register
ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT
1Bh R-C External
Diode Fault
- - - - E3FLT E2FLT E1FLT - 00h
Table 5.12 Channel Mask Register
ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT
1Fh R/W Channel
Mask
VSENSE_
MASK
VSRC_
MASK
PEAK_
MASK
-E3
MASK
E2
MASK
E1
MASK
INT
MASK
00h
Q MICFIDCHIFI ALERT ALERT ALERT ALERT ALERT ALERT ALERT ALERT ALERT ALERT W ALERT
High-Side Current-Sense and Multiple 1°C Temperature Monitor
DS20005239A 45 EMC1704
DATASHEET
Bit 2 - E2MASK - Masks the ALERT pin from asserting when the External Diode 2 channel is out-of-
limit or reports a diode fault.
‘0’ (default) - The External Diode 2 channel will cause the ALERT pin to be asserted if it is out-of-
limit or reports a diode fault.
‘1’ - The External Diode 2 channel will not cause the ALERT pin to be asserted if it is out-of-limit
or reports a diode fault.
Bit 1 - E1MASK - Masks the ALERT pin from asserting when the External Diode 1 channel is out-of-
limit or reports a diode fault.
‘0’ (default) - The External Diode 1 channel will cause the ALERT pin to be asserted if it is out-of-
limit or reports a diode fault.
‘1’ - The External Diode 1 channel will not cause the ALERT pin to be asserted if it is out-of-limit
or reports a diode fault.
Bit 0 - INTMASK - Masks the ALERT pin from asserting when the Internal Diode temperature is out-
of-limit.
‘0’ (default) - The Internal Diode channel will cause the ALERT pin to be asserted if it is out-of-limit.
‘1’ - The Internal Diode channel will not cause the ALERT pin to be asserted if it is out-of-limit.
5.12 Consecutive Alert Register
The Consecutive Alert Register determines how many times an out-of-limit error or diode fault must
be detected in consecutive measurements before the interrupt status registers are asserted. This
applies to temperature limits only. The voltage measurement and current sense measurements are
controlled via the Voltage Channel Configuration register and Current Sense Configuration register
respectively (see Section 5.19 and Section 5.20).
When the ALERT pin is configured as a comparator, the consecutive alert counter will ignore diode
fault and low limit errors and only increment if the measured temperature meets or exceeds the High
Limit.
Each measurement channel has a separate fault queue associated with the high limit, low limit, and
diode fault condition except the internal diode.
Bit 7 - TIMEOUT - Determines whether the SMBus Timeout function is enabled.
‘0’ (default) - The SMBus Timeout feature is disabled. The SMCLK line can be held low indefinitely
without the device resetting its SMBus protocol.
‘1’ - The SMBus Timeout feature is enabled. If the SMCLK line is held low for more than 30ms,
the device will reset the SMBus protocol.
Bits 6-4 - CTHRM[2:0] - Determines the number of consecutive measurements that must exceed the
corresponding Tcrit Limit before the THERM pin is asserted.
Bits 3-1 - CALRT[2:0] - Determines the number of consecutive measurements that must have an out-
of-limit condition or diode fault before the ALERT pin is asserted. All temperature channels use this
value to set the respective counters. The bits are decoded as shown in Table 5.14. The default setting
is 1 consecutive out-of-limit conversion.
Table 5.13 Consecutive Alert Register
ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT
22h R/W Consecutive
Alert
TIME
OUT
CTHRM[2:0] CALRT[2:0] - 70h
Q MICFIDCHIP
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
EMC1704 46 DS20005239A
DATASHEET
5.13 Beta Configuration Registers
This register is used to set the Beta Compensation factor that is used for the external diode channels.
Bit 4 - AUTOX - Enables the Beta Compensation factor autodetection function. This function shall be
disabled for External Diode 3 at all times and for External Diode 2 when APD is enabled.
‘0’ - The Beta Compensation Factor autodetection circuitry is disabled. The External Diode will
always use the Beta Compensation factor set by the BETAx[3:0] bits.
‘1’ (default) - The Beta Compensation factor autodetection circuitry is enabled. At the beginning of
every conversion, the optimal Beta Compensation factor setting will be determined and applied.
The BETAx[3:0] bits will be automatically updated to indicate the current setting.
Bit 3-0 - BETAx[3:0] - These bits always reflect the current beta configuration settings. If autodetection
circuitry is enabled, these bits will be updated automatically and writing to these bits will have no effect.
If the autodetection circuitry is disabled, these bits will determine the beta configuration setting that is
used for their respective channels.
Care should be taken when setting the BETAx[3:0] bits when the autodetection circuitry is disabled. If
the Beta Compensation factor is set at a beta value that is higher than the transistor beta, the circuit
may introduce measurement errors. When measuring a discrete thermal diode (such as 2N3904) or a
CPU diode that functions like a discrete thermal diode (such as an AMD processor diode), the
BETAx[3:0] bits should be set to ‘1111b’.
Table 5.14 Consecutive ALERT / THERM Settings
210
NUMBER OF CONSECUTIVE OUT-OF-LIMIT
MEASUREMENTS
000 1
(default for CALRT[2:0])
001 2
011 3
111 4
(default for CTHRM[2:0])
Table 5.15 Beta Configuration Registers
ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT
25h R/W External
Diode 1 Beta
Configuration
- - - AUTO1 BETA1[3:0] 10h
26h R/W External
Diode 2 Beta
Configuration
- - - AUTO2 BETA2[3:0] 10h
Q MICFIDCHIP
High-Side Current-Sense and Multiple 1°C Temperature Monitor
DS20005239A 47 EMC1704
DATASHEET
5.14 External Diode Ideality Factor Registers
Table 5.16 Beta Compensation
AUTO
BETAX[3:0]
MINIMUM BETA
3210
00000 0.050
00001 0.066
00010 0.087
00011 0.114
00100 0.150
00101 0.197
00110 0.260
00111 0.342
01000 0.449
01001 0.591
01010 0.778
01011 1.024
01100 1.348
01101 1.773
01110 2.333
01111 Disabled
1XXXX Automatically detected
Table 5.17 Ideality Configuration Registers
ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT
27h R/W External
Diode 1
Ideality
Factor
- - 0 1 0 IDCF1[2:0] 12h
28h R/W External
Diode 2
Ideality
Factor
- - 0 1 0 IDCF2[2:0] 12h
31h R/W External
Diode 3
Ideality
Factor
- - 0 1 0 IDCF3[2:0] 12h
Q MICFIDCHIP ALERT ALERT
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
EMC1704 48 DS20005239A
DATASHEET
These registers store the ideality factors that are applied to the external diodes. Table 5.18 defines
each setting and the corresponding ideality factor. Beta Compensation and Resistance Error Correction
automatically correct for most diode ideality errors; therefore, it is not recommended that these settings
be updated without consulting Microchip.
APPLICATION NOTE: When measuring a 65nm Intel CPUs, the Ideality Setting should be the default 12h. When
measuring 45nm Intel CPUs, the Ideality Setting should be 15h.
5.15 High Limit Status Register
The High Limit Status Register contains the status bits that are set when a temperature or voltage
channel high limit is met or exceeded. If any of these bits are set, the HIGH status bit in the Status
Register is set. Reading from the High Limit Status Register will clear all bits if the error condition has
been removed. Reading from the register will also clear the HIGH status bit in the Status Register if
the error condition has been removed.
If not masked, the ALERT pin will be set if the programmed number of consecutive alert counts have
been met and any of these status bits are set. Once set, the status bits will remain set until read unless
the ALERT pin is configured as a comparator output (see Section 4.4.2).
Bit 7 - VSENSE_HIGH - This bit is set when the VSENSE value meets or exceeds its programmed high
limit.
Bit 6 - VSRC_HIGH - This bit is set when the VSOURCE value meets or exceeds its programmed high
limit.
Bit 3 - E3HIGH - This bit is set when the External Diode 3 channel meets or exceeds its programmed
high limit.
Bit 2 - E2HIGH - This bit is set when the External Diode 2 channel meets or exceeds its programmed
high limit.
Table 5.18 Ideality Factor Look-Up Table (Diode Model)
SETTING FACTOR
10h 1.0053
11h 1.0066
12h 1.0080
13h 1.0093
14h 1.0106
15h 1.0119
16h 1.0133
17h 1.0146
Table 5.19 High Limit Status Register
ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT
35h R-C High Limit
Status
VSENSE_
HIGH
VSRC_
HIGH
--E3
HIGH
E2
HIGH
E1
HIGH
I
HIGH
00h
Q MICFIDCHIP ALERT
High-Side Current-Sense and Multiple 1°C Temperature Monitor
DS20005239A 49 EMC1704
DATASHEET
Bit 1 - E1HIGH - This bit is set when the External Diode 1 channel meets or exceeds its programmed
high limit.
Bit 0 - IHIGH - This bit is set when the Internal Diode channel meets or exceeds its programmed high
limit.
5.16 Low Limit Status Register
The Low Limit Status Register contains the status bits that are set when a temperature or voltage
channel drops below the low limit. If any of these bits are set, the LOW status bit in the Status Register
is set. Reading from the Low Limit Status Register will clear all bits. Reading from the register will also
clear the LOW status bit in the Status Register if the error status has been removed.
If not masked, the ALERT pin will be set if the programmed number of consecutive alert counts have
been met and any of these status bits are set.
Once set, the status bits will remain set until read.
Bit 7 - VSENSE_LOW - This bit is set when the VSENSE value drops below its programmed low limit.
Bit 6 - VSRC_LOW - This bit is set when the VSOURCE value drops below its programmed low limit.
Bit 3 - E3LOW - This bit is set when the External Diode 3 channel drops below its programmed low
limit.
Bit 2 - E2LOW - This bit is set when the External Diode 2 channel drops below its programmed low
limit.
Bit 1 - E1LOW - This bit is set when the External Diode 1 channel drops below its programmed low
limit.
Bit 0 - ILOW - This bit is set when the Internal Diode channel drops below its programmed low limit.
5.17 Crit Limit Status Register
The Crit Limit Status register contains the status bits that are set when a temperature or voltage
channel Tcrit or Vcrit Limit is met or exceeded (see Section 5.9 and Section 5.27). If any of these bits
are set, the CRIT status bit in the Status register is set. Reading from the Crit Limit Status register will
not clear the status bits. Once the temperature drops below the Tcrit Limit minus the Tcrit Hysteresis,
the corresponding status bits will be automatically cleared. Once the voltage drops below the Vcrit Limit
minus the Vcrit Hysteresis, the corresponding status bits will be automatically cleared. The CRIT bit in
the Status register will be cleared when all individual bits are cleared.
Table 5.20 Low Limit Status Register
ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT
36h R-C Low Limit
Status
VSENSE_
LOW
VSRC_
LOW
--E3
LOW
E2
LOW
E1
LOW
ILOW 00h
Table 5.21 Crit Limit Status Register
ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT
37h R-C Crit Limit
Status
VSENSE_
VCRIT
VSRC_
VCRIT
--E3
TCRIT
E2
TCRIT
E1
TCRIT
ITCRIT 00h
THERM THERM THERM THERM THERM THERM Q MICFIDCHIP
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
EMC1704 50 DS20005239A
DATASHEET
Bit 7 - VSENSE_VCRIT - This bit is set when the VSENSE value meets or exceeds its programmed
Vcrit limit. When set, this bit will assert the THERM pin.
Bit 6 - VSRC_VCRIT- This bit is set when the VSOURCE value meets or exceeds its programmed Vcrit
limit. When set, this bit will assert the THERM pin.
Bit 3 - E3TCRIT - This bit is set when the External Diode 3 channel meets or exceeds its programmed
Tcrit Limit. When set, this bit will assert the THERM pin.
Bit 2 - E2TCRIT - This bit is set when the External Diode 2 channel meets or exceeds its programmed
Tcrit Limit. When set, this bit will assert the THERM pin.
Bit 1 - E1TCRIT - This bit is set when the External Diode 1 channel meets or exceeds its programmed
Tcrit limit. When set, this bit will assert the THERM pin.
Bit 0 - ITCRIT - This bit is set when the Internal Diode channel meets or exceeds its programmed Tcrit
limit. When set, this bit will assert the THERM pin.
5.18 Averaging Control Register
The Averaging Control Register controls the digital averaging on the external diode channels.
Bits 5-4 - AVG3[1:0] - Controls the digital averaging that is applied to the External Diode 3 temperature
measurements as shown in Table 5 .2 3 .
Bits 3-2 - AVG2[1:0] - Controls the digital averaging that is applied to the External Diode 2 temperature
measurements as shown in Table 5 .2 3 .
Bits 1-0 - AVG1[1:0] - Controls the digital averaging that is applied to the External Diode 1 temperature
measurements as shown in Table 5 .2 3 .
Table 5.22 Filter Configuration Register
ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT
40h R/W Filter Control - - AVG3[1:0] AVG2[1:0] AVG1[1:0] 00h
Table 5.23 Averaging Settings
AVGX[1:0]
AVERAGING10
0 0 Disabled (default)
012x
104x
118x
G MICFIDCHIP ALERT iTHERM ALERT THERM m ALERT W
High-Side Current-Sense and Multiple 1°C Temperature Monitor
DS20005239A 51 EMC1704
DATASHEET
5.19 Voltage Sampling Configuration Register
The Voltage Sampling Configuration register controls functionality for the source voltage measurement
and Peak Detector circuitry.
Bit 7 - PK_ALERT_THERM - Determines whether the ALERT pin or THERM pin is asserted if the Peak
Detector detects a current spike. If configured to assert the ALERT pin, the PEAK_MASK can block
the pin assertion normally. If configured to assert the THERM pin, it will not be masked.
‘0’ - The Peak Detector circuitry will assert the ALERT pin when a current spike is detected. The
ALERT pin must be configured to operate in Comparator mode or it will not be asserted.
‘1’ (default) - The Peak Detector circuitry will assert the THERM pin when a current spike is
detected.
Bits 3 - 2 - V_QUEUE[1:0] - Determine the number of consecutive measurements that VSOURCE must
exceed the limits before flagging an interrupt.
Bits 1-0 - V_AVG[1:0] - Controls the digital averaging that is applied to the source voltage
measurement, as shown in Ta b l e 5 . 2 6 .
Table 5.24 Voltage Sampling Configuration Register
ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT
50h R/W Voltage
Sampling
Config
PK_
ALERT_
THERM
- - - V_QUEUE[1:0] V_AVG[1:0] 80h
Table 5.25 Voltage Queue Settings
V_QUEUE[1:0]
NUMBER OF CONSECUTIVE OUT-OF-LIMIT MEASUREMENTS10
0 0 1 (default)
01 2
10 3
11 4
Table 5.26 Voltage Averaging Settings
V_AVG[1:0]
AVERAGING10
0 0 Disabled (default)
012x
104x
118x
Q MICFIDCHIP
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
EMC1704 52 DS20005239A
DATASHEET
5.20 Current Sense Sampling Configuration Register
The Current Sense Sampling Configuration register stores the controls for determining the Current
Sense sampling / update time.
Bits 7 - 6 - CS_QUEUE[1:0] - Determine the number of consecutive measurements that the measured
VSENSE must exceed the limits before flagging an interrupt.
Bits 5 - 4 - CS_SAMP_AVG[1:0] - Determines the number of averages that the Current Sensing
Circuitry will take as shown in Tab l e 5 . 2 9 .
Bits 3 - 2 - CS_SAMP_TIME[1:0] - Determines the sampling time of the Current Sensing Circuitry as
shown in Tab l e 5.30. The VSENSE voltage will be updated at this rate representing the average current
over the Sampling Time multiplied by the Averaging factor as shown in Ta bl e 5 . 3 1 .
Table 5.27 Current Sense Sampling Configuration Register
ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT
51h R/W Current Sense
Sampling Config
CS_QUEUE
[1:0]
CS_SAMP_
AVG [1:0]
CS_SAMP_
TIME[1:0]
CS_RNG
[1:0]
03h
Table 5.28 Sense Queue Settings
CS_QUEUE[1:0]
NUMBER OF CONSECUTIVE OUT-OF-LIMIT MEASUREMENTS10
0 0 1 (default)
01 2
10 3
11 4
Table 5.29 Current Sense Averaging Settings
CS_SAMP_AVG[1:0]
AVERAGING10
0 0 1x (default)
012x
104x
118x
Q MICFIDCHIP
High-Side Current-Sense and Multiple 1°C Temperature Monitor
DS20005239A 53 EMC1704
DATASHEET
Bits 1 - 0 - CS_RNG[1:0] - Determines the Current Sense maximum expected voltage (full scale range)
as shown in Table 5.32.
5.21 Peak Detection Configuration Register
Table 5.30 Current Sensing Sampling Time Settings
CS_SAMP_TIME[1:0]
CURRENT SENSOR SAMPLING TIME 10
0 0 82ms (default)
0 1 82ms
1 0 164ms
1 1 328ms
Table 5.31 Total Sampling Times
SAMPLING TIME
AVERAGING SELECTION
1X 2X 4X 8X
82ms 82ms 164ms 328ms 655ms
164ms 164ms 328ms 655ms 1310ms
328ms 328ms 655ms 1310ms 2620ms
Table 5.32 Current Sensing Range (Full Scale Range) Settings
CS_RNG[1:0]
CURRENT SENSOR RANGE10
00 10mV
01 20mV
10 40mV
1 1 80mV (default)
Table 5.33 Peak Detection Configuration Register
ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT
52h R/W Peak
Detection
Config
PEAK_DET_TH[3:0] PEAK_DET_DUR[3:0] 00h
Q MICFIDCHIP
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
EMC1704 54 DS20005239A
DATASHEET
The Peak Detection Configuration register controls the threshold and durations used by the Peak
Detection circuitry. At all times, the Peak Detection threshold and duration are set by the values written
into this register. The resistors on the TH_SEL and DUR_SEL pins are used to determine the initial
values of this register (EMC1704-2 only) and will not be retained if the value is over written by the user.
These values may be updated at any time via the SMBus.
Bits 7-4 - PEAK_DET_TH[3:0] - Determines the Peak Detector Threshold level as shown in Ta b l e 5 . 34 .
Bits 4-0 - PEAK_DET_DUR[3:0] - Determines the Peak Detector minimum time threshold as shown in
Table 5.35.
Table 5.34 PEAK_DET_TH[3:0] Bit Decode
PEAK_DET_TH[3:0]
PEAK DETECTION THRESHOLD3210
0000 10mV
0001 15mV
0010 20mV
0011 25mV
0100 30mV
0101 35mV
0110 40mV
0111 45mV
1000 50mV
1001 55mV
1010 60mV
1011 65mV
1100 70mV
1101 75mV
1110 80mV
1111 85mV
Table 5.35 PEAK_DET_DUR[3:0] Bit Decode
PEAK_DET_DUR[3:0]
PEAK DETECTION MINIMUM
DURATION3210
0000 1ms
0 0 0 1 5.12ms
0 0 1 0 25.6 ms
0 0 1 1 51.2 ms
Q MICFIDCHIP
High-Side Current-Sense and Multiple 1°C Temperature Monitor
DS20005239A 55 EMC1704
DATASHEET
5.22 Sense Voltage Registers
The Sense Voltage registers store the measured VSENSE voltage across the sense resistor (RSENSE)
placed between the SENSE+ and SENSE- pins (see Section 4.1.1, "Current Measurement"). Note that
the bit weighting values are for representation of the voltage relative to full scale. There is no internal
scaling of data and all normal binary bit weightings still apply.
The Sense Voltage register data format is standard 2’s complement format with the positive full scale
value (7F_Fh) and negative full scale value (80_0h) equal to the programmed maximum sense voltage
(see Section 5.20, "Current Sense Sampling Configuration Register").
The Sign bit indicates the direction of current flow. If the Sign bit is ‘0’, current is flowing through
RSENSE from the SENSE+ pin to the SENSE- pin. If the Sign bit is ‘1’, the current is flowing through
RSENSE from the SENSE- pin to the SENSE+ pin. See Section 4.1.1, "Current Measurement" for
examples.
0 1 0 0 76.8 ms
0 1 0 1 102.4ms
0 1 1 0 128.0ms
0 1 1 1 256.0ms
1 0 0 0 384.0ms
1 0 0 1 512.0ms
1 0 1 0 768.0ms
1 0 1 1 1024.0ms
1 1 0 0 1536.0ms
1 1 0 1 2048.0ms
1 1 1 0 3072.0ms
1 1 1 1 4096.0ms
Table 5.36 Sense Voltage Registers
ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT
54h R Sense Voltage
High Byte
Sign 1024 512 256 128 64 32 16 00h
55h R Sense Voltage
Low Byte
8421 00h
Table 5.35 PEAK_DET_DUR[3:0] Bit Decode (continued)
PEAK_DET_DUR[3:0]
PEAK DETECTION MINIMUM
DURATION3210
Q MICFIDCHIP
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
EMC1704 56 DS20005239A
DATASHEET
5.23 Source Voltage Registers
The Source Voltage registers store the voltage measured at the SENSE+ pin (see Section 4.1.2,
"Voltage Measurement") as a digital value, VSOURCE, consisting of a high byte and low byte with five
of its LSBs always zero.
The measured voltage is determined by summing the bit weights of each bit set. For example, if VBUS
was 7.4V, the Source Voltage registers would read 0100_1110 for the high byte and 1100_0000b for
the low byte corresponding to 6V + 0.75V + 0.375V + 0.1875V + 0.0469V + 0.0234V = 7.383V.
The bit weightings are assigned for human interpretation. They should be disregarded when translating
the information via a computing system as shown in Section 4.1.2, "Voltage Measurement".
The Source Voltage registers cannot support negative values, and all values less than 0V will be
recorded as 0V.
5.24 Power Ratio Registers
Table 5.37 VSENSE Data Format
VSENSE BINARY HEX (AS READ BY REGISTERS)
Minus Full Scale 1000_0000_0000 80_0h
-2 LSB 1111_1111_1110 FF_Eh
-1 LSB 1111_1111_1111 FF_Fh
Zero 0000_0000_0000 00_0h
+1 LSB 0000_0000_0001 00_1h
+2 LSB 0000_0000_0010 00_2h
Plus Full Scale 0111_1111_1111 7F_Fh
Table 5.38 Source Voltage Registers
ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT
58h R VSOURCE
High Byte
12 6 3 1.5 0.75 0.375 0.1875 0.0938 00h
59h R VSOURCE
low Byte
0.0469 0.0234 0.0117 - - - - - 00h
Table 5.39 Power Ratio Registers
ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT
5Bh R Power Ratio
High Byte
32768 16384 8192 4096 2048 1024 512 256 00h
Q MICFIDCHIP ALERT ALERT
High-Side Current-Sense and Multiple 1°C Temperature Monitor
DS20005239A 57 EMC1704
DATASHEET
The Power Ratio registers store a power factor value that is used to determine the final average power
delivered to the system (see Section 4.1.3, "Power Calculation"). The power factor value is the result
of the multiplication of the VSENSE reading and the VSOURCE reading values shifted to a 16-bit number.
It represents the ratio of delivered power with respect to maximum power.
5.25 VSENSE Limit Registers
The VSENSE Limit registers store a high and low limit for VSENSE. VSENSE is compared against both
limits after each update.
The data format for the limit is a raw binary form that is relative to the maximum VSENSE that has been
programmed.
If the measured sense voltage meets or exceeds the high limit or drops below the low limit, the ALERT
pin is asserted and the VSENSE_HIGH or VSENSE_LOW status bits are set in the High Limit Status
or Low Limit Status registers (see Section 5.15 and Section 5.16).
APPLICATION NOTE: VSENSE is always checked to be greater than the high limit or less than the low limit including
when VSENSE is negative.
5.26 Source Voltage Limit Registers
The Source Voltage Limit registers store the high and low limits for VSOURCE. VSOURCE is compared
against all limits after each update.
If VSOURCE meets or exceeds the corresponding high limit or drops below the low limit, the ALERT pin
is asserted and the VSRC_HIGH or VSRC_LOW status bits are set in the High Limit Status or Low
5Ch R Power Ratio
Low Byte
128 64 32 16 8 4 2 1 00h
Table 5.40 VSENSE Limit Registers
ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT
60h R/W Sense Voltage
High Limit
Sign 1024 512 256 128 64 32 16 7Fh
61h R/W Sense Voltage
Low Limit
Sign 1024 512 256 128 64 32 16 80h
Table 5.41 Source Voltage Limit Registers
ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT
64h R/W Source
Voltage
High Limit
12 6 3 1.5 0.75 0.375 0.1875 0.0938 FFh
65h R/W Source
Voltage Low
Limit
12 6 3 1.5 0.75 0.375 0.1875 0.0938 00h
Table 5.39 Power Ratio Registers
ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT
Q MICFIDCHIP THERM ALERT ALERT ALERT
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
EMC1704 58 DS20005239A
DATASHEET
Limit Status registers (see Section 5.15 and Section 5.16).
5.27 Critical Voltage Limit Registers
The Critical Voltage Limit registers store the critical voltage limits (Vcrit limits) for VSENSE and VSOURCE.
If the respective value meets or exceeds its critical limit, the THERM pin will be asserted low and the
respective VCRIT status bit will be set (see Section 5.17, "Crit Limit Status Register"). It will remain
asserted until the respective value drops below its limit minus the respective Vcrit Hysteresis value.
5.28 GPIO Config and Status Register
The GPIO Configuration Register controls the GPIO pin.
Bit 3 - GPIO_MSK - Determines whether the GPIO pin, when configured as a GPIO input, will cause
the ALERT pin to be asserted. When the GPIO pin is configured as an output, this bit is ignored.
‘0’ - When configured as a GPIO input, the ALERT pin is asserted when the GPIO pin changes
states.
‘1’ (default) - When configured as a GPIO input, the ALERT pin is not asserted when the GPIO pin
changes states.
Bit 2 - GPIO_IN - Mirrors the pin state of the GPIO pin. This bit is read only and the GPIO Status bit
is set when the GPIO is configured as an input and this bit changes state.
Bit 1 - GPIO_OUT - Determines the output state of the GPIO pin when configured as an output. When
the GPIO pin is configured as an input, this bit is ignored.
‘0’ (default) - The GPIO pin state is low.
‘1’ - The GPIO pin state is high.
Bit 0 - GPIO_DIR - Determines the direction of the GPIO pin.
‘0’ (default) - The GPIO pin acts as an input.
‘1’ - The GPIO pin acts as an output.
Table 5.42 Critical Voltage Limit Registers
ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT
66h R/W Sense Voltage
Vcrit Limit
Sign 1024 512 256 128 64 32 16 7Fh
68h R/W Source Voltage
Vcrit Limit
12 6 3 1.5 0.75 0.375 0.1875 0.0938 FFh
69h R/W Sense Voltage
Vcrit Hysteresis
---2561286432 16 0Ah
6Ah R/W Source Voltage
Vcrit Hysteresis
- - - 1.5 0.75 0.375 0.1875 0.0938 0Ah
Table 5.43 GPIO Config and Status Register
ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT
70h R/W GPIO
Config
----GPIO_
MSK
GPIO_
IN
GPIO_
OUT
GPIO_
DIR
08h
Q MICFIDCHIP
High-Side Current-Sense and Multiple 1°C Temperature Monitor
DS20005239A 59 EMC1704
DATASHEET
5.29 Product Features Register (EMC1704-2 only)
The Product Features register indicates functionality that is selected by the user based on pin states
upon device power up. This register applies to the EMC1704-2 only. It will always read 00h for the
EMC1704-1.
Bits 7-4 - TH_SEL[3:0] - Indicates the selected Peak Detector Threshold setting as determined by the
TH_SEL pin. This value will be the default setting for the PEAK_DET_TH[3:0] bits and uses the same
decode as given in Table 5.34.
Bits 3-0 - DUR_SEL[3:0] - Indicates the selected Peak Detector minimum duration setting as
determined by the DUR_SEL pin. This value will be the default setting for the PEAK_DET_DUR[3:0]
bits and uses the same decode as given in Table 5. 35 .
5.30 Product ID Register
The Product ID Register holds a unique value that identifies the device.
5.31 SMSC ID Register
The Manufacturer ID register contains an 8-bit word that identifies SMSC as the manufacturer of the
EMC1704.
Table 5.44 Product Features
ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT
FCh R Product
Features
TH_SEL[3:0] DUR_SEL[3:0] 00h
Table 5.45 Product ID Register
ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT
FDhRProduct ID00111011 3Bh
Table 5.46 Manufacturer ID Register
ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT
FEhRSMSC ID01011101 5Dh
G MICFIDCHIP
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
EMC1704 60 DS20005239A
DATASHEET
5.32 Revision Register
The Revision register contains an 8-bit word that identifies the die revision.
Table 5.47 Revision Register
ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT
FFh R Revision10000010 82h
G MICRDCHIP A D SEEDETNLA' We / 14 3 ‘ T \ ‘ ‘ ‘ 92 / $51 */ '/‘7 iiiii ii E Z/ a 1/ / MU U U l fim 7' 001D— 0020X45 'rggfingJ—L14XbAA w W “0004 ‘ w‘ j r )- N <)> mag; SEATING PLANE A1i m m
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
DS20005239A 61 EMC1704
DATASHEET
Chapter 6 Package Description
6.1 EMC1704-1 Package Drawing (14-Pin SOIC)
Figure 6.1 14-Pin SOIC Package Drawings
G MICFIDCHIFI R0003 MIN 7 0.010 “ iiiiii , GAUGE PLANE R0003 M|N %’ SEATING PLANE 0° - 8° (0.041) D ETAIL "A" DIST—T W127 Illlnlir 5‘35 43 THE USER MAY MODIFY THE PCB LAND PATTERN DIMENSIONS, BASED ON THEIR EXPERIENCE AND/OR PROCESS CAPABILITY. RECOMMENDED PCB LAND PATTERN
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
EMC1704 62 DS20005239A
DATASHEET
Figure 6.2 14-Pin SOIC Package Drawings Detail “A”
Figure 6.3 14-Pin SOIC Recommended PCB Land Pattern
6‘ MICRDCHIP COMMON DIMENSIONS SYMBOL MIN NOM MAX NOTE REMARK A 0.053 7 0,069 7 OVERALL PKG HEIGHT AI 0,004 7 0.0I0 7 STANDOEE A2 0.049 7 0.065 7 BODY THICKNESS D 0.336 0 340 0.344 3 "X" BODY SIZE E 0228 0 236 0.244 7 LEAD SPAN EI 0.I50 0.I54 OISE 3 ‘Y‘ BODY SIZE L 0.0I5 0 025 0.035 7 LEAD EDOT LENGTH b 0.0I2 7 0020 2,4 LEAD WIDTH c 0.007 7 0.0I0 4 LEAD FOOT THICKNESS e 0050 BSC 7 LEAD PITCH NOTES: 1 ALL DIMENSIONS ARE IN INCHES 2 TRUE POSITION SPREAD TOLERANCE OF EACH LEAD IS : 0 0049 inches AT MAXIMUM MATERIAL CONDITION. DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OF THE FOOT. 3 DIMENSION "D" DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS ORGATE BURRS. MAXIMUM MOLD FLASH. PROTRUSIONS OR GATE BURRS IS 0.006" PER END. DIMENSION 'EI" DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. MAXIMUM INTERLEAD FLASH OR PROTRUSION IS 0.010" PER SIDE. 'D1" & "E1" DIMENSIONS ARE DETERMINED AT DATUM PLANE "H" AND INCLUDE ANY MISMATCH BETWEEN THE TOP AND BO'I'I'OM OF THE PLASTIC BODY. 4 'b' 8" 'APPLY TO THE FLAT SECTION OF THE LEAD BEI'WEEN 0.004 TO 0.010" FROM THE LEAD TIP. 5 THE CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT. THEN A PIN 1 IDENTIFIER MUST BE LOCATED WITHIN THE IN DEX AREA INDICATED.
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
DS20005239A 63 EMC1704
DATASHEET
Figure 6.4 14-Pin SOIC Dimensions and Notes
TERMINAL #1 IDENTIFIER AREA (DIZ X E12) A TOP VIEW (A2) I A1 SIDE VIEW Q MICRDCHIFI ‘ D2 A 18X K 4 <7 terminal="" #i="" ‘5="" identifier/area="" uiu="" (912x512)="" 4="" i="" ,="" i="" c/exposed="" pada="" e="" 2="" e2="" 3’="" i="" e="" 3="" stl="" ;="" c="" i="" h="" flifl="" hi="" 4.—="" ligxh="" i="" boti'om="" view="" 3—d="" views="">
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
EMC1704 64 DS20005239A
DATASHEET
6.2 EMC1704-2 Package Drawing (16-Pin QFN 4mm x 4mm)
Figure 6.5 16-Pin QFN 4mm x 4mm Package Drawings
Q MlcncICHIp 0.05 OVERALL PACKAGE HEIGHT 0.02 STANDOFF D 20 REF LEAD
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
DS20005239A 65 EMC1704
DATASHEET
Figure 6.6 16-Pin QFN 4mm x 4mm Dimensions and Notes
Figure 6.7 16-Pin QFN 4mm x 4mm PCB Footprint
G MICFIDCHIFI DIAMETER : 0 so m 5 CR f DDDDD DUDE] DDDDD DEED (,3. DDDDDDDDEEDDDDD \ sn'isn: DDDmDDD EDD EDD o \ijx
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
EMC1704 66 DS20005239A
DATASHEET
6.3 EMC1704 Package Markings
Figure 6.8 EMC1704-1 Package Markings
Figure 6.9 EMC1704-2 Package Markings
TOP
BOTTOM
PB-FREE/GREEN SYMBOL
(100% Sn)
MINIMUM CIRCLE "R"
DIAMETER = 0.80 mm
ALL TOP LINES: CENTER
HORIZONTAL ALIGNMENT
2x 1.5pt
0.60
PIN 1
PIN 1
Line 1-T – SMSC Logo
Line 2-T – Device Number, Version E M C 1 7 0 4
Line 3-T – Revision, Date Code,
Last 7 digits of Lot Number
-1
R Y WW 1 3 4 5 6a2
Line 1-B – Engineering Code
Line 2-B – Vendor Code and Country
of Origin Abbreviation
e3
2x 1.5pt
BOTTOM
BOTTOM MARKING NOT ALLOWED
LINE: 1 – SMSC Logo without circled (R) symbol
LINE: 2 – Device ID - Version
LINE: 3 – Last 7 digits of Lot Number
LINE: 4 – Revision and Country Code (RCC)
LINES 1 to 3: CENTER HORIZONTAL ALIGNMENT
LINE 4: LEFT HORIZONTAL ALIGNMENT
PB-FREE/GREEN SYMBOL
(Matte Sn)
0.41
3x 0.56
TOP
e3
PIN 1
1704
CCR
123456a
-2E
6‘ MICROCHIP
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
DS20005239A 67 EMC1704
DATASHEET
Chapter 7 Datasheet Revision History
Table 7.1 Customer Revision History
REVISION LEVEL & DATE SECTION/FIGURE/ENTRY CORRECTION
DS20005239A (10-23-13) Table 2.2, "Electrical
Specifications"
Updated VDD Pin Supply Current for
IDD_ALL_STANDBY Typ and Max specifications.
Rev. 1.2 (09-27-10) Table 2.1, "Absolute
Maximum Ratings"
Added spec for voltage between SENSE pins.
Table 2.2, "Electrical
Specifications"
Updated all electrical specs for current sense
measurement, supply current, and peak detector.
Electrical Specifications
APPLICATION NOTE:
Added note: The EMC1704 is trimmed at the
80mV range for best accuracy.
Section 5.13, "Beta
Configuration Registers"
“BETAx[2:0] bits” changed to “BETAx[3:0] bits”.
Rev. 1.1 (06-16-10) System Diagram Updated.
Section 5.15, "High Limit
Status Register" and Section
5.16, "Low Limit Status
Register"
ALERT# pin won’t be set if masked.
Table 5.32, "Current
Sensing Range (Full Scale
Range) Settings"
Changed title from Current Sensing Range to
Current Sensing Range (Full Scale Range)
Settings.
Table 2.2, "Electrical
Specifications"
TA upper limit changed from 125°C to 85°C.
Bus voltage symbol changed from VSOURCE to
VBUS.
IDD at 4 conversions/second with dynamic
averaging enabled changed from 0.95 typ and
1.375 max to 0.9 typ and 1.3 max.
IDD at 4 conversions/second with dynamic
averaging disabled changed from 0.80 typ to 0.8
typ.
IDD at 1 conversion/second with dynamic
averaging disabled changed from 650 typ and 1
max to 0.7 typ and 1.0 max.
VSENSE Full Scale Sense Range values changed
from 0 min and +/- max values to - min values and
+ max values; conditions changed.
Total Unadjusted VSENSE Measurement Error
(VSENSE_TUE) renamed VSENSE Measurement
Error (VSENSE_ERR); typ value at 20-80mV FSR
changed from 0.8 to +/-0.5 and max changed from
+/-1.5 to +/-1; typ value at 10mV FSR changed
from 0.2 to +/-0.8 and max changed from +/-2 to
+/-1.5.
VSENSE_OFF condition added.
VSENSE Measurement Gain Error has new symbol
VSENSE_GN; added typ +/-0.2 and changed max
from 0.5 to +/-0.5.
VTH_ERR changed from +/-20 to +/-2.
VSOURCE_ERR changed conditions; typ changed
from 0.05 to +/-0.2 and max changed from 1 to +/-
0.5.
Added Power Ratio Measurement specs.
Data hold time changed from 0.6 min and 6 max
to 0 min and no max.
Q MICFIDCHIP
High-Side Current-Sense and Multiple 1°C Temperature Monitor
Datasheet
EMC1704 68 DS20005239A
DATASHEET
Figure 4.1, "EMC1704
System Diagram"
Diagram modified
Section 5.32, "Revision
Register"
Functional revision C changed default from 81h to
82h.
Rev. 1.0 (11-09-09) Formal release
Table 7.1 Customer Revision History (continued)
REVISION LEVEL & DATE SECTION/FIGURE/ENTRY CORRECTION

Products related to this Datasheet

IC TEMP MONITOR I2C/SMBUS 16QFN
IC TEMP MONITOR I2C/SMBUS 16QFN
IC TEMP MONITOR I2C/SMBUS 16QFN