ATA5577C Datasheet by Microchip Technology

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Features
Contactless power supply
Contactless Read/Write data transmission
Radio frequency fRF from 100kHz to 150kHz
Basic Mode or Extended Mode
Compatible with Atmel® T5557, ATA5567
Replacement for Atmel e5551/T5551 in most common operation modes
Configurable for ISO/IEC 11784/785 compatibility
Total 363 bits EEPROM memory: 11 blocks (32 bits + 1 lock bit)
7 32 bits EEPROM User Memory, including 32-bit Password Memory
2 32 bits for unique ID
1 32-bit option register in EEPROM to set up the Analog Front End:
Clock and gap detection level
Improved downlink timing
Clamp and modulation voltage
Soft modulation switching
Write damping like the Atmel T5557/ATA5567 or with resistor
Downlink protocol
1 32-bit configuration register in EEPROM to set up:
Data rate:
RF/2 to RF/128, binary selectable or
Fixed Basic Mode rates
Modulation/coding:
Bi-phase, Manchester, FSK, PSK, NRZ
Other options:
Password Mode
Max block feature
Direct Access Mode
Sequence terminator(s)
Blockwise write protection (lock bit)
Answer-On-Request (AOR) Mode
Inverse data output
Disable test mode access
Fast downlink (~6Kbits/s versus ~3Kbits/s)
OTP functionality
Init delay (~67ms)
ATA5577C
Read/Write LF RFID IDIC 100 to 150kHz
DATASHEET
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High Q-antenna tolerance due to build in options
Adaptable to different applications: access control, animal ID and waste management
On-chip trimmed antenna capacitor:
250pF/330pF (±3%)
75pF/130pF (on request)
Without on-chip capacitor (on request)
Pad options
Atmel ATA5577M1C
100µm 100µm for wire bonding or flip chip
Atmel ATA5577M2C
200µm 400µm for direct coil bonding
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1. Description
The Atmel® ATA5577C is a contactless read/write IDentification IC (IDIC®) for applications in the 125kHz or 134kHz
frequency band. A single coil connected to the chip serves as the IC's power supply and bi-directional communication
interface. The antenna and chip together form a transponder or tag.
The on-chip 363-bit EEPROM (11 blocks with 33 bits each) can be read and written block-wise from a base station (reader).
Data is transmitted from the IDIC (uplink) using load modulation. This is achieved by damping the RF field with a resistive
load between the two terminals, coil 1 and coil 2. The IC receives and decodes serial base station commands (downlink),
which are encoded as 100% amplitude modulated (OOK) pulse-interval-encoded bit streams.
2. Compatibility
The Atmel ATA5577C is designed to be compatible with the Atmel T5557/ATA5567. The structure of the configuration
register is identical. The two modes, basic mode and extended mode, are also available. The Atmel ATA5577C is able to
replace the Atmel e5551/T5551 in most common operation modes. In all applications, the correct functionality of the
replacements must be evaluated and proved.
For further details, refer to the Atmel web site for product-relevant application notes.
3. System Block Diagram
Figure 3-1. RFID System Using Atmel ATA5577C Tag
Data
Reader
or
Base station
Atmel ATA5577
Power
1) Mask option
1)
Transponder
Coil interface
Controller
Memory
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4. Atmel ATA5577C - Functional Blocks
Figure 4-1. Block Diagram
4.1 Analog Front End (AFE)
The AFE includes all circuits that are directly connected to the coil terminals. It generates the IC's power supply and handles
the bi-directional data communication with the reader. It consists of the following blocks.
Rectifier to generate a DC supply voltage from the AC coil voltage
Clock extractor
Switchable load between Coil1 and Coil2 for data transmission from the tag to the reader
Field-gap detector for data transmission from the base station to the tag
ESD-protection circuitry
4.2 AFE Option Register
The option register maintains a readable shadow copy of the data held in the EEPROM block 3, page 1. This contains the
analog front end's level and threshold settings, as well as enhanced downlink protocol selection with which the device can be
fine tuned for perfect operation and all application environments. It is continually refreshed during read-mode operation and
(re)-loaded after every power-on reset (POR) event or reset command. By default, the option register is pre-programmed
according to Table 10-1 on page 39.
4.3 Data-rate Generator
The data rate is binary programmable to operate at any even-numbered data rate between RF/2 and RF/128, or to any of the
fixed, basic-mode data rates (RF/8, RF/16, RF/32, RF/40, RF/50, RF/64, RF/100 and RF/128).
4.4 Write Decoder
The write decoder detects the write gaps and verifies the validity of the data stream according to the Atmel® e555x downlink
protocol (pulse interval encoding).
Memory
(363-bit EEPROM)
Modulator
AFE option register
Analog front end
Data-rate
generator
Write
decoder
POR
Coil 2
Coil 1
Controller
Test logic HV generator
Input register
Mode register
1) Mask option
1)
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4.5 HV Generator
This on-chip charge pump circuit generates the high voltage required to program the EEPROM.
4.6 DC Supply
Power is supplied to the IDIC externally via the two coil connections. The IC rectifies and regulates this RF source, and uses
it to generate its supply voltage.
4.7 Power-On Reset (POR)
The power-on reset (POR) circuit blocks the voltage supply to the IDIC until an acceptable voltage threshold has been
reached.
4.8 Clock Extraction
The clock extraction circuit uses the external RF signal as its internal clock source.
4.9 Controller
The control logic module executes the following functions:
Load mode register with configuration data from EEPROM block 0 after power on and during reading
Load option register with the settings for the analog front end stored in EEPROM page 1, block 3 after power on and
during reading
Control all EEPROM memory read/write access and data protection
Handles the downlink command decoding detecting protocol violations and error conditions
4.10 Mode Register
The mode register maintains a readable shadow copy of the configuration data held in block 0 of the EEPROM. It is
continually refreshed during read mode and (re-)loaded after every POR event or reset command. On delivery, the mode
register is pre-programmed according to Table 10-1 on page 39.
4.11 Modulator
The modulator encodes the serialized EEPROM data for transmission to a tag reader or base station. Several types of
modulation are available including Manchester, bi-phase, FSK, PSK, and NRZ.
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4.12 Memory
The memory is a 363-bit EEPROM, which is arranged in 11 blocks of 33 bits each. Each block includes a single lock bit,
which is responsible for write-protecting the associated block. Programming takes place on a block basis, so a
complete block (including lock bit) can be programmed with a single command. The memory is subdivided into two
page areas. Page 0 contains eight blocks, and page 1 contains three blocks. All 33 bits of a block, including the lock bit, are
programmed simultaneously.
Block 0 of page 0 contains the mode/configuration data, which is not transmitted during regular-read mode operations.
Addressing block 0 will always affect block 0 of page 0 regardless of the page selector. Block 7 of page 0 may be used as
a protection password.
Block 3 of page 1 contains the analog front end option register, which is also not transmitted during regular-read mode
operation.
Bit 0 of every block is the lock bit for that block. Once locked, the block (including the lock bit itself) is not re-
programmable via the RF field.
Blocks 1 and 2 of page 1 contain traceability data and are transmitted with the modulation parameters defined in the
configuration register after the opcode “11” is issued by the reader (see Figure 5-10 on page 19 and Figure 5-11 on page 19).
The traceability data blocks are programmed and locked by Atmel®.
Figure 4-2. Memory Map
0 1.........................................................................................32
Page 1
LAnalog front end option set-up Block 3
1 Traceability data Block 2
1 Traceability data Block 1
LPage 0 configuration data Block 0
Page 0
L User data or password Block 7
L User data Block 6
L User data Block 5
L User data Block 4
L User data Block 3
L User data Block 2
L User data Block 1
LConfiguration data Block 0
32 bits
Not transmitted
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4.13 Traceability Data Structure/Unique ID
Blocks 1 and 2 of page 1 contain the traceability data and are programmed and locked by Atmel® during production testing
(1). The most significant byte of block 1 is fixed to E0h, the allocation class (ACL). as defined in ISO/IEC 15963-1. The
second byte is, therefore, defined in ISO/IEC 7816-6 as Atmel manufacturer ID (15h). The following 5 bits indicate chip ID
(CID - "00001b" for Atmel ATA5577M1, and "00010" for Atmel ATA5577M2), and the next bits (IC revision, ICR) are used by
Atmel for the IC and/or foundry version of the Atmel ATA5577C.
The lower 40 bits of data encode Atmel's traceability information, and conform to a unique numbering system (unique ID).
These 40 data bits contain the lot ID (year, quarter, number), wafer number (Wafer#), and die number of the wafer (DW).
Note: 1. This is only valid for sawn wafer on foil delivery.
Figure 4-3. Atmel ATA5577C Traceability Data Structure
ACL Allocation class as defined in ISO/IEC 15963-1 = E0h
MFC Atmel Corporation manufacturer code as defined in ISO/IEC 7816-6 = 15h
CID 5 bit Chip ID for identification of the different products
“00001b” for Atmel ATA5577M1 and “00010b” for Atmel ATA5577M2
ICR 3-bit IC revision to identify foundry and/or revision of IC
Year 1-digit BCD encoded year of manufacturing
Quarter 2 bits for quarter of manufacturing
Number 14 bits of consecutive number
Wafer# 5 bits for wafer number
DW 15 bits designating sequential die number on wafer
Example: “E0h“ “15h“ “0000 1b“ “010b“ “9h“ “00b“ “00b“
8 bit 8 bit 5 bit 3 bit 4 bit 2 bit 2 bit
Bit No. 1 8 9 16 17 21 22 24 25 28 29 30 31 32
Block 1 ACL MFC CID ICR Year Quarter Number
Bit value 63 MSB 32
Bit value 31 LSB 0
Block 2 Number Wafer# DW
Bit No. 1 12 13 17 18 31 32
12 bit 5 bit 15 bit
Example: “0000 1010 0100b“ “0110 0b“ “000 0100 1101 0010b“
(Example is for Atmel ATA5577M1330C, Year: 2009, Quarter: 1st, Number: 0164, Wafer#: 12, DW: 1234)
(2) (2y Nukes: 1. If the opnon key Is 6 or 9, lhe from end opnons are amlvaked. For all olher values, they take on lhe default stale (all 0). If AtmeL
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5. Operating the Atmel ATA5577C
5.1 Configuring the Atmel ATA5577C
Table 5-1. Block 3 Page 1– Analog Front End Option Set-up
L 1 2 3 45678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
0000000000
Lock Bit
Option Key(1)
Soft Modulation
Clamp Voltage
Modulation Voltage
Clock-detection Threshold
Gap-detection Threshold
Write Damping
Demod Delay
Downlink Protocol
Reserved for Future Use
(RFU)
0 Unlocked
1Locked
Off 0 0 0 0 0 Fixed Bit Length
One pulse weak 0 1 0 0 1 Long Leading Reference
One pulse strong 1 0 0 1 0 Leading Zero Reference
Two pulses 1 1 0 1 1 1 of 4 Coding Reference
Smooth111 00None
Clamp med typ(2). 6Vp0 0 0 1 One pulse
RFU 0 1 1 0 Two pulses
Clamp low typ(2). 5Vp10 11RFU
Clamp high typ(2). 8Vp1 1 0 0 0 WD + low att.
Mod med typ(2). 2Vp0 0 0 0 1 WD + high att.
RFU 0 1 0 1 0 Low att.
Mod low typ(2). 1Vp1 0 0 1 1 High att.
Mod high typ(2). 3Vp1 1 1 0 0 WD only
Clkdet med typ. 550mVp 0 0 1 0 1 Off
RFU 0 1 1 1 0 RFU
Clkdet low typ. 250mVp10 111RFU
Clkdet high typ. 800mVp11
Gapdet med typ. 550mVp00
RFU 0 1
Gapdet low typ. 250mVp10
Gapdet high typ. 850mVp11
Notes: 1. If the option key is 6 or 9, the front end options are activated. For all other values, they take on the default state (all 0). If
the option key is 6, then the complete page 1 (i.e., option register and traceability data) cannot be overwritten by any test
write command. This means that if the lock bits of the three blocks of page 1 are set and the option key is 6, then all of
page 1's blocks are locked against change.
2. Weak field condition
L 5 6 7 8 13141516 21222324 29303132 Notes: 1. If the Master Keyls 6 me 1est mode access IS alsab ed L 5 6 7 5 13141516 21222324 29303132 No e: 1. If (he Keyls 6 and bl1 15 Is set, the test mode access Is disable and me extended mode 15 aclwe AtmeL
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Table 5-2. Block 0 Page 0 – Configuration Mapping in Basic Mode
L 1 2 3 45678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
0000000 0 0 00
Lock Bit
Master Key
(1), (2)
Data Bit
Rate
Modulation
PSKCF
AOR
MAX
BLOCK
PWD
ST Sequence Terminator
Init Delay
RF/8000 00RF/2
RF/16001 01RF/4
0 Unlocked RF/32 0 1 0 1 0 RF/8
1 Locked RF/40 0 1 1 1 1 Res.
RF/50100 00000Direct
RF/64101 00001PSK1
RF/100110 00010PSK2
RF/128111 00011PSK3
00100FSK1
00101FSK2
00110FSK1a
00111FSK2a
0 1 0 0 0 Manchester
1 0 0 0 0 Bi-phase
11000Reserved
Notes: 1. If the Master Key is 6 the test mode access is disabled
2. If the Master Key is neither 6 nor 9, the extended function mode and Init Delay are disabled
Table 5-3. Block 0 Page 0 – Configuration Map in Extended Mode (X-mode)
L 1 2 3 45678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
0000 1
Lock Bit
Master Key(1), (2) n5 n4 n3 n2 n1 n0
Data Bit Rate
RF/(2n+2)
X-mode
Modulation
PSK-
CF
AOR
OTP
MAX-
BLOCK
PWD
Seq. Start Marker
Fast Downlink
Inverse Data
Init Delay
00 RF/2
Direct0000001 RF/4
0 Unlocked
Locked
PSK1 0000110 RF/8
1 PSK2 0001011 Res.
PSK3 00011
FSK100100
FSK200101
Manchester01000
Bi-phase 10000
Differential bi-
phase 11000
Note: 1. If the Master Key is 6 and bit 15 is set, the test mode access is disabled and the extended mode is active
2. If the Master Key is 9 and bit 15 is set, the extended mode is enabled
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5.2 Soft Modulation Switching
Abrupt rise of the modulation signal at the beginning of modulation - especially in applications with high-quality antennas -
could lead to clock losses and, therefore, timing violations. To prevent this, several soft modulation settings can be chosen
for a soft transition into the modulation state.
Soft modulation should only be used in combination with modulation schemes and data rates which do not involve high
frequency-modulation changes.
5.3 Demodulation Delay
Soft modulation will cause imbalance in modulated and unmodulated phases. Depending on the soft modulation setting, the
unmodulated phase can be longer than the modulated phase. To balance out this mismatch, the switch point from the
modulated to the unmodulated phase can be delayed for one or two pulses.
These delays and soft modulation switching should only be used in combination with modulation schemes and data rates
which do not involve high frequency-modulation changes.
Table 5-4. Soft Modulation Switching Scheme
Bit 5-7 (bl3 p1) 000 010 100 110 111
Description No soft
modulation One pulse weak One pulse strong Two pulses Smooth
dampclamp 75% 50%
Table 5-5. Demodulation Delay Scheme
Bits 19 and 20 (bl3 p1) Description
00
01
10
C1-C2
mod
C1-C2
mod
No demodulation delay
Demodulation delay
one pulse
Demodulation delay
two pulses
C1-C2
mod
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5.4 Write Damping
Reader-to-tag communication is initialized by sending a start gap from the reader station. To ease gap detection with respect
to detecting subsequent field gaps reliably, receive damping and low attenuation are activated by default.
Especially in combination with high quality coils, a higher attenuation factor can be switched on to fasten the relaxation time.
Using antenna coils with low Q-factor might make it feasible to switch off the write damping. This results in better energy
balance and, therefore, improved write distance.
5.5 Initialization and Init-Delay
The power-on reset (POR) circuit remains active until an adequate voltage threshold has been reached. This, in turn,
triggers the default initialization delay sequence. During this configuration period of about 192 field clocks, the Atmel®
ATA5577C is initialized with the configuration data stored in EEPROM block 0 and with the options stored in block 3, page 1.
Tag modulation in regular-read mode will be observed about 3ms after entering the RF field. If the init-delay bit is set, the
Atmel ATA5577C variant with damping during initialization remains in a permanent damping state for t ~ 69ms at f = 125kHz.
The Atmel ATA5577C variant without damping will start modulation after t ~ 69ms without damping.
Init delay = 0: TINIT = 192 TC + TPOR ~ 3ms; TC = 8µs at f = 125kHz
(TPOR denotes delay for POR and depends on environmental conditions)
Init delay = 1: TINIT = (192 + 8192) TC + TPOR ~ 69ms
Any field gap occurring during this initialization phase will restart the complete sequence. After this initialization time, the
Atmel ATA5577C enters regular-read mode, and modulation starts automatically using the parameters defined in the
configuration register.
5.6 Modulator in Basic Mode
The modulator consists of data encoders for the following types of modulation in Basic mode:
5.7 Maxblock
After entering regular-read mode, the Atmel ATA5577C transmits the data content starting with block 1. The MAXBLK
setting defines how many data blocks will be transmitted.
Table 5-6. Types of Modulation in Basic Mode
Mode Direct Data Output
FSK1a(1) FSK/8 - FSK/5 0 = RF/8 1 = RF/5
FSK2a(1) FSK/8 - FSK/10 0 = RF/8 1 = RF/10
FSK1(1) FSK/5 - FSK/8 0 = RF/5 1 = RF/8
FSK2(1) FSK/10 - FSK/ 8 0 = RF/10 1 = RF/8
PSK1(2) Phase change when input changes
PSK2(2) Phase change on bit clock if input high
PSK3(2) Phase change on rising edge of input
Manchester 0 = falling edge, 1 = rising edge
Bi-phase 1 creates an additional mid-bit change
NRZ 1 = damping on, 0 = damping off
Notes: 1. A common multiple of bit rate and FSK frequencies is recommended.
2. In PSK mode the selected data rate has to be an integer multiple of the PSK sub carrier frequency.
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5.8 Password
When password mode is active (PWD = 1), the first 32 bits after the opcode are regarded as the password. They are
compared bit by bit with the contents of block 7, starting at bit 1. If the comparison fails, the Atmel ATA5577C will not
program the memory. Instead it will restart in regular-read mode once the command transmission is finished.
Note: In password mode, MAXBLK should be set to a value lower than 7 to prevent the password from being trans-
mitted by the Atmel ATA5577C.
Each transmission of the direct access command (2 opcode bits, 32-bit password, “0” bit, plus 3 address bits = 38 bits)
needs about 18ms. Testing all possible combinations (about 4.3 billion) would take about two years.
5.9 Answer-On-Request (AOR) Mode
When the AOR bit in the configuration register is set, the Atmel® ATA5577C does not start modulation in the regular-read
mode after loading configuration block 0. The tag waits for a valid AOR data stream (wake-up command) from the reader
before modulation is enabled. The wake-up command consists of the opcode ("10" or "11") followed by a valid password.
The selected tag will remain active until the RF field is turned off or a new command with a different password is transmitted,
which may address another tag in the RF field.
Figure 5-1. Answer-on-request (AOR) Mode, Fixed Bit-length Protocol Example
Table 5-7. Atmel ATA5577C - Modes of Operation
PWD AOR Behavior of Tag after Reset Command or POR De-activate Function
1 1
Answer-On-Request (AOR) mode:
- Modulation starts after wake up with a matching password
- Programming needs valid password
Command with non-matching
password deactivates the
selected tag
1 0
Password mode:
- Modulation in regular-read mode starts after reset
- Programming and direct access needs valid password
0-
Normal mode:
- Modulation in regular-read mode starts after reset
- Programming and direct access without password
Loading
configuration
and option No modulation
because AOR = 1
POR
VCoil1 - Coil2
Modulation
AOR wake-up command
(with valid PWD)
AH Lugs read? i) AtmeL
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Figure 5-2. Anticollision Procedure Using AOR Mode
"Select a single tag"
send OPCODE + PWD
"wake-up command"
Initialize tags with
AOR = 1, PWD = 1
POWER-ON RESET
Read configuration
Password correct?
Tag
Reader
Decode data
No
No
Yes
Yes
Send block 1 to MAXBLK
Receive damping ON
Enter AOR mode
Field ON OFF
Field OFF ON
Wait for OPCODE +
PWD "wake-up
command"
Wait for tW > 2.5ms
All tags read?
Exit
Makes: 1. A common multiple oi bit rate and FSK frequencies is recommended. AtmeL
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5.10 ATA5577C in Extended Mode (X-mode)
In general, setting of the master key (bits 1 to 4) of block 0 to the value 6 or 9 together with the X-mode bit will enable the
extended mode functions such as the binary bit-rate generator, OTP functionality, fast downlink, inverse data output and
sequence start marker.
Master key = 9: Test mode access and extended mode are both enabled.
Master key = 6: Any test mode access will be denied but the extended mode is still enabled.
Any other master key setting will prevent activation of the Atmel® ATA5577C extended mode options, even when the X-
mode bit is set.
5.10.1 Modulator in Extended-Mode
5.10.2 Binary Bit-rate Generator
In extended mode the data rate is binary programmable to operate at any even-numbered data rate between RF/2 and
RF/128 as given in the formula below.
Data rate = RF / (2n + 2)
5.10.3 OTP Functionality
If the OTP bit is set to 1, all memory blocks are write protected and behave as if all lock bits are set to 1. If, in addition, the
master key is set to 6, the Atmel ATA5577C mode of operation is locked forever (one-time-programming functionality).
If the master key is set to 9, test-mode access allows re-configuration of the tag.
5.10.4 Fast Downlink
In the optional fast downlink mode, the time between two gaps is reduced. In the fixed bit-length protocol mode, there are
nominally 12 field clocks for a 0 and 28 field clocks for a 1. When there is no gap for more than 32 field clocks after a
previous gap, the Atmel ATA5577C in the fixed bit length protocol mode will exit the downlink mode (refer to Table 5-10 on
page 20).
The fast downlink mode timings for the long-leading-reference protocol are shown in Table 5-11 on page 21, for the leading-
zero-reference protocol in Table 5-12 on page 21 and for the 1-of-4-coding protocol in Table 5-12 on page 21.
Table 5-8. Atmel ATA5577C Types of Modulation in Extended Mode
Mode Direct Data Output Encoding Inverse Data Output Encoding
FSK1(1) FSK/5 - FSK/8 0 = RF/5; 1 = RF/8 FSK/8 - FSK/5 0 = RF/8; 1 = RF/5 (= FSK1a)
FSK2(1) FSK/10 - FSK/8 0 = RF/10; 1 = RF/8 FSK/8 -
FSK/10 0 = RF/8; 1 = RF/10 (= FSK2a)
PSK1(2) Phase change when input changes Phase change when input changes
PSK2(2) Phase change on bit clock if input high Phase change on bit clock if input low
PSK3(2) Phase change on rising edge of input Phase change on falling edge of input
Manchester 0 = falling edge, 1 = rising edge mid bit 1 = falling edge, 0 = rising edge mid bit
Bi-phase 1 creates an additional mid-bit change 0 creates an additional mid-bit change
Differential bi-phase 0 creates an additional mid-bit change 1 creates an additional mid-bit change
NRZ 1 = damping on, 0 = damping off 0 = damping on, 1 = damping off
Notes: 1. A common multiple of bit rate and FSK frequencies is recommended.
2. In PSK mode the selected data rate has to be an integer multiple of the PSK sub-carrier frequency.
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5.10.5 Inverse Data Output
In extended mode (X-mode), the Atmel ATA5577C supports an inverse data output option. If inverse data is enabled, the
modulator shown in Figure 5-3 works on inverted data (see Figure 5-8 on page 14). This function is supported for all basic
types of encoding.
Figure 5-3. Data Encoder for Inverse Data Output
5.11 Tag-to-Reader Communication
During read operation (uplink mode), the data stored within the EEPROM are cycled, and the coil 1 and Coil 2 terminals are
load modulated. This resistive load modulation can be detected at the reader device.
5.11.1 Regular-read Mode
In regular-read mode, data from the memory are transmitted serially, starting with block 1, bit 1, up to the last block (for
example, 7), bit 32. The last block to be read is defined by the mode parameter field MAXBLK in EEPROM block 0. When
the data block addressed by MAXBLK has been read, data transmission restarts with block 1, bit 1.
The user may limit the cyclic data stream in regular-read mode by setting MAXBLK between 0 and 7 (representing each of
the eight data blocks). If set to 7, blocks 1 through 7 can be read. If set to 1, only block 1 is transmitted continuously. If set to
0, the contents of the configuration block (normally not transmitted) can be read. In the case of MAXBLK = 0 or 1, regular-
read mode cannot be distinguished from block-read mode.
Figure 5-4. Examples of Different MAXBLK Settings
Every time the Atmel® ATA5577C enters regular or block read mode, the first bit transmitted is a logical 0. The data stream
starts with block 1, bit 1, continues through MAXBLK bit 32, and, if in regular-read mode, cycles continuously.
Note: This behavior is different from that of the original Atmel e555x, and helps to decode PSK-modulated data.
FSK2
MUX
Data output
Data clock
ModulatorInverse data output
Intern out
data
Bi-phase
Manchester
FSK1
Direct/NRZ
PSK3
PSK2
PSK1
CLK
DSync
XOR
R
0
Loading block 0
Block 4 Block 5 Block 2Block 1Block 1
0
Loading block 0
Block 0 Block 0 Block 0Block 0Block 0
0
MAXBLK = 5
MAXBLK = 0
MAXBLK = 2
Loading block 0
Block 2 Block 1 Block 1Block 2Block 1
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5.11.2 Block-read Mode
With the direct-access command, only the addressed block is read repetitively. This mode is called block-read mode. Direct
access is entered by transmitting the page access opcode (“10” or “11”), a single 0 and the requested 3-bit block address
when the tag is in normal mode.
In password mode (PWD bit set), direct access to a single block needs the valid 32-bit password to be transmitted after the
page access opcode, followed by a 0 and the 3-bit block address. If the transmitted password does not match the contents of
block 7, the Atmel ATA5577C tag returns to regular-read mode.
Note: A direct access to block 0 of page 1 will read the configuration data of block 0, page 0.
A direct access to block 4 to 7 of page 1 reads all data bits as zero.
5.11.3 Sequence Terminator (Basic Mode)
The sequence terminator (ST) is a special damping pattern which is inserted in front of the first block and may be used to
synchronize the reader. This sequence terminator is recommended only for FSK and Manchester coding. This basic mode
sequence terminator consists of four bit periods. During the first and third bit period, the data value is 1. During the second
and fourth bit periods, modulation is switched off (using Manchester encoding, switched on).
Bi-phase modulated data blocks need fixed leading and trailing bits in combination with the sequence terminator to be
reliably identified.
The sequence terminator may be individually enabled by setting mode bit 29 (ST = 1) in basic mode (X-mode = 0).
In the regular-read mode, the sequence terminator is inserted at the start of each MAXBLK-limited read data stream.
In block-read mode, after any block write or direct access command, or if MAXBLK was set to 1, the sequence terminator is
inserted before the transmission of the selected block.
This behavior is different from that of previous ICs (Atmel e5551/T5551, T5554). For further details, refer to the relevant
application notes.
Figure 5-5. Read Data Stream with Sequence Terminator
Figure 5-6. Basic Mode Sequence Terminator Waveforms
Block 2 MAXBLK Block 2Block 1Block 1
Sequence terminator
Sequence terminator
Block 2 MAXBLK Block 2Block 1
Regular-read mode
St = on
No terminator Block 1
Modulation
off (on)
Modulation
off (on)
Data 1Bit period Data 1
Waveforms per different modulation types
FSK
VCoilPP
Manchester
Sequence terminator is not suitable for Bi-phase or PSK modulation
Sequence Last bit
bit 1 or 0
First bit
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5.11.4 Sequence Start Marker (X-mode)
The Atmel® ATA5577C sequence start marker is a special damping pattern in extended mode which may be used to
synchronize the reader. The sequence start marker consists of two bits ("01" or "10") which are inserted as a header before
the first block to be transmitted if, in extended mode, bit 29 is set. At the start of a new block sequence, the value of the two
bits is inverted.
Figure 5-7. Atmel ATA5577C Sequence Start Marker in Extended Mode
5.12 Reader to Tag Communication
Data is transmitted to the tag by interrupting the RF field with short field gaps (on-off keying) in accordance with the Atmel
T5557/ATA5567 write method (downlink mode). The duration of these field gaps is, for example, 100µs. The time between
two gaps encodes the 0/1 information to be transmitted (pulse interval encoding). There are four different downlink protocols
available, which are selectable via bit 21 and bit 22 in the option register block 3, page 1 (see Table 5-1 on page 8).
Choosing the default downlink protocol (fixed-bit-length protocol), the time between two gaps is nominally 24 field clocks for
a 0 and 56 field clocks for a 1. When there is no gap for more than 64 field clocks after a previous gap, the Atmel ATA5577C
exits the downlink mode. The tag starts with the command execution if the correct number of bits were received. If a failure is
detected, the Atmel ATA5577C does not continue and enters regular-read mode.
Improved downlink performance could be achieved by choosing self-calibrating downlink protocols. The Atmel ATA5577C
offers three different possibilities to achieve better performance using self-calibrating downlink protocols.
Long leading reference:
Fully forward and backward compatible with former tags and readers.
Leading zero:
A reader has to send a leading zero in front of the downlink bit stream. This leading zero serves as a reference for the
following zero and one bits.
1-of-4 coding:
Compact downlink protocol with optimized energy balance
5.12.1 Start Gap
The initial gap is referred to as the start gap. This triggers the reader-to-tag communication. In the option register (block 3,
page 1), several settings can be chosen to ease gap detection during this mode of operation; for example, the receive
damping can be activated (see Table 5-1 on page 8). The start gap may need to be longer than subsequent gaps — so-
called write gaps — in order to be detected reliably.
A start gap will be accepted at any time after the mode register has been loaded (3ms). A single gap will not change the
previously selected page (by a previous opcode “10” or “11”).
Block 2 MAXBLK MAXBLKBlock 2Block 110 1001Block 1
Sequence start marker
Block read mode
Regular read mode
10 Block n10 Block n10 Block n 01 Block n 01 01Block n
Nuke: All absolute limes assume TC = 1 [f = Bus (f = 125kHz) AtmeL
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Figure 5-8. Start of Reader-to-tag Communication
5.12.2 Downlink Data Protocols
The Atmel® ATA5577C expects to receive a dual-bit opcode as a part of a reader command sequence. There are three valid
opcodes:
The opcode “10” precedes all downlink operations for page 0.
The opcode “11” precedes all downlink operations for page 1. Performing a direct access command on block 0 always
provides block 0 page 0 independently of the page selector
(see Figure 4-2 on page 6).
The RESET opcode “00” initiates an initialization cycle
The fourth opcode “01” precedes all test mode write operations. Any test mode access is ignored after master key (bits 1 to
4) in block 0 has been set to “6”. Any further modifications of the master key are prohibited by setting the lock bit of block 0
or the OTP bit.
Downlink has to follow these rules:
Standard write needs the opcode, the lock bit, 32 data bits and the 3-bit address (38 bits total)
Protected write (PWD bit set) requires a valid 32-bit password between the opcode and the data and address bits
Protected write (PWD bit set) in conjunction with the leading-zero-reference protocol or with the 1-of-4-coding
protocol requires two padding zero bits between the opcode and the password (see also Figure 5-17 on page 24).
This ensures the uniqueness of the direct access with password and the standard write command (see also Table 6-1
on page 26).
For the AOR wake-up command an opcode and a valid password are necessary to select and activate a specific tag
Note: The data bits are read in the same order as written.
If the transmitted command sequence is invalid, the Atmel ATA5577C enters regular-read mode with the previously selected
page (by previous opcode “10” or “11”).
Table 5-9. Gap Scheme
Parameters Remark Symbol Min. Max. Unit
Start gap Sgap 850 TC
Write gap Normal downlink mode Wgap 820 TC
Note: All absolute times assume TC = 1 / fC = 8µs (fC = 125kHz)
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Figure 5-9. Complete Writing Sequence with Fixed-bit-length Protocol
Figure 5-10. Atmel ATA5577C Command Formats Fixed-bit-length Protocol and Long-leading-reference Protocol
Figure 5-11. Atmel ATA5577C Command Formats Leading-zero-reference Protocol and 1-of-4-coding Protocol
Write mode Read modeRead mode
ProgrammingBlock addressBlock data
Lock bitStart gap
Configuration
loading
POR
Opcode
Password 32 01
OP
Password 321
1p*)0Addr02
**) R = Reference pulse if necessary
*) p = page selector
00
1p*)
1p*)LData
Addr 02
Addr 02321
1p*)
1p*)
Ref
R**)
R**)
R**)
R**)
R**)
R**)
R**)
AOR (wake-up command)
Reset command
Page 0/1 regular read
Standard write
Direct access (PWD = 0)
Direct access (PWD = 1)
Protected write 1 Data AddrLPassword 32 2132 0
1p*)
Password 32 0100
00
OP
Password 321
1p*)0Addr02
**) R = Reference pulse
*) p = page selector
00
1p*)
1p*)L Data
Addr 02
Addr 02321
1p*)
1p*)
Ref
R**)
R**)
R**)
R**)
R**)
R**)
R**)
AOR (wake-up command)
Reset command
Page 0/1 regular read
Standard write
Direct access (PWD = 0)
Direct access (PWD = 1)
Protected write 100 Data AddrLPassword 32 2132 0
1p*)
Note: All absolute times assume TC = 1 [f = Bus (f = 125kHz) AtmeL
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5.12.3 Fixed-bit-length Protocol
In the fixed-bit-length protocol, the time between two gaps is nominally 24 field clocks for a 0 and 56 field clocks for a 1.
When there is no gap for more than 64 field clocks after a previous gap, the Atmel® ATA5577C exits the downlink mode. This
protocol is compatible with the Atmel T5557/ATA5567 transponder.
Figure 5-12. Fixed-bit-length Protocol
5.12.4 Long-leading-reference Protocol
To achieve better downlink performance, an enhanced Atmel ATA5577C reader places a reference pulse in front of the
opcode. This reference pulse is used as a timing reference for all following data, thus providing an auto-adjustment for
varying environmental conditions. The long-leading-reference protocol allows full compatibility and coexistence of both
Atmel T5557/ATA5567 and Atmel ATA5577C devices with both Atmel T5557/ATA5567 compatible readers and advanced
Atmel ATA5577C readers. However, only the Atmel ATA5577C devices can profit from the self calibration and the resultant
increase in write distance (see Table 5-1 on page 8 for option register settings).
In this mode, the reference pulse in front of the command is monitored. Depending on the pulse length, the remainder of the
command is either evaluated using the fixed-bit-length protocol, or is used as a measurement reference to evaluate the
following command bits. Otherwise, the following bits are considered as an invalid command.
a) For a reference-based command, the reference pulse (dRef) will have a length of 16 to 32 + 136 = 152 to 168 field clocks
(zero bit + timing bias = reference pulse). Hence, the expected length will lie between 152 and 168 field clocks. The
equivalent expected zero-bit length is then extracted and used as a reference for all following bits. The long-leading-
reference pulse in this case is used as a timing reference only, and does not contribute to the command data itself (see
Figure 5-13, part a on 21).
b) Should the first bit lie within the fixed-bit-length frame (for example, in normal mode: 0: 16 to 32 clocks; 1: 48 to 64 clocks),
the device will then automatically switch to the fixed-bit-length protocol (see Section 5.12.3 “Fixed-bit-length Protocol” on
page 20) and this first pulse will be evaluated as the first command bit. This allows compatibility with long-leading-reference
programmed Atmel ATA5577C devices interacting with Atmel T5557/ATA5567 readers, which do not send any reference
pulses (see Figure 5-13, part b on 21).
c) If an Atmel T5557/ATA5567 device interacts with an enhanced Atmel ATA5577C reader, the reference pulse (152 to 168
field clocks) is ignored by the Atmel T5557/ATA5567 and the following data bits will evaluated correctly. Therefore, an Atmel
T5557/ATA5567 device is compatible with an enhanced Atmel ATA5577C reader (see Figure 5-13, part b on 21).
d) Should the first bit correspond to neither (a) nor (b) then it will be rejected as an invalid command.
Table 5-10. Downlink Data Coding Scheme with Fixed-bit-length Protocol
Parameter Remark Symbol
Normal Downlink Fast Downlink
UnitMin. Typ. Max. Min. Typ. Max.
Start gap Sgap 815 50 815 50 Tc
Write gap Wgap 810 20 810 20 Tc
Write data
coding (gap
separation)
0 data d016 24 32 812 16 Tc
1 data d148 56 64 24 28 32 Tc
Note: All absolute times assume TC = 1 / fC = 8µs (fC = 125kHz)
10
Nme: All absolme Ixmes assume T = 1 II = 8ps (f = 125kHz) Nme: All absolme Ixmes assume T = 1 II = 8ps (f = 125kHz) AtmeL
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Figure 5-13. Long-leading-reference Protocol
5.12.5 Leading-zero-reference Protocol
If the device is programmed in this mode, it will always expect a reference pulse before the command data itself. This pulse
length should correspond exactly to the length of the zero bits in the following command. All further lengths of the zero and
one bits of the command are derived from the reference pulse. Therefore, downlink performance is optimal in different
environmental conditions.
Figure 5-14. Leading-zero-reference Protocol
Table 5-11. Downlink Data Coding Scheme with Long Leading Reference
Parameter Remark Symbol
Normal Downlink Fast Downlink
UnitMin. Typ. Max. Min. Typ. Max.
Start gap Sgap 815 50 815 50 Tc
Write gap Wgap 810 20 810 20 Tc
Write data
coding (gap
separation)
Reference Pulse dref
152 160 168 140 144 148 Tc
136 clocks + 0 data bit 132 clocks + 0 data bit Tc
0 data d0dref – 143 dref – 136 dref – 128 dref – 135 dref – 132 dref – 124 Tc
1 data d1dref 111 dref – 104 dref – 96 dref – 119 dref – 116 dref – 112 Tc
Note: All absolute times assume TC = 1 / fC = 8µs (fC = 125kHz)
1Reference pulse 0
a)
10
b)
1Reference pulse 0
c)
Table 5-12. Downlink Data Coding Scheme with Leading-zero Reference
Parameter Remark Symbol
Normal Downlink Fast Downlink
UnitMin. Typ. Max. Min. Typ. Max.
Start gap Sgap 815 50 815 50 Tc
Write gap Wgap 810 20 810 20 Tc
Write data
coding (gap
separation)
Reference Pulse dref 12 72 8 68 Tc
0 data d0dref – 7 dref dref + 8 dref – 3 dref dref + 4 Tc
1 data d1dref + 9 dref + 16 dref + 24 dref + 5 dref + 8 dref + 12 Tc
Note: All absolute times assume TC = 1 / fC = 8µs (fC = 125kHz)
10(0)
Reference pulse
Note: All absolme umes assume T = 1 II = aps (f = 125kHz) AtmeL
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5.12.6 1-of-4-coding Protocol
This protocol codes the data in bit pairs so that the length of each packet can have one of four discrete lengths. This protocol
is extremely compact and exhibits the least number of field gaps, which in turn improves the device's ability to extract power
from the field. Additionally, a leading reference pulse “00” is placed in front of the downlink command. This serves as a
reference pulse for all following data bits, thus providing an auto-adjustment for varying environmental conditions.
Figure 5-15. 1-of-4-coding Protocol
Table 5-13. Downlink Data Coding Scheme with 1-of-4 Coding
Parameter Remark Symbol
Normal Downlink Fast Downlink
UnitMin. Typ. Max. Min. Typ. Max.
Start gap Sgap 815 50 815 50 Tc
Write gap Wgap 810 20 810 20 Tc
Write data
coding (gap
separation)
Reference pulse “00” dref 12 72 8 68 Tc
“00” data d00 dref – 7 dref dref + 8 dref – 3 dref dref + 4 Tc
“01” data d01 dref + 9 dref + 16 dref + 24 dref + 5 dref + 8 dref + 12 Tc
“10” data d10 dref + 25 dref + 32 dref + 40 dref + 13 dref + 16 dref + 20 Tc
“11” data d11 dref + 41 dref + 48 dref + 56 dref + 21 dref + 24 dref + 28 Tc
Note: All absolute times assume TC = 1 / fC = 8µs (fC = 125kHz)
Reference pulse
(00) 00
Reference pulse
(00) 10
01 10 11
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ATA5577C [DATASHEET]
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Figure 5-16. Standard Write Sequence Example
1001110100
00 01 1010 00 11
00101101001
1001110100
Opcode Blockdata: "100 ... 1" Blockaddr.: "011" Programming Read modeRead mode
c) Leading-zero-reference Protocol
Opcode
Blockdata:
"100 ... 1"
Blockaddr.:
"011" Programming Read modeRead mode
d) 1-of-4-coding Protocol
Opcode Blockdata: "100 ... 1" Blockaddr.: "011" Programming Read modeRead mode
Opcode
Reference Pulse
Reference Pulse
Start gap Lock bit
Reference Pulse
Blockdata: "100 ... 1" Blockaddr.: "011" Programming Read modeRead mode
Start gap Lock bit
Start gap Lock bit
Start gap Lock bit
a) Fixed-bit-length Protocol
b) Long-leading-reference Protocol
AF M —>H<— dw="" f="" -i="" ir="" 11="" d="" 1w="" f="" 4*="">
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Figure 5-17. Protected Write Sequence Example
5.13 Programming
When all necessary information has been received by the Atmel® ATA5577C, programming may proceed. There is a clock
delay between the end of the writing sequence and the start of programming.
Typical programming time is 5.6ms. This cycle includes a data verification read to grant secure and correct programming.
After programming is successfully executed, the Atmel ATA5577C enters block-read mode, transmitting the block just
programmed (see Figure 5-18 on page 25).
Note: This timing and behavior is different from that of the Atmel e555x-family predecessors. For further details, refer
to relevant Atmel application notes.
If the command sequence is validated and the addressed block is not write protected, the new data will be programmed into
the EEPROM memory. The new state of the block write protection bit (lock bit) will be programmed at the same time
accordingly.
Each programming cycle consists of four consecutive steps: erase block, erase verification (data = 0), programming, and
write verification (corresponding data bits = 1).
11 000101101110
11 00010110
0
00 0001 1001 11111000
100 10010100101
1110
Start gap Lock bit
Start gap Lock bit
Lock bit
Opcode PWD: "1101 ... " Blockdata: "100 ... 1" Blockaddr.: "011" Programming Read modeRead mode
a) Fixed-bit-length Protocol
Padding zerosStart gap
Opcode PWD: "1101 ... " Blockdata: "100 ... 1" Blockaddr.: "011" Programming Read modeRead mode
c) Leading-zero-reference Protocol
Opcode
PWD: "1101 ... "
Blockdata:
"100 ... 1"
Blockaddr.:
"011" Programming Read modeRead mode
d) 1-of-4-coding Protocol
Reference Pulse
Reference Pulse
Lock bitPadding zerosStart gap
Reference Pulse
Opcode PWD: "1101 ... " Blockdata: "100 ... 1" Blockaddr.: "011" Programming Read modeRead mode
b) Long-leading-reference Protocol
11
‘ \ M w w w \ AtmeL
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Figure 5-18. Coil Voltage after Programming a Memory Block
Notes: 1. Programming of page 1 with following single gap will lead to a page 1 read. To enter regular-read mode, a POR
or Reset command has to be performed.
Read programmed
memory block
POR/
Reset
or Read block 1 to MAXBLK5.6 ms
Single
gap
(Regular-read mode)(Block-read mode)Programming and
data verification
Write data to tag
V
Coil 1 - Coil 2
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6. Error Handling
Several error conditions can be detected to ensure that only valid bits are programmed into the EEPROM. There are two
error types, which lead to two different actions.
6.1 Errors During Command Sequence
The following detectable errors could occur while sending a command sequence to the Atmel® ATA5577C:
Wrong number of field clocks between two gaps (that is, not a valid 1 or 0 pulse stream)
Password mode is activated and the password does not match the contents of block 7
The number of bits received in the command sequence is incorrect
Valid bit counts accepted by the Atmel ATA5577C are listed in the following table.
If any of these erroneous conditions (except AOR mode) are detected, the Atmel ATA5577C enters regular-read mode,
starting with block 1 of the page defined in the command sequence. An erroneous AOR wake-up command will stop
modulation (modulation defeat).
Table 6-1. Bit Counts of Command Sequences
Command Protect
Fixed-bit-
length
Protocol
Long-leading-
reference
Protocol
Leading-zero-
reference
Protocol
1-of-4-
coding
Protocol
Standard write (PWD = 0) 38 bits 38 bits 38 bits 38 bits
Direct access (PWD = 0) 6 bits 6 bits 6 bits 6 bits
Password write (PWD = 1) 70 bits 70 bits 72 bits 72 bits
Direct access with PWD (PWD = 1) 38 bits 38 bits 40 bits 40 bits
AOR wake up (PWD = 1) 34 bits 34 bits 36 bits 36 bits
Reset command 2 bits 2 bits 2 bits 2 bits
Page 0/1 regular read 2 bits 2 bits 2 bits 2 bits
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6.2 Errors Before/During Programming the EEPROM
If the command sequence was received successfully, the following error could still prevent programming:
The lock bit of the addressed block is already set
In case of a locked block, programming mode will not be entered. The Atmel® ATA5577C reverts to block-read mode
continuously transmitting the currently addressed block
If a data verification error is detected after an executed data block programming, the tag will stop modulation
(modulation defeat) until a new command is transmitted.
Figure 6-1. Atmel ATA5577C Functional Diagram
addr = current
Block-read mode
addr = 1 to MAXBLK
Program and verify
Write
Password check
Lock bit check
Number of bits
OP(10..)
Command decode
OP(11..)
Start
gap
Write
OP(1p) 1)
OP(1p) 1)
1) p = page selector
Direct access
OP(1p) 1)
Modulation
defeat
Reset
to page 0
Test mode
if master key < > 6
AOR = 1
Page 0
Single gap
OP(01)OP(00)
Page 0Page 1
Page 0 or 1
fail data = old
fail data = old
fail data = old
Gap
Gap Command mode
AOR = 0
Set-up modes
Power-on reset
Regular-read mode
AOR mode
okData verification failed data = new
AAAAA
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Figure 6-2. Example with Manchester Coding with Data Rate RF/16
Data rate =
16 field clocks (FC)
110100
8 FC
891169181816 916
16 16916 819 821821
8 FC
Manchester coded
Inverted modulator
signal
RF field
Data stream
AAAAA
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Figure 6-3. Example of Bi-phase Coding with Data Rate RF/16
9169816169161
81821 82181691 81691
Bi-phase coded
Inverted modulator
signal
RF field
Data stream
Data rate =
16 field clocks (FC)
11100 0
8 FC8 FC
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Figure 6-4. Example: FSK1a Coding with Data Rate RF/40, Sub-carrier f0=RF/8, f
1=RF/5
51515181 8181
Inverted modulator
signal
RF field
f0 = RF/8
f1 = RF/5
Data stream
Data rate =
40 field clocks (FC)
11
0
100
31
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Figure 6-5. Example of PSK1 Coding with Data Rate RF/16
16988211 16 8116 8116 8116 81
Subcarrier RF/2
Inverted modulator
signal
RF field
Data stream
Data rate =
16 field clocks (FC)
100110
8 FC8 FC
,,,,,,, , _ _ _ _ ,Al'll! ,,,,,,, ,,,,,,, _____ ,,,,,,, ,,,,,,, ,,,,,,, ,,,,,,,
ATA5577C [DATASHEET]
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Figure 6-6. Example of PSK2 Coding with Data Rate RF/16
16 8116 8116 8116 8116988211
Subcarrier RF/2
Inverted
modulator signal
RF field
Data stream
Data rate =
16 field clocks (FC)
10 0
011
8 FC8 FC
5223252225;
33
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Figure 6-7. Example of PSK3 Coding with Data Rate RF/16
1681816181681 16811698211
Subcarrier RF/2
Inverted
modulator signal
RF field
Data stream
Data rate =
16 field clocks (FC)
101001
8 FC8 FC
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7. Animal ID
In ISO11784/11785, the code structure of a 128-bit FDX-B telegram is defined. Following is an example of how to program
the Atmel ATA5577C for ISO 11785 FDX-B.
Figure 7-1. Structure of the ISO 11785 FDX-B Telegram
Notes: 1. Except for the header, every eight bits are followed by one control bit (1), to prevent the header from recurring.
2. All data is transmitted LSB first.
3. Country codes are defined in ISO 3166
4. The bits reserved for future use (RFU) are all set to 0.
5. If the data block flag is not set, the trailer bits are all set to 0.
6. CRC is performed on the 64-bit identification code without the control bits. The generator polynomial is
P(x) = x16 + x12 + x5 + 1. Reverse CRC-CCITT (0x 8 408) is used. Data stream is LSB first.
Programming of the Atmel® ATA5577C for animal ID:
Encoding of the data is differential bi-phase RF/32
128 bits have to be transmitted in regular-read mode (Maxblock = 4)
Table 7-1. Example Data for Animal ID
Code Dec. Value Hex. Value Comment
Animal flag 1 1 Use for animal ID
RFU 0 0 Reserved for future use
Data block flag 0 0 No data in trailer
Country code 999 3E7 Country code for demo tags
Unique number 78187493530 123456789A Any demo number
CRC 36255 8D9F CRC for the identification code
11
Header
11-bit fixed
00000000001
24-bit trailer all zeros
+ 3 bits
16-bit CRC
+ 2 bits
TrailerCRCIdentification Code
64-bit Identification Code
+ 8 bits
Bit No.
Bits
128102 ...
10184 ...
1220 ...
Bit No. 83 ...
832012 ... ...
111...
2 x (8+1) 3 x (8+1)8 x (8+1)
Control bit '1'
LSB LSBMSB
LSBMSB
MSB
Control bit '1'
Data Block Flag
Animal Flag
Control bit '1'
Control bit '1'
Control bit '1'
Control bit '1'
Control bit '1'
Control bit '1'
Country Code
2 bits
Control bit '1'
RFU 7 bits Unique
Number
6 bits
Unique
Number 8 bits
Unique
Number 8 bits
Unique
Number 8 bits
Unique
Number 8 bits
Country Code
8 bits
RFU 7 bits
RFU 14 bits Country Code 10 bits Unique Number 38 bits
Make: 1. Depending on application, senings may vary AtmeL
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Table 7-2. Programming the Atmel ATA5577C with Example Data
Block Address Value Comment
Option register Block 3, page 1 0x 6DD0 0000(1) Soft modulation, two pulses recommended
Configuration register Block 0, page 0 0x 603F 8080 RF/32, differential bi-phase, Maxblock = 4
User data block 1 Block 1, page 0 0x 002B 31EB Header, unique number
User data block 2 Block 2, page 0 0x 54B2 979F Unique number (cont.), country code
User data block 3 Block 3, page 0 0x 8040 7F3B Data block flag, RFU, animal flag, CRC
User data block 4 Block 4, page 0 0x 1804 0201 CRC (cont.), trailer bits
Note: 1. Depending on application, settings may vary
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8. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters Symbol Value Unit
Maximum DC current into Coil1/Coil2 Icoil 20 mA
Maximum AC current into Coil1/Coil2, f = 125kHz Icoil p 20 mA
Power dissipation (die) (free-air condition, time of
application: 1s) Ptot 100 mW
Electrostatic discharge maximum to ANSI/ESD-
STM5.1-2001 standard (HBM) Vmax 3000 V
Operating ambient temperature range Tamb –40 to +85 °C
Storage temperature range (data retention
reduced) Tstg –40 to +150 °C
9. Electrical Characteristics
Tamb = +25°C; fcoil = 125kHz; unless otherwise specified
No. Parameters Test Conditions Symbol Min. Typ. Max. Unit Type*
1RF frequency range fRF 100 125 150 kHz
2.1
Supply current (without
current consumed by
the external LC tank
circuit)
Tamb = 25°C(1)
IDD
1.5 3µA T
2.2 Read - full temperature
range 2 5 µA Q
2.3 Programming - full
temperature range 25 µA Q
3.1
Coil voltage (AC
supply)
POR threshold
(50-mV hysteresis)
Vcoil pp
3.6 V Q
3.2 Read mode and write
command(2) 6 Vclamp V Q
3.3 Program EEPROM(2) 8 Vclamp V Q
4Start-up time Vcoil pp = 6V tstartup 2.5 ms Q
5.1
Clamp voltage
(depends on settings in
option register)
3-mA current into
Coil1/Coil2
Vpp clamp lo 11 V Q
5.2 Vpp clamp
med
13 V Q
5.3 Vpp clamp hi 14 17 21 V T
5.4 20-mA current into
Coil1/Coil2
Vpp clamp
med
13 15 18 V T
*) Type means: T: directly or indirectly tested during production; Q: guaranteed based on initial product qualification data
Notes: 1. IDD measurement set-up: EEPROM programmed to 00 ... 000 (erase all); chip in modulation defeat.
2. Current into Coil1/Coil2 is limited to 10mA.
3. Since EEPROM performance is influenced by assembly processes, Atmel cannot confirm the parameters for -DDW
(tested die on unsawn wafer) delivery.
4. See Section 10. “Ordering Information” on page 38.
AtmeL
37
ATA5577C [DATASHEET]
9187H–RFID–07/14
6.1
Modulation parameters
(depends on settings in
option register)
3-mA current into
Coil1/Coil2 and
modulation ON
Vpp mod lo 2 3 4 V T
6.2 Vpp mod med 5 V Q
6.3 Vpp mod hi 7 V Q
6.4
20-mA current into
Coil1/Coil2 and
modulation ON
Vpp mod med 67.5 9 V T
6.5 Thermal stability Vmod lo /
Tamb
–1 mV/°C Q
7.1 Clock detection level
(depends on settings in
option register)
Vcoil pp = 8V
Vclkdet lo 250 mV Q
7.2 Vclkdet med 400 550 730 mV T
7.3 Vclkdet hi 800 mV Q
7.4 Gap detection level
(depends on settings in
option register)
Vcoil pp = 8 V
Vgapdet lo 250 mV Q
7.5 Vgapdet med 400 550 730 mV T
7.6 Vgapdet hi 850 mV Q
8Programming time
From last command
gap to re-enter read
mode (64 + 648
internal clocks)
Tprog 55.7 6ms T
9Endurance Erase all/Write all(3) ncycle 100000 Cycles Q
10.1
Data retention
Top = 55°C(3) tretention 10 20 50 Years Q
10.2 Top = 150°C(3) tretention 96 hrs T
10.3 Top = 250°C(3) tretention 24 hrs Q
11.1
Resonance capacitor Mask option(4) Cr
320 330 340
pF
T
11.2 242 250 258
11.3 130
11.4 75
11.5 10 Q
12.1 Micromodule capacitor
parameters(4)
Capacitance tolerance
Tamb
Cr320 330 340 pF T
9. Electrical Characteristics (Continued)
Tamb = +25°C; fcoil = 125kHz; unless otherwise specified
No. Parameters Test Conditions Symbol Min. Typ. Max. Unit Type*
*) Type means: T: directly or indirectly tested during production; Q: guaranteed based on initial product qualification data
Notes: 1. IDD measurement set-up: EEPROM programmed to 00 ... 000 (erase all); chip in modulation defeat.
2. Current into Coil1/Coil2 is limited to 10mA.
3. Since EEPROM performance is influenced by assembly processes, Atmel cannot confirm the parameters for -DDW
(tested die on unsawn wafer) delivery.
4. See Section 10. “Ordering Information” on page 38.
AtmeL
ATA5577C [DATASHEET]
9187H–RFID–07/14
38
10. Ordering Information
ATA5577M 1 ccc C -xxx Package Drawing
DDB 6” sawn wafer on foil with ring, thickness 150µm
(approx. 6mil) Figure 11-1 on page 40
DDW 6” wafer, thickness 680µm (approx. 27mil)
On-chip Capacity Value in pF
000 pF On request
075 pF On request
250 pF On request
330 pF
Standard pads
1 330 C -PAE NOA3 micromodule (lead-free) Figure 11-4 on page 43/
Figure 11-5 on page 44
1 330 C -UFQW XDFN package 1.5mm by 2mm, thickness 0.37mm Figure 11-6 on page 45
1 330 C -PPMY Transponder Brick package See datasheet
ATA5577M1330C-PPMY
1 33S C -DDB As ATA5577M1330C-DDB, pre-programmed in unique format Figure 11-1 on page 40
ATA5577M 2 ccc C -xxx Package Drawing
DBB 6” sawn wafer on foil with ring, thickness 150µm
(approx. 6mil) with gold bumps 25µm Figure 11-2 on page 41
DBQ Die in blister tape, thickness 280µm (approx. 11mil),
plus gold bumps 25µm Figure 11-3 on page 42
On-chip Capacity Value in pF
250 pF On request
330 pF
Mega pads 200µm by 400µm
2
2
33S
33S
C
C
-DBB
-DBQ
As ATA5577M2330C-DBB, pre-programmed in unique format
As ATA5577M2330C-DBQ, pre-programmed in unique format
Figure 11-2 on page 41
Figure 11-3 on page 42
2 33A C -DBB 6” sawn wafer on foil with ring, thickness 280µm (approx. 11mil)
with gold bumps 25µm
AtmeL
39
ATA5577C [DATASHEET]
9187H–RFID–07/14
10.1 Available Order Codes
ATA5577M1330C-DDB
ATA5577M1330C-DDW
ATA5577M1330C-PAE
ATA5577M1330C-UFQW
ATA5577M1330C-PPMY
ATA5577M133SC-DDB
ATA5577M2330C-DBB
ATA5577M2330C-DBQ
ATA5577M233AC-DBB
ATA5577M233SC-DBB
New order codes will be created by customer request if order quantities are over 250k pieces.
10.2 Configuration on Delivery
Table 10-1. Configuration on Delivery
Block Address Value Comment
AFE option set up Block 3, page 1 0x 0000 0000 All option take on the default state
Configregister Block 0, page 0 0x 0008 8040 RF/32, Manchester, Maxblock = 2
User data block 1 Block 1, page 0 0x 0000 0000 All “0”
User data block 2 Block 2, page 0 0x 0000 0000 All “0”
Atmet AtmeL
ATA5577C [DATASHEET]
9187H–RFID–07/14
40
11. Package Information
Figure 11-1. Sawn Wafer on Foil with Ring (Type 1, Standard Pads)
Package Drawing Contact:
packagedrawings@atmel.com
GPC DRAWING NO.
REV. TITLE
9.920-6676.03-4 1
07/19/10
Dimensions
ATA5577M1xxxC-DDB
Dimensions in mm
specifications
according to DIN
technical drawings
20:1
Die Dimensions
Orientation on frame 59.5 63.6
4B
B
212
87.5
86.5
Wafer ATA5577M1xxxC-DDB
6" Wafer frame, plastic
thickness 2.5mm
UV Tape Adwill D176
Label:
Qty:
Wafer no:
Lot no:
Prod: ATA5577M1xxxC-DDB
0.347
(0.08)
0.117
0.125
1.15
0.1
0.181
0.095
C1 C2
0.07
(0.08) 0.1
1
0.15±0.012
A
A
Ø3
Ø227.7
212
Ø150
Ø194.5
330
33D
Option
xxx
fll @ Atmet AtmeL
41
ATA5577C [DATASHEET]
9187H–RFID–07/14
Figure 11-2. Sawn Wafer on Foil with Ring (Type 2, Mega Pads and Au Bumps)
Package Drawing Contact:
packagedrawings@atmel.com
GPC DRAWING NO.
REV. TITLE
9.920-6679.02-4 1
07/19/10
Dimensions
ATA5577M2xxxC-DBB
Dimensions in mm
specifications
according to DIN
technical drawings
20:1
Die Dimensions
Orientation on frame
4B
B
Wafer ATA5577M2xxxC-DBB
6" Wafer frame, plastic
thickness 2.5mm
UV Tape Adwill D176
Label:
Qty:
Wafer no:
Lot no:
Prod: ATA5577M2xxxC-DBB
(Au bump)
(BCB coating)
0.2
0.324
59.5 63.6
0.04
×
45°
(0.08)
1±0.015 0.155±0.014
0.005±0.002
0.025±0.005
0.15±0.012
0.175±0.017
0.177±0.015
0.4±0.015
1.355±0.015
(0.08)
212
87.5
86.5
A
A
Ø3
212
Ø227.7
Ø150
Ø194.5
330
Option
xxx
0.005 "d 0.04 x 45° 0.2 \ 0.30520 am Atmet AtmeL
ATA5577C [DATASHEET]
9187H–RFID–07/14
42
Figure 11-3. Die in Blister Tape
Package Drawing Contact:
packagedrawings@atmel.com
GPC DRAWING NO.
REV. TITLE
9.800-5110.01-4 2
02/28/12
Dimensions
ATA5577M2xxxC-DBQ
specifications
according to DIN
technical drawings
0.177±0.015
0.4±0.015
1.355±0.015
(BCB coating)
0.285±0.0135
0.005±0.0015
(Au bump)
0.025±0.005
0.305±0.0017
0.28±0.012
8.4
reel Ø330
20:1
Die Dimensions
0.5
0.254
1.3
1.52 8
C2 C1
(0.08)
1
0.324
0.2
4
0.04 x 45°
’’X’’
’’X’’
Label acc. ’’Packaging and Packing Spec.’’
cover tape
carrier tape
Specification Tape and reel
Dimensions in mm
Packing acc. IEC 60286-3
330
Option
xxx
Atmet AtmeL
43
ATA5577C [DATASHEET]
9187H–RFID–07/14
Figure 11-4. NOA3 Micromodule
Package Drawing Contact:
packagedrawings@atmel.com
GPC DRAWING NO.
REV. TITLE
6.549-5035.01-4 1
Package: Micro Module
Subcontractor: Ned Card
Note 2
Note 4
8-0.02
8.1±0.03
5.1±0.05
1.42±0.05
specifications
according to DIN
technical drawings
Dimensions in mm
Note:
1. Reject hole by testing device
2. Punching cutline
recommendation for singulation
3. Total package thickness
exclusive punching burr
4. Module dimension
after electrical disconnection
Issue: 1; 28.04.06
Subcontractor: NedCard
Drawing refers to following types: Micromodule NOA-3
Drawing-No.: 6.549-5035.01-4
9.5±0.03
4.8±0.05
5.15±0.03
1.42±0.05
4.75+0.02
0.05 B
0.03
4.625
1.585
0
2.515
6.265
12.165
15.915
31.83
21.815
Note 1
Note 2
5.06±0.03
R1.5±0.03
R1.1±0.03 (4x)
R0.2 max.
Note 4
0.09-0.01
0.38-0.035
Note 3
A
X
X5:1
2.375
2.375
B
25.565
BA
0.03 B
0.05 A
Ф2±0.05
04/28/06
Q
ATA5577C [DATASHEET]
9187H–RFID–07/14
44
Figure 11-5. Shipping Reel for NOA3 Micromodule
Ø 329.6
120
°
(3x)
16.7
Ø171
Ø175
R1.14
Ø13
2.3
41.4 to
max 43.0
Ø 298.5
2.2
2
Atmet AtmeL
45
ATA5577C [DATASHEET]
9187H–RFID–07/14
Figure 11-6. XDFN Package
Package Drawing Contact:
packagedrawings@atmel.com
GPC DRAWING NO.
REV. TITLE
6.543-5159.01-4 1
04/06/11
Package: XDFN_1.5x2_2L
Dimensions in mm
specifications
according to DIN
technical drawings
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN NOM MAXSymbol
0.1 nom.A1
1.5 1.551.45E
1 BSCe
1.1 1.21E1
0.7 0.80.6D2
0.7 0.80.6D1
22.051.95D
0.37 0.40.32A
D
e
D1
D2
PIN 1 ID
A
A1
E
E1
AtmeL
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46
12. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this
document.
Revision No. History
9187H-RFID-07/14
Section 10 “Ordering Information” on pages 38 to 39 updated
Section 11 “Package Information” on pages 40 to 45 updated
9187G-RFID-04/13 Section 10 “Ordering Information” on pages 37 to 38 updated
9187F-RFID-01/13
Section 5.5 “Initialization and Init-Delay” on page 11 updated
Figure 5-1 “Answer-on-request (AOR) Mode ...” on page 12 updated
Figure 5-9 “Complete Writing Sequence ...” on page 19 updated
Ordering Information for ATA5577M1cccC-DDW on pages 37 and 38 added
9187E-RFID-07/12 Section 10 “Ordering Information” on pages 37 to 38: Ordering codes added
9187D-RFID-04/12
Figure 11-4 “Die in Blister Tape” on page 42 added
Figure 11-5 “Die on Sticky Tape” on page 43 updated
9187C-RFID-04/11
Figure 11-1 “Pad Layout (Type 1, Standard Pads)” on page 41 removed
Figure 11-2 “Pad Layout (Type 2, Mega Pads)” on page 42 removed
9187BX-RFID-03/11
Section 10 “Ordering Information” on page 39 changed
Section 10.1 “Available Order Codes” on page 40 changed
Figure 11-4 “Die in Waffle Pack” on page 44 added
Atmet ‘ Enabling Unlimited Possibilities” ”um E
X
XXX
XX
Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com
© 2014 Atmel Corporation. / Rev.: 9187H–RFID–07/14
Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, AVR®, AVR Studio®, and others are registered trademarks or trademarks of Atmel
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is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE
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