T6818, T6828 Datasheet by Microchip Technology

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A IIIEI. 41m —z
Rev. 4530E–BCD–07/04
Features
Supply Voltage up to 40 V
RDSon Typically 0.5 at 25°C, Maximum 1.1 at 150°C
Up to 1.5 A Output Current
Three Half-bridge Outputs Formed by Three High-side and Three Low-side Drivers
Capable to Switch all Kinds of Loads Such as DC Motors, Bulbs, Resistors, Capacitors
and Inductors
No Shoot-through Current
Very Low Quiescent Current IS < 5 µA in Standby Mode versus Total Temperature
Range
Outputs Short-circuit Protected
Overtemperature Protection for Each Switch and Overtemperature Prewarning
Undervoltage Protection
Various Diagnostic Functions Such as Shorted Output, Open-load, Overtemperature
and Power-supply Fail Detection
Serial Data Interface, Daisy Chain Capable, up to 2 MHz Clock Frequency
SO14 Power Package
Description
The T6818/T6828 are fully protected driver interfaces designed in 0.8-µm BCDMOS
technology. They are used to control up to 3 different loads by a microcontroller in
automotive and industrial applications.
Each of the 3 high-side and 3 low-side drivers is capable to drive currents up to 1.5 A.
The drivers are internally connected to form 3 half-bridges and can be controlled sep-
arately from a standard serial data interface. Therefore, all kinds of loads such as
bulbs, resistors, capacitors and inductors can be combined. The IC design especially
supports the application of H-bridges to drive DC motors.
Protection is guaranteed regarding short-circuit conditions, overtemperature and und-
ervoltage. Various diagnostic functions and a very low quiescent current in
stand-by-mode opens a wide range of applications. Automotive qualification (protec-
tion against conducted interferences, EMC protection and 2-kV ESD protection) gives
added value and enhanced quality for exacting requirements of automotive
applications.
Triple Half-
bridge DMOS
Output Driver
with Serial Input
Control
T6818/T6828
DDDDDDDDDDDDDDD DDDDDDDDDDDDDDDD proleclion Power-on rese‘ Thermal prolechon
2 T6818/T6828
4530EBCD07/04
Figure 1. Block Diagram
DI
CLK
INH
DO
CS
UV
protection
Serial interface
Input register
Output register
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
S
R
R
O
C
Sn.n. n. n.n.n.
P
S
F
O
P
L
S
C
D
n.
u. H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
T
P
OUT3
VS
VCC
Thermal
protection
Control
logic Power-on
reset
Charge
pump
OUT2 OUT1
n.n.
u.
GND
n.
u.
n.
u.
n.
u.
n.
u.
n.
u.
u. u. u. u. u. u. u. 3
11
1
7
8
14
21213
5
6
4
10
9
GND
GND
GND
Fault
detect
Fault
detect
Fault
detect
Fault
detect Fault
detect Fault
detect
EEEEEEE 41m
3
T6818/T6828
4530E–BCD–07/04
Pin Configuration
Figure 2. Pining SO14
GND
OUT3
VS
CS
DI
CLK
GND
GND
OUT1
OUT2
VCC
INH
DO
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Pin Description
Pin Symbol Function
1GND
T6818: ground; reference potential; internal connection to pin 7, 8 and 14; cooling tab
T6828: additional connection to heat slug
2OUT3
Half-bridge output 3; formed by internally connected power MOS high-side switch 3 and low-side switch 3
with internal reverse diodes; short circuit protection; overtemperature protection; diagnosis for short and
open load
3VS Power supply for output stages OUT1, OUT2 and OUT3, internal supply
4CS Chip select input; 5-V CMOS logic level input with internal pull up;
low = serial communication is enabled, high = disabled
5DI Serial data input; 5-V CMOS logic level input with internal pull down; receives serial data from the control
device; DI expects a 16-bit control word with LSB being transferred first
6CLK Serial clock input; 5-V CMOS logic level input with internal pull down;
controls serial data input interface and internal shift register (fmax = 2 MHz)
7GND Ground; see pin 1
8GND Ground; see pin 1
9DO
Serial data output; 5-V CMOS logic level tri-state output for output (status) register data; sends 16-bit
status information to the microcontroller (LSB is transferred first); output will remain tri-stated unless
device is selected by CS = low, therefore, several ICs can operate on one data output line only.
10 INH Inhibit input; 5-V logic input with internal pull down; low = standby,
high = normal operation
11 VCC Logic supply voltage (5 V)
12 OUT2 Half-bridge output 2; see pin 2
13 OUT1 Half-bridge output 1; see pin 2
14 GND Ground; see pin 1
j T \ I 1 1 l I I 1 .V. l I 1 'A l .1' K I I T gfi‘fumufi’Jj_FuflgflgflujJfiL/jquflumUT; % It I K I l l‘ l‘ l 1 l 1 J1 l K I %
4 T6818/T6828
4530E–BCD–07/04
Functional Description
Serial Interface Data transfer starts with the falling edge of the CS signal. Data must appear at DI syn-
chronized to CLK and are accepted on the falling edge of the CLK signal. LSB (bit 0,
SRR) has to be transferred first. Execution of new input data is enabled on the rising
edge of the CS signal. When CS is high, pin DO is in tri-state condition. This output is
enabled on the falling edge of CS. Output data will change their state with the rising
edge of CLK and stay stable until the next rising edge of CLK appears. LSB (bit 0, TP) is
transferred first.
Figure 3. Data Transfer
SRR LS1 HS1 LS2 HS2 LS3 HS3 n. u. n. u. n. u. n. u. n. u. n. u. OCS n. u. n. u.
CS
DI
CLK
DO TP S1L S1H S2L S2H S3L S3H n. u. n. u. n. u. n. u. n. u. n. u. SCD OPL PSF
0123456789101112131415
Table 1. Input Data Protocol
Bit Input Register Function
0SRR
Status register reset (high = reset; the bits PSF, OPL and SCD in
the output data register are set to low)
1LS1 Controls output LS1 (high = switch output LS1 on)
2HS1 Controls output HS1 (high = switch output HS1 on)
3LS2 See LS1
4HS2 See HS1
5LS3 See LS1
6HS3 See HS1
7n. u. Not used
8n. u. Not used
9n. u. Not used
10 n. u. Not used
11 n. u. Not used
12 n. u. Not used
13 OCS Overcurrent shutdown (high = overcurrent shutdown is active)
14 n. u. Not used
15 n. u. Not used
41m
5
T6818/T6828
4530E–BCD–07/04
Table 2. Output Data Protocol
Bit
Output (Status)
Register Function
0 TP Temperature prewarning: high = warning
1Status LS1 High = output is on, low = output is off; not affected by SRR
2Status HS1 High = output is on, low = output is off; not affected by SRR
3Status LS2 Description see LS1
4Status HS2 Description see HS1
5Status LS3 Description see LS1
6Status HS3 Description see HS1
7n. u. Not used
8n. u. Not used
9n. u. Not used
10 n. u. Not used
11 n. u. Not used
12 n. u. Not used
13 SCD
Short circuit detected: set high when at least one high-side or
low-side switch is switched off by a short-circuit condition. Bits 1 to
6 can be used to detect the shorted switch.
14 OPL
Open load detected: set high, when at least one active high-side or
low-side switch sinks/sources a current below the open load
threshold current.
15 PSF Power-supply fail: undervoltage at pin VS detected
After power-on reset, the input register has the following status:
Bit 15 Bit 14 Bit 13
(OCS)
Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6
(HS3)
Bit 5
(LS3)
Bit 4
(HS2)
Bit 3
(LS2)
Bit 2
(HS1)
Bit 1
(LS1)
Bit 0
(SRR)
xxHxxxxxxLLLLLLL
The following patterns are used to enable internal test modes of the IC. It is not recommended to use these patterns during
normal operation.
Bit 15 Bit 14 Bit 13
(OCS)
Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6
(HS3)
Bit 5
(LS3)
Bit 4
(HS2)
Bit 3
(LS2)
Bit 2
(HS1)
Bit 1
(LS1)
Bit 0
(SRR)
HHHHHLLLLLLLLLLL
HHHLLHHLLLLLLLLL
HHH LLLLHHLLLLLLL
41m
6 T6818/T6828
4530E–BCD–07/04
Power-supply Fail In case of undervoltage at pin VS, the Power-Supply Fail bit (PSF) in the output register
is set and all outputs are disabled. To detect an undervoltage, its duration has to last
longer than the undervoltage detection delay time tdUV. The outputs are enabled immedi-
ately when supply voltage recovers normal operation value. The PSF bit stays high until
it is reset by the SRR bit in the input register.
Open-load Detection If the current through a high-side or low-side switch in ON-state stays below the open-
load detection threshold, the open-load detection bit (OPL) in the output register is set.
The OPL bit stays high until it is reset by the SRR bit in the input register. To detect an
open load, its duration has to last longer than the open-load detection delay time tdSd.
Overtemperature
Protection
If the junction temperature of one or more output stages exceeds the thermal prewarn-
ing threshold, TjPW set, the temperature prewarning bit (TP) in the output register is set.
When the temperature falls below the thermal prewarning threshold, TjPW reset, the bit TP
is reset. The TP bit can be read without transferring a complete 16-bit data word. The
status of TP is available at pin DO with the falling edge of CS. After the microcontroller
has read this information, CS is set high and the data transfer is interrupted without
affecting the status of input and output registers.
If the junction temperature of one or more output stages exceeds the thermal shutdown
threshold, Tj switch off, all outputs are disabled and the corresponding bits in the output
register are set to low. The outputs can be enabled again when the temperature falls
below the thermal shutdown threshold, Tjswitch on and the SRR bit in the input register is
set to high. Hysteresis of thermal prewarning and shutdown threshold avoids
oscillations.
Short-circuit Protection The output currents are limited by a current regulator. Overcurrent detection is activated
by writing a high to the OCS bit in the input register. When the current in an output stage
exceeds the overcurrent limitation and shutdown threshold, it is switched off after a
delay time (tdSd). The short-circuit detection bit (SCD) is set and the corresponding sta-
tus bit in the output register is set to low. For OCS = low the overcurrent shutdown is
inactive. The SCD bit is also set if the current exceeds the overcurrent limitation and
shutdown threshold, but the outputs are not affected. By writing a high to the SRR bit in
the input register the SCD bit is reset and the disabled outputs are enabled.
Inhibit 0 V applied to pin 10 (INH) inhibits the T6818/T6828.
All output switches are then turned off and switched to tri-state. The data in the output
register are deleted. The current consumption is reduced to less than 5 µA at pin VS and
less than 25 µA at pin VCC. The output switches can be activated again by switching pin
10 (INH) to 5 V which initiates an internal power-on reset.
41m
7
T6818/T6828
4530E–BCD–07/04
Note: 1. Threshold for undervoltage detection
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
All values refer to GND pins.
Parameters Pin Symbol Value Unit
Supply voltage 3 VVS -0.3 to +40 V
Supply voltage
t < 0.5 s; IS > -2 A 3 VVS -1 V
Logic supply voltage 11 VVCC -0.3 to +7 V
Logic input voltage 4 to 6, 10 VCS,VDI, VCLK, VINH -0.3 to VVCC+0.3 V
Logic output voltage 9 VDO -0.3 to VVCC+0.3 V
Input current 4 to 6, 10 ICS,IDI, ICLK, IINH -10 to +10 mA
Output current 9 IDO -10 to +10 mA
Output current 2, 12 and 13 IOut3, IOut2, IOut1 Internally limited, see output specification
Output voltage 2, 12 and 13 IOut3, IOut2, IOut1 -0.3 to +40 V
Reverse conducting current
(tpulse = 150 µs)
2, 12 and 13
towards pin 3 IOut3, IOut2, IOut1 17 A
Junction temperature range TJ-40 to +150 °C
Storage temperature range TSTG -55 to +150 °C
Thermal Resistance
Parameters Test Conditions Symbol Value Unit
T6818
Junction pin Measured to GND
Pins 1, 7, 8 and 14 RthJP 30 K/W
Junction ambient RthJA 65 K/W
T6828
Junction pin Measured to heat slug
GND pins 1, 7, 8 and 14 RthJP 5K/W
Junction ambient RthJA 30 K/W
Operating Range
Parameters Symbol Value Unit
Supply voltage VVS VUV(1) to 40 V
Logic supply voltage VVCC 4.75 to 5.25 V
Logic input voltage
V
CS
,V
DI
, V
CLK
,
V
INH
-0.3 to VVCC V
Serial interface clock frequency fCLK 2MHz
Junction temperature range Tj-40 to +150 °C
41m
8 T6818/T6828
4530E–BCD–07/04
Note: 1. Test pulse 5: Vsmax = 40 V
Noise and Surge Immunity
Parameters Test Conditions Value
Conducted interferences ISO 7637-1 Level 4(1)
Interference suppression VDE 0879 Part 2 Level 5
ESD (Human Body Model) ESD S 5.1 2 kV
ESD (Machine Model) JEDEC A115A 200 V
Electrical Characteristics
7.5 V < VVS < 40 V; 4.75 V < VVCC < 5.25 V; INH = High; -40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins.
No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
1 Current Consumption
1.1 Quiescent current VS VVS < 20 V, INH = low 3 IVS 1 5 µA A
1.2 Quiescent current VCC 4.75 V < VVCC < 5.25 V,
INH = low 11 IVCC 15 25 µA A
1.3 Supply current VS VVS < 20 V normal
operating, all outputs off 3 IVS 4 6 mA A
1.4 Supply current VCC 4.75 V < VVCC < 5.25 V,
normal operating 11 IVCC 350 500 µA A
1.5 Discharge current VS VVS = 32.5 V,
INH = low 3 IVS 0.5 5.5 mA A
1.6 Discharge current VS VVS = 40 V,
INH = low 3 IVS 2.5 10 mA A
2 Undervoltage Detection, Power-on Reset
2.1 Power-on reset
threshold 11 VVCC 3.2 3.9 4.4 V A
2.2 Power-on reset
delay time After switching on VCC tdPor 30 95 190 µs A
2.3 Undervoltage-detection
threshold VCC = 5 V 3 VUv 5.6 7.0 V A
2.4 Undervoltage-detection
hysteresis VCC = 5 V 3 VUv 0.6 V A
2.5 Undervoltage-detection
delay time tdUV 10 40 µs A
3 Thermal Prewarning and Shutdown
3.1 Thermal prewarning set TjPW set 120 145 170 °C B
3.2 Thermal prewarning
reset TjPW reset 105 130 155 °C B
3.3 Thermal prewarning
hysteresis TjPW 15 °C B
3.4 Thermal shutdown off Tj switch off 150 175 200 °C B
3.5 Thermal shutdown on Tj switch on 135 160 185 °C B
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note: 1. Delay time between rising edge of input signal at pin CS after data transmission and switch on output stages to 90% of final
level. Device not in standby for t > 1 ms
41m
9
T6818/T6828
4530E–BCD–07/04
3.6 Thermal shutdown
hysteresis Tj switch off 15 °CB
3.7
Ratio thermal shutdown
off/thermal prewarning
set
Tj switch off/
TjPW set
1.05 1.2 B
3.8
Ratio thermal shutdown
on/thermal prewarning
reset
Tj switch on/
TjPW reset
1.05 1.2 B
4 Output Specification (OUT1-OUT3)
4.1
On resistance
IOut 1-3 = -1.3 A 2, 12,
13 RDSOn1-3 1.1 A
4.2 IOut 1-3 = 1.3 A 2, 12,
13 RDSOn1-3 1.1 A
4.3 High-side output
leakage current
VOut 1-3 = 0 V,
output stages off
2, 12,
13 IOut1-3 -15 µA A
4.4 Low-side output
leakage current
VOut 1-3 = VVS,
output stages off
2, 12,
13 IOut1-3 200 µA A
4.5
High-side switch
reverse diode forward
voltage
IOut 1-3 = 1.5 A 2, 12,
13 VOut1-3 - VVS 1.5 V A
4.6 Low-side switch reverse
diode forward voltage IOut 1-3 = -1.5 A 2, 12,
13 VOut 1-3 -1.5 V A
4.7
High-side overcurrent
limitation and shutdown
threshold
2, 12,
13 IOut1-3 -2.5 -2 -1.5 A A
4.8
Low-side overcurrent
limitation and shutdown
threshold
2, 12,
13 IOut1-3 1.5 22.5 A A
4.9 Overcurrent shutdown
delay time tdSd 10 40 µs A
4.10 High-side open-load
detection threshold
2, 12,
13 IOut1-3 -45 -30 -15 mA A
4.11 Low-side open-load
detection threshold
2, 12,
13 IOut1-3 15 30 45 mA A
4.12 Open-load detection
delay time tdSd 200 600 µs A
4.13 High-side output switch
on delay(1)
VVS = 13 V
RLoad = 30 tdon 20 µs A
4.14 Low-side output switch
on delay(1)
VVS = 13 V
RLoad = 30 tdon 20 µs A
4.15 High-side output switch
off delay(1)
VVS = 13 V
RLoad = 30 tdoff 20 µs A
Electrical Characteristics (Continued)
7.5 V < VVS < 40 V; 4.75 V < VVCC < 5.25 V; INH = High; -40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins.
No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note: 1. Delay time between rising edge of input signal at pin CS after data transmission and switch on output stages to 90% of final
level. Device not in standby for t > 1 ms
41m
10 T6818/T6828
4530E–BCD–07/04
4.16 Low-side output switch
off delay(1)
VVS = 13 V
RLoad = 30 tdoff sA
4.17
Dead time between
corresponding high-
and low-side switches
VVS = 13 V
RLoad = 30 tdon - tdoff 1µs A
5 Logic Inputs DI, CLK, CS, INH
5.1 Input voltage low-level
threshold 4-6, 10 VIL
0.3 ×
VVCC
V A
5.2 Input voltage high-level
threshold 4-6, 10 VIH
0.7 ×
VVCC
V A
5.3 Hysteresis of input
voltage 4-6, 10 VI50 700 mV B
5.4 Pull-down current pin
DI, CLK, INH VDI, VCLK, VINH = VCC 5, 6, 10 IPD 10 65 µA A
5.5 Pull-up current
Pin CS VCS = 0 V 4 IPU -65 -10 µA A
6 Serial Interface – Logic Output DO
6.1 Output-voltage low level IDOL = 2 mA 9 VDOL 0.4 V A
6.2 Output-voltage high
level IDOL = -2 mA 9 VDOH
VVCC -
0.7 V V A
6.3 Leakage current
(tri-state)
VCS = VCC
0V < VDO < VVCC
9 IDO -10 10 µA A
7Inhibit Input - Timing
7.1
Delay time from
standby to normal
operation
tdINH 100 µs A
Electrical Characteristics (Continued)
7.5 V < VVS < 40 V; 4.75 V < VVCC < 5.25 V; INH = High; -40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins.
No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note: 1. Delay time between rising edge of input signal at pin CS after data transmission and switch on output stages to 90% of final
level. Device not in standby for t > 1 ms
41m
11
T6818/T6828
4530E–BCD–07/04
Serial Interface – Timing
No. Parameters Test Conditions Pin Timing Chart No.(1) Symbol Min. Typ. Max. Unit Type*
8.1 DO enable after CS
falling edge CDO = 100 pF 9 1 tENDO 200 ns D
8.2 DO disable after CS
rising edge CDO = 100 pF 9 2 tDISDO 200 ns D
8.3 DO fall time CDO = 100 pF 9 - tDOf 100 ns D
8.4 DO rise time CDO = 100 pF 9 - tDOr 100 ns D
8.5 DO valid time CDO = 100 pF 9 10 tDOVal 200 ns D
8.6 CS setup time 4 4 tCSSethl 225 ns D
8.7 CS setup time 4 8 tCSSetlh 225 ns D
8.8 CS high time 4 9 tCSh 500 ns D
8.9 CLK high time 6 5 tCLKh 225 ns D
8.10 CLK low time 6 6 tCLKl 225 ns D
8.11 CLK period time 6 - tCLKp 500 ns D
8.12 CLK setup time 6 7 tCLKSethl 225 ns D
8.13 CLK setup time 6 3 tCLKSetlh 225 ns D
8.14 DI setup time 5 11 tDIset 40 ns D
8.15 DI hold time 5 12 tDIHold 40 ns D
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note: 1. See Figure 4 on page 12
12 CS CLK DI CLK DO
12 T6818/T6828
4530E–BCD–07/04
Figure 4. Serial Interface Timing with Chart Numbers
CS
DO
1 2
CS
CLK
4
5
6
7
9
83
DI
CLK
DO
10 12
11
Inputs DI, CLK, CS: High level = 0.7 × V
CC
, low level = 0.3 × V
CC
Output DO: High level = 0.8 × V
CC
, low level = 0.2 × V
CC
DDDDDDDDDDDDDDD DDDDDDDDDDDDDDDD Application Notes It is strongly recommended to con possible to the power supply and Recommended value lor capacito Electrolytic capacitor C > 22 pF l for electrolytic capacitor depen reverse conducting current l0““ 2‘ Recommended value lor capacito Electrolytic capacitor C > 10 pF in To reduce thermal resistance it is close as possible to the GND pins Negative spikes at the output pin switched off with a high side driv hon ol the T6818/T6828. In this co If this behavior is not acceptable necessary, that for switching on Reset) is set, to ensure a reset of film—El. 4530EeBCD~07/OA — i
13
T6818/T6828
4530EBCD07/04
Application Circuit
Application Notes It is strongly recommended to connect the blocking capacitors at VCC and VS as close as
possible to the power supply and GND pins.
Recommended value for capacitors at VS:
Electrolytic capacitor C > 22 µF in parallel with a ceramic capacitor C = 100 nF. Value
for electrolytic capacitor depends on external loads, conducted interferences and
reverse conducting current IOut1,2,3 (see “Absolute Maximum Ratings” on page 7).
Recommended value for capacitors at VCC:
Electrolytic capacitor C > 10 µF in parallel with a ceramic capacitor C = 100 nF.
To reduce thermal resistance it is recommended to place cooling areas on the PCB as
close as possible to the GND pins.
Negative spikes at the output pins (e.g. negative spikes caused by an inductive load
switched off with a high side driver) may activate the overtemperature protection func-
tion of the T6818/T6828. In this condition, all outputs will be switched off simultaneously.
If this behavior is not acceptable or compatible with your application functionally, it is
necessary, that for switching on required outputs again, the SRR bit (Status Register
Reset) is set, to ensure a reset of the overtemperature function.
DI
CLK
INH
DO
CS
UV
protection
Serial interface
Input register
Output register
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
S
R
R
O
C
Sn.n. n. n.n.n.
P
S
F
O
P
L
S
C
D
n.
u. H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
T
P
OUT3
VS
VCC
Thermal
protection
Control
logic Power-on
reset
Charge
pump
OUT2 OUT1
n.n.
u.
GND
n.
u.
n.
u.
n.
u.
n.
u.
n.
u.
u. u. u. u. u. u. u.
3
11
1
7
8
14
21213
5
6
4
10
9
GND
GND
GND
Fault
detect
Fault
detect
Fault
detect
Fault
detect
Fault
detect
Fault
detect
5 V
++
13 V
BYT41D
VS
+
VBatt
Microcontroller
U5021M
Watchdog
VCC
Reset
Trigger
Enable
MM
VCC
VCC
VCC
14 T6818/T6828
4530E–BCD–07/04
Package Information
Ordering Information
Extended Type Number Package Remarks
T6818-TUS SO14 Power package, tubed
T6818-TUQ SO14 Power package, taped and reeled
T6828-T2S SO14 Power package with heat slug, tubed
T6828-T2Q SO14 Power package with heat slug, taped and reeled
technical drawings
according to DIN
specifications
Package SO14
Dimensions in mm
0.25
0.10
8.75
0.4
1.27
7.62
1.4
5.2
4.8
3.7
3.8
6.15
5.85
0.
2
14 8
17
hea' slug expose: 1 7 Pamem H H H H H H H W th hear slug ‘ I Dxmensmns m mm ‘ ‘ v mum draqu auvmng >0 mm Spam (shuns 1.62 max 0‘41 0.1max, 152 max 127 new 7x1‘17:7‘62 nom‘ Drawmquo 651.1730‘310171. \ssue 1‘ ZS OZ 02 E w
15
T6818/T6828
4530E–BCD–07/04
41m
16 T6818/T6828
4530E–BCD–07/04
Revision History Please note that the following page numbers referred to in this section refer to the
specific revision mentioned, not to this document.
Changes from Rev.
4530C - 11/03 to Rev.
4530D - 04/04
1. Features on page 1 changed.
Changes from Rev.
4530D - 04/04 to Rev.
4530E - 07/04
1. Table “Ordering Information” on page 14 changed.
.11_mEL®
Printed on recycled paper.
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