74ALVC164245 Datasheet by NXP USA Inc.

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1. General description
The 74ALVC164245 is a high-performance, low-power, low-voltage, Si-gate CMOS
device, superior to most advanced CMOS compatible TTL families.
The 74ALVC164245 is a 16-bit (dual octal) dual supply translating transceiver featuring
non-inverting 3-state bus compatible outputs in both send and receive directions. It is
designed to interface between a 3 V and 5 V bus in a mixed 3 V and 5 V supply
environment.
This device can be used as two 8-bit transceivers or one 16-bit transceiver.
The direction control inputs (1DIR and 2DIR) determine the direction of the data flow.
nDIR (active HIGH) enables data from nAn ports to nBn ports. nDIR (active LOW) enables
data from nBn ports to nAn ports. The output enable inputs (1OE and 2OE), when HIGH,
disable both nAn and nBn ports by placing them in a high-impedance OFF-state. Pins
nAn, nOE and nDIR are referenced to VCC(A) and pins nBn are referenced to VCC(B).
In suspend mode, when one of the supply voltages is zero, there will be no current flow
from the non-zero supply towards the zero supply. The nAn-outputs must be set 3-state
and the voltage on the A-bus must be smaller than Vdiode (typical 0.7 V). VCC(B) VCC(A)
(except in suspend mode).
2. Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range:
3 V port (VCC(A)): 1.5 V to 3.6 V
5 V port (VCC(B)): 1.5 V to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Control inputs voltage range from 2.7 V to 5.5 V
Inputs accept voltages up to 5.5 V
High-impedance outputs when VCC(A) or VCC(B) = 0 V
Complies with JEDEC standard JESD8-B/JESD36
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Specified from 40 °C to +85 °C and 40 °C to +125 °C
74ALVC164245
16-bit dual supply translating transceiver; 3-state
Rev. 05 — 13 April 2010 Product data sheet
74ALVC164245_5 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 05 — 13 April 2010 2 of 20
NXP Semiconductors 74ALVC164245
16-bit dual supply translating transceiver; 3-state
3. Ordering information
4. Functional diagram
Table 1. Ordering information
Type number Temperature
range Package
Name Description Version
74ALVC164245DL 40 °C to +125 °C SSOP48 plastic shrink small outline package; 48 leads;
body width 7.5 mm SOT370-1
74ALVC164245DGG 40 °C to +125 °C TSSOP48 plastic thin shrink small outline package; 48 leads;
body width 6.1 mm SOT362-1
74ALVC164245BQ 40 °C to +125 °C HXQFN60U plastic thermal enhanced extremely thin quad flat
package; no leads; 60 terminals; UTLP based;
body 4 × 6 × 0.5 mm
SOT1134-1
Fig 1. Logic symbol
1DIR
1B0
1B1
1B2
1B3
1B4
1B5
1B6
1B7
2B0
2B1
2B2
2B3
2B4
2B5
2B6
2B7
1A0
1A1
1A2
1A3
1A4
1A5
1A6
1A7
2A0
2A1
2A2
2A3
2A4
2A5
2A6
2A7
1OE
2DIR
2OE
001aaa789
gamma
74ALVC164245_5 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 05 — 13 April 2010 3 of 20
NXP Semiconductors 74ALVC164245
16-bit dual supply translating transceiver; 3-state
Fig 2. IEC logic symbol
G3
G6
3EN1[BA]
6EN1[BA]
3EN2[AB]
6EN2[AB]
1A0
2A1
2A0
2A2
2A3
2A4
2A5
2A6
2A7
2B1
2B2
2B3
2B4
2B5
2B6
2B7
1OE
1DIR
001aaa79
0
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1B0
2B0
1B1
1B2
1B3
1B4
1B5
1B6
1B7
5
4
2
1
2OE
2DIR
7 7 jjjjjjjjjjjjjjjjjjjjjjjj O EEEEEEEEEEEEEEEEEEEEEEEE
74ALVC164245_5 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 05 — 13 April 2010 4 of 20
NXP Semiconductors 74ALVC164245
16-bit dual supply translating transceiver; 3-state
5. Pinning information
5.1 Pinning
Fig 3. Pin configuration SOT370-1 (SSOP48) and SOT362-1 (TSSOP48)
74ALVC164245
1DIR 1OE
1B0 1A0
1B1 1A1
GND GND
1B2 1A2
1B3 1A3
V
CC(B)
V
CC(A)
1B4 1A4
1B5 1A5
GND GND
1B6 1A6
1B7 1A7
2B0 2A0
2B1 2A1
GND GND
2B2 2A2
2B3 2A3
V
CC(B)
V
CC(A)
2B4 2A4
2B5 2A5
GND GND
2B6 2A6
2B7 2A7
2DIR 2OE
001aab037
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
74ALVC164245_5 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 05 — 13 April 2010 5 of 20
NXP Semiconductors 74ALVC164245
16-bit dual supply translating transceiver; 3-state
(1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input.
Fig 4. Pin configuration SOT1134-1 (HXQFN60U)
D1
D3A16A15A14A13A12A11D2
B9 B10 D7 A17
A18
B11
A19
B12
A20
B13
A21
B14
B8
A10 D6
A9
A8
B7
B6
A7
B5
A6
A22
B15
A23
B16
A24
B17
A25
A26
D8
D4A27
B18
A28A29
B19B20
A30A31A32
B4
A5
B3
B2
B1
D5
A4
A3
A2
A1
74ALVC164245
001aai85
1
Transparent top view
GND
(1)
terminal 1
index area
la,
74ALVC164245_5 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 05 — 13 April 2010 6 of 20
NXP Semiconductors 74ALVC164245
16-bit dual supply translating transceiver; 3-state
5.2 Pin description
6. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
7. Limiting values
Table 2. Pin description
Symbol Pin Description
SOT370-1 and SOT362-1 SOT1134-1
1DIR, 2DIR 1, 24 A30, A13 direction control input
1B0 to 1B7 2, 3, 5, 6, 8, 9, 11, 12 B20, A31, D5, D1, A2, B2, B3, A5 data input/output
2B0 to 2B7 13, 14, 16, 17, 19, 20, 22, 23 A6, B5, B6, A9, D2, D6, A12, B8 data input/output
GND 4, 10, 15, 21, 28, 34, 39, 45 A32, A3, A8, A11, A16, A19, A24, A27 ground (0 V)
VCC(B) 7, 18 A1, A10, supply voltage B (5 V bus)
1OE, 2OE 48, 25 A29, A14 output enable input (active LOW)
1A0 to 1A7 47, 46, 44, 43, 41, 40, 38, 37 B18, A28, D8, D4, A25, B16, B15, A22 data input/output
2A0 to 2A7 36, 35, 33, 32, 30, 29, 27, 26 A21, B13, B12, A18, D3, D7, A15, B10 data input/output
VCC(A) 31, 42 A17, A26 supply voltage A (3 V bus)
n.c. - A4, A7, A20, A23, B1, B4, B7, B9, B11,
B14, B17, B19 not connected
Table 3. Function table[1]
Inputs Outputs
nOE nDIR nAn nBn
L L nAn = nBn inputs
L H inputs nBn = nAn
HXZZ
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). See
[1].
Symbol Parameter Conditions Min Max Unit
VCC(B) supply voltage B VCC(B) VCC(A) 0.5 +6.0 V
VCC(A) supply voltage A VCC(B) VCC(A) 0.5 +4.6 V
IIK input clamping current VI<0V 50 - mA
VIinput voltage [2] 0.5 +6.0 V
VI/O input/output voltage 0.5 VCC +0.5 V
IOK output clamping current VO>V
CC or VO<0V - ±50 mA
VOoutput voltage output HIGH or LOW [2] 0.5 VCC +0.5 V
output 3-state [2] 0.5 +6.0 V
IO(sink/source) output sink or source
current VO=0VtoV
CC -±50 mA
ICC supply current - 100 mA
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Product data sheet Rev. 05 — 13 April 2010 7 of 20
NXP Semiconductors 74ALVC164245
16-bit dual supply translating transceiver; 3-state
[1] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.
[2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[3] Above 60 °C the value of Ptot derates linearly with 5.5 mW/K.
[4] Above 70 °C the value of Ptot derates linearly with 1.8 mW/K.
8. Recommended operating conditions
IGND ground current 100 - mA
Tstg storage temperature 65 +150 °C
Ptot total power dissipation Tamb =40 °C to +125 °C
(T)SSOP48 package [3] -500mW
HXQFN60U package [4] - 1000 mW
Table 4. Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). See
[1].
Symbol Parameter Conditions Min Max Unit
Table 5. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
VCC(B) supply voltage B VCC(B) VCC(A)
maximum speed performance 2.7 - 5.5 V
low-voltage applications 1.5 - 5.5 V
VCC(A) supply voltage A VCC(B) VCC(A)
maximum speed performance 2.7 - 3.6 V
low-voltage applications 1.5 - 3.6 V
VIinput voltage control inputs: nOE and nDIR 0- 5.5V
VI/O input/output voltage nAn port 0 - VCC(A) V
nBn port 0 - VCC(B) V
VOoutput voltage nAn port 0 - VCC(A) V
nBn port 0 - VCC(B) V
Tamb ambient temperature 40 - +125 °C
Δt/ΔV input transition rise
and fall rate VCC(A) = 2.7 V to 3.0 V 0 - 20 ns/V
VCC(A) = 3.0 V to 3.6 V 0 - 10 ns/V
VCC(B) = 3.0 V to 4.5 V 0 - 20 ns/V
VCC(B) = 4.5 V to 5.5 V 0 - 10 ns/V
\va \
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Product data sheet Rev. 05 — 13 April 2010 8 of 20
NXP Semiconductors 74ALVC164245
16-bit dual supply translating transceiver; 3-state
9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Tamb = 40 °C to +85 °C Tamb = 40 °C to +125 °CUnit
Min Typ[1] Max Min Typ[1] Max
VIH HIGH-level
input voltage nBn port
VCC(B) = 3.0 V to 5.5 V [2] 2.0 - - 2.0 - - V
nAn port, nOE and nDIR
VCC(A) = 3.0 V to 3.6 V 2.0 - - 2.0 - - V
VCC(A) = 2.3 V to 2.7 V [2] 1.7 - - 1.7 - - V
VIL LOW-level
input voltage nBn port
VCC(B) = 4.5 V to 5.5 V [2] --0.8--0.8V
VCC(B) = 3.0 V to 3.6 V [2] --0.7--0.7V
nAn port, nOE and nDIR
VCC(A) = 3.0 V to 3.6 V - - 0.8 - - 0.8 V
VCC(A) = 2.3 V to 2.7 V [2] --0.7--0.7V
VOH HIGH-level
output voltage nBn port; VI=V
IH or VIL
IO=24 mA; VCC(B) = 4.5 V VCC(B) 0.8 - - VCC(B) 1.2 - - V
IO=12 mA; VCC(B) = 4.5 V VCC(B) 0.5 - - VCC(B) 0.8 - - V
IO=18 mA; VCC(B) = 3.0 V VCC(B) 0.8 - - VCC(B) 1.0 - - V
IO=100 μA; VCC(B) = 3.0 V VCC(B) 0.2 VCC(B) -V
CC(B) 0.3 VCC(B) -V
nAn port; VI=V
IH or VIL
IO=24 mA; VCC(A) = 3.0 V VCC(A) 0.7 - - VCC(A) 1.0 - - V
IO=100 μA; VCC(A) = 3.0 V VCC(A) 0.2 - - VCC(A) 0.3 - - V
IO=12 mA; VCC(A) = 2.7 V VCC(A) 0.5 - - VCC(A) 0.8 - - V
IO=8mA; V
CC(A) = 2.3 V VCC(A) 0.6 - - VCC(A) 0.6 - - V
IO=100 μA; VCC(A) = 2.3 V VCC(A) 0.2 VCC(A) -V
CC(A) 0.3 VCC(A) -V
VOL LOW-level
output voltage nBn port; VI=V
IH or VIL
IO=24mA; V
CC(B) = 4.5 V - - 0.55 - - 0.60 V
IO = 12 mA; VCC(B) = 4.5 V - - 0.40 - - 0.80 V
IO= 100 μA; VCC(B) = 4.5 V - - 0.20 - - 0.30 V
IO= 18 mA; VCC(B) = 3.0 V - - 0.55 - - 0.80 V
IO= 100 μA; VCC(B) = 3.0 V - - 0.20 - - 0.30 V
nAn port; VI=V
IH or VIL
IO= 24 mA; VCC(A) = 3.0 V - - 0.55 - - 0.80 V
IO= 100 μA; VCC(A) = 3.0 V - - 0.20 - - 0.30 V
IO= 12 mA; VCC(A) = 2.7 V - - 0.40 - - 0.60 V
IO= 12 mA; VCC(A) = 2.3 V - - 0.60 - - 0.60 V
IO= 100 μA; VCC(A) = 2.3 V - - 0.20 - - 0.20 V
IIinput leakage
current VI=5.5VorGND - ±0.1 ±5-±0.1 ±10 μA
IOZ OFF-state
output current VI=V
IH or VIL;
VO=V
CC or GND
[3] -±0.1 ±10 - ±0.1 ±20 μA
\va \ mp, \ see Figure 7 Figure 5 Figure 5 \va \
74ALVC164245_5 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 05 — 13 April 2010 9 of 20
NXP Semiconductors 74ALVC164245
16-bit dual supply translating transceiver; 3-state
[1] All typical values are measured at VCC(B) = 5.0 V, VCC(A) = 3.3 V and Tamb =25°C.
[2] If VCC(A) < 2.7 V, the switching levels at all inputs are not TTL compatible.
[3] For transceivers, the parameter IOZ includes the input leakage current.
[4] VCC(A) = 2.7 V to 3.6 V: other inputs at VCC(A) or GND; VCC(B) = 4.5 V to 5.5 V: other inputs at VCC(B) or GND.
10. Dynamic characteristics
ICC supply current VI=V
CC or GND; IO= 0 A - 0.1 40 - 0.1 80 μA
ΔICC additional
supply current per control pin;
VI=V
CC 0.6 V; IO=0A
[4] - 5 500 - 5 5000 μA
CIinput
capacitance -4.0- - --pF
CI/O input/output
capacitance nAn and nBn port - 5.0 - - - - pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Tamb = 40 °C to +85 °C Tamb = 40 °C to +125 °CUnit
Min Typ[1] Max Min Typ[1] Max
Table 7. Dynamic characteristics
GND = 0 V; tr = tf
2.5 ns; CL = 50 pF; for test circuit see Figure 7.
Symbol Parameter Conditions Tamb = 40 °C to +85 °CTamb = 40 °C to +125 °CUnit
Min Typ[1] Max Min Max
tpd propagation
delay nAn to nBn; see Figure 5 [2]
VCC(A) = 2.3 V to 2.7 V;
VCC(B) = 3.0 V to 3.6 V 1.5 3.3 7.6 1.5 9.5 ns
VCC(A) = 2.7 V;
VCC(B) = 4.5 V to 5.5 V 1.0 3.0 5.9 1.0 7.5 ns
VCC(A) = 3.0 V to 3.6 V;
VCC(B) = 4.5 V to 5.5 V 1.0 2.9 5.8 1.0 7.5 ns
nBn to nAn; see Figure 5 [2]
VCC(A) = 2.3 V to 2.7 V;
VCC(B) = 3.0 V to 3.6 V 1.0 3.0 7.6 1.0 9.5 ns
VCC(A) = 2.7 V;
VCC(B) = 4.5 V to 5.5 V 1.0 4.3 6.7 1.0 8.5 ns
VCC(A) = 3.0 V to 3.6 V;
VCC(B) = 4.5 V to 5.5 V 1.2 2.5 5.8 1.2 7.5 ns
see M 9 Figure 6 7 Wm i 9 Figure 6 7 9 Figure 6 7 9 Figure 6 7
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Product data sheet Rev. 05 — 13 April 2010 10 of 20
NXP Semiconductors 74ALVC164245
16-bit dual supply translating transceiver; 3-state
ten enable time nOE to nBn; see Figure 6 [2]
VCC(A) = 2.3 V to 2.7 V;
VCC(B) = 3.0 V to 3.6 V 1.5 4.1 11.5 1.5 14.5 ns
VCC(A) = 2.7 V;
VCC(B) = 4.5 V to 5.5 V 1.5 3.6 9.2 1.5 11.5 ns
VCC(A) = 3.0 V to 3.6 V;
VCC(B) = 4.5 V to 5.5 V 1.0 3.2 8.9 1.0 12.0 ns
nOE to nAn; see Figure 6 [2]
VCC(A) = 2.3 V to 2.7 V;
VCC(B) = 3.0 V to 3.6 V 1.5 4.6 12.3 1.5 15.5 ns
VCC(A) = 2.7 V;
VCC(B) = 4.5 V to 5.5 V 1.5 4.3 9.3 1.5 12.0 ns
VCC(A) = 3.0 V to 3.6 V;
VCC(B) = 4.5 V to 5.5 V 1.0 3.2 8.9 1.0 11.5 ns
tdis disable time nOE to nBn; see Figure 6 [2]
VCC(A) = 2.3 V to 2.7 V;
VCC(B) = 3.0 V to 3.6 V 2.0 2.7 10.5 2.0 13.5 ns
VCC(A) = 2.7 V;
VCC(B) = 4.5 V to 5.5 V 2.5 4.6 9.0 2.5 11.5 ns
VCC(A) = 3.0 V to 3.6 V;
VCC(B) = 4.5 V to 5.5 V 2.1 4.9 8.6 2.1 11.0 ns
nOE to nAn; see Figure 6 [2]
VCC(A) = 2.3 V to 2.7 V;
VCC(B) = 3.0 V to 3.6 V 1.0 2.7 9.3 1.0 12.0 ns
VCC(A) = 2.7 V;
VCC(B) = 4.5 V to 5.5 V 1.5 3.5 9.0 1.5 11.5 ns
VCC(A) = 3.0 V to 3.6 V;
VCC(B) = 4.5 V to 5.5 V 2.0 3.2 8.6 2.0 11.0 ns
Table 7. Dynamic characteristics …continued
GND = 0 V; tr = tf
2.5 ns; CL = 50 pF; for test circuit see Figure 7.
Symbol Parameter Conditions Tamb = 40 °C to +85 °CTamb = 40 °C to +125 °CUnit
Min Typ[1] Max Min Max
see M ii: 52
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Product data sheet Rev. 05 — 13 April 2010 11 of 20
NXP Semiconductors 74ALVC164245
16-bit dual supply translating transceiver; 3-state
[1] All typical values are measured at nominal voltage for VCC(B) and VCC(A) and at Tamb =25°C.
[2] tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[3] CPD is used to determine the dynamic power dissipation (PDin μW).
PD=C
PD ×VCC2×fi×N+Σ(CL×VCC2×fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL×VCC2×fo) = sum of outputs.
[4] The condition is VI = GND to VCC.
11. AC waveforms
CPD power
dissipation
capacitance
5 V port: nAn to nBn;
VCC(B) = 5 V; VCC(A) = 3.3 V
[3][4]
outputs enabled - 30 - - - pF
outputs disabled - 15 - - - pF
3 V port: nBn to nAn;
VCC(B) = 5 V; VCC(A) = 3.3 V
[3][4]
outputs enabled - 40 - - - pF
outputs disabled - 5 - - - pF
Table 7. Dynamic characteristics …continued
GND = 0 V; tr = tf
2.5 ns; CL = 50 pF; for test circuit see Figure 7.
Symbol Parameter Conditions Tamb = 40 °C to +85 °CTamb = 40 °C to +125 °CUnit
Min Typ[1] Max Min Max
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 5. Input (nAn, nBn) to output (nBn, nAn) propagation delays
001aaa7
92
nAn, nBn
input
nBn, nAn
output
tPHL tPLH
GND
VI
VM
VM
VOH
VOL
4 ‘ lg e TL e if *
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Product data sheet Rev. 05 — 13 April 2010 12 of 20
NXP Semiconductors 74ALVC164245
16-bit dual supply translating transceiver; 3-state
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with output load.
Fig 6. 3-state enable and disable times
mna362
tPLZ
tPHZ
outputs
disabled
outputs
enabled
VY
VX
outputs
enabled
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
nOE input
VI
VOL
VOH
VCC
VM
GND
GND
tPZL
tPZH
VM
VM
Table 8. Measurement points
Direction Supply voltage Input Output
VCC(A) VCC(B) VIVMVMVXVY
nAn port to nBn
port 2.3 V to 2.7 V 2.7 V to 3.6 V VCC(A) 0.5 ×VCC(A) 1.5 V VOL(B) + 0.3 V VOH(B) 0.3 V
nBn port to nAn
port 2.3 V to 2.7 V 2.7 V to 3.6 V 2.7 V 1.5 V 0.5 ×VCC(A) VOL(A) + 0.15 V VOH(A) 0.15 V
nAn port to nBn
port 2.7 V to 3.6 V 4.5 V to 5.5 V 2.7 V 1.5 V 0.5 ×VCC(B) 0.2 × VCC(B) 0.8 × VCC(B)
nBn port to nAn
port 2.7 V to 3.6 V 4.5 V to 5.5 V 3.0 V 1.5 V 1.5 V VOL(A) + 0.3 V VOH(A) 0.3 V
Fig 7. Test daia is given in Mt Definitions ior test circuit: RT = Termination resistance should be equai to output imped CL = Load capacimnce including iig and piece capacitance. m = Load resistance Load circuitry for switching limes 3—H—
74ALVC164245_5 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 05 — 13 April 2010 13 of 20
NXP Semiconductors 74ALVC164245
16-bit dual supply translating transceiver; 3-state
Test data is given in Table 9.
Definitions for test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
Fig 7. Load circuitry for switching times
VEXT
VCC
VIVO
DUT
CL
RT
RL
RL
G
Table 9. Test data
Direction Supply voltage Load VEXT
VCC(A) VCC(B) CLRLtPLH, tPHL tPZH, tPHZ tPZL, tPLZ
nAn port to nBn
port 2.3 V to 2.7 V 2.7 V to 3.6 V 50 pF 500 Ωopen GND 2 × VCC
nBn port to nAn
port 2.3 V to 2.7 V 2.7 V to 3.6 V 50 pF 500 Ωopen GND 6.0 V
nAn port to nBn
port 2.7 V to 3.6 V 4.5 V to 5.5 V 50 pF 500 Ωopen GND 2 × VCC
nBn port to nAn
port 2.7 V to 3.6 V 4.5 V to 5.5 V 50 pF 500 Ωopen GND 6.0 V
DIMENSIONS (mm meme ovi ‘nal dimensions) Imn A, A2 A3 hp c DI" Em e HE L LI) 0 v w y 04 235 oz 022 mm vs ma i0 12 "‘m 02 220 “25 02 013 I575 74 0535 mi ‘4 06 10 025 0‘3 0‘ Male 1 Piasiic Or meiai prulmsiuns ai o 25 mm maximum per Side are mi maimed ouTLINE REFERENCES EUROPEAN VERSION ,Ec JEDEC Jan PROJECTION SOTJNJ M07115 E» @ fig 2 a Package Outline SOT37D-1 (SSOP48) uAchusmsj AH minimmu Wm m immmmen- I; mm «mm dixciaimeix (:NXVEV 2am mgr“, Producl data sheel Rev. 05 — 13 April 20") IA
74ALVC164245_5 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 05 — 13 April 2010 14 of 20
NXP Semiconductors 74ALVC164245
16-bit dual supply translating transceiver; 3-state
12. Package outline
Fig 8. Package outline SOT370-1 (SSOP48)
UNIT A1A2A3bpcD
(1) E(1) eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.4
0.2
2.35
2.20 0.25 0.3
0.2
0.22
0.13
16.00
15.75
7.6
7.4 0.635 1.4 0.25
10.4
10.1
1.0
0.6
1.2
1.0
0.85
0.40
8
0
o
o
0.18 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT370-1 99-12-27
03-02-19
(1)
wM
bp
D
HE
E
Z
e
c
vMA
X
A
y
48 25
MO-118
24
1
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
pin 1 index
0 5 10 mm
scale
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm
SOT370
-1
A
max.
2.8
O HHHHHHHHHH HHHHHHHEHHHH |:| D I_I_I_I_I_I_I_I_I_I_I DIMENSIONS (mm are me or nal dimensions). UNIT A. A, A3 bp c D"! Em 9 H5 L LF 0 v w y z a 015 I05 025 0,2 126 52 a: as 050 03 3° W“ 005 055 025 017 0,1 I24 50 “5 79 ‘ 04 035 025 005 0‘ 04 0° Nmes 1 Wash!) m meIal pvouusIuns am Is mm maxImum perslde are um Inc‘uded 2 Wash!) ImerIead prouusmns cl 0 25 mm maxImum per slde are um Included REFERENCES OUTLINE EUROPEAN IssuE DATE VERSION ,Ec JEDEC J5,” PaoJEcnoN 99—1427. 5013624 E @ 0370249 'g 9. Package outline SOT362-1 (TSSOP48) unvousmsj AH mmmm pmvmld m Immnmmen- I; mm «mm decIaImeI: meV a v 2am AH "gm, Producl data sheel Rev. 05 — 13 April 20") IS
74ALVC164245_5 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 05 — 13 April 2010 15 of 20
NXP Semiconductors 74ALVC164245
16-bit dual supply translating transceiver; 3-state
Fig 9. Package outline SOT362-1 (TSSOP48)
UNIT A1A2A3bpcD
(1) E(2) eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05
0.2
0.1
8
0
o
o
0.1
DIMENSIONS (mm are the original dimensions).
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
SOT362-1 99-12-27
03-02-19
wM
θ
A
A1
A2
D
Lp
Q
detail X
E
Z
e
c
L
X
(A )
3
0.25
124
48 25
y
pin 1 index
b
H
1.05
0.85
0.28
0.17
0.2
0.1
12.6
12.4
6.2
6.0 0.5 1 0.25
8.3
7.9
0.50
0.35
0.8
0.4
0.08
0.8
0.4
p
EvMA
A
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362
-1
A
max.
1.2
0
2.5
5 mm
scale
MO-153
7 J FEl V/ YICP e: » (é) * ’ii 4* ‘ \ [3] El * m‘m ”E El ‘ {+7 El El El ‘ E El D ‘ E El El El D3 + EB El ‘ E El El El '3 E El El ‘ BE / \ El El El Iii EH Efli J / El El EHEI El K \ ‘ H \ 7 0 2 5 5 mm ##4## Dwmensuons sca‘e um Am i: DDhEEhee‘ez 9323 eRk L L‘ v w y h max 050 005 035 41 ‘90 SI 390 025 035 0125 mm mm 043 002 030 40 185 60 385 05 I 25 3 45 05 020 030 0075 007 005 008 01 mm 046 000 025 39 180 59 380 015 025 0025 smmrw Omlme Helevences Emopean \ssue dam WSW" \EC ‘ JEDEC ‘ JEITA Drmecmn sonmq g© 0342-17 Fig 10. Package outline SOT1134-1 (HXOFNSOU) unvousmsj AH mmvmafiuu mm“: m lmsdnzumen' m mm «mm d‘xdmmev: Producl data sheel Rev. 05 — 13 April 20")
74ALVC164245_5 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 05 — 13 April 2010 16 of 20
NXP Semiconductors 74ALVC164245
16-bit dual supply translating transceiver; 3-state
Fig 10. Package outline SOT1134-1 (HXQFN60U)
References
Outline
version
European
projection Issue date
IEC JEDEC JEITA
SOT1134-1 - - -
- - -
- - -
sot1134-1_po
08-12-17
09-01-22
Unit
mm
max
nom
min
0.50
0.48
0.46
0.05
0.02
0.00
4.1
4.0
3.9
1.90
1.85
1.80
6.1
6.0
5.9
3.90
3.85
3.80
1 2.5 4.5
0.125
0.075
0.025
0.07
A
Dimensions
H
XQFN60U: plastic thermal enhanced extremely thin quad flat package; no leads;
6
0 terminals; UTLP based; body 4 x 6 x 0.5 mm SOT1134
-1
A1b
0.35
0.30
0.25
DD
hEE
h
0.08 0.1
yy
1
e
0.5
e1e2e3
3
e4eR
0.5
k
0.25
0.20
0.15
L
0.35
0.30
0.25
L1v
0.05
w
0 2.5 5 mm
scale
AC B
v
Cw
B A
terminal 1
index area
D
E
C
y
C
y1
X
detail X
AA1
eR
e3e4
e2
e1
e
e
1/2 e
1/2 e
bAC B
v
Cw
k
L
B20 B18
A27
D8
D4A32
D5
D7D6
D1
D3D2
Dh
Eh
L1
terminal 1
index area
A11 A16
B10B8
A17
B11
B17
A26A1
B1
A10
B7
74ALVC164245_5 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 05 — 13 April 2010 17 of 20
NXP Semiconductors 74ALVC164245
16-bit dual supply translating transceiver; 3-state
13. Abbreviations
14. Revision history
Table 10. Abbreviations
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74ALVC164245_5 20100413 Product data sheet - 74ALVC164245_4
Modifications: 74ALVC164245BQ changed from HUQFN60U (SOT1025-1) to HXQFN60U (SOT1134-1)
package.
74ALVC164245_4 20081111 Product data sheet - 74ALVC164245_3
Modifications: Added type number 74ALVC164245 (HUQFN60U package)
74ALVC164245_3 20040914 Product data sheet - 74ALVC164245_2
74ALVC164245_2 20040601 Product data sheet - 74ALVC164245_1
74ALVC164245_1 19980826 Product specification - -
74ALVC164245_5 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 05 — 13 April 2010 18 of 20
NXP Semiconductors 74ALVC164245
16-bit dual supply translating transceiver; 3-state
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. The product is not designed, authorized or warranted to be
suitable for use in medical, military, aircraft, space or life support equipment,
nor in applications where failure or malfunction of an NXP Semiconductors
product can reasonably be expected to result in personal injury, death or
severe property or environmental damage. NXP Semiconductors accepts no
liability for inclusion and/or use of NXP Semiconductors products in such
equipment or applications and therefore such inclusion and/or use is at the
customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on a weakness or default in the
customer application/use or the application/use of customer’s third party
customer(s) (hereinafter both referred to as “Application”). It is customer’s
sole responsibility to check whether the NXP Semiconductors product is
suitable and fit for the Application planned. Customer has to do all necessary
testing for the Application in order to avoid a default of the Application and the
product. NXP Semiconductors does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
hug :l/www. nxgcom salesaddresses®nx9£0m
74ALVC164245_5 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 05 — 13 April 2010 19 of 20
NXP Semiconductors 74ALVC164245
16-bit dual supply translating transceiver; 3-state
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74ALVC164245
16-bit dual supply translating transceiver; 3-state
© NXP B.V. 2010. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 13 April 2010
Document identifier: 74ALVC164245_5
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
6 Functional description . . . . . . . . . . . . . . . . . . . 6
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
8 Recommended operating conditions. . . . . . . . 7
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 8
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
11 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . 11
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 17
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
16 Contact information. . . . . . . . . . . . . . . . . . . . . 19
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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