C8051F55x, 56x, 57x Datasheet

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SILIEEIN LABS
Mixed Signal ISP Flash MCU Family
C8051F55x/56x/57x
Rev. 1.2 9/14 Copyright © 2014 by Silicon Laboratories C8051F55x, C8051F56x, C8051F57x
Analog Peripherals
-12-Bit ADC
Up to 200 ksps
Up to 32 external single-ended inputs
VREF from on-chip VREF, external pin or VDD
Internal or external start of conversion source
Built-in temperature sensor
-Two Comparators
Programmable hysteresis and response time
Configurable as interrupt or reset source
Low current
On-Chip Debug
-On-chip debug circuitry facilitates full speed, non-
intrusive in-system debug (no emulator required)
-Provides breakpoints, single stepping,
inspect/modify memory and registers
-Superior performance to emulation systems using
ICE-chips, target pods, and sockets
-Low cost, complete development kit
Supply Voltage 1.8 to 5.25 V
-Typical operating current: 19 mA at 50 MHz
-Typical stop mode current: 1 µA
High-Speed 8051 µC Core
-Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
-Up to 50 MIPS throughput with 50 MHz clock
-Expanded interrupt handler
Memory
-2304 bytes internal data RAM (256 + 2048 XRAM)
-32 or 16 kB Flash; In-system programmable in
512-byte Sectors
Digital Peripherals
-33, 25, or 18 Port I/O; All 5 V tolerant
-CAN 2.0 Controller—no crystal required
-LIN 2.1 Controller (Master and Slave capable); no
crystal required
-Hardware enhanced UART, SMBus™, and
enhanced SPI™ serial ports
-Four general purpose 16-bit counter/timers
-16-bit programmable counter array (PCA) with six
capture/compare modules and enhanced PWM
functionality
Clock Sources
-Internal 24 MHz with ±0.5% accuracy for CAN and
master LIN operation
-External oscillator: Crystal, RC, C, or clock
(1 or 2 pin modes)
-Can switch between clock sources on-the-fly;
useful in power saving modes
Packages
-40-pin QFN (C8051F568-9 and ‘F570-5)
-32-pin QFP/QFN (C8051F560-7)
-24-pin QFN (C8051F550-7)
Automotive Qualified
-Temperature Range: –40 to +125 °C
-Compliant to AEC-Q100
ANALOG
PERIPHERALS
32 kB
ISP FLASH 2 kB XRAM
POR
DEBUG
CIRCUITRY
FLEXIBLE
INTERRUPTS
8051 CPU
(50 MIPS)
DIGITAL I/O
24 MHz PRECISION
INTERNAL OSCILLATOR
HIGH-SPEED CONTROLLER CORE
WDT
2x Clock Multiplier
UART 0
SMBus
SPI
PCA
Timers 0-3
CAN
Crossbar
LIN
Ports 0-4
External
Memory
Interface
A
M
U
X
12-bit
200 ksps
ADC
TEMP
SENSOR
Voltage
Comparators 0-1
VREG
VREF
, . SILIEUN LABS
C8051F55x/56x/57x
2 Rev. 1.2
, . SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 3
Table of Contents
1. System Overview ..................................................................................................... 16
2. Ordering Information............................................................................................... 20
3. Pin Definitions.......................................................................................................... 22
4. Package Specifications........................................................................................... 28
4.1. QFN-40 Package Specifications........................................................................ 28
4.2. QFP-32 Package Specifications........................................................................ 30
4.3. QFN-32 Package Specifications........................................................................ 32
4.4. QFN-24 Package Specifications........................................................................ 34
5. Electrical Characteristics........................................................................................ 36
5.1. Absolute Maximum Specifications..................................................................... 36
5.2. Electrical Characteristics ................................................................................... 37
6. 12-Bit ADC (ADC0)................................................................................................... 47
6.1. Modes of Operation........................................................................................... 48
6.1.1. Starting a Conversion................................................................................ 48
6.1.2. Tracking Modes......................................................................................... 48
6.1.3. Timing ....................................................................................................... 49
6.1.4. Burst Mode................................................................................................ 50
6.2. Output Code Formatting.................................................................................... 52
6.2.1. Settling Time Requirements...................................................................... 52
6.3. Selectable Gain ................................................................................................. 53
6.3.1. Calculating the Gain Value........................................................................ 53
6.3.2. Setting the Gain Value .............................................................................. 55
6.4. Programmable Window Detector....................................................................... 61
6.4.1. Window Detector In Single-Ended Mode .................................................. 63
6.5. ADC0 Analog Multiplexer .................................................................................. 65
6.6. Temperature Sensor.......................................................................................... 67
7. Voltage Reference.................................................................................................... 68
8. Comparators............................................................................................................. 70
8.1. Comparator Multiplexer ..................................................................................... 76
9. Voltage Regulator (REG0)....................................................................................... 79
10. CIP-51 Microcontroller........................................................................................... 81
10.1. Performance.................................................................................................... 81
10.2. Instruction Set.................................................................................................. 83
10.2.1. Instruction and CPU Timing .................................................................... 83
10.3. CIP-51 Register Descriptions .......................................................................... 87
10.4. Serial Number Special Function Registers (SFRs) ......................................... 91
11. Memory Organization ............................................................................................ 92
11.1. Program Memory............................................................................................. 92
11.1.1. MOVX Instruction and Program Memory ................................................ 93
11.2. Data Memory................................................................................................... 93
11.2.1. Internal RAM ........................................................................................... 93
12. Special Function Registers................................................................................... 95
12.1. SFR Paging ..................................................................................................... 95
, . SILIEUN LABS
C8051F55x/56x/57x
4 Rev. 1.2
12.2. Interrupts and SFR Paging.............................................................................. 95
12.3. SFR Page Stack Example............................................................................... 97
13. Interrupts .............................................................................................................. 112
13.1. MCU Interrupt Sources and Vectors.............................................................. 112
13.1.1. Interrupt Priorities.................................................................................. 113
13.1.2. Interrupt Latency ................................................................................... 113
13.2. Interrupt Register Descriptions...................................................................... 115
13.3. External Interrupts INT0 and INT1................................................................. 122
14. Flash Memory....................................................................................................... 124
14.1. Programming The Flash Memory.................................................................. 124
14.1.1. Flash Lock and Key Functions.............................................................. 124
14.1.2. Flash Erase Procedure ......................................................................... 125
14.1.3. Flash Write Procedure .......................................................................... 125
14.1.4. Flash Write Optimization....................................................................... 126
14.2. Non-volatile Data Storage ............................................................................. 127
14.3. Security Options ............................................................................................ 127
14.4. Flash Write and Erase Guidelines................................................................. 129
14.4.1. VDD Maintenance and the VDD monitor ................................................ 129
14.4.2. PSWE Maintenance.............................................................................. 130
14.4.3. System Clock ........................................................................................ 130
15. Power Management Modes................................................................................. 135
15.1. Idle Mode....................................................................................................... 135
15.2. Stop Mode ..................................................................................................... 136
15.3. Suspend Mode .............................................................................................. 136
16. Reset Sources...................................................................................................... 138
16.1. Power-On Reset............................................................................................ 139
16.2. Power-Fail Reset/VDD Monitor ..................................................................... 139
16.3. External Reset............................................................................................... 141
16.4. Missing Clock Detector Reset ....................................................................... 141
16.5. Comparator0 Reset ....................................................................................... 142
16.6. PCA Watchdog Timer Reset ......................................................................... 142
16.7. Flash Error Reset .......................................................................................... 142
16.8. Software Reset.............................................................................................. 142
17. External Data Memory Interface and On-Chip XRAM....................................... 144
17.1. Accessing XRAM........................................................................................... 144
17.1.1. 16-Bit MOVX Example .......................................................................... 144
17.1.2. 8-Bit MOVX Example ............................................................................ 144
17.2. Configuring the External Memory Interface................................................... 145
17.3. Port Configuration.......................................................................................... 145
17.4. Multiplexed Mode .......................................................................................... 149
17.5. Memory Mode Selection................................................................................ 150
17.5.1. Internal XRAM Only .............................................................................. 150
17.5.2. Split Mode without Bank Select............................................................. 150
17.5.3. Split Mode with Bank Select.................................................................. 151
17.5.4. External Only......................................................................................... 151
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C8051F55x/56x/57x
Rev. 1.2 5
17.6. Timing .......................................................................................................... 151
17.6.1. Multiplexed Mode.................................................................................. 153
18. Oscillators and Clock Selection ......................................................................... 157
18.1. System Clock Selection................................................................................. 157
18.2. Programmable Internal Oscillator.................................................................. 159
18.2.1. Internal Oscillator Suspend Mode......................................................... 159
18.3. Clock Multiplier .............................................................................................. 162
18.4. External Oscillator Drive Circuit..................................................................... 164
18.4.1. External Crystal Example...................................................................... 166
18.4.2. External RC Example............................................................................ 167
18.4.3. External Capacitor Example.................................................................. 167
19. Port Input/Output ................................................................................................. 169
19.1. Port I/O Modes of Operation.......................................................................... 170
19.1.1. Port Pins Configured for Analog I/O...................................................... 170
19.1.2. Port Pins Configured For Digital I/O...................................................... 170
19.1.3. Interfacing Port I/O in a Multi-Voltage System ...................................... 171
19.2. Assigning Port I/O Pins to Analog and Digital Functions............................... 171
19.2.1. Assigning Port I/O Pins to Analog Functions ........................................ 171
19.2.2. Assigning Port I/O Pins to Digital Functions.......................................... 171
19.2.3. Assigning Port I/O Pins to External Digital Event Capture Functions ... 172
19.3. Priority Crossbar Decoder ............................................................................. 172
19.4. Port I/O Initialization ...................................................................................... 174
19.5. Port Match ..................................................................................................... 179
19.6. Special Function Registers for Accessing and Configuring Port I/O ............. 183
20. Local Interconnect Network (LIN0)..................................................................... 193
20.1. Software Interface with the LIN Controller..................................................... 194
20.2. LIN Interface Setup and Operation................................................................ 194
20.2.1. Mode Definition ..................................................................................... 194
20.2.2. Baud Rate Options: Manual or Autobaud ............................................. 194
20.2.3. Baud Rate Calculations: Manual Mode................................................. 194
20.2.4. Baud Rate Calculations—Automatic Mode........................................... 196
20.3. LIN Master Mode Operation .......................................................................... 197
20.4. LIN Slave Mode Operation ............................................................................ 198
20.5. Sleep Mode and Wake-Up ............................................................................ 199
20.6. Error Detection and Handling ........................................................................ 199
20.7. LIN Registers................................................................................................. 200
20.7.1. LIN Direct Access SFR Registers Definitions ....................................... 200
20.7.2. LIN Indirect Access SFR Registers Definitions..................................... 202
21. Controller Area Network (CAN0) ........................................................................ 210
21.1. Bosch CAN Controller Operation................................................................... 211
21.1.1. CAN Controller Timing .......................................................................... 211
21.1.2. CAN Register Access............................................................................ 212
21.1.3. Example Timing Calculation for 1 Mbit/Sec Communication ................ 212
21.2. CAN Registers............................................................................................... 214
21.2.1. CAN Controller Protocol Registers........................................................ 214
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C8051F55x/56x/57x
6 Rev. 1.2
21.2.2. Message Object Interface Registers..................................................... 214
21.2.3. Message Handler Registers.................................................................. 214
21.2.4. CAN Register Assignment .................................................................... 215
22. SMBus................................................................................................................... 218
22.1. Supporting Documents.................................................................................. 219
22.2. SMBus Configuration..................................................................................... 219
22.3. SMBus Operation .......................................................................................... 219
22.3.1. Transmitter Vs. Receiver....................................................................... 220
22.3.2. Arbitration.............................................................................................. 220
22.3.3. Clock Low Extension............................................................................. 220
22.3.4. SCL Low Timeout.................................................................................. 220
22.3.5. SCL High (SMBus Free) Timeout ......................................................... 221
22.4. Using the SMBus........................................................................................... 221
22.4.1. SMBus Configuration Register.............................................................. 221
22.4.2. SMB0CN Control Register .................................................................... 225
22.4.3. Data Register ........................................................................................ 228
22.5. SMBus Transfer Modes................................................................................. 228
22.5.1. Write Sequence (Master) ...................................................................... 229
22.5.2. Read Sequence (Master)...................................................................... 230
22.5.3. Write Sequence (Slave) ........................................................................ 231
22.5.4. Read Sequence (Slave)........................................................................ 232
22.6. SMBus Status Decoding................................................................................ 232
23. UART0................................................................................................................... 235
23.1. Baud Rate Generator .................................................................................... 235
23.2. Data Format................................................................................................... 237
23.3. Configuration and Operation ......................................................................... 238
23.3.1. Data Transmission ................................................................................ 238
23.3.2. Data Reception ..................................................................................... 238
23.3.3. Multiprocessor Communications........................................................... 240
24. Enhanced Serial Peripheral Interface (SPI0) ..................................................... 246
24.1. Signal Descriptions........................................................................................ 247
24.1.1. Master Out, Slave In (MOSI)................................................................. 247
24.1.2. Master In, Slave Out (MISO)................................................................. 247
24.1.3. Serial Clock (SCK) ................................................................................ 247
24.1.4. Slave Select (NSS) ............................................................................... 247
24.2. SPI0 Master Mode Operation........................................................................ 248
24.3. SPI0 Slave Mode Operation.......................................................................... 250
24.4. SPI0 Interrupt Sources .................................................................................. 250
24.5. Serial Clock Phase and Polarity .................................................................... 251
24.6. SPI Special Function Registers..................................................................... 252
25. Timers ................................................................................................................... 259
25.1. Timer 0 and Timer 1 ...................................................................................... 261
25.1.1. Mode 0: 13-bit Counter/Timer ............................................................... 261
25.1.2. Mode 1: 16-bit Counter/Timer ............................................................... 262
25.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload..................................... 262
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C8051F55x/56x/57x
Rev. 1.2 7
25.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)................................ 263
25.2. Timer 2 .......................................................................................................... 269
25.2.1. 16-bit Timer with Auto-Reload............................................................... 269
25.2.2. 8-bit Timers with Auto-Reload............................................................... 269
25.2.3. External Oscillator Capture Mode ......................................................... 270
25.3. Timer 3 .......................................................................................................... 275
25.3.1. 16-Bit Timer with Auto-Reload .............................................................. 275
25.3.2. 8-Bit Timers with Auto-Reload .............................................................. 275
25.3.3. External Oscillator Capture Mode ......................................................... 276
26. Programmable Counter Array............................................................................. 281
26.1. PCA Counter/Timer ....................................................................................... 282
26.2. PCA0 Interrupt Sources................................................................................. 283
26.3. Capture/Compare Modules ........................................................................... 283
26.3.1. Edge-triggered Capture Mode............................................................... 284
26.3.2. Software Timer (Compare) Mode.......................................................... 285
26.3.3. High-Speed Output Mode ..................................................................... 286
26.3.4. Frequency Output Mode ....................................................................... 287
26.3.5. 8-bit, 9-bit, 10-bit and 11-bit Pulse Width Modulator Modes ................. 288
26.3.6. 16-Bit Pulse Width Modulator Mode...................................................... 290
26.4. Watchdog Timer Mode .................................................................................. 291
26.4.1. Watchdog Timer Operation................................................................... 291
26.4.2. Watchdog Timer Usage ........................................................................ 292
26.5. Register Descriptions for PCA0..................................................................... 294
27. C2 Interface .......................................................................................................... 300
27.1. C2 Interface Registers................................................................................... 300
27.2. C2 Pin Sharing .............................................................................................. 303
, . SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 8
List of Figures
Figure 1.1. C8051F568-9 and ‘F570-5 (40-pin) Block Diagram .............................. 17
Figure 1.2. C8051F560-7 (32-pin) Block Diagram ................................................... 18
Figure 1.3. C8051F550-7 (24-pin) Block Diagram ................................................... 19
Figure 3.1. QFN-40 Pinout Diagram (Top View) ..................................................... 24
Figure 3.2. QFP-32 Pinout Diagram (Top View) ...................................................... 25
Figure 3.3. QFN-32 Pinout Diagram (Top View) ..................................................... 26
Figure 3.4. QFN-24 Pinout Diagram (Top View) ..................................................... 27
Figure 4.1. QFN-40 Package Drawing .................................................................... 28
Figure 4.2. QFN-40 Landing Diagram ..................................................................... 29
Figure 4.3. QFP-32 Package Drawing ..................................................................... 30
Figure 4.4. QFP-32 Landing Diagram ..................................................................... 31
Figure 4.5. QFN-32 Package Drawing .................................................................... 32
Figure 4.6. QFN-32 Landing Diagram ..................................................................... 33
Figure 4.7. QFN-24 Package Drawing .................................................................... 34
Figure 4.8. QFN-24 Landing Diagram ..................................................................... 35
Figure 5.1. Minimum VDD Monitor Threshold vs. System Clock Frequency ........... 39
Figure 6.1. ADC0 Functional Block Diagram ........................................................... 47
Figure 6.2. ADC0 Tracking Modes .......................................................................... 49
Figure 6.3. 12-Bit ADC Tracking Mode Example ..................................................... 50
Figure 6.4. 12-Bit ADC Burst Mode Example With Repeat Count Set to 4 ............. 51
Figure 6.5. ADC0 Equivalent Input Circuit ............................................................... 53
Figure 6.6. ADC Window Compare Example: Right-Justified Data ......................... 64
Figure 6.7. ADC Window Compare Example: Left-Justified Data ........................... 64
Figure 6.8. ADC0 Multiplexer Block Diagram .......................................................... 65
Figure 6.9. Temperature Sensor Transfer Function ................................................ 67
Figure 7.1. Voltage Reference Functional Block Diagram ....................................... 68
Figure 8.1. Comparator Functional Block Diagram ................................................. 70
Figure 8.2. Comparator Hysteresis Plot .................................................................. 71
Figure 8.3. Comparator Input Multiplexer Block Diagram ........................................ 76
Figure 9.1. External Capacitors for Voltage Regulator Input/Output—
Regulator Enabled ............................................................................................. 79
Figure 9.2. External Capacitors for Voltage Regulator Input/Output—Regulator Dis-
abled ............................................................................................................... 80
Figure 10.1. CIP-51 Block Diagram ......................................................................... 82
Figure 11.1. C8051F55x/56x/57x Memory Map ...................................................... 92
Figure 11.2. Flash Program Memory Map ............................................................... 93
Figure 12.1. SFR Page Stack .................................................................................. 96
Figure 12.2. SFR Page Stack While Using SFR Page 0x0 To Access SPI0DAT ... 97
Figure 12.3. SFR Page Stack After CAN0 Interrupt Occurs .................................... 98
Figure 12.4. SFR Page Stack Upon PCA Interrupt Occurring During a CAN0 ISR . 99
Figure 12.5. SFR Page Stack Upon Return From PCA Interrupt .......................... 100
Figure 12.6. SFR Page Stack Upon Return From CAN0 Interrupt ........................ 101
Figure 14.1. Flash Program Memory Map ............................................................. 127
, . SILIEUN LABS
C8051F55x/56x/57x
9 Rev. 1.2
Figure 16.1. Reset Sources ................................................................................... 138
Figure 16.2. Power-On and VDD Monitor Reset Timing ....................................... 139
Figure 17.1. Multiplexed Configuration Example ................................................... 149
Figure 17.2. EMIF Operating Modes ..................................................................... 150
Figure 17.3. Multiplexed 16-bit MOVX Timing ....................................................... 153
Figure 17.4. Multiplexed 8-bit MOVX without Bank Select Timing ........................ 154
Figure 17.5. Multiplexed 8-bit MOVX with Bank Select Timing ............................. 155
Figure 18.1. Oscillator Options .............................................................................. 157
Figure 18.2. Example Clock Multiplier Output ....................................................... 162
Figure 18.3. External 32.768 kHz Quartz Crystal Oscillator Connection Diagram 167
Figure 19.1. Port I/O Functional Block Diagram .................................................... 169
Figure 19.2. Port I/O Cell Block Diagram .............................................................. 170
Figure 19.3. Peripheral Availability on Port I/O Pins .............................................. 173
Figure 19.4. Crossbar Priority Decoder in Example Configuration ........................ 174
Figure 20.1. LIN Block Diagram ............................................................................ 193
Figure 21.1. Typical CAN Bus Configuration ......................................................... 210
Figure 21.2. CAN Controller Diagram .................................................................... 211
Figure 21.3. Four segments of a CAN Bit .............................................................. 213
Figure 22.1. SMBus Block Diagram ...................................................................... 218
Figure 22.2. Typical SMBus Configuration ............................................................ 219
Figure 22.3. SMBus Transaction ........................................................................... 220
Figure 22.4. Typical SMBus SCL Generation ........................................................ 222
Figure 22.5. Typical Master Write Sequence ........................................................ 229
Figure 22.6. Typical Master Read Sequence ........................................................ 230
Figure 22.7. Typical Slave Write Sequence .......................................................... 231
Figure 22.8. Typical Slave Read Sequence .......................................................... 232
Figure 23.1. UART0 Block Diagram ...................................................................... 235
Figure 23.2. UART0 Timing Without Parity or Extra Bit ......................................... 237
Figure 23.3. UART0 Timing With Parity ................................................................ 237
Figure 23.4. UART0 Timing With Extra Bit ............................................................ 237
Figure 23.5. Typical UART Interconnect Diagram ................................................. 238
Figure 23.6. UART Multi-Processor Mode Interconnect Diagram ......................... 240
Figure 24.1. SPI Block Diagram ............................................................................ 246
Figure 24.2. Multiple-Master Mode Connection Diagram ...................................... 249
Figure 24.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram
............................................................................................................. 249
Figure 24.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram
............................................................................................................. 249
Figure 24.5. Master Mode Data/Clock Timing ....................................................... 251
Figure 24.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................... 252
Figure 24.7. Slave Mode Data/Clock Timing (CKPHA = 1) ................................... 252
Figure 24.8. SPI Master Timing (CKPHA = 0) ....................................................... 256
Figure 24.9. SPI Master Timing (CKPHA = 1) ....................................................... 256
Figure 24.10. SPI Slave Timing (CKPHA = 0) ....................................................... 257
Figure 24.11. SPI Slave Timing (CKPHA = 1) ....................................................... 257
, . SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 10
Figure 25.1. T0 Mode 0 Block Diagram ................................................................. 262
Figure 25.2. T0 Mode 2 Block Diagram ................................................................. 263
Figure 25.3. T0 Mode 3 Block Diagram ................................................................. 264
Figure 25.4. Timer 2 16-Bit Mode Block Diagram ................................................. 269
Figure 25.5. Timer 2 8-Bit Mode Block Diagram ................................................... 270
Figure 25.6. Timer 2 External Oscillator Capture Mode Block Diagram ................ 271
Figure 25.7. Timer 3 16-Bit Mode Block Diagram ................................................. 275
Figure 25.8. Timer 3 8-Bit Mode Block Diagram ................................................... 276
Figure 25.9. Timer 3 External Oscillator Capture Mode Block Diagram ................ 277
Figure 26.1. PCA Block Diagram ........................................................................... 281
Figure 26.2. PCA Counter/Timer Block Diagram ................................................... 282
Figure 26.3. PCA Interrupt Block Diagram ............................................................ 283
Figure 26.4. PCA Capture Mode Diagram ............................................................. 285
Figure 26.5. PCA Software Timer Mode Diagram ................................................. 286
Figure 26.6. PCA High-Speed Output Mode Diagram ........................................... 287
Figure 26.7. PCA Frequency Output Mode ........................................................... 288
Figure 26.8. PCA 8-Bit PWM Mode Diagram ........................................................ 289
Figure 26.9. PCA 9, 10 and 11-Bit PWM Mode Diagram ...................................... 290
Figure 26.10. PCA 16-Bit PWM Mode ................................................................... 291
Figure 26.11. PCA Module 2 with Watchdog Timer Enabled ................................ 292
Figure 27.1. Typical C2 Pin Sharing ...................................................................... 303
, . SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 11
List of Tables
Table 2.1. Product Selection Guide ......................................................................... 21
Table 3.1. Pin Definitions for the C8051F55x/56x/57x ............................................ 22
Table 4.1. QFN-40 Package Dimensions ................................................................ 28
Table 4.2. QFN-40 Landing Diagram Dimensions ................................................... 29
Table 4.3. QFP-32 Package Dimensions ................................................................ 30
Table 4.4. QFP-32 Landing Diagram Dimensions ................................................... 31
Table 4.5. QFN-32 Package Dimensions ................................................................ 32
Table 4.6. QFN-32 Landing Diagram Dimensions ................................................... 33
Table 4.7. QFN-24 Package Dimensions ................................................................ 34
Table 4.8. QFN-24 Landing Diagram Dimensions ................................................... 35
Table 5.1. Absolute Maximum Ratings .................................................................... 36
Table 5.2. Global Electrical Characteristics ............................................................. 37
Table 5.3. Port I/O DC Electrical Characteristics ..................................................... 40
Table 5.4. Reset Electrical Characteristics .............................................................. 41
Table 5.5. Flash Electrical Characteristics .............................................................. 41
Table 5.6. Internal High-Frequency Oscillator Electrical Characteristics ................. 42
Table 5.7. Clock Multiplier Electrical Specifications ................................................ 43
Table 5.8. Voltage Regulator Electrical Characteristics .......................................... 43
Table 5.9. ADC0 Electrical Characteristics .............................................................. 44
Table 5.10. Temperature Sensor Electrical Characteristics .................................... 45
Table 5.11. Voltage Reference Electrical Characteristics ....................................... 45
Table 5.12. Comparator 0 and Comparator 1 Electrical Characteristics ................. 46
Table 10.1. CIP-51 Instruction Set Summary .......................................................... 84
Table 12.1. Special Function Register (SFR) Memory Map for Pages 0x00 and 0x0F
106
Table 12.2. Special Function Register (SFR) Memory Map for Page 0x0C .......... 107
Table 12.3. Special Function Registers ................................................................. 108
Table 13.1. Interrupt Summary .............................................................................. 114
Table 14.1. Flash Security Summary .................................................................... 128
Table 17.1. EMIF Pinout (C8051F568-9 and ‘F570-5) .......................................... 146
Table 17.2. AC Parameters for External Memory Interface ................................... 156
Table 19.1. Port I/O Assignment for Analog Functions ......................................... 171
Table 19.2. Port I/O Assignment for Digital Functions ........................................... 172
Table 19.3. Port I/O Assignment for External Digital Event Capture Functions .... 172
Table 20.1. Baud Rate Calculation Variable Ranges ............................................ 194
Table 20.2. Manual Baud Rate Parameters Examples ......................................... 196
Table 20.3. Autobaud Parameters Examples ........................................................ 197
Table 20.4. LIN Registers* (Indirectly Addressable) .............................................. 202
Table 21.1. Background System Information ........................................................ 212
Table 21.2. Standard CAN Registers and Reset Values ....................................... 215
Table 22.1. SMBus Clock Source Selection .......................................................... 222
Table 22.2. Minimum SDA Setup and Hold Times ................................................ 223
, . SILIEUN LABS
C8051F55x/56x/57x
12 Rev. 1.2
Table 22.3. Sources for Hardware Changes to SMB0CN ..................................... 227
Table 22.4. SMBus Status Decoding ..................................................................... 233
Table 23.1. Baud Rate Generator Settings for Standard Baud Rates ................... 236
Table 24.1. SPI Slave Timing Parameters ............................................................ 258
Table 26.1. PCA Timebase Input Options ............................................................. 282
Table 26.2. PCA0CPM and PCA0PWM Bit Settings for
PCA Capture/Compare Modules ........................................................ 284
Table 26.3. Watchdog Timer Timeout Intervals1 ................................................... 293
, . SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 13
List of Registers
SFR Definition 6.4. ADC0CF: ADC0 Configuration ...................................................... 58
SFR Definition 6.5. ADC0H: ADC0 Data Word MSB .................................................... 59
SFR Definition 6.6. ADC0L: ADC0 Data Word LSB ...................................................... 59
SFR Definition 6.7. ADC0CN: ADC0 Control ................................................................ 60
SFR Definition 6.8. ADC0TK: ADC0 Tracking Mode Select ......................................... 61
SFR Definition 6.9. ADC0GTH: ADC0 Greater-Than Data High Byte .......................... 62
SFR Definition 6.10. ADC0GTL: ADC0 Greater-Than Data Low Byte .......................... 62
SFR Definition 6.11. ADC0LTH: ADC0 Less-Than Data High Byte .............................. 63
SFR Definition 6.12. ADC0LTL: ADC0 Less-Than Data Low Byte ............................... 63
SFR Definition 6.13. ADC0MX: ADC0 Channel Select ................................................. 66
SFR Definition 7.1. REF0CN: Reference Control ......................................................... 69
SFR Definition 8.1. CPT0CN: Comparator0 Control ..................................................... 72
SFR Definition 8.2. CPT0MD: Comparator0 Mode Selection ....................................... 73
SFR Definition 8.3. CPT1CN: Comparator1 Control ..................................................... 74
SFR Definition 8.4. CPT1MD: Comparator1 Mode Selection ....................................... 75
SFR Definition 8.5. CPT0MX: Comparator0 MUX Selection ........................................ 77
SFR Definition 8.6. CPT1MX: Comparator1 MUX Selection ........................................ 78
SFR Definition 9.1. REG0CN: Regulator Control .......................................................... 80
SFR Definition 10.1. DPL: Data Pointer Low Byte ........................................................ 88
SFR Definition 10.2. DPH: Data Pointer High Byte ....................................................... 88
SFR Definition 10.3. SP: Stack Pointer ......................................................................... 89
SFR Definition 10.4. ACC: Accumulator ....................................................................... 89
SFR Definition 10.5. B: B Register ................................................................................ 89
SFR Definition 10.6. PSW: Program Status Word ........................................................ 90
SFR Definition 10.7. SNn: Serial Number n .................................................................. 91
SFR Definition 12.1. SFR0CN: SFR Page Control ..................................................... 102
SFR Definition 12.2. SFRPAGE: SFR Page ............................................................... 103
SFR Definition 12.3. SFRNEXT: SFR Next ................................................................ 104
SFR Definition 12.4. SFRLAST: SFR Last .................................................................. 105
SFR Definition 13.1. IE: Interrupt Enable .................................................................... 116
SFR Definition 13.2. IP: Interrupt Priority .................................................................... 117
SFR Definition 13.3. EIE1: Extended Interrupt Enable 1 ............................................ 118
SFR Definition 13.4. EIP1: Extended Interrupt Priority 1 ............................................ 119
SFR Definition 13.5. EIE2: Extended Interrupt Enable 2 ............................................ 120
SFR Definition 13.6. EIP2: Extended Interrupt Priority Enabled 2 .............................. 121
SFR Definition 13.7. IT01CF: INT0/INT1 Configuration .............................................. 123
SFR Definition 14.1. PSCTL: Program Store R/W Control ......................................... 131
SFR Definition 14.2. FLKEY: Flash Lock and Key ...................................................... 132
SFR Definition 14.3. FLSCL: Flash Scale ................................................................... 133
SFR Definition 14.4. CCH0CN: Cache Control ........................................................... 134
SFR Definition 14.5. ONESHOT: Flash Oneshot Period ............................................ 134
SFR Definition 15.1. PCON: Power Control ................................................................ 137
SFR Definition 16.1. VDM0CN: VDD Monitor Control ................................................ 141
, . SILIEUN LABS
C8051F55x/56x/57x
14 Rev. 1.2
SFR Definition 16.2. RSTSRC: Reset Source ............................................................ 143
SFR Definition 17.1. EMI0CN: External Memory Interface Control ............................ 147
SFR Definition 17.2. EMI0CF: External Memory Configuration .................................. 148
SFR Definition 17.3. EMI0TC: External Memory Timing Control ................................ 152
SFR Definition 18.1. CLKSEL: Clock Select ............................................................... 158
SFR Definition 18.2. OSCICN: Internal Oscillator Control .......................................... 160
SFR Definition 18.3. OSCICRS: Internal Oscillator Coarse Calibration ...................... 161
SFR Definition 18.4. OSCIFIN: Internal Oscillator Fine Calibration ............................ 161
SFR Definition 18.5. CLKMUL: Clock Multiplier .......................................................... 163
SFR Definition 18.6. OSCXCN: External Oscillator Control ........................................ 165
SFR Definition 19.1. XBR0: Port I/O Crossbar Register 0 .......................................... 176
SFR Definition 19.2. XBR1: Port I/O Crossbar Register 1 .......................................... 177
SFR Definition 19.3. XBR2: Port I/O Crossbar Register 1 .......................................... 178
SFR Definition 19.4. P0MASK: Port 0 Mask Register ................................................. 179
SFR Definition 19.5. P0MAT: Port 0 Match Register .................................................. 179
SFR Definition 19.6. P1MASK: Port 1 Mask Register ................................................. 180
SFR Definition 19.7. P1MAT: Port 1 Match Register .................................................. 180
SFR Definition 19.8. P2MASK: Port 2 Mask Register ................................................. 181
SFR Definition 19.9. P2MAT: Port 2 Match Register .................................................. 181
SFR Definition 19.10. P3MASK: Port 3 Mask Register ............................................... 182
SFR Definition 19.11. P3MAT: Port 3 Match Register ................................................ 182
SFR Definition 19.12. P0: Port 0 ................................................................................. 183
SFR Definition 19.13. P0MDIN: Port 0 Input Mode ..................................................... 184
SFR Definition 19.14. P0MDOUT: Port 0 Output Mode .............................................. 184
SFR Definition 19.15. P0SKIP: Port 0 Skip ................................................................. 185
SFR Definition 19.16. P1: Port 1 ................................................................................. 185
SFR Definition 19.17. P1MDIN: Port 1 Input Mode ..................................................... 186
SFR Definition 19.18. P1MDOUT: Port 1 Output Mode .............................................. 186
SFR Definition 19.19. P1SKIP: Port 1 Skip ................................................................. 187
SFR Definition 19.20. P2: Port 2 ................................................................................. 187
SFR Definition 19.21. P2MDIN: Port 2 Input Mode ..................................................... 188
SFR Definition 19.22. P2MDOUT: Port 2 Output Mode .............................................. 188
SFR Definition 19.23. P2SKIP: Port 2 Skip ................................................................. 189
SFR Definition 19.24. P3: Port 3 ................................................................................. 189
SFR Definition 19.25. P3MDIN: Port 3 Input Mode ..................................................... 190
SFR Definition 19.26. P3MDOUT: Port 3 Output Mode .............................................. 190
SFR Definition 19.27. P3SKIP: Port 3Skip .................................................................. 191
SFR Definition 19.28. P4: Port 4 ................................................................................. 191
SFR Definition 19.29. P4MDOUT: Port 4 Output Mode .............................................. 192
SFR Definition 20.1. LIN0ADR: LIN0 Indirect Address Register ................................. 200
SFR Definition 20.2. LIN0DAT: LIN0 Indirect Data Register ....................................... 200
SFR Definition 20.3. LIN0CF: LIN0 Control Mode Register ........................................ 201
SFR Definition 21.1. CAN0CFG: CAN Clock Configuration ........................................ 217
SFR Definition 22.1. SMB0CF: SMBus Clock/Configuration ...................................... 224
SFR Definition 22.2. SMB0CN: SMBus Control .......................................................... 226
, . SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 15
SFR Definition 22.3. SMB0DAT: SMBus Data ............................................................ 228
SFR Definition 23.1. SCON0: Serial Port 0 Control .................................................... 241
SFR Definition 23.2. SMOD0: Serial Port 0 Control .................................................... 243
SFR Definition 23.3. SBUF0: Serial (UART0) Port Data Buffer .................................. 244
SFR Definition 23.4. SBCON0: UART0 Baud Rate Generator Control ...................... 244
SFR Definition 23.6. SBRLL0: UART0 Baud Rate Generator Reload Low Byte ........ 245
SFR Definition 23.5. SBRLH0: UART0 Baud Rate Generator Reload High Byte ....... 245
SFR Definition 24.1. SPI0CFG: SPI0 Configuration ................................................... 253
SFR Definition 24.2. SPI0CN: SPI0 Control ............................................................... 254
SFR Definition 24.3. SPI0CKR: SPI0 Clock Rate ....................................................... 255
SFR Definition 24.4. SPI0DAT: SPI0 Data ................................................................. 255
SFR Definition 25.1. CKCON: Clock Control .............................................................. 260
SFR Definition 25.2. TCON: Timer Control ................................................................. 265
SFR Definition 25.3. TMOD: Timer Mode ................................................................... 266
SFR Definition 25.4. TL0: Timer 0 Low Byte ............................................................... 267
SFR Definition 25.5. TL1: Timer 1 Low Byte ............................................................... 267
SFR Definition 25.6. TH0: Timer 0 High Byte ............................................................. 268
SFR Definition 25.7. TH1: Timer 1 High Byte ............................................................. 268
SFR Definition 25.8. TMR2CN: Timer 2 Control ......................................................... 272
SFR Definition 25.9. TMR2RLL: Timer 2 Reload Register Low Byte .......................... 273
SFR Definition 25.10. TMR2RLH: Timer 2 Reload Register High Byte ...................... 273
SFR Definition 25.11. TMR2L: Timer 2 Low Byte ....................................................... 274
SFR Definition 25.12. TMR2H Timer 2 High Byte ....................................................... 274
SFR Definition 25.13. TMR3CN: Timer 3 Control ....................................................... 278
SFR Definition 25.14. TMR3RLL: Timer 3 Reload Register Low Byte ........................ 279
SFR Definition 25.15. TMR3RLH: Timer 3 Reload Register High Byte ...................... 279
SFR Definition 25.16. TMR3L: Timer 3 Low Byte ....................................................... 280
SFR Definition 25.17. TMR3H Timer 3 High Byte ....................................................... 280
SFR Definition 26.1. PCA0CN: PCA Control .............................................................. 294
SFR Definition 26.2. PCA0MD: PCA Mode ................................................................ 295
SFR Definition 26.3. PCA0PWM: PCA PWM Configuration ....................................... 296
SFR Definition 26.4. PCA0CPMn: PCA Capture/Compare Mode .............................. 297
SFR Definition 26.5. PCA0L: PCA Counter/Timer Low Byte ...................................... 298
SFR Definition 26.6. PCA0H: PCA Counter/Timer High Byte ..................................... 298
SFR Definition 26.7. PCA0CPLn: PCA Capture Module Low Byte ............................. 299
SFR Definition 26.8. PCA0CPHn: PCA Capture Module High Byte ........................... 299
H , . SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 16
1. System Overview
C8051F55x/56x/57x devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted fea-
tures are listed below. Refer to Table 2.1 for specific product feature selection and part ordering numbers.
High-speed pipelined 8051-compatible microcontroller core (up to 50 MIPS)
In-system, full-speed, non-intrusive debug interface (on-chip)
Controller Area Network (CAN 2.0B) Controller with 32 message objects, each with its own indentifier
mask (C8051F550/1/4/5, ‘F560/1/4/5/8/9, and ‘F572/3)
LIN 2.1 peripheral (fully backwards compatible, master and slave modes) (C8051F550/2/4/6,
‘F560/2/4/6/8, and ‘F570/2/4)
True 12-bit 200 ksps 32-channel single-ended ADC with analog multiplexer
Precision programmable 24 MHz internal oscillator that is within ±0.5% across the temperature range
and for VDD voltages greater than or equal to the on-chip voltage regulator minimum output at the low
setting. The oscillator is within +1.0% for VDD voltages below this minimum output setting.
On-chip Clock Multiplier to reach up to 50 MHz
32 kB (C8051F550-3, ‘F560-3, ‘F568-9, and ‘F570-1) or 16 kB (C8051F554-7, ‘F564-7, and ‘F572-5) of
on-chip Flash memory
2304 bytes of on-chip RAM
SMBus/I2C, Enhanced UART, and Enhanced SPI serial interfaces implemented in hardware
Four general-purpose 16-bit timers
External Data Memory Interface (C8051F568-9 and ‘F570-5) with 64 kB address space
Programmable Counter/Timer Array (PCA) with six capture/compare modules and Watchdog Timer
function
On-chip Voltage Regulator
On-chip Power-On Reset, VDD Monitor, and Temperature Sensor
On-chip Voltage Comparator
33, 25, or 18 Port I/O (5 V push-pull)
With on-chip Voltage Regulator, Power-On Reset, VDD monitor, Watchdog Timer, and clock oscillator, the
C8051F55x/56x/57x devices are truly stand-alone System-on-a-Chip solutions. The Flash memory can be
reprogrammed even in-circuit, providing non-volatile data storage, and also allowing field upgrades of the
8051 firmware. User software has complete control of all peripherals, and may individually shut down any
or all peripherals for power savings.
The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip
resources), full speed, in-circuit debugging using the production MCU installed in the final application. This
debug logic supports inspection and modification of memory and registers, setting breakpoints, single
stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging
using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging with-
out occupying package pins.
The devices are specified for 1.8 V to 5.25 V operation over the automotive temperature range (–40 to
+125 °C). The C8051F568-9 and ‘F570-5 are available in 40-pin QFN packages, the C8051F560-7
devices are available in 32-pin QFP and QFN packages, and the C8051F550-7 are available in 24-pin
QFN packages. All package options are lead-free and RoHS compliant. See Table 2.1 for ordering infor-
mation. Block diagrams are included in Figure 1.1, Figure 1.2, and Figure 1.3.
, . SILIEUN LABS
C8051F55x/56x/57x
17 Rev. 1.2
Figure 1.1. C8051F568-9 and ‘F570-5 (40-pin) Block Diagram
Digital Peripherals
UART0
Timers 0,
1, 2, 3
6 channel
PCA/WDT
LIN 2.1
Priority
Crossbar
Decoder
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
Crossbar Control
Port I/O Configuration
SFR
Bus
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
SPI
Debug /
Programming
Hardware
Power On
Reset
Reset
C2CK/RST
P1.6
P1.7
Analog Peripherals
Comparator 0
+
-
12-bit
200ksps
ADC
A
M
U
X
VREF
VDD
VDD
VREF
GND
CP0, CP0A
Voltage
Reference VREF
System Clock Setup
External Oscillator
XTAL1
CIP-51 8051 Controller
Core (50 MHz)
32 or 16 kB Flash
Program Memory
256 Byte RAM
Port 0
Drivers
Port 1
Drivers
Voltage Regulator
(LDO)
GND
VREGIN
VDD
XTAL2
VIO
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Port 2
Drivers
Port 3
Drivers
Temp
Sensor
P0 – P3
Comparator 1
+
-
CP1, CP1A
CAN 2.0B
GNDA
VDDA
Clock Multiplier
Internal Oscillator
(±0.5%)
External Memory Interface
2 kB XRAM
I2C
C2D
P4.0/C2D
Port 4
Driver
:P Comparalm (2Q Comparalm fl , . SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 18
Figure 1.2. C8051F560-7 (32-pin) Block Diagram
Digital Peripherals
UART0
Timers 0,
1, 2, 3
6 channel
PCA/WDT
LIN 2.1
Priority
Crossbar
Decoder
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
Crossbar Control
Port I/O Configuration
SFR
Bus
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
SPI
Debug /
Programming
Hardware
Power On
Reset
Reset
C2CK/RST
P1.6
P1.7
Analog Peripherals
Comparator 0
+
-
12-bit
200ksps
ADC
A
M
U
X
VREF
VDD
VDD
VREF
GND
CP0, CP0A
Voltage
Reference VREF
System Clock Setup
External Oscillator
XTAL1
CIP-51 8051 Controller
Core (50 MHz)
32 or 16 kB Flash
Program Memory
256 Byte RAM
Port 0
Drivers
Port 1
Drivers
Voltage Regulator
(LDO)
GND
VREGIN
VDD
XTAL2
VIO
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0/C2D
Port 2
Drivers
Port 3
Driver
Temp
Sensor
P0 – P3
Comparator 1
+
-
CP1, CP1A
CAN 2.0B
GNDA
VDDA
Clock Multiplier
Internal Oscillator
(±0.5%)
2 kB XRAM
I2C
C2D
, . SILIEUN LABS
C8051F55x/56x/57x
19 Rev. 1.2
Figure 1.3. C8051F550-7 (24-pin) Block Diagram
Digital Peripherals
UART0
Timers 0,
1, 2, 3
6 channel
PCA/WDT
LIN 2.1
Priority
Crossbar
Decoder
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
Crossbar Control
Port I/O Configuration
SFR
Bus
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
SPI
Debug /
Programming
Hardware
Power On
Reset
Reset
C2CK/RST
P1.6
P1.7
Analog Peripherals
Comparator 0
+
-
12-bit
200ksps
ADC
A
M
U
X
VREF
VDD
VDD
VREF
GND
CP0, CP0A
Voltage
Reference VREF
System Clock Setup
External Oscillator
XTAL1
CIP-51 8051 Controller
Core (50 MHz)
32 or 16 kB Flash
Program Memory
256 Byte RAM
Port 0
Drivers
Port 1
Drivers
Voltage Regulator
(LDO)
GND
VREGIN
VDD
XTAL2
VIO
P2.0
P2.1/C2D
Port 2
Drivers
Temp
Sensor
P0 – P2
Comparator 1
+
-
CP1, CP1A
CAN 2.0B
GNDA
Clock Multiplier
Internal Oscillator
(±0.5%)
2 kB XRAM
I2C
C2D
, . SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 20
2. Ordering Information
The following features are common to all devices in this family:
50 MHz system clock and 50 MIPS throughput (peak)
2304 bytes of RAM (256 internal bytes and 2048 XRAM bytes)
SMBus/I2C, Enhanced SPI, Enhanced UART
Four Timers
Six Programmable Counter Array channels
Internal 24 MHz oscillator
Internal Voltage Regulator
12-bit, 200 ksps ADC
Internal Voltage Reference and Temperature Sensor
Two Analog Comparators
Table 2.1 shows the feature that differentiate the devices in this family.
, ‘ SILIEIJN LABS
C8051F55x/56x/57x
21 Rev. 1.2
Note: The suffix of the part number indicates the device rating and the package. All devices are RoHS compliant.
All devices in Table 2.1 are also available in an automotive version. For the automotive version, the -I in the
ordering part number is replaced with -A. For example, the automotive version of the C8051F550-IM is the
C8051F550-AM.
The -AM and -AQ devices receive full automotive quality production status, including AEC-Q100 qualifica-
tion, registration with International Material Data System (IMDS) and Part Production Approval Process
(PPAP) documentation. PPAP documentation is available at www.silabs.com with a registered and NDA
approved user account. The -AM and -AQ devices enable high volume automotive OEM applications with
their enhanced testing and processing. Please contact Silicon Labs sales for more information regarding
–AM and -AQ devices for your automotive project.
Table 2.1. Product Selection Guide
Ordering Part Number
Flash Memory (kB)
CAN2.0B
LIN2.1
Digital Port I/Os
External Mem. Interface
Package
Ordering Part Number
Flash Memory (kB)
CAN2.0B
LIN2.1
Digital Port I/Os
External Mem. Interface
Package
C8051F550-IM 32
 
18 QFN-24 C8051F564-IM 16
 
25 QFN-32
C8051F551-IM 32
18 QFN-24 C8051F564-IQ 16
 
25 QFP-32
C8051F552-IM 32
18 QFN-24 C8051F565-IM 16
25 QFN-32
C8051F553-IM 32 — — 18 QFN-24 C8051F565-IQ 16
25 QFP-32
C8051F554-IM 16
 
18 QFN-24 C8051F566-IM 16
25 QFN-32
C8051F555-IM 16
18 QFN-24 C8051F566-IQ 16
25 QFP-32
C8051F556-IM 16
18 QFN-24 C8051F567-IM 16 25 QFN-32
C8051F557-IM 16 — — 18 QFN-24 C8051F567-IQ 16 25 QFP-32
C8051F560-IM 32
 
25 QFN-32 C8051F568-IM 32
 
33
QFN-40
C8051F560-IQ 32
 
25 QFP-32 C8051F569-IM 32
33
QFN-40
C8051F561-IM 32
25 QFN-32 C8051F570-IM 32
33
QFN-40
C8051F561-IQ 32
25 QFP-32 C8051F571-IM 32 33
QFN-40
C8051F562-IM 32
25 QFN-32 C8051F572-IM 16
 
33
QFN-40
C8051F562-IQ 32
25 QFP-32 C8051F573-IM 16
33
QFN-40
C8051F563-IM 32 — — 25 QFN-32 C8051F574-IM 16
33
QFN-40
C8051F563-IQ 32 — — 25 QFP-32 C8051F575-IM 16 33
QFN-40
, . SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 22
3. Pin Definitions
Table 3.1. Pin Definitions for the C8051F55x/56x/57x
Name Pin
40-pin
packages
Pin
32-pin
packages
Pin
24-pin
packages
Type Description
VDD 4 4 3 Digital Supply Voltage. Must be connected.
GND 6 6 4 Digital Ground. Must be connected.
VDDA 5 5 — Analog Supply Voltage. Must be connected.
GNDA 7 7 5 Analog Ground. Must be connected.
VREGIN 3 3 2 Voltage Regulator Input
VIO 2 2 1 Port I/O Supply Voltage. Must be connected.
RST/
C2CK
10 10 8D I/O
D I/O
Device Reset. Open-drain output of internal
POR or VDD Monitor.
Clock signal for the C2 Debug Interface.
P4.0/
C2D
9 D I/O or A In
D I/O
Port 4.0. See SFR Definition 19.28.
Bi-directional data signal for the C2 Debug
Interface.
P3.0/
C2D
9 D I/O or A In
D I/O
Port 3.0. See SFR Definition 19.24.
Bi-directional data signal for the C2 Debug
Interface.
P2.1/
C2D
7 D I/O or A In
D I/O
Port 2.1. See SFR Definition 19.20.
Bi-directional data signal for the C2 Debug
Interface.
P0.0 8 8 6 D I/O or A In Port 0.0. See SFR Definition 19.12.
P0.1 1 1 24 D I/O or A In Port 0.1
P0.2 40 32 23 D I/O or A In Port 0.2
P0.3 39 31 22 D I/O or A In Port 0.3
P0.4 38 30 21 D I/O or A In Port 0.4
P0.5 37 29 20 D I/O or A In Port 0.5
P0.6 36 28 19 D I/O or A In Port 0.6
P0.7 35 27 18 D I/O or A In Port 0.7
, . SILIEUN LABS
C8051F55x/56x/57x
23 Rev. 1.2
P1.0 34 26 17 D I/O or A In Port 1.0. See SFR Definition 19.16.
P1.1 33 25 16 D I/O or A In Port 1.1.
P1.2 32 24 15 D I/O or A In Port 1.2.
P1.3 31 23 14 D I/O or A In Port 1.3.
P1.4 30 22 13 D I/O or A In Port 1.4.
P1.5 29 21 12 D I/O or A In Port 1.5.
P1.6 28 20 11 D I/O or A In Port 1.6.
P1.7 27 19 10 D I/O or A In Port 1.7.
P2.0 26 18 9D I/O or A In Port 2.0. See SFR Definition 19.20.
P2.1 25 17 D I/O or A In Port 2.1.
P2.2 24 16 D I/O or A In Port 2.2.
P2.3 23 15 D I/O or A In Port 2.3.
P2.4 22 14 D I/O or A In Port 2.4.
P2.5 21 13 D I/O or A In Port 2.5.
P2.6 20 12 D I/O or A In Port 2.6.
P2.7 19 11 D I/O or A In Port 2.7.
P3.0 18 D I/O or A In Port 3.0. See SFR Definition 19.24.
P3.1 17 D I/O or A In Port 3.1.
P3.2 16 D I/O or A In Port 3.2.
P3.3 15 D I/O or A In Port 3.3.
P3.4 14 D I/O or A In Port 3.4.
P3.5 13 D I/O or A In Port 3.5.
P3.6 12 D I/O or A In Port 3.6.
P3.7 11 D I/O or A In Port 3.7.
Table 3.1. Pin Definitions for the C8051F55x/56x/57x (Continued)
Name Pin
40-pin
packages
Pin
32-pin
packages
Pin
24-pin
packages
Type Description
6" SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 24
Figure 3.1. QFN-40 Pinout Diagram (Top View)
GND
C8051F568-IM
C8051F569-IM
C8051F570-IM
C8051F571-IM
C8051F572-IM
C8051F573-IM
C8051F574-IM
C8051F575-IM
(Top View)
P2.2
P2.1
P2.0
P1.7
P1.6
P1.5
27
28
29
25
24
26
P1.430
P2.323
P2.422
P2.521
P3.2
P3.1
P3.0
P2.7
P2.6
14
13
12
16
17
15
11
P3.3
18
P3.4
19
P3.5
20
P3.6
P3.7
GNDA
GND
VDDA
VDD
VREGIN
VIO
4
3
2
6
7
5
P0.1 / CNVSTR 1
P0.0 / VREF 8
P4.0 / C2D 9
RST / C2CK 10
P1.0
P0.7 / CAN RX
P0.6 / CAN TX
P0.5 / UART0 RX
P0.4 / UART0 TX
P0.3 / XTAL2
37
38
39
35
34
36
P0.2 / XTAL140
P1.133
P1.232
P1.331
, . SILIEUN LABS
C8051F55x/56x/57x
25 Rev. 1.2
Figure 3.2. QFP-32 Pinout Diagram (Top View)
1
VREGIN
P1.2
P1.7
P1.4
P1.3
P1.5
GNDA
VIO
P2.0
P2.1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
P1.6
C8051F560-IQ
C8051F561-IQ
C8051F562-IQ
C8051F563-IQ
C8051F564-IQ
C8051F565-IQ
C8051F566-IQ
C8051F567-IQ
(Top View)
P0.0 / VREF
VDD
VDDA
P0.1 / CNVSTR
P2.6
P2.5
P2.4
P2.3
P2.2 P1.1
P1.0
P2.7
P0.6 / CAN TX
P0.5 / UART0 RX
P0.4 / UART0 TX
RST / C2CK
P3.0 / C2D
GND
P0.7 / CAN RX
P0.3 / XTAL2
P0.2 / XTAL1
SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 26
Figure 3.3. QFN-32 Pinout Diagram (Top View)
SILIEUN LABS
C8051F55x/56x/57x
27 Rev. 1.2
Figure 3.4. QFN-24 Pinout Diagram (Top View)
GND P1.4
P1.3
P1.2
P1.1
P1.0
P0.7/CAN0 RX
15
14
13
17
18
16
P2.1/C2D
RST/C2CK
P2.0
P1.7
P1.6
P1.5
10
11
12
8
7
9
VIO
VREGIN
VDD
GND
GNDA
P0.0/VREF
4
5
6
2
1
3
P0.6/CAN0 TX
P0.5/UART0 RX
P0.4/UART0 TX
P0.3/XTAL2
P0.2/XTAL1
P0.1/CNVSTR
22
23
24
20
19
21
C8051F550-IM
C8051F551-IM
C8051F552-IM
C8051F553-IM
C8051F554-IM
C8051F555-IM
C8051F556-IM
C8051F557-IM
(Top View)
C8051F55x/56x/57x
Rev. 1.2 28
4. Package Specifications
4.1. QFN-40 Package Specifications
Figure 4.1. QFN-40 Package Drawing
Table 4.1. QFN-40 Package Dimensions
Dimension Min Typ Max Dimension Min Typ Max
A0.80 0.85 0.90 E2 4.00 4.10 4.20
A1 0.00 0.05 L0.35 0.40 0.45
b0.18 0.23 0.28 L1 0.10
D6.00 BSC aaa 0.10
D2 4.00 4.10 4.20 bbb 0.10
e0.50 BSC ddd 0.05
E6.00 BSC eee 0.08
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Solid State Outline MO-220, variation VJJD-5, except for
features A, D2, and E2 which are toleranced per supplier designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
HHHLWJ T iwmwmmm : 4L 1 , . SILIEUN LABS
C8051F55x/56x/57x
29 Rev. 1.2
Figure 4.2. QFN-40 Landing Diagram
Table 4.2. QFN-40 Landing Diagram Dimensions
Dimension Min Max Dimension Min Max
C1 5.80 5.90 X2 4.10 4.20
C2 5.80 5.90 Y1 0.75 0.85
e0.50 BSC Y2 4.10 4.20
X1 0.15 0.25
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimension and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-SM-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is
calculated based on a Fabrication Allowance of 0.05 mm.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the
metal pad is to be 60 μm minimum, all the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure
good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
9. A 4x4 array of 0.80 mm square openings on a 1.05 mm pitch should be used for the center ground pad.
Card Assembly
10. A No-Clean, Type-3 solder paste is recommended.
11. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
lllllllll I: L ‘H’m HHHHHHHH IIIIEII‘ if n I-Ill ‘ SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 30
4.2. QFP-32 Package Specifications
Figure 4.3. QFP-32 Package Drawing
Table 4.3. QFP-32 Package Dimensions
Dimension Min Typ Max Dimension Min Typ Max
A 1.60 E9.00 BSC.
A1 0.05 0.15 E1 7.00 BSC.
A2 1.35 1.40 1.45 L0.45 0.60 0.75
b0.30 0.37 0.45 aaa 0.20
c0.09 0.20 bbb 0.20
D9.00 BSC. ccc 0.10
D1 7.00 BSC. ddd 0.20
e0.80 BSC. θ3.5°
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC outline MS-026, variation BBA.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
L IT LLLLLLLL ‘LLLMLL i—L LLLLLLLLLLLLLLL LL U”JLLLLLLL’L , . SILIEUN LABS
C8051F55x/56x/57x
31 Rev. 1.2
Figure 4.4. QFP-32 Landing Diagram
Table 4.4. QFP-32 Landing Diagram Dimensions
Dimension Min Max Dimension Min Max
C1 8.40 8.50 X1 0.40 0.50
C2 8.40 8.50 Y1 1.25 1.35
E0.80 BSC
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the
metal pad is to be 60 μm minimum, all the way around the pad.
Stencil Design
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure
good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
Card Assembly
7. A No-Clean, Type-3 solder paste is recommended.
8. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
TI- { r—v—fl HHHHHHHHV \ 4D}- , L r w: m m n ‘5 w 7m ”imrm 7mm” _ D L g EL a ’\ 1 ‘ n E1 ‘ W 7 ‘ 7 n E ‘m ‘m m m w H , m "H ‘H E‘ E" E‘ HP 1} , . SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 32
4.3. QFN-32 Package Specifications
Figure 4.5. QFN-32 Package Drawing
Table 4.5. QFN-32 Package Dimensions
Dimension Min Typ Max Dimension Min Typ Max
A0.80 0.9 1.00 E2 3.20 3.30 3.40
A1 0.00 0.02 0.05 L0.30 0.40 0.50
b0.18 0.25 0.30 L1 0.00 0.15
D5.00 BSC. aaa 0.15
D2 3.20 3.30 3.40 bbb 0.15
e0.50 BSC. ddd 0.05
E5.00 BSC. eee 0.08
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220, variation VHHD except for
custom features D2, E2, and L which are toleranced per supplier designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
f7 fl m J HHHHHHHH \HHHHHHM *—\+HHH\ SSSSSSSSSSS
C8051F55x/56x/57x
33 Rev. 1.2
Figure 4.6. QFN-32 Landing Diagram
Table 4.6. QFN-32 Landing Diagram Dimensions
Dimension Min Max Dimension Min Max
C1 4.80 4.90 X2 3.20 3.40
C2 4.80 4.90 Y1 0.75 0.85
e0.50 BSC Y2 3.20 3.40
X1 0.20 0.30
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the
metal pad is to be 60 μm minimum, all the way around the pad.
Stencil Design
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure
good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
7. A 3x3 array of 1.0 mm openings on a 1.20 mm pitch should be used for the center ground pad.
Card Assembly
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
HHWEE m7 j H SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 34
4.4. QFN-24 Package Specifications
Figure 4.7. QFN-24 Package Drawing
Table 4.7. QFN-24 Package Dimensions
Dimension Min Typ Max Dimension Min Typ Max
A0.70 0.75 0.80 L0.30 0.40 0.50
A1 0.00 0.02 0.05 L1 0.00 0.15
b0.18 0.25 0.30 aaa 0.15
D4.00 BSC bbb 0.10
D2 2.55 2.70 2.80 ddd 0.05
e0.50 BSC eee 0.08
E4.00 BSC Z0.24
E2 2.55 2.70 2.80 Y0.18
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Solid State Outline MO-220, variation WGGD, except for
custom features D2, E2, Z, Y, and L which are toleranced per supplier designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
EIIII‘E ‘ ‘ ”,7,+,7,% ‘ -j m ‘ , . SILIEUN LABS
C8051F55x/56x/57x
35 Rev. 1.2
Figure 4.8. QFN-24 Landing Diagram
Table 4.8. QFN-24 Landing Diagram Dimensions
Dimension Min Max Dimension Min Max
C1 3.90 4.00 X2 2.70 2.80
C2 3.90 4.00 Y1 0.65 0.75
E0.50 BSC Y2 2.70 2.80
X1 0.20 0.30
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the
metal pad is to be 60 μm minimum, all the way around the pad.
Stencil Design
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure
good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
7. A 2x2 array of 1.10 mm x 1.10 mm openings on a 1.30 mm pitch should be used for the center ground
pad.
Card Assembly
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
, . SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 36
5. Electrical Characteristics
5.1. Absolute Maximum Specifications
Table 5.1. Absolute Maximum Ratings
Parameter Conditions Min Typ Max Units
Ambient Temperature under Bias –55 135 °C
Storage Temperature –65 150 °C
Voltage on VREGIN with Respect to GND –0.3 5.5 V
Voltage on VDD with Respect to GND –0.3 2.8 V
Voltage on VDDA with Respect to GND –0.3 2.8 V
Voltage on VIO with Respect to GND –0.3 5.5 V
Voltage on any Port I/O Pin or RST with Respect to
GND –0.3 — VIO + 0.3 V
Maximum Total Current through VREGIN or GND 500 mA
Maximum Output Current Sunk by RST or any Port Pin 100 mA
Maximum Output Current Sourced by any Port Pin 100 mA
Note: Stresses outside of the range of the “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the devices at those or any other conditions
outside of those indicated in the operation listings of this specification is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
|/\ |/\ , . SILIEUN LABS
C8051F55x/56x/57x
37 Rev. 1.2
5.2. Electrical Characteristics
Table 5.2. Global Electrical Characteristics
–40 to +125 °C, 24 MHz system clock unless otherwise specified.
Parameter Conditions Min Typ Max Units
Supply Input Voltage (VREGIN)1.85.25V
Digital Supply Voltage (VDD) System Clock < 25 MHz
System Clock > 25 MHz
VRST1—2.75 V
2 — 2.75
Analog Supply Voltage (VDDA)
(Must be connected to VDD)
System Clock < 25 MHz
System Clock > 25 MHz
VRST1—2.75 V
2 — 2.75
Port I/O Supply Voltage (VIO) Normal Operation 1.82—5.25 V
Digital Supply RAM Data
Retention Voltage —1.5— V
SYSCLK (System Clock)30—50MHz
TSYSH (SYSCLK High Time) 9 ns
TSYSL (SYSCLK Low Time) 9 ns
Specified Operating
Temperature Range –40 — +125 °C
Digital Supply Current—CPU Active (Normal Mode, fetching instructions from Flash)
IDD4VDD = 2.1 V, F = 200 kHz 85 µA
VDD = 2.1 V, F = 1.5 MHz 660 µA
VDD = 2.1 V, F = 25 MHz 9.2 11 mA
VDD = 2.1 V, F = 50 MHz 17 21 mA
IDD4VDD = 2.6 V, F = 200 kHz 120 µA
VDD = 2.6 V, F = 1.5 MHz 920 µA
VDD = 2.6 V, F = 25 MHz 13 21 mA
VDD = 2.6 V, F = 50 MHz 22 33 mA
IDD Supply Sensitivity4F = 25 MHz 68 %/V
F = 1 MHz 77 %/V
Notes:
1. Given in Table 5.4 on page 41.
2. VIO should not be lower than the VDD voltage.
3. SYSCLK must be at least 32 kHz to enable debugging.
4. Guaranteed by characterization. Does not include oscillator supply current.
5. IDD estimation for different frequencies.
6. Idle IDD estimation for different frequencies.
\A |/\ \A |/\ , . SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 38
IDD Frequency Sensitivity 4,5 VDD = 2.1 V, F < 12.5 MHz, T =
25 °C
0.43 — mA/MHz
VDD = 2.1 V, F > 12.5 MHz, T =
25 °C
0.33 — mA/MHz
VDD = 2.6 V, F < 12.5 MHz, T =
25 °C
0.60 — mA/MHz
VDD = 2.6 V, F > 12.5 MHz, T =
25 °C
0.42 — mA/MHz
Digital Supply Current—CPU Inactive (Idle Mode, not fetching instructions from Flash)
IDD4VDD = 2.1 V, F = 200 kHz 50 µA
VDD = 2.1 V, F = 1.5 MHz 410 µA
VDD = 2.1 V, F = 25 MHz 6.5 8.0 mA
VDD = 2.1 V, F = 50 MHz 13 16 mA
IDD4VDD = 2.6 V, F = 200 kHz 67 µA
VDD = 2.6 V, F = 1.5 MHz 530 µA
VDD = 2.6 V, F = 25 MHz 8.0 15 mA
VDD = 2.6 V, F = 50 MHz 16 25 mA
IDD Supply Sensitivity4F = 25 MHz 55 %/V
F = 1 MHz 58
IDD Frequency Sensitivity 4.6 VDD = 2.1V, F < 12.5 MHz, T = 25 °C — 0.26
mA/MHz
VDD = 2.1V, F > 12.5 MHz, T = 25 °C — 0.26
VDD = 2.6V, F < 12.5 MHz, T = 25 °C — 0.34
VDD = 2.6V, F > 12.5 MHz, T = 25 °C — 0.34
Digital Supply Current4
(Stop or Suspend Mode)
Oscillator not running,
VDD Monitor Disabled
µA
Temp = 25 °C—1
Temp = 60 °C—6
Temp= 125 °C—70
Table 5.2. Global Electrical Characteristics (Continued)
–40 to +125 °C, 24 MHz system clock unless otherwise specified.
Parameter Conditions Min Typ Max Units
Notes:
1. Given in Table 5.4 on page 41.
2. VIO should not be lower than the VDD voltage.
3. SYSCLK must be at least 32 kHz to enable debugging.
4. Guaranteed by characterization. Does not include oscillator supply current.
5. IDD estimation for different frequencies.
6. Idle IDD estimation for different frequencies.
.N yo 8 N 5% VDD Monieronage (V) G é 'm 1.75 1.7 I D 5 ‘ID l5 2‘] 25 II 35 AU 45 5C] Sysmm Clock Frequency (MHZ) SILIEEIN LAES
C8051F55x/56x/57x
39 Rev. 1.2
Figure 5.1. Minimum VDD Monitor Threshold vs. System Clock Frequency
Note: With system clock frequencies greater than 25 MHz, the VDD monitor level should be set to the high threshold
(VDMLVL = 1b in SFR VDM0CN) to prevent undefined CPU operation. The high threshold should only be used
with an external regulator powering VDD directly. See Figure 9.2 on page 80 for the recommended power
supply connections.
, . SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 40
Table 5.3. Port I/O DC Electrical Characteristics
VDD = 1.8 to 2.75 V, –40 to +125 °C unless otherwise specified.
Parameters Conditions Min Typ Max Units
Output High Voltage IOH = –3 mA, Port I/O push-pull
IOH = –10 µA, Port I/O push-pull
IOH = –10 mA, Port I/O push-pull
VIO 0.4
VIO 0.02
VIO 0.7
V
Output Low Voltage VIO = 1.8 V:
IOL = 70 µA
IOL = 8.5 mA
VIO = 2.7 V:
IOL = 70 µA
IOL = 8.5 mA
VIO = 5.25 V:
IOL = 70 µA
IOL = 8.5 mA
50
750
45
550
40
400
mV
Input High Voltage VREGIN = 5.25 V 0.7 x VIO V
Input Low Voltage VREGIN = 2.7 V 0.3 x VIO V
Input Leakage
Current
Weak Pullup Off
Weak Pullup On, VIO = 2.1 V,
VIN = 0 V, VDD = 1.8 V
Weak Pullup On, VIO = 2.6 V,
VIN = 0 V, VDD = 2.6 V
Weak Pullup On, VIO = 5.0 V,
VIN = 0 V, VDD = 2.6 V
7
17
49
±2
9
22
115
µA
, ‘ SILIEIJN LABS
C8051F55x/56x/57x
41 Rev. 1.2
Table 5.4. Reset Electrical Characteristics
–40 to +125 °C unless otherwise specified.
Parameter Conditions Min Typ Max Units
RST Output Low Voltage VIO = 5 V; IOL = 70 µA 40 mV
RST Input High Voltage 0.7 x VIO ——
RST Input Low Voltage 0.3 x VIO
RST Input Pullup Current RST = 0.0 V, VIO = 5 V 49 115 µA
VDD RST Threshold (VRST-LOW)1.65 1.75 1.80 V
VDD RST Threshold (VRST-HIGH)2.25 2.30 2.45 V
VREGIN Ramp Time for Power On VREGIN Ramp 0–1.8 V ——1ms
Missing Clock Detector Timeout
Time from last system clock
rising edge to reset initiation
VDD = 2.1 V
VDD = 2.5 V
200
200
340
250
600
600
µs
Reset Time Delay Delay between release of
any reset source and code
execution at location 0x0000 —155175µs
Minimum RST Low Time to
Generate a System Reset 6—µs
VDD Monitor Turn-on Time —60100µs
VDD Monitor Supply Current —12µA
Table 5.5. Flash Electrical Characteristics
VDD = 1.8 to 2.75 V, –40 to +125 °C unless otherwise specified.
Parameter Conditions Min Typ Max Units
Flash Size
C8051F550-3, ‘F560-3,
‘F568-9, and ‘F570-1 327681
Bytes
C8051F554-7, ‘F564-7, and
‘F572-5 16384
Endurance 20 k 150 k Erase/Write
Retention 125 °C 10 — — Years
Erase Cycle Time 25 MHz System Clock 28 30 45 ms
Write Cycle Time 25 MHz System Clock 79 84 125 µs
VDD Write/Erase operations VRST-HIGH2—— V
Temperature during
Programming Opera-
tions
–I Devices
–A Devices
0
–40
+125
+125 °C
1. On the 32 kB Flash devices, 1024 bytes at addresses 0x7C00 to 0x7FFF are reserved.
2. See Table 5.4 for the VRST-HIGH specification.
\V , . SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 42
Table 5.6. Internal High-Frequency Oscillator Electrical Characteristics
VDD = 1.8 to 2.75 V, –40 to +125 °C unless otherwise specified; Using factory-calibrated settings.
Parameter Conditions Min Typ Max Units
Oscillator Frequency IFCN = 111b;
VDD > VREGMIN1
IFCN = 111b;
VDD < VREGMIN1
24 0.5%
24 1.0%
242
242
24 + 0.5%
24 + 1.0%
MHz
Oscillator Supply Current
(from VDD)Internal Oscillator On
OSCICN[7:6] = 11b
880 1300 µA
Internal Oscillator Suspend
OSCICN[7:6] = 00b
ZTCEN = 1
Temp = 25 °C
Temp = 85 °C
Temp = 125 °C
67
90
130
Wake-up Time From Suspend OSCICN[7:6] = 00b — 1 µs
Power Supply Sensitivity Constant Temperature 0.11 %/V
Temperature Sensitivity3Constant Supply
TC1
TC2
5.0
–0.65
ppm/°C
ppm/°C2
1. VREGMIN is the minimum output of the voltage regulator for its low setting (REG0CN: REG0MD = 0b). See
Table 5.8, “Voltage Regulator Electrical Characteristics,” on page 43.
2. This is the average frequency across the operating temperature range
3. Use temperature coefficients TC1 and TC2 to calculate the new internal oscillator frequency using the
following equation:
f(T) = f0 x (1 + TC1 x (T - T0) + TC2 x (T - T0)2)
where f0 is the internal oscillator frequency at 25 °C and T0 is 25 °C.
, . SILIEUN LABS
C8051F55x/56x/57x
43 Rev. 1.2
Table 5.7. Clock Multiplier Electrical Specifications
VDD = 1.8 to 2.75 V, –40 to +125 °C unless otherwise specified.
Parameter Conditions Min Typ Max Units
Input Frequency (Fcmin)2——MHz
Output Frequency 50 MHz
Power Supply Current 0.9 1.9 mA
Table 5.8. Voltage Regulator Electrical Characteristics
VDD = 1.8 to 2.75 V, –40 to +125 °C unless otherwise specified.
Parameter Conditions Min Typ Max Units
Input Voltage Range (VREGIN)1.8* — 5.25 V
Dropout Voltage (VDO)Maximum Current = 50 mA 10 mV/mA
Output Voltage (VDD)2.1 V operation (REG0MD = 0)
2.6 V operation (REG0MD = 1)
2.0
2.5
2.1
2.6
2.25
2.75 V
Bias Current 1 9 µA
Dropout Indicator Detection
Threshold With respect to VDD –0.21 –0.02 V
Output Voltage Temperature
Coefficient —0.29 —mV/°C
VREG Settling Time 50 mA load with VREGIN = 2.4 V
and VDD load capacitor of 4.8 µF —450 — µs
*Note: The minimum input voltage is 1.8 V or VDD + VDO(max load), whichever is greater
, . SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 44
Table 5.9. ADC0 Electrical Characteristics
VDDA = 1.8 to 2.75 V, –40 to +125 °C, VREF = 1.5 V (REFSL=0) unless otherwise specified.
Parameter Conditions Min Typ Max Units
DC Accuracy
Resolution 12 bits
Integral Nonlinearity ±0.5 ±3 LSB
Differential Nonlinearity Guaranteed Monotonic ±0.5 ±1 LSB
Offset Error1–10 3.0 10 LSB
Full Scale Error –20 5.7 20 LSB
Offset Temperature Coefficient 7.7 ppm/°C
Dynamic performance (10 kHz sine-wave single-ended input, 1 dB below Full Scale, 200 ksps)
Signal-to-Noise Plus Distortion 63 65 dB
Total Harmonic Distortion Up to the 5th harmonic; 80 dB
Spurious-Free Dynamic Range -82 dB
Conversion Rate
SAR Conversion Clock — — 3.6 MHz
Conversion Time in SAR Clocks213 clocks
Track/Hold Acquisition Time3VDDA > 2.0 V
VDDA < 2.0 V
1.5
3.5
µs
Throughput Rate4VDDA > 2.0 V — — 200 ksps
Analog Inputs
ADC Input Voltage Range5gain = 1.0 (default)
gain = n
0
0
VREF
VREF / n
V
Absolute Pin Voltage with respect
to GND 0 — VIO V
Sampling Capacitance 31 pF
Input Multiplexer Impedance — 3 kΩ
Power Specifications
Power Supply Current
(VDDA supplied to ADC0) Operating Mode, 200 ksps 1100 1500 µA
Burst Mode (Idle) 1100 1500 µA
Power-On Time 5 — µs
Power Supply Rejection –60 mV/V
Notes:
1. Represents one standard deviation from the mean. Offset and full-scale error can be removed through
calibration.
2. An additional 2 FCLK cycles are required to start and complete a conversion
3. Additional tracking time may be required depending on the output impedance connected to the ADC input.
See Section “6.2.1. Settling Time Requirements” on page 52.
4. An increase in tracking time will decrease the ADC throughput.
5. See Section “6.3. Selectable Gain” on page 53 for more information about the setting the gain.
, ‘ SILIEIJN LABS
C8051F55x/56x/57x
45 Rev. 1.2
Table 5.10. Temperature Sensor Electrical Characteristics
VDDA = 1.8 to 2.75 V, –40 to +125 °C unless otherwise specified.
Parameter Conditions Min Typ Max Units
Linearity ±0.1 °C
Slope 3.33 mV/°C
Slope Error* 88 µV/°C
Offset Temp = 0 °C 856 mV
Offset Error* Temp = 0 °C ±14 mV
Power Supply Current 18 µA
Tracking Time 12 — — µs
*Note: Represents one standard deviation from the mean.
Table 5.11. Voltage Reference Electrical Characteristics
VDDA = 1.8 to 2.75 V, –40 to +125 °C unless otherwise specified.
Parameter Conditions Min Typ Max Units
Internal Reference (REFBE = 1)
Output Voltage 25 °C ambient (REFLV = 0) 1.45 1.50 1.55 V
25 °C ambient (REFLV = 1), VDD = 2.6 V 2.15 2.20 2.25
VREF Short-Circuit Current 5 10 mA
VREF Temperature
Coefficient 38 ppm/°C
Power Consumption Internal 30 50 µA
Load Regulation Load = 0 to 200 µA to AGND 3 µV/µA
VREF Turn-on Time 1 4.7 µF tantalum and 0.1 µF bypass 1.5 ms
VREF Turn-on Time 2 0.1 µF bypass 46 µs
Power Supply Rejection 1.2 mV/V
External Reference (REFBE = 0)
Input Voltage Range 1.5 — VDDA V
Input Current Sample Rate = 200 ksps; VREF = 1.5 V 2.1 µA
Power Specifications
Reference Bias Generator REFBE = 1 or TEMPE = 1 21 40 µA
, . SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 46
Table 5.12. Comparator 0 and Comparator 1 Electrical Characteristics
VIO = 1.8 to 5.25 V, –40 to +125 °C unless otherwise noted.
Parameter Conditions Min Typ Max Units
Response Time:
Mode 0, Vcm* = 1.5 V
CPn+ – CPn– = 100 mV 330 ns
CPn+ – CPn– = –100 mV 390 ns
Response Time:
Mode 1, Vcm* = 1.5 V
CPn+ – CPn– = 100 mV 490 ns
CPn+ – CPn– = –100 mV 610 ns
Response Time:
Mode 2, Vcm* = 1.5 V
CPn+ – CPn– = 100 mV 590 ns
CP0+ – CP0– = –100 mV 750 ns
Response Time:
Mode 3, Vcm* = 1.5 V
CPn+ – CPn– = 100 mV 2300 ns
CPn+ – CPn– = –100 mV 3100 ns
Common-Mode Rejection Ratio 2.1 13 mV/V
Positive Hysteresis 1 CPnHYP1–0 = 00 -2 0 2 mV
Positive Hysteresis 2 CPnHYP1–0 = 01 2 6 10 mV
Positive Hysteresis 3 CPnHYP1–0 = 10 511 20 mV
Positive Hysteresis 4 CPnHYP1–0 = 11 13 21 40 mV
Negative Hysteresis 1 CPnHYN1–0 = 00 -2 0 2 mV
Negative Hysteresis 2 CPnHYN1–0 = 01 2510 mV
Negative Hysteresis 3 CPnHYN1–0 = 10 511 20 mV
Negative Hysteresis 4 CPnHYN1–0 = 11 13 21 40 mV
Inverting or Non-Inverting Input
Voltage Range –0.25 — VIO + 0.25 V
Input Capacitance — 8 pF
Input Offset Voltage –10 +10 mV
Power Supply
Power Supply Rejection 0.18 mV/V
Power-up Time — 3 µs
Supply Current at DC
Mode 0 6.3 20 µA
Mode 1 3.4 10 µA
Mode 2 2.6 7.5 µA
Mode 3 0.6 3µA
*Note: Vcm is the common-mode voltage on CP0+ and CP0–.
2584 5034 5334 5.334 >m3mS< 5.34="" zwpmmam="">< silieun="" labs="">
C8051F55x/56x/57x
Rev. 1.2 47
6. 12-Bit ADC (ADC0)
The ADC0 on the C8051F55x/56x/57x consists of an analog multiplexer (AMUX0) with 33, 25, or 18 total
input selections and a 200 ksps, 12-bit successive-approximation-register (SAR) ADC with integrated
track-and-hold, programmable window detector, programmable attenuation (1:2), and hardware accumula-
tor. The ADC0 subsystem has a special Burst Mode which can automatically enable ADC0, capture and
accumulate samples, then place ADC0 in a low power shutdown mode without CPU intervention. The
AMUX0, data conversion modes, and window detector are all configurable under software control via the
Special Function Registers shows in Figure 6.1. ADC0 inputs are single-ended and may be configured to
measure P0.0-P3.7, the Temperature Sensor output, VDD, or GND with respect to GND. The voltage refer-
ence for ADC0 is selected as described in Section “6.6. Temperature Sensor” on page 67. ADC0 is
enabled when the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1, or when performing
conversions in Burst Mode. ADC0 is in low power shutdown when AD0EN is logic 0 and no Burst Mode
conversions are taking place.
Figure 6.1. ADC0 Functional Block Diagram
ADC0CN
AD0CM0
AD0CM1
AD0LJST
AD0WINT
AD0BUSY
AD0INT
BURSTEN
AD0EN
Start
Conversion
VDD
35-to-1
AMUX0
VDD
P0.0
P0.7
P1.0
P1.7
ADC0MX
ADC0MX4
ADC0MX3
ADC0MX2
ADC0MX1
ADC0MX0
GND
Temp Sensor
ADC0TK
AD0PWR3
AD0PWR2
AD0PWR1
AD0PWR0
AD0TM1
AD0TM0
AD0TK1
AD0TK0
Burst Mode
Logic
Start
Conversion
Burst Mode
Oscillator
25 MHz Max
SYSCLK
FCLK
P2.2-P2.7, P3.0 available
on 40-pin and 32-pin
packages
P3.1-P3.7 available on 40-
pin packages
00 AD0BUSY (W)
10 CNVSTR Input
Timer 2 Overflow11
01 Timer 1 Overflow
12-Bit
SAR
ADC
REF
FCLK
ADC0H
32
ADC0LTH
AD0WINT
ADC0LTL
ADC0GTH ADC0GTL
ADC0L
ADC0CF
GAINEN
AD0RPT0
AD0RPT1
AD0SC0
AD0SC1
AD0SC2
AD0SC3
AD0SC4
AD0POST
AD0PRE
AD0TM1:0
Accumulator
Window
Compare
Logic
Selectable
Gain
P2.0
P2.7
P3.0
P3.7
ADC0GNLADC0GNH ADC0GNA
, . SILIEUN LABS
C8051F55x/56x/57x
48 Rev. 1.2
6.1. Modes of Operation
In a typical system, ADC0 is configured using the following steps:
1. If a gain adjustment is required, refer to Section “6.3. Selectable Gain” on page 53.
2. Choose the start of conversion source.
3. Choose Normal Mode or Burst Mode operation.
4. If Burst Mode, choose the ADC0 Idle Power State and set the Power-up Time.
5. Choose the tracking mode. Note that Pre-Tracking Mode can only be used with Normal Mode.
6. Calculate the required settling time and set the post convert-start tracking time using the AD0TK bits.
7. Choose the repeat count.
8. Choose the output word justification (Right-Justified or Left-Justified).
9. Enable or disable the End of Conversion and Window Comparator Interrupts.
6.1.1. Starting a Conversion
A conversion can be initiated in one of four ways, depending on the programmed states of the ADC0 Start
of Conversion Mode bits (AD0CM10) in register ADC0CN. Conversions may be initiated by one of the fol-
lowing:
Writing a 1 to the AD0BUSY bit of register ADC0CN
A rising edge on the CNVSTR input signal (pin P0.1)
A Timer 1 overflow (i.e., timed continuous conversions)
A Timer 2 overflow (i.e., timed continuous conversions)
Writing a 1 to AD0BUSY provides software control of ADC0 whereby conversions are performed "on-
demand.” During conversion, the AD0BUSY bit is set to logic 1 and reset to logic 0 when the conversion is
complete. The falling edge of AD0BUSY triggers an interrupt (when enabled) and sets the ADC0 interrupt
flag (AD0INT). Note: When polling for ADC conversion completions, the ADC0 interrupt flag (AD0INT)
should be used. Converted data is available in the ADC0 data registers, ADC0H:ADC0L, when bit AD0INT
is logic 1. Note that when Timer 2 overflows are used as the conversion source, Low Byte overflows are
used if Timer2 is in 8-bit mode; High byte overflows are used if Timer 2 is in 16-bit mode. See Section
“25. Timers” on page 259 for timer configuration.
Important Note About Using CNVSTR: The CNVSTR input pin also functions as Port pin P0.1. When the
CNVSTR input is used as the ADC0 conversion source, Port pin P0.1 should be skipped by the Digital
Crossbar. To configure the Crossbar to skip P0.1, set to 1 Bit1 in register P0SKIP. See Section “19. Port
Input/Output” on page 169 for details on Port I/O configuration.
6.1.2. Tracking Modes
Each ADC0 conversion must be preceded by a minimum tracking time for the converted result to be accu-
rate. ADC0 has three tracking modes: Pre-Tracking, Post-Tracking, and Dual-Tracking. Pre-Tracking Mode
provides the minimum delay between the convert start signal and end of conversion by tracking continu-
ously before the convert start signal. This mode requires software management in order to meet minimum
tracking requirements. In Post-Tracking Mode, a programmable tracking time starts after the convert start
signal and is managed by hardware. Dual-Tracking Mode maximizes tracking time by tracking before and
after the convert start signal. Figure 6.2 shows examples of the three tracking modes.
Pre-Tracking Mode is selected when AD0TM is set to 10b. Conversions are started immediately following
the convert start signal. ADC0 is tracking continuously when not performing a conversion. Software must
allow at least the minimum tracking time between each end of conversion and the next convert start signal.
The minimum tracking time must also be met prior to the first convert start signal after ADC0 is enabled.
, . SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 49
Post-Tracking Mode is selected when AD0TM is set to 01b. A programmable tracking time based on
AD0TK is started immediately following the convert start signal. Conversions are started after the pro-
grammed tracking time ends. After a conversion is complete, ADC0 does not track the input. Rather, the
sampling capacitor remains disconnected from the input making the input pin high-impedance until the
next convert start signal.
Dual-Tracking Mode is selected when AD0TM is set to 11b. A programmable tracking time based on
AD0TK is started immediately following the convert start signal. Conversions are started after the pro-
grammed tracking time ends. After a conversion is complete, ADC0 tracks continuously until the next con-
version is started.
Depending on the output connected to the ADC input, additional tracking time, more than is specified in
Table 5.9, may be required after changing MUX settings. See the settling time requirements described in
Section “6.2.1. Settling Time Requirements” on page 52.
Figure 6.2. ADC0 Tracking Modes
6.1.3. Timing
ADC0 has a maximum conversion speed specified in Table 5.9. ADC0 is clocked from the ADC0 Subsys-
tem Clock (FCLK). The source of FCLK is selected based on the BURSTEN bit. When BURSTEN is
logic 0, FCLK is derived from the current system clock. When BURSTEN is logic 1, FCLK is derived from
the Burst Mode Oscillator, an independent clock source with a maximum frequency of 25 MHz.
When ADC0 is performing a conversion, it requires a clock source that is typically slower than FCLK. The
ADC0 SAR conversion clock (SAR clock) is a divided version of FCLK. The divide ratio can be configured
using the AD0SC bits in the ADC0CF register. The maximum SAR clock frequency is listed in Table 5.9.
ADC0 can be in one of three states at any given time: tracking, converting, or idle. Tracking time depends
on the tracking mode selected. For Pre-Tracking Mode, tracking is managed by software and ADC0 starts
conversions immediately following the convert start signal. For Post-Tracking and Dual-Tracking Modes,
the tracking time after the convert start signal is equal to the value determined by the AD0TK bits plus 2
FCLK cycles. Tracking is immediately followed by a conversion. The ADC0 conversion time is always 13
SAR clock cycles plus an additional 2 FCLK cycles to start and complete a conversion. Figure 6.3 shows
timing diagrams for a conversion in Pre-Tracking Mode and tracking plus conversion in Post-Tracking or
Dual-Tracking Mode. In this example, repeat count is set to one.
Convert Start
Post-Tracking
AD0TM= 01 Track Convert IdleIdle Track Convert..
Pre-Tracking
AD0TM = 10 Track Convert Track Convert ...
Dual-Tracking
AD0TM = 11 Track Convert TrackTrack Track Convert..
, . SILIEUN LABS
C8051F55x/56x/57x
50 Rev. 1.2
Figure 6.3. 12-Bit ADC Tracking Mode Example
6.1.4. Burst Mode
Burst Mode is a power saving feature that allows ADC0 to remain in a very low power state between con-
versions. When Burst Mode is enabled, ADC0 wakes from a very low power state, accumulates 1, 4, 8, or
16 samples using an internal Burst Mode clock (approximately 25 MHz), then re-enters a very low power
state. Since the Burst Mode clock is independent of the system clock, ADC0 can perform multiple conver-
sions then enter a very low power state within a single system clock cycle, even if the system clock is slow
(e.g., 32.768 kHz), or suspended.
Burst Mode is enabled by setting BURSTEN to logic 1. When in Burst Mode, AD0EN controls the ADC0
idle power state (i.e. the state ADC0 enters when not tracking or performing conversions). If AD0EN is set
to logic 0, ADC0 is powered down after each burst. If AD0EN is set to logic 1, ADC0 remains enabled after
each burst. On each convert start signal, ADC0 is awakened from its Idle Power State. If ADC0 is powered
down, it will automatically power up and wait the programmable Power-up Time controlled by the AD0PWR
bits. Otherwise, ADC0 will start tracking and converting immediately. Figure 6.4 shows an example of Burst
Mode Operation with a slow system clock and a repeat count of 4.
Important Note: When Burst Mode is enabled, only Post-Tracking and Dual-Tracking modes can be used.
When Burst Mode is enabled, a single convert start will initiate a number of conversions equal to the repeat
count. When Burst Mode is disabled, a convert start is required to initiate each conversion. In both modes,
the ADC0 End of Conversion Interrupt Flag (AD0INT) will be set after “repeat count” conversions have
Convert Start
ADC0 State Track
ADC0 State Convert
Time FS1 S2 S12 S13
... F
Time FS1 S2 S12 S13
... F
Convert
FS1 S2 F
Post-Tracking or Dual-Tracking Modes (AD0TK = ‘00')
Pre-Tracking Mode
AD0INT Flag
AD0INT Flag
Key
F
Sn
Equal to one period of FCLK.
Each Sn is equal to one period of the SAR clock.
, . SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 51
been accumulated. Similarly, the Window Comparator will not compare the result to the greater-than and
less-than registers until “repeat count” conversions have been accumulated.
Note: When using Burst Mode, care must be taken to issue a convert start signal no faster than once every four
SYSCLK periods. This includes external convert start signals.
Figure 6.4. 12-Bit ADC Burst Mode Example With Repeat Count Set to 4
Track..
System Clock
Convert Start
(AD0BUSY or Timer
Overflow)
Post-Tracking
AD0TM = 01
AD0EN = 0
Powered
Down Powered
Down
T C
Power-Up
and Idle T C T C T C Power-Up
and Idle TC..
Dual-Tracking
AD0TM = 11
AD0EN = 0
Powered
Down Powered
Down
T C
Power-Up
and Track T C T C T C Power-Up
and Track TC..
AD0PWR
Post-Tracking
AD0TM = 01
AD0EN = 1 Idle IdleT C T C T C T C T C..
Dual-Tracking
AD0TM = 11
AD0EN = 1 Track TrackT C T C T C T C T C..
T C T C
T C T C
T = Tracking
C = Converting
Convert Start
(CNVSTR)
Post-Tracking
AD0TM = 01
AD0EN = 0
Powered
Down Powered
Down
T C
Power-Up
and Idle Power-Up
and Idle TC..
Dual-Tracking
AD0TM = 11
AD0EN = 0
Powered
Down Powered
Down
T C
Power-Up
and Track Power-Up
and Track TC..
AD0PWR
Post-Tracking
AD0TM = 01
AD0EN = 1 Idle IdleT C
Dual-Tracking
AD0TM = 11
AD0EN = 1 Track TrackT C T C
T C
T = Tracking
C = Converting
Idle..
REF REF REF , . SILIEUN LABS
C8051F55x/56x/57x
52 Rev. 1.2
6.2. Output Code Formatting
The registers ADC0H and ADC0L contain the high and low bytes of the output conversion code. When the
repeat count is set to 1, conversion codes are represented in 12-bit unsigned integer format and the output
conversion code is updated after each conversion. Inputs are measured from 0 to VREF x 4095/4096. Data
can be right-justified or left-justified, depending on the setting of the AD0LJST bit (ADC0CN.2). Unused
bits in the ADC0H and ADC0L registers are set to 0. Example codes are shown below for both right-justi-
fied and left-justified data.
When the ADC0 Repeat Count is greater than 1, the output conversion code represents the accumulated
result of the conversions performed and is updated after the last conversion in the series is finished. Sets
of 4, 8, or 16 consecutive samples can be accumulated and represented in unsigned integer format. The
repeat count can be selected using the AD0RPT bits in the ADC0CF register. The value must be right-jus-
tified (AD0LJST = 0), and unused bits in the ADC0H and ADC0L registers are set to 0. The following
example shows right-justified codes for repeat counts greater than 1. Notice that accumulating 2n samples
is equivalent to left-shifting by n bit positions when all samples returned from the ADC have the same
value.
6.2.1. Settling Time Requirements
A minimum tracking time is required before an accurate conversion is performed. This tracking time is
determined by any series impedance, including the AMUX0 resistance, the ADC0 sampling capacitance,
and the accuracy required for the conversion.
Figure 6.5 shows the equivalent ADC0 input circuit. The required ADC0 settling time for a given settling
accuracy (SA) may be approximated by Equation 6.1. When measuring the Temperature Sensor output,
use the settling time specified in Table 5.10. When measuring VDD with respect to GND, RTOTAL reduces to
RMUX. See Table 5.9 for ADC0 minimum settling time requirements as well as the mux impedance and
sampling capacitor values.
Equation 6.1. ADC0 Settling Time Requirements
Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB).
t is the required settling time in seconds. RTOTAL is the sum of the AMUX0 resistance and any external
source resistance. n is the ADC resolution in bits (10).
Input Voltage Right-Justified ADC0H:ADC0L
(AD0LJST = 0) Left-Justified ADC0H:ADC0L
(AD0LJST = 1)
VREF x 4095/4096 0x0FFF 0xFFF0
VREF x 2048/4096 0x0800 0x8000
VREF x 2047/4096 0x07FF 0x7FF0
00x0000 0x0000
Input Voltage Repeat Count = 4 Repeat Count = 8 Repeat Count = 16
VREF x 4095/4096 0x3FFC 0x7FF8 0xFFF0
VREF x 2048/4096 0x2000 0x4000 0x8000
VREF x 2047/4096 0x1FFC 0x3FF8 0x7FF0
00x0000 0x0000 0x0000
t2n
SA
--------


RTOTALCSAMPLE
×ln=
, . SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 53
Figure 6.5. ADC0 Equivalent Input Circuit
6.3. Selectable Gain
ADC0 on the C8051F55x/56x/57x family of devices implements a selectable gain adjustment option. By
writing a value to the gain adjust address range, the user can select gain values between 0 and 1.016.
For example, three analog sources to be measured have full-scale outputs of 5.0 V, 4.0 V, and 3.0 V,
respectively. Each ADC measurement would ideally use the full dynamic range of the ADC with an internal
voltage reference of 1.5 V or 2.2 V (set to 2.2 V for this example). When selecting the first source (5.0 V
full-scale), a gain value of 0.44 (5 V full scale x 0.44 = 2.2 V full scale) provides a full-scale signal of 2.2 V
when the input signal is 5.0 V. Likewise, a gain value of 0.55 (4 V full scale x 0.55 = 2.2 V full scale) for the
second source and 0.73 (3 V full scale x 0.73 = 2.2 V full scale) for the third source provide full-scale ADC0
measurements when the input signal is full-scale.
Additionally, some sensors or other input sources have small part-to-part variations that must be
accounted for to achieve accurate results. In this case, the programmable gain value could be used as a
calibration value to eliminate these part-to-part variations.
6.3.1. Calculating the Gain Value
The ADC0 selectable gain feature is controlled by 13 bits in three registers. ADC0GNH contains the 8
upper bits of the gain value and ADC0GNL contains the 4 lower bits of the gain value. The final GAINADD
bit (ADC0GNA.0) controls an optional extra 1/64 (0.016) of gain that can be added in addition to the
ADC0GNH and ADC0GNL gain. The ADC0GNA.0 bit is set to 1 after a power-on reset.
The equivalent gain for the ADC0GNH, ADC0GNL and ADC0GNA registers is as follows:
Equation 6.2. Equivalent Gain from the ADC0GNH and ADC0GNL Registers
Where:
GAIN is the 12-bit word of ADC0GNH[7:0] and ADC0GNL[7:4]
GAINADD is the value of the GAINADD bit (ADC0GNA.0)
gain is the equivalent gain value from 0 to 1.016
RMUX
CSAMPLE
RCInput= RMUX * CSAMPLE
MUX Select
Px.x
gain GAIN
4096
---------------


GAINADD 1
64
------


×+=
, . SILIEUN LABS
C8051F55x/56x/57x
54 Rev. 1.2
For example, if ADC0GNH = 0xFC, ADC0GNL = 0x00, and GAINADD = 1, GAIN = 0xFC0 = 4032, and the
resulting equation is as follows:
The table below equates values in the ADC0GNH, ADC0GNL, and ADC0GNA registers to the equivalent
gain using this equation.
For any desired gain value, the GAIN registers can be calculated by the following:
Equation 6.3. Calculating the ADC0GNH and ADC0GNL Values from the Desired Gain
Where:
GAIN is the 12-bit word of ADC0GNH[7:0] and ADC0GNL[7:4]
GAINADD is the value of the GAINADD bit (ADC0GNA.0)
gain is the equivalent gain value from 0 to 1.016
When calculating the value of GAIN to load into the ADC0GNH and ADC0GNL registers, the GAINADD bit
can be turned on or off to reach a value closer to the desired gain value.
For example, the initial example in this section requires a gain of 0.44 to convert 5 V full scale to 2.2 V full
scale. Using Equation 6.3:
If GAINADD is set to 1, this makes the equation:
The actual gain from setting GAINADD to 1 and ADC0GNH and ADC0GNL to 0x6CA is 0.4399. A similar
gain can be achieved if GAINADD is set to 0 with a different value for ADC0GNH and ADC0GNL.
ADC0GNH Value ADC0GNL Value GAINADD Value GAIN Value Equivalent Gain
0xFC (default) 0x00 (default) 1 (default) 4032 + 64 1.0 (default)
0x7C 0x00 1 1984 + 64 0.5
0xBC 0x00 1 3008 + 64 0.75
0x3C 0x00 1 960 + 64 0.25
0xFF 0xF0 0 4095 + 0 ~1.0
0xFF 0xF0 1 4096 + 64 1.016
GAIN 4032
4096
-------------


11
64
------


×
+0.984 0.016+1.0===
GAIN gain GAINADD 1
64
------


×


4096×=
GAIN 0.44 GAINADD 1
64
------


×


4096×=
GAIN 0.44 1 1
64
------


×


4096×0.424 4096×1738 0x06CA====
, . SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 55
6.3.2. Setting the Gain Value
The three programmable gain registers are accessed indirectly using the ADC0H and ADC0L registers
when the GAINEN bit (ADC0CF.0) bit is set. ADC0H acts as the address register, and ADC0L is the data
register. The programmable gain registers can only be written to and cannot be read. See Gain Register
Definition 6.1, Gain Register Definition 6.2, and Gain Register Definition 6.3 for more information.
The gain is programmed using the following steps:
1. Set the GAINEN bit (ADC0CF.0)
2. Load the ADC0H with the ADC0GNH, ADC0GNL, or ADC0GNA address.
3. Load ADC0L with the desired value for the selected gain register.
4. Reset the GAINEN bit (ADC0CF.0)
Notes:
1. An ADC conversion should not be performed while the GAINEN bit is set.
2. Even with gain enabled, the maximum input voltage must be less than VREGIN and the maximum
voltage of the signal after gain must be less than or equal to VREF.
In code, changing the value to 0.44 gain from the previous example looks like:
// in ‘C’:
ADC0CF |= 0x01; // GAINEN = 1
ADC0H = 0x04; // Load the ADC0GNH address
ADC0L = 0x6C; // Load the upper byte of 0x6CA to ADC0GNH
ADC0H = 0x07; // Load the ADC0GNL address
ADC0L = 0xA0; // Load the lower nibble of 0x6CA to ADC0GNL
ADC0H = 0x08; // Load the ADC0GNA address
ADC0L = 0x01; // Set the GAINADD bit
ADC0CF &= ~0x01; // GAINEN = 0
; in assembly
ORL ADC0CF,#01H ; GAINEN = 1
MOV ADC0H,#04H ; Load the ADC0GNH address
MOV ADC0L,#06CH ; Load the upper byte of 0x6CA to ADC0GNH
MOV ADC0H,#07H ; Load the ADC0GNL address
MOV ADC0L,#0A0H ; Load the lower nibble of 0x6CA to ADC0GNL
MOV ADC0H,#08H ; Load the ADC0GNA address
MOV ADC0L,#01H ; Set the GAINADD bit
ANL ADC0CF,#0FEH ; GAINEN = 0
, ‘ SILIEIJN LABS
C8051F55x/56x/57x
56 Rev. 1.2
Indirect Address = 0x04;
Indirect Address = 0x07;
Gain Register Definition 6.1. ADC0GNH: ADC0 Selectable Gain High Byte
Bit76543210
Name GAINH[7:0]
Type W
Reset 11111100
Bit Name Function
7:0 GAINH[7:0] ADC0 Gain High Byte.
See Section 6.3.1 for details on calculating the value for this register.
Note: This register is accessed indirectly; See Section 6.3.2 for details for writing this register.
Gain Register Definition 6.2. ADC0GNL: ADC0 Selectable Gain Low Byte
Bit76543210
Name GAINL[3:0] Reserved Reserved Reserved Reserved
Type W W W W W
Reset 00000000
Bit Name Function
7:4 GAINL[3:0] ADC0 Gain Lower 4 Bits.
See Figure 6.3.1 for details for setting this register.
This register is only accessed indirectly through the ADC0H and ADC0L register.
3:0 Reserved Must Write 0000b
Note: This register is accessed indirectly; See Section 6.3.2 for details for writing this register.
, . SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 57
Indirect Address = 0x08;
Gain Register Definition 6.3. ADC0GNA: ADC0 Additional Selectable Gain
Bit76543210
Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved GAINADD
Type WWWWWWWW
Reset 00000001
Bit Name Function
7:1 Reserved Must Write 0000000b.
0GAINADD ADC0 Additional Gain Bit.
Setting this bit add 1/64 (0.016) gain to the gain value in the ADC0GNH and
ADC0GNL registers.
Note: This register is accessed indirectly; See Section 6.3.2 for details for writing this register.
, . SILIEUN LABS
C8051F55x/56x/57x
58 Rev. 1.2
SFR Address = 0xBC; SFR Page = 0x00
SFR Definition 6.4. ADC0CF: ADC0 Configuration
Bit76543210
Name AD0SC[4:0] AD0RPT[1:0] GAINEN
Type R/W R/W R/W R/W
Reset 11111000
Bit Name Function
7:3 AD0SC[4:0] ADC0 SAR Conversion Clock Period Bits.
SAR Conversion clock is derived from system clock by the following equation, where
AD0SC refers to the 5-bit value held in bits AD0SC40. SAR Conversion clock
requirements are given in the ADC specification table
BURSTEN = 0: FCLK is the current system clock
BURSTEN = 1: FCLK is a maximum of 30 MHz, independent of the current system
clock..
Note: Round up the result of the calculation for AD0SC
2:1 A0RPT[1:0] ADC0 Repeat Count.
Controls the number of conversions taken and accumulated between ADC0 End of
Conversion (ADCINT) and ADC0 Window Comparator (ADCWINT) interrupts. A con-
vert start is required for each conversion unless Burst Mode is enabled. In Burst
Mode, a single convert start can initiate multiple self-timed conversions. Results in
both modes are accumulated in the ADC0H:ADC0L register. When AD0RPT1–0 are
set to a value other than '00', the AD0LJST bit in the ADC0CN register must be
set to '0' (right justified).
00: 1 conversion is performed.
01: 4 conversions are performed and accumulated.
10: 8 conversions are performed and accumulated.
11: 16 conversions are performed and accumulated.
0GAINEN Gain Enable Bit.
Controls the gain programming. Refer to Section “6.3. Selectable Gain” on page 53
for information about using this bit.
AD0SC FCLK
CLKSAR
-------------------- 1=
, . SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 59
SFR Address = 0xBE; SFR Page = 0x00
SFR Address = 0xBD; SFR Page = 0x00
SFR Definition 6.5. ADC0H: ADC0 Data Word MSB
Bit76543210
Name ADC0H[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 ADC0H[7:0] ADC0 Data Word High-Order Bits.
For AD0LJST = 0 and AD0RPT as follows:
00: Bits 3–0 are the upper 4 bits of the 12-bit result. Bits 7–4 are 0000b.
01: Bits 4–0 are the upper 5 bits of the 14-bit result. Bits 7–5 are 000b.
10: Bits 5–0 are the upper 6 bits of the 15-bit result. Bits 7–6 are 00b.
11: Bits 7–0 are the upper 8 bits of the 16-bit result.
For AD0LJST = 1 (AD0RPT must be 00): Bits 7–0 are the most-significant bits of the
ADC0 12-bit result.
SFR Definition 6.6. ADC0L: ADC0 Data Word LSB
Bit76543210
Name ADC0L[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 ADC0L[7:0] ADC0 Data Word Low-Order Bits.
For AD0LJST = 0: Bits 7–0 are the lower 8 bits of the ADC0 Accumulated Result.
For AD0LJST = 1 (AD0RPT must be '00'): Bits 7–4 are the lower 4 bits of the 12-bit
result. Bits 3–0 are 0000b.
, . SILIEUN LABS
C8051F55x/56x/57x
60 Rev. 1.2
SFR Address = 0xE8; SFR Page = 0x00; Bit-Addressable
SFR Definition 6.7. ADC0CN: ADC0 Control
Bit76543210
Name AD0EN BURSTEN AD0INT AD0BUSY AD0WINT AD0LJST AD0CM[1:0]
Type R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Bit Name Function
7AD0EN ADC0 Enable Bit.
0: ADC0 Disabled. ADC0 is in low-power shutdown.
1: ADC0 Enabled. ADC0 is active and ready for data conversions.
6BURSTEN ADC0 Burst Mode Enable Bit.
0: Burst Mode Disabled.
1: Burst Mode Enabled.
5AD0INT ADC0 Conversion Complete Interrupt Flag.
0: ADC0 has not completed a data conversion since AD0INT was last cleared.
1: ADC0 has completed a data conversion.
4AD0BUSY ADC0 Busy Bit. Read:
0: ADC0 conversion is not
in progress.
1: ADC0 conversion is in
progress.
Write:
0: No Effect.
1: Initiates ADC0 Conver-
sion if AD0CM[1:0] = 00b
3AD0WINT ADC0 Window Compare Interrupt Flag.
This bit must be cleared by software
0: ADC0 Window Comparison Data match has not occurred since this flag was last
cleared.
1: ADC0 Window Comparison Data match has occurred.
2AD0LJST ADC0 Left Justify Select Bit.
0: Data in ADC0H:ADC0L registers is right-justified
1: Data in ADC0H:ADC0L registers is left-justified. This option should not be used
with a repeat count greater than 1 (when AD0RPT[1:0] is 01b, 10b, or 11b).
1:0 AD0CM[1:0] ADC0 Start of Conversion Mode Select.
00: ADC0 start-of-conversion source is write of 1 to AD0BUSY.
01: ADC0 start-of-conversion source is overflow of Timer 1.
10: ADC0 start-of-conversion source is rising edge of external CNVSTR.
11: ADC0 start-of-conversion source is overflow of Timer 2.
rT , . SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 61
SFR Address = 0xBA; SFR Page = 0x00
6.4. Programmable Window Detector
The ADC Programmable Window Detector continuously compares the ADC0 output registers to user-pro-
grammed limits, and notifies the system when a desired condition is detected. This is especially effective in
an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system
response times. The window detector interrupt flag (AD0WINT in register ADC0CN) can also be used in
polled mode. The ADC0 Greater-Than (ADC0GTH, ADC0GTL) and Less-Than (ADC0LTH, ADC0LTL)
registers hold the comparison values. The window detector flag can be programmed to indicate when mea-
sured data is inside or outside of the user-programmed limits, depending on the contents of the ADC0
Less-Than and ADC0 Greater-Than registers.
SFR Definition 6.8. ADC0TK: ADC0 Tracking Mode Select
Bit76543210
Name AD0PWR[3:0] AD0TM[1:0] AD0TK[1:0]
Type R/W R/W R/W
Reset 11111111
Bit Name Function
7:4 AD0PWR[3:0] ADC0 Burst Power-up Time.
For BURSTEN = 0: ADC0 Power state controlled by AD0EN
For BURSTEN = 1, AD0EN = 1: ADC0 remains enabled and does not enter the
very low power state
For BURSTEN = 1, AD0EN = 0: ADC0 enters the very low power state and is
enabled after each convert start signal. The Power-up time is programmed accord-
ing the following equation:
or
3:2 AD0TM[1:0] ADC0 Tracking Mode Enable Select Bits.
00: Reserved.
01: ADC0 is configured to Post-Tracking Mode.
10: ADC0 is configured to Pre-Tracking Mode.
11: ADC0 is configured to Dual Tracking Mode.
1:0 AD0TK[1:0] ADC0 Post-Track Time.
00: Post-Tracking time is equal to 2 SAR clock cycles + 2 FCLK cycles.
01: Post-Tracking time is equal to 4 SAR clock cycles + 2 FCLK cycles.
10: Post-Tracking time is equal to 8 SAR clock cycles + 2 FCLK cycles.
11: Post-Tracking time is equal to 16 SAR clock cycles + 2 FCLK cycles.
AD0PWR Tstartup
200ns
------------------------ 1=
Tstartup AD0PWR 1+()200ns=
, . SILIEUN LABS
C8051F55x/56x/57x
62 Rev. 1.2
SFR Address = 0xC4; SFR Page = 0x00
SFR Address = 0xC3; SFR Page = 0x00
SFR Definition 6.9. ADC0GTH: ADC0 Greater-Than Data High Byte
Bit76543210
Name ADC0GTH[7:0]
Type R/W
Reset 11111111
Bit Name Function
7:0 ADC0GTH[7:0] ADC0 Greater-Than Data Word High-Order Bits.
SFR Definition 6.10. ADC0GTL: ADC0 Greater-Than Data Low Byte
Bit76543210
Name ADC0GTL[7:0]
Type R/W
Reset 11111111
Bit Name Function
7:0 ADC0GTL[7:0] ADC0 Greater-Than Data Word Low-Order Bits.
, . SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 63
SFR Address = 0xC6; SFR Page = 0x00
SFR Address = 0xC5; SFR Page = 0x00
6.4.1. Window Detector In Single-Ended Mode
Figure 6.6 shows two example window comparisons for right-justified data with
ADC0LTH:ADC0LTL = 0x0200 (512d) and ADC0GTH:ADC0GTL = 0x0100 (256d). The input voltage can
range from 0 to VREF x (4095/4096) with respect to GND, and is represented by a 12-bit unsigned integer
value. The repeat count is set to one. In the left example, an AD0WINT interrupt will be generated if the
ADC0 conversion word (ADC0H:ADC0L) is within the range defined by ADC0GTH:ADC0GTL and
ADC0LTH:ADC0LTL (if 0x0100 < ADC0H:ADC0L < 0x0200). In the right example, and AD0WINT interrupt
will be generated if the ADC0 conversion word is outside of the range defined by the ADC0GT and
ADC0LT registers (if ADC0H:ADC0L < 0x0100 or ADC0H:ADC0L > 0x0200). Figure 6.7 shows an exam-
ple using left-justified data with the same comparison values.
SFR Definition 6.11. ADC0LTH: ADC0 Less-Than Data High Byte
Bit76543210
Name ADC0LTH[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 ADC0LTH[7:0] ADC0 Less-Than Data Word High-Order Bits.
SFR Definition 6.12. ADC0LTL: ADC0 Less-Than Data Low Byte
Bit76543210
Name ADC0LTL[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 ADC0LTL[7:0] ADC0 Less-Than Data Word Low-Order Bits.
.P» i a F :H ‘ i}— ‘ SSSSSSSSSSS
C8051F55x/56x/57x
64 Rev. 1.2
Figure 6.6. ADC Window Compare Example: Right-Justified Data
Figure 6.7. ADC Window Compare Example: Left-Justified Data
0x0FFF
0x0201
0x0200
0x01FF
0x0101
0x0100
0x00FF
0x0000
0
Input Voltage
(Px.x - GND)
VREF x (4095/4096)
VREF x (512/4096)
VREF x (256/4096)
AD0WINT=1
AD0WINT
not affected
AD0WINT
not affected
ADC0LTH:ADC0LTL
ADC0GTH:ADC0GTL
0x0FFF
0x0201
0x0200
0x01FF
0x0101
0x0100
0x00FF
0x0000
0
Input Voltage
(Px.x - GND)
VREF x (1023/
1024)
VREF x (512/4096)
VREF x (256/4096)
AD0WINT
not affected
AD0WINT=1
AD0WINT=1
ADC0H:ADC0L ADC0H:ADC0L
ADC0GTH:ADC0GTL
ADC0LTH:ADC0LTL
0xFFF0
0x2010
0x2000
0x1FF0
0x1010
0x1000
0x0FF0
0x0000
0
Input Voltage
(Px.x - GND)
VREF x (4095/4096)
VREF x (512/4096)
VREF x (256/4096)
AD0WINT=1
AD0WINT
not affected
AD0WINT
not affected
ADC0LTH:ADC0LTL
ADC0GTH:ADC0GTL
0xFFF0
0x2010
0x2000
0x1FF0
0x1010
0x1000
0x0FF0
0x0000
0
Input Voltage
(Px.x - GND)
VREF x (4095/4096)
VREF x (512/4096)
VREF x (256/4096)
AD0WINT
not affected
AD0WINT=1
AD0WINT=1
ADC0H:ADC0L ADC0H:ADC0L
ADC0LTH:ADC0LTL
ADC0GTH:ADC0GTL
, . SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 65
6.5. ADC0 Analog Multiplexer
ADC0 includes an analog multiplexer to enable multiple analog input sources. Any of the following may be
selected as an input: P0.0P3.7, the on-chip temperature sensor, the core power supply (VDD), or ground
(GND). ADC0 is single-ended and all signals measured are with respect to GND. The ADC0 input
channels are selected using the ADC0MX register as described in SFR Definition 6.13.
Figure 6.8. ADC0 Multiplexer Block Diagram
Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be config-
ured as analog inputs, and should be skipped by the Digital Crossbar. To configure a Port pin for analog
input, set to 0 the corresponding bit in register PnMDIN. To force the Crossbar to skip a Port pin, set to 1
the corresponding bit in register PnSKIP. See Section “19. Port Input/Output” on page 169 for more Port
I/O configuration details.
ADC0
Temp
Sensor
AMUX
VDD
ADC0MX
ADC0MX5
ADC0MX4
ADC0MX3
ADC0MX2
ADC0MX1
ADC0MX0
P0.0
P2.2-P2.7, P3.0 available as
inputs on 40-pin and 32-pin
packages
P3.1-P3.7 available as inputs on
48-pin and 40-pin packages
GND
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
P3.7
, . SILIEUN LABS
C8051F55x/56x/57x
66 Rev. 1.2
SFR Address = 0xBB; SFR Page = 0x00;
SFR Definition 6.13. ADC0MX: ADC0 Channel Select
Bit76543210
Name ADC0MX[5:0]
Type R R R/W
Reset 00111111
Bit Name Function
7:6 Unused Read = 00b; Write = Don’t Care.
5:0 AMX0P[5:0] AMUX0 Positive Input Selection.
000000: P0.0
000001: P0.1
000010: P0.2
000011: P0.3
000100: P0.4
000101: P0.5
000110: P0.6
000111: P0.7
001000: P1.0
001001: P1.1
001010: P1.2
001011: P1.3
001100: P1.4
001101: P1.5
001110: P1.6
001111: P1.7
010000: P2.0
010001: P2.1
010010: P2.2 (Only available on 40-pin and 32-pin package devices)
010011: P2.3 (Only available on 40-pin and 32-pin package devices)
010100: P2.4 (Only available on 40-pin and 32-pin package devices)
010101: P2.5 (Only available on 40-pin and 32-pin package devices)
010110: P2.6 (Only available on 40-pin and 32-pin package devices)
010111: P2.7 (Only available on 40-pin and 32-pin package devices)
011000: P3.0 (Only available on 40-pin and 32-pin package devices)
011001: P3.1 (Only available on 40-pin package devices)
011010: P3.2 (Only available on 40-pin package devices)
011011: P3.3 (Only available on 40-pin package devices)
011100: P3.4 (Only available on 40-pin package devices)
011101: P3.5 (Only available on 40-pin package devices)
011110: P3.6 (Only available on 40-pin package devices)
011111: P3.7 (Only available on 40-pin package devices)
100000–101111: Reserved
110000: Temp Sensor
110001: VDD
110010111111: GND
Temp; = (VTEMP - Offset) / Slope _A Slope (V/deg c ‘ <— oh‘set="" (v="" at="" 0="" celsius)="" 7="" .="" silieun="" labs="">
C8051F55x/56x/57x
Rev. 1.2 67
6.6. Temperature Sensor
An on-chip temperature sensor is included on the C8051F55x/56x/57x devices which can be directly
accessed via the ADC multiplexer in single-ended configuration. To use the ADC to measure the tempera-
ture sensor, the ADC multiplexer channel should be configured to connect to the temperature sensor. The
temperature sensor transfer function is shown in Figure 6.9. The output voltage (VTEMP) is the positive
ADC input is selected by bits AD0MX[4:0] in register ADC0MX. The TEMPE bit in register REF0CN
enables/disables the temperature sensor, as described in SFR Definition 7.1. While disabled, the tempera-
ture sensor defaults to a high impedance state and any ADC measurements performed on the sensor will
result in meaningless data. Refer to Table 5.10 for the slope and offset parameters of the temperature sen-
sor.
Figure 6.9. Temperature Sensor Transfer Function
Temperature
Voltage
VTEMP = (Slope x TempC) + Offset
Offset (V at 0 Celsius)
Slope (V / deg C)
TempC = (VTEMP - Offset) / Slope
SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 68
7. Voltage Reference
The Voltage reference multiplexer on the C8051F55x/56x/57x devices is configurable to use an externally
connected voltage reference, the on-chip reference voltage generator routed to the VREF pin, or the VDD
power supply voltage (see Figure 7.1). The REFSL bit in the Reference Control register (REF0CN, SFR
Definition 7.1) selects the reference source for the ADC. For an external source or the on-chip reference,
REFSL should be set to 0 to select the VREF pin. To use VDD as the reference source, REFSL should be
set to 1.
The BIASE bit enables the internal voltage bias generator, which is used by the ADC, Temperature Sensor,
and internal oscillator. This bias is automatically enabled when any peripheral which requires it is enabled,
and it does not need to be enabled manually. The bias generator may be enabled manually by writing a 1
to the BIASE bit in register REF0CN. The electrical specifications for the voltage reference circuit are given
in Table 5.11.
The on-chip voltage reference circuit consists of a temperature stable bandgap voltage reference genera-
tor and a gain-of-two output buffer amplifier. The output voltage is selectable between 1.5 V and 2.25 V.
The on-chip voltage reference can be driven on the VREF pin by setting the REFBE bit in register REF0CN
to a 1. The maximum load seen by the VREF pin must be less than 200 µA to GND. Bypass capacitors of
0.1 µF and 4.7 µF are recommended from the VREF pin to GND. If the on-chip reference is not used, the
REFBE bit should be cleared to 0. Electrical specifications for the on-chip voltage reference are given in
Table 5.11.
Important Note about the VREF Pin: When using either an external voltage reference or the on-chip ref-
erence circuitry, the VREF pin should be configured as an analog pin and skipped by the Digital Crossbar.
Refer to Section “19. Port Input/Output” on page 169 for the location of the VREF pin, as well as details of
how to configure the pin in analog mode and to be skipped by the crossbar. If VDD is selected as the volt-
age reference in the REF0CN register and the ADC is enabled in the ADC0CN register, the P0.0/VREF pin
cannot operate as a general purpose I/O pin in open-drain mode. With the above settings, this pin can
operate in push-pull output mode or as an analog input.
Figure 7.1. Voltage Reference Functional Block Diagram
VREF
(to ADC)
To Analog Mux
VDD
VREF
R1
VDD External
Voltage
Reference
Circuit
GND
Temp Sensor
EN
Bias Generator To ADC, Internal
Oscillators
EN
IOSCE
N
0
1
REF0CN
REFSL
TEMPE
BIASE
REFBE
REFBE
Internal
Reference
EN
Recommended Bypass
Capacitors
+
4.7μF0.1μF
, . SILIEUN LABS
C8051F55x/56x/57x
69 Rev. 1.2
SFR Address = 0xD1; SFR Page = 0x00
SFR Definition 7.1. REF0CN: Reference Control
Bit76543210
Name ZTCEN REFLV REFSL TEMPE BIASE REFBE
Type RRRRR/W R/W R/W R/W
Reset 00000000
Bit Name Function
7:6 Unused Read = 00b; Write = don’t care.
5ZTCEN Zero Temperature Coefficient Bias Enable Bit.
This bit must be set to 1b before entering oscillator suspend mode.
0: ZeroTC Bias Generator automatically enabled when required.
1: ZeroTC Bias Generator forced on.
4REFLV Voltage Reference Output Level Select.
This bit selects the output voltage level for the internal voltage reference
0: Internal voltage reference set to 1.5 V.
1: Internal voltage reference set to 2.20 V.
3REFSL Voltage Reference Select.
This bit selects the ADCs voltage reference.
0: VREF pin used as voltage reference.
1: VDD used as voltage reference. If VDD is selected as the voltage reference and the
ADC is enabled in the ADC0CN register, the P0.0/VREF pin cannot operate as a gen-
eral purpose I/O pin in open-drain mode. With the above settings, this pin can operate
in push-pull output mode or as an analog input.
2TEMPE Temperature Sensor Enable Bit.
0: Internal Temperature Sensor off.
1: Internal Temperature Sensor on.
1BIASE Internal Analog Bias Generator Enable Bit.
0: Internal Bias Generator off.
1: Internal Bias Generator on.
0REFBE On-chip Reference Buffer Enable Bit.
0: On-chip Reference Buffer off.
1: On-chip Reference Buffer on. Internal voltage reference driven on the VREF pin.
ML, CPTnMD ‘7 _ : ————— L___J —$ JWHE |— a,/ , . SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 70
8. Comparators
The C8051F55x/56x/57x devices include two on-chip programmable voltage Comparators. A block dia-
gram of the comparators is shown in Figure 8.1, where “n” is the comparator number (0 or 1). The two
Comparators operate identically except that Comparator0 can also be used a reset source. For input
selection details, refer to SFR Definition 8.5 and SFR Definition 8.6.
Each Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0, CP1), or an
asynchronous “raw” output (CP0A, CP1A). The asynchronous signal is available even when the system
clock is not active. This allows the Comparators to operate and generate an output with the device in
STOP mode. When assigned to a Port pin, the Comparator outputs may be configured as open drain or
push-pull (see Section “19.4. Port I/O Initialization” on page 174). Comparator0 may also be used as a
reset source (see Section “16.5. Comparator0 Reset” on page 142).
The Comparator0 inputs are selected in the CPT0MX register (SFR Definition 8.5). The CMX0P1-CMX0P0
bits select the Comparator0 positive input; the CMX0N1-CMX0N0 bits select the Comparator0 negative
input. The Comparator1 inputs are selected in the CPT1MX register (SFR Definition 8.6). The CMX1P1-
CMX1P0 bits select the Comparator1 positive input; the CMX1N1-CMX1N0 bits select the Comparator1
negative input.
Important Note About Comparator Inputs: The Port pins selected as Comparator inputs should be con-
figured as analog inputs in their associated Port configuration register, and configured to be skipped by the
Crossbar (for details on Port configuration, see Section “19.1. Port I/O Modes of Operation” on page 170).
Figure 8.1. Comparator Functional Block Diagram
VIO
Reset
Decision
Tree
+
-
Crossbar
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
(SYNCHRONIZER)
GND
CPn +
CPn -
CPTnMD
CPnRIE
CPnFIE
CPnMD1
CPnMD0
CPn
CPnA
CPn
Interrupt
0
1
0
1
CPnRIF
CPnFIF
0
1
CPnEN
0
1
EA
Comparator
Input Mux
CPTnCN
CPnEN
CPnOUT
CPnRIF
CPnFIF
CPnHYP1
CPnHYP0
CPnHYN1
CPnHYN0
,HL , . SILIEUN LABS
C8051F55x/56x/57x
71 Rev. 1.2
Comparator outputs can be polled in software, used as an interrupt source, and/or routed to a Port pin.
When routed to a Port pin, Comparator outputs are available asynchronous or synchronous to the system
clock; the asynchronous output is available even in STOP mode (with no system clock active). When dis-
abled, the Comparator output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic low state,
and the power supply to the comparator is turned off. See Section “19.3. Priority Crossbar Decoder” on
page 172 for details on configuring Comparator outputs via the digital Crossbar. Comparator inputs can be
externally driven from –0.25 V to (VDD) + 0.25 V without damage or upset. The complete Comparator elec-
trical specifications are given in Table 5.12.
The Comparator response time may be configured in software via the CPTnMD registers (see SFR Defini-
tion 8.2). Selecting a longer response time reduces the Comparator supply current. See Table 5.12 for
complete timing and supply current requirements.
Figure 8.2. Comparator Hysteresis Plot
Comparator hysteresis is software-programmable via its Comparator Control register CPTnCN.
The amount of negative hysteresis voltage is determined by the settings of the CPnHYN bits. As shown in
Figure 8.2, various levels of negative hysteresis can be programmed, or negative hysteresis can be dis-
abled. In a similar way, the amount of positive hysteresis is determined by the setting the CPnHYP bits.
Comparator interrupts can be generated on both rising-edge and falling-edge output transitions. (For Inter-
rupt enable and priority control, see “13. Interrupts” .) The CPnFIF flag is set to 1 upon a Comparator fall-
ing-edge, and the CPnRIF flag is set to 1 upon the Comparator rising-edge. Once set, these bits remain
set until cleared by software. The output state of the Comparator can be obtained at any time by reading
the CPnOUT bit. The Comparator is enabled by setting the CPnEN bit to 1, and is disabled by clearing this
bit to 0.
Positive Hysteresis Voltage
(Programmed with CPnHYP Bits)
Negative Hysteresis Voltage
(Programmed by CPnHYN Bits)
VIN-
VIN+
INPUTS
CIRCUIT CONFIGURATION
+
_
CPn+
CPn- CPn
VIN+
VIN-
OUT
VOH
Positive Hysteresis
Disabled Maximum
Positive Hysteresis
Negative Hysteresis
Disabled Maximum
Negative Hysteresis
OUTPUT
VOL
, . SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 72
Note that false rising edges and falling edges can be detected when the comparator is first powered on or
if changes are made to the hysteresis or response time control bits. Therefore, it is recommended that the
rising-edge and falling-edge flags be explicitly cleared to logic 0 a short time after the comparator is
enabled or its mode bits have been changed.
SFR Address = 0x9A; SFR Page = 0x00
SFR Definition 8.1. CPT0CN: Comparator0 Control
Bit76543210
Name CP0EN CP0OUT CP0RIF CP0FIF CP0HYP[1:0] CP0HYN[1:0]
Type R/W RR/W R/W R/W R/W
Reset 00000000
Bit Name Function
7CP0EN Comparator0 Enable Bit.
0: Comparator0 Disabled.
1: Comparator0 Enabled.
6CP0OUT Comparator0 Output State Flag.
0: Voltage on CP0+ < CP0.
1: Voltage on CP0+ > CP0.
5CP0RIF Comparator0 Rising-Edge Flag. Must be cleared by software.
0: No Comparator0 Rising Edge has occurred since this flag was last cleared.
1: Comparator0 Rising Edge has occurred.
4CP0FIF Comparator0 Falling-Edge Flag. Must be cleared by software.
0: No Comparator0 Falling-Edge has occurred since this flag was last cleared.
1: Comparator0 Falling-Edge has occurred.
3:2 CP0HYP[1:0] Comparator0 Positive Hysteresis Control Bits.
00: Positive Hysteresis Disabled.
01: Positive Hysteresis = 5 mV.
10: Positive Hysteresis = 10 mV.
11: Positive Hysteresis = 20 mV.
1:0 CP0HYN[1:0] Comparator0 Negative Hysteresis Control Bits.
00: Negative Hysteresis Disabled.
01: Negative Hysteresis = 5 mV.
10: Negative Hysteresis = 10 mV.
11: Negative Hysteresis = 20 mV.
, . SILIEUN LABS
C8051F55x/56x/57x
73 Rev. 1.2
SFR Address = 0x9B; SFR Page = 0x00
SFR Definition 8.2. CPT0MD: Comparator0 Mode Selection
Bit76543210
Name CP0RIE CP0FIE CP0MD[1:0]
Type R R R/W R/W R R R/W
Reset 00000010
Bit Name Function
7:6 Unused Read = 00b, Write = Don’t Care.
5CP0RIE Comparator0 Rising-Edge Interrupt Enable.
0: Comparator0 Rising-edge interrupt disabled.
1: Comparator0 Rising-edge interrupt enabled.
4CP0FIE Comparator0 Falling-Edge Interrupt Enable.
0: Comparator0 Falling-edge interrupt disabled.
1: Comparator0 Falling-edge interrupt enabled.
3:2 Unused Read = 00b, Write = don’t care.
1:0 CP0MD[1:0] Comparator0 Mode Select.
These bits affect the response time and power consumption for Comparator0.
00: Mode 0 (Fastest Response Time, Highest Power Consumption)
01: Mode 1
10: Mode 2
11: Mode 3 (Slowest Response Time, Lowest Power Consumption)
, . SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 74
SFR Address = 0x9D; SFR Page = 0x00
SFR Definition 8.3. CPT1CN: Comparator1 Control
Bit76543210
Name CP1EN CP1OUT CP1RIF CP1FIF CP1HYP[1:0] CP1HYN[1:0]
Type R/W RR/W R/W R/W R/W
Reset 00000000
Bit Name Function
7CP1EN Comparator1 Enable Bit.
0: Comparator1 Disabled.
1: Comparator1 Enabled.
6CP1OUT Comparator1 Output State Flag.
0: Voltage on CP1+ < CP1–.
1: Voltage on CP1+ > CP1–.
5CP1RIF Comparator1 Rising-Edge Flag. Must be cleared by software.
0: No Comparator1 Rising Edge has occurred since this flag was last cleared.
1: Comparator1 Rising Edge has occurred.
4CP1FIF Comparator1 Falling-Edge Flag. Must be cleared by software.
0: No Comparator1 Falling-Edge has occurred since this flag was last cleared.
1: Comparator1 Falling-Edge has occurred.
3:2 CP1HYP[1:0] Comparator1 Positive Hysteresis Control Bits.
00: Positive Hysteresis Disabled.
01: Positive Hysteresis = 5 mV.
10: Positive Hysteresis = 10 mV.
11: Positive Hysteresis = 20 mV.
1:0 CP1HYN[1:0] Comparator1 Negative Hysteresis Control Bits.
00: Negative Hysteresis Disabled.
01: Negative Hysteresis = 5 mV.
10: Negative Hysteresis = 10 mV.
11: Negative Hysteresis = 20 mV.
, . SILIEUN LABS
C8051F55x/56x/57x
75 Rev. 1.2
SFR Address = 0x9E; SFR Page = 0x00
SFR Definition 8.4. CPT1MD: Comparator1 Mode Selection
Bit76543210
Name CP1RIE CP1FIE CP1MD[1:0]
Type R R R/W R/W R R R/W
Reset 00000010
Bit Name Function
7:6 Unused Read = 00b, Write = Don’t Care.
5CP1RIE Comparator1 Rising-Edge Interrupt Enable.
0: Comparator1 Rising-edge interrupt disabled.
1: Comparator1 Rising-edge interrupt enabled.
4CP1FIE Comparator1 Falling-Edge Interrupt Enable.
0: Comparator1 Falling-edge interrupt disabled.
1: Comparator1 Falling-edge interrupt enabled.
3:2 Unused Read = 00b, Write = don’t care.
1:0 CP1MD[1:0] Comparator1 Mode Select.
These bits affect the response time and power consumption for Comparator1.
00: Mode 0 (Fastest Response Time, Highest Power Consumption)
01: Mode 1
10: Mode 2
11: Mode 3 (Slowest Response Time, Lowest Power Consumption)
, . SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 76
8.1. Comparator Multiplexer
C8051F55x/56x/57x devices include an analog input multiplexer for each of the comparators to connect
Port I/O pins to the comparator inputs. The Comparator0 inputs are selected in the CPT0MX register (SFR
Definition 8.5). The CMX0P3CMX0P0 bits select the Comparator0 positive input; the CMX0N3–CMX0N0
bits select the Comparator0 negative input. Similarly, the Comparator1 inputs are selected in the CPT1MX
register using the CMX1P3-CMX1P0 bits and CMX1N3–CMX1N0 bits. The same pins are available to both
multiplexers at the same time and can be used by both comparators simultaneously.
Important Note About Comparator Inputs: The Port pins selected as comparator inputs should be con-
figured as analog inputs in their associated Port configuration register, and configured to be skipped by the
Crossbar (for details on Port configuration, see Section “19.6. Special Function Registers for Accessing
and Configuring Port I/O” on page 183).
Figure 8.3. Comparator Input Multiplexer Block Diagram
VDD
+
-
GND
CPn +
CPn -
P0.1
P0.3
P0.5
P0.7
CPTnMX
CMXnN3
CMXnN2
CMXnN1
CMXnN0
CMXnP3
CMXnP2
CMXnP1
CMXnP0
P1.1
P1.3
P1.5
P1.7
P2.1
P2.3
P2.5
P2.7
P0.0
P0.2
P0.4
P0.6
P1.0
P1.2
P1.4
P1.6
P2.0
P2.2
P2.4
P2.6
, . SILIEUN LABS
C8051F55x/56x/57x
77 Rev. 1.2
SFR Address = 0x9C; SFR Page = 0x00
SFR Definition 8.5. CPT0MX: Comparator0 MUX Selection
Bit76543210
Name CMX0N[3:0] CMX0P[3:0]
Type R/W R/W
Reset 01110111
Bit Name Function
7:4 CMX0N[3:0] Comparator0 Negative Input MUX Selection.
0000: P0.1
0001: P0.3
0010: P0.5
0011: P0.7
0100: P1.1
0101: P1.3
0110: P1.5
0111: P1.7
1000: P2.1
1001: P2.3 (only available on 40-pin and 32-pin devices)
1010: P2.5 (only available on 40-pin and 32-pin devices)
1011: P2.7 (only available on 40-pin and 32-pin devices)
1100–1111: None
3:0 CMX0P[3:0] Comparator0 Positive Input MUX Selection.
0000: P0.0
0001: P0.2
0010: P0.4
0011: P0.6
0100: P1.0
0101: P1.2
0110: P1.4
0111: P1.6
1000: P2.0
1001: P2.2 (only available on 40-pin and 32-pin devices)
1010: P2.4 (only available on 40-pin and 32-pin devices)
1011: P2.6 (only available on 40-pin and 32-pin devices)
1100–1111: None
, . SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 78
SFR Address = 0x9F; SFR Page = 0x00
SFR Definition 8.6. CPT1MX: Comparator1 MUX Selection
Bit76543210
Name CMX1N[3:0] CMX1P[3:0]
Type R/W R/W
Reset 01110111
Bit Name Function
7:4 CMX1N[3:0] Comparator1 Negative Input MUX Selection.
0000: P0.1
0001: P0.3
0010: P0.5
0011: P0.7
0100: P1.1
0101: P1.3
0110: P1.5
0111: P1.7
1000: P2.1
1001: P2.3 (only available on 40-pin and 32-pin devices)
1010: P2.5 (only available on 40-pin and 32-pin devices)
1011: P2.7 (only available on 40-pin and 32-pin devices)
1100–1111: None
3:0 CMX1P[3:0] Comparator1 Positive Input MUX Selection.
0000: P0.0
0001: P0.2
0010: P0.4
0011: P0.6
0100: P1.0
0101: P1.2
0110: P1.4
0111: P1.6
1000: P2.0
1001: P2.2 (only available on 40-pin and 32-pin devices)
1010: P2.4 (only available on 40-pin and 32-pin devices)
1011: P2.6 (only available on 40-pin and 32-pin devices)
1100–1111: None
SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 79
9. Voltage Regulator (REG0)
C8051F55x/56x/57x devices include an on-chip low dropout voltage regulator (REG0). The input to REG0
at the VREGIN pin can be as high as 5.25 V. The output can be selected by software to 2.1 V or 2.6 V. When
enabled, the output of REG0 appears on the VDD pin, powers the microcontroller core, and can be used to
power external devices. On reset, REG0 is enabled and can be disabled by software.
The Voltage regulator can generate an interrupt (if enabled by EREG0, EIE2.0) that is triggered whenever
the VREGIN input voltage drops below the dropout threshold voltage. This dropout interrupt has no pending
flag and the recommended procedure to use it is as follows:
1. Wait enough time to ensure the VREGIN input voltage is stable
2. Enable the dropout interrupt (EREG0, EIE2.0) and select the proper priority (PREG0, EIP2.0)
3. If triggered, inside the interrupt disable it (clear EREG0, EIE2.0), execute all procedures necessary to
protect your application (put it in a safe mode and leave the interrupt now disabled.
4. In the main application, now running in the safe mode, regularly checks the DROPOUT bit
(REG0CN.0). Once it is cleared by the regulator hardware the application can enable the interrupt
again (EREG0, EIE1.6) and return to the normal mode operation.
The input (VREGIN) and output (VDD) of the voltage regulator should both be bypassed with a large capaci-
tor (4.7 µF + 0.1 µF) to ground as shown in Figure 9.1. This capacitor will eliminate power spikes and pro-
vide any immediate power required by the microcontroller. The settling time associated with the voltage
regulator is shown in Table 5.8 on page 43.
Note: The output of the internal voltage regulator is calibrated by the MCU immediately after any reset
event. The output of the un-calibrated internal regulator could be below the high threshold setting of
the VDD Monitor. If this is the case and the VDD Monitor is set to the high threshold setting and if the
MCU receives a non-power on reset (POR), the MCU will remain in reset until a POR occurs (i.e.,
VDD Monitor will keep the device in reset). A POR will force the VDD Monitor to the low threshold
setting which is guaranteed to be below the un-calibrated output of the internal regulator. The device
will then exit reset and resume normal operation. It is for this reason Silicon Labs strongly
recommends that the VDD Monitor is always left in the low threshold setting (i.e. default value upon
POR).
Figure 9.1. External Capacitors for Voltage Regulator Input/Output—
Regulator Enabled
VDD
VDD
REG0
4.7 µF
4.7 µF .1 µF
.1 µF
VREGIN
%>7‘ , . SILIEUN LABS
C8051F55x/56x/57x
80 Rev. 1.2
If the internal voltage regulator is not used, the VREGIN input should be tied to VDD, as shown in Figure 9.2.
Figure 9.2. External Capacitors for Voltage Regulator Input/Output—Regulator Disabled
SFR Address = 0xC9; SFR Page = 0x00
SFR Definition 9.1. REG0CN: Regulator Control
Bit 7 6 5 4 3 2 1 0
Name REGDIS Reserved REG0MD DROPOUT
Type R/W R/W RR/W R R R R
Reset 0 1 0 1 0 0 0 0
Bit Name Function
7REGDIS Voltage Regulator Disable Bit.
0: Voltage Regulator Enabled
1: Voltage Regulator Disabled
6 Reserved Read = 1b; Must Write 1b.
5Unused Read = 0b; Write = Don’t Care.
4REG0MD Voltage Regulator Mode Select Bit.
0: Voltage Regulator Output is 2.1 V.
1: Voltage Regulator Output is 2.6 V.
3:1 Unused Read = 000b. Write = Don’t Care.
0DROPOUT Voltage Regulator Dropout Indicator.
0: Voltage Regulator is not in dropout.
1: Voltage Regulator is in or near dropout.
VREGIN
VDD
VDD
4.7 µF .1 µF
, . SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 81
10. CIP-51 Microcontroller
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft-
ware. The MCU family has a superset of all the peripherals included with a standard 8051. The CIP-51
also includes on-chip debug hardware (see description in Section 27), and interfaces directly with the ana-
log and digital subsystems providing a complete data acquisition or control-system solution in a single inte-
grated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see Figure 10.1 for a block diagram).
The CIP-51 includes the following features:
Fully Compatible with MCS-51 Instruction Set
50 MIPS Peak Throughput with 50 MHz Clock
0 to 50 MHz Clock Frequency
Extended Interrupt Handler
Reset Input
Power Management Modes
On-chip Debug Logic
Program and Data Memory Security
10.1. Performance
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan-
dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51
core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more
than eight system clock cycles.
g} Lg, H 4b m 4.: | H: ‘7 H: 4" —>I: « ': a: K: ‘7 la 1% w %' |— , . SILIEUN LABS
C8051F55x/56x/57x
82 Rev. 1.2
Figure 10.1. CIP-51 Block Diagram
With the CIP-51's maximum system clock at 50 MHz, it has a peak throughput of 50 MIPS. The CIP-51 has
a total of 109 instructions. The table below shows the total number of instructions that require each execu-
tion time.
Programming and Debugging Support
In-system programming of the Flash program memory and communication with on-chip debug support
logic is accomplished via the Silicon Labs 2-Wire Development Interface (C2).
The on-chip debug support logic facilitates full speed in-circuit debugging, allowing the setting of hardware
breakpoints, starting, stopping and single stepping through program execution (including interrupt service
routines), examination of the program's call stack, and reading/writing the contents of registers and mem-
ory. This method of on-chip debugging is completely non-intrusive, requiring no RAM, Stack, timers, or
other on-chip resources. C2 details can be found in Section “27. C2 Interface” on page 300.
The CIP-51 is supported by development tools from Silicon Labs and third party vendors. Silicon Labs pro-
vides an integrated development environment (IDE) including editor, debugger and programmer. The IDE's
debugger and programmer interface to the CIP-51 via the C2 interface to provide fast and efficient in-sys-
tem device programming and debugging. Third party macro assemblers and C compilers are also avail-
able.
Clocks to Execute 1 2 2/3 33/4 44/5 5 8
Number of Instructions 26 50 514 7 3 1 2 1
DATA BUS
TMP1 TMP2
PRGM. ADDRESS REG.
PC INCREMENTER
ALU
PSW
DATA BUS
DATA BUS
MEMORY
INTERFACE
MEM_ADDRESS
D8
PIPELINE
BUFFER
DATA POINTER
INTERRUPT
INTERFACE
SYSTEM_IRQs
EMULATION_IRQ
MEM_CONTROL
CONTROL
LOGIC
A16
PROGRAM COUNTER (PC)
STOP
CLOCK
RESET
IDLE POWER CONTROL
REGISTER
DATA BUS
SFR
BUS
INTERFACE
SFR_ADDRESS
SFR_CONTROL
SFR_WRITE_DATA
SFR_READ_DATA
D8
D8
B REGISTER
D8
D8
ACCUMULATOR
D8
D8
D8
D8
D8
D8
D8
D8
MEM_WRITE_DATA
MEM_READ_DATA
D8
SRAM
ADDRESS
REGISTER SRAM
D8
STACK POINTER
D8
, . SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 83
10.2. Instruction Set
The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruc-
tion set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51
instructions are the binary and functional equivalent of their MCS-51™ counterparts, including opcodes,
addressing modes and effect on PSW flags. However, instruction timing is different than that of the stan-
dard 8051.
10.2.1. Instruction and CPU Timing
In many 8051 implementations, a distinction is made between machine cycles and clock cycles, with
machine cycles varying from 2 to 12 clock cycles in length. However, the CIP-51 implementation is based
solely on clock cycle timing. All instruction timings are specified in terms of clock cycles.
Due to the pipelined architecture of the CIP-51, most instructions execute in the same number of clock
cycles as there are program bytes in the instruction. Conditional branch instructions take one less clock
cycle to complete when the branch is not taken as opposed to when the branch is taken. Table 10.1 is the
CIP-51 Instruction Set Summary, which includes the mnemonic, number of bytes, and number of clock
cycles for each instruction.
, ‘ SILIEIJN LABS
C8051F55x/56x/57x
84 Rev. 1.2
Table 10.1. CIP-51 Instruction Set Summary
Mnemonic Description Bytes Clock
Cycles
Arithmetic Operations
ADD A, Rn Add register to A 1 1
ADD A, direct Add direct byte to A 2 2
ADD A, @Ri Add indirect RAM to A 1 2
ADD A, #data Add immediate to A 2 2
ADDC A, Rn Add register to A with carry 1 1
ADDC A, direct Add direct byte to A with carry 2 2
ADDC A, @Ri Add indirect RAM to A with carry 1 2
ADDC A, #data Add immediate to A with carry 2 2
SUBB A, Rn Subtract register from A with borrow 1 1
SUBB A, direct Subtract direct byte from A with borrow 2 2
SUBB A, @Ri Subtract indirect RAM from A with borrow 1 2
SUBB A, #data Subtract immediate from A with borrow 2 2
INC A Increment A 1 1
INC Rn Increment register 1 1
INC direct Increment direct byte 2 2
INC @Ri Increment indirect RAM 1 2
DEC A Decrement A 1 1
DEC Rn Decrement register 1 1
DEC direct Decrement direct byte 2 2
DEC @Ri Decrement indirect RAM 1 2
INC DPTR Increment Data Pointer 1 1
MUL AB Multiply A and B 1 4
DIV AB Divide A by B 1 8
DA A Decimal adjust A 1 1
Logical Operations
ANL A, Rn AND Register to A 1 1
ANL A, direct AND direct byte to A 2 2
ANL A, @Ri AND indirect RAM to A 1 2
ANL A, #data AND immediate to A 2 2
ANL direct, A AND A to direct byte 2 2
ANL direct, #data AND immediate to direct byte 3 3
ORL A, Rn OR Register to A 1 1
ORL A, direct OR direct byte to A 2 2
ORL A, @Ri OR indirect RAM to A 12
ORL A, #data OR immediate to A 2 2
ORL direct, A OR A to direct byte 2 2
ORL direct, #data OR immediate to direct byte 3 3
XRL A, Rn Exclusive-OR Register to A 1 1
XRL A, direct Exclusive-OR direct byte to A 2 2
XRL A, @Ri Exclusive-OR indirect RAM to A 1 2
Note: Certain instructions take a variable number of clock cycles to execute depending on instruction alignment and
the FLRT setting (SFR Definition 14.3).
, . SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 85
XRL A, #data Exclusive-OR immediate to A 2 2
XRL direct, A Exclusive-OR A to direct byte 2 2
XRL direct, #data Exclusive-OR immediate to direct byte 3 3
CLR A Clear A 1 1
CPL A Complement A 1 2
RL A Rotate A left 1 1
RLC A Rotate A left through Carry 1 1
RR A Rotate A right 1 1
RRC A Rotate A right through Carry 1 1
SWAP A Swap nibbles of A 1 1
Data Transfer
MOV A, Rn Move Register to A 1 1
MOV A, direct Move direct byte to A 2 2
MOV A, @Ri Move indirect RAM to A 1 2
MOV A, #data Move immediate to A 2 2
MOV Rn, A Move A to Register 1 1
MOV Rn, direct Move direct byte to Register 2 2
MOV Rn, #data Move immediate to Register 2 2
MOV direct, A Move A to direct byte 2 2
MOV direct, Rn Move Register to direct byte 2 2
MOV direct, direct Move direct byte to direct byte 3 3
MOV direct, @Ri Move indirect RAM to direct byte 2 2
MOV direct, #data Move immediate to direct byte 3 3
MOV @Ri, A Move A to indirect RAM 1 2
MOV @Ri, direct Move direct byte to indirect RAM 2 2
MOV @Ri, #data Move immediate to indirect RAM 2 2
MOV DPTR, #data16 Load DPTR with 16-bit constant 3 3
MOVC A, @A+DPTR Move code byte relative DPTR to A 14-7*
MOVC A, @A+PC Move code byte relative PC to A 1 3
MOVX A, @Ri Move external data (8-bit address) to A 1 3
MOVX @Ri, A Move A to external data (8-bit address) 1 3
MOVX A, @DPTR Move external data (16-bit address) to A 1 3
MOVX @DPTR, A Move A to external data (16-bit address) 1 3
PUSH direct Push direct byte onto stack 2 2
POP direct Pop direct byte from stack 2 2
XCH A, Rn Exchange Register with A 1 1
XCH A, direct Exchange direct byte with A 2 2
XCH A, @Ri Exchange indirect RAM with A 1 2
XCHD A, @Ri Exchange low nibble of indirect RAM with A 1 2
Boolean Manipulation
CLR C Clear Carry 1 1
CLR bit Clear direct bit 2 2
Table 10.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic Description Bytes Clock
Cycles
Note: Certain instructions take a variable number of clock cycles to execute depending on instruction alignment and
the FLRT setting (SFR Definition 14.3).
, ‘ SILIEIJN LABS
C8051F55x/56x/57x
86 Rev. 1.2
SETB C Set Carry 1 1
SETB bit Set direct bit 2 2
CPL C Complement Carry 1 1
CPL bit Complement direct bit 2 2
ANL C, bit AND direct bit to Carry 2 2
ANL C, /bit AND complement of direct bit to Carry 2 2
ORL C, bit OR direct bit to carry 2 2
ORL C, /bit OR complement of direct bit to Carry 2 2
MOV C, bit Move direct bit to Carry 2 2
MOV bit, C Move Carry to direct bit 2 2
JC rel Jump if Carry is set 22/(4-6)*
JNC rel Jump if Carry is not set 22/(4-6)*
JB bit, rel Jump if direct bit is set 33/(5-7)*
JNB bit, rel Jump if direct bit is not set 33/(5-7)*
JBC bit, rel Jump if direct bit is set and clear bit 33/(5-7)*
Program Branching
ACALL addr11 Absolute subroutine call 24-6*
LCALL addr16 Long subroutine call 35-7*
RET Return from subroutine 16-8*
RETI Return from interrupt 16-8*
AJMP addr11 Absolute jump 24-6*
LJMP addr16 Long jump 35-7*
SJMP rel Short jump (relative address) 24-6*
JMP @A+DPTR Jump indirect relative to DPTR 13-5*
JZ rel Jump if A equals zero 22/(4-6)*
JNZ rel Jump if A does not equal zero 22/(4-6)*
CJNE A, direct, rel Compare direct byte to A and jump if not equal 34/(6-8)*
CJNE A, #data, rel Compare immediate to A and jump if not equal 33/(6-8)*
CJNE Rn, #data, rel Compare immediate to Register and jump if not
equal 33/(5-7)*
CJNE @Ri, #data, rel Compare immediate to indirect and jump if not
equal 34/(6-8)*
DJNZ Rn, rel Decrement Register and jump if not zero 22/(4-6)*
DJNZ direct, rel Decrement direct byte and jump if not zero 33/(5-7)*
NOP No operation 1 1
Table 10.1. CIP-51 Instruction Set Summary (Continued)
Mnemonic Description Bytes Clock
Cycles
Note: Certain instructions take a variable number of clock cycles to execute depending on instruction alignment and
the FLRT setting (SFR Definition 14.3).
, . SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 87
10.3. CIP-51 Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits
should not be set to logic l. Future product versions may use these bits to implement new features in which
case the reset value of the bit will be logic 0, selecting the feature's default state. Detailed descriptions of
the remaining SFRs are included in the sections of the datasheet associated with their corresponding sys-
tem function.
Notes on Registers, Operands and Addressing Modes:
Rn—Register R0–R7 of the currently selected register bank.
@Ri—Data RAM location addressed indirectly through R0 or R1.
rel—8-bit, signed (two’s complement) offset relative to the first byte of the following instruction. Used by
SJMP and all conditional jumps.
direct—8-bit internal data location’s address. This could be a direct-access Data RAM location (0x00–
0x7F) or an SFR (0x80–0xFF).
#data—8-bit constant
#data16—16-bit constant
bit—Direct-accessed bit in Data RAM or SFR
addr11—11-bit destination address used by ACALL and AJMP. The destination must be within the
same 2 kB page of program memory as the first byte of the following instruction.
addr16—16-bit destination address used by LCALL and LJMP. The destination may be anywhere within
the 64 kB program memory space.
There is one unused opcode (0xA5) that performs the same function as NOP.
All mnemonics copyrighted © Intel Corporation 1980.
, ‘ SILIEIJN LABS
C8051F55x/56x/57x
88 Rev. 1.2
SFR Address = 0x82; SFR Page = All Pages
SFR Address = 0x83; SFR Page = All Pages
SFR Definition 10.1. DPL: Data Pointer Low Byte
Bit76543210
Name DPL[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 DPL[7:0] Data Pointer Low.
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indi-
rectly addressed Flash memory or XRAM.
SFR Definition 10.2. DPH: Data Pointer High Byte
Bit76543210
Name DPH[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 DPH[7:0] Data Pointer High.
The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indi-
rectly addressed Flash memory or XRAM.
, . SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 89
SFR Address = 0x81; SFR Page = All Pages
SFR Address = 0xE0; SFR Page = All Pages; Bit-Addressable
SFR Address = 0xF0; SFR Page = All Pages; Bit-Addressable
SFR Definition 10.3. SP: Stack Pointer
Bit76543210
Name SP[7:0]
Type R/W
Reset 00000111
Bit Name Function
7:0 SP[7:0] Stack Pointer.
The Stack Pointer holds the location of the top of the stack. The stack pointer is incre-
mented before every PUSH operation. The SP register defaults to 0x07 after reset.
SFR Definition 10.4. ACC: Accumulator
Bit76543210
Name ACC[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 ACC[7:0] Accumulator.
This register is the accumulator for arithmetic operations.
SFR Definition 10.5. B: B Register
Bit76543210
Name B[7:0]
Type R/W
Reset 00000000
Bit Name Function
7:0 B[7:0] B Register.
This register serves as a second accumulator for certain arithmetic operations.
, . SILIEUN LABS
C8051F55x/56x/57x
90 Rev. 1.2
SFR Address = 0xD0; SFR Page = All Pages; Bit-Addressable
SFR Definition 10.6. PSW: Program Status Word
Bit76543210
Name CY AC F0 RS[1:0] OV F1 PARITY
Type R/W R/W R/W R/W R/W R/W R
Reset 00000000
Bit Name Function
7CY Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a bor-
row (subtraction). It is cleared to logic 0 by all other arithmetic operations.
6AC Auxiliary Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a
borrow from (subtraction) the high order nibble. It is cleared to logic 0 by all other arith-
metic operations.
5F0 User Flag 0.
This is a bit-addressable, general purpose flag for use under software control.
4:3 RS[1:0] Register Bank Select.
These bits select which register bank is used during register accesses.
00: Bank 0, Addresses 0x00-0x07
01: Bank 1, Addresses 0x08-0x0F
10: Bank 2, Addresses 0x10-0x17
11: Bank 3, Addresses 0x18-0x1F
2OV Overflow Flag.
This bit is set to 1 under the following circumstances:
An ADD, ADDC, or SUBB instruction causes a sign-change overflow.
A MUL instruction results in an overflow (result is greater than 255).
A DIV instruction causes a divide-by-zero condition.
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all
other cases.
1F1 User Flag 1.
This is a bit-addressable, general purpose flag for use under software control.
0PARITY Parity Flag.
This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared
if the sum is even.
, . SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 91
10.4. Serial Number Special Function Registers (SFRs)
The C8051F55x/56x/57x devices include four SFRs, SN0 through SN3, that are pre-programmed during
production with a unique, 32-bit serial number. The serial number provides a unique identification number
for each device and can be read from the application firmware. If the serial number is not used in the appli-
cation, these four registers can be used as general purpose SFRs.
SFR Addresses: SN0 = 0xF9; SN1 = 0xFA; SN2 = 0xFB; SN3 = 0xFC; SFR Page = 0x0F;
SFR Definition 10.7. SNn: Serial Number n
Bit76543210
Name SERNUMn[7:0]
Type R/W
Reset Varies—Unique 32-bit value
Bit Name Function
7:0 SERNUMn[7:0] Serial Number Bits.
The four serial number registers form a 32-bit serial number, with SN3 as the
most significant byte and SN0 as the least significant byte.
, . SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 92
11. Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types. The memory organization is shown in
Figure 11.1
Figure 11.1. C8051F55x/56x/57x Memory Map
11.1. Program Memory
The CIP-51 core has a 64 kB program memory space. The C8051F55x/56x/57x devices implement 32 kB
or 16 kB of this program memory space as in-system, re-programmable Flash memory, organized in a con-
tiguous block from addresses 0x0000 to 0x7FFF in 32 kB devices and addresses 0x0000 to 0x3FFF in
16 kB devices. The address 0x7BFF in 32 kB devices and 0x3FFF in 16 kB devices serves as the security
lock byte for the device. Addresses above 0x7BFF are reserved in the 32 kB devices.
PROGRAM/DATA MEMORY
(FLASH)
(Direct and Indirect
Addressing)
0x00
0x7F
Upper 128 RAM
(Indirect Addressing
Only)
0x80
0xFF Special Function
Register's
(Direct Addressing Only)
DATA MEMORY (RAM)
General Purpose
Registers
0x1F
0x20
0x2F Bit Addressable
Lower 128 RAM
(Direct and Indirect
Addressing)
0x30
INTERNAL DATA ADDRESS SPACE
EXTERNAL DATA ADDRESS SPACE
0x0000
0x07FF
Same 2048 bytes as
from 0x0000 to 0x07FF,
wrapped on 2048-byte
boundaries
0x8000
0xFFFF
32 kB FLASH
(In-System
Programmable in 512
Byte Sectors)
0x0000
RESERVED
0x7C00
0x7BFF
C8051F550/1/2/3
C8051F560/1/2/3/8/9
C8051F570/1
16 kB FLASH
(In-System
Programmable in 512
Byte Sectors)
0x0000
0x3FFF
XRAM
2K Bytes
(accessable using
MOVX instruction)
C8051F554/5/6/7
C8051F564/5/6/7
C8051F572/3/4/5
, . SILIEUN LABS
C8051F55x/56x/57x
93 Rev. 1.2
Figure 11.2. Flash Program Memory Map
11.1.1. MOVX Instruction and Program Memory
The MOVX instruction in an 8051 device is typically used to access external data memory. On the
C8051F55x/56x/57x devices, the MOVX instruction is normally used to read and write on-chip XRAM, but
can be re-configured to write and erase on-chip Flash memory space. MOVC instructions are always used
to read Flash memory, while MOVX write instructions are used to erase and write Flash. This Flash access
feature provides a mechanism for the C8051F55x/56x/57x to update program code and use the program
memory space for non-volatile data storage. Refer to Section “14. Flash Memory” on page 124 for further
details.
11.2. Data Memory
The C8051F55x/56x/57x devices include 2304 bytes of RAM data memory. 256 bytes of this memory is
mapped into the internal RAM space of the 8051. The other 2048 bytes of this memory is on-chip “exter-
nal” memory. The data memory map is shown in Figure 11.1 for reference.
11.2.1. Internal RAM
There are 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The
lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either
direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00
through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight
byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as bytes or
as 128 bit locations accessible with the direct addressing mode.
The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the
same address space as the Special Function Registers (SFR) but is physically separate from the SFR
space. The addressing mode used by an instruction when accessing locations above 0x7F determines
whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use
direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the
upper 128 bytes of data memory. Figure 11.1 illustrates the data memory organization of the
Lock Byte
0x0000
0x3FFF
0x3FFE
FLASH memory organized in
512-byte pages
0x3E00
Flash Memory Space
(16 kB Flash Device)
Lock Byte Page
Lock Byte
0x0000
0x7BFF
0x7BFE
0x7C00
0x7A00
Flash Memory Space
(32 kB Flash Device)
Lock Byte Page
0x7FFF
Reserved Area
C8051F550/1/2/3
C8051F560/1/2/3/8/9
C8051F570/1
C8051F554/5/6/7
C8051F564/5/6/7
C8051F572/3/4/5
, . SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 94
C8051F55x/56x/57x.
11.2.1.1. General Purpose Registers
The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of gen-
eral-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only
one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1
(PSW.4), select the active register bank (see description of the PSW in SFR Definition 10.6). This allows
fast context switching when entering subroutines and interrupt service routines. Indirect addressing modes
use registers R0 and R1 as index registers.
11.2.1.2. Bit Addressable Locations
In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20
through 0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from
0x00 to 0x7F. Bit 0 of the byte at 0x20 has bit address 0x00 while bit7 of the byte at 0x20 has bit address
0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished from a full byte access by
the type of instruction used (bit source or destination operands as opposed to a byte source or destina-
tion).
The MCS-51™ assembly language allows an alternate notation for bit addressing of the form XX.B where
XX is the byte address and B is the bit position within the byte. For example, the instruction:
MOV C, 22.3h
moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag.
11.2.1.3. Stack
A programmer's stack can be located anywhere in the 256-byte data memory. The stack area is desig-
nated using the Stack Pointer (SP) SFR. The SP will point to the last location used. The next value pushed
on the stack is placed at SP+1 and then SP is incremented. A reset initializes the stack pointer to location
0x07. Therefore, the first value pushed on the stack is placed at location 0x08, which is also the first regis-
ter (R0) of register bank 1. Thus, if more than one register bank is to be used, the SP should be initialized
to a location in the data memory not being used for data storage. The stack depth can extend up to
256 bytes.
, . SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 95
12. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the C8051F55x/56x/57x's resources and
peripherals. The CIP-51 controller core duplicates the SFRs found in a typical 8051 implementation as well
as implementing additional SFRs used to configure and access the sub-systems unique to the
C8051F55x/56x/57x. This allows the addition of new functionality while retaining compatibility with the
MCS-51™ instruction set. Table 12.3 lists the SFRs implemented in the C8051F55x/56x/57x device family.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g., P0, TCON, SCON0, IE, etc.) are bit-
addressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied
addresses in the SFR space are reserved for future use. Accessing unoccupied addresses in the SFR
space will have an indeterminate effect and should be avoided. Refer to the corresponding pages of the
data sheet, as indicated in Table 12.3, for a detailed description of each register.
12.1. SFR Paging
The CIP-51 features SFR paging, allowing the device to map many SFRs into the 0x80 to 0xFF memory
address space. The SFR memory space has 256 pages. In this way, each memory location from 0x80 to
0xFF can access up to 256 SFRs. The C8051F55x/56x/57x family of devices utilizes three SFR pages:
0x00, 0x0C, and 0x0F. SFR pages are selected using the Special Function Register Page Selection regis-
ter, SFRPAGE (see SFR Definition 11.3). The procedure for reading and writing an SFR is as follows:
1. Select the appropriate SFR page number using the SFRPAGE register.
2. Use direct accessing mode to read or write the special function register (MOV instruction).
12.2. Interrupts and SFR Paging
When an interrupt occurs, the SFR Page Register will automatically switch to the SFR page containing the
flag bit that caused the interrupt. The automatic SFR Page switch function conveniently removes the bur-
den of switching SFR pages from the interrupt service routine. Upon execution of the RETI instruction, the
SFR page is automatically restored to the SFR Page in use prior to the interrupt. This is accomplished via
a three-byte SFR Page Stack. The top byte of the stack is SFRPAGE, the current SFR Page. The second
byte of the SFR Page Stack is SFRNEXT. The third, or bottom byte of the SFR Page Stack is SFRLAST.
Upon an interrupt, the current SFRPAGE value is pushed to the SFRNEXT byte, and the value of
SFRNEXT is pushed to SFRLAST. Hardware then loads SFRPAGE with the SFR Page containing the flag
bit associated with the interrupt. On a return from interrupt, the SFR Page Stack is popped resulting in the
value of SFRNEXT returning to the SFRPAGE register, thereby restoring the SFR page context without
software intervention. The value in SFRLAST (0x00 if there is no SFR Page value in the bottom of the
stack) of the stack is placed in SFRNEXT register. If desired, the values stored in SFRNEXT and SFR-
LAST may be modified during an interrupt, enabling the CPU to return to a different SFR Page upon exe-
cution of the RETI instruction (on interrupt exit). Modifying registers in the SFR Page Stack does not cause
a push or pop of the stack. Only interrupt calls and returns will cause push/pop operations on the SFR
Page Stack.
On the C8051F55x/56x/57x devices, vectoring to an interrupt will switch SFRPAGE to page 0x00, except
for the CAN0 interrupt which will switch SFRPAGE to page 0x0C.
SSSSSSSSSSS
C8051F55x/56x/57x
96 Rev. 1.2
Figure 12.1. SFR Page Stack
Automatic hardware switching of the SFR Page on interrupts may be enabled or disabled as desired using
the SFR Automatic Page Control Enable Bit located in the SFR Page Control Register (SFR0CN). This
function defaults to “enabled” upon reset. In this way, the autoswitching function will be enabled unless dis-
abled in software.
A summary of the SFR locations (address and SFR page) are provided in Table 12.3 in the form of an SFR
memory map. Each memory location in the map has an SFR page row, denoting the page in which that
SFR resides. Certain SFRs are accessible from ALL SFR pages, and are denoted by the “(ALL PAGES)”
designation. For example, the Port I/O registers P0, P1, P2, and P3 all have the “(ALL PAGES)” designa-
tion, indicating these SFRs are accessible from all SFR pages regardless of the SFRPAGE register value.
SFRNEXT
SFRPAGE
SFRLAST
CIP-51
Interrupt
Logic
SFRPGCN Bit
SILIEDN LABS
C8051F55x/56x/57x
Rev. 1.2 97
12.3. SFR Page Stack Example
The following is an example that shows the operation of the SFR Page Stack during interrupts. In this
example, the SFR Control register is left in the default enabled state (i.e., SFRPGEN = 1), and the CIP-51
is executing in-line code that is writing values to SPI Data Register (SFR “SPI0DAT”, located at address
0xA3 on SFR Page 0x00). The device is also using the CAN peripheral (CAN0) and the Programmable
Counter Array (PCA0) peripheral to generate a PWM output. The PCA is timing a critical control function in
its interrupt service and so its associated ISR that is set to high priority. At this point, the SFR page is set to
access the SPI0DAT SFR (SFRPAGE = 0x00). See Figure 12.2.
Figure 12.2. SFR Page Stack While Using SFR Page 0x0 To Access SPI0DAT
0x0
(SPI0DAT) SFRPAGE
SFRLAST
SFRNEXT
SFR Page
Stack SFR's
SILICEIN LAES
C8051F55x/56x/57x
98 Rev. 1.2
While CIP-51 executes in-line code (writing values to SPI0DAT in this example), the CAN0 Interrupt
occurs. The CIP-51 vectors to the CAN0 ISR and pushes the current SFR Page value (SFR Page 0x00)
into SFRNEXT in the SFR Page Stack. The SFR page needed to access CAN’s SFRs is then automatically
placed in the SFRPAGE register (SFR Page 0x0C). SFRPAGE is considered the “top” of the SFR Page
Stack. Software can now access the CAN0 SFRs. Software may switch to any SFR Page by writing a new
value to the SFRPAGE register at any time during the CAN0 ISR to access SFRs that are not on SFR
Page 0x0C. See Figure 12.3.
Figure 12.3. SFR Page Stack After CAN0 Interrupt Occurs
0xC
(CAN0)
0x0
(SPI0DAT)
SFRPAGE
SFRLAST
SFRNEXT
SFRPAGE
pushed to
SFRNEXT
SFR Page 0xC
Automatically
pushed on stack in
SFRPAGE on CAN0
interrupt
, . SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 99
While in the CAN0 ISR, a PCA interrupt occurs. Recall the PCA interrupt is configured as a high priority
interrupt, while the CAN0 interrupt is configured as a low priority interrupt. Thus, the CIP-51 will now vector
to the high priority PCA ISR. Upon doing so, the CIP-51 will automatically place the SFR page needed to
access the PCA’s special function registers into the SFRPAGE register, SFR Page 0x00. The value that
was in the SFRPAGE register before the PCA interrupt (SFR Page 0x0C for CAN0) is pushed down the
stack into SFRNEXT. Likewise, the value that was in the SFRNEXT register before the PCA interrupt (in
this case SFR Page 0x00 for SPI0DAT) is pushed down to the SFRLAST register, the “bottom” of the
stack. Note that a value stored in SFRLAST (via a previous software write to the SFRLAST register) will be
overwritten. See Figure 12.4.
Figure 12.4. SFR Page Stack Upon PCA Interrupt Occurring During a CAN0 ISR
0x0
(PCA)
0xC
(CAN0)
0x0
(SPI0DAT)
SFRPAGE
SFRLAST
SFRNEXT
SFR Page 0x0
Automatically
pushed on stack in
SFRPAGE on PCA
interrupt
SFRPAGE
pushed to
SFRNEXT
SFRNEXT
pushed to
SFRLAST
C8051F55x/56x/57x
100 Rev. 1.2
On exit from the PCA interrupt service routine, the CIP-51 will return to the CAN0 ISR. On execution of the
RETI instruction, SFR Page 0x00 used to access the PCA registers will be automatically popped off of the
SFR Page Stack, and the contents of the SFRNEXT register will be moved to the SFRPAGE register. Soft-
ware in the CAN0 ISR can continue to access SFRs as it did prior to the PCA interrupt. Likewise, the con-
tents of SFRLAST are moved to the SFRNEXT register. Recall this was the SFR Page value 0x00 being
used to access SPI0DAT before the CAN0 interrupt occurred. See Figure 12.5.
Figure 12.5. SFR Page Stack Upon Return From PCA Interrupt
0xC
(CAN0)
0x0
(SPI0DAT)
SFRPAGE
SFRLAST
SFRNEXT
SFR Page 0x0
Automatically
popped off of the
stack on return from
interrupt
SFRNEXT
popped to
SFRPAGE
SFRLAST
popped to
SFRNEXT
SSSSSSSSSSS
C8051F55x/56x/57x
Rev. 1.2 101
On the execution of the RETI instruction in the CAN0 ISR, the value in SFRPAGE register is overwritten
with the contents of SFRNEXT. The CIP-51 may now access the SPI0DAT register as it did prior to the
interrupts occurring. See Figure 12.6.
Figure 12.6. SFR Page Stack Upon Return From CAN0 Interrupt
In the example above, all three bytes in the SFR Page Stack are accessible via the SFRPAGE, SFRNEXT,
and SFRLAST special function registers. If the stack is altered while servicing an interrupt, it is possible to
return to a different SFR Page upon interrupt exit than selected prior to the interrupt call. Direct access to
the SFR Page stack can be useful to enable real-time operating systems to control and manage context
switching between multiple tasks.
Push operations on the SFR Page Stack only occur on interrupt service, and pop operations only occur on
interrupt exit (execution on the RETI instruction). The automatic switching of the SFRPAGE and operation
of the SFR Page Stack as described above can be disabled in software by clearing the SFR Automatic
Page Enable Bit (SFRPGEN) in the SFR Page Control Register (SFR0CN). See SFR Definition 12.1.
0x0
(SPI0DAT) SFRPAGE
SFRLAST
SFRNEXT
SFR Page 0xC
Automatically
popped off of the
stack on return from
interrupt
SFRNEXT
popped to
SFRPAGE
, . SILIEUN LABS
C8051F55x/56x/57x
102 Rev. 1.2
SFR Address = 0x84; SFR Page = 0x0F
SFR Definition 12.1. SFR0CN: SFR Page Control
Bit 7 6 5 4 3 2 1 0
Name SFRPGEN
Type RRRRRRRR/W
Reset 0 0 0 0 0 0 0 1
Bit Name Function
7:1 Unused Read = 0000000b; Write = Don’t Care
0SFRPGEN SFR Automatic Page Control Enable.
Upon interrupt, the C8051 Core will vector to the specified interrupt service routine
and automatically switch the SFR page to the corresponding peripheral or function’s
SFR page. This bit is used to control this autopaging function.
0: SFR Automatic Paging disabled. The C8051 core will not automatically change to
the appropriate SFR page (i.e., the SFR page that contains the SFRs for the periph-
eral/function that was the source of the interrupt).
1: SFR Automatic Paging enabled. Upon interrupt, the C8051 will switch the SFR
page to the page that contains the SFRs for the peripheral or function that is the
source of the interrupt.
, . SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 103
SFR Address = 0xA7; SFR Page = All Pages
SFR Definition 12.2. SFRPAGE: SFR Page
Bit 7 6 5 4 3 2 1 0
Name SFRPAGE[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
Bit Name Function
7:0 SFRPAGE[7:0] SFR Page Bits.
Represents the SFR Page the C8051 core uses when reading or modifying
SFRs.
Write: Sets the SFR Page.
Read: Byte is the SFR page the C8051 core is using.
When enabled in the SFR Page Control Register (SFR0CN), the C8051 core will
automatically switch to the SFR Page that contains the SFRs of the correspond-
ing peripheral/function that caused the interrupt, and return to the previous SFR
page upon return from interrupt (unless SFR Stack was altered before a return-
ing from the interrupt). SFRPAGE is the top byte of the SFR Page Stack, and
push/pop events of this stack are caused by interrupts (and not by reading/writ-
ing to the SFRPAGE register)
, . SILIEUN LABS
C8051F55x/56x/57x
104 Rev. 1.2
SFR Address = 0x85; SFR Page = All Pages
SFR Definition 12.3. SFRNEXT: SFR Next
Bit 7 6 5 4 3 2 1 0
Name SFRNEXT[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
Bit Name Function
7:0 SFRNEXT[7:0] SFR Page Bits.
This is the value that will go to the SFR Page register upon a return from inter-
rupt.
Write: Sets the SFR Page contained in the second byte of the SFR Stack. This
will cause the SFRPAGE SFR to have this SFR page value upon a return from
interrupt.
Read: Returns the value of the SFR page contained in the second byte of the
SFR stack.
SFR page context is retained upon interrupts/return from interrupts in a 3 byte
SFR Page Stack: SFRPAGE is the first entry, SFRNEXT is the second, and
SFRLAST is the third entry. The SFR stack bytes may be used alter the context
in the SFR Page Stack, and will not cause the stack to “push” or “pop”. Only
interrupts and return from interrupts cause pushes and pops of the SFR Page
Stack.
, . SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 105
SFR Address = 0xA7; SFR Page = All Pages
SFR Definition 12.4. SFRLAST: SFR Last
Bit 7 6 5 4 3 2 1 0
Name SFRLAST[7:0]
Type R/W
Reset 0 0 0 0 0 0 0 0
Bit Name Function
7:0 SFRLAST[7:0] SFR Page Stack Bits.
This is the value that will go to the SFRNEXT register upon a return from inter-
rupt.
Write: Sets the SFR Page in the last entry of the SFR Stack. This will cause the
SFRNEXT SFR to have this SFR page value upon a return from interrupt.
Read: Returns the value of the SFR page contained in the last entry of the SFR
stack.
SFR page context is retained upon interrupts/return from interrupts in a 3 byte
SFR Page Stack: SFRPAGE is the first entry, SFRNEXT is the second, and
SFRLAST is the third entry. The SFR stack bytes may be used alter the context
in the SFR Page Stack, and will not cause the stack to “push” or “pop”. Only
interrupts and return from interrupts cause pushes and pops of the SFR Page
Stack.
hhi’ , ‘ SILIEIJN LABS
C8051F55x/56x/57x
106 Rev. 1.2
Table 12.1. Special Function Register (SFR) Memory Map for Pages 0x00 and 0x0F
Address
Page
0(8) 1(9) 2(A) 3(B) 4(C) 5(D) 6(E) 7(F)
F8 0
F
SPI0CN PCA0L
SN0
PCA0H
SN1
PCA0CPL0
SN2
PCA0CPH0
SN3
PCACPL4 PCACPH4 VDM0CN
F0 0
F
B
(All Pages)
P0MAT
P0MDIN
P0MASK
P1MDIN
P1MAT
P2MDIN
P1MASK
P3MDIN
EIP1
EIP1
EIP2
EIP2
E8 0
F
ADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2 PCA0CPL3 PCA0CPL3 RSTSRC
E0 0
F
ACC
(All Pages) XBR0 XBR1 CCH0CN IT01CF
EIE1
(All Pages)
EIE2
(All Pages)
D8 0
F
PCA0CN PCA0MD
PCA0PWM
PCA0CPM0 PCA0CPM1 PCA0CPM2 PCA0CPM3 PCA0CPM4 PCA0CPM5
D0 0
F
PSW
(All Pages)
REF0CN LIN0DATA LIN0ADDR
P0SKIP P1SKIP P2SKIP P3SKIP
C8 0
F
TMR2CN REG0CN
LIN0CF
TMR2RLL TMR2RLH TMR2L TMR2H PCA0CPL5 PCA0CPH5
C0 0
F
SMB0CN SMB0CF SMB0DAT ADC0GTL ADC0GTH ADC0LTL ADC0LTH
XBR2
B8 0
F
IP
(All Pages)
ADC0TK ADC0MX ADC0CF ADC0L ADC0H
B0 0
F
P3
(All Pages)
P2MAT P2MASK
EMI0CF
P4
(All Pages)
FLSCL
(All Pages)
FLKEY
(All Pages)
A8 0
F
IE
(All Pages)
SMOD0 EMI0CN
EMI0TC SBCON0 SBRLL0 SBRLH0
P3MAT
P3MDOUT
P3MASK
P4MDOUT
A0 0
F
P2
(All Pages)
SPI0CFG
OSCICN
SPI0CKR
OSCICRS
SPI0DAT
P0MDOUT P1MDOUT P2MDOUT
SFRPAGE
(All Pages)
98 0
F
SCON0 SBUF0 CPT0CN CPT0MD CPT0MX CPT1CN CPT1MD
OSCIFIN
CPT1MX
OSCXCN
90 0
F
P1
(All Pages)
TMR3CN TMR3RLL TMR3RLH TMR3L TMR3H
CLKMUL
88 0
F
TCON
(All Pages)
TMOD
(All Pages)
TL0
(All Pages)
TL1
(All Pages)
TH0
(All Pages)
TH1
(All Pages)
CKCON
(All Pages)
PSCTL
CLKSEL
80 0
F
P0
(All Pages)
SP
(All Pages)
DPL
(All Pages)
DPH
(All Pages) SFR0CN
SFRNEXT
(All Pages)
SFRLAST
(All Pages)
PCON
(All Pages)
0(8) 1(9) 2(A) 3(B) 4(C) 5(D) 6(E) 7(F)
(bit addressable)
, . SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 107
Table 12.2. Special Function Register (SFR) Memory Map for Page 0x0C
0(8) 1(9) 2(A) 3(B) 4(C) 5(D) 6(E) 7(F)
F8 CAN0IF2DA2L CAN0IF2DA2H CAN0IF2DB1L CAN0IF2DB1H CAN0IF2DB2L CAN0IF2DB2H
F0 B
(All Pages)
CAN0IF2A2L CAN0IF2A2H CAN0IF2DA1L CAN0IF2DA1H
E8 CAN0IF2M1L CAN0IF2M1H CAN0IF2M2L CAN0IF2M2H CAN0IF2A1L CAN0IF2A1H
E0 ACC
(All Pages)
CAN0IF2CML CAN0IF2CMH EIE1
(All Pages)
EIE2
(All Pages)
D8 CAN0IF1DB1L CAN0IF1DB1H CAN0IF1DB2L CAN0IF1DB2H CAN0IF2CRL CAN0IF2CRH
D0 PSW
(All Pages)
CAN0IF1MCL CAN0IF1MCH CAN0IF1DA1L CAN0IF1DA1H CAN0IF1DA2L CAN0IF1DA2H
C8 CAN0IF1A1L CAN0IF1A1H CAN0IF1A2L CAN0IF1A2H CAN0IF2MCL CAN0IF2MCH
C0 CAN0CN CAN0IF1CML CAN0IF1CMH CAN0IF1M1L CAN0IF1M1H CAN0IF1M2L CAN0IF1M2H
B8 IP
(All Pages)
CAN0MV1L CAN0MV1H CAN0MV2L CAN0MV2H CAN0IF1CRL CAN0IF1CRH
B0 P3
(All Pages)
CAN0IP2L CAN0IP2H P4
(All Pages)
FLSCL
(All Pages)
FLKEY
(All Pages)
A8 IE
(All Pages)
CAN0ND1L CAN0ND1H CAN0ND2L CAN0ND2H CAN0IP1L CAN0IP1H
A0 P2
(All Pages)
CAN0BRPE CAN0TR1L CAN0TR1H CAN0TR2L CAN0TR2H SFRPAGE
(All Pages)
98 SCON0
(All Pages)
CAN0BTL CAN0BTH CAN0IIDL CAN0IIDH CAN0TST
90 P1
(All Pages)
CAN0CFG CAN0STAT CAN0ERRL CAN0ERRH
88 TCON
(All Pages)
TMOD
(All Pages)
TL0
(All Pages)
TL1
(All Pages)
TH0
(All Pages)
TH1
(All Pages)
CKCON
(All Pages)
80 P0
(All Pages)
SP
(All Pages)
DPL
(All Pages)
DPH
(All Pages)
SFRNEXT
(All Pages)
SFRLAST
(All Pages)
PCON
(All Pages)
0(8) 1(9) 2(A) 3(B) 4(C) 5(D) 6(E) 7(F)
(bit addressable)
, ‘ SILIEIJN LABS
C8051F55x/56x/57x
108 Rev. 1.2
Table 12.3. Special Function Registers
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register Address Description Page
ACC 0xE0 Accumulator 89
ADC0CF 0xBC ADC0 Configuration 58
ADC0CN 0xE8 ADC0 Control 60
ADC0GTH 0xC4 ADC0 Greater-Than Compare High 62
ADC0GTL 0xC3 ADC0 Greater-Than Compare Low 62
ADC0H 0xBE ADC0 High 59
ADC0L 0xBD ADC0 Low 59
ADC0LTH 0xC6 ADC0 Less-Than Compare Word High 63
ADC0LTL 0xC5 ADC0 Less-Than Compare Word Low 63
ADC0MX 0xBB ADC0 Mux Configuration 66
ADC0TK 0xBA ADC0 Tracking Mode Select 61
B0xF0 B Register 89
CCH0CN 0xE3 Cache Control 134
CKCON 0x8E Clock Control 260
CLKMUL 0x97 Clock Multiplier 163
CLKSEL 0x8F Clock Select 158
CPT0CN 0x9A Comparator0 Control 72
CPT0MD 0x9B Comparator0 Mode Selection 73
CPT0MX 0x9C Comparator0 MUX Selection 77
CPT1CN 0x9D Comparator1 Control 72
CPT1MD 0x9E Comparator1 Mode Selection 73
CPT1MX 0x9F Comparator1 MUX Selection 77
DPH 0x83 Data Pointer High 88
DPL 0x82 Data Pointer Low 88
EIE1 0xE6 Extended Interrupt Enable 1 118
EIE2 0xE7 Extended Interrupt Enable 2 118
EIP1 0xF6 Extended Interrupt Priority 1 119
EIP2 0xF7 Extended Interrupt Priority 2 120
EMI0CF 0xB2 External Memory Interface Configuration 148
EMI0CN 0xAA External Memory Interface Control 147
EMI0TC 0xAA External Memory Interface Timing Control 152
FLKEY 0xB7 Flash Lock and Key 132
FLSCL 0xB6 Flash Scale 133
IE 0xA8 Interrupt Enable 116
IP 0xB8 Interrupt Priority 117
, . SILIEUN LABS
C8051F55x/56x/57x
Rev. 1.2 109
IT01CF 0xE4 INT0/INT1 Configuration 123
LIN0ADR 0xD3 LIN0 Address 200
LIN0CF 0xC9 LIN0 Configuration 200
LIN0DAT 0xD2 LIN0 Data 201
OSCICN 0xA1 Internal Oscillator Control 160
OSCICRS 0xA2 Internal Oscillator Coarse Control 161
OSCIFIN 0x9E Internal Oscillator Fine Calibration 161
OSCXCN 0x9F External Oscillator Control 165
P0 0x80 Port 0 Latch 183
P0MASK 0xF2 Port 0 Mask Configuration 179
P0MAT 0xF1 Port 0 Match Configuration 179
P0MDIN 0xF1 Port 0 Input Mode Configuration 184
P0MDOUT 0xA4 Port 0 Output Mode Configuration 184
P0SKIP 0xD4 Port 0 Skip 185
P1 0x90 Port 1 Latch 185
P1MASK 0xF4 Port 1 Mask Configuration 180
P1MAT 0xF3 Port 1 Match Configuration 180
P1MDIN 0xF2 Port 1 Input Mode Configuration 186
P1MDOUT 0xA5 Port 1 Output Mode Configuration 186
P1SKIP 0xD5 Port 1 Skip 187
P2 0xA0 Port 2 Latch 187
P2MASK 0xB2 Port 2 Mask Configuration 181
P2MAT 0xB1 Port 2 Match Configuration 181
P2MDIN 0xF3 Port 2 Input Mode Configuration 188
P2MDOUT 0xA6 Port 2 Output Mode Configuration 188
P2SKIP 0xD6 Port 2 Skip 189
P3 0xB0 Port 3 Latch 189
P3MASK 0xAF Port 3 Mask Configuration 182
P3MAT 0xAE Port 3 Match Configuration 182
P3MDIN 0xF4 Port 3 Input Mode Configuration 190
P3MDOUT 0xAE Port 3 Output Mode Configuration 190
P3SKIP 0xD7 Port 3 Skip 191
P4 0xB5 Port 4 Latch 191
P4MDOUT 0xAF Port 4 Output Mode Configuration 192
PCA0CN 0xD8 PCA Control 294
PCA0CPH0 0xFC PCA Capture 0 High 299
Table 12.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register Address Description Page
, ‘ SILIEIJN LABS
C8051F55x/56x/57x
110 Rev. 1.2
PCA0CPH1 0xEA PCA Capture 1 High 299
PCA0CPH2 0xEC PCA Capture 2 High 299
PCA0CPH3 0xEE PCA Capture 3 High 299
PCA0CPH4 0xFE PCA Capture 4 High 299
PCA0CPH5 0xCF PCA Capture 5 High 299
PCA0CPL0 0xFB PCA Capture 0 Low 299
PCA0CPL1 0xE9 PCA Capture 1 Low 299
PCA0CPL2 0xEB PCA Capture 2 Low 299
PCA0CPL3 0xED PCA Capture 3 Low 299
PCA0CPL4 0xFD PCA Capture 4 Low 299
PCA0CPL5 0xCE PCA Capture 5 Low 299
PCA0CPM0 0xDA PCA Module 0 Mode Register 297
PCA0CPM1 0xDB PCA Module 1 Mode Register 297
PCA0CPM2 0xDC PCA Module 2 Mode Register 297
PCA0CPM3 0xDD PCA Module 3 Mode Register 297
PCA0CPM4 0xDE PCA Module 4 Mode Register 297
PCA0CPM5 0xDF PCA Module 5 Mode Register 297
PCA0H 0xFA PCA Counter High 298
PCA0L 0xF9 PCA Counter Low 298
PCA0MD 0xD9 PCA Mode 295
PCA0PWM 0xD9