Davinci-DM644x EVM Tech Ref Datasheet by Spectrum Digital Inc

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SPECTRUM ML INCORPORAYED 2006 DSP Development Systems
Davinci-DM644x
Evaluation Module
2006 DSP Development Systems
Reference
Technical
DaVinci-DM644x Evaluation
Module Technical Reference
508165-0001 Rev. C
October 2006
SPECTRUM DIGITAL, INC.
12502 Exchange Drive, Suite 440 Stafford, TX. 77477
Tel: 281.494.4505 Fax: 281.494.5310
sales@spectrumdigital.com www.spectrumdigital.com
IMPORTANT NOTICE
Spectrum Digital, Inc. reserves the right to make changes to its products or to discontinue any
product or service without notice. Customers are advised to obtain the latest version of relevant
information to verify that the data being relied on is current before placing orders.
Spectrum Digital, Inc. warrants performance of its products and related software to current
specifications in accordance with Spectrum Digital’s standard warranty. Testing and other quality
control techniques are utilized to the extent deemed necessary to support this warranty.
Please be aware that the products described herein are not intended for use in life-support
appliances, devices, or systems. Spectrum Digital does not warrant nor is Spectrum Digital liable for
the product described herein to be used in other than a development environment.
Spectrum Digital, Inc. assumes no liability for applications assistance, customer product design,
software performance, or infringement of patents or services described herein. Nor does Spectrum
Digital warrant or represent any license, either express or implied, is granted under any patent right,
copyright, or other intellectual property right of Spectrum Digital, Inc. covering or relating to any
combination, machine, or process in which such Digital Signal Processing development products or
services might be or are used.
WARNING
This equipment is intended for use in a laboratory test environment only. It generates, uses, and can
radiate radio frequency energy and has not been tested for compliance with the limits of computing
devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable
protection against radio frequency interference. Operation of this equipment in other environments
may cause interference with radio communications, in which case the user at his own expense will be
required to take whatever measures necessary to correct this interference.
Copyright © 2006 Spectrum Digital, Inc.
Contents
Contents
1 Introduction to the DM644x Evaluation Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Provides you with a description of the DM644x Evaluation Module, key features, and
block diagram.
1.1 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.2 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.3 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.5 Configuration Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.6 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
2 Board Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Describes the operation of the major board components on the DM644x Evaluation Module.
2.1 EMIF Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.1.1 DDR2 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.1.2 Flash, NAND Flash, SRAM Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.1.3 ATA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.1.4 Compact Flash Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.1.5 Memory Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.1.6 VLYNQ Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.1.7 UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.1.8 EMIF Buffer/Decoder Control CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.2 Input Video Port Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.2.1 On Chip Video Output DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.2.2 AIC33 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.2.3 Audio PLL/VCXO Circuit/PLL1705 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.3 Ethernet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.4 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.4.1 I/O Expanders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
2.4.2 MSP430 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.5 SPDIF Analog, and Optical Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.6 Daughter Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.7 DM644x Core CPU Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.8 USB Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.9 Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
3 Physical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Describes the physical layout of the DM644x Evaluation Module and its connectors.
3.1 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.2 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.2.1 J1, Emulation Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.2.2 J2, MSP430 JTAG Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.2.3 J3, SD/MMC/MS Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.2.4 J4, CS2 Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.2.5 J5, SD/MMC/MS Termination Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.2.6 J6, External RESET Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.2.7 J7, USB Host/Client Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.2.8 J8, Dual RCA Jack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.2.9 J9, Video Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.2.10 J10, USB Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
3.2.11 J11, Video In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.2.12 J12, Video In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.2.13 J13, SPDIF Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
3.2.14 J14, +5V Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
3.2.15 J15, SM/xD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
3.2.16 J16, Mini PCI VLYNQ Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
3.2.17 J17, FPGA Programming Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
3.3 Peripheral Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
3.3.1 P1, Compact Flash Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
3.3.2 P2, Ethernet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
3.3.3 P3, Line In/Mic Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
3.3.4 P4, Headphone Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
3.3.5 P5, Dual Output RCA Jack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
3.3.6 P6, UART0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
3.4 JP1, ATA Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22
3.5 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
3.6 Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
3.6.1 S1, EMU0/1 Select Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
3.6.2 S2, TRSTn Select Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25
3.6.3 S3, Processor Configuration/Boot Load Options . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26
3.6.4 S4, RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
3.6.5 SW1, Power On/Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
3.7 Daughter Card Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
3.7.1 DC1, EMIF Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28
3.7.2 DC2, GIOV33/Ethernet Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29
3.7.3 DC3, SPI, McBSP, I2C Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30
3.7.4 DC4, Video Input Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31
3.7.5 DC5, Video Output Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32
3.7.6 DC6, SD Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33
3.7.7 DC7, Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33
3.8 Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34
A Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
Contains the schematics for the DM644x Evaluation Module
B Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
Contains the mechanical information about the DM644x Evaluation Module
About This Manual
This document describes the board level operations of the DM644x Evaluation Module
(EVM). The EVM is based on the Texas Instruments DM644x Processor.
The DM644x Evaluation Module is a table top card that allows engineers and software
developers to evaluate certain characteristics of the DM644x processor to determine if
the processor meets the designers application requirements. Evaluators can create
software to execute on board or expand the system in a variety of ways.
Notational Conventions
This document uses the following conventions.
The DM644x Evaluation Module will sometimes be referred to as the DM644x EVM or
EVM.
Program listings, program examples, and interactive displays are shown in a special
italic typeface. Here is a sample program listing.
equations
!rd = !strobe&rw;
Information About Cautions
This book may contain cautions.
This is an example of a caution statement.
A caution statement describes a situation that could potentially damage your software,
or hardware, or other equipment. The information in a caution is provided for your
protection. Please read each caution carefully.
Related Documents, Application Notes and User Guides
Information regarding DaVinciTM technology can be found at the following Texas
Instruments website:
http://www.ti.com/corp/docs/landing/davinci/index.html
Table 1: Manual History
Revision History
A Production Release
BCorrected I2C address of TVP5146
C Corrected Pin 70, Table 30, DC1 connector
Table 2: Board History
Revision History
C Production Release
1-1
Chapter 1
Introduction to the
DM644x EVM
Chapter One provides a description of the DM644x EVM along with the key
features and a block diagram of the circuit board.
Topic Page
1.1 Key Features 1-2
1.2 Functional Overview 1-3
1.3 Basic Operation 1-4
1.4 Memory Map 1-5
1.5 Configuration Switch Settings 1-6
1.6 Power Supply 1-7
EM Mm
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1-2 DM644x EVM Technical Reference
1.1 Key Features
The DM644x EVM is a standalone development platform that enables users to
evaluate and develop applications for the TI DaVinci processor family. Schematics,
logic equations and application notes are available to ease hardware development and
reduce time to market.
The EVM comes with a full complement of on board devices that suit a wide variety of
application environments. Key features include:
• A Texas Instruments DM644x processor with an ARM processor operating up to
300 Mhz. and a C64xx DSP operating up to 600 Mhz.
• 1 video input port, supports composite or S video
• 4 video DAC outputs - component, RGB, composite
• 256 Mbytes of DDR2 DRAM
• UART, Media Card interface (SD card, xD card, SM card, MS card, MMC)
• 16 Mbytes of non-volatile Flash memory, 64 Mbytes NAND Flash, 4 Mbytes SRAM
• AIC33 stereo codec
Figure 1-1, Block Diagram DM644x EVM
SM/xD
Compact
Flash
IR PWR
SW
S3
Config
DC3 DC2
3V
BAT
DC1 (EMIF)
SD/
MMC/
MS
TI JTAG
MSP430
JTAG
SVHS
IN
USB
VIDEO
IN
AUDIO
IN
HP OUT
AUDIO
OUT
S/PDIF
Optical
S/PDIF
Analog
UART
+5V
MSP430
User LEDs
DC7
DC6
S1 S2
NAND
Flash
1.2V DSP Core Voltage
1.8V I/O Voltage
3.3V Board Supply Voltage
AIC33
J5
I2C
GPIO
I2C
GPIO
I2C
GPIO I2C
EEPROM
D A V I N C I
EVALUATION MODULE
A TEXAS INSTRUMENTS TECHNOLOGY
NOR
Flash
DC4 (VIDEO IN)
TVP
5146 S/PDIF
Drivers
SVHS
OUT
DAC OUT
DC5 (VIDEO OUT)
EMIF
Video Ports
ATA Hard Disk
DDR
I2C
CPLD
Serial Media
DaVinci
ENET
PHY
EMAC
Altera
JTAG
DDR
DDR
10/100
ENET
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• USB2 Interface
• 10/100 MBS Ethernet Interface
• IR Remote Interface, real time clock, via MSP430
• Configurable boot load options
• JTAG emulation interface
• 8 user LEDs
• Single voltage power supply (+5V)
• Expansion connectors for daughter card use
• ATA Interface, Vlynq Interface
• SPDIF Interface, analog, and optical
1.2 Functional Overview of the DM644x EVM
The DM644x on the DaVinci EVM interfaces to on-board peripherals through the
16-bit wide EMIF peripheral interface pins. The DDR2 memory is connected to its own
dedicated 32 bit wide bus. The EMIF bus is also connected to the Flash, SRAM,
NAND, and daughter card expansion connectors which are used for add-in boards.
On board video decoder and on chip encoders interface video streams to the DM644x
processor. One decoder and 4 on chip DAC channels are standard on the EVM. On
screen display functions are implemented in software on the DM644x processor.
An on-board AIC33 codec allows the DSP to transmit and receive analog audio
signals. The I2C bus is used for the codec control interface, while the McBSP controls
the audio stream. Signal interfacing is done through 3.5mm audio jacks that correspond
to microphone input, line input, and line output. The codec can select the line input as
the active input.
The EVM includes 8 LEDs, IR interface, and Real time clock which can be used to
provide the user with interactive feedback. These interfaces are implemented via
software on a MSP430 and are accessed by reading and writing to the I2C registers.
Media cards, ATA interface, VLYNQ, and ethernet MAC interfaces are integrated
peripheral on the DM644x processor exploiting its system on a chip architecture.
An included 5V external power supply is used to power the board. On-board switching
voltage regulators provide the +1.2V CPU core voltage and +3.3V for peripherals and
+1.8V memory and DM644x I/O. The board is held in reset until these supplies are
within operating specifications.
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1-4 DM644x EVM Technical Reference
Code Composer communicates with the EVM through an external emulator via the
20 pin external JTAG connector.
1.3 Basic Operation
The EVM is designed to work with TI’s Code Composer Studio development, or
standard GDB tool environments. Code Composer communicates with the board
through an external JTAG emulator. To start, follow the instructions in the Quick Start
Guide to install Code Composer. This process will install all of the necessary
development tools, documentation and drivers.
Detailed information about the EVM including examples and reference material is
available on the EVM’s CD-ROM.
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1-5
1.4 Memory Map
The DaVinci family of processors have a large byte addressable address space, some
limitations to byte addressing are determined by peripheral interconnection to the
Davinci device. Program code and data can be placed anywhere in the unified address
space. Addresses are multiple sizes depending on hardware implementation. Refer to
the appropriate device data sheets for more details.
The memory map shows the address space of a generic DaVinci processor on the left
with specific details of how each region is used on the right. By default, the internal
memory sits at the beginning of the address space. Portions of memory can be
remapped in software as L2 cache rather than fixed RAM.
The part incorporates a dual EMIF interface. One dedicated EMIF directly interfaces to
the DDR2 memory. The other EMIF has 4 separate addressable regions called chip
enable spaces (CS2-CS5). The Flash, NAND Flash, or SRAM are mapped into CE2
space and selectable via J4. Daughter cards use CE2 and CE3. When CE2 is used for
daughter card interfacing J4 must be set appropriately. CS4 and CS5 are reserved for
the VLYNQ interface on the EVM.
ARM Instruction RAM
DM644x EVM
Generic DaVinci
Address Space
Address
0x00000000
0x00040000
0x02000000
0x06000000
0x08000000
0x80000000
AEMIF CS3
AEMIF CS4
AEMIF CS5
DDR
Figure 1-2, Memory Map, DM644x EVM
ARM Instruction RAM
ARM Data RAM ARM Data RAM
AEMIF CS2 Flash/NAND/SRAM/DC
0x04000000 DC
VLNQ
VLNQ
DDR
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1-6 DM644x EVM Technical Reference
1.5 Configuration Switch Settings
The EVM has a single 10 position configuration switch that allow users to control the
operational state of the processor when it is released from reset. The configuration
switch is labeled S3 on the EVM board.
Switch S3 configures the boot mode that will be used when the DSP starts executing.
By default the switches are configured to EMIF boot (out of 8-bit Flash) in little endian
mode. The table below shows the settings for switch S3.
Table 1: Configuration Switch S3 Settings
Position Name Function Boot Mode
1 COUT0 Boot Mode 0 00 - Boot from ROM NAND
01 - Boot from AEMIF
10 - Boot from ROM HPI
11 - Boot from ROM UART
2 COUT1 Boot Mode 1
3 COUT2 Bus width: 0=8 bit, 1=16 bit
4 COUT3 0=ARM boots DSP,
1=C64xx self boots
5YOUT4
6YOUT3
7YOUT2
8YOUT1
9YOUT0
10 USER For Demos
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1.6 Power Supply
The EVM operates from a single +5V external power supply connected to the main
power input (J14), a 2.5 MM. barrel-type plug. Internally, the +5V input is converted into
+1.2V, +1.8V and +3.3V using Texas Instruments swift voltage regulators. The +1.2V
supply is used for the DSP core while the +3.3V supply is used for the DSP's I/O buffers
and other chips on the board. The +1.8 volt supply is used for DM644x I/O, low voltage
memory, and peripherals, and DDR2 memory.
There are four power test points on the EVM; TP14, TP25, TP26, and TP43. These test
points provide a convenient mechanism to check the EVM’s multiple power supplies.
The table below shows the voltages for each test point and what the supply is used for.
Table 2: Power Test Points
Test Point Voltage Voltage Use
TP43 +1.2 V DM644x Core
TP25 +1.2 V DM644x Core/Power Down
TP26 +1.8 V DDR2 Memory, DSP I/O,
and logic
TP14 +3.3V DSP I/O and logic
Spectrum Digital, Inc
1-8 DM644x EVM Technical Reference
2-1
Chapter 2
Board Components
This chapter describes the operation of the major board components on
the DM644x EVM.
Topic Page
2.1 EMIF Interfaces 2-2
2.1.1 DDR2 Memory Interface 2-2
2.1.2 Flash, NAND Flash, SRAM Memory Interface 2-2
2.1.3 ATA Interface 2-2
2.1.4 Compact Flash Interface 2-3
2.1.5 Memory Card Interface 2-3
2.1.6 VLYNQ Interface 2-3
2.1.7 UART Interface 2-3
2.1.8 EMIF Buffer/Decoder Control CPLD 2-3
2.2 Input Video Port Interfaces 2-4
2.2.1 On Chip Video Output DACs 2-4
2.2.2 AIC33 Interface 2-5
2.2.3 Audio PLL/VCXO Circuit/PLL1705 Clock Generator 2-6
2.3 Ethernet Interface 2-7
2.4 I2C Interface 2-7
2.4.1 I/O Expanders 2-8
2.4.2 MSP430 2-9
2.5 SPDIF Analog, and Optical Interfaces 2-9
2.6 Daughter Card Interface 2-10
2.7 DM644x Core CPU Clock 2-10
2.8 USB Clock 2-10
2.9 Battery 2-11
Spectrum Digital, Inc
2-2 DM644x EVM Technical Reference
2.1 EMIF Interfaces
A separate 16 bit EMIF with four chip enables divide up the address space and allow
for asynchronous accesses on the EVM. CE4 and CE5 are reserved for VLYNQ use
allowing the EVM two dedicated chip enables. CE2 is used for Flash, NAND Flash,
SRAM, and xD and SM Media cards. Both CE2 and/or CE3 can be routed to the
daughter card interface connectors.
2.1.1 DDR2 Memory Interface
The DM644x device incorporates a dedicated 32 bit wide DDR2 memory bus. The EVM
uses two gigabit 16 bit wide memories on this bus, for a total of 256 megabytes of
memory for program, data, and video storage. The internal DDR controller uses a
PLL to control the DDR memory timing. The interface supports rates up to 166 Mhz.,
and is clocked on differential edges for optimal performance. Memory refresh for DDR2
is handled automatically by the DM644x internal DDR controller.
2.1.2 Flash, NAND Flash, SRAM Memory Interface
The DM644x has 16 megabytes of NOR Flash, or 64 megabytes of NAND Flash, or
4 megabytes of SRAM memory mapped into the CE2 space. This NOR Flash memory,
and NAND Flash memory are used primarily for boot loading. SRAM is used for
debugging application code. The CE2 space is configured as 16 bits wide on the
DM644x EVM for NOR Flash and SRAM usage, and 8 bit wide for NAND flash usage.
2.1.3 ATA Interface
The DM644x integrates a standard ATA interface on chip. This interface is multiplexed
with the EMIF interface at +1.8 volt levels. The EVM incorporates a standard Lap drive
Hard Disk Drive connector, JP1. Level translators are used to translate the data to
+3.3 volt interface levels and a CPLD is used to translate the control interface to
+3.3V levels. Buffer control is implemented via the CPLD. The drive is selected via I2C
I/O expander U35 bit P6. When the hard drive is in use other peripherals such as the
compact Flash interface and the xD/SM media cards on the EM bus are not accessible
without reconfiguring the EMIF or I2C select lines.
Table 1: EMIF Interfaces
Chip Select Function
CE2 NOR Flash, NAND Flash, SRAM
(see JP4 definition)
CE2 Daughter Card Interface
(see JP4 definition)
CE3 Daughter Card Interface
Spectrum Digital, Inc
2-3
2.1.4 Compact Flash Interface
The EVM incorporates a PIO type Compact Flash interface. The Compact Flash is
selected via I2C expander U35 bit P5. The interface is multiplexed on the EMIF
interface. When the Compact Flash interface is in use other interfaces such as the ATA
or xD/SM card on the EMIF cannot be used without reconfiguring the EMIF or interface
selects.
2.1.5 Memory Card Interface
The EVM supports a number of media card interfaces. On the EMIF the EVM supports
xD/SM interfaces. These are selected via U35 I2C I/O expander. On the peripheral
interface the EVM supports MMC/MS/MSPro/SD.
When the xD/SM interface is used other interfaces such as the ATA or CF interface on
the EMIF cannot be used without reconfiguring the EMIF or interface selects.
2.1.6 VLYNQ Interface
The DM644x brings its internal VLYNQ interface out to a mini PCI connector J16. The
VLYNQ interface is multiplexed on the EM bus and this bus must be reconfigured after
boot up to support VLYNQ. A multiplexer is used to minimize board layout stubs and
allow as direct as possible interface for the VLYNQ signals.
2.1.7 UART Interface
The internal UART0 on the DM644x device is driven to connector J6. The UART’s
interface is level shifted and routed to the RS-232 line drivers prior to being brought
out to a DB-9 connector, J6.
2.1.8 EMIF Buffer/Decoder Control CPLD
The EMIF buffer and decode functions are implemented with a CPLD. The EVM board
incorporates an Altera MAX II EPM240TCG100 device. The device has 2 banks of
I/O. One bank is used for +1.8 volt signals. The other bank is for+3.3 volt signals.
This allows the device to do level shifting.
The CPLD incorporates the ATA control interface, CF control interface, xD/SM control
interface along with a divide by 8 counter for video synchronization. The CPLD also
incorporates various logic functions for buffer control and glue logic.
Spectrum Digital, Inc
2-4 DM644x EVM Technical Reference
2.2 Input Video Port Interfaces
The DM644x EVM supports video capture via the devices internal video ports. A Texas
Instruments TVP5146 is used to decode composite video or S-video inputs into the
device after being level shifted. J11 is used for the S-video inputs and J12 for the
composite inputs on the EVM.
User inputs can be driven via daughter card connector DC4 when the on board level
translator is tristate via driving control Capture Enable signal high on DC4.
2.2.1 On Chip Video Output DACs
The DM644x incorporates 4 output DACs to interface to various output standards. The
DACs are buffered via opamps and driven to a quad RCA jack, J8. The outputs of the
DACs are programmable to support composite video, component video, or RGB.
Figure 2-1, DM644x CPLD Block Diagram
SM/xD
Compact
Flash
IR PWR
SW
S3
Config
DC3 DC2
3V
BAT
DC1 (EMIF)
SD/
MMC/
MS
TI JTAG
MSP430
JTAG
SVHS
IN
USB
VIDEO
IN
AUDIO
IN
HP OUT
AUDIO
OUT
S/PDIF
Optical
S/PDIF
Analog
UART
+5V
MSP430
User LEDs
DC7
DC6
S1 S2
NAND
Flash
1.2V DSP Core Voltage
1.8V I/O Voltage
3.3V Board Supply Voltage
AIC33
J5
I2C
GPIO
I2C
GPIO
I2C
GPIO I2C
EEPROM
D A V I N C I
EVALUATION MODULE
A TEXAS INSTRUMENTS TECHNOLOGY
NOR
Flash
DC4 (VIDEO IN)
TVP
5146 S/PDIF
Drivers
SVHS
OUT
DAC OUT
DC5 (VIDEO OUT)
EMIF
Video Ports
ATA Hard Disk
DDR
I2C
CPLD
Serial Media
DaVinci
ENET
PHY
EMAC
Altera
JTAG
DDR
DDR
10/100
ENET
3% II_ H—fl—fi 0A 4 H
Spectrum Digital, Inc
2-5
2.2.2 AIC33 Interface
The EVM uses a Texas Instruments TLV320AIC33 stereo codec for input and output of
audio signals. The codec samples analog signals on the microphone or line inputs and
converts them into digital data so it can be processed by the DSP. When the DSP is
finished with the data it uses the codec to convert the samples back into analog signals
on the line output so the user can hear the output.
The codec communicates using two serial channels, one to control the codec’s internal
configuration registers and one to send and receive digital audio samples. The I2C bus
is used as the unidirectional control channel. The control channel is generally only used
when configuring the codec, it is typically idle when audio data is being transmitted,
The McBSP is used as the bi-directional data channel. All audio data flows through the
data channel. Many data formats are supported based on the three variables of
sample width, clock signal source and serial data format. The EVM examples generally
use a 16-bit sample width with the codec in master mode so it generates the frame
sync and bit clocks at the correct sample rate without effort on the DSP side.
The codec has a programmable clock from a PLL1705 PLL device. The default system
clock is 18.432 Mhz. The internal sample rate generate subdivides the 18.432 MHz
clock to generate common frequencies such as 48KHz and 8KHz. The sample rate is
set by a codec register. The figure below shows the codec interface on the DM644x
EVM.
Figure 2-2, DM644x EVM CODEC INTERFACE
DOUT
DIN
BCLK
WCLK
MIC IN
LINE IN
LINE OUT
HP OUT
McBSP
I2S Format
AIC33 Codec
Digital Analog
MIC IN
LINE IN
LINE OUT
HP OUT
SCL
SDA
I
2
C
Control
S
CL
S
DA I
2
C Format
D
R
D
X
C
LKR
C
LKX
F
SR
F
SX
Control Registers
ADC
DAC
U
Spectrum Digital, Inc
2-6 DM644x EVM Technical Reference
2.2.3 Audio PLL/VCXO Circuit/PLL1705 Clock Generator
The DM644x EVM implements a multiple PLL clock generator for creating the Audio
clocks for the board.
In streaming video applications the audio and video sequences can lose
synchronization. The DM644x uses a VCXO interpolation circuit to incrementally speed
up or slow down the STCLK input to allow for this synchronization to remain locked.
The PWM0 and timer inputs on DM644x are used to control this feature. The PWM0 pin
drives a PICX100-27W Voltage Controlled Oscillator which is divided by 8 in the CPLD
and fed back into the timer input pin.
The STCLK is also a source clock for the PLL1705 programmable PLL device. This
device creates the clocks for the AIC33 Codec, daughter card VIDCLK an AUDIOCLK.
The PLL1705 is programmable via an I2C and Expander U18. Software sequencing on
the I/O expander is required to interface correctly to the PLL1708’s programmable
inputs.
The diagram below is a simplified diagram of this clocking scheme.
DM644x
VCXO
Circuit Using
PICX100-27
PLL1705
SCK03
SCK02
MCK02
MCK01
XT1
PWM0
IN
P
L
L
M
S
P
L
L
M
C
P
L
L
M
D
To I/O Expander
Figure 2-3, Audio PLL/VCXO Circuit/PLL1705 Clock Generator
STCLK
TIMER
AUDIO_CLK
SCK01
SCK00
CPLD /8
Counter
VID_CLK
Spectrum Digital, Inc
2-7
2.3 Ethernet Interface
The DM644x integrates an ethernet MAC on chip. This interface is routed to the PHY
via CBT switches. The EVM uses an Intel LXT971 PHY. The 10/100 Mbit interface is
isolated and brought out to a RJ-45 standard ethernet connector, P2. The PHY directly
interfaces to the DM644x. The ethernet address is stored in the I2C serial ROM during
manufacturing.
The RJ-45 has 2 LEDs integrated into its connector. The LEDs are green and yellow
and indicate the status of the ethernet link. The green LED, when on, indicates link and
when blinking indicates link activity. The yellow LED, when illuminated, indicates full
duplex mode.
When configuring the PHY use the high drive option in the PHY register 26 to
compensate for the routing length and extra capacitance of the CBT switches.
2.4 I2C Interface
The I2C bus on the DM644x is ideal for interfacing to the control registers of many
devices. On the DM644x EVM the I2C bus is used to configure the video decoder,
stereo Codec, I/O expanders, and communicate with the MSP430. An I2C ROM is also
interfaced via the serial bus. The format of the bus is shown in the figure below.
The addresses of the on board peripherals are shown in the table below.
Table 2: I2C Memory Map
Device Address R/W Function
TVP5146 0x5D R/W Capture 1 Decoder
PCF 8574A 0x38 R/W LEDs
PCF 8574A 0x39 R/W PLL/User Switch
PCF 8574A 0x3A R/W Peripheral Selects
TLV320AIC33 0x1B R/W CODEC
24WC256 0x50 R/W I2C EEPROM
MSP430 0x23 R/W LEDs, IR, RTC
Figure 2-4, I2C Bus Format
Start Slave Address W ACK Sub Address ACK-S Data ACK-S Stop
Write Sequence
Start Slave Address R Data STOP
Read Sequence
Spectrum Digital, Inc
2-8 DM644x EVM Technical Reference
2.4.1 I/O Expanders
The DM644x EVM uses three I2C expanders to handle various bit I/O functions. Each
of these is an bit I/O expander, a PCF8574A. At Power Up Reset the expanders are
initialized to 0xFF, all ones. The functions for each of the I/O expanders are shown in
the tables below.
* - useful as input only
High Input - Switch in “ON” Position
Low Input - Switch in “OFF” Position
Table 3: U2 I/O Expander
Pin Number Function States
P0 User LED DS8 0 = Turns LED On, 1 = Turns LED Off
P1 User LED DS7 0 = Turns LED On, 1 = Turns LED Off
P2 User LED DS6 0 = Turns LED On, 1 = Turns LED Off
P3 User LED DS5 0 = Turns LED On, 1 = Turns LED Off
P4 User LED DS4 0 = Turns LED On, 1 = Turns LED Off
P5 User LED DS3 0 = Turns LED On, 1 = Turns LED Off
P6 User LED DS2 0 = Turns LED On, 1 = Turns LED Off
P7 User LED DS1 0 = Turns LED On, 1 = Turns LED Off
Table 4: U18 I/O Expander
Pin Number Function
P0 PLL Program Interface, PLL CSEL Pin
P1 PLL Program Interface, PLL SR Pin
P2 PLL Program Interface, PLL FS1 Pin
P3 PLL Program Interface, PLL FS2 Pin
P4 Spare IO1
P5 Spare IO2
P6 Spare IO3
P7 User DIP Switch *
Spectrum Digital, Inc
2-9
* Only one interface, ATA or CF, can be enabled at a time
2.4.2 MSP430
The DM644x EVM incorporates infrared remote, real time clock, and some bit I/O in a
MSP430 microcontroller. The I2C interface is used on the DM644x processor to
communicate to the MSP430. The MSP430 acts as a slave device on the I2C bus.
2.5 SPDIF Analog, and Optical Interfaces
The McBSP’s DX pin on the DM644x can be configured to operate as a SPDIF
transmitter. The DM644x EVM supports a single SPDIF output with both analog and
optical interfaces. The analog SPDIF output pin is routed to a level translator then to a
driver and filter circuit before being output on J13. The same level translator is used for
another driver which then drives the optical transmitter U65. When the SPDIF interface
is enabled the TLV320AIC33 codec is disabled.
Table 5: U35 I/O Expander
Pin Number Function State
P0 USB Bus Drive 0 = Enable USB Bus Drive
P1 VDD IMX Enable 0 = Disables VDDIMX supply
P2 VLYNQ 0 = Turns on VLYNQ Mux U11
P3 Compact Flash Reset Drives Reset Low to CF Adapter
P4 Not Used
P5 WLAN Reset 0 = Removes Reset from WLAN
P6 ATA Select *0 = Enables ATA Interface
P7 Compact Flash Select *0 = Enables CF Interface
Spectrum Digital, Inc
2-10 DM644x EVM Technical Reference
2.6 Daughter Card Interfaces
The EVM provides expansion connectors that can be used to accept plug-in daughter
cards. The daughter card allows users to build on their EVM platform to extend its
capabilities and provide customer and application specific I/O. The expansion
connectors are for all major interfaces including memory, peripherals, and video
expansion.
The pin outs for this interface are documented in Section 3.
The memory connector provides access to the DSP’s EMIF signals to interface with
memories and memory mapped devices.
The video capture port is brought out to the daughter card interface. Four signals are
used to disable the on board video peripherals so that they can be used by the
expansion connector. The table below indicates the operation of these signals.
Other than the buffering, most daughter card signals are not modified on the board.
2.7 DM644x Core CPU Clock
The DM644x EVM uses a 27 Megahertz crystal to generate the input clock. The
DM644x has an internal PLL which can multiply the input clock to generate the internal
clock. The PLL multiplier is set via software on the DM644x device.
2.8 USB Clock
The DM644x EVM uses a 24 Mhz crystal for the USB II clock generator. The USB
controller is completely integrated in the DM644x device.
Table 6: Daughter Card Video Enable
Signal State To Enable
Daughter Card
Use
DM644x Signals
Enables
CAPTURE_EN 1 DC4 YI0-YI7
PCLK,VD,HD
McBSP_EN 1 DC3 McBSP
ENET_ENABLE 1 DC2 GIOV33 pins
Spectrum Digital, Inc
2-11
2.9 Battery
The DM644x EVM incorporates a battery holder to provide backup power to the
MSP430’s real time clock when the power is not applied to the board. The optional
battery should be +3 volt 20 millimeter coin type Lithium single cell.
Some common part numbers for batteries which should operate in the EVM are shown
in the table below.
These batteries are available from Duracell, Eveready, Panasonic, Ray-O-Vac, Sanyo,
Sony, Sieko, Toshiba, Varta, and other battery manufacturers.
Table 7: Battery Part Numbers
Part Numbers
CR2032
DL2032
BR2032
CR2025
BR2025
CR2016
BR2016
DL2016
Spectrum Digital, Inc
2-12 DM644x EVM Technical Reference
3-1
Chapter 3
Physical Description
This chapter describes the physical layout of the DM644x EVM and its
interfaces.
Topic Page
3.1 Board Layout 3-3
3.2 Connectors 3-5
3.2.1 J1, Emulation Header 3-6
3.2.2 J2, MSP430 JTAG Header 3-6
3.2.3 J3, SD/MMC/MS Connector 3-7
3.2.4 J4, CS2 Select 3-8
3.2.5 J5, SD/MMC/MS Termination Select 3-8
3.2.6 J6, External RESET Interface 3-9
3.2.7 J7, USB Host/Client Termination 3-9
3.2.8 J8, Dual RCA Jack 3-10
3.2.9 J9, Video Out 3-10
3.2.10 J10, USB Connector 3-11
3.2.11 J11, Video In 3-12
3.2.12 J12, Video In 3-12
3.2.13 J13, SPDIF Out 3-13
3.2.14 J14, +5V Input 3-13
3.2.15 J15, SM/xD Interface 3-14
3.2.16 J16, Mini PCI VLYNQ Interface 3-15
3.2.17 J17, FPGA Programming Header 3-16
3.3 Peripheral Connectors 3-16
3.3.1 P1, Compact Flash Connector 3-17
3.3.2 P2, Ethernet Interface 3-18
3.3.3 P3, Line In/Mic Interface 3-18
3.3.4 P4, Headphone Out 3-19
Spectrum Digital, Inc
3-2 DM644x EVM Technical Reference
Topic Page
3.3.5 P5, Dual Output RCA Jack 3-20
3.3.6 P6, UART0 3-21
3.4 JP1, ATA Interface Connector 3-22
3.5 LEDs 3-23
3.6 Switches 3-23
3.6.1 S1, EMU0/1 Select Switch 3-24
3.6.2 S2, TRSTn Select Switch 3-25
3.6.3 S3, Processor Configuration/Boot Load Options 3-26
3.6.4 S4, RESET 3-27
3.6.5 SW1, Power On/Off 3-27
3.7 Daughter Card Connectors 3-27
3.7.1 DC1, EMIF Expansion Connector 3-28
3.7.2 DC2, GIOV33/Ethernet Connector 3-29
3.7.3 DC3, SPI, McBSP, I2C Connector 3-30
3.7.4 DC4, Video Input Connector 3-31
3.7.5 DC5, Video Output Connector 3-32
3.7.6 DC6, SD Interface Connector 3-33
3.7.7 DC7, Power Connector 3-33
3.8 Test Points 3-34
(D é éuéééggéééé g g é a) E w @
Spectrum Digital, Inc
3-3
3.1 Board Layout
The DM644x EVM is a 8.75 x 4.5 inch (210 x 115 mm.) ten (10) layer printed circuit
board which is powered by an external +5 volt only power supply. Figure 3-1 shows the
layout of the DM644x EVM.
Figure 3-1, DM644x EVM, Interfaces Top Side
SW1
J5
J7
J8
J9
J12
J11
J13
J10 DC1
J17
J14
J4
P1
J2
S4
DC6
DC2
DC3
DC4
DC5
P3
P4
P5
P2
P6
BHT1
S1
J1
S2
DS10
DC7
S3
DS9
J3
DS1-DS8
J6
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Spectrum Digital, Inc
3-4 DM644x EVM Technical Reference
Figure 3-2, DM644x EVM, Interfaces, Bottom Side
JP1
J15
J16
Spectrum Digital, Inc
3-5
3.2 Connectors
The EVM has seventeen (17) connectors providing interfaces to various peripherals.
These connectors are described in the following sections.
Table 1: Connectors
Connector Size Function Board Side
J1 20 Emulation Header Top
J2 2x7 MSP430 JTAG Top
J3 24 SD/MMC/MS Top
J4 8 CS2 Select Top
J5 3 SD/MMC/DC
Termination Select Top
J6 2 External
RESET Interface Top
J7 2 USB Host/Client
Termination Top
J8 8 DAC Connector Top
J9 4 Video Out Top
J10 2 USB Top
J11 4 Video In Top
J12 2 Video In Top
J13 2 SPDIF Out Top
J14 2 +5V In Top
J15 46 SM/xD Bottom
J16 2x62 Mini PCI for VLYNQ Bottom
J17 2x5 CPLD Programming
Header (Factory Use) Top
Spectrum Digital, Inc
3-6 DM644x EVM Technical Reference
3.2.1 J1, Emulation Header
The J1 Emulation Header is located on the top side of the board and is used to provide
an interface to JTAG emulators. The connections for this connector is shown on page
33 of the schematics in appendix A. The pinout for the J1 connector is shown in the
table below.
3.2.2 J2, MSP430 JTAG Header
The J2 MSP430 JTAG Header is located on the top side of the board and is used to
provide a programming interface to the MSP430 microcontroller. The connections for
this connector are shown on page 28 of the schematics in appendix A. The pinout for
the J2 connector is shown in the table below.
Table 2: J1, Emulation Header
Pin # Signal Pin # Signal
1DSP_TMS2 TRSTn
3 DSP_TDI 4 TDIS
5 VCC_1.8V 6 Key-clipped
7 DSP_TDO 8 GND
9 DSP_RTCK 10 GND
11 CTI_TCK 12 GND
13 CTI_EMU0 14 CTI_EMU1
15 EMULATOR_RSTn 16 GND
17 NC 18 NC
19 NC 20 GND
Table 3: J21, MSP430 JTAG Header
Pin # Signal Pin # Signal
1 430_TDO 2 NC
3 430_TDI 4 MSP430_3V3
5 430_TMS 6 NC
7 430_TCK 8 430_TEST/VPP
9GND10
11 NC 12 NC
13 NC 14 NC
Spectrum Digital, Inc
3-7
3.2.3 J3, SD/MMC/MS Connector
The J3 SD/MMC/MS connector is located on the top side of the board and is used to
provide an interface to a SD/MMC/MD card. The connections for this connector is
shown on page 16 of the schematics in appendix A. The pinout for the J3 connector is
shown in the table below.
Table 4: J3, SD/MMC/MS Connector
Pin # Signal Pin # Signal
1 SD_DATA3 2 SD_CMD
3GND4VCC_3.3V
5 SD_CLK 6 GND
7 SD_DATA0 8 SD_DATA1
9 SD_DATA2 10 GND
11 MS.CMD.BS 12 MS.DATA1
13 MS.DATA0 14 MS.DATA2
15 MS.INS/
VCC_3.3V 16 MS.DATA3
17 MS.CLK 18 VCC_3.3V
19 GND 20 VCC_3.3V
21 SD/MMC.INS/
VCC_3.3V 22 GND
23 GND 24
DUDE DEED EDD
Spectrum Digital, Inc
3-8 DM644x EVM Technical Reference
3.2.4 J4, CS2 Select
The J4 connector is actually a 8 position jumper located on the top side of the board
and is used to select the type of memory that the CS2 signal is routed to. The CS2 can
be routed to the four signals shown in the figure below. Only one (1) device can be
selected at a time. To reconfigure this signal, power down the EVM, change the jumper,
and then power the board back up. Do NOT change this jumper with the power on. The
connections for this connector is shown on page 10 of the schematics in appendix A.
3.2.5 J5, SD/MMC/MS Termination Select
The J5 connector is a 3 position jumper located on the top side of the board and is used
to select the termination (ground or VCC_3.3V)for the SD/MMC/MS connector (J3).
Either the +3.3V (1-2 position) or Ground (2-3 position) must be selected. To
reconfigure this termination, power down the EVM, change the jumper, and then power
the board back up. Do NOT change this jumper with the power on. The connections for
this connector are shown on page 16 of the schematics in appendix A.
Table 5: J5, SD/MMC/MS Termination Select
Media Type Position
SD 1-2
MMC 1-2
MS 1-2
MS PRO 2-3
Route EM_CS2 to FLASH_CEz
Route EM_CS2 to SRAM_CEz
Route EM_CS2 to NAND_CEz
Route EM_CS2 to DC_EM_CS2
1
FLASH
SRAM
NAND
DC
J4
Figure 3-3, J4, CS2 Select
1
J5
Figure 3-4, J5, SD/MMC/MS Termination Select
2
3
1
GND
+3.3V
D69
Spectrum Digital, Inc
3-9
3.2.6 J6, External RESET Interface
The J6 connector is a 2 position jumper located on the top side of the board and is used
to externally reset the board. This connector is unpopulated as shipped from the
factory. This circuitry parallels the RESET switch, S4. The connections for this
connector are shown on page 34 of the schematics in appendix A.
3.2.7 J7, USB Host/Client Termination
The J7 connector is a 3 position jumper located on the top side of the board and is used
to select the termination for the USB host/client configuration on USB connector J10.
Either the +3.3V (1-2 position) or Ground (2-3 position) must be selected. This signal
must be terminated. To reconfigure this termination, power down the EVM, change the
jumper, and then power the board back up. Do NOT change this jumper with the power
on. The connections for this connector are shown on page 21 of the schematics in
appendix A.
1
J6
Figure 3-5, J6, External RESET Interface
2GND
PBSW_RSTz
J7
Figure 3-6, J7, USB Host/Client Termination
23
1
GND
+3.3V
USB_ID
O //\ 4/ K,/ .\
Spectrum Digital, Inc
3-10 DM644x EVM Technical Reference
3.2.8 J8, Dual RCA Jack
The J8 connector is a dual RCA jack providing 4 DAC outputs. Do NOT plug into these
connectors with the power on. The figure below shows this connector as viewed from
the card edge. The position of each DAC output is identified. The connections for this
connector are shown on page 25 of the schematics in appendix A.
3.2.9 J9, Video Out
Connector J9 is a four pin mini din connector which interfaces to an output display
device. This connector brings out the DAC B (DAC B-TOP from J8) and DAC C
(DAC C-TOP from J8). Do NOT plug into this connector with the power on. The figure
below shows this connector as viewed from the card edge. The connections for this
connector are shown on page 25 of the schematics in appendix A.
Table 6: J9, Video Out, Mini Din Connector
Pin # Signal Name
1 Ground
2 Ground
3DAC_IOUTB
4DAC_IOUTC
Figure 3-7, J8, Dual RCA Jack
DAC A-BOTTOM
DAC B-TOP
DAC C-TOP
DAC D-BOTTOM
Pin 1 Pin 2
Pin 3 Pin 4
Figure 3-8, J9, Front View, Mini Din Connector
Spectrum Digital, Inc
3-11
3.2.10 J10, USB Connector
Connector J10 is a USB connector. Three different connectors can be mounted at
location J10. The default connector is USB host. The three tables below show the
signals on each possible connector. The connections for this connector are shown on
page 21 of the schematics in appendix A.
Table 7: J10B, USB Peripheral Connector
Pins Signal
1A USB_VBUS
2B USB_DM
3B USB_DP
4B GND
1,2 USB_SHIELD
Table 8: J10B, Mini A-B USB On The Go Connector
Pins Signal
1AB USB_VBUS
2AB USB_DM
3AB USB_DP
4AB USB_ID
5AB GND
5,6,7,8 USB_SHIELD
Table 9: J10C, USB Host Connector
Pins Signal
1A USB_VBUS
2A USB_DM
3A USB_DP
4A GND
3,4 USB_SHIELD
Spectrum Digital, Inc
3-12 DM644x EVM Technical Reference
3.2.11 J11, Video In
Connector J11 is a four pin mini din connector which interfaces to the TVP5146
encoder. This connector brings in a video signal (LUMA) to pin 9 on the TVP5146.
Do NOT plug into this connector with the power on. The figure below shows this
connector as viewed from the card edge. The connections for this connector are shown
on page 24 of the schematics in appendix A.
3.2.12 J12, Video In
J12 is an RCA jack used as a video input to the TVP5146 encoder. This connector
brings in a video signal to pin 8 on the TVP5146. Do NOT plug into this connector with
the power on. The figure below shows this connector as viewed from the card edge.
The connections for this connector are shown on page 24 of the schematics in
appendix A.
Table 10: J11, Video In, Mini Din Connector
Pin # Signal Name
1GND
2GND
3LUMA
4 Chroma
Table 11: J12, Video In, RCA Jack
Pin # Signal Name
1 Pin 8, TVP5146
2GND
Pin 1 Pin 2
Pin 3 Pin 4
Figure 3-9, J11,Front View, Mini Din Connector
Figure 3-10, J12, Video In RCA Jack
Pin 2, Shield (ground)
Pin 1, Signal Input
Spectrum Digital, Inc
3-13
3.2.13 J13, SPDIF Out
J12 is an RCA jack used as an output from the DX signal on the DM644x. This
connector brings out the SPDIF signal. Do NOT plug into this connector with the power
on. The figure below shows this connector as viewed from the card edge. The
connections for this connector are shown on page 27 of the schematics in appendix A.
3.2.14 J14, +5V Input
Connector J14 is the input power connector. This connector bring in +5 volts to the
EVM. This is 2.5mm. jack. Inside of the jack is tied to On/Off power switch SW1.
The other side is tied to ground and LED DS9. The figure below shows this connector
as viewed from the card edge. The connections for this connector are shown on page
34 of the schematics in appendix A.
Table 12: J13, SPDIF, RCA Jack
Pin # Signal Name
1 SPDIF Analog output
2GND
Figure 3-11, J13, SPDIF Out, RCA Jack
Pin 2, Shield (ground)
Pin 1, Signal Output
PC Board
J14
+5V
Ground
Front View
Figure 3-12, J14, +5 Volt Input Connector
Spectrum Digital, Inc
3-14 DM644x EVM Technical Reference
3.2.15 J15, SM/xD Interface
Connector J14 provides an interface to SM/xD memory cards. This connector is located
on the bottom side of the board. Do NOT plug into this connector with the power on.
The table below shows the signals on this connector. The connections for this
connector are shown on page 34 of the schematics in appendix A.
Table 13: J15, SM/xD Interface
Connector
Pin Name EVM
Signal Connector
Pin Name EVM
Signal
SM.I/01 3V3.EM.D0 SM.LVD NC
SM.I/02 3V3.EM.D1 SM.VCC1 VCC_3.3V
SM.I/03 3V3.EM.D2 SM.VCC2 VCC_3.3V
SM.I/04 3V3.EM.D3 SM.VSS1 GND
SM.I/05 3V3.EM.D4 SM.VSS2 GND
SM.I/06 3V3.EM.D5 xD.VSS2 GND
SM.I/07 3V3.EM.D6 xD.CD xD.CD/VCC_3.3V
SM.I/08 3V3.EM.D7 xD.R/B 3V3.WAIT/BUSY
SM.CLE 3V3.CLE_EM_A2 xD.RE 3V3.READ_OE
SM.ALE 3V3.ALE_EM_A1 xD.CE 3V3.SM_CEz
SM.WE 3V3.WRITE_WE xD.CLE 3V3.CLE_EM_A2
SM.WP GND xD.ALE 3V3.ALE_EM_A1
SM.R/B 3V3.WAIT/BUSY xD.WE 3V3.WRITE_WE
SM.RE 3V3.READ.OE xD.WP SM.Xd.wp
SM.CE 3V3.SM_CEz xD.VSS1 GND
SM.CD SM.CD/
VCC_3.3V xD.I/O0 3V3.EM_D0
SM.OPTION GND xD.I/O1 3V3.EM_D1
SM.26 GND xD.I/O2 3V3.EM_D2
SM.25 GND xD.I/O3 3V3.EM_D3
SM.SENS.1 GND xD.I/O4 3V3.EM_D4
SM.SENS.2 GND xD.I/O5 3V3.EM_D5
xD.VCC1 VCC_3.3V xD.I/O6 3V3.EM_D6
xD.VCC2 VCC_3.3V xD.I/O7 3V3.EM_D7
Spectrum Digital, Inc
3-15
3.2.16 J16, Mini PCI VLYNQ Interface
Connector J16 provides an interface to TI supported VNLYNQ cards. This mini-PCI
connector is located on the bottom side of the board. Do NOT plug into this connector
with the power on. The table below shows the signals on this connector. The
connections for this connector are shown on page 32 of the schematics in appendix A.
Table 14: J16, VLYNQ Card Interface
Pin # Signal
1,2,7-9,11-14,17,
18,EMC1,EMC2,
EMC3,EMC4,93,98,
100,112,121,
104-110,113,
115-120,122-124
NC
15,20,23,25,26,27
32,33,34,35,37,41,
42,45-49,50-62,
64-69,71-87,
90-92,94-96,
99,101,102,114
GND
10,111 VCC_1.8V
19,28,31,40,63,70,
88,89,97,103 VCC_3.3V
3 SLP_CLK_EN
4 SLP_REG/WAKEUP
5PM_EN
6WLAN_INTR
16 SD_CLK/VLYNQ_CLK
21 SD_CMD/VLYNQ_RXD0
22 SD_DATA3/VLYQ_RXD1
24 VLYNQ_SCRUN/SD_DATA0
26 1V8.WLAN_RESET
29 VLYNQ_RXD2
30 VLYNQ_RXD3
36 SD_DATA2/VLYNQ_TXD0
38 VLYNQ_TXD2
39 VLYNQ_TXD3
43 SD_DATA1/VLYNQ_TXD1
Spectrum Digital, Inc
3-16 DM644x EVM Technical Reference
3.2.17 J17, FPGA Programming Header
Connector J17 is a 10 pin header that provides a programming interface to the
FPGA, U14. This connector is located on the top side of the board. Do NOT plug into
this connector with the power on. The table below shows the signals on this connector.
This connector is for factory use only. Reprogramming this CPLD affects the
functionality of your EVM.
3.3 Peripheral Connectors
Table 15: J17, FPGA Programming Header
Pin # Signal Pin # Signal
1 ISR_TCK 2 GND
3 ISR_TDO 4 VCC_1.8V
5ISR_TMS6 NC
7NC8NC
9 ISR_TDI 10 GND
Table 16: Peripheral Connectors
Connector Pins Signal Board Side
P1 50 Compact Flash Top
P2 8 Ethernet Top
P3 4 Line In/Mic Top
P4 2 HP Out Top
P5 4 Line Out Top
P6 8 UART0 Top
Spectrum Digital, Inc
3-17
3.3.1 P1, Compact Flash Connector
The P1 connector is located on the top side of the board and is used to provide an
interface to a Compact Flash memory card. This is a 2 x 25 pin male connector. The
connections for this connector is shown on page 19 of the schematics in appendix A.
The pinout for the P1 connector is shown in the table below.
Table 17: P1, Compact Flash Connector
Pin # Signal Pin # Signal
1 GND 2 3V3.EM_D3
3 3V3.EM_D4 4 3V3.EM_D5
5 3V3.EM_D6 6 3V3.EM_D7
7 3V3.CF.ATA_CS0 8 GND
9GND10GND
11 GND 12 GND
13 Pin 3, U10 14 GND
15 GND 16 GND
17 GND 18 3V3.CF.ATA2_EM_A0
19 3V3.CF.ATA1_EM_BA1 20 3V3.CF.ATA0_EM_BA0
21 3V3.EM_D0 22 3V3.EM_D1
23 3V3.EM_D2 24
25 VCC_3.V/3V3.CF_CD2 26 VCC_3.V/3V3.CF_CD1
27 3V3.EM_D11 28 3V3.EM_D12
29 3V3.EM_D13 30 3V3.EM_D14
31 3V3.EM_D15 32 3V3.CF.ATA_CS1
33 NC 34 3V3.CF.READ_OE
35 3V3.CF.WRITE_WE 36 VCC_3.3V
37 3V3.CF.INTRQ_EM_RNW 38 Pin 3, U10
39 GND 40 NC
41 3V3.CF_RESETz 42 3V3.CF.WAIT/BUSY
43 NC 44 VCC_3.3V
45 NC 46 NC
47 3V3.EM_D8 48 3V3.EM_D9
49 3V3.EM_D10 50 GND
Spectrum Digital, Inc
3-18 DM644x EVM Technical Reference
3.3.2 P2, Ethernet Interface
The P2 connector is located on the top side of the board and is used to provide an
Ethernet interface. This is a standard RJ-45 connector. The connections for this
connector is shown on page 22 of the schematics in appendix A. The pinout for the P2
connector is shown in the table below.
3.3.3 P3, Line In/Mic Interface
The P2 connector is provides a stereo input (lower) and microphone input (upper) to
the TVL320AIC33 on the EVM. This connector is located on the top side of the board.
A view of the connector from the card edge is shown in the figure below. The signals
present on this connector are defined in the following table. The connections for this
connector is shown on page 26 of the schematics in appendix A.
Table 18: P2, Ethernet Interface
Pin # Signal Pin # Signal
1 LXT_TDP 2 LXT_TDM
3 LXT_RDP 4 LXT_TDCT
5NC6LXT_RDM
7NC8 GND
9 VCC_3.3V 10 LED1-
11 VCC_3.3V 12 LINKLED-
Table 19: P3, Line In/Mic Interface
Pin # Signal Input
1 Isolated Ground Mic
2 MIC3L/MIC3R Mic
3 MIC3L/MIC3R Mic
4 Isolated Ground Line In
5 LINE1R+/LINE2R+ Line In
6 LINE1L+/LINE2L+ Line In
Figure 3-13, P3, Line In/Mic Interface
MIC
Stereo Line In
(upper)
(lower)
Spectrum Digital, Inc
3-19
3.3.4 P4, Headphone Out
The P4 connector is a stereo headphone output from the TVL320AIC33 on the EVM.
This connector is located on the top side of the board. A view of the connector from the
card edge is shown in the figure below. The signals present on this connector are
defined in the following table. The connections for this connector is shown on page 26
of the schematics in appendix A.
Table 20: P4, Headphone Out Interface
Pin # Signal
1 Isolated Ground
2HPLOUT
3HPROUT
4NC
Figure 3-14, P4, Headphone Out Interface
Stereo Line Out
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3-20 DM644x EVM Technical Reference
3.3.5 P5, Dual Output RCA Jack
The P5 connector is a dual output RCA jack bringing audio from the TVL320AIC33 on
the EVM. This connector is located on the top side of the board. A view of the
connector from the card edge is shown in the figure below. The signals present on this
connector are defined in the following table. The connections for this connector is
shown on page 26 of the schematics in appendix A.
Table 21: P5, Dual Output RCA Jack
Pin # Signal
1 Isolated Ground
2 LEFT_LO+
3RIGHT_LO+
Figure 3-15, P5, Dual Output RCA Jack
WHITE
RED
cocoa coco
Spectrum Digital, Inc
3-21
3.3.6 P6, UART0
The P6 connector is a 9 pin make D-connector which provides a UART interface to the
EVM. This connector interfaces to the MAX 3221 RS-232 line driver (U64) and is
located on the top side of the board. A view of the connector from the card edge is
shown in the figure below. The signals present on this connector are defined in the
following table. The connections for this connector is shown on page 20 of the
schematics in appendix A.
The pin numbers and their corresponding signals are shown in the table below. This
corresponds to a standard dual row to DB-9 connector interface used on personal
computers.
Table 22: P6, UART0 Pinout
Pin # Signal Name Direction
1NC N/A
2S_A_RXD In
3S_A_TXD Out
4NC N/A
5GND N/A
6NC N/A
7S_A_TXD Out
8S_A_TXD Out
9NC N/A
10,11 Earth Ground N/A
9
54321
876
Figure 3-16, P6, DB9 Male Connector
Spectrum Digital, Inc
3-22 DM644x EVM Technical Reference
3.4 JP1, ATA Interface Connector
The JP1 connector is located on the bottom side of the board and is used to provide an
ATA interface to a hard disk drive. This is a 2 x 22 pin male connector. The connections
for this connector is shown on page 18 of the schematics in appendix A. The pinout for
the JP1 connector is shown in the table below.
Table 23: JP1, ATA Interface
Pin # Signal Pin # Signal
1 ATA RESETn 2 GND
3 ATA.DD7 4 ATA.DD8
5 ATA.DD6 6 ATA.DD9
7 ATA.DD5 8 ATA.DD10
9 ATA.DD4 10 ATA.DD11
11 ATA.DD3 12 ATA.DD12
13 ATA.DD2 14 ATA.DD13
15 ATA.DD1 16 ATA.DD14
17 ATA.DD0 18 ATA.DD15
19 GND 20 NC
21 ATA.DMARQ 22 GND
23 ATA.DIOW 24 GND
25 ATA.DIOR 26 GND
27 ATA.IORDY 28 ATA_CSEL, TP34
29 ATA.DMACK 30 GND
31 ATA.INTRQ 32 GND
33 ATA.DA1 34 TP33
35 ATA.DA0 36 ATA.DA2
37 ATA.CS0 38 ATA.CS1
39 ATA.DASPn 40 GND
41 VCC_5V 42 VCC_5V
43 GND 44 NC
Spectrum Digital, Inc
3-23
3.5 LEDs
The EVM has ten (10) LEDs which are located on the top side of the board. Eight of
these LEDs (DS1-8) are under user control and addressed over the I2C bus. One LED
(DS9) indicates the presence of +5 volts on the board. The remaining LED (DS10)
indicates a hard disk drive is plugged into the EVM. Additional information regarding
the LEDs are shown in the table below.
3.6 Switches
The EVM has five (5) switches. The function of these switches are shown in the table
below.
Table 24: LEDs
LED # Use Color Schematic
Page
DS1 User Defined Green 27
DS2 User Defined Green 27
DS3 User Defined Green 27
DS4 User Defined Green 27
DS5 User Defined Green 27
DS6 User Defined Green 27
DS7 User Defined Green 27
DS8 User Defined Green 27
DS9 +5V Green 34
DS10 +3.3V Red 18
Table 25: Switches
Switch Function Type Board
Side Schematic
Page
S1 EMU0/1 Selection DIP Top 33
S2 TRSTn Select DIP Top 33
S3 Boot
Configuration
Options DIP Top 10
S4 RESET Push button Top 34
SW1 Power On/Off Toggle Top 34
W
Spectrum Digital, Inc
3-24 DM644x EVM Technical Reference
3.6.1 S1, EMU0/1 Select Switch
S1 is a 2 position DIP switch providing 4 options in selecting the state of the EMU0 and
EMU1 pins on the processor. The connections for this switch are shown on page 33
of the schematics in appendix A. A view of the switch is shown in the figure below. The
selection options with this switch are in the table below.
* is the factory shipped configuration
Table 26: S1, EMU0/1 Select
State at Reset
EMU0 EMU1 Function
L L Emulation Debug ARM JTAG Enabled
L H Not Defined
H L Not Defined
H H Emulation Debug *
Both ARM & DSP JTAG Enabled
Figure 3-17, S1, EMU0/1 Select Switch
EMU0
EMU1
H
H
L
L
S1
M
Spectrum Digital, Inc
3-25
3.6.2 S2, TRSTn Select Switch
S2 is a 2 position DIP switch providing 4 options in selecting the state of the TRST
signal for JTAG emulation. The connections for this switch are shown on page 33
of the schematics in appendix A. A view of the switch is shown in the figure below. The
selection options with this switch are in the table below.
* is the factory shipped configuration
Table 27: S2, TRST Select
Switch Position Function
A Right TRST Pull up
A Left TRST Pull down *
B Right TRST low on power up
Reset
B Left Delay via capacitor
(capacitor not populated) *
Figure 3-18, S2, TRST Select
TRSTn
TRSTn
S2 A
B
EEEEE
Spectrum Digital, Inc
3-26 DM644x EVM Technical Reference
3.6.3 S3, Processor Configuration/Boot Load Options
S2 is a 10 position DIP switch providing 9 options in selecting the processor
configuration and boot load modes. when a switch is in the “ON” position the specific
function is selected. The connections for this switch are shown on page 10 of the
schematics in appendix A. A view of the switch is shown in the figure below. The
selection options with this switch are in the table below.
Table 28: S3, Processor Configuration/Boot Load Options
Position Name Function
1 COUT0 Bootmode 0
2 COUT1 Bootmode 1
3 COUT2 Bus width: 0=8 bit, 1=16 bit
4 COUT3 0=ARM boots DSP,
1=C64xx self boots
5YOUT4
6YOUT3
7YOUT2
8YOUT1
9YOUT0
10 USER For Demos
Figure 3-19, S3, Processor Configuration/
COUT0
S3
ON
12345678910
COUT1
COUT2
COUT3
YOUT4
YOUT3
YOUT2
YOUT1
YOUT0
SPARE
Boot Load Options
Spectrum Digital, Inc
3-27
3.6.4 S4, RESET
Switch S4 is a push button rest switch that will RESET the processor. This switch is in
parallel with J6. The connections for this switch are shown on page 34 of the
schematics in appendix A.
3.6.5 SW1, Power On/Off
Switch S1 is a toggle switch that provides power to the EVM. The connections for this
switch are shown on page 34 of the schematics in appendix A.
3.7 Daughter Card Connectors
The EVM has seven connectors that are available for daughter card connections.
These connectors make many of the signals on the EVM available to be used by
external logic. The signals on each of the connectors are described in the following
tables. The table below lists the connectors.
Table 29: Daughter Card Connectors
Connector Size Function Board
Side Schematic
Page
DC1 2x35 EMIF Top 29
DC2 2x20 GIOV33/Ethernet Top 31
DC3 2x15 SPI, McBSP, I2CTop 31
DC4 2x20 Video In Top 30
DC5 2x25 Video Out Top 30
DC6 2x5 SD Interface Top 31
DC7 2x5 Power Top 35
Spectrum Digital, Inc
3-28 DM644x EVM Technical Reference
3.7.1 DC1, EMIF Expansion Connector
Table 30: DC1, EMIF Expansion Connector
Pin # Signal Pin # Signal
1 B.EM_A21 2 B.EM_A20
3 B.EM_A19 4 B.EM_A18
5 B.EM_A17 6 B.EM_A16
7 B.EM_A15 8 B.EM_A14
9GND10GND
11 B.EM_A13 12 B.EM_A12
13 B.EM_A11 14 B.EM_A10
15 B.EM_A9 16 B.EM_A8
17 B.EM_A7 18 B.EM_A6
19 GND 20 GND
21 B.EM_A5 22 B.EM_A4
23 B.EM_A3 24 CLE_EM_A4
25 B.EM_A1 26 ATA2_EM_A0
27 GND 28 GND
29 ATA_CS1 30 ATA_CS0
31 ATA1_EM_BA1 32 ATA0_EM_BA0
33 WRITE_WE 34 READ_OE
35 WAIT/BUSY 36 INTRQ_EM_RNW
37 GND 38 GND
39 EM_D15 40 EM_D14
41 EM_D13 42 EM_D12
43 EM_D11 44 EM_D10
45 GND 46 GND
47 EM_D9 48 EM_D8
49 EM_D7 50 EM_D6
51 EM_D5 52 EM_D4
53 GND 54 GND
55 EM_D3 56 EM_D2
57 EM_D1 58 EM_D0
59 EM_CS3 60 DC_EM_CS2
61 1.8V.SYS_RESETz 62 CLKOUT0
63 GND 64 GND
65 VCC_3.3V 66 VCC_3.3V
67 GND 68 GND
69 VCC_5V 70 VCC_1.8V
Spectrum Digital, Inc
3-29
3.7.2 DC2, GIOV33/Ethernet Connector
Table 31: DC2, GIOV33/Ethernet Connector
Pin # Signal Pin # Signal
1GND2GND
3 GIOV33_0 4 GIOV33_1
5 GIOV33_2 6 GIOV33_3
7 GIOV33_4 8 GIOV33_5
9GND10GND
11 GIOV33_6 12 GIOV33_7
13 GIOV33_8 14 GIOV33_9
15 GIOV33_10 16 GIOV33_11
17 GND 18 GND
19 GIOV33_12 20 GIOV33_13
21 GIOV33_14 22 GIOV33_15
23 GIOV33_16 24 GND
25 GND 26 3V3.SYS_RESETz
27 ENET_ENABLEz 28 GND
29 VCC_1.8V 30 3V3.UART_RXD1
31 VCC_1.8V 32 3V3.UART_TXD1
33 GND 34 GND
35 VCC_3.3V 36 VCC_3.3V
37 VCC_5V 38 VCC_5V
39 GND 40 GND
Spectrum Digital, Inc
3-30 DM644x EVM Technical Reference
3.7.3 DC3, SPI, McBSP, I2C Connector
Table 32: DC3, SPI, McBSP, I2C Connector
Pin # Signal Pin # Signal
1 SPI_EN1 2 SPI_EN0
3 SPI_DI 4 SPI_DO
5 SPI_CLK 6 TIMER_IN_DC3
7GND8GND
9DR10DX
11 CLKR 12 CLKX
13 FSR 14 FSX
15 GND 16 GND
17 1.8V.SYS_RESETz 18 1.8V.I2C_CLK
19 McBSP_EN 20 1.8V.I2C_DATA
21 AUDIO_CLK 22 GND
23 GND 24 1.8V_DC3_PCLK
25 VCC_3.3V 26 VCC_3.3V
27 GND 28 GND
29 VCC_5V 30 VCC_1.8V
Spectrum Digital, Inc
3-31
3.7.4 DC4, Video Input Connector
Table 33: DC4, Video Input Connector
Pin # Signal Pin # Signal
1 1.8V.SYS_RESETz 2 CAPTURE_EN
3GND4GND
5GIO16GIO4
7GND8GND
9 PWM110PWM2
11 GND 12 GND
13 Y10 14 Y11
15Y1216Y13
17Y1418Y15
19Y1620Y15
21 GND 22 GND
23 GND 24 HD
25 PCLK/1V8.DC_PCLK 26 VD
27 GND 28 GND
29CI030CI1
31CI232CI3
33CI434CI5
35CI636CI7
37 GND 38 GND
39 1V8.I2C_CLK 40 1V8.I2C_DATA
41 VCC_1.8V 42 VCC_1.8V
43 GND 44 GND
45 VCC_3.3V 46 VCC_3.3V
47 GND 48 GND
49 VCC_5V 50 VCC_5V
Spectrum Digital, Inc
3-32 DM644x EVM Technical Reference
3.7.5 DC5, Video Output Connector
Table 34: DC5, Video Output Connector
Pin # Signal Pin # Signal
1GIO02GIO2
3GIO34GIO5
5GIO66GIO38
7GND8GND
9COUT010COUT1
11 COUT2 12 COUT3
13 COUT4 14 COUT5
15 COUT6 16 COUT7
17 GND 18 GND
19 VPBECLK/VID_CLK 20 HSYNC
21 GND 22 GND
23 VCLK 24 VSYNC
25 GND 26 GND
27 YOUT0 28 YOUT1
29 YOUT2 30 YOUT3
31 YOUT4 32 YOUT5
33 YOUT6 34 YOUT7
35 GND 36 GND
37 1.8V.I2C_CLK 38 1.8V.SYS_RESETz
39 1.8V.I2C_DATA 40 GND
41 VCC_1.8V 42 VCC_1.8V
43 GND 44 GND
45 VCC_3.3V 46 VCC_3.3V
47 GND 48 GND
49 VCC_5V 50 VCC_5V
Spectrum Digital, Inc
3-33
3.7.6 DC6, SD Interface Connector
3.7.7 DC7, Power Connector
Table 35: DC6, SD Interface Connector
Pin # Signal Pin # Signal
1 SD_CLK 2 SD_CMD
3GND4GND
5 SD_DATA0 6 SD_DATA1
7 SD_DATA2 8 SD_DATA3
9GND10GND
Table 36: DC7, Power Connector
Pin # Signal Pin # Signal
1 VDDIMX_EN 2 GND
3 DSP_CORE_SUPPLY 4 DSP_CORE_SUPPLY
5 GND 6 GND
7 VCC_1.8V 8 VCC_1.8V
9GND10GND
Spectrum Digital, Inc
3-34 DM644x EVM Technical Reference
3.8 Test Points
The EVM has 63 test points. All test points appear on the top of the board. The
following figure identifies the position of each test point. the next table list each test
point and the signal appearing on that test point.
Figure 3-20, DM644x EVM, Test Points
TP1
TP9
TP8
TP7
TP6
TP3
TP5
TP2
TP4
TP10
TP11
TP19
TP20
TP21
TP22
TP14
TP25
TP15
TP16
TP17
TP26
TP18
TP27
TP28
TP29
TP31
TP30
TP33
TP35
TP37
TP32
TP34
TP42
TP36
TP40 TP38
TP39
TP41
TP43
TP46
TP49
TP44
TP45
TP47
TP48
TP53
TP54
TP55
TP56
TP57
TP60
TP63
TP58
TP59
TP61
TP62
TP65
TP66
TP69
TP64
TP67
TP68
TP70
Spectrum Digital, Inc
3-35
Table 37: DM644x EVM Test Points
Test Point
#Signal Schematic
Page Test Point
#Signal Schematic
Page
TP1 GND 4,34 TP36
TP2 GND 34 TP37 U27,U38,PIN 4,VCC_3.3V 35
TP3 GND 34 TP38 GND 4
TP4 U4,P24,P1.3/TA2 28 TP39 U28A,DDR_VSS.DLLVCC_1
.8V 4
TP5 VCC_5V 34 TP40 VCC_1.8V 4
TP6 GND 4 TP41 DSP_CORE_VDD 9
TP7 U28A,DDR_AMUX.DLL TP42 U28D,VDD.10
DSP_CORE_VDD 9
TP8 U28E,PLLPWR18
VCC_1.8V 8 TP43 DSP_CORE_VDD 35
TP9 GND 8 TP44
TP10 U28E,AMUX 8 TP45 GND
TP11 U28D,VDDS1.14
VCC_1.8V 9TP46 U28H,
USB_VDDA1P8PHY
VCC_1.8V
7
TP14 +3.3V 34 TP47 VCC_1.8V 7
TP15 TP48 VCC_3.3V 7
TP16 3V3_PWR_OK 34 TP49 U28H,
USB_VDDA3P3PHY
VCC_3.3V
7
TP17 GND 4 TP53 VCC_1.8V 5
TP18 U28E,APLLREFV
DSP_CORE_VDD 8 TP54 U28G,VDDA18V
VCC_1.8V 5
TP19 VCC_1.8V 8 TP55 U28G,VDDA11
DSP_CORE_VDD 5
TP20 DSP_CORE_VDD 8 TP56 U51,Pin 36 24
TP21 VCC_1.8V 9 TP57 U51,Pin 37 24
TP22 U28D,VDDSHV.4
VCC_3.3V 9 TP58 U58,PIN 64,MDINT 22
TP25 DSP_CORE_VDDIMX 35 TP59
TP26 VCC_1.8V 35 TP60
TP27 GND 34 TP61 DSP_CORE_VDD 5
TP28 JP1,Pin 28, ATA_CSEL 18 TP62 U51,Pin 30 24
TP29 TP63 U52,A8,MPF2 26
TP30 U28D,VDDIMX.11
DSP_CORE_VDDIMX 9 TP64 U52,A9,MPF3 26
TP31 DSP_CORE_VDDIMX 9 TP65 U52,C8,SCL 26
TP32 VCC_3.3V 9 TP66 U28I,GIO45/PWM0
VCC_1.8V 5
TP33 JP1, Pin 34 18 TP67 VIN, U54,PIN 3 5
TP34 TP68 GND 34
TP35 TP69 U52,J9,GPIO1 26
TP70 GND 34
Spectrum Digital, Inc
3-36 DM644x EVM Technical Reference
A-1
Appendix A
Schematics
This appendix contains the schematics for the DaVinci EVM.
Spectrum Digital, Inc
A-2 DM644x EVM Technical Reference
5
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C C
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A A
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D
SPECTRUM DIGITAL INCORPORATED
508162-0001
Monday, March 06, 2006 1 35
B
DAVINCI EVALUATION MODULE
Title Block
SCHEMATIC CONTENTS
01 DAVINCI EVM TITLE SHEET
02 DAVINCI EVM BLOCK DIAGRAM
03 DAVINCI EMIF INTERFACE
04 DAVINCI DDR INTERFACE
05 DAVINCI VIDEO INTERFACE
06 DAVINCI I/O INTERFACE
07 DAVINCI USB & SD/MMC/MS CONTROLLER
08 DAVINCI EMULATION & CLOCKS
09 DAVINCI POWER PINS
10 DAVINCI CONFIGURATION CONTROL/BOOT OPTIONS
11 DDR2 MEMORY
12 SRAM/NAND FLASH
13 NOR FLASH
14 EMIF LEVEL SHIFTER
15 EMIF CPLD MULTIPLEXER
16 SD/MMC/MS CONNECTOR
17 SM/xD CONNECTOR
18 ATA INTERFACE
19 COMPACT FLASH CONNECTOR
20 RS232 INTERFACE
21 USB 2.0 INTERFACE
22 ETHERNET INTERFACE
23 TVP5146 LEVEL SHIFTER
24 TVP5416 VIDEO DECODER
25 VIDEO OUT
26 AIC33 AUDIO INTERFACE
27 SPDIF OUTPUTS & USER LEDS
28 MSP430 & IR INTERFACE
29 EMIF EXPANSION CONNECTOR
30 VIDEO INPUT/OUTPUT CONNECTORS
31 EMAC/GIO & McBSP/SPI & SD CONNECTORS
32 VLYNQ CONNECTOR
33 DAVINCI EMULATION HEADER
34 POWER SUPPLY ( 3.3V ) & SYSTEM RESET LOGIC
35 POWER SUPPLY ( 1.8V & DSP_CORE) & EVM POWER CONNECTOR
REV
ENGR
2
REVISION STATUS OF SHEETS
1
11
SH
DATE
14 12 13
DATE
ENGR-MGR
MFG
7
DWN
DATE
8
DATE
10
SH
DATE
CHK
RLSE
APPLICATION
REV
35
NEXT ASSY
DATE
6
DATE
9
QA
USED ON
4
15
AAABBAA
BDAAA
R.R.P.
T.W.K.
R.R.P.
R.R.P.
C.M.D.
R.R.P.
R.R.P.
02/17/2005
02/17/2005
16 17 18 19 20
21 22 23 24 25 02/17/2005
02/17/2005
03/01/2004
02/17/2005
02/17/2005
REV
SH
BBAAA
BBB
DBB
AAAAA
AADA
26 27 28 29 30
AA
31 32 33 34
A Initial schematic ready for layout - Alpha Release
DESCRIPTIONREV APPROVEDDATE
02/17/05 RRP
4. ALL 0.1 uF AND 0.01uF CAPACITORS ARE DECOUPLING CAPS UNLESS
OTHERWISE NOTED. THEY ARE SHOWN ON THE PAGE WITH THE INTEGRATED
CIRCUITS THEY SHOULD BE PLACED NEAR.
NOTES, UNLESS OTHERWISE SPECIFIED:
1. RESISTANCE VALUES IN OHMS.
2. CAPACTITANCE VALUES IN MICROFARADS.
3. REFERENCE DESIGNATORS USED:
5. OBSERVE THE FOLLOWING LAYOUT NOTES:
1. TOP - SIGNAL ROUTING
2. GROUND PLANE
3. INNER1 - SIGNAL ROUTING
4. VCC3 PLANE (3.3V BOARD)
5. INNER2 - SIGNAL ROUTING
6. INNER3 - SIGNAL ROUTING
7. VCC PLANE 2
8. INNER4 - SIGNAL ROUTING
9. GROUND PLANE
10. BOTTOM - SIGNAL ROUTING
6. BOARD PROPERTIES
B1. General layers 50 +/- 5 OHM MATCHED IMPEDANCE
C. OUTER LAYERS 0.5 OZ CU /W 0.5 OZ AU PLATING
D. INNER LAYERS 1.0 OZ CU
E. FR4 BOARD MATERIAL
F. MINIMUM TRACE WIDTH/SPACING 4 MILS
G. MINIMUM VIA SIZE 10/19 MIL
H. LAYER STACKUP:
A. ROUTE TO WITHIN 10% OF MANHATTAN DISTANCE
B2. USB layer 90 ohm differential
35
D
BBeta Release RRP09/27/05
I2C ADDRESS TABLE
IO EXPANDER 0
IO EXPANDER 1
IO EXPANDER 2
I2C ROM
AIC33
TVP5146
MSP430
0x50
BASE
0x1B
0x5D
0x23
0x38 (LED)
0x39 (PLL/USER_SW)
0x3A (USB/CD_RESET)
SHEET
26
24
28
28
28
28
6
CGamma Release RRP10/28/05
DProduction Release 02/18/06 RRP
Spectrum Digital, Inc
A-3
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D D
C C
B B
A A
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A
SPECTRUM DIGITAL INCORPORATED
508162-0001
Wednesday, November 16, 2005 2 35
B
DAVINCI EVALUATION MODULE
DAVINCI BLOCK DIAGRAM
DaVinci
SH:3-9
DDR2 IF
SH:4
SH:12
NAND Flash (64MB)
SH:13
NOR Flash (16MB)
SH:12
SRAM (4MB)
SH:14
Switch
SH:32
VLYNQ Connector
SH:16
SD/MMC/MS Connector
SH:25
(4) DAC Video Outputs
SH:30
DC #5 Connector
SH:31
DC #3 Connector
SH:27
SPDIF Outputs
SH:7
Switch
SH:26
Stereo Codec
(AIC33)
SH:31
DC #3 Connector
SH:30
DC #4 Connector
SH:5
VCXO/PLL
(Audio & Video
Clock Generation)
SH:17
SMC/xD Connector
SH:19
Compact Flash Connector
SH:14,15
1.8V to 3.3V
Level Shifters
SH:18
ATA Connector
SH:33
Emulator Header
SH:29
DC #1 Connector
SH:11
DDR2 SDRAM (256MB)
SH:21
USB 2.0 IF
SH:22
Ethernet IF
SH:30
DC #4 Connector
SH:31
DC #2 Connector
SH:22
Switch
SH:6
EEPROM
SH:27
(8) LEDs
SH:23
Level Shifter
& Switch
SH:20
UART
(Debug Term)
SH:24
Video Decoder
(TVP5146)
SH:28
MSP430
IR/RTC/SC
Emulator
SH:8
USB 2.0
SH:7
Image In
SH:5
UART1
SH:3
I2C
SH:6
SH:28
Resistor
Pop Option
SH:6
EMAC/
GPIOs
UART0
SH:6
SH:31
DC #6 Connector
Config Control &
EM_CS2 Select
SH:10
Power Supply (3.3V)
& System Reset Logic
SH:34
Power Supply (1.8V & DSP Core)
& DC #7 Connector
SH:35
EMIF/VLYNQ
SH:3
SD/MMC/MS
SH:7
(4) DACs
SH:5
Video Out
SH:5
PWM0
SH:5
Timer In
SH:8
PWM [2:1]
SH:5
SPI
SH:6
McBSP
SH:7
Power Pins
SH:9
SH:8
Crystal/Osc
SH:8
PLLs
fii H H
Spectrum Digital, Inc
A-4 DM644x EVM Technical Reference
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5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
EM_D15
EM_D11
EM_D13
EM_D9
EM_D5
EM_D7
EM_D3
EM_D1
EM_A21
EM_A16
EM_A18
EM_A20
EM_A14
EM_A8
EM_A6
EM_A10
EM_A4
EM_A12
EM_A19
EM_A17
EM_A15
EM_A13
EM_A11
EM_A9
EM_A7
EM_A5
EM_A3
EM_D14
EM_D12
EM_D8
EM_D4
EM_D6
EM_D2
EM_D0
EM_D10
CPU.VLYNQ_CLK VLYNQ_SCRUN
VLYNQ_CLK
CPU.VLYNQ_CLK
VCC_1.8V
VCC_1.8V
EM_D[0:15] 12,13,14,29 EM_A[3:21] 12,13,14,29
CLE_EM_A2 12,13,15,29
ALE_EM_A1 12,13,15,29
ATA2_EM_A0 12,13,15,29
ATA1_EM_BA1 12,13,15,29
ATA_CS0 15,29
ATA_CS1 15,29
READ_OE 12,13,15,29
WRITE_WE 12,13,15,29
EM_CS2 10,15
EM_CS3 29
ATA0_EM_BA0 15,29
INTRQ_EM_RNW15,29
UART_TXD1/DMACK 15
VLYNQ_CLK 32
VLYNQ_SCRUN 32
WAIT/BUSY15,29
INTRQ_EM_RNW 15,29
UART_RXD1/DMARQ 15
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B
SPECTRUM DIGITAL INCORPORATED
508162-0001
Wednesday, November 16, 2005 3 35
B
DAVINCI EVALUATION MODULE
DAVINCI EMIF INTERFACE
R180 22
R168 22
U28B
DAVINCI-BGA_24
EM_D14/HD14
H5 EM_D13/HD13
F2 EM_D12/HD12
D1 EM_D11/HD11
G4 EM_D10/HD10
G5 EM_D09/HD09
E2
EM_D15/HD15
E1
EM_D08/HD08
F3
EM_D07/HD07
C1 EM_D06/HD06
F4 EM_D05/HD05
D2 EM_D04/HD04
E4 EM_D03/HD03
E3 EM_D02/HD02
F5 EM_D01/HD01
D3 EM_D00/HD00
E5
INTRQ_EM_RNW/HRNW G3
WAIT_BUSYN/HRDYN
F1
READ_OE/HDS1N H4
WRITE_WE/HDS2N G2
UART_TXD1/DMACK H3
UART_RXD1/DMARQ G1
GIO8/VLYNQ_CLK/EM_CS5 T1
EM_CS2/HCSN C2
EM_CS3/HASN B1
GIO9/VLYNQ_SCRUN/EM_CS4 T2
EM_BA1/ATA1_BA1/GIO52 H2
CLE_EM_A2/HCNTLA J1
GIO28/EM_A3 K2
GIO27/EM_A4 K4
GIO26/EM_A5 K3
GIO25/EM_A6 N1
GIO24/EM_A7 N2
GIO23/EM_A8 N3
GIO22/EM_A9 M4
GIO21/EM_A10 P1
GIO20/EM_A11 P2
GIO/19EM_A12 R1
GIO18/EM_A13 N4
GIO17/VLYNQ_RXD3/EM_A14 P4
GIO16/VLYNQ_TXD3/EM_A15 P3
GIO15/VLYNQ_RXD2/EM_A16 R5
GIO14/VLYNQ_TXD2/EM_A17 R2
GIO13/VLYNQ_RXD1/EM_A18 P5
GIO12/VLYNQ_TXD1/EM_A19 R4
GIO11/VLYNQ_RXD0/EM_A20 R3
EM_BA0/ATA0_BA0/HINTN J3
ATA_CS0/GIO50 J5
ATA_CS1/GIO51 H1
GIO10/VLYNQ_TXD0/EM_A21 T3
ALE_EM_A1/HHWIL J2
EM_A0/ATA2_EM_A0/GIO53/HCNTLB J4
RN8 RPACK8-10
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
R173 22
R170 22
R171
243
C170
NO-POP
R172 22
R174 22
R167 22
RN7 RPACK8-10
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
R203 22
RN3 RPACK8-10
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
RN2 RPACK8-10
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
R169 22
R161
1K
C171
NO-POP
R179 22
R394
NO-POP
R175 22
RN9 RPACK8-10
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
Spectrum Digital, Inc
A-5
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR_D8
DDR_D12
DDR_D14
DDR_D6
DDR_D25
DDR_D16
DDR_D26
DDR_D19
DDR_D21
DDR_D20
DDR_D22
DDR_D23
DDR_D28
DDR_D31
DDR_D27
DDR_D17
DDR_D29
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D7
DDR_D9
DDR_D10
DDR_D11
DDR_D13
DDR_D15
DDR_D18
DDR_D24
DDR_D30
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_BS00
DDR_BS01
DDR_BS02
DDR_CS
DDR_CLK
DDR_CLK_N
DDR_DQS0
DDR_DQM0
DDR_DQS1
DDR_DQS2
DDR_DQS3
DDR_DQM3
BDDR_A0
BDDR_A3
BDDR_A4
BDDR_A5
BDDR_A6
BDDR_A7
BDDR_BS02
BDDR_BS01
BDDR_BS00
BDDR_A8
BDDR_A9
BDDR_A10
BDDR_A11
BDDR_A12
BDDR_DQS0
BDDR_DQS1
BDDR_DQS2
BDDR_DQS3
BDDR_DQM0
BDDR_DQM1
BDDR_DQM2
BDDR_DQM3
BDDR_CS
BDDR_CLK
BDDR_CLK_N
BDDR_CKE
DDR_DQM2
DDR_DQM1
VREF_STL
BDDR_A1
BDDR_A2
DDR_RAS
DDR_CKE
DDR_WE
DDR_CAS
BDDR_WE
BDDR_RAS
BDDR_CAS
VCC_1.8V
DDR_D[0:31]11 DDR_A[0:12] 11
DDR_DQM0 11
DDR_DQS2 11
DDR_CAS 11
DDR_CLK 11
DDR_CS 11
DDR_CLK_N 11
DDR_WE 11
DDR_RAS 11
DDR_CKE 11
DDR_DQS3 11
DDR_DQS1 11
DDR_DQS0 11
DDR_DQM3 11
DDR_BS02 11
DDR_BS01 11
DDR_BS00 11
DDR_DQM1 11
DDR_DQM2 11
VREF_STL11
Size:
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A
SPECTRUM DIGITAL INCORPORATED
508162-0001
Wednesday, November 16, 2005 4 35
B
DAVINCI EVALUATION MODULE
DAVINCI DDR INTERFACE
SURFACE MOUNT TEST POINT PADS
USED FOR VERIFYING DDR TIMINGS
ROUTE CLOCK DIFFERENTIAL WITH 15 MIL SPACING BETWEEN
PLACE RESISTOR BY DATA TERMINATOR PINS
BALANCE LINE LENGTHS WITH DATA BYTES LENGTHS
RN17 RPACK4-47
1
2
3
4 5
6
7
8
R51 47
R53 0.22
R206 47
R33 47
TP7
1
R182 47
C189
0.1uF
TP17
1
RN13RPACK4-47
1
2
3
45
6
7
8
R181 47
R218 0
TP38
1
C190
1uF
L10
BLM21PG221SN1D
1 2
R221 47
TP45
1
C216
0.22uF
RN12 RPACK4-47
1
2
3
4 5
6
7
8
RN10 RPACK4-47
1
2
3
4 5
6
7
8
R219 200 TP40
1
U28A
DAVINCI-BGA_24
DDR_A00 W13
DDR_A01 U13
DDR_A02 V13
DDR_A03 U12
DDR_A04 V12
DDR_A05 W12
DDR_A06 W11
DDR_A07 V11
DDR_A08 V10
DDR_A09 U11
DDR_A10 U10
DDR_A11 W10
DDR_A12 W9
DDR_BS00 U8
DDR_CS T9
DDR_CLK_N W8
DDR_WE T8
DDR_CLK W7
DDR_CKE V8
DDR_ZP T13
DDR_ZN T12
DDR_VSS.DLL T11
DDR_VDD.DLL T10
DDR_CAS T7
DDR_RAS U7
DDR_D00
U1
DDR_D01
U2
DDR_D02
V1
DDR_D03
V2
DDR_D04
W2
DDR_D05
U3
DDR_D06
V3
DDR_D07
W3
DDR_D08
V4
DDR_D09
W4
DDR_D010
U5
DDR_D11
V5
DDR_D12
W5
DDR_D13
V6
DDR_D14
W6
DDR_D15
V7
DDR_D16
W14
DDR_D17
V14
DDR_D18
W15
DDR_D19
V15
DDR_D20
U15
DDR_D21
W16
DDR_D22
V16
DDR_D23
T17
DDR_D24
V17
DDR_D25
U17
DDR_D26
U18
DDR_D27
W17
DDR_D28
V18
DDR_D29
W18
DDR_D30
V19
DDR_D31
U19
DDR_BS01 V9
DDR_BS02 U9
DDR_AMUX.DLL R8
DDR_DQS0 U4
DDR_DQS1 U6
DDR_DQM0 T4
DDR_DQM1 T6
DDR_DQS3 U16
DDR_DQS2 U14
DDR_DQM2 T14
DDR_DQM3 T16
VREFSTL
T15
TP39
1
TP6
1
R205 47
RN11 RPACK4-47
1
2
3
4 5
6
7
8
R52 47
R32 47
R41 47
R220 47
R204 200
Spectrum Digital, Inc
A-6 DM644x EVM Technical Reference
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VREF_0.5V VREF_1.24V
VCC_1.8V
VCC_3.3V
VCC_1.8V
DSP_CORE_VDD
VCC_1.8V
VCC_1.8V
VCC_3.3V
VCC_3.3V
VCC_3.3V
VCC_3.3V
VCC_3.3V
COUT0 10,30
COUT2 10,30
COUT4 30
YOUT0 10,30
YOUT2 10,30
VSYNC 30
COUT1 10,30
COUT3 10,30
HSYNC 30
YOUT1 10,30
YOUT3 10,30
COUT6 30
COUT7 30
COUT5 30
YOUT5 30
YOUT4 10,30
YOUT6 30
YOUT7 30
VPBECLK 30
VCLK 30
PWM1 30
PWM2 30
HD23,30
VD23,30
CI530
CI730
CI430
CI630
CI330 CI230 CI130 CI030
YI423,30
YI623,30
YI323,30
YI523,30
YI223,30 YI123,30 YI023,30
PCLK23,30
YI723,30
DAC_IOUTA 25
DAC_IOUTB 25
DAC_IOUTC 25
DAC_IOUTD 25
AUDIO_CLK 26,31
VID_CLK 30
3V3.DC_PCLK27
PLL.FS228 PLL.FS128
PLL.SR28
PLL.CSEL28
CPLD_TIMER_IN 15
Size:
Date:
DWG NO Revision:
Sheet o f
Title:
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C
SPECTRUM DIGITAL INCORPORATED
508162-0001
Wednesday, November 16, 2005 5 35
B
DAVINCI EVALUATION MODULE
DAVINCI VIDEO INTERFACE
VREF =1.24 VOLTS
R236 22
TP67
1
R294 NO-POP
R233 22
R243
0
R303 100K
C310
NO-POP
R291 33
Q1
2N3904
U28G
DAVINCI-BGA_24
DAC_IOUTA P19
DAC_IOUTB P18
DAC_IOUTC R19
DAC_IOUTD T19
VSSA11
T18
VSSA18
P17
DAC_VREF R17
VDDA18V
R18
DAC_RBIAS R16
VDDA11
P16
R365 33
TP66
1
C231
.001uF
C271
NO-POP
U28I
DAVINCI-BGA_24
CI7/CCD15/UART_RXD2
N19
CI6/CCD14/UART_TXD2
N18
CI5/CCD13/UART_CTS2
N17
CI4/CCD12/UART_RTS2
N16
CI3/CCD11
N15
CI2/CCD10
M17
CI1/CCD09
M16
CI0/CCD08
M15
YI7/CCD07
L18
YI6/CCD06
L17
YI5/CCD05
L16
YI4/CCD04
L15
YI3/CCD03
K19
YI2/CCD02
K18
YI1/CCD01
K17
YI0/CCD00
K16
PCLK
M19
HD
M18
VD
L19
GIO47/PWM2/B2 A15
GIO46/PWM1/R2 B15
YOUT7 E18
YOUT6 E17
YOUT5 E16
YOUT4/AEAW4 E15
YOUT3/AEAW3 D18
YOUT2/AEAW2 D17
YOUT1/AEAW1 D16
YOUT0/AEAW0 D15
COUT7 C16
COUT6 B19
COUT5 B18
COUT4 A18
COUT3/DSP_BT B17
COUT2/8_16 A17
COUT1/BTSEL1 B16
COUT0/BT_SEL0 A16
VCLK D19
VSYNC C18
HSYNC C17
VBECLK C19
GIO45/PWM0 C15
TP53
1
C230
.1uF
R292 33
TP61
1
R302
0
R297 33
RN21 RPACK8-33
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
C232
.1uF
R241 7.5K
U57
SN74AUC1G125
3
4
5
2
1
R232 22
R293 NO-POP
R300
10K
C235
1uF
C233
.001uF
RN18 RPACK8-33
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
TP55
1
C312
10pF
R298
10K
C267
0.1uF
U55
PLL1705
VDD1 1
VDD2 13
XT1
10
XT2
11
VDD3 20
VCC 8
DGND1 4
DGND2 16
SR
7
FS2
6
FS1
5
SCKO1 19
AGND 9
DGND3 17
SCKO3 3
SCKO0 18
SCKO2 2
MCKO2 15
MCKO1 14
CSEL
12
+
C66
10uF
R295 NO-POP
R216 22
C270
0.1uF
+
C65
10uF
L22
BLM21PG221SN1D
12
C269
0.1uF
R299
10K
U56
SN74AUC1G125
3
4
5
2
1
R63 0.22
R62 0.22
TP54
1
R240
4.99K
C272
0.1uF
R304
2.2K
R290 33R234 22
R301
NO-POP
C273
100pF
R194 22
L21
BLM21PG221SN1D
12
R244
NO-POP
+C71
10 uF
R366 33
C268
0.1uF
R296
10K
R307
1K
R239 4.02K
Y5
27MHz
U39
TLV431ADBV
5 3
4
R242
1K
C234
.1uF
R305 22.1K 1%
U54
PI6CX100-27W
X1
1X2 8
GND
4VIN
3VDD 6
CLKOUT 5
NC1
2NC2 7
C311
0.1uF
C266
0.1uF
C265
0.1uF
Spectrum Digital, Inc
A-7
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
I2C_CLK
I2C_DATA
UART_RXD0
UART_TXD0
3V3.I2C_CLK
3V3.I2C_DATA
1V8.MSP430_INT
VCC_1.8V
VCC_3.3V
VCC_3.3VVCC_3.3V
VCC_1.8V
VCC_1.8V
1V8.I2C_CLK 26,30,31
GIO3 30
GIO6 30
GIO0 30
GIO2 30
GIO5 30
GIO38 30
GIO4 30
GIO1 30
GIOV33_0 22,31
GIOV33_2 22,31
GIOV33_4 22,31
GIOV33_6 22,31
GIOV33_8 22,31
GIOV33_10 22,31
GIOV33_12 22,31
GIOV33_14 22,31
GIOV33_16 22,31
GIOV33_1 22,31
GIOV33_3 22,31
GIOV33_5 22,31
GIOV33_7 22,31
GIOV33_9 22,31
GIOV33_11 22,31
GIOV33_13 22,31
GIOV33_15 22,31
SPI_EN1 31
SPI_EN0 31
SPI_CLK 31
SPI_DI 31
SPI_DO 31
3V3.I2C_CLK 24,27,28
3V3.I2C_DATA 24,27,28
UART_RXD0 20
UART_TXD0 20
1V8.I2C_DATA 26,30,31
1V8.MSP430_INT15
ATA_DIR 15
Size:
Date:
DWG NO Revision:
Sheet o f
Title:
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B
SPECTRUM DIGITAL INCORPORATED
508162-0001
Wednesday, November 16, 2005 6 35
B
DAVINCI EVALUATION MODULE
DAVINCI I/O INTERFACE
EEPROM ( 32KBytes )
R424
10K
U34
24WC256
A0
1VCC 8
VSS
4NC
3SCL 6
SDA 5
A1
2WP 7
U28C
DAVINCI-BGA_24
GIOV33.1/TXCLK A13
GIOV33.2/COL A12
GIOV33.3/TXD0 B12
GIOV33.13/RXER D10
GIOV33.4/TXD1 D12
GIOV33.5/TXD2 A11
GIOV33.6/TXD3 C12
GIOV33.7/RXD0 E12
GIOV33.14/CRS C10
GIOV33.8/RXD1 C11
GIOV33.9/RXD2 B11
GIOV33.10/RXD3 E11
GIOV33.11/RXCLK A10
GIOV33.15/MDIO E10
GIOV33.12/RXDV D11
GIOV33.0/TXEN B13
GIO0/LCD_OE C13
GIO1/C_WEN E13
GIO2/G0 D13
GIO3/LCD_FIELD/B0 C14
GIO4/C_FIELD/R0 B14
GIO5/G1 E14
GIO6/B1 A14
GIO44/I2C_DATA B4
GIO38/R1 D14
GIO43/I2C_CLK C4
GIO36/UART_TXD0 C5
GIO35/UART_RXD0 D5
GIO41/SPI_DO A2
GIO37/SPI_EN0 A4
GIO42/SPI_EN1/ATADIR B2
GIO39/SPI_CLK A3
GIO7 C3
GIOV33.16/MDC B10
GIO40/SPI_DI B3
R212
2.2K
R201 22
C162
0.1uF
C194
0.1uF
R211
2.2K
R215
2.2K
R197 22
C195
0.1uF
R198 22
R214
2.2K
R213
100K
VREF2
GND
VREF1
ENABLE
SCL1
SDA1
SCL2
SDA2
U33
PCA9306
7
6
2
8
3
1
54
RN14 RPACK4-22
1
2
3
4 5
6
7
8
R410
10K
P —<>—w H F‘
Spectrum Digital, Inc
A-8 DM644x EVM Technical Reference
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VCC_3.3V
VCC_1.8V
VCC_3.3V
SD_CLK 16,31,32
SD_DATA0 16,31,32
SD_CMD 16,31,32
SD_DATA1 16,31,32
SD_DATA3 16,31,32
SD_DATA2 16,31,32
CLKR 31
FSR 31
DR 31
DX 27,31
FSX 31
CLKX 31
USB_ID 21
USB_VBUS 21
B_CLKR 26
B_FSR 26
B_DR 26
B_DX 26
B_FSX 26
B_CLKX 26
McBSP_EN31
USB_DM 21
USB_DP 21
Size:
Date:
DWG NO Revision:
Sheet o f
Title:
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B
SPECTRUM DIGITAL INCORPORATED
508162-0001
Wednesday, November 16, 2005 7 35
B
DAVINCI EVALUATION MODULE
DAVINCI USB & SD/MMC/MMC CONTROLLER
Place C206 as close to device as possible, between 2 to 5 millimeters
U53 is a switch used for DC3 to allow the McBSP
to be disconnected from on-board circuitry.
Signal levels are at 1.8 Volt logic levels on both
sides of switch
Place R217 as close to device as possible
C274
0.1uF
R60 0.22 R308
10K
RN15
RPACK4-22
1
2
3
4 5
6
7
8
RN16 RPACK4-22
1
2
3
4 5
6
7
8
C209
0.1uF
R309
360
R199 22
TP48
1
TP49
1
C211
0.01uF
U28H
DAVINCI-BGA_24
USB_VDDA3P3PHY
J19
USB_VSSA3P3PHY
J18
USB_VDDA1P8PHY
H17
USB_VSSA1P8PHY
H16
USB_DP G19
USB_ID J16
USB_VBUS J17
USB_VDDA1P2LDOPHY
G18
USB_VSS_REF_PHY G16
USB_DM H19
USB_R1 H18
R196 22
R200 22
U53
74CBTLV3245
A1
2B1 18
A2
3B2 17
A3
4B3 16
A4
5B4 15
A5
6B5 14
A6
7B6 13
A7
8B7 12
A8
9B8 11
G
19
NC
1VCC 20
GND 10
U28F
DAVINCI-BGA_24
GIO31/FSX C8
GIO32/FSR C7
GIO29/CLKX B8
GIO30/CLKR A8
GIO33/DX B7
GIO34/DR A7
SD_DATA1/MS_DATA1 E9
SD_DATA0/MS_DATA0 D8
SD_DATA2/MS_DATA2 D9
SD_DATA3/MS_DATA3 C9
SD_CMD/MS_BS B9
SD_CLK/MS_CLK A9
R217
10K
C206
1uF
TP47
1
L15
BLM21PG221SN1D
1 2
L13
BLM21PG221SN1D
1 2
R195 22
TP46
1
C212
0.1uF
+
C59
10uF
+
C60
10uF
C207
0.01uF
R61 0.22
Spectrum Digital, Inc
A-9
VCC_1.8V
VCC_1.8V
VCC_1.8V
VCC_1.8V
VCC_1.8V
DSP_CORE_VDD
DSP_EMU033
DSP_EMU133
DSP_TRST#33
DSP_TDO33
DSP_TDI33
DSP_TMS33
DSP_RTCK33
DSP_TCK33
TIMER_IN15
1.8V.SYS_RESETz13,15,26,29,30,31,34
CLKOUT0 29
Size:
Date:
DWG NO Revision:
Sheet of
Title:
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B
SPECTRUM DIGITAL INCORPORATED
508162-0001
Wednesday, November 16, 2005 8 35
B
DAVINCI EVALUATION MODULE
DAVINCI EMULATION & CLOCKS
OPTIONAL OSCILLATOR POPULATION
CRYSTAL AND CAPS REMOVED WHEN
OSCILLATOR IS USED
R235 NO-POP
TP8
1
R178 NO-POP
C227
.1uF
EIA0402
C141
.1uF
EIA0402
R177 0
C144 18pF
TP20
1
R237 0
C140
1000pF
C229 18pF
R238
NO-POP
R176
NO-POP
C147
1uF
C148
1uF
TP18
1
TP19
1
C139 18pF U12
NO-POP/27 MHz
VCC
4
OUT
3GND 2
EN 1
TP10
1
Y3
24MHz
L5
BLM21PG221SN1D
1 2
L2
BLM21PG221SN1D
1 2
Y2
27MHz
U28E
DAVINCI-BGA_24
TCK
A6
TMS
E6
TRST
D7
TDI
A5
TDO
B5
EMU1
C6
EMU0
D6
RESET
L4
M24X0 F19
M24GND F17
M24XI F18
GIO49/CLKOUT1/TIM_IN E19
GIO48/CLKOUT0 K1
RTCK
B6
MX0 M1
MXI L1
MXGND L2
APLLREFV
M3
AMUX
L3
PLLPWR18
M2
R35 0.22
U40
NO-POP/24 MHz
VCC
4
OUT
3GND 2
EN 1
C142
0.1uF
C138
0.1uF
TP9
1
L6
BLM21PG221SN1D
1 2
R34 0.22
C228 18 pF
C137
1000pF
L14
BLM21PG221SN1D
1 2
¥4v 407 >— H»— >— H»— >— H»— >— H»— ~ ~0~ >— —(H >— HP — » H—4 1H HH w H—Hu H}— —0— ,7 WW 5 H %»H w» w AH ,—
Spectrum Digital, Inc
A-10 DM644x EVM Technical Reference
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CPU_DSP_CORE_VDDIMX
CPU_VCC_3.3V
CPU_DSP_CORE_VDD
CPU_VCC_1.8V
CPU_VCC_1.8V
CPU_VCC_1.8V
CPU_VCC_1.8V
CPU_VCC_1.8V
CPU_DSP_CORE_VDDIMX
CPU_VCC_3.3V
CPU_DSP_CORE_VDD
VCC_3.3V
VCC_1.8V
DSP_CORE_VDD
DSP_CORE_VDDIMX
Size:
Date:
DWG NO Revision:
Sheet o f
Title:
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A
SPECTRUM DIGITAL INCORPORATED
508162-0001
Wednesday, November 16, 2005 9 35
B
DAVINCI EVALUATION MODULE
DAVINCI POWER PINS
R42 0.025
C205
0.1uF
C183
0.1uF
R54 0.025
+C30
22uF
C185
0.1uF
C214
0.1uF
C179
0.1uF
TP21
1
C199
0.1uF
C210
0.1uF
C146
0.1uF
C202
0.1uF
C188
0.1uF
+C40
22uF
+C31
22uF
+C47
22uF
C178
0.1uF
C136
0.1uF
+C27
22uF
C184
0.1uF
R36 0.025
C177
0.1uF
C175
0.1uF
C176
0.1uF
TP31
1
C180
0.1uF
+C58
22uF
C111
0.1uF
C186
0.1uF
+
C125
NO-POP C203
0.1uF
TP22
1
C143
0.1uF
C134
0.1uF
C215
0.1uF
+C48
22uF
C145
0.1uF
C135
0.1uF
C113
0.1uF
+
C130
NO-POP
C167
0.1uF
C181
0.1uF
TP42
1
C174
0.1uF
TP11
1
C187
0.1uF
U28D
DAVINCI-BGA_24
VDDS.1
E7 VDDS.2
F6 VDDS.3
F8 VDDS.4
F14 VDDS.5
F16 VDDS.6
G7 VDDS.7
G9 VDDS.8
G15 VDDS.9
H6 VDDS.10
H14 VDDS.11
J7 VDDS.12
J15 VDDS.13
K6 VDDS.14
K14 VDDS.15
L5 VDDS.16
L7 VDDS.17
L13 VDDS.18
M6 VDDS.19
M14
VDDIMX.1
H8 VDDIMX.2
H10 VDDIMX.3
H11 VDDIMX.4
H12 VDDIMX.5
J9 VDDIMX.6
J10 VDDIMX.7
J11 VDDIMX.8
J13 VDDIMX.9
K8 VDDIMX.10
K9 VDDIMX.11
K11
VDD.1
F15 VDD.2
K10 VDD.3
K12 VDD.4
L8 VDD.5
L9 VDD.6
L10 VDD.7
L11
NC.3 A19
PORDIS
D4
VSS.20 K5
VSS.21 K7
VSS.22 K13
VSS.23 K15
VSS.24 L6
VSS.25 L12
VSS.26 L14
VSS.27 M5
VSS.28 M7
VSS.29 M9
VSS.30 M11
VSS.31 M13
VSS.32 N6
VSS.33 N8
VSS.34 N10
VSS.35 N12
VSS.36 N14
VSS.37 P7
VSS.38 P9
VSS.39 P11
VSS.40 P13
VSS.41 P15
VSS.42 R6
VSS.43 R7
VSS.44 R10
VSS.45 R12
VSS.14 H13
VSS.15 H15
VSS.16 J6
VSS.17 J8
VSS.18 J12
VSS.19 J14
VSS.1 E8
VSS.2 F7
VSS.3 F9
VSS.7 G11
VSS.9 G13
VSS.4 G6
VSS.8 G12
VSS.10 G14
VSS.11 G17
VSS.12 H7
VSS.13 H9
VDDS1.1
N7 VDDS1.2
N9 VDDS1.3
N11 VDDS1.4
N13 VDDS1.5
P6 VDDS1.6
P8 VDDS1.7
P10 VDDS1.8
P12 VDDS1.9
P14 VDDS1.10
R9 VDDS1.11
R11 VDDS1.12
R13 VDDS1.13
R15
VDD.8
M8 VDD.9
M10 VDD.10
M12
VDDSHV.1
F10 VDDSHV.2
F11 VDDSHV.3
F12 VDDSHV.4
F13
VSS.5 G8
VSS.6 G10
VDDS.20
N5
VSS.46 R14
NC.4 W19
VDDS1.14
T5
NC.1 A1
NC.2 W1
TP41
1
R37 0.025
+C28
22uF
+
C132
NO-POP
C200
0.1uF
C204
0.1uF
C168
0.1uF
C201
0.1uF
C115
0.1uF
C208
0.1uF
+C49
22uF
C213
0.1uF
C182
0.1uF
R202 0
TP30
1
TP32
1
+C127
NO-POP
C169
0.1uF
+C29
22uF
fifififififififififi
Spectrum Digital, Inc
A-11
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VCC_1.8V
YOUT0 5,30
YOUT1 5,30
YOUT2 5,30
YOUT3 5,30
YOUT4 5,30
EM_CS23,15
NAND_CEz 12
SRAM_CEz 12
FLASH_CEz 13
DC_EM_CS2 29
COUT3 5,30
COUT2 5,30
COUT1 5,30
COUT0 5,30
USER_SW 28
Size:
Date:
DWG NO Revision:
Sheet o f
Title:
Page Contents:
A
SPECTRUM DIGITAL INCORPORATED
508162-0001
Wednesday, November 16, 2005 10 35
B
DAVINCI EVALUATION MODULE
DAVINCI CONFIGURATION CONTROL/BOOT OPTIONS
BOOT CONFIGURATION SWITCH
ONLY ONE DEVICE CAN BE SELECTED
AT A TIME AT POWER UP.
TO RECONFIGURE BOARD
POWER DOWN EVM,
CHANGE JUMPER TO DESIRED DEVICE.
11 = Boot from ROM (UART)
1 = GEM Self-Boots
PINS FUNCTION SWITCH S1
Selects ARM Boot Mode
BTSEL[1:0] 00 = Boot from ROM (NAND)
01 = Boot from AEM IF
10 = Boot from ROM (HPI)
Non-secure device
COUT[1:0]
MODE
Selects AEM IF CS2 Bus Width
8_16COUT2 0 = 8-bit
1 = 16-bit
S1-2=XXX S1-1=XXX
S1-3=XXX
S1-3=XXX
S1-2=XXX S1-1=XXX
S1-2=XXX S1-1=XXX
S1-2=XXX S1-1=XXX
COUT3 DSP_BT
0 = ARM boots GEM S1-4=XXX
S1-4=XXX
YOUT[4:0] AEAW [4:0]
Address Bus Width
DSP BOOT
S1-5=XXX
S1-6=XXX
S1-7=XXX
S1-8=XXX
ALL ADDRESS LINES GPIO
S1-9=XXX
SPARE SWITCH
R230 1K
R227
10K
R229 1K
1
2
3
4
5
6
7
8
9
10
S3
DIP_SWITCH-10
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
RN29 RPACK8-1K
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
R228
NO-POP
RN28
RPACK8-NO-POP
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
J4
CONN 4x2
2
4
6
8
1
3
5
7
» AH-(h fi— AL—w H“ ‘ 4H“ 4H“ w w H H \ —0—U‘ —H ‘ —0—(h —<>—w —H—w —H—w { 1 “ T ‘ H W ‘ H \ ‘ \HHHHH H H W *HAU ‘ fi— —
Spectrum Digital, Inc
A-12 DM644x EVM Technical Reference
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR_A10
DDR_A8
DDR_A7
DDR_A1
DDR_A9
DDR_A5
DDR_A0
DDR_A6
DDR_A2
DDR_A11
DDR_A12
DDR_A3
DDR_A4DDR_A4
DDR_A3
DDR_A12
DDR_A11
DDR_A2
DDR_A6
DDR_A0
DDR_A5
DDR_A9
DDR_A1
DDR_A7
DDR_A8
DDR_A10
DDR_BS00
DDR_BS01
DDR_BS02DDR_BS02
DDR_BS01
DDR_BS00
DDR_CLK_N
DDR_CLK
DDR_CS
DDR_CLK
DDR_CLK_N
DDR_CAS
DDR_CKE
DDR_RAS
DDR_WE
DDR_DQS0
DDR_DQM0
DDR_DQS1
DDR_DQS2
DDR_DQM1 DDR_DQM2
DDR_DQM3
DDR_CS
DDR_RAS
DDR_CKE
DDR_CAS
DDR_WE
DDR_DQS3
VREF_STL
VREF_STL
DDR_D12
DDR_D14
BDDR_D15
BDDR_D14
BDDR_D13
BDDR_D12
BDDR_D11
BDDR_D10
BDDR_D9
BDDR_D8
BDDR_D7
BDDR_D6
BDDR_D5
BDDR_D4
BDDR_D3
BDDR_D2
BDDR_D1
BDDR_D14
BDDR_D12
DDR_D28
DDR_D29
DDR_D30
BDDR_D31
BDDR_D30
BDDR_D29
BDDR_D27
BDDR_D28
BDDR_D26
BDDR_D25
BDDR_D24
BDDR_D23
BDDR_D22
BDDR_D21
BDDR_D20
BDDR_D19
BDDR_D18
BDDR_D17
BDDR_D16
BDDR_D29
BDDR_D30
BDDR_D28
DDR_D2
DDR_D0
BDDR_D2
BDDR_D0
BDDR_D0
DDR_D9
DDR_D11BDDR_D11
BDDR_D9
DDR_D31
DDR_D24
BDDR_D31
BDDR_D24
BDDR_D13 DDR_D15
DDR_D13
BDDR_D15
DDR_D10
DDR_D8
BDDR_D10
BDDR_D8
DDR_D6
DDR_D4
BDDR_D6
BDDR_D4
DDR_D1
DDR_D3
BDDR_D1
BDDR_D3 BDDR_D17
BDDR_D19
BDDR_D20
BDDR_D22
BDDR_D27
BDDR_D25 DDR_D27
DDR_D25
BDDR_D16
BDDR_D18 DDR_D16
DDR_D18
BDDR_D23
BDDR_D21
DDR_D23
DDR_D21
BDDR_D5
BDDR_D7 DDR_D7
DDR_D5
BDDR_D26 DDR_D26
DDR_D17
DDR_D19
DDR_D22
DDR_D20
BDDR_D[0:15] BDDR_D[16:31]
VCC_1.8V
VCC_1.8VVCC_1.8V
DDR_D[0:31]4
DDR_A[0:12]4
DDR_BS024DDR_BS014DDR_BS004
DDR_WE4DDR_CKE4
DDR_CLK4
DDR_RAS4
DDR_CLK_N4
DDR_CAS4DDR_CS4
DDR_DQM24DDR_DQM34
DDR_DQS24
DDR_DQS14
DDR_DQS04
DDR_DQM14DDR_DQM04
VREF_STL 4
DDR_DQS34
Size:
Date:
DWG NO Revision:
Sheet o f
Title:
Page Contents:
A
SPECTRUM DIGITAL INCORPORATED
508162-0001
Wednesday, November 16, 2005 11 35
B
DAVINCI EVALUATION MODULE
DDR2 MEMORY
128 MEGABYTES 128 MEGABYTES
RN31 RPACK4-47
1
2
3
4 5
6
7
8
U20
MT47H64M16BT
A12
V2
A11
U7
A10
R2
A9
U3
A8
U8
A7
U2
A6
T7
A5
T3
A4
T8
A3
T2
A2
R7
A1
R3
A0
R8
BA2
P1
BA1
P3
BA0
P2
NC.1
AA9
NC.2
AA8
NC.3
AA2
NC.4
AA1
NC.5
D2
NC.6
V8
NC.7
A9
NC.8
A8
NC.9
A2
NC.10
A1
NC.11
H2
RFU.1
V3
RFU.2
V7
ODT
N9
CS#
P8
CAS#
P7
RAS#
N7
WE#
N3
CKE
N2
CK
M8
CK#
N8
UDQS#/NU
D8
UDQS
E7
LDQS#/NU
H8
LDQS
J7
UDM
E3
LDM
J3
VDD.1 M9
VDD.2 H1
VDD.3 R9
VDD.4 D1
VDD.5 V1
VDDQ.1 F3
VDDQ.2 F7
VDDQ.3 K1
VDDQ.4 K3
VDDQ.5 K7
VDDQ.6 K9
VDDQ.7 D9
VDDQ.8 F1
VDDQ.9 F9
VDDQ.10 H9
VDDL M1
VREF M2
DQ15 E9
DQ14 E1
DQ13 G9
DQ12 G1
DQ11 G3
DQ10 G7
DQ9 F2
DQ8 F8
DQ7 J9
DQ6 J1
DQ5 L9
DQ4 L1
DQ3 L3
DQ2 L7
DQ1 K2
DQ0 K8
VSS.1 U9
VSS.2 T1
VSS.3 H3
VSS.4 D3
VSS.5 M3
VSSQ.1 G8
VSSQ.2 J8
VSSQ.3 D7
VSSQ.4 J2
VSSQ.5 E2
VSSQ.6 L8
VSSQ.7 L2
VSSQ.8 E8
VSSQ.9 H7
VSSQ.10 G2
VSSDL M7
RN26 RPACK4-47
1
2
3
4 5
6
7
8
U32
MT47H64M16BT
A12
V2
A11
U7
A10
R2
A9
U3
A8
U8
A7
U2
A6
T7
A5
T3
A4
T8
A3
T2
A2
R7
A1
R3
A0
R8
BA2
P1
BA1
P3
BA0
P2
NC.1
AA9
NC.2
AA8
NC.3
AA2
NC.4
AA1
NC.5
D2
NC.6
V8
NC.7
A9
NC.8
A8
NC.9
A2
NC.10
A1
NC.11
H2
RFU.1
V3
RFU.2
V7
ODT
N9
CS#
P8
CAS#
P7
RAS#
N7
WE#
N3
CKE
N2
CK
M8
CK#
N8
UDQS#/NU
D8
UDQS
E7
LDQS#/NU
H8
LDQS
J7
UDM
E3
LDM
J3
VDD.1 M9
VDD.2 H1
VDD.3 R9
VDD.4 D1
VDD.5 V1
VDDQ.1 F3
VDDQ.2 F7
VDDQ.3 K1
VDDQ.4 K3
VDDQ.5 K7
VDDQ.6 K9
VDDQ.7 D9
VDDQ.8 F1
VDDQ.9 F9
VDDQ.10 H9
VDDL M1
VREF M2
DQ15 E9
DQ14 E1
DQ13 G9
DQ12 G1
DQ11 G3
DQ10 G7
DQ9 F2
DQ8 F8
DQ7 J9
DQ6 J1
DQ5 L9
DQ4 L1
DQ3 L3
DQ2 L7
DQ1 K2
DQ0 K8
VSS.1 U9
VSS.2 T1
VSS.3 H3
VSS.4 D3
VSS.5 M3
VSSQ.1 G8
VSSQ.2 J8
VSSQ.3 D7
VSSQ.4 J2
VSSQ.5 E2
VSSQ.6 L8
VSSQ.7 L2
VSSQ.8 E8
VSSQ.9 H7
VSSQ.10 G2
VSSDL M7
C224
0.1uF
+C57
22 uF
C154
0.1uF
C217
0.1uF
C222
0.1uF
C220
0.1uF
C152
0.1uF C218
0.1uF
RN27 RPACK4-47
1
2
3
4 5
6
7
8
R208
1K 1%
+C18
22 uF +C102
NO-POP
RN19 RPACK4-47
1
2
3
4 5
6
7
8
RN6 RPACK4-47
1
2
3
4 5
6
7
8
RN20 RPACK4-47
1
2
3
4 5
6
7
8
C151
0.1uF C221
0.1uF
C157
0.1uF
C149
0.1uF
C156
0.1uF
RN5 RPACK4-47
1
2
3
4 5
6
7
8
R207
1K 1%
C225
0.1uF
RN30 RPACK4-47
1
2
3
4 5
6
7
8
C150
0.1uF
C223
0.1uF
C155
0.1uF
C219
0.1uF
C153
0.1uF
HM 1 \ \h W
Spectrum Digital, Inc
A-13
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
EM_A7
EM_A6
EM_A9
EM_A4
B.EM_A11
B.EM_A10
EM_A5
EM_A8
EM_A3
B.EM_A16
B.EM_A15
B.EM_A13
B.EM_A12
B.EM_A17
B.EM_A14
B.EM_A19
B.EM_A18
ATA2_EM_A0
ATA1_EM_BA1
SRAM_CE2
EM_D2
EM_D8
EM_D5
EM_D0
EM_D2
EM_D3
EM_D4
EM_D4
EM_D14
EM_D15
EM_D5
EM_D3
EM_D7
EM_D12
EM_D1
EM_D6
EM_D13
EM_D6
EM_D0
EM_D11
EM_D10
EM_D9
EM_D7
EM_D1
CLE_EM_A2
CLE_EM_A2
ALE_EM_A1
ALE_EM_A1
WRITE_WE
READ_OE
READ_OE
WRITE_WE
VCC_1.8V
VCC_1.8V
VCC_1.8V
VCC_1.8V
VCC_1.8V
VCC_1.8V
EM_A[3:21]3,13,14,29
ATA2_EM_A03,13,15,29 ALE_EM_A13,13,15,29
WRITE_WE3,13,15,29
CLE_EM_A23,13,15,29
SRAM_CEz10
ATA1_EM_BA13,13,15,29
READ_OE3,13,15,29
NAND_CEz10
EM_D[0:15] 3,13,14,29
NAND_BUSY15
B.EM_A[10:21]13,14,29
Size:
Date:
DWG NO Revision:
Sheet o f
Title:
Page Contents:
A
SPECTRUM DIGITAL INCORPORATED
508162-0001
Wednesday, November 16, 2005 12 35
B
DAVINCI EVALUATION MODULE
SRAM/NAND FLASH
SRAM ( 4MBytes )
NAND FLASH ( 64MBytes )
K9K1G08 supports 128 MEGABYTES
R137
10K
R141
10K
C90
0.1uF
R135
10K
U7
SAMSUNG->K1S3216BCD
DQ16 G1
DQ1 B6
DQ2 C5
DQ3 C6
DQ4 D5
DQ5 E5
DQ6 F5
DQ7 F6
DQ8 G6
DQ9 B1
DQ10 C1
DQ11 C2
DQ12 D2
DQ13 E2
DQ14 F2
DQ15 F1
A0
A3 A1
A4 A2
A5 A3
B3 A4
B4 A5
C3 A6
C4 A7
D4 A8
H2 A9
H3 A10
H4 A11
H5
VSS.1
D1
VSS.2
E6
CS1
B5
WE
G5
OE
A2
UB
B2
LB
A1
A12
G3 A13
G4 A14
F3 A15
F4 A16
E4 A17
D3 A18
H1 A19
G2
VCC.2 E1
VCC.1 D6
NC.1 E3
CS2
A6
A20
H6
SAMSUNG K9K1208/Q/D/U/0C
U6
NC.1
B1
NC.2
B4
NC.3
B5
NC.4
B6
NC.5
C1
NC.6
C2
R/B
A6
RE
B2
CE
A4
NC.7
C3
NC.8
C4
VCC.1 F6
VSS.1 A3
NC.20
E4
NC.21
E5
CLE
B3
ALE
A2
WE
A5
WP
A1
NC.19
E3 NC.18
E2 NC.17
E1 NC.16
D6 NC.15
D5
VSS.2 H1
I/O00 F2
NC.9
C5
I/O01 G2
NC.10
C6
I/O02 H2
NC.11
D1
I/O03 H3
NC.12
D2
NC.14
D4
NC.22
F1
NC.13
D3
VCC.2 G4
LOCKPRE
E6
NC.23
F3
I/O04 H4
NC.25
F5
I/O05 G5
NC.24
F4
I/O06 H5
I/O07 G6
VSS.3 H6
NC.26
G1
NC.27
G3
C92
.1uF
R139
NO-POP
R138
10K
R136
0
R113
NO-POP
R134
0
C91
0.1uF
C93
.1uF
R140
10K
Spectrum Digital, Inc
A-14 DM644x EVM Technical Reference
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
EM_D3
EM_D8
EM_D6
EM_D5
EM_D7
EM_D0
EM_D1
EM_D2
EM_D4
EM_D9
EM_D10
EM_D11
EM_D13
EM_D12
EM_D14
EM_D15
ATA1_EM_BA1
ATA2_EM_A0
ALE_EM_A1
CLE_EM_A2
B.EM_A21
B.EM_A18
EM_A8
EM_A9
EM_A7
B.EM_A19
EM_A6
EM_A4
B.EM_A15
B.EM_A12
B.EM_A11
B.EM_A17
EM_A3
B.EM_A13
B.EM_A10
B.EM_A16
B.EM_A14
EM_A5
B.EM_A20
VCC_1.8V
VCC_1.8V
VCC_3.3V
VCC_1.8V
VCC_1.8V
VCC_1.8V
EM_D[0:15] 3,12,14,29
FLASH_CEz10
ATA1_EM_BA13,12,15,29
EM_A[3:21]3,12,14,29
ATA2_EM_A03,12,15,29 ALE_EM_A1
3,12,15,29 CLE_EM_A23,12,15,29
WRITE_WE3,12,15,29 READ_OE3,12,15,29
1.8V.SYS_RESETz8,15,26,29,30,31,34
B.EM_A[10:21]12,14,29
Size:
Date:
DWG NO Revision:
Sheet o f
Title:
Page Contents:
A
SPECTRUM DIGITAL INCORPORATED
508162-0001
Wednesday, November 16, 2005 13 35
B
DAVINCI EVALUATION MODULE
NOR FLASH
16 MBytes
U13 AM29LV256M
A0
31
A1
26
A2
25
A3
24
A4
23
A5
22
A6
21
A7
20
A8
10
A9
9
A10
8
A11
7
A12
6
A13
5
A14
4
A15
3
A16
54
BYTE
53
CE
32
OE
34
RESET
14
WE
13
VCC 43
VSS1 33
VSS2 52
RY/BY 17
DQ15/A-1 51
DQ0 35
DQ1 37
DQ2 39
DQ3 41
DQ4 44
DQ5 46
DQ6 48
DQ7 50
DQ8 36
DQ9 38
DQ10 40
DQ11 42
DQ12 45
DQ13 47
DQ14 49
A17
19
A18
18
A19
11
A20
12
A21
15
A22
2
A23
1
NC1 27
NC2 28
NC3 30
NC4 55
NC5 56
WP/ACC
16
VIO 29
C120
.1uF
R114
10K
R142
10K
R116
NO-POP
R115
10K
R143
10K
C94
.1uF
HHHHHHH
Spectrum Digital, Inc
A-15
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VLYNQ_RXD3
VLYNQ_RXD2
EM_A12
EM_A10
EM_A11
B.EM_A16
B.EM_A20
B.EM_A15
B.EM_A17
B.EM_A18
B.EM_A19
B.EM_A21
B.EM_A14
EM_A18
EM_A21
EM_A17
EM_A19
EM_A15
EM_A16
EM_A14
EM_A20
B.VLNQ_TXD0
B.VLNQ_TXD1
B.VLNQ_TXD2
B.VLNQ_TXD3
VLYNQ_TXD1
VLYNQ_TXD2
VLYNQ_TXD0
VLYNQ_TXD3
EM_A13
B.EM_A10
B.EM_A13
B.EM_A11
B.EM_A12
VLYNQ_RXD0
VLYNQ_RXD1
3V3.EM_D15
3V3.EM_D14
3V3.EM_D13
3V3.EM_D12
3V3.EM_D11
3V3.EM_D10
3V3.EM_D9
3V3.EM_D8
3V3.EM_D7
3V3.EM_D6
3V3.EM_D5
3V3.EM_D4
3V3.EM_D3
3V3.EM_D2
3V3.EM_D1
3V3.EM_D0
EM_D15
EM_D14
EM_D13
EM_D12
EM_D11
EM_D10
EM_D9
EM_D8
EM_D7
EM_D6
EM_D5
EM_D4
EM_D3
EM_D2
EM_D1
EM_D0
VCC_3.3V
VCC_3.3V
VCC_3.3V
VCC_1.8V
VLYNQ_ONz28 EM_A[3:21]3,12,13,29
VLYNQ_RXD032 VLYNQ_RXD132 VLYNQ_RXD232 VLYNQ_RXD332
SLP_CLK_EN 32
ELP_REQ/WAKEUP 32
PM_EN 32
WLAN_INTR 32
B.EM_A[10:21] 12,13,29
VLYNQ_TXD3 32
VLYNQ_TXD1 32
VLYNQ_TXD2 32
VLYNQ_TXD0 32
3V3.EM_D[0:15] 17,18,19
EM_D[0:15]3,12,13,29
1V8.EM_DATA_BUF_EN15 1V8.EM_DATA_BUF_DIR15
Size:
Date:
DWG NO Revision:
Sheet o f
Title:
Page Contents:
D
SPECTRUM DIGITAL INCORPORATED
508162-0001
Monday, March 06, 2006 14 35
B
DAVINCI EVALUATION MODULE
EMIF LEVEL SHIFTER
U11 is a switch used to enable Vlynq functions.
Signal levels are at 1.8 Volt logic levels on both
sides of switch
L A TO B1
DIR BUS
L B->A
H B<-A
R413 22
R419 22
C105
0.1uF
C116
5.6pF
U11
SN74CBTLV16292DGGR
NC.14
56
GND.2
19
1A
2
11A
25
1B1 54
1B2 53
GND.1
8VCC.1 17
GND.3
38
GND.4
49
NC.13
55
2A
4
3A
6
4A
9
5A
11
6A
13
7A
15
8A
18
9A
21
10A
23
12A
27
NC.1
3
NC.2
5
NC.3
7
NC.4
10
NC.5
12
NC.6
14
NC.7
16
NC.8
20
S
1
2B1 52
3B1 50
9B1 36
4B1 47
5B1 45
6B1 43
7B1 41
8B1 39
10B1 34
2B2 51
3B2 48
4B2 46
5B2 44
6B2 42
7B2 40
8B2 37
11B2 31
12B2 29
NC.9
22
NC.10
24
NC.11
26
NC.12
28
11B1 32
12B1 30
9B2 35
10B2 33
C119
NO-POP
R414 22
C121
0.1uF
C117
5.6pF
R144 10K
R415 22
C118
NO-POP
R416 22
C373
560pF
C106
0.1uF
R417 22
R392
NO-POP
C89
0.1uF
R412 22
U8
SN74AVCB164245VR
1B1
2
1B2
3
1B3
5
1B4
6
1B5
8
1B6
9
1B7
11
1B8
12
2B1
13
2B2
14
2B3
16
2B4
17
2B5
19
2B6
20
2B7
22
2B8
23
1A1 47
1A2 46
1A3 44
1A4 43
1A5 41
1A6 40
1A7 38
1A8 37
2A1 36
2A2 35
2A3 33
2A4 32
2A5 30
2A6 29
2A7 27
2A8 26
1DIR
1
1OEn
48
2DIR
24
2OEn
25
VCCB
7
VCCB
18 VCCA 42
VCCA 31
GND 28
GND 34
GND 39
GND 45
GND 4
GND 10
GND 15
GND 21
R393
NO-POP
R418 22
C88
0.1uF
,::r 33 w H
Spectrum Digital, Inc
A-16 DM644x EVM Technical Reference
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ISR_TCK
ISR_TMS
ISR_TDO
ISR_TCK
ISR_TDO
ISR_TMS
ISR_TDI
ISR_TCK
ISR_TDO
ISR_TDI
DLOOP1
DLOOP2
DLOOP3
DLOOP4
DLOOP5
ISR_TMS
VCC_3.3VVCC_1.8V
VCC_3.3V VCC_3.3V
VCC_3.3V
VCC_1.8V
VCC_1.8V
VCC_1.8V
VCC_3.3V
VCC_3.3V
3V3.SM_CEz28 CFn_SEL28
3V3.CF_PWR_ON19,28
ATA_SEL28
1.8V.SYS_RESETz8,13,26,29,30,31,34
1V8.MSP430_INT6INTRQ_EM_RNW3,29
WAIT/BUSY3,29
ATA1_EM_BA13,12,13,29
ALE_EM_A13,12,13,29ATA2_EM_A03,12,13,29
CLE_EM_A23,12,13,29
WRITE_WE3,12,13,29 READ_OE3,12,13,29
1V8.EM_DATA_BUF_DIR14 1V8.EM_DATA_BUF_EN14
3V3.ATA_BUFF_ENz 18
3V3.ATA_BUFF_DIR 18
ATA_DIR6
EM_CS23,10 ATA_CS13,29 ATA_CS03,29
UART_RXD1/DMARQ3UART_TXD1/DMACK3
ATA0_EM_BA03,29
3V3.ATA_RESETn 18
3V3.ATA.WAIT/BUSY 18
3V3.ATA.DMARQ 18
3V3.ATA.INTRQ_EM_RNW 18
3V3.ATA.DIOW 18
3V3.ATA.CS0 18
3V3.ATA.DIOR 18
3V3.ATA.DA0 18
3V3.ATA.DA1 18
3V3.ATA.DMACK 18
3V3.ATA.CS1 18
3V3.ATA.DA2 18
MSP430_INT 28
3V3.SYS_RESETz 22,24,28,31
3V3.SM.WAIT/BUSY 17
3V3.SM.SM_CEz 17
3V3.SM.WRITE_WE 17
3V3.SM.READ_OE 17
3V3.SM.ALE_EM_A1 17
3V3.SM.CLE_EM_A2 17
3V3.CF.ATA0_EM_BA0 19
3V3.CF.ATA1_EM_BA1 19
3V3.CF.ATA2_EM_A0 19
3V3.CF.READ_OE 19
3V3.CF.ATA_CS0 19
3V3.CF.ATA_CS1 19
3V3.CF.WRITE_WE 19
3V3.CF.WAIT/BUSY 19
3V3.CF.INTRQ_EM_RNW 19
3V3.UART_RXD1 28,31
3V3.UART_TXD1 28,31
SPAREIO3 28
SPAREIO2 28
SPAREIO1 28
NAND_BUSY12
TIMER_IN8
TIMER_IN_DC331
CPLD_TIMER_IN 5
Size:
Date:
DWG NO Revision:
Sheet o f
Title:
Page Contents:
C
SPECTRUM DIGITAL INCORPORATED
508162-0001
Wednesday, November 16, 2005 15 35
B
DAVINCI EVALUATION MODULE
EMIF DATA BUS LEVEL SHIFTER
CPLD REVISION 508163-0001B
C104
0.1uF
RN24
RPACK4-10K
1
2
3
4 5
6
7
8
C129
0.1uF C131
0.1uF
L62
NO-POP
U14
EPM240GTC100
B1.PIN2
2
B1.PIN3
3
TDI.B1
23
B1.PIN4
4
B1.PIN6
6
B1.PIN7
7
B1.PIN8
8
B1.VCCIO1A 9
GNDIO1
10
GNDINTA
11
B1.GCLK0
12
VCCINT1 13
B1.GCLK1
14
TMS.B1
22
B1.PIN16
16
B1.PIN17
17
B1.PIN18
18
B1.PIN19
19
B1.PIN20
20
B1.PIN21
21
B1.PIN27
27 B1.PIN26
26
B1.PIN28
28
B1.PIN29
29
B1.PIN30
30
B1.VCCIO1B 31
B1.PIN33
33
B1.PIN34
34
B1.PIN35
35
B1.PIN36
36
B1.PIN37
37
B1.PIN38
38
B1.PIN39
39
B1.PIN40
40
B1.PIN41
41
B1.PIN42
42
B1.DEV_OE
43
B1.DEV_CLRn
44
B1.VCCIO1C 45
GNDIO3
46
B1.PIN47
47
B1.PIN48
48
B1.PIN49
49
B1.PIN50
50
B1.PIN51
51
B2.PIN52 52
GNDIO2
32
B2.PIN54 54
B2.PIN55 55
B2.PIN57 57
B2.PIN58 58
B2.VCCIO1A 59
GNDIO4
60
B2.PIN61 61
TCK.B1
24
VCCINT2 63
B2.PIN66 66
GNDINTB
65
B2.PIN67 67
B2.PIN68 68
B2.PIN69 69
B2.PIN70 70
B2.PIN71 71
B2.PIN72 72
TDO.B1
25
B2.PIN73 73
B2.PIN76 76
B2.PIN77 77
GNDIO5
79
B2.VCCIO1B 80
B2.PIN81 81
B2.PIN83 83
B2.PIN84 84
B2.PIN85 85
B2.GCLK3 64
B2.GCLK2 62
B2.PIN86 86
GNDIO6
93
B2.VCCIO1C 94
B2.PIN96 96
B2.PIN97 97
B2.PIN98 98
B2.PIN99 99
B2.PIN100 100
B1.PIN5
5
B1.PIN15
15
B2.PIN53 53
B2.PIN56 56
B2.PIN74 74
B2.PIN75 75
B2.PIN78 78
B2.PIN82 82
B2.PIN87 87
B2.PIN88 88
B2.PIN89 89
B2.PIN90 90
B2.PIN91 91
B2.PIN92 92
B2.PIN95 95
B2.PIN1 1
R406
10K
R368 NO-POP
J17
SMT FEMALE HEADER 5X2
1 2
3 4
5 6
7 8
910
C108
0.1uF
R43
10K
L63
BLM41P750SPT
C109
0.1uF
R3
10K
R165 0
C128
0.1uF C107
0.1uF
R192 0
R36933
R191
10K
C126
0.1uF
Spectrum Digital, Inc
A-17
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MS.CLK
MS.DATA3
MS.DATA0
SD_DATA0
SD_CMD
SD_DATA1 MS.CMD.BS
MS.DATA1
MS.DATA1
MS.DATA0
MS.DATA2
MS.DATA2
SD_DATA2
MS.DATA3
MS.CLK
SD_CLK
SD_DATA3
VCC_3.3V
VCC_3.3V
VCC_3.3V
VCC_3.3V
VCC_3.3V
VCC_3.3V
VCC_3.3V
SD_DATA17,31,32
SD_DATA37,31,32 SD_DATA27,31,32
SD_CLK7,31,32
SD_CMD7,31,32
SD_DATA07,31,32
SD/MMC.INS 28
MS.INS 28
SD/MMC.WP 28
Size:
Date:
DWG NO Revision:
Sheet o f
Title:
Page Contents:
A
SPECTRUM DIGITAL INCORPORATED
508162-0001
Wednesday, November 16, 2005 16 35
B
DAVINCI EVALUATION MODULE
SD/MMC/MS CONNECTOR
SELECTS TERMINATION FOR SD/MMC/MS
WHEN USING DAT3 CARD DETECTION
PULL DOWN IS POPULATED WITH 470K OHM
RESISTOR AND PULL UP IN NOT POPULATED
J5 TERMINATION
MEMORY STICK
MEMORY STICK PRO
MMC CARD
SD CARD
1-2
1-2
1-2
2-3
R123
51K
J5
HEADER 3
1
2
3
R121
100K
+C10
10uF
R119
NO-POP
R127 0
J3
SCDB2A101
SD.DAT3
1
SD.CMD
2
SD.VSS1
3
SD.VDD
4
SD.CLK
5
SD.VSS2
6
SD.DAT0
7
SD.DAT1
8
SD.DAT2
9
WP
20
COM
22
INS
21
GND.1 23
MS.VSS1 10
MS.BS 11
MS.DATA1 12
MS.SDIO/DATA0 13
MS.DATA2 14
MS.XINS 15
MS.DATA3 16
MS.SCLK 17
MS.VCC 18
MS.VSS2 19
R108
51K
R124
51K
C78
.1uF
R122
51K
R99
0
R118
NO-POP
R126
51K
C95
0.1uF
R120
51K R117
51K
R73
51K
U5
SN74LVC1G125
3
4
5
2
1
R125
NO-POP
Spectrum Digital, Inc
A-18 DM644x EVM Technical Reference
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
3V3.WRITE_WE
3V3.ALE_EM_A1
3V3.SM_CEz
3V3.CLE_EM_A2
3V3.READ_OE
3V3.WAIT/BUSY
3V3.EM_D0
3V3.EM_D1
3V3.EM_D2
3V3.EM_D3
3V3.EM_D4
3V3.EM_D5
3V3.EM_D6
3V3.EM_D7
SM.xD.WP
3V3.WRITE_WE
3V3.ALE_EM_A1
3V3.READ_OE
3V3.SM_CEz
3V3.WAIT/BUSY
3V3.CLE_EM_A2
SM.xD.WP
3V3.EM_D7
3V3.EM_D6
3V3.EM_D5
3V3.EM_D4
3V3.EM_D3
3V3.EM_D2
3V3.EM_D1
3V3.EM_D0
VCC_3.3V
VCC_3.3V
VCC_3.3V
VCC_3.3V
VCC_3.3V
3V3.SM.SM_CEz15
3V3.SM.READ_OE15
3V3.SM.WRITE_WE15 3V3.SM.ALE_EM_A115 3V3.SM.CLE_EM_A215
3V3.EM_D[0:15]14,18,19
3V3.SM.WAIT/BUSY15
SM.CD 28
xD.CD 28
SM.xD.WP 28
Size:
Date:
DWG NO Revision:
Sheet o f
Title:
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B
SPECTRUM DIGITAL INCORPORATED
508162-0001
Wednesday, November 16, 2005 17 35
B
DAVINCI EVALUATION MODULE
SM/xD CONNECTOR
Chant Sincere SM/xD Connector
ADD INLINE RESISTORS HERE
J15
SM/xD_CONNECTOR
SM.I/O1
SMC6
SM.I/O2
SMC7
SM.I/O3
SMC8
SM.I/O4
SMC9
SM.I/O5
SMC13
SM.I/O6
SMC14
SM.I/O7
SMC15
SM.I/O8
SMC16
SM.CLE
SMC2
SM.ALE
SMC3
SM.WE
SMC4
SM.WP
SMC5
SM.OPTION
SMC18
SM.R/B
SMC19
SM.RE
SMC20
SM.CE
SMC21
xD.VCC2 XD20
SM.VSS1 SMC1
SM.VSS2 SMC10
SM.LVD SMC17
SM.VCC2 SMC22
SM.CD
SMC11
SM.SENS.1
SMCSW1
SM.25
SMCWP1 SM.26
SMCWP2
SM.SENS.2
SMCSW2
xD.CD XD1
xD.CLE XD5
xD.ALE XD6
xD.WE XD7
xD.WP XD8
xD.R/B XD2
xD.RE XD3
xD.CE XD4
xD.VSS1 XD9
xD.I/O0 XD10
xD.I/O1 XD11
xD.I/O2 XD12
xD.I/O3 XD13
xD.I/O4 XD14
xD.I/O5 XD15
xD.I/O6 XD16
xD.I/O7 XD17
SM.VCC1 SMC12
xD.VCC1 XD18
xD.VSS2 XD19
R106
10K
R77
NO-POP
R107
10K
RN23
100K
1
2
3
4
6
7
8
5
R78
10K
R76
10K
RN22
100K
1
2
3
4
6
7
8
5
+C9
10uF
Spectrum Digital, Inc
A-19
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ATA_DASPn
ATA_CSEL
ATA.DD0
ATA.DD1
ATA.DD2
ATA.DD3
ATA.DD4
ATA.DD5
ATA.DD6
ATA.DD7
ATA.DD8
ATA.DD9
ATA.DD10
ATA.DD11
ATA.DD12
ATA.DD13
ATA.DD14
ATA.DD15
3V3.EM_D4
3V3.EM_D6
3V3.EM_D5
3V3.EM_D2
3V3.EM_D1
3V3.EM_D0
3V3.EM_D3
3V3.EM_D7
3V3.EM_D15
3V3.EM_D9
3V3.EM_D10
3V3.EM_D11
3V3.EM_D12
3V3.EM_D8
3V3.EM_D13
3V3.EM_D14
ATA.DD0
ATA.DD1
ATA.DD2
ATA.DD3
ATA.DD4
ATA.DD5
ATA.DD6
ATA.DD7 ATA.DD8
ATA.DD9
ATA.DD10
ATA.DD11
ATA.DD12
ATA.DD13
ATA.DD14
ATA.DD15
ATA.DD[0:15]
ATA.DA0
ATA.DA1 ATA.DA2
ATA.DMACK
ATA.CS0 ATA.CS1
ATA.DIOR
ATA.DIOW
ATA.DMARQ
ATA.INTRQ
ATA.DMARQ
ATA.IORDY
ATA.INTRQ
ATA_RESETn
ATA_RESETn
ATA.IORDY
ATA.CS1
ATA.CS0
ATA.DIOR
ATA.DIOW
ATA.DMACK
ATA.DA0
ATA.DA2
ATA.DA1
VCC_5V
VCC_5V
VCC_5V
VCC_3.3V
VCC_3.3V
VCC_3.3VVCC_3.3V
VCC_3.3V
3V3.ATA.DA215
3V3.ATA.CS115
3V3.EM_D[0:15]14,17,19
3V3.ATA.DA0
153V3.ATA.DA115
3V3.ATA.CS015
3V3.ATA.DIOR153V3.ATA.DIOW15
3V3.ATA.DMARQ 15
3V3.ATA.INTRQ_EM_RNW 15
3V3.ATA.WAIT/BUSY 15
3V3.ATA_RESETn15
3V3.ATA_BUFF_DIR15
3V3.ATA_BUFF_ENz15
3V3.ATA.DMACK15
Size:
Date:
DWG NO Revision:
Sheet o f
Title:
Page Contents:
A
SPECTRUM DIGITAL INCORPORATED
508162-0001
Wednesday, November 16, 2005 18 35
B
DAVINCI EVALUATION MODULE
ATA INTERFACE
KEY
NC
IOCS16
DIR BUS
L B->A
H B<-A
MOUNTING HOLES
TP34
TEST POINT
1
R154
10K
R401
NO-POP
R57 33
Z7
1
C86
.1uF
R55 33
R153 82
R112
10K
R45 22
R155
1K
R156 33
C101
.1uF
RN4 RPACK8-33
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
R150 82
C87
.1uF
R158
20K
DS10
LED,GRN
R157 82
R58 33
RN1 RPACK8-33
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
R223
2K
R148
5.6K
U9
SN74LVT16245B/SN74CB3Q16245
Vcc
7
Vcc
18 Vcc 31
Vcc 42
1A1 47
1A2 46
1A3 44
1A4 43
1A5 41
1A6 40
1A7 38
1A8 37
1B1
2
1B2
3
1B3
5
1B4
6
1B5
8
1B6
9
1B7
11
1B8
12
2A1 36
2A2 35
2A3 33
2A4 32
2A5 30
2A6 29
2A7 27
2A8 26
2B1
13
2B2
14
2B3
16
2B4
17
2B5
19
2B6
20
2B7
22
2B8
23
1OE 48
1DIR 1
2OE 25
2DIR 24
GND 4
GND 10
GND 15
GND 21
GND
28
GND
34
GND
39
GND
45
R44
0
JP1
HEADER 22X2
1 2
3 4
5 6
7 8
910
11 12
13 14
15 16
17 18
19 20
21 22
2324
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
R48 33
Z8
1
C103
.1uF
Z9
1
R56 33
R47 22
TP33
TEST POINT
1
R46 22
Z6
1
Spectrum Digital, Inc
A-20 DM644x EVM Technical Reference
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CF_A2
CF_A1
CF_A0
3V3.EM_D15
3V3.EM_D14
3V3.EM_D13
3V3.EM_D12
3V3.EM_D11
3V3.EM_D10
3V3.EM_D9
3V3.EM_D8
3V3.EM_D7
3V3.EM_D6
3V3.EM_D5
3V3.EM_D4
3V3.EM_D3
3V3.EM_D2
3V3.EM_D1
3V3.EM_D0
VCC_3.3V
VCC_3.3V
VCC_3.3V
VCC_3.3V
3V3.CF_CD1 28
3V3.CF_CD2 28
3V3.EM_D[0:15] 14,17,18
3V3.CF_RESETz28
3V3.CF.WAIT/BUSY15
3V3.CF.ATA0_EM_BA015 3V3.CF.ATA1_EM_BA115 3V3.CF.ATA2_EM_A0153V3.CF_PWR_ON15,28
3V3.CF.WRITE_WE15
3V3.CF.READ_OE15
3V3.CF.ATA_CS015
3V3.CF.ATA_CS115
3V3.CF.INTRQ_EM_RNW15
Size:
Date:
DWG NO Revision:
Sheet o f
Title:
Page Contents:
B
SPECTRUM DIGITAL INCORPORATED
508162-0001
Wednesday, November 16, 2005 19 35
B
DAVINCI EVALUATION MODULE
COMPACT FLASH CONNECTOR
+
C16
10uF C15
.1uF
R28
100K
U10
FDC6331L
VIN
4VOUT 3
VOUT 2
R1/C1
6
ON/OFF
5
R2 1
R21
20K
C17
.1uF
R22
1K
R25
10K
R26
20K
R110
2K
R20
100K
R24
0
R23
10K
R27
0
R400
NO-POP
R109
100K
P1
Compact Flash Connector
GND
1
D03 2
D04 3
D05 4
D06 5
D07 6
CE1
7
A10
8
OE
9
A09
10 A08
11 A07
12
VCC
13
A06
14 A05
15 A04
16 A03
17 A02
18 A01
19 A00
20 D00 21
D01 22
D02 23
WP
24 CD2 25
CD1 26
D11 27
D12 28
D13 29
D14 30
D15 31
CE2
32
VS1 33
IORD
34
IOWR
35
WE
36
RDY/BSY
37
VCC
38
CSEL
39
VS2 40
RESET
41
WAIT
42
INPACK#
43
REG
44
BVD2 45
BVD1 46
D08 47
D09 48
D10 49
GND
50
R111 NO-POP
4‘ L“ .LJ u
Spectrum Digital, Inc
A-21
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
S_A_TXD
S_A_RXDS_A_RXD
3V3.UART_RXD0
UART_TXD0 3V3.UART_TXD0
UART_RXD0
VCC_3.3V VCC_3.3V
VCC_3.3V
VCC_3.3VVCC_1.8V
VCC_3.3VVCC_1.8V
UART_TXD06
UART_RXD06
Size:
Date:
DWG NO Revision:
Sheet o f
Title:
Page Contents:
A
SPECTRUM DIGITAL INCORPORATED
508162-0001
Wednesday, November 16, 2005 20 35
B
DAVINCI EVALUATION MODULE
RS232 INTERFACE
L B-->A
H A-->B
DIR FUNCTION
R356 0
L46 1uH
+C299
1uF
C294
10pF
+C298
1uF
U64 MAX3221
DIN
11
INVALID
10
ROUT
9
C1+
2
C1-
4
V+
3
VCC
15
GND
14
V- 7
C2- 6
C2+ 5
RIN 8
ENABLE
1
FORCEOFF 16
DOUT 13
FORCEON 12
C243
.1uF
R357
10
U43
SN74AVC1T45
A1 3
VCCB
6VCCA 1
GND1
2
B1
4
DIR 5
R354
10K
L54
BLM21PG221SN1D
1 2
C297
10pF
+
C296
1uF
C245
.1uF
L47 1uH
L55
BLM21PG221SN1D
1 2
C301
.1uF
R355
10K
+C302
1uF
C300
10pF
C295
10pF
+C77
47uF
C246
.1uF
U42
SN74AVC1T45
A1 3
VCCB
6VCCA 1
GND1
2
B1
4
DIR 5
C244
.1uF
P6
DSUB9-Male
5
9
4
8
3
7
2
6
1
10 11
% WW LJ
Spectrum Digital, Inc
A-22 DM644x EVM Technical Reference
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
USB_DP
USB_SHIELD
USB_DM
USB_SHIELD
USB_SHIELD
USB_SHIELD
USB_SHIELD
VCC_5V
VCC_5V
VCC_3.3V
VCC_3.3V
USB_DM7USB_DP7
USB_VBUS7
USB_ID7
USB.DRVVBUSz28
Size:
Date:
DWG NO Revision:
Sheet o f
Title:
Page Contents:
C
SPECTRUM DIGITAL INCORPORATED
508162-0001
Wednesday, November 16, 2005 21 35
B
DAVINCI EVALUATION MODULE
USB 2.0 INTERFACE
THESE FOOTPRINTS ARE OVERLAYED
ONLY 1 OF 3 IS POPULATED AT 1 TIME
Selects Termination
for Host/Client
configurations
STUB TO R337 AND JUMPER NEED TO BE MINIMUM
0.1 TO 0.2 INCHES MAX
MINI A-B CONNECTOR
FULL SIZE B CONNECTOR
FULL SIZE A CONNECTOR
For host mode Capacitor Minimum Capacitance
is 100uF, this design uses 104.7uF
both C133 and C69 installed.
For Peripheral or OTG the
Capacitancer should be 4.7 uF
so remove R132 thus C69 provides capacitance
R377
100K
+
C133
100uF
+
C69
4.7uF
C350
.1uF
J7
HEADER 3
1
2
3
C293
100nF
TP59
1
L53
BLM21PG221SN1D
1 2
TP60
1
J10B
USB-miniAB/A/B connector
ATTACH
1B
D-
2B
D+
3B
GND
4B
SHIELD1 1
SHIELD2 2
D6 NO-POP
R379
NO-POP
S
D
G
Q2
IRLML6401
R378
10K
L52
BLM21PG221SN1D
1 2
J10C
USB-miniAB/A/B connector
VBUS-A
1A
D-
2A
D+
3A
GND
4A
SHIELD3 3
SHIELD4 4
R337
1.5K
U59
SN74AHC1G08
1
24
53
R133 0
C351
.1uF
R132 0
J10A
USB-miniAB/A/B connector
VBUS
1AB
D-
2AB
D+
3AB
GND
5AB
SHIELD5
5
ID
4AB
SHIELD6
6
SHIELD7
7
SHIELD8
8
Spectrum Digital, Inc
A-23
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LXT_RDM
LXT_TDCT
LXT_TDP
MII_RXDV
MII_CRS
XSPDO_MDIO
MII_RXD3
MII_RCLK
MII_TXCLK
RBIAS
MII_RDX2
MTXD3 LXT_RDP_c
MII_RXD1
MTXEN
MTXD2
MTXD1
LXT_RDM_c
MII_RXD0
MDINT_TP
MTXD0
PWRDWN
SLEEP
MII_COL
SYS_RSTz
MII_RXER
XSPCLK_MDCLK
PAUSE
TXSLEW1
TXSLEW0
LXT_RDP
MTXD3
MTXEN
MTXD0
ENET_ENABLEz
ENET_ENABLEz
LINKLED-
LED1-
MTXD1
MTXD2
LXT_TDM
PWRDWN
TXSLEW0
SLEEP
PAUSE
TXSLEW1
LED1-
LINKLED-
AVCC3.3
AVCC3.3
AVCC3.3
VCC_3.3V
VCC_3.3V
VCC_3.3V
VCC_3.3V
VCC_3.3V
VCC_3.3V
VCC_3.3V
ENET_ENABLEz 31
GIOV33_0 6,31
GIOV33_2 6,31
GIOV33_4 6,31
GIOV33_6 6,31
GIOV33_8 6,31
GIOV33_10 6,31
GIOV33_12 6,31
GIOV33_14 6,31
GIOV33_16 6,31
GIOV33_1 6,31
GIOV33_3 6,31
GIOV33_5 6,31
GIOV33_7 6,31
GIOV33_9 6,31
GIOV33_11 6,31
GIOV33_13 6,31
GIOV33_15 6,31
3V3.SYS_RESETz 15,24,28,31
Size:
Date:
DWG NO Revision:
Sheet o f
Title:
Page Contents:
B
SPECTRUM DIGITAL INCORPORATED
508162-0001
Wednesday, November 16, 2005 22 35
B
DAVINCI EVALUATION MODULE
ETHERNET INTERFACE
DUPLEX
STATUS
Place terminations
close to PHY source
pins.
COLLISION/
LINK/ SPEED
ACTIVITY
Route pairs together,
pairs are (3 and 6) and
(1 and 2).
R275
100
R358
49.9
R288
49.9
R222 360
L32 BLM41P750SPT
R262 22
R285 10k
C258
.1uF
R274 0 EIA0402
C257
0.01uF
C248
10pF
C226
.1uF
R287 10k
C262
.1uF R276
100
R282 10k
R289 0
L56
BLM21PG221SN1D
1 2
R277
100
L31
EXC-3BB102H
12
C303
.1uF R279 10k
R278 10k
C304
270pF
R283 10k
R257 0 EIA0402
R260 NO POP
L57
BLM21PG221SN1D
1 2
Y6
25MHz
C259
.1uF
R407
10K
C260
270pF
TP58
MDINT
RN34 RPACK8-33
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
C264
10pF
R280 1.5k
R286 NO POP
C263
0.01uF
R261 22
R281 NO POP
R258
NO-POP
U58
LXT971ALE
TX_CLK
55
TXD0
57
TXD1
58
TXD2
59
TXD3
60
TX_EN
56
TX_ER
54
COL
62
CRS
63
RX_CLK
52
RXD0
48
RXD1
47
RXD2
46
RXD3
45
RX_DV
49
RX_ER
53
MDDIS
3
MDC
43
MDIO
42
MDINT#
64
TDI
27
TDO
28
TPFOP 19
TPFON 20
TPFIP 23
TPFIN 24
LED/CFG1 38
LED/CFG2 37
LED/CFG3 36
ADDR0 12
ADDR1 13
ADDR2 14
ADDR3 15
ADDR4 16
XO 2
REFCLK/XI 1
PWRDWN 39
RBIAS 17
TEST1 35
RESET#
4
TEST0 34
VCCA 22
GND 25
SD/TP# 26
GND1
7
GND2
11
GND3
18
GND4
41
GND5
50
GND6
61
VCCD 51
VCCIO1 8
VCCIO2 40
VCCA 21
TMS
29
TCK
30
TRST#
31
TxSLEW0
5
TxSLEW1
6
PAUSE
33
SLEEP
32
N/C1 9
N/C2 10
N/C3 44
P2
RJ45 HALO HFJ11-2450E-L21
TXD-CT
4
NC1
7
GND
8
TXD+
1
TXD-
2
RXD+
3
RXD-
6RXD-CT
5
S0
14 S1
13
LED1+
9LED1-
10
LED2-
12
LED2+
11
C247
.1uF
U41
CBTLV16210DGGR
2OE 47
1OE 48
1A1 2
2A1 13
1B1
46
2B1
35
GND
8GND
17 GND
32 GND
41
VCC 15
1A2 3
1A3 4
1A4 5
1A5 6
1A6 7
1A7 9
1A8 10
1A9 11
1A10 12
2A2 14
2A3 16
2A4 18
2A5 19
2A6 20
2A7 21
2A8 22
2A9 23
2A10 24
NC
1
1B2
45
1B3
44
1B4
43
1B5
42
1B6
40
1B7
39
1B8
38
1B9
37
1B10
36
2B2
34
2B3
33
2B4
31
2B5
30
2B6
29
2B7
28
2B8
27
2B9
26
2B10
25
R259 360
R284 22.1k
C261
.1uF
Spectrum Digital, Inc
A-24 DM644x EVM Technical Reference
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
TVP5146VIDEO4
TVP5146VIDEO3
TVP5146VIDEO2
TVP5146VIDEO1
TVP5146VIDEO0
TVP5146VIDEO6
TVP5146VIDEO7
TVP5146VIDEO5
YI0
YI1
YI2
YI3
YI4
YI5
YI6
YI7
B.YI0
B.YI1
B.YI2
B.YI3
B.YI4
B.YI5
B.YI6
B.YI7
VCC_3.3V VCC_1.8V
VCC_1.8V
TVP5146VIDEO[0:7]24
TVP5146HSYNC24 TVP5146VSYNC24 TVP5146PCLK24
YI3 5,30
YI4 5,30
YI5 5,30
YI7 5,30
YI0 5,30
YI1 5,30
HD 5,30
VD 5,30
CAPTURE_EN30
YI2 5,30
1.8V_DC3_PCLK 31
YI6 5,30
PCLK 5,30
Size:
Date:
DWG NO Revision:
Sheet o f
Title:
Page Contents:
A
SPECTRUM DIGITAL INCORPORATED
508162-0001
Wednesday, November 16, 2005 23 35
B
DAVINCI EVALUATION MODULE
TVP5146 LEVEL SHIFTER
DIR BUS
L B->A
H B<-A
U66 is a tri-stateable logic translator used for DC4
to allow the TVP5146 to be disconnected
from on-board circuitry.Signal levels are at 1.8V logic
levels on B side and 3.3V on A sides of translator.
RN32 RPACK4-33
1
2
3
4 5
6
7
8
RN33RPACK8-33
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16
R226 0
R231
0
C67
0.1uF
R264
10K
C62
0.1uF
R64
360
C68
0.1uF
U66
SN74AVCB164245VR
1B1 2
1B2 3
1B3 5
1B4 6
1B5 8
1B6 9
1B7 11
1B8 12
2B1 13
2B2 14
2B3 16
2B4 17
2B5 19
2B6 20
2B7 22
2B8 23
1A1
47
1A2
46
1A3
44
1A4
43
1A5
41
1A6
40
1A7
38
1A8
37
2A1
36
2A2
35
2A3
33
2A4
32
2A5
30
2A6
29
2A7
27
2A8
26
1DIR 1
1OEn 48
2DIR 24
2OEn 25
VCCB 7
VCCB 18
VCCA
42
VCCA
31
GND
28 GND
34 GND
39 GND
45
GND
4
GND
10
GND
15
GND
21
C61
0.1uF
Spectrum Digital, Inc
A-25
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LUMA
TVP5146VIDEO4
TVP5146VIDEO3
TVP5146VIDEO1
TVP5146VIDEO0
TVP5146VIDEO6
TVP5146VIDEO7
TVP5146VIDEO5
TVP5146VIDEO2
3.3VA_DDEC 3.3VD_DDEC1.8VD_DDEC
3.3VD_DDEC
3.3VA_DDEC
3.3VD_DDEC
1.8VA_DDEC
3.3VD_DDEC
3.3VD_DDEC
1.8VD_DDEC
1.8VA_DDEC
3.3VA_DDEC
3.3VD_DDEC1.8VD_DDEC
1.8VA_DDECVCC_1.8V VCC_3.3V
VCC_1.8V VCC_3.3V
3V3.SYS_RESETz15,22,28,31
TVP5146VIDEO[0:7] 23
TVP5146VSYNC 23
TVP5146PCLK 23
TVP5146HSYNC 23
3V3.I2C_CLK6,27,28
3V3.I2C_DATA6,27,28
Size:
Date:
DWG NO Revision:
Sheet o f
Title:
Page Contents:
A
SPECTRUM DIGITAL INCORPORATED
508162-0001
Wednesday, November 16, 2005 24 35
B
DAVINCI EVALUATION MODULE
TVP5146 VIDEO DECODER
DDEC_GND DDEC_GND DDEC_GND DDEC_GND
DDEC_GND
DDEC_GND DDEC_GND DDEC_GND
DDEC_GND
DDEC_GND
DDEC_GND
DDEC_GND
DDEC_GND
DDEC_GND
DDEC_GND
DDEC_GND
DDEC_GND
DDEC_GND
DDEC_GND
DDEC_GND
DDEC_GND
DDEC_GND
DDEC_GND
DDEC_GND
ISOLATE GROUNDS
AND CONNECT AT
SINGLE LOCATION
IN THE GROUND PLANE
DDEC_GND
C286
0.1uF
C337
0.1uF
C367
330pF
L39 2.7uH
Y4
14.31818mhz
C347
0.1uF
R328
NO POP
C344
680pF
C332
330pF
C325
680pF
L43 2.7uH
C342
330pF
R265
4.7K
C338
330pF
L41 2.7uH
C346
0.1uF
C292
33pF
R336 0
J12
RCA JACK
1
2
C368
330pF
R330
2K
L38 BLM41P750SPT
1 2
C343
.1uF
C329
0.1uF
C287
0.1uF
R376
75
R335 22
L44 2.7uH
R333
4.7K
C284
0.1uF
C335
0.1uF
J11 749181-1
3 4
21
5 6
L40 2.7uH
TP62
1
C288
0.1uF
R327
NO POP
C339
.1uF
C333
.1uF
C250
0.1uF
L42 2.7uH
C331
0.1uF
R334
2.2K
C341
0.1uF R329
2K
R266 22
C290
0.1uF
TP56
1
U51
TVP5146
VI_3_B
17
VI_3_A
16
VI_2_B
8
VI_2_C
9
Y8 44
Y9 43
Y7 45
THERMAL
81
CH3_A18GND
15
CH4_A18GND
24
CH1_A18GND
79
DGND4
56
CH1_A33GND
3
CH3_A33GND
19 CH2_A33GND
6
VI_3_C
18
VI_4_A
23
Y2 52
Y3 51
Y6 46
CH4_A33GND
22
DGND2
32
DGND3
42
IOGND1
39
IOGND2
49
IOGND3
62
PLL_A18GND
77
DGND1
27
DGND5
68
A18GND_REF
13 AGND
26
CH2_A18VDD 11
CH3_A18VDD 14
CH4_A18VDD 25
CH1_A18VDD 78
CH1_A33VDD 4
CH2_A33VDD 5
CH3_A33VDD 20
CH4_A33VDD 21
A18VDD_REF 12
DVDD1 31
DVDD2 41
DVDD3 55
DVDD4 67
IOVDD1 38
IOVDD2 48
IOVDD3 61
PLL_A18VDD 76
VI_2_A
7
VI_1_C
2
VI_1_B
1
VI_1_A
80
SCL
28
SDA
29
Y5 47
Y4 50
Y1 53
Y0 54
C9 57
C858
C7 59
C6 60
C5 63
C4 64
C3 65
C2 66
C1 69
C0 70
XTAL1 74
XTAL2 75
DATACLK 40
RESETB
34
PWRDWN
33
INTREQ 30
FSS/GPIO
35
GLCO/12CA 37
HS/CS/GPIO 72
VS/VBLK/GPIO 73
FID/GPIO 71
AVID/GPIO 36
CH2_A18GND
10
C345
0.1uF
C285
0.1uF
C326
330pF
L28 BLM41P750SPT
1 2
C340
680pF
C328
.1uF
C334
0.1uF
RN35
RPACK8-33
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
C330
0.1uF
C327
0.1uF
L37 BLM41P750SPT
1 2
C348
0.1uF
R374
75
TP57
1
R332
100K
L23 BLM41P750SPT
1 2
C289
.1uF
C291
0.1uF
C283
0.1uF
C336
0.1uF
C349
33pF
R331 22
R375
75
WWJ WW \>>>W> WW JWHW WWJ 3 J : t3: w» w? HA 4JJ WM JJH HA WW ”JJ filfi
Spectrum Digital, Inc
A-26 DM644x EVM Technical Reference
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VOUT_ON
VOUT_ON
VOUT_ON
3V3A_VOUT
VOUT_ON
VCC_3.3V DAC_3V3
DAC_3V3
DAC_3V3
DAC_3V3
DAC_3V3
DAC_3V3
DAC_IOUTA5
DAC_IOUTB5
DAC_IOUTD5
DAC_IOUTC5
Size:
Date:
DWG NO Revision:
Sheet o f
Title:
Page Contents:
A
SPECTRUM DIGITAL INCORPORATED
508162-0001
Wednesday, November 16, 2005 25 35
B
DAVINCI EVALUATION MODULE
VIDEO OUTPUT
DENC_GND
DENC_GND
DENC_GND
DENC_GND
DENC_GND
DENC_GND
DENC_GND
DENC_GND
DENC_GND DENC_GND
DENC_GND
DENC_GND
DENC_GND
DENC_GND
DENC_GND
DENC_GND
DENC_GNDDENC_GND
DENC_GND DENC_GND
DENC_GND DENC_GND
ISOLATE GROUNDS
AND CONNECT AT
SINGLE LOCATION
IN THE GROUND PLANE
DENC_GND
DENC_GNDDENC_GND
DENC_GND
DENC_GND
DENC_GND
DENC_GNDDENC_GND
DENC_GND DENC_GND
DENC_GNDDENC_GND
DENC_GND DENC_GND
1812LS-273XJB 1812LS-273XJB
1812LS-273XJB1812LS-273XJB
1812LS-273XJB 1812LS-273XJB
1812LS-273XJB 1812LS-273XJB
L12 BLM41P750SPT
C355
0.1uF
R343 1130 1%
R348
1K
R350 75
L36 1uH
-
+
U48
OPA357AIDBV
3
4
5
2 6
1
C363
10pF
-
+
U50
OPA357AIDBV
3
4
5
2 6
1
R345
267 1%
R347 1130 1%
J9749181-1
3 4
21
5 6
C361
10pF
L27 12uH
L35 1uH
R352
1K
C252
27pF
-
+
U49
OPA357AIDBV
3
4
5
2 6
1
C359
0.1uF
C253
27pF
R338 75
L25 12uH
C362
10pF
R339 1130 1%
R346 75
R270
1K
L19 12uH
R351 1130 1%
L18 12uH
R342 75
C354
10pF
C352
0.1uF
C360
10pF
C358
0.1uF
R349
267 1%
R381 NO-POP
R272
1K
L26 12uH
C254
27pF
+C63
10uF
C357
10pF
C251
27pF
C256
0.1uF
R271
1K
R269
1K
C353
10pF
C356
10pF
L33 1uH
-
+
U47
OPA357AIDBV
3
4
5
2 6
1
+C64
220uF
L20 12uH
R340
1K
R380 10K
C255
0.01uF
R344
1K
R341
267 1%
L17 12uH L34 1uH
L16 BLM41P750SPT
R353
267 1%
L24 12uH
J8
DUAL RCA JACK
2
1
3
4
5
6
Spectrum Digital, Inc
A-27
VCC_1.8V
VCC_1.8V
VCC_3.3V
VCC_1.8V
B_CLKR7
B_FSR7
B_DR7
B_DX7
B_FSX7
B_CLKX7
1V8.I2C_DATA6,30,31
1V8.I2C_CLK6,30,31
AUDIO_CLK5,31
1.8V.SYS_RESETz8,13,15,29,30,31,34
Size:
Date:
DWG NO Revision:
Sheet of
Title:
Page Contents:
A
SPECTRUM DIGITAL INCORPORATED
508162-0001
Wednesday, November 16, 2005 26 35
B
DAVINCI EVALUATION MODULE
AIC33 AUDIO INTERFACE
MIC_IN
LINE_IN
ISOLATE GROUNDS
AND CONNECT AT
SINGLE LOCATION
IN THE GROUND PLANE
C279
.1uF
P4
Headphone Out
3
4
2
1
TP63 1
R371
330
P5
DUAL RCA JACK
2
1
3
U52
TVL320AIC33IZQE
HPLOUT D1
HPLCOM E1
LINE1R+
B7
LINE1R-
B6
LINE2L+
A4
LINE2L-
B5
MICBIAS
A2
WCLK
F9
DOUT
F8
MPF2
A8
MCLK
G8
SELECT
E8
SDA D8
RIGHT_LO+ J6
DRVSS.1 E2
DRVSS.2 F2
GPIO2 J8
LEFT_LO+ J4
LEFT_LO- J5
MONO_LO- J3
DIN
E9
MIC3R
A1
LINE2R+
B4
LINE2R-
A3
HPRCOM F1
HPROUT G1
MIC3L
B3
DRVDD.2 H1
AVDD_ADC B1
AVSS_ADC.1 C2
AVDD_DAC J1
AVSS_DAC.1 G2
RESET
H8
MFP0
B8
MFP1
B9
DVDD
H9
DVSS
D9 IOVDD
C9
MICDET
B2
RIGHT_LO- J7
SCL C8
MONO_LO+ J2
GPIO1 J9
LINE1L-
A5 LINE1L+
A6
BCLK
G9
MFP3
A9
AVSS_ADC.2 D2
AVSS_DAC.2 H2
DRVDD.1 C1
L48 BLM21PG221SN1D
C278
.1uF
C316
.1uF
C314
.1uF
R312 10
L29
BLM21PG221SN1D
R388 5.6K
R370
47K
P3
Dual-Stereo
1U 2
1L 5
4U3
5U 1
5L 4
4L 6
+
C73 33uF,6.3V
+
C72 33uF,6.3V
C319
.1uF
C366
220pF
+
C70
10uF
L50 BLM21PG221SN1D
C277
.1uF
C323 .1uF
R367
20K
R314 10
R324 10K
R316 10
C322 .1uF
C249
.1uF
R384
20K
C318
.1uF
R313
20K
R372
330
R383
20K
C276
1uF
TP64 1
R325 NO-POP
+
C76 10uF,6.3V
R382
20K
R317 10
L51 BLM21PG221SN1D
R326 NO-POP
TP65
1
+
C75 10uF,6.3V
C324 .1uF
C280
.1uF L30 BEAD M2301
R315 10
L45
BLM21PG221SN1D
R310
10
C317
220pF
R318
10K
R323 0
R320 10
TP69
1
L49 BLM21PG221SN1D
R319
20K
+
C74
10uF
R311
20K
C275
.1uF
R373
10K
C321
.1uF
C315
.1uF
C281
.1uF
R386
5.6K
R322 10K
C282
.1uF
C365
220pF
R321 0
R385 5.6K
R387
5.6K
C320 .1uF
Spectrum Digital, Inc
A-28 DM644x EVM Technical Reference
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VCC_3.3V
VCC_3.3V
VCC_3.3V
VCC_3.3V
VCC_3.3V
VCC_1.8V
VCC_3.3V
3V3.I2C_CLK6,24,28
3V3.I2C_DATA6,24,28
DX7,31
3V3.DC_PCLK 5
1V8.DC_PCLK30
Size:
Date:
DWG NO Revision:
Sheet o f
Title:
Page Contents:
A
SPECTRUM DIGITAL INCORPORATED
508162-0001
Wednesday, November 16, 2005 27 35
B
DAVINCI EVALUATION MODULE
SPDIF OUTPUTS & USER LEDS
L B-->A
H A-->B
DIR FUNCTION
USER CONTROLLED LEDS
SPDIF OUT
OPTICAL SPDIF OUT
C306
0.1uF
R71
330
R66
330
C309
0.1uF