PSoC 4200 Family Datasheet by Cypress Semiconductor Corp

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PSoC® 4: PSoC 4200
Family Datasheet
Programmable System-on-Chip (PSoC®)
Cypress Semiconductor Corporation 198 Champion Court San Jose,CA 95134-1709 408-943-2600
Document Number: 001-87197 Rev. *J Revised July 10, 2017
General Description
PSoC® 4 is a scalable and reconfigurable platform architecture for a family of mixed-signal programmable embedded system
controllers with an ARM® Cortex™-M0 CPU. It combines programmable and reconfigurable analog and digital blocks with flexible
automatic routing. The PSoC 4200 product family, based on this platform, is a combination of a microcontroller with digital program-
mable logic, high-performance analog-to-digital conversion, opamps with Comparator mode, and standard communication and timing
peripherals. The PSoC 4200 products will be fully upward compatible with members of the PSoC 4 platform for new applications and
design needs. The programmable analog and digital sub-systems allow flexibility and in-field tuning of the design.
Features
32-bit MCU Sub-system
48-MHz ARM Cortex-M0 CPU with single cycle multiply
Up to 32 kB of flash with Read Accelerator
Up to 4 kB of SRAM
Programmable Analog
Two opamps with reconfigurable high-drive external and
high-bandwidth internal drive, Comparator modes, and ADC
input buffering capability
12-bit, 1-Msps SAR ADC with differential and single-ended
modes; Channel Sequencer with signal averaging
Two current DACs (IDACs) for general-purpose or capacitive
sensing applications on any pin
Two low-power comparators that operate in Deep Sleep mode
Programmable Digital
Four programmable logic blocks called universal digital blocks,
(UDBs), each with 8 Macrocells and data path
Cypress-provided peripheral component library, user-defined
state machines, and Verilog input
Low Power 1.71-V to 5.5-V Operation
20-nA Stop Mode with GPIO pin wakeup
Hibernate and Deep Sleep modes allow wakeup-time versus
power trade-offs
Capacitive Sensing
Cypress CapSense Sigma-Delta (CSD) provides best-in-class
SNR (>5:1) and water tolerance
Cypress-supplied software component makes capacitive
sensing design easy
Automatic hardware tuning (SmartSense™)
Segment LCD Drive
LCD drive supported on all pins (common or segment)
Operates in Deep Sleep mode with 4 bits per pin memory
Serial Communication
Two independent run-time reconfigurable serial communi-
cation blocks (SCBs) with reconfigurable I2C, SPI, or UART
functionality
Timing and Pulse-Width Modulation
Four 16-bit timer/counter pulse-width modulator (TCPWM)
blocks
Center-aligned, Edge, and Pseudo-random modes
Comparator-based triggering of Kill signals for motor drive and
other high-reliability digital logic applications
Up to 36 Programmable GPIOs
Any GPIO pin can be CapSense, LCD, analog, or digital
Drive modes, strengths, and slew rates are programmable
Five different packages
48-pin TQFP, 44-pin TQFP, 40-pin QFN, 35-ball WLCSP, and
28-pin SSOP package
35-ball WLCSP package is shipped with I2C Bootloader in
Flash
Extended Industrial Temperature Operation
–40 °C to + 105 °C operation
PSoC Creator Design Environment
Integrated Development Environment (IDE) provides
schematic design entry and build (with analog and digital
automatic routing)
Applications Programming Interface (API) component for all
fixed-function and programmable peripherals
Industry-Standard Tool Compatibility
After schematic entry, development can be done with
ARM-based industry-standard development tools
General Description
PSoC® 4 is a scalable and reconfigurable platform architecture for a family of mixed-signal programmable embedded system
controllers with an ARM® Cortex™-M0 CPU. It combines programmable and reconfigurable analog and digital blocks with flexible
automatic routing. The PSoC 4200 product family, based on this platform, is a combination of a microcontroller with digital program-
mable logic, high-performance analog-to-digital conversion, opamps with Comparator mode, and standard communication and timing
peripherals. The PSoC 4200 products will be fully upward compatible with members of the PSoC 4 platform for new applications and
design needs. The programmable analog and digital sub-systems allow flexibility and in-field tuning of the design.
Features
32-bit MCU Sub-system
48-MHz ARM Cortex-M0 CPU with single cycle multiply
Up to 32 kB of flash with Read Accelerator
Up to 4 kB of SRAM
Programmable Analog
Two opamps with reconfigurable high-drive external and
high-bandwidth internal drive, Comparator modes, and ADC
input buffering capability
12-bit, 1-Msps SAR ADC with differential and single-ended
modes; Channel Sequencer with signal averaging
Two current DACs (IDACs) for general-purpose or capacitive
sensing applications on any pin
Two low-power comparators that operate in Deep Sleep mode
Programmable Digital
Four programmable logic blocks called universal digital blocks,
(UDBs), each with 8 Macrocells and data path
Cypress-provided peripheral component library, user-defined
state machines, and Verilog input
Low Power 1.71-V to 5.5-V Operation
20-nA Stop Mode with GPIO pin wakeup
Hibernate and Deep Sleep modes allow wakeup-time versus
power trade-offs
Capacitive Sensing
Cypress CapSense Sigma-Delta (CSD) provides best-in-class
SNR (>5:1) and water tolerance
Cypress-supplied software component makes capacitive
sensing design easy
Automatic hardware tuning (SmartSense™)
Segment LCD Drive
LCD drive supported on all pins (common or segment)
Operates in Deep Sleep mode with 4 bits per pin memory
Serial Communication
Two independent run-time reconfigurable serial communi-
cation blocks (SCBs) with reconfigurable I2C, SPI, or UART
functionality
Timing and Pulse-Width Modulation
Four 16-bit timer/counter pulse-width modulator (TCPWM)
blocks
Center-aligned, Edge, and Pseudo-random modes
Comparator-based triggering of Kill signals for motor drive and
other high-reliability digital logic applications
Up to 36 Programmable GPIOs
Any GPIO pin can be CapSense, LCD, analog, or digital
Drive modes, strengths, and slew rates are programmable
Five different packages
48-pin TQFP, 44-pin TQFP, 40-pin QFN, 35-ball WLCSP, and
28-pin SSOP package
35-ball WLCSP package is shipped with I2C Bootloader in
Flash
Extended Industrial Temperature Operation
–40 °C to + 105 °C operation
PSoC Creator Design Environment
Integrated Development Environment (IDE) provides
schematic design entry and build (with analog and digital
automatic routing)
Applications Programming Interface (API) component for all
fixed-function and programmable peripherals
Industry-Standard Tool Compatibility
After schematic entry, development can be done with
ARM-based industry-standard development tools
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PSoC® 4: PSoC 4200
Family Datasheet
Document Number: 001-87197 Rev. *J Page 2 of 45
More Information
Cypress provides a wealth of data at www.cypress.com to help you to select the right PSoC device for your design, and to help you
to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the knowledge base article
KBA86521, How to Design with PSoC 3, PSoC 4, and PSoC 5LP. Following is an abbreviated list for PSoC 4:
Overview: PSoC Portfolio, PSoC Roadmap
Product Selectors: PSoC 1, PSoC 3, PSoC 4, PSoC 5LP
In addition, PSoC Creator includes a device selection tool.
Application notes: Cypress offers a large number of PSoC
application notes covering a broad range of topics, from basic
to advanced level. Recommended application notes for getting
started with PSoC 4 are:
AN79953: Getting Started With PSoC 4
AN88619: PSoC 4 Hardware Design Considerations
AN86439: Using PSoC 4 GPIO Pins
AN57821: Mixed Signal Circuit Board Layout
AN81623: Digital Design Best Practices
AN73854: Introduction To Bootloaders
AN89610: ARM Cortex Code Optimization
AN90071: CY8CMBRxxx CapSense Design Guide
Technical Reference Manual (TRM) is in two documents:
Architecture TRM details each PSoC 4 functional block.
Registers TRM describes each of the PSoC 4 registers.
Development Kits:
CY8CKIT-042, PSoC 4 Pioneer Kit, is an easy-to-use and
inexpensive development platform. This kit includes
connectors for Arduino™ compatible shields and Digilent®
Pmod™ daughter cards.
CY8CKIT-049 is a very low-cost prototyping platform. It is a
low-cost alternative to sampling PSoC 4 devices.
CY8CKIT-001 is a common development platform for any
one of the PSoC 1, PSoC 3, PSoC 4, or PSoC 5LP families
of devices.
The MiniProg3 device provides an interface for flash
programming and debug.
PSoC Creator
PSoC Creator is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design
of PSoC 3, PSoC 4, and PSoC 5LP based systems. Create designs using classic, familiar schematic capture supported by over 100
pre-verified, production-ready PSoC Components; see the list of component datasheets. With PSoC Creator, you can:
1. Drag and drop component icons to build your hardware
system design in the main design workspace
2. Codesign your application firmware with the PSoC hardware,
using the PSoC Creator IDE C compiler
3. Configure components using the configuration tools
4. Explore the library of 100+ components
5. Review component datasheets
Figure 1. Multiple-Sensor Example Project in PSoC Creator
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PSoC® 4: PSoC 4200
Family Datasheet
Document Number: 001-87197 Rev. *J Page 3 of 45
Contents
Functional Definition........................................................ 5
CPU and Memory Subsystem ..................................... 5
System Resources ...................................................... 5
Analog Blocks.............................................................. 6
Programmable Digital.................................................. 7
Fixed Function Digital.................................................. 8
GPIO ........................................................................... 8
Special Function Peripherals....................................... 9
Pinouts ............................................................................ 10
Power............................................................................... 16
Unregulated External Supply..................................... 16
Regulated External Supply........................................ 17
Development Support .................................................... 18
Documentation .......................................................... 18
Online ........................................................................ 18
Tools.......................................................................... 18
Electrical Specifications ................................................ 19
Absolute Maximum Ratings....................................... 19
Device Level Specifications....................................... 19
Analog Peripherals.................................................... 23
Digital Peripherals ..................................................... 27
Memory ..................................................................... 30
System Resources .................................................... 31
Ordering Information...................................................... 35
Part Numbering Conventions .................................... 36
Packaging........................................................................ 37
Acronyms........................................................................ 41
Document Conventions................................................. 43
Units of Measure ....................................................... 43
Revision History............................................................. 44
Sales, Solutions, and Legal Information...................... 45
Worldwide Sales and Design Support....................... 45
Products .................................................................... 45
PSoC® Solutions ...................................................... 45
Cypress Developer Community................................. 45
Technical Support ..................................................... 45
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PSoC® 4: PSoC 4200
Family Datasheet
Document Number: 001-87197 Rev. *J Page 4 of 45
Figure 2. Block Diagram
The PSoC 4200 devices include extensive support for
programming, testing, debugging, and tracing both hardware
and firmware.
The ARM Serial_Wire Debug (SWD) interface supports all
programming and debug features of the device.
Complete debug-on-chip functionality enables full-device
debugging in the final system using the standard production
device. It does not require special interfaces, debugging pods,
simulators, or emulators. Only the standard programming
connections are required to fully support debug.
The PSoC Creator IDE provides fully integrated programming
and debug support for the PSoC 4200 devices. The SWD
interface is fully compatible with industry-standard third-party
tools. With the ability to disable debug features, with very robust
flash protection, and allowing customer-proprietary functionality
to be implemented in on-chip programmable blocks, the
PSoC 4200 family provides a level of security not possible with
multi-chip application solutions or with microcontrollers.
The debug circuits are enabled by default and can only be
disabled in firmware. If not enabled, the only way to re-enable
them is to erase the entire device, clear flash protection, and
reprogram the device with new firmware that enables debugging.
Additionally, all device interfaces can be permanently disabled
(device security) for applications concerned about phishing
attacks due to a maliciously reprogrammed device or attempts to
defeat security by starting and interrupting flash programming
sequences. Because all programming, debug, and test inter-
faces are disabled when maximum device security is enabled,
PSoC 4200 with device security enabled may not be returned for
failure analysis. This is a trade-off the PSoC 4200 allows the
customer to make.
PSoC 4200
32-bit
AHB-Lite
CPU Subsystem
SRAM
Up to 4 kB
SRAM Controller
ROM
4 kB
ROM Controller
FLASH
Up to 32 kB
Read Accelerator
Deep Sleep
Hibernate
Active /Sleep
SWD
NVIC, IRQMX
Cortex
M0
48 MHz
FAST MUL
System Interconnect (Single Layer AHB )
IO Subsystem
36x GPIOs
IOSS GPIO (5x ports)
Peripherals
System Resources
Power
Clock
WDT
ILO
Reset
Clock Control
DFT Logic
Test
IMO
DFT Analog
Sleep Control
PWRSYS
REF
POR LVD
NVLatches
BOD
WIC
Reset Control
XRES
Peripheral Interconnect (MMIO)
PCLK
4x TCPWM
LCD
2x SCB-I2C/SPI/UART
2x LP Comparator
Capsense
Port Interface & Digital System Interconnect (DSI)
Programmable
Digital
x4
UDB...UDB
Power Modes
CTBmSMX
SAR ADC
(12-bit)
x1
Programmable
Analog
x1
2x OpAmp
High Speed I/O Matrix
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PSoC® 4: PSoC 4200
Family Datasheet
Document Number: 001-87197 Rev. *J Page 5 of 45
Functional Definition
CPU and Memory Subsystem
CPU
The Cortex-M0 CPU in PSoC 4200 is part of the 32-bit MCU
subsystem, which is optimized for low-power operation with
extensive clock gating. It mostly uses 16-bit instructions and
executes a subset of the Thumb-2 instruction set. This enables
fully compatible binary upward migration of the code to higher
performance processors such as the Cortex-M3 and M4, thus
enabling upward compatibility. The Cypress implementation
includes a hardware multiplier that provides a 32-bit result in one
cycle. It includes a nested vectored interrupt controller (NVIC)
block with 32 interrupt inputs and also includes a Wakeup
Interrupt Controller (WIC). The WIC can wake the processor up
from the Deep Sleep mode, allowing power to be switched off to
the main processor when the chip is in the Deep Sleep mode.
The Cortex-M0 CPU provides a Non-Maskable Interrupt (NMI)
input, which is made available to the user when it is not in use
for system functions requested by the user.
The CPU also includes a debug interface, the serial wire debug
(SWD) interface, which is a 2-wire form of JTAG; the debug
configuration used for PSoC 4200 has four break-point (address)
comparators and two watchpoint (data) comparators.
Flash
The PSoC 4200 device has a flash module with a flash accel-
erator, tightly coupled to the CPU to improve average access
times from the flash block. The flash block is designed to deliver
1 wait-state (WS) access time at 48 MHz and with 0-WS access
time at 24 MHz. The flash accelerator delivers 85% of
single-cycle SRAM access performance on average. Part of the
flash module can be used to emulate EEPROM operation if
required.
The PSoC 4200 Flash supports the following flash protection
modes at the memory subsystem level:
Open: No Protection. Factory default mode in which the
product is shipped.
Protected: User may change from Open to Protected. This
mode disables Debug interface accesses. The mode can be
set back to Open but only after completely erasing the Flash.
Kill: User may change from Open to Kill. This mode disables
all Debug accesses. The part cannot be erased externally, thus
obviating the possibility of partial erasure by power interruption
and potential malfunction and security leaks. This is an irrecvo-
cable mode.
In addition, row-level Read/Write protection is also supported to
prevent inadvertent Writes as well as selectively block Reads.
Flash Read/Write/Erase operations are always available for
internal code using system calls.
SRAM
SRAM memory is retained during Hibernate.
SROM
A supervisory ROM that contains boot and configuration routines
is provided.
System Resources
Power System
The power system is described in detail in the section Power on
page 16. It provides assurance that voltage levels are as
required for each respective mode and either delay mode entry
(on power-on reset (POR), for example) until voltage levels are
as required for proper function or generate resets (brown-out
detect (BOD)) or interrupts (low-voltage detect (LVD)). The
PSoC 4200 operates with a single external supply over the range
of 1.71 to 5.5 V and has five different power modes, transitions
between which are managed by the power system. The
PSoC 4200 provides Sleep, Deep Sleep, Hibernate, and Stop
low-power modes.
Clock System
The PSoC 4200 clock system is responsible for providing clocks
to all subsystems that require clocks and for switching between
different clock sources without glitching. In addition, the clock
system ensures that no metastable conditions occur.
The clock system for PSoC 4200 consists of the internal main
oscillator (IMO) and the internal low-power oscillator (ILO) and a
provision for an external clock.
Figure 3. PSoC 4200 MCU Clocking Architecture
The HFCLK signal can be divided down (see PSoC 4200 MCU
Clocking Architecture) to generate synchronous clocks for the
UDBs, and the analog and digital peripherals. There are a total
of 12 clock dividers for PSoC 4200, each with 16-bit divide
capability; this allows eight to be used for the fixed-function
blocks and four for the UDBs. The analog clock leads the digital
clocks to allow analog events to occur before digital clock-related
noise is generated. The 16-bit capability allows a lot of flexibility
in generating fine-grained frequency values and is fully
supported in PSoC Creator. When UDB-generated pulse inter-
rupts are used, SYSCLK must equal HFCLK.
UDB
Dividers
Analog
Divider
Peripheral
Dividers
SYSCLK
PrescalerHFCLK
UDBn
SAR clock
PERXYZ_CLK
IMO
ILO
HFCLK
LFCLK
EXTCLK
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PSoC® 4: PSoC 4200
Family Datasheet
Document Number: 001-87197 Rev. *J Page 6 of 45
IMO Clock Source
The IMO is the primary source of internal clocking in PSoC 4200.
It is trimmed during testing to achieve the specified accuracy.
Trim values are stored in nonvolatile latches (NVL). Additional
trim settings from flash can be used to compensate for changes.
The IMO default frequency is 24 MHz and it can be adjusted
between 3 MHz to 48 MHz in steps of 1 MHz. The IMO tolerance
with Cypress-provided calibration settings is ±2%.
ILO Clock Source
The ILO is a very low-power oscillator, which is primarily used to
generate clocks for peripheral operation in Deep Sleep mode.
ILO-driven counters can be calibrated to the IMO to improve
accuracy. Cypress provides a software component, which does
the calibration.
Watchdog Timer
A watchdog timer is implemented in the clock block running from
the ILO; this allows watchdog operation during Deep Sleep and
generates a watchdog reset if not serviced before the timeout
occurs. The watchdog reset is recorded in the Reset Cause
register.
Reset
PSoC 4200 can be reset from a variety of sources including a
software reset. Reset events are asynchronous and guarantee
reversion to a known state. The reset cause is recorded in a
register, which is sticky through reset and allows software to
determine the cause of the Reset. An XRES pin is reserved for
external reset to avoid complications with configuration and
multiple pin functions during power-on or reconfiguration. The
XRES pin has an internal pull-up resistor that is always enabled.
Voltage Reference
The PSoC 4200 reference system generates all internally
required references. A 1% voltage reference spec is provided for
the 12-bit ADC. To allow better signal to noise ratios (SNR) and
better absolute accuracy, it is possible to bypass the internal
reference using a GPIO pin or to use an external reference for
the SAR.
Analog Blocks
12-bit SAR ADC
The 12-bit 1-Msps SAR ADC can operate at a maximum clock
rate of 18 MHz and requires a minimum of 18 clocks at that
frequency to do a 12-bit conversion.
The block functionality is augmented for the user by adding a
reference buffer to it (trimmable to ±1%) and by providing the
choice (for the PSoC-4200 case) of three internal voltage refer-
ences: VDD, VDD/2, and VREF (nominally 1.024 V) as well as an
external reference through a GPIO pin. The sample-and-hold
(S/H) aperture is programmable allowing the gain bandwidth
requirements of the amplifier driving the SAR inputs, which
determine its settling time, to be relaxed if required. System
performance will be 65 dB for true 12-bit precision providing
appropriate references are used and system noise levels permit.
To improve performance in noisy conditions, it is possible to
provide an external bypass (through a fixed pin location) for the
internal reference amplifier.
The SAR is connected to a fixed set of pins through an 8-input
sequencer. The sequencer cycles through selected channels
autonomously (sequencer scan) and does so with zero switching
overhead (that is, aggregate sampling bandwidth is equal to
1 Msps whether it is for a single channel or distributed over
several channels). The sequencer switching is effected through
a state machine or through firmware driven switching. A feature
provided by the sequencer is buffering of each channel to reduce
CPU interrupt service requirements. To accommodate signals
with varying source impedance and frequency, it is possible to
have different sample times programmable for each channel.
Also, signal range specification through a pair of range registers
(low and high range values) is implemented with a corresponding
out-of-range interrupt if the digitized value exceeds the
programmed range; this allows fast detection of out-of-range
values without the necessity of having to wait for a sequencer
scan to be completed and the CPU to read the values and check
for out-of-range values in software.
The SAR is able to digitize the output of the on-board temper-
ature sensor for calibration and other temperature-dependent
functions. The SAR is not available in Deep Sleep and Hibernate
modes as it requires a high-speed clock (up to 18 MHz). The
SAR operating range is 1.71 V to 5.5 V.
Figure 4. SAR ADC System Diagram
SARMUX
Port 2 (8 inputs)
vplusvminus
P0
P7
Data and
Status Flags
Reference
Selection
External
Reference
and
Bypass
(optional)
POS
NEG
SAR Sequencer
SARADC
Inputs from other Ports
VDD/2 VDDD VREF
AHB System Bus and Programmable Logic
Interconnect
Sequencing
and Control
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PSoC® 4: PSoC 4200
Family Datasheet
Document Number: 001-87197 Rev. *J Page 7 of 45
Two Opamps (CTBm Block)
PSoC 4200 has two opamps with Comparator modes which
allow most common analog functions to be performed on-chip
eliminating external components; PGAs, voltage buffers, filters,
trans-impedance amplifiers, and other functions can be realized
with external passives saving power, cost, and space. The
on-chip opamps are designed with enough bandwidth to drive
the S/H circuit of the ADC without requiring external buffering.
Temperature Sensor
PSoC 4200 has one on-chip temperature sensor This consists
of a diode, which is biased by a current source that can be
disabled to save power. The temperature sensor is connected to
the ADC, which digitizes the reading and produces a temper-
ature value using Cypress supplied software that includes
calibration and linearization.
Low-power Comparators
PSoC 4200 has a pair of low-power comparators, which can also
operate in the Deep Sleep and Hibernate modes. This allows the
analog system blocks to be disabled while retaining the ability to
monitor external voltage levels during low-power modes. The
comparator outputs are normally synchronized to avoid metasta-
bility unless operating in an asynchronous power mode
(Hibernate) where the system wake-up circuit is activated by a
comparator switch event.
Programmable Digital
Universal Digital Blocks (UDBs) and Port Interfaces
PSoC 4200 has four UDBs; the UDB array also provides a
switched Digital System Interconnect (DSI) fabric that allows
signals from peripherals and ports to be routed to and through
the UDBs for communication and control. The UDB array is
shown in the following figure.
Figure 5. UDB Array
UDBs can be clocked from a clock divider block, from a port
interface (required for peripherals such as SPI), and from the DSI
network directly or after synchronization.
A port interface is defined, which acts as a register that can be
clocked with the same source as the PLDs inside the UDB array.
This allows faster operation because the inputs and outputs can
be registered at the port interface close to the I/O pins and at the
edge of the array. The port interface registers can be clocked by
one of the I/Os from the same port. This allows interfaces such
as SPI to operate at higher clock speeds by eliminating the delay
for the port input to be routed over DSI and used to register other
inputs (see Figure 6).
The UDBs can generate interrupts (one UDB at a time) to the
interrupt controller. The UDBs retain the ability to connect to any
pin on the chip through the DSI.
Figure 6. Port Interface
Programmable Digital Subsystem
UDBIF
UDB UDB
UDB UDB
DSI DSI
DSI DSI
BUS IF CLK IF Port IF
Port IF
Port IF
High -Speed I/O Matrix
CPU
Sub-system
System
Interconnect Clocks
4 to 8
8 to 32
Routing
Channels
Other Digital
Signals in Chip
IRQ IF
Clock Selector
Block from
UDB
9
Digital
GlobalClocks
3 DSI Signals ,
1 I/O Signal
4
Reset Selector
Block from
UDB
2
2
Input Registers Output Registers
To DSI
8
From DSI
8
8 8
Enables
8
From DSI
4
4
7 6 . . . 0 7 6 . . . 0 3 2 1 0
High Speed I/O Matrix
To Clock
Tree
[0]
[0]
[1]
[1]
[1]
[1]
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PSoC® 4: PSoC 4200
Family Datasheet
Document Number: 001-87197 Rev. *J Page 8 of 45
Fixed Function Digital
Timer/Counter/PWM Block (TCPWM)
The TCPWM block consists of four 16-bit counters with
user-programmable period length. There is a Capture register to
record the count value at the time of an event (which may be an
I/O event), a period register used to either stop or auto-reload the
counter when its count is equal to the period register, and
compare registers to generate compare value signals which are
used as PWM duty cycle outputs. The block also provides true
and complementary outputs with programmable offset between
them to allow use as deadband programmable complementary
PWM outputs. It also has a Kill input to force outputs to a prede-
termined state; for example, this is used in motor drive systems
when an overcurrent state is indicated and the PWMs driving the
FETs need to be shut off immediately with no time for software
intervention.
Serial Communication Blocks (SCB)
PSoC 4200 has two SCBs, which can each implement an I2C,
UART, or SPI interface.
I2C Mode: The hardware I2C block implements a full
multi-master and slave interface (it is capable of multimaster
arbitration). This block is capable of operating at speeds of up to
1 Mbps (Fast Mode Plus) and has flexible buffering options to
reduce interrupt overhead and latency for the CPU. The FIFO
mode is available in all channels and is very useful in the
absence of DMA.
The I2C peripheral is compatible with the I2C Standard-mode,
Fast-mode, and Fast-Mode Plus devices as defined in the NXP
I2C-bus specification and user manual (UM10204). The I2C bus
I/O is implemented with GPIO in open-drain modes. The I2C bus
uses open-drain drivers for clock and data with pull-up resistors
on the bus for clock and data connected to all nodes. The
required Rise and Fall times for different I2C speeds are
guaranteed by using appropriate pull-up resistor values
depending on VDD, Bus Capacitance, and resistor tolerance.
For detailed information on how to calculate the optimum pull-up
resistor value for your design, refer to the UM10204 I2C bus
specification and user manual (the latest revision is available at
www.nxp.com).
PSoC 4200 is not completely compliant with the I2C spec in the
following respects:
GPIO cells are not overvoltage-tolerant and, therefore, cannot
be hot-swapped or powered up independently of the rest of the
I2C system.
Fast-Mode Plus has an IOL specification of 20 mA at a VOL of
0.4 V. The GPIO cells can sink a maximum of 8-mA IOL with a
VOL maximum of 0.6 V.
Fast mode and Fast-Mode Plus specify minimum Fall times,
which are not met with the GPIO cell; Slow strong mode can
help meet this spec depending on the Bus Load.
When the SCB is an I2C master, it interposes an IDLE state
between NACK and Repeated Start; the I2C spec defines Bus
free as following a Stop condition so other Active Masters do
not intervene but a Master that has just become activated may
start an Arbitration cycle.
When the SCB is in I2C slave mode, and Address Match on
External Clock is enabled (EC_AM = 1) along with operation in
the internally clocked mode (EC_OP = 0), then its I2C address
must be even.
UART Mode: This is a full-feature UART operating at up to
1 Mbps. It supports automotive single-wire interface (LIN),
infrared interface (IrDA), and SmartCard (ISO7816) protocols, all
of which are minor variants of the basic UART protocol. In
addition, it supports the 9-bit multiprocessor mode that allows
addressing of peripherals connected over common RX and TX
lines. Common UART functions such as parity error, break
detect, and frame error are supported. An 8-deep FIFO allows
much greater CPU service latencies to be tolerated. Note that
hardware handshaking is not supported. This is not commonly
used and can be implemented with a UDB-based UART in the
system, if required.
SPI Mode: The SPI mode supports full Motorola SPI, TI SSP
(essentially adds a start pulse used to synchronize SPI Codecs),
and National Microwire (half-duplex form of SPI). The SPI block
can use the FIFO.
GPIO
PSoC 4200 has 36 GPIOs. The GPIO block implements the
following:
Eight drive strength modes:
Analog input mode (input and output buffers disabled)
Input only
Weak pull-up with strong pull-down
Strong pull-up with weak pull-down
Open drain with strong pull-down
Open drain with strong pull-up
Strong pull-up with strong pull-down
Weak pull-up with weak pull-down
Input threshold select (CMOS or LVTTL).
Individual control of input and output buffer enabling/disabling
in addition to the drive strength modes.
Hold mode for latching previous state (used for retaining I/O
state in Deep Sleep mode and Hibernate modes).
Selectable slew rates for dV/dt related noise control to improve
EMI.
The pins are organized in logical entities called ports, which are
8-bit in width. During power-on and reset, the blocks are forced
to the disable state so as not to crowbar any inputs and/or cause
excess turn-on current. A multiplexing network known as a
high-speed I/O matrix is used to multiplex between various
signals that may connect to an I/O pin. Pin locations for
fixed-function peripherals are also fixed to reduce internal multi-
plexing complexity (these signals do not go through the DSI
network). DSI signals are not affected by this and any pin may
be routed to any UDB through the DSI network.
Data output and pin state registers store, respectively, the values
to be driven on the pins and the states of the pins themselves.
Every I/O pin can generate an interrupt if so enabled and each
I/O port has an interrupt request (IRQ) and interrupt service
routine (ISR) vector associated with it (5 for PSoC 4200 since it
has 4.5 ports).
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PSoC® 4: PSoC 4200
Family Datasheet
Document Number: 001-87197 Rev. *J Page 9 of 45
Special Function Peripherals
LCD Segment Drive
PSoC 4200 has an LCD controller which can drive up to four
commons and up to 32 segments. It uses full digital methods to
drive the LCD segments requiring no generation of internal LCD
voltages. The two methods used are referred to as digital corre-
lation and PWM.
Digital correlation pertains to modulating the frequency and
levels of the common and segment signals to generate the
highest RMS voltage across a segment to light it up or to keep
the RMS signal zero. This method is good for STN displays but
may result in reduced contrast with TN (cheaper) displays.
PWM pertains to driving the panel with PWM signals to effec-
tively use the capacitance of the panel to provide the integration
of the modulated pulse-width to generate the desired LCD
voltage. This method results in higher power consumption but
can result in better results when driving TN displays. LCD
operation is supported during Deep Sleep refreshing a small
display buffer (4 bits; 1 32-bit register per port).
CapSense
CapSense is supported on all pins in PSoC 4200 through a
CapSense Sigma-Delta (CSD) block that can be connected to
any pin through an analog mux bus that any GPIO pin can be
connected to via an Analog switch. CapSense function can thus
be provided on any pin or group of pins in a system under
software control. A component is provided for the CapSense
block to make it easy for the user.
Shield voltage can be driven on another Mux Bus to provide
water tolerance capability. Water tolerance is provided by driving
the shield electrode in phase with the sense electrode to keep
the shield capacitance from attenuating the sensed input.
The CapSense block has two IDACs which can be used for
general purposes if CapSense is not being used.(both IDACs are
available in that case) or if CapSense is used without water
tolerance (one IDAC is available).
WLCSP Package Bootloader
The WLCSP package is supplied with an I2C Bootloader
installed in flash. The bootloader is compatible with PSoC
Creator bootloadable project files and has the following default
settings:
I2C SCL and SDA connected to port pins P4.0 and P4.1 respec-
tively (external pull-up resistors required)
I2C Slave mode, address 8, data rate = 100 kbps
Single application
Wait two seconds for bootload command
Other bootloader options are as set by the PSoC Creator
Bootloader Component default
Occupies the bottom 4.5 KB of flash
For more information on this bootloader, see the following
Cypress application note:
AN73854 - Introduction to Bootloaders
Note that a PSoC Creator bootloadable project must be
associated with .hex and .elf files for a bootloader project that is
configured for the target device. Bootloader .hex and .elf files can
be found at http://www.cypress.com/?rID=78632. The
factory-installed bootloader can be overwritten using JTAG or
SWD programming.
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PSoC® 4: PSoC 4200
Family Datasheet
Document Number: 001-87197 Rev. *J Page 14 of 45
Figure 7. 48-Pin TQFP Pinout
Figure 8. 44-pin TQFP Part Pinout
TQFP
(Top View)
VD DD
10
11
P2[1]
33
32
31
30
29
28
27
26
25
24
23
36
35
34
2
3
4
5
6
7
8
9
12
13
14
15
16
17
18
19
20
21
22
VSS
(GPIO) P2[0]
(GPIO
)
(GPIO) P2[2]
(GPIO) P2[3]
(GPIO) P2[4]
(GPIO) P2[5]
(GPIO) P2[6]
(G PIO) P 2[7]
VSS
(GPIO) P3[0]
(GPIO) P3[1]
(G PIO ) P3 [ 4 ]
(GPIO) P3[5]
(GPIO) P3[6]
(GPIO) P3[7]
VDDD
(GPIO) P4[0]
(GPIO) P4[1]
(GPIO) P4[2] VD DA
(GPIO) P4[3]
(GPIO) P0[0]
(GPIO) P0[1]
(GPIO) P0[2]
(GPIO) P0[3]
(GPIO) P0[4]
(GPIO) P0[5]
(GPIO) P0[6]
(GPIO) P0[7]
XRES
VCCD
VSSA
(GPIO)P1[0] 37
38
39
40
1
41
42
43
44
(GPIO)P1[1]
(GPIO)P1[2]
(GPIO)P1[3]
(GPIO)P1[4]
(GPIO)P1[5]
(GPIO)P1[6]
(G PIO )P 1[7 ]
(GPIO) P3[2]
(GPIO) P3[3]
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PSoC® 4: PSoC 4200
Family Datasheet
Document Number: 001-87197 Rev. *J Page 15 of 45
Figure 9. 40-Pin QFN Pinout
Figure 10. 35-Ball WLCSP
Figure 11. 28-Pin SSOP Pinout
QFN
(Top View)
10
30
29
28
27
26
25
24
23
22
21
2
3
4
5
6
7
8
9
(GPIO)P3[3]
(GPIO)P2[1]
(GPIO)P2[3]
(GPIO)P2[4]
(GPIO)P2[6]
(GPIO)P2[7]
VSS
(GPIO)P3[1]
(GPIO)P3[2]
(GPIO)P3[5]
(GPIO)P3[6]
(GPIO)P3[7]
(GPIO)P4[0]
(GPIO)P4[1]
(GPIO)P4[2]
(GPIO)P4[3]
(GPIO)P0[0]
VDDD
(GPIO)P0[1]
(GPIO)P0[2]
(GPIO)P0[3]
(GPIO)P0[4]
(GPIO)P0[5]
(GPIO)P0[7]
XRES
(GPIO)P3[4]
VDDA
VSSA
1
(GPIO)P1[0]
(GPIO)P1[1]
(GPIO)P1[2]
(GPIO)P1[3]
(GPIO)P1[4]
(GPIO)P1[7]
VCCD
(GPIO)P3[0]
(GPIO)P2[0]
(GPIO)P2[2] (GPIO)P0[6]
(GPIO)P2[5]
20
19
18
17
16
15
14
13
12
11
31
32
33
34
35
36
37
38
39
40
7654321 1 2 3 4 5 6 7
A VCCD P0.5 P0.1 P0.2 P0.3 P4.2 P4.3 A P4.3 P4.2 P0.3 P0.2 P0.1 P0.5 VCCD
B VSS XRES P0.7 P0.6 P0.4 P4.1 P4.0 B P4.0 P4.1 P0.4 P0.6 P0.7 XRES VSS
C VDD P1.2 P1.1 P1.0 P0.0 P3.4 P3.3 C P3.3 P3.4 P0.0 P1.0 P1.1 P1.2 VDD
D P1.3 P1.6 P1.5 P1.4 P2.2 P3.1 P3.2 D P3.2 P3.1 P2.2 P1.4 P1.5 P1.6 P1.3
EP1.7/VREF P2.5 P2.4 P2.3 P2.6 P2.7 P3.0 E P3.0 P2.7 P2.6 P2.3 P2.4 P2.5 P1.7/VREF
Balls Up View Top View
(GPIO)P0[1]
SSOP
(Top View)
10
11
(GPIO)P1[2]
28
27
26
25
23
22
21
20
19
18
17
2
3
4
5
6
7
8
9
(GPIO)P1[1]
(GPIO)P1[7]
(GPIO)P2[2]
(GPIO)P2[3]
(GPIO)P2[4]
(GPIO)P2[5]
(GPIO)P2[6]
(GPIO)P3[0] (GPIO)P4[3]
(GPIO)P0[0]
(GPIO)P0[2]
(GPIO)P0[3]
(GPIO)P0[6]
(GPIO)P0[7]
XRES
VDDD
VSS
1
12
13
14
(GPIO)P1[0]
(GPIO)P3[1]
(GPIO)P3[2]
(GPIO)P4[2]
VCCD
(GPIO)P4[1]
(GPIO)P4[0]
16
15
24
(GPIO)P2[7]
(GPIO)P3[3]
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PSoC® 4: PSoC 4200
Family Datasheet
Document Number: 001-87197 Rev. *J Page 16 of 45
Power
The following power system diagrams show the minimum set of
power supply pins as implemented for the PSoC 4200. The
system has one regulator in Active mode for the digital circuitry.
There is no analog regulator; the analog circuits run directly from
the VDDA input. There are separate regulators for the Deep Sleep
and Hibernate (lowered power supply and retention) modes.
There is a separate low-noise regulator for the bandgap. The
supply voltage range is 1.71 to 5.5 V with all functions and
circuits operating over that range.
Figure 12. PSoC 4 Power Supply
The PSoC 4200 family allows two distinct modes of power supply
operation: Unregulated External Supply and Regulated External
Supply modes.
Unregulated External Supply
In this mode, PSoC 4200 is powered by an external power supply
that can be anywhere in the range of 1.8 V to 5.5 V. This range
is also designed for battery-powered operation, for instance, the
chip can be powered from a battery system that starts at 3.5 V
and works down to 1.8 V. In this mode, the internal regulator of
PSoC 4200 supplies the internal logic and the VCCD output of
PSoC 4200 must be bypassed to ground via an external
capacitor (in the range of 1 µF to 1.6 µF; X5R ceramic or better).
VDDA and VDDD must be shorted together; the grounds, VSSA
and VSS must also be shorted together. Bypass capacitors must
be used from VDDD to ground, typical practice for systems in this
frequency range is to use a capacitor in the 1-µF range in parallel
with a smaller capacitor (0.1 µF for example). Note that these are
simply rules of thumb and that, for critical applications, the PCB
layout, lead inductance, and the bypass capacitor parasitic
should be simulated to design and obtain optimal bypassing.
Figure 13. 48-TQFP Package Example
Figure 14. 44-TQFP Package Example
Analog
Domain
VDDA
VSSA
VDDA
1.8 Volt
Reg
VDDD
VSSD
VDDD
VCCD
Digital
Domain
Power Supply Bypass Capacitors
VDDD–VSS 0.1-µF ceramic at each pin (C2, C6) plus
bulk capacitor 1 µF to 10 µF (C1). Total
capacitance may be greater than 10 µF.
VDDA–VSSA 0.1-µF ceramic at pin (C4). Additional
1 µF to 10 µF (C3) bulk capacitor. Total
capacitance may be greater than 10 µF.
VCCD–VSS 1-µF ceramic capacitor at the VCCD pin
(C5)
VREF–VSSA
(optional)
The internal bandgap may be bypassed
with a 1-µF to 10-µF capacitor. Total
capacitance may be greater than 10 µF.
C2 0.1 µF
GROUND
1 µF C1
C5 1 µF
0.1 µF C4 C3 1 µF
GROUND
GROUND
GROUND
GROUND
C3 1 µF0.1 µF C4
48 47 46 45 44 43 42 41 40 39 38 37
(GPIO)P1.7/VREF
1?36 XRES
(GPIO) P2.0 235
(GPIO) P0.7
(GPIO) P2.1 334
(GPIO) P0.6
(GPIO) P2.2 433
(GPIO) P0.5
(GPIO) P2.3 548 TQFP 32 (GPIO) P0.4
(GPIO) P2.4 631
(GPIO) P0.3
(GPIO) P2.5 730
(GPIO) P0.2
(GPIO) P2.6 829
(GPIO) P0.1
(GPIO) P2.7 928
(GPIO) P0.0
NC 10 27 NC
NC 11 26 NC
(GPIO) P3.0 12 25 (GPIO) P4.3
13 14 15 16 17 18 19 20 21 22 23 24
(GPIO) P3.1
(GPIO) P3.2
VSSD
(GPIO) P3.3
(GPIO) P3.4
(GPIO) P3.5
(GPIO) P3.6
(GPIO) P3.7
VDDD
(GPIO) P4.0
(GPIO) P4.1
(GPIO) P4.2
(GPIO) P1.6
(GPIO) P1.5
(GPIO) P1.4
(GPIO) P1.3
(GPIO) P1.2
(GPIO) P1.1
(GPIO) P1.0
VSSA
VDDA
VDDD
VSSD
VCCD
Top View
TQFP
(Top View)
10
33
32
31
30
29
28
27
26
25
24
2
3
4
5
6
7
8
9
VSS
VDDA
VSSA
1
VDDD
22
21
20
19
18
17
16
15
14
13
34
35
36
37
38
39
40
41
42
43
44
11
12
23
VSS
VDDD
(GPIO)P2[0]
(GPIO)P2[1]
(GPIO)P2[2]
(GPIO)P2[3]
(GPIO)P2[4]
(GPIO)P2[5]
(GPIO)P2[6]
(GPIO)P2[7]
(GPIO)P3[0]
(GPIO) P3[3]
(GPIO) P3[1]
(GPIO) P3[2]
(GPIO) P3[5]
(GPIO) P3[6]
(GPIO) P3[7]
(GPIO) P4[0]
(GPIO) P4[1]
(GPIO) P4[2]
(GPIO) P3[4]
(GP IO) P4[3]
(GP IO) P0[0]
(GP IO) P0[1]
(GP IO) P0[2]
(GP IO) P0[3]
(GP IO) P0[4]
(GP IO) P0[5]
(GP IO) P0[7]
XRES
(GP IO) P0[6]
(GPIO)P1[2]
(GPIO)P1[3]
(GPIO)P1[4]
(GPIO)P1[5]
(GPIO)P1[6]
(GPIO)P1[7]
(GPIO)P1[1]
(GPIO)P1[0]
C2 0.1 µF
VSS
1 µF C1
VSS
C5 1 µF
VSS
VCCD
C6 0.1 µF
VSS
VSS
VSS
0.1 µF C4 C3 1 µF
CYPRESS uuuuuuuuuuuuuuuuuu HP HP 252? 4-H- HF
PSoC® 4: PSoC 4200
Family Datasheet
Document Number: 001-87197 Rev. *J Page 17 of 45
Note It is good practice to check the datasheets for your bypass
capacitors, specifically the working voltage and the DC bias
specifications. With some capacitors, the actual capacitance can
decrease considerably when the DC bias (VDDA, VDDD, or VCCD)
is a significant percentage of the rated working voltage. VDDA
must be equal to or higher than the VDDD supply when powering
up.
Figure 15. 40-pin QFN Example
Figure 16. 28-SSOP Example Regulated External Supply
In this mode, PSoC 4200 is powered by an external power supply
that must be within the range of 1.71 V to 1.89 V (1.8 ±5%); note
that this range needs to include power supply ripple too. In this
mode, VCCD, VDDA, and VDDD pins are all shorted together and
bypassed. The internal regulator is disabled in firmware.
(GPIO) P3[3]
(GPIO) P4[1]
(GPIO) P4[2]
(GPIO) P3[4]
0.1 µF C4
C5 1 µF
QFN
(Top View)
10
11
30
29
28
27
26
25
24
23
22
21
33
32
31
2
3
4
5
6
7
8
9
12
13
14
15
16
17
18
19
20
(GPIO) P2[1]
(GPIO) P2[3]
(GPIO) P2[4]
(GPIO) P2[5]
(GPIO) P2[6]
(GPIO) P2[7]
VSS
(GPIO) P3[1]
(GPIO) P3[2]
(GPIO) P3[5]
(GPIO) P3[6]
(GPIO) P3[7]
(GPIO) P4[0]
(GPIO) P4[3]
(GPIO) P0[0]
VDDD
(GPIO) P0[1]
(GPIO) P0[2]
(GPIO) P0[3]
(GPIO) P0[4]
(GPIO) P0[5]
(GPIO) P0[6]
(GPIO) P0[7]
XRES
VDDA
VSSA 34
35
36
37
1
38
39
40
(GPIO)P1[0]
(GPIO)P1[1]
(GPIO)P1[2]
(GPIO)P1[3]
(GPIO)P1[4]
(GPIO)P1[7]
VCCD
(GPIO) P3[0]
(GPIO) P2[0]
(GPIO) P2[2]
VSS
VSS
VSS
VSS
VSS
C3 1µF1µF C1 C2 0.1 µF
(GPIO) P3[0]
( GPIO) P0[1]
SSOP
( Top View)
10
11
P1[2]
28
27
26
25
23
22
21
20
19
18
17
2
3
4
5
6
7
8
9
(GPIO)
P1[1]
(GPIO )
(GPIO) P1[7]
( GPIO) P2[2]
(GPIO ) P2[3]
(GPIO ) P2[4]
(GPIO ) P2[5]
(GPIO) 2[6]
(GPIO) P4[3]
(GPIO) P0[0]
( GPIO) P0[2]
( GPIO) P0[3]
( GPIO) P0[6]
(GPIO) P0[7]
XRES
VDDD
VSS1
12
13
14
(GPIO )
P1[0]
(GPIO)
P3[1]
(GPIO)
P3[2]
(GPIO )
P3[3]
(GPIO)
P2[7]
(GPIO)
P4[2]
VCCD
(GPIO)
P4[1]
(GPIO)
P4[0]
16
15
24 C3 1µF
VSS
VSS
0.1 µF C2 C1 1µF VSS
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PSoC® 4: PSoC 4200
Family Datasheet
Document Number: 001-87197 Rev. *J Page 18 of 45
Development Support
The PSoC 4200 family has a rich set of documentation, devel-
opment tools, and online resources to assist you during your
development process. Visit www.cypress.com/go/psoc4 to find
out more.
Documentation
A suite of documentation supports the PSoC 4200 family to
ensure that you can find answers to your questions quickly. This
section contains a list of some of the key documents.
Software User Guide: A step-by-step guide for using PSoC
Creator. The software user guide shows you how the PSoC
Creator build process works in detail, how to use source control
with PSoC Creator, and much more.
Component Datasheets: The flexibility of PSoC allows the
creation of new peripherals (components) long after the device
has gone into production. Component data sheets provide all of
the information needed to select and use a particular component,
including a functional description, API documentation, example
code, and AC/DC specifications.
Application Notes: PSoC application notes discuss a particular
application of PSoC in depth; examples include brushless DC
motor control and on-chip filtering. Application notes often
include example projects in addition to the application note
document.
Technical Reference Manual: The Technical Reference Manual
(TRM) contains all the technical detail you need to use a PSoC
device, including a complete description of all PSoC registers.
The TRM is available in the Documentation section at
www.cypress.com/psoc4.
Online
In addition to print documentation, the Cypress PSoC forums
connect you with fellow PSoC users and experts in PSoC from
around the world, 24 hours a day, 7 days a week.
Tools
With industry standard cores, programming, and debugging
interfaces, the PSoC 4200 family is part of a development tool
ecosystem. Visit us at www.cypress.com/go/psoccreator for the
latest information on the revolutionary, easy to use PSoC Creator
IDE, supported third party compilers, programmers, debuggers,
and development kits.
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PSoC® 4: PSoC 4200
Family Datasheet
Document Number: 001-87197 Rev. *J Page 19 of 45
Electrical Specifications
Absolute Maximum Ratings
Device Level Specifications
All specifications are valid for –40 °C TA 105 °C and TJ 125 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
Note
1. Usage above the absolute maximum conditions listed in Tab le 1 may cause permanent damage to the device. Exposure to absolute maximum conditions for extended
periods of time may affect device reliability. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature
Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification.
Table 1. Absolute Maximum Ratings[1]
Spec ID# Parameter Description Min Typ Max Units Details/
Conditions
SID1 VDDD_ABS Digital supply relative to VSSD –0.5 – 6 V Absolute max
SID2 VCCD_ABS Direct digital core voltage input relative
to Vssd
–0.5 – 1.95 V Absolute max
SID3 VGPIO_ABS GPIO voltage –0.5 VDD+0.5 V Absolute max
SID4 IGPIO_ABS Maximum current per GPIO –25 25 mA Absolute max
SID5 IGPIO_injection GPIO injection current, Max for VIH >
VDDD, and Min for VIL < VSS
–0.5 0.5 mA Absolute max,
current injected
per pin
BID44 ESD_HBM Electrostatic discharge human body
model
2200 – V
BID45 ESD_CDM Electrostatic discharge charged device
model
500 – V
BID46 LU Pin current for latch-up –200 200 mA
Table 2. DC Specifications
Spec ID# Parameter Description Min Typ Max Units Details/
Conditions
SID53 VDD Power Supply Input Voltage
(VDDA = VDDD = VDD)
1.8 5.5 V With regulator enabled
SID255 VDDD Power Supply Input Voltage unregulated 1.71 1.8 1.89 V Internally unregulated
supply
SID54 VCCD Output voltage (for core logic) 1.8 V
SID55 CEFC External Regulator voltage bypass 1 1.3 1.6 µF X5R ceramic or better
SID56 CEXC Power supply decoupling capacitor 1 µF X5R ceramic or better
Active Mode, VDD = 1.71 V to 5.5 V. Typical Values measured at VDD = 3.3 V
SID9 IDD4 Execute from Flash; CPU at 6 MHz 2.8 mA
SID10 IDD5 Execute from Flash; CPU at 6 MHz 2.2 mA T = 25 °C
SID12 IDD7 Execute from Flash; CPU at 12 MHz, 4.2 mA
SID13 IDD8 Execute from Flash; CPU at 12 MHz 3.7 mA T = 25 °C
SID16 IDD11 Execute from Flash; CPU at 24 MHz 6.7 mA T = 25 °C
SID17 IDD12 Execute from Flash; CPU at 24 MHz 7.2 mA
SID19 IDD14 Execute from Flash; CPU at 48 MHz 12.8 mA T = 25 °C
SID20 IDD15 Execute from Flash; CPU at 48 MHz 13.8 mA
Sleep Mode, VDD = 1.7V to 5.5V
SID25 IDD20 I2C wakeup, WDT, and Comparators on.
6 MHz.
–1.31.8 mAV
DD = 1.71 to 5.5 V.
SID25A IDD20A I2C wakeup, WDT, and Comparators on.
12 MHz
–1.72.2 mAV
DD = 1.71 to 5.5 V.
m m
PSoC® 4: PSoC 4200
Family Datasheet
Document Number: 001-87197 Rev. *J Page 20 of 45
Deep Sleep Mode, VDD = 1.8 V to 3.6 V (Regulator on)
SID31 IDD26 I2C wakeup and WDT on. 1.3 µA T = 25 °C
SID32 IDD27 I2C wakeup and WDT on. 45 µA T = 85 °C
Deep Sleep Mode, VDD = 3.6V to 5.5V
SID34 IDD29 I2C wakeup and WDT on 1.5 15 µA Typ. at 25 °C. Max at 85
°C.
Deep Sleep Mode, VDD = 1.71 V to 1.89 V (Regulator bypassed)
SID37 IDD32 I2C wakeup and WDT on. 1.7 µA T = 25 °C
SID38 IDD33 I2C wakeup and WDT on 60 µA T = 85 °C
Deep Sleep Mode, +105 °C
SID33Q IDD28Q I2C wakeup and WDT on. Regulator Off. 135 µA VDD = 1.71 to 1.89
SID34Q IDD29Q I2C wakeup and WDT on. 180 µA VDD = 1.8 to 3.6
SID35Q IDD30Q I2C wakeup and WDT on. 140 µA VDD = 3.6 to 5.5
Hibernate Mode, VDD = 1.8 V to 3.6 V (Regulator on)
SID40 IDD35 GPIO and Reset active 150 - nA T = 25 °C
SID41 IDD36 GPIO and Reset active 1000 nA T = 85 °C
Hibernate Mode, VDD = 3.6 V to 5.5 V
SID43 IDD38 GPIO and Reset active 150 nA T = 25 °C
Hibernate Mode, VDD = 1.71 V to 1.89 V (Regulator bypassed)
SID46 IDD41 GPIO and Reset active 150 nA T = 25 °C
SID47 IDD42 GPIO and Reset active 1000 nA T = 85 °C
Hibernate Mode, +105 °C
SID42Q IDD37Q Regulator Off 19.4 µA VDD = 1.71 to 1.89
SID43Q IDD38Q 17 µA VDD = 1.8 to 3.6
SID44Q IDD39Q 16 µA VDD = 3.6 to 5.5
Stop Mode
SID304 IDD43A Stop Mode current; VDD = 3.3 V 20 80 nA Typ. at 25 °C. Max at 85
°C.
Stop Mode, +105 °C
SID304Q IDD43AQ Stop Mode current; VDD = 3.6 V 5645 nA
XRES current
SID307 IDD_XR Supply current while XRES asserted 2 5 mA
Table 2. DC Specifications (continued)
Spec ID# Parameter Description Min Typ Max Units Details/
Conditions
Table 3. AC Specifications
Spec ID# Parameter Description Min Typ Max Units Details/
Conditions
SID48 FCPU CPU frequency DC 48 MHz 1.71 VDD 5.5
SID49 TSLEEP Wakeup from sleep mode 0 µs Guaranteed by
characterization
SID50 TDEEPSLEEP Wakeup from Deep Sleep mode 25 µs 24 MHz IMO.
Guaranteed by
characterization
SID51 THIBERNATE Wakeup from Hibernate and Stop
modes
2 ms Guaranteed by
characterization
SID52 TRESETWIDTH External reset pulse width 1 µs Guaranteed by
characterization
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PSoC® 4: PSoC 4200
Family Datasheet
Document Number: 001-87197 Rev. *J Page 21 of 45
GPIO
Note
2. VIH must not exceed VDDD + 0.2 V.
Table 4. GPIO DC Specifications
Spec ID# Parameter Description Min Typ Max Units Details/
Conditions
SID57 VIH[2] Input voltage high threshold 0.7 ×
VDDD
–– VCMOS Input
SID58 VIL Input voltage low threshold 0.3 ×
VDDD
VCMOS Input
SID241 VIH[2] LVTTL input, VDDD < 2.7 V 0.7×
VDDD
–– V
SID242 VIL LVTTL input, VDDD < 2.7 V 0.3 ×
VDDD
V
SID243 VIH[2] LVTTL input, VDDD 2.7 V 2.0 V
SID244 VIL LVTTL input, VDDD 2.7 V 0.8 V
SID59 VOH Output voltage high level VDDD
–0.6
–– VI
OH = 4 mA at
3-V VDDD
SID60 VOH Output voltage high level VDDD
–0.5
–– VI
OH = 1 mA at
1.8-V VDDD
SID61 VOL Output voltage low level 0.4 V IOL = 4 mA at
1.8-V VDDD
SID62 VOL Output voltage low level 0.6 V IOL = 8 mA at 3-V
VDDD
SID62A VOL Output voltage low level 0.4 V IOL = 3 mA at 3-V
VDDD
SID63 RPULLUP Pull-up resistor 3.5 5.6 8.5 k
SID64 RPULLDOWN Pull-down resistor 3.5 5.6 8.5 k
SID65 IIL Input leakage current (absolute value) 2 nA 25 °C, VDDD =
3.0 V
SID65A IIL_CTBM Input leakage current (absolute value)
for CTBM pins
–– 4nA
SID66 CIN Input capacitance 7 pF
SID67 VHYSTTL Input hysteresis LVTTL 25 40 mV VDDD 2.7 V.
Guaranteed by
characterization
SID68 VHYSCMOS Input hysteresis CMOS 0.05 ×
VDDD
mV Guaranteed by
characterization
SID69 IDIODE Current through protection diode to
VDD/Vss
––100µA Guaranteed by
characterization
SID69A ITOT_GPIO Maximum Total Source or Sink Chip
Current
200 mA Guaranteed by
characterization
1'! z- CYPRESS nnnnnnnnnnnnnnnnnn m /\ m a m m /\ m /\
PSoC® 4: PSoC 4200
Family Datasheet
Document Number: 001-87197 Rev. *J Page 22 of 45
XRES
Table 5. GPIO AC Specifications
(Guaranteed by Characterization)
Spec ID# Parameter Description Min Typ Max Units Details/
Conditions
SID70 TRISEF Rise time in fast strong mode 2 12 ns 3.3-V VDDD,
Cload = 25 pF
SID71 TFALLF Fall time in fast strong mode 2 12 ns 3.3-V VDDD,
Cload = 25 pF
SID72 TRISES Rise time in slow strong mode 10 60 ns 3.3-V VDDD,
Cload = 25 pF
SID73 TFALLS Fall time in slow strong mode 10 60 ns 3.3-V VDDD,
Cload = 25 pF
SID74 FGPIOUT1 GPIO Fout;3.3 V VDDD 5.5 V. Fast
strong mode.
33 MHz 90/10%, 25-pF
load, 60/40 duty
cycle
SID75 FGPIOUT2 GPIO Fout;1.7 VVDDD3.3 V. Fast
strong mode.
16.7 MHz 90/10%, 25-pF
load, 60/40 duty
cycle
SID76 FGPIOUT3 GPIO Fout;3.3 V VDDD 5.5 V. Slow
strong mode.
7 MHz 90/10%, 25-pF
load, 60/40 duty
cycle
SID245 FGPIOUT4 GPIO Fout;1.7 V VDDD 3.3 V. Slow
strong mode.
3.5 MHz 90/10%, 25-pF
load, 60/40 duty
cycle
SID246 FGPIOIN GPIO input operating frequency;
1.71 V VDDD 5.5 V
48 MHz 90/10% VIO
Table 6. XRES DC Specifications
Spec ID# Parameter Description Min Typ Max Units Details/
Conditions
SID77 VIH Input voltage high threshold 0.7 ×
VDDD
V CMOS input
SID78 VIL Input voltage low threshold 0.3 ×
VDDD
V CMOS input
SID79 RPULLUP Pull-up resistor 3.5 5.6 8.5 k
SID80 CIN Input capacitance 3 pF
SID81 VHYSXRES Input voltage hysteresis 100 mV Guaranteed by
characterization
SID82 IDIODE Current through protection diode to
VDDD/VSS
100 µA Guaranteed by
characterization
Table 7. XRES AC Specifications
Spec ID# Parameter Description Min Typ Max Units Details/
Conditions
SID83 TRESETWIDTH Reset pulse width 1 µs Guaranteed by
characterization
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PSoC® 4: PSoC 4200
Family Datasheet
Document Number: 001-87197 Rev. *J Page 23 of 45
Analog Peripherals
Opamp
Table 8. Opamp Specifications
(Guaranteed by Characterization)
Spec ID# Parameter Description Min Typ Max Units Details/
Conditions
IDD Opamp block current. No load.
SID269 IDD_HI Power = high 1100 1850 µA
SID270 IDD_MED Power = medium 550 950 µA
SID271 IDD_LOW Power = low 150 350 µA
GBW Load = 20 pF, 0.1 mA. VDDA = 2.7 V
SID272 GBW_HI Power = high 6 MHz
SID273 GBW_MED Power = medium 4 MHz
SID274 GBW_LO Power = low 1 MHz
IOUT_MAX VDDA 2.7 V, 500 mV from rail
SID275 IOUT_MAX_HI Power = high 10 mA
SID276 IOUT_MAX_MID Power = medium 10 mA
SID277 IOUT_MAX_LO Power = low 5 mA
IOUT VDDA = 1.71 V, 500 mV from rail
SID278 IOUT_MAX_HI Power = high 4 mA
SID279 IOUT_MAX_MID Power = medium 4 mA
SID280 IOUT_MAX_LO Power = low 2 mA
SID281 VIN Charge pump on, VDDA 2.7 V –0.05 VDDA – 0.2 V
SID282 VCM Charge pump on, VDDA 2.7 V –0.05 VDDA 0.2 V
VOUT VDDA 2.7 V
SID283 VOUT_1 Power = high, Iload=10 mA 0.5 VDDA 0.5 V
SID284 VOUT_2 Power = high, Iload=1 mA 0.2 VDDA 0.2 V
SID285 VOUT_3 Power = medium, Iload=1 mA 0.2 VDDA 0.2 V
SID286 VOUT_4 Power = low, Iload=0.1mA 0.2 VDDA 0.2 V
SID288 VOS_TR Offset voltage, trimmed 1 ±0.5 1 mV High mode
SID288A VOS_TR Offset voltage, trimmed ±1 mV Medium mode
SID288B VOS_TR Offset voltage, trimmed ±2 mV Low mode
SID290 VOS_DR_TR Offset voltage drift, trimmed –10 ±3 10 µV/°C High mode.
TA 85 °C
SID290Q VOS_DR_TR Offset voltage drift, trimmed 15 ±3 15 µV/°C High mode.
TA 105 °C
SID290A VOS_DR_TR Offset voltage drift, trimmed ±10 µV/°C Medium mode
SID290B VOS_DR_TR Offset voltage drift, trimmed ±10 µV/°C Low mode
SID291 CMRR DC 70 80 dB VDDD = 3.6 V
SID292 PSRR At 1 kHz, 100-mV ripple 70 85 dB VDDD = 3.6 V
Noise – –
SID293 VN1 Input referred, 1 Hz - 1GHz, power =
high
– 94 µVrms
SID294 VN2 Input referred, 1 kHz, power = high 72 nV/rtHz
SID295 VN3 Input referred, 10kHz, power = high 28 nV/rtHz
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PSoC® 4: PSoC 4200
Family Datasheet
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Comparatorr
SID296 VN4 Input referred, 100kHz, power = high 15 nV/rtHz
SID297 Cload Stable up to maximum load. Perfor-
mance specs at 50 pF.
– 125 pF
SID298 Slew_rate Cload = 50 pF, Power = High, VDDA
2.7 V
6– – V/µs
SID299 T_op_wake From disable to enable, no external RC
dominating
–300 – µs
SID299A OL_GAIN Open Loop Gain 90 dB Guaranteed by
design
Comp_mode Comparator mode; 50 mV drive,
Trise = Tfall (approx.)
–– –
SID300 TPD1 Response time; power = high 150 ns
SID301 TPD2 Response time; power = medium 400 ns
SID302 TPD3 Response time; power = low 2000 ns
SID303 Vhyst_op Hysteresis 10 mV
Table 8. Opamp Specifications
(Guaranteed by Characterization) (continued)
Spec ID# Parameter Description Min Typ Max Units Details/
Conditions
Table 9. Comparator DC Specifications
Spec ID# Parameter Description Min Typ Max Units Details/
Conditions
SID85 VOFFSET2 Input offset voltage, Common Mode
voltage range from 0 to VDD-1
–– ±4 mV
SID85A VOFFSET3 Input offset voltage. Ultra low-power
mode (VDDD 2.2 V for Temp < 0 °C,
VDDD 1.8 V for Temp > 0 °C)
–±12 mV
SID86 VHYST Hysteresis when enabled, Common
Mode voltage range from 0 to VDD -1.
10 35 mV Guaranteed by
characterization
SID87 VICM1 Input common mode voltage in normal
mode
0–V
DDD – 0.1 V Modes 1 and 2.
SID247 VICM2 Input common mode voltage in low
power mode (VDDD 2.2 V for Temp <
C, V
DDD 1.8 V for Temp > 0 °C)
0–V
DDD V
SID247A VICM3 Input common mode voltage in ultra low
power mode
0–V
DDD
1.15
V
SID88 CMRR Common mode rejection ratio 50 dB VDDD 2.7 V.
Guaranteed by
characterization
SID88A CMRR Common mode rejection ratio 42 dB VDDD 2.7 V.
Guaranteed by
characterization
SID89 ICMP1 Block current, normal mode 400 µA Guaranteed by
characterization
SID248 ICMP2 Block current, low power mode 100 µA Guaranteed by
characterization
SID259 ICMP3 Block current, ultra low power mode
(VDDD 2.2 V for Temp < 0 °C, VDDD
1.8V for Temp >C)
6 28 µA Guaranteed by
characterization
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PSoC® 4: PSoC 4200
Family Datasheet
Document Number: 001-87197 Rev. *J Page 25 of 45
Temperature Sensor
SAR ADC
SID90 ZCMP DC input impedance of comparator 35 MGuaranteed by
characterization
Table 9. Comparator DC Specifications (continued)
Spec ID# Parameter Description Min Typ Max Units Details/
Conditions
Table 10. Comparator AC Specifications
(Guaranteed by Characterization)
Spec ID# Parameter Description Min Typ Max Units Details/Conditions
SID91 TRESP1 Response time, normal mode 110 ns 50-mV overdrive
SID258 TRESP2 Response time, low power mode 200 ns 50-mV overdrive
SID92 TRESP3 Response time, ultra low power mode
(VDDD 2.2V for Temp <C, V
DDD
1.8 V for Temp > 0 °C)
– – 15 µs 200-mV overdrive
Table 11. Temperature Sensor Specifications
Spec ID# Parameter Description Min Typ Max Units Details/Conditions
SID93 TSENSACC Temperature sensor accuracy 5 ±1 +5 °C –40 to +85 °C
Table 12. SAR ADC DC Specifications
Spec ID# Parameter Description Min Typ Max Units Details/Conditions
SID94 A_RES Resolution 12 bits
SID95 A_CHNIS_S Number of channels - single ended 8 8 full speed
SID96 A-CHNKS_D Number of channels - differential 4 Diff inputs use
neighboring I/O
SID97 A-MONO Monotonicity Yes. Based on
characterization
SID98 A_GAINERR Gain error ±0.1 % With external
reference.
Guaranteed by
characterization
SID99 A_OFFSET Input offset voltage 2 mV Measured with 1-V
VREF. Guaranteed by
characterization
SID100 A_ISAR Current consumption 1 mA
SID101 A_VINS Input voltage range - single ended VSS –V
DDA V Based on device
characterization
SID102 A_VIND Input voltage range - differential VSS – VDDA V Based on device
characterization
SID103 A_INRES Input resistance 2.2 KBased on device
characterization
SID104 A_INCAP Input capacitance 10 pF Based on device
characterization
SID106 A_PSRR Power supply rejection ratio 70 dB
SID107 A_CMRR Common mode rejection ratio 66 dB Measured at 1 V
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PSoC® 4: PSoC 4200
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SID111 A_INL Integral non linearity –1.7 +2 LSB VDD = 1.71 to 5.5,
1 Msps, Vref = 1 to
5.5.
SID111A A_INL Integral non linearity –1.5 +1.7 LSB VDDD = 1.71 to 3.6,
1 Msps, Vref = 1.71 to
VDDD.
SID111B A_INL Integral non linearity –1.5 +1.7 LSB VDDD = 1.71 to 5.5,
500 Ksps, Vref = 1 to
5.5.
SID112 A_DNL Differential non linearity –1 +2.2 LSB VDDD = 1.71 to 5.5, 1
Msps, Vref = 1 to 5.5.
SID112A A_DNL Differential non linearity –1 +2 LSB VDDD = 1.71 to 3.6, 1
Msps, Vref = 1.71 to
VDDD.
SID112B A_DNL Differential non linearity –1 +2.2 LSB VDDD = 1.71 to 5.5,
500 Ksps, Vref = 1 to
5.5.
Table 12. SAR ADC DC Specifications (continued)
Spec ID# Parameter Description Min Typ Max Units Details/Conditions
Table 13. SAR ADC AC Specifications
(Guaranteed by Characterization)
Spec ID# Parameter Description Min Typ Max Units Details/Conditions
SID108 A_SAMP_1 Sample rate with external reference
bypass cap
1 Msps
SID108A A_SAMP_2 Sample rate with no bypass cap.
Reference = VDD
––500Ksps
SID108B A_SAMP_3 Sample rate with no bypass cap.
Internal reference
––100Ksps
SID109 A_SNDR Signal-to-noise and distortion ratio
(SINAD)
65 dB FIN = 10 kHz
SID113 A_THD Total harmonic distortion –65 dB FIN = 10 kHz.
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PSoC® 4: PSoC 4200
Family Datasheet
Document Number: 001-87197 Rev. *J Page 27 of 45
CSD
Table 14. CSD Specifications
Spec ID# Parameter Description Min Typ Max Units Details/
Conditions
SID.CSD#16 IDAC1IDD IDAC1 (8 bits) block current 1125 μA
SID.CSD#17 IDAC2IDD IDAC2 (7 bits) block current 1125 μA
SID308 VCSD Voltage range of operation 1.71 5.5 V
SID308A Vcompidac Voltage compliance range of IDAC for S0 0.8 VDD-0.8 V
SID309 IDAC1 DNL for 8-bit resolution –1 1 LSB
SID310 IDAC1 INL for 8-bit resolution –3 3 LSB
SID311 IDAC2 DNL for 7-bit resolution –1 1 LSB
SID312 IDAC2 INL for 7-bit resolution –3 3 LSB
SID313 SNR Ratio of counts of finger to noise, 0.1-pF
sensitivity
5 – – Ratio Capacitance
range of 9 to 35 pF,
0.1-pF sensitivity
SID314 IDAC1_CRT1 Output current of Idac1 (8 bits) in High
range
– 612 uA
SID314A IDAC1_CRT2 Output current of Idac1 (8 bits) in Low
range
– 306 uA
SID315 IDAC2_CRT1 Output current of Idac2 (7 bits) in High
range
– 304.8 uA
SID315A IDAC2_CRT2 Output current of Idac2 (7 bits) in Low
range
– 152.4 uA
SID320 IDACOFFSET All zeroes input ±1 LSB
SID321 IDACGAIN Full-scale error less offset ±10 %
SID322 IDACMISMATCH Mismatch between IDACs 7 LSB
SID323 IDACSET8 Settling time to 0.5 LSB for 8-bit IDAC 10 μs Full-scale
transition. No
external load.
SID324 IDACSET7 Settling time to 0.5 LSB for 7-bit IDAC 10 μs Full-scale
transition. No
external load.
SID325 CMOD External modulator capacitor 2.2 nF 5-V rating, X7R or
NP0 cap.
CYPRESS EHIEDDEDu-Iwckknw All modes All modes All modes Fc max : Fcpu. Trigger Evenls can be Minimum possible Minimum lime Minimum pulse widlh Minimum pulse widlh
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Family Datasheet
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Digital Peripherals
The following specifications apply to the Timer/Counter/PWM peripherals in the Timer mode.
Timer/Counter/PWM
I2C
Table 15. TCPWM Specifications
(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID.TCPWM.1 ITCPWM1 Block current consumption at 3 MHz 45 µA All modes
(Timer/Counter/PWM)
SID.TCPWM.2 ITCPWM2 Block current consumption at 12 MHz 155 µA All modes
(Timer/Counter/PWM)
SID.TCPWM.2A ITCPWM3 Block current consumption at 48 MHz 650 µA All modes
(Timer/Counter/PWM)
SID.TCPWM.3 TCPWMFREQ Operating frequency Fc MHz Fc max = Fcpu.
Maximum = 24 MHz
SID.TCPWM.4 TPWMENEXT Input Trigger Pulse Width for all
Trigger Events 2/Fc – ns
Trigger Events can be
Stop, Start, Reload,
Count, Capture, or Kill
depending on which
mode of operation is
selected.
SID.TCPWM.5 TPWMEXT Output Trigger Pulse widths 2/Fc ns
Minimum possible
width of Overflow,
Underflow, and CC
(Counter equals
Compare value)
trigger outputs
SID.TCPWM.5A TCRES Resolution of Counter 1/Fc ns
Minimum time
between successive
counts
SID.TCPWM.5B PWMRES PWM Resolution 1/Fc ns Minimum pulse width
of PWM Output
SID.TCPWM.5C QRES Quadrature inputs resolution 1/Fc ns
Minimum pulse width
between Quadrature
phase inputs.
Table 16. Fixed I2C DC Specifications
(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID149 II2C1 Block current consumption at 100 kHz 50 µA
SID150 II2C2 Block current consumption at 400 kHz 135 µA
SID151 II2C3 Block current consumption at 1 Mbps 310 µA
SID152 II2C4 I2C enabled in Deep Sleep mode 1.4 µA
Table 17. Fixed I2C AC Specifications
(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID153 FI2C1 Bit rate 1 Mbps
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Family Datasheet
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LCD Direct Drive
SPI Specifications
Table 18. LCD Direct Drive DC Specifications
(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID154 ILCDLOW Operating current in low power mode 5 µA 16 × 4 small segment
disp. at 50 Hz
SID155 CLCDCAP LCD capacitance per segment/common
driver
500 5000 pF Guaranteed by Design
SID156 LCDOFFSET Long-term segment offset 20 mV
SID157 ILCDOP1 PWM Mode current. 5-V bias.
24-MHz IMO. 25 °C
0.6 mA 32 × 4 segments.
50 Hz
SID158 ILCDOP2 PWM Mode current. 3.3-V bias.
24-MHz IMO. 25 °C
0.5 mA 32 × 4 segments.
50 Hz
Table 19. LCD Direct Drive AC Specifications
(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID159 FLCD LCD frame rate 10 50 150 Hz
Table 20. Fixed UART DC Specifications
(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID160 IUART1 Block current consumption at
100 Kbits/sec
––55µA
SID161 IUART2 Block current consumption at
1000 Kbits/sec
– 312 µA
Table 21. Fixed UART AC Specifications
(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units
SID162 FUART Bit rate 1 Mbps
Table 22. Fixed SPI DC Specifications
(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units
SID163 ISPI1 Block current consumption at 1 Mbits/sec 360 µA
SID164 ISPI2 Block current consumption at 4 Mbits/sec 560 µA
SID165 ISPI3 Block current consumption at 8 Mbits/sec 600 µA
Table 23. Fixed SPI AC Specifications
(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units
SID166 FSPI SPI operating frequency (master; 6X
oversampling)
–– 8MHz
"Acvanss EHIEDnEnIAInNnRRnw a TROWWRWEI ] [3] [ l E[ 1 [3]
PSoC® 4: PSoC 4200
Family Datasheet
Document Number: 001-87197 Rev. *J Page 30 of 45
Memory
Table 24. Fixed SPI Master Mode AC Specifications
(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units
SID167 TDMO MOSI valid after Sclock driving edge 15 ns
SID168 TDSI MISO valid before Sclock capturing edge.
Full clock, late MISO Sampling used
20 ns
SID169 THMO Previous MOSI data hold time with respect
to capturing edge at Slave
0–– ns
Table 25. Fixed SPI Slave Mode AC Specifications
(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units
SID170 TDMI MOSI valid before Sclock capturing edge 40 ns
SID171 TDSO MISO valid after Sclock driving edge 42 + 3 ×
Tscbclk
ns
SID171A TDSO_ext MISO valid after Sclock driving edge in Ext.
Clock mode
– – 48 ns
SID172 THSO Previous MISO data hold time 0 ns
SID172A TSSELSCK SSEL Valid to first SCK Valid edge 100 ns
Table 26. Flash DC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID173 VPE Erase and program voltage 1.71 5.5 V
Note
3. It can take as much as 20 milliseconds to write to Flash. During this time the device should not be Reset, or Flash operations will be interrupted and cannot be relied
on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs.
Make certain that these are not inadvertently activated.
Table 27. Flash AC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID174 TROWWRITE[3] Row (block) write time (erase and
program)
20 ms Row (block) = 128 bytes
SID175 TROWERASE[3] Row erase time 13 ms
SID176 TROWPROGRAM[3] Row program time after erase 7 ms
SID178 TBULKERASE[3] Bulk erase time (32 KB) 35 ms
SID180 TDEVPROG[3] Total device program time 7 seconds Guaranteed by charac-
terization
SID181 FEND Flash endurance 100 K cycles Guaranteed by charac-
terization
SID182 FRET Flash retention. TA 55 °C, 100 K
P/E cycles
20 years Guaranteed by charac-
terization
SID182A Flash retention. TA 85 °C, 10 K
P/E cycles
10 – – years Guaranteed by charac-
terization
SID182B FRETQ Flash retention. TA 105 °C, 10 K
P/E cycles, three years at TA 
85 °C
10 20 years Guaranteed by charac-
terization
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Family Datasheet
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System Resources
Power-on-Reset (POR) with Brown Out
Voltage Monitors
Table 28. Imprecise Power On Reset (IPOR)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID185 VRISEIPOR Rising trip voltage 0.80 1.45 V Guaranteed by charac-
terization
SID186 VFALLIPOR Falling trip voltage 0.75 1.4 V Guaranteed by charac-
terization
SID187 VIPORHYST Hysteresis 15 200 mV Guaranteed by charac-
terization
Table 29. Precise Power On Reset (POR)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID190 VFALLPPOR BOD trip voltage in active and
sleep modes
1.64 V Full functionality
between 1.71 V and
BOD trip voltage is
guaranteed by charac-
terization
SID192 VFALLDPSLP BOD trip voltage in Deep Sleep 1.4 V Guaranteed by charac-
terization
BID55 Svdd Maximum power supply ramp
rate
–– 67kV/sec
Table 30. Voltage Monitors DC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID195 VLVI1 LVI_A/D_SEL[3:0] = 0000b 1.71 1.75 1.79 V
SID196 VLVI2 LVI_A/D_SEL[3:0] = 0001b 1.76 1.80 1.85 V
SID197 VLVI3 LVI_A/D_SEL[3:0] = 0010b 1.85 1.90 1.95 V
SID198 VLVI4 LVI_A/D_SEL[3:0] = 0011b 1.95 2.00 2.05 V
SID199 VLVI5 LVI_A/D_SEL[3:0] = 0100b 2.05 2.10 2.15 V
SID200 VLVI6 LVI_A/D_SEL[3:0] = 0101b 2.15 2.20 2.26 V
SID201 VLVI7 LVI_A/D_SEL[3:0] = 0110b 2.24 2.30 2.36 V
SID202 VLVI8 LVI_A/D_SEL[3:0] = 0111b 2.34 2.40 2.46 V
SID203 VLVI9 LVI_A/D_SEL[3:0] = 1000b 2.44 2.50 2.56 V
SID204 VLVI10 LVI_A/D_SEL[3:0] = 1001b 2.54 2.60 2.67 V
SID205 VLVI11 LVI_A/D_SEL[3:0] = 1010b 2.63 2.70 2.77 V
SID206 VLVI12 LVI_A/D_SEL[3:0] = 1011b 2.73 2.80 2.87 V
SID207 VLVI13 LVI_A/D_SEL[3:0] = 1100b 2.83 2.90 2.97 V
SID208 VLVI14 LVI_A/D_SEL[3:0] = 1101b 2.93 3.00 3.08 V
SID209 VLVI15 LVI_A/D_SEL[3:0] = 1110b 3.12 3.20 3.28 V
SID210 VLVI16 LVI_A/D_SEL[3:0] = 1111b 4.39 4.50 4.61 V
SID211 LVI_IDD Block current 100 µA Guaranteed by
characterization
Table 31. Voltage Monitors AC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID212 TMONTRIP Voltage monitor trip time 1 µs Guaranteed by
characterization
@chREss nnnnnnnnnnnnnnnnnn
PSoC® 4: PSoC 4200
Family Datasheet
Document Number: 001-87197 Rev. *J Page 32 of 45
SWD Interface
Internal Main Oscillator
Internal Low-Speed Oscillator
Table 32. SWD Interface Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID213 F_SWDCLK1 3.3 V VDD 5.5 V 14 MHz SWDCLK 1/3 CPU
clock frequency
SID214 F_SWDCLK2 1.71 V VDD 3.3 V 7 MHz SWDCLK 1/3 CPU
clock frequency
SID215 T_SWDI_SETUP T = 1/f SWDCLK 0.25*T ns Guaranteed by
characterization
SID216 T_SWDI_HOLD T = 1/f SWDCLK 0.25*T ns Guaranteed by
characterization
SID217 T_SWDO_VALID T = 1/f SWDCLK 0.5*T ns Guaranteed by
characterization
SID217A T_SWDO_HOLD T = 1/f SWDCLK 1 ns Guaranteed by
characterization
Table 33. IMO DC Specifications
(Guaranteed by Design)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID218 IIMO1 IMO operating current at 48 MHz 1000 µA
SID219 IIMO2 IMO operating current at 24 MHz 325 µA
SID220 IIMO3 IMO operating current at 12 MHz 225 µA
SID221 IIMO4 IMO operating current at 6 MHz 180 µA
SID222 IIMO5 IMO operating current at 3 MHz 150 µA
Table 34. IMO AC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID223 FIMOTOL1 Frequency variation from 3 to
48 MHz
––±2%±3% if T
A > 85 °C and
IMO frequency <
24 MHz
SID226 TSTARTIMO IMO startup time 12 µs
SID227 TJITRMSIMO1 RMS Jitter at 3 MHz 156 ps
SID228 TJITRMSIMO2 RMS Jitter at 24 MHz 145 ps
SID229 TJITRMSIMO3 RMS Jitter at 48 MHz 139 ps
Table 35. ILO DC Specifications
(Guaranteed by Design)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID231 IILO1 ILO operating current at 32 kHz 0.3 1.05 µA Guaranteed by
Characterization
SID233 IILOLEAK ILO leakage current 2 15 nA Guaranteed by
Design
@chREss nnnnnnnnnnnnnnnnnn
PSoC® 4: PSoC 4200
Family Datasheet
Document Number: 001-87197 Rev. *J Page 33 of 45
Table 36. ILO AC Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID234 TSTARTILO1 ILO startup time 2 ms Guaranteed by charac-
terization
SID236 TILODUTY ILO duty cycle 40 50 60 % Guaranteed by charac-
terization
SID237 FILOTRIM1 32 kHz trimmed frequency 15 32 50 kHz Max ILO frequency is
70 kHz if TA > 85 °C
Table 37. External Clock Specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID305 ExtClkFreq External Clock input Frequency 0 48 MHz Guaranteed by
characterization
SID306 ExtClkDuty Duty cycle; Measured at VDD/2 45 55 % Guaranteed by
characterization
Table 38. UDB AC Specifications
(Guaranteed by Characterization)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
Datapath performance
SID249 FMAX-TIMER Max frequency of 16-bit timer in a
UDB pair
––48MHz
SID250 FMAX-ADDER Max frequency of 16-bit adder in a
UDB pair
––48MHz
SID251 FMAX_CRC Max frequency of 16-bit CRC/PRS in
a UDB pair
––48MHz
PLD Performance in UDB
SID252 FMAX_PLD Max frequency of 2-pass PLD
function in a UDB pair
––48MHz
Clock to Output Performance
SID253 TCLK_OUT_UDB1 Prop. delay for clock in to data out at
25 °C, Typ.
–15 – ns
SID254 TCLK_OUT_UDB2 Prop. delay for clock in to data out,
Worst case.
–25 – ns
nnnnnnnnnnnnnnnnnn
PSoC® 4: PSoC 4200
Family Datasheet
Document Number: 001-87197 Rev. *J Page 34 of 45
Table 39. Block Specs
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID256* TWS48* Number of wait states at 48 MHz 1 CPU execution from
Flash. Guaranteed
by characterization
SID257 TWS24* Number of wait states at 24 MHz 0 CPU execution from
Flash. Guaranteed
by characterization
SID260 VREFSAR Trimmed internal reference to SAR –1 +1 % Percentage of Vbg
(1.024 V).
Guaranteed by
characterization
SID262 TCLKSWITCH Clock switching from clk1 to clk2 in
clk1 periods
3 4 Periods . Guaranteed by
design
* Tws48 and Tws24 are guaranteed by Design
Table 40. UDB Port Adaptor Specifications
(Based on LPC Component Specs, Guaranteed by Characterization -10-pF load, 3-V VDDIO and VDDD)
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID263 TLCLKDO LCLK to output delay 18 ns
SID264 TDINLCLK Input setup time to LCLCK rising
edge
–– 7ns
SID265 TDINLCLKHLD Input hold time from LCLK rising edge 5 ns
SID266 TLCLKHIZ LCLK to output tristated 28 ns
SID267 TFLCLK LCLK frequency 33 MHz
SID268 TLCLKDUTY LCLK duty cycle (percentage high) 40 60 %
@chREss
PSoC® 4: PSoC 4200
Family Datasheet
Document Number: 001-87197 Rev. *J Page 35 of 45
Ordering Information
The PSoC 4200 part numbers and features are listed in the following table.
Table 41. PSoC 4200 Family Ordering Information
Family
MPN
Features Package
Max CPU Speed (MHz)
Flash (KB)
SRAM (KB)
UDB
Op-amp (CTBm)
CapSense
Direct LCD Drive
12-bit SAR ADC
LP Comparators
TCPWM Blocks
SCB Blocks
GPIO
28-SSOP
35-WLCSP
40-QFN
44-TQFP
48-TQFP
4200
CY8C4244PVI-432 48 16 4 2 1 - - 1 Msps 2 4 2 24
CY8C4244PVI-442 48 16 4 2 1 √√ 1 Msps 2 4 2 24
CY8C4244PVQ-432 48 16 4 2 1 - - 1 Msps 2 4 2 24
CY8C4244PVQ-442 48 16 4 2 1 √√ 1 Msps 2 4 2 24
CY8C4244FNI-443 48 16 4 2 2 √√ 1 Msps 2 4 2 31
CY8C4244LQI-443 48 16 4 2 2 √√ 1 Msps 2 4 2 34
CY8C4244AXI-443 48 16 4 2 2 √√ 1 Msps 2 4 2 36
CY8C4244LQQ-443 48 16 4 2 2 √√ 1 Msps 2 4 2 34
CY8C4244AXQ-443 48 16 4 2 2 √√ 1 Msps 2 4 2 36
CY8C4244AZI-443 48 16 4 2 2 √√ 1 Msps 2 4 2 36
CY8C4245AXI-473 48 32 4 4 2 - - 1 Msps 2 4 2 36
CY8C4245AXQ-473 48 32 4 4 2 - - 1 Msps 2 4 2 36
CY8C4245AZI-473 48 32 4 4 2 - - 1 Msps 2 4 2 36
CY8C4245PVI-482 48 32 4 4 1 √√ 1 Msps 2 4 2 24
CY8C4245PVQ-482 48 32 4 4 1 √√ 1 Msps 2 4 2 24
CY8C4245FNI-483(T) 48 32 4 4 2 √√ 1 Msps 2 4 2 31
CY8C4245LQI-483 48 32 4 4 2 √√ 1 Msps 2 4 2 34
CY8C4245AXI-483 48 32 4 4 2 √√ 1 Msps 2 4 2 36
CY8C4245LQQ-483 48 32 4 4 2 √√ 1 Msps 2 4 2 34
CY8C4245AXQ-483 48 32 4 4 2 √√ 1 Msps 2 4 2 36
CY8C4245AZI-483 48 32 4 4 2 √√ 1 Msps 2 4 2 36
PSoC® 4: PSoC 4200
Family Datasheet
Document Number: 001-87197 Rev. *J Page 36 of 45
Part Numbering Conventions
PSoC 4 devices follow the part numbering convention described in the following table. All fields are single-character alphanumeric (0,
1, 2, …, 9, A,B, …, Z) unless stated otherwise.
The part numbers are of the form CY8C4ABCDEF-XYZ where the fields are defined as follows.
The Field Values are listed in the following table.
Architecture
Cypress Prefix
Family within Architecture
Speed Grade
Flash Capacity
Package Code
Temperature Range
Attributes Set
4: PSoC 4
4: 48MHz
5: 32KB
AX: TQFP
I: Industrial
Example CY8C 4 A EDCBFYX-Z
2: 4200 Family
Field Description Values Meaning
CY8C Cypress Prefix
4 Architecture 4 PSoC 4
AFamily within archi-
tecture
1 4100 Family
2 4200 Family
B CPU Speed 224 MHz
448 MHz
C Flash Capacity 416 KB
532 KB
DE Package Code
AX, AZ TQFP
LQ QFN
PV SSOP
FN WLCSP
F Temperature Range I Industrial
Q Extended Industrial
XYZ Attributes Code 000-999 Code of feature set in specific family
’\ z-
PSoC® 4: PSoC 4200
Family Datasheet
Document Number: 001-87197 Rev. *J Page 37 of 45
Packaging
PSoC 4 CAB Libraries with Schematics Symbols and PCB Footprints are on the Cypress web site at
http://www.cypress.com/cad-resources/psoc-4-cad-libraries?source=search&cat=technical_documents.
Table 42. Package Characteristics
Parameter Description Conditions Min Typ Max Units
TAOperating ambient temperature –40 25.00 105 °C
TJOperating junction temperature –40 125 °C
TJA Package JA (28-pin SSOP) 66.58 – °C/Watt
TJA Package JA (35-ball WLCSP) 28.00 °C/Watt
TJA Package JA (40-pin QFN) 15.34 °C/Watt
TJA Package JA (44-pin TQFP) 57.16 °C/Watt
TJA Package JA (48-pin TQFP) 67.30 °C/Watt
TJC Package JC (28-pin SSOP) 26.28 °C/Watt
TJC Package JC (35-ball WLCSP) 00.40 °C/Watt
TJC Package JC (40-pin QFN) 2.50 °C/Watt
TJC Package JC (44-pin TQFP) 17.47 °C/Watt
TJC Package JC (48-pin TQFP) 27.60 °C/Watt
Table 43. Solder Reflow Peak Temperature
Package Maximum Peak
Temperature Maximum Time at Peak Temperature
28-pin SSOP 260 °C 30 seconds
35-ball WLCSP 260 °C 30 seconds
40-pin QFN 260 °C 30 seconds
44-pin TQFP 260 °C 30 seconds
48-pin TQFP 260 °C 30 seconds
Table 44. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
Package MSL
28-pin SSOP MSL 3
35-ball WLCSP MSL 3
40-pin QFN MSL 3
44-pin TQFP MSL 3
48-pin TQFP MSL 3
CYPRESS ' mum m Iwukxow a 114' H4 BIA 1., 1 pm 1 m HHHHHHHHHHHHHH 1 m 75a (7 V m DIMENSIEINS 1N MILLIMETERS MIN‘ MAX 15 is 1mm Wu :mwn “NE ‘ M f , . a - ass m “5 1“ 0 MIN» ‘ ‘ GAUGE PLANE EDD I I @ MAX‘ 185 L Y Y E- m % nae m a T 125 m» , 4 m was TOP VIEW leE VIEW BOTTOM VIEW NOTE
PSoC® 4: PSoC 4200
Family Datasheet
Document Number: 001-87197 Rev. *J Page 38 of 45
Figure 17. 28-pin (210-mil) SSOP Package Outline
Figure 18. 35-ball WLCSP Package Outline
51-85079 *F
D
C
B
A
1234
1234
D
C
B
A
TOP VIEW BOTTOM VIEW
SIDE VIEW
NOTES:
1. REFERENCE JEDEC PUBLICATION 95, DESIGN GUIDE 4.18
2. ALL DIMENSIONS ARE IN MILLIMETERS
E
56 7 567
E
001-93741 **
CchREss msaaxa m IDNcRRow TOP VIEW aaa tum m m I O m \ am I am D 3 H) A H 2a Moms: 1. @ HATCH AREA Is SOLDERAELE EXPOSED PAD 2. REFERENCE JEDEC a Mo-zu a. PACKAGE WEIGHT: 6: :2 mg A. ALL DIMENSIONS ARE IN MILLIMETERS Iznuxnan :a mama su man as: NDTEI I JEDEC srn REF M54126 gamma PLANE \Ifi'fl‘ Isa m “m \ I ”was 3 DIMENSIDNS IN MILLIMETERS [SEE aEmLA E VIEW nus HAN wean MAX amaas BOTIOM VIEW a A I, a UUwaUUUUU 7303— I D C 050 3 Ci 9 3 C7 i 3 EE N TE I C E 3 5 ° c ‘ j C D C D C 1‘ In (I ’1 H H fl H H (I f: 2° N V II: II; 7 fang R wa HIN aaa MIN azu MINI Ian REF aEmL A a EDDY LENmH DIMENSIEIN DUES NUT INCLUDE MULD PRuTRusmN/END FLASH MDLD PRDTRUSIEIN/[ND FLASH SHALL NEIT EXCEED money In (n25 rm) PER SIDE EDDY LENmH DIMENSIEINS ARE MAX PLASTIC EDDY SIZE INCLUDING MEILD MISMATCH
PSoC® 4: PSoC 4200
Family Datasheet
Document Number: 001-87197 Rev. *J Page 39 of 45
Figure 19. 40-pin QFN Package Outline
The center pad on the QFN package should be connected to ground (VSS) for best mechanical, thermal, and electrical performance.
If not connected to ground, it should be electrically floating and not connected to any other signal.
Figure 20. 44-pin TQFP Package Outline
001-80659 *A
51-85064 *G
CYPRESS ' mum m Iwukmw :EE DETAILA s‘ootues 3n 7 Hutu m :n o‘auxn‘ns as (man TVP 1?:1‘ STANDAZIFF u‘us MIN u 15 MAX DIMENXIDNX ARE IN MILLIMETERX Y R‘ we MN on MIN‘ LDEI REF‘ DETAILA R ans MIN nee MAX‘ GAUGE PLANE air 7 usutn 15
PSoC® 4: PSoC 4200
Family Datasheet
Document Number: 001-87197 Rev. *J Page 40 of 45
Figure 21. 48-Pin TQFP Package Outline
51-85135 *C
@chREss nnnnnnnnnnnnnnnnnn
PSoC® 4: PSoC 4200
Family Datasheet
Document Number: 001-87197 Rev. *J Page 41 of 45
Acronyms
Table 45. Acronyms Used in this Document
Acronym Description
abus analog local bus
ADC analog-to-digital converter
AG analog global
AHB AMBA (advanced microcontroller bus archi-
tecture) high-performance bus, an ARM data
transfer bus
ALU arithmetic logic unit
AMUXBUS analog multiplexer bus
API application programming interface
APSR application program status register
ARM®advanced RISC machine, a CPU architecture
ATM automatic thump mode
BW bandwidth
CAN Controller Area Network, a communications
protocol
CMRR common-mode rejection ratio
CPU central processing unit
CRC cyclic redundancy check, an error-checking
protocol
DAC digital-to-analog converter, see also IDAC, VDAC
DFB digital filter block
DIO digital input/output, GPIO with only digital
capabilities, no analog. See GPIO.
DMIPS Dhrystone million instructions per second
DMA direct memory access, see also TD
DNL differential nonlinearity, see also INL
DNU do not use
DR port write data registers
DSI digital system interconnect
DWT data watchpoint and trace
ECC error correcting code
ECO external crystal oscillator
EEPROM electrically erasable programmable read-only
memory
EMI electromagnetic interference
EMIF external memory interface
EOC end of conversion
EOF end of frame
EPSR execution program status register
ESD electrostatic discharge
ETM embedded trace macrocell
FIR finite impulse response, see also IIR
FPB flash patch and breakpoint
FS full-speed
GPIO general-purpose input/output, applies to a PSoC
pin
HVI high-voltage interrupt, see also LVI, LVD
IC integrated circuit
IDAC current DAC, see also DAC, VDAC
IDE integrated development environment
I2C, or IIC Inter-Integrated Circuit, a communications
protocol
IIR infinite impulse response, see also FIR
ILO internal low-speed oscillator, see also IMO
IMO internal main oscillator, see also ILO
INL integral nonlinearity, see also DNL
I/O input/output, see also GPIO, DIO, SIO, USBIO
IPOR initial power-on reset
IPSR interrupt program status register
IRQ interrupt request
ITM instrumentation trace macrocell
LCD liquid crystal display
LIN Local Interconnect Network, a communications
protocol.
LR link register
LUT lookup table
LVD low-voltage detect, see also LVI
LVI low-voltage interrupt, see also HVI
LVTTL low-voltage transistor-transistor logic
MAC multiply-accumulate
MCU microcontroller unit
MISO master-in slave-out
NC no connect
NMI nonmaskable interrupt
NRZ non-return-to-zero
NVIC nested vectored interrupt controller
NVL nonvolatile latch, see also WOL
opamp operational amplifier
PAL programmable array logic, see also PLD
Table 45. Acronyms Used in this Document (continued)
Acronym Description
nnnnnnnnnnnnnnnnnn @chREss
PSoC® 4: PSoC 4200
Family Datasheet
Document Number: 001-87197 Rev. *J Page 42 of 45
PC program counter
PCB printed circuit board
PGA programmable gain amplifier
PHUB peripheral hub
PHY physical layer
PICU port interrupt control unit
PLA programmable logic array
PLD programmable logic device, see also PAL
PLL phase-locked loop
PMDD package material declaration data sheet
POR power-on reset
PRES precise power-on reset
PRS pseudo random sequence
PS port read data register
PSoC®Programmable System-on-Chip™
PSRR power supply rejection ratio
PWM pulse-width modulator
RAM random-access memory
RISC reduced-instruction-set computing
RMS root-mean-square
RTC real-time clock
RTL register transfer language
RTR remote transmission request
RX receive
SAR successive approximation register
SC/CT switched capacitor/continuous time
SCL I2C serial clock
SDA I2C serial data
S/H sample and hold
SINAD signal to noise and distortion ratio
SIO special input/output, GPIO with advanced
features. See GPIO.
SOC start of conversion
SOF start of frame
SPI Serial Peripheral Interface, a communications
protocol
SR slew rate
SRAM static random access memory
SRES software reset
SWD serial wire debug, a test protocol
Table 45. Acronyms Used in this Document (continued)
Acronym Description
SWV single-wire viewer
TD transaction descriptor, see also DMA
THD total harmonic distortion
TIA transimpedance amplifier
TRM technical reference manual
TTL transistor-transistor logic
TX transmit
UART Universal Asynchronous Transmitter Receiver, a
communications protocol
UDB universal digital block
USB Universal Serial Bus
USBIO USB input/output, PSoC pins used to connect to
a USB port
VDAC voltage DAC, see also DAC, IDAC
WDT watchdog timer
WOL write once latch, see also NVL
WRES watchdog timer reset
XRES external reset I/O pin
XTAL crystal
Table 45. Acronyms Used in this Document (continued)
Acronym Description
@chREss nnnnnnnnnnnnnnnnnn
PSoC® 4: PSoC 4200
Family Datasheet
Document Number: 001-87197 Rev. *J Page 43 of 45
Document Conventions
Units of Measure
Table 46. Units of Measure
Symbol Unit of Measure
°C degrees Celsius
dB decibel
fF femto farad
Hz hertz
KB 1024 bytes
kbps kilobits per second
Khr kilohour
kHz kilohertz
kkilo ohm
ksps kilosamples per second
LSB least significant bit
Mbps megabits per second
MHz megahertz
Mmega-ohm
Msps megasamples per second
µA microampere
µF microfarad
µH microhenry
µs microsecond
µV microvolt
µW microwatt
mA milliampere
ms millisecond
mV millivolt
nA nanoampere
ns nanosecond
nV nanovolt
ohm
pF picofarad
ppm parts per million
ps picosecond
s second
sps samples per second
sqrtHz square root of hertz
Vvolt
P500”
PSoC® 4: PSoC 4200
Family Datasheet
Document Number: 001-87197 Rev. *J Page 44 of 45
Revision History
Description Title: PSoC® 4: PSoC 4200 Family Datasheet Programmable System-on-Chip (PSoC®)
Document Number: 001-87197
Revision ECN Orig. of
Change Submission
Date Description of Change
*B 4108562 WKA 08/29/2013 Added clarifying note about the XRES pin in the Reset section.
Updated UDB Array diagram.
Added a link reference to the PSoC 4 TRM.
Updated the footnote in Absolute Maximum Ratings.
Updated Sleep Mode IDD specs in DC Specifications.
Updated Comparator DC Specifications
Updated SAR ADC AC Specifications
Updated LCD Direct Drive DC Specifications
Updated the number of GPIOs in Ordering Information.
*C 4568937 MKEA/
WKA
11/19/2014 Added More Information and PSoC Creator sections.
Added 48-pin TQFP pin and package details.
Added SID308A spec details.
Updated Ordering Information.
*D 4617283 WKA 01/08/2015 Corrected typo in the ordering information table.
Updated 28-pin SSOP package diagram.
*E 4643655 WKA 04/29/2015 Added 35 WLCSP pinout and package detail information.
Updated CSD specifications.
*F 5287114 WKA 06/09/2016 Added reference to AN90071 in the More Information section.
Updated Flash section with details of flash protection modes.
Added notes in the Pinouts section.
Updated 40-pin QFN and 28-pin SSOP pin diagrams.
Added PSoC 4 Power Supply diagram.
Updated the Bypass Capacitors column in the Power Supply table.
Updated values for SID32, SID34, SID38, SID269, SID270, SID271.
Added SID299A.
Updated Comparator Specifications.
Updated TCPWM Specifications.
Updated values for SID149, SID160, SID171.
Updated Conditions for SID190.
Added BID55.
Removed Conditions for SID237.
Added reference to PSoC 4 CAB Libraries with Schematics Symbols and PCB
Footprints in the Packaging section.
*G 5327384 WKA 06/28/2016 Removed capacitor connection for Pin 15 in Figure 13.
*H 5702140 GNKK 04/19/2017 Updated the Cypress logo and copyright information.
*I 5738586 WKA 05/16/2017 Updated max value of SID61.
*J 5795966 WKA 07/10/2017 Changed Pin 33 name in 40-pin QFN Pinout from VDDD to VDDA to correct
typo; pinout table is correct and not changed.
Removed reference to swd_io[1] and swd_clk[1].
Corrected 44-TQFP Package Example.
@cvpngss
Document Number: 001-87197 Rev. *J Revised July 10, 2017 Page 45 of 45
PSoC® 4: PSoC 4200
Family Datasheet
© Cypress Semiconductor Corporation 2013-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes to this document without further notice. Cypress does not
assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or
programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application
made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of
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