ADAU7002 Datasheet by Analog Devices Inc.

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ANALOG DEVICES T T
Stereo PDM-to-I2S or
TDM Conversion IC
Data Sheet ADAU7002
Rev. B Document Feedbac
k
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2013–2016 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
64× decimation of a stereo pulse density modulation (PDM)
bit stream to pulse code modulation (PCM) audio data
Slave I2S or time division multiplexed (TDM) output interface
Configurable TDM slots
I/O supply operation: 1.62 V to 3.6 V
64× output sample rate PDM clock
64×/128×/192×/256×/384×/512× output sample rate BCLK
Automatic BCLK ratio detection
Output sample rate: 4 kHz to 96 kHz
Automatic PDM CLK drive at 64× the sample rate
Automatic power down with BCLK removal
0.67 mA operating current at 48 kHz and 1.8 V IOVDD supply
Shutdown current: <1 μA
8-ball, 1.56 mm × 0.76 mm, 0.4 mm pitch WLCSP
Power-on reset
APPLICATIONS
Mobile computing
Portable electronics
Consumer electronics
GENERAL DESCRIPTION
The ADAU7002 converts a stereo PDM bit stream into a PCM
output. The source for the PDM data can be two microphones
or other PDM sources. The PCM audio data is output on a
serial audio interface port in either I2S or TDM format.
The ADAU7002 is specified over the commercial temperature
range (−40°C to +85°C). It is available in a halide-free, 8-ball,
1.56 mm × 0.76 mm, wafer level chip scale package (WLCSP).
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
PDM_CLK
CONFIG GND
1.62
V
TO 3.6V
IOVDD
PDM_DAT
BCLK
LRCLK
SDATA
PDM
INPUT
PORT
DIGITAL
DECIMATION
FILTERING
ADAU7002
11265-001
I
2
S
OUTPUT
PORT
ADAU7002 Data Sheet
Rev. B | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution .................................................................................. 4
Pin Configuration and Function Descriptions ..............................5
Typical Performance Characteristics ..............................................6
Typical Application Circuit ..............................................................8
Applications Information .................................................................9
Overview ........................................................................................9
Clocking ..........................................................................................9
Serial Audio Output Interface .....................................................9
Outline Dimensions ....................................................................... 13
Ordering Guide .......................................................................... 13
REVISION HISTORY
11/2016—Rev. A to Rev. B
Change to Serial Port Timing Section and Time From BCLK
Falling Parameter; Table 7 ............................................................. 10
Changes to Figure 19 Caption and Figure 21 Caption .............. 12
7/2013—Rev. 0 to Rev. A
Changes to Supply Current Test Conditions/Comments ............ 3
Changes to Figure 5 .......................................................................... 6
Added Figure 6; Renumbered Sequentially ................................... 6
Changes to Figure 14 and Figure 15 ............................................ 10
Changes to Figure 16, Figure 17, and Figure 18 ......................... 11
Changes to Figure 19, Figure 20, and Figure 21 ......................... 12
1/2013—Revision 0: Initial Version
Table L
Data Sheet ADAU7002
Rev. B | Page 3 of 16
SPECIFICATIONS
IOVDD = 1.8 V, TA = 25°C, BCLK = 3.072 MHz, output = 48 kHz, I2S format, unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
DIGITAL INPUT/OUTPUT
High Level Input Voltage (VIH) 0.7 × IOVDD V
Low Level Input Voltage (VIL) 0.3 × IOVDD V
Input Leakage, High (IIH) BCLK and LRCLK pins 1 µA
Input Leakage, Low (IIL) BCLK and LRCLK pins 1 µA
Input Capacitance 5 pF
SDATA
4.5
mA
PDM_CLK 9 mA
PERFORMANCE
Dynamic Range 20 Hz to 20 kHz, 60 dB input
With A-Weighted Filter (RMS) 110 dB
Signal-to-Noise-Ratio A-weighted, fourth-order input 110 dB
Decimation Ratio 64×
Frequency Response DC to 0.45 output fS 0.1 +0.01 dB
Stop Band 0.566 fS
Stop-Band Attenuation 60 dB
Group Delay 0.02 fS input signal 3.31 LRCLK cycles
Gain PDM to PCM 0 dB
Start-Up Time 48 LRCLK cycles
Bit Width Internal and output 20 Bits
Interchannel Phase
0
Degrees
CLOCKING
Output Sampling Rate fS LRCLK pulse rate 4 48 96 kHz
BCLK Frequency
BCLK
0.256
3.072
24.576
MHz
POWER SUPPLIES
Supply Voltage Range IOVDD 1.62 3.6 V
Supply Current IOVDD = 1.8 V 0.67 mA
IOVDD = 3.3 V 1.33 mA
IOVDD = 1.8 V, 16 kHz output 0.21 mA
IOVDD = 3.3 V, 16 kHz output 0.41 mA
Shutdown Current IOVDDSD, no input clocks 1 µA
ESD CAUTION ESD (e‘ecucstatic discharge) sensitive devize. . Chavged mm and mm" board; (an mscmge wuhoux daemon mmougn ms pvaducx feamves gamed m pmpnemy pmemun (wiumy, damage ‘2l\ may mum on dewcex xubjecled m high enevgy SD. hevefove. propev \SD precauhons shoud be mm m mm performante degradauon or on of mnmona Ky
ADAU7002 Data Sheet
Rev. B | Page 4 of 16
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings apply at 25°C, unless otherwise noted.
Table 2.
Parameter Rating
IOVDD Supply Voltage 3.6 V
Input Voltage 3.6 V
ESD Susceptibility 4 kV
Storage Temperature Range 65°C to +150°C
Operating Temperature Range −40°C to +85°C
Junction Temperature Range −65°C to +165°C
Lead Temperature (Soldering, 60 sec)
300°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA (junction to air) is specified for the worst-case conditions,
that is, a device soldered in a circuit board for surface-mount
packages. θJA is determined according to JESD51-9 on a 4-layer
printed circuit board (PCB) with natural convection cooling.
Table 3. Thermal Resistance
Package Type θJA Unit
8-ball, 1.56 mm × 0.76 mm WLCSP
90
°C/W
ESD CAUTION
Data Sheet ADAU7002
Rev. B | Page 5 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 2. Pin Configuration (Top Side View)
Table 4. Pin Function Descriptions
Pin No. Mnemonic Type Description
A1 PDM_DAT Input PDM Data Input
A2 PDM_CLK Output PDM Clock Output
B1 SDATA Output Serial Data Output for I2S/TDM
B2 BCLK Input Bit Clock for I2S/TDM
C1 GND Ground Ground
C2 LRCLK Input Left/Right Clock for I2S/Frame Sync for TDM
D1 IOVDD Supply Input/Output and Digital Supply
D2 CONFIG Input Configuration Pin
TOP VIEW
(BALL SIDE DOWN)
11265-002
BALL
A
1
CORNER
A
PDM_
DAT PDM_
CLK
SDATA BCLK
GND LRCLK
IOVDD CONFIG
21
B
C
D
1m: 72 >3“; éomu GEEHEJ 5:1: .5; 0,1 Emgdi. REEVES; z . E: and)“. xdxgfidn 520
ADAU7002 Data Sheet
Rev. B | Page 6 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 3. FFT, fS = 48 kHz, −60 dBFS Input
Figure 4. Frequency Response
Figure 5. Group Delay vs. Normalized Frequency (Relative to fS)
Figure 6. Group Delay vs. Frequency, fS = 48 kHz
Figure 7. Total Harmonic Distortion + Noise (THD + N) vs.
Normalized Frequency (Relative to fS)
Figure 8. THD + N Level vs. Generator Level
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
–180
–190
LEVEL (dBFS)
FREQUENCY (Hz)
20 100 1k 10k 20k
CH1
CH2
11265-003
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.0001 0.001 0.01 0.1 1
LEVEL (dBFS)
11265-004
NORMALIZED FREQUENCY (RELATIVE TO
f
S
) (Hz)
0
1
2
3
4
6
5
7
8
GROUP DELAY (LRCLK CYCLES)
11265-100
NORMALIZED FREQUENCY (RELATIVE TO
f
S
) (Hz)
0.0001 0.001 0.01 0.1 1
0
20
40
60
80
120
100
140
160
GROUP DELAY (µs)
11265-101
FREQUENCY (Hz)
10 100 1k 10k 100k
0.0001 0.001 0.01 0.1 1
–140
–120
–100
–80
–60
–20
–40
0
THD + N (dBFS)
11265-006
NORMALIZED FREQUENCY (RELATIVE TO
f
S
) (Hz)
–120
–100
–80
–60
–40
–20
0
–120 –100 –80 –60 –40 –20 0
THD + N LEVEL (dBFS)
GENERATOR LEVEL (dBFS)
11265-007
uuuuuuuuuuuu
Data Sheet ADAU7002
Rev. B | Page 7 of 16
Figure 9. Supply Current vs. Supply Voltage
Figure 10. Out-of-Band Frequency Response (48 kHz Output)
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4
SUPPLY CURRENT (mA)
SUPPLY VOLTAGE (V)
11265-009
0
–20
–40
–60
–80
–100
–120
–140
–160
MAGNITUDE (dB)
FREQUENCY (MHz)
00.5 1.0 1.5
11265-010
WH IOVDD ovn GND
ADAU7002 Data Sheet
Rev. B | Page 8 of 16
TYPICAL APPLICATION CIRCUIT
Figure 11. Typical Application Circuit
PDM_CLK
CONFIG
GND
IOVDD
0.1µF
IOVDD
PDM_DAT
PDM_CLK
CONFIG
PDM_DAT
LRCLK
SDATA
BCLK
ADAU7002
LRCLK
SDATA
OPTIONAL
PULL-DOWN
RESISTOR
BCLK
11265-011
”wig H‘
Data Sheet ADAU7002
Rev. B | Page 9 of 16
APPLICATIONS INFORMATION
OVERVIEW
The ADAU7002 provides stereo decimation from a 1-bit PDM
source to a 20-bit PCM audio. The downsampling ratio is fixed
at 64×. The 20-bit downsampled PCM audio is output via
standard I2S or TDM formats.
The input source for the ADAU7002 can be any device that has
a PDM output, such as a digital microphone. The output pins of
these microphones can connect directly to the input pins of the
ADAU7002.
CLOCKING
The ADAU7002 requires a BCLK rate that is a minimum of 64×
the LRCLK sample rate. BCLK rates of 128×, 192×, 256×, 384×,
and 512× the LRCLK rate are also supported. The ADAU7002
automatically detects the ratio between BCLK and LRCLK and
generates a PDM clock output at 64× the LRCLK rate. The
minimum sample rate is 4 kHz, and the maximum is 96 kHz,
which correspond to a PDM clock range of 256 kHz to 6.144 MHz.
Internally, all processing is done at the PDM_CLK rate.
When BCLK is removed, the ADAU7002 powers down
automatically. When BCLK is not present, the PDM_CLK
output stops.
Table 5. PDM Timing Parameters
Parameter tMIN t
MAX Unit
Data Setup Time, tSETUP 10 ns
Data Hold Time, tHOLD 7 ns
PDM data is latched on both edges of the clock.
Figure 12. PDM Timing Diagram
SERIAL AUDIO OUTPUT INTERFACE
The ADAU7002 supports I2S and TDM serial output formats.
Format selection and TDM slot placement is set with the CONFIG
pin. The SDATA pin is in tristate mode, except when the port is
driving serial data based on the CONFIG pin configuration.
Table 6. TDM Slot Selection
Device Setting CONFIG Pin Configuration
I2S Format Tie to IOVDD
TDM Slot 1 to Slot 2 Used/Driven, 32-Bit Slots Tie to GND
TDM Slot 3 to Slot 4 Used/Driven, 32-Bit Slots Open
TDM Slot 5 to Slot 6 Used/Driven, 32-Bit Slots Tie to IOVDD through a 47 kΩ resistor
TDM Slot 7 to Slot 8 Used/Driven, 32-Bit Slots Tie to GND through a 47 kΩ resistor
RL
t
HOLD
t
SETUP
PDM_CLK
PDM_DAT RL
11265-012
ADAU7002 Data Sheet
Rev. B | Page 10 of 16
Serial Port Timing
Figure 13. Serial Port Timing Diagram
IOVDD = 1.62 V to 3.63 V, load capacitance = 25 pF, unless otherwise noted.
Table 7. I2S/TDM Timing Parameters
Parameter Symbol tMIN tMAX Unit
BCLK Pulse Width High tBIH 10 ns
BCLK Pulse Width Low tBIL 10 ns
LRCLK Setup Time tLIS 10 ns
LRCLK Hold Time
t
LIH
10
ns
Time from BCLK Falling tSODM 18 ns
Figure 14. I2S, CONFIG Pin Tied to IOVDD
Figure 15. TDM8 Channel 1 and Channel 2, CONFIG Pin Tied to GND
11265-013
BCLK
LRCLK
SDATA
TDM MODE
SDATA
I2S JUSTIFIED
MODE
t
BIH
MSB
MSB
MSB – 1
t
BIL
t
LIS
t
LIH
t
SODM
t
SODM
LRCLK
BCLK
SDATA I
2
S LEFT CHANNEL
20
BCLKs
I
2
S RIGHT CHANNEL
TRISTATE TRISTATE
11265-014
SLOT 1
LRCLK
BCLK
SDATA
20
BCLKs
RIGHTLEFT
SLOT 2
SLOT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7 SLOT 8
TRISTATE TRISTATE TRISTATE TRISTATE TRISTATE TRISTATE
11265-015
Data Sheet ADAU7002
Rev. B | Page 11 of 16
Figure 16. TDM8 Channel 3 and Channel 4, CONFIG Pin Open
Figure 17. TDM8 Channel 5 to Channel 6, CONFIG Pin Tied to IOVDD Through a 47 kΩ Resistor
Figure 18. TDM8 Channel 7 and Channel 8, CONFIG Pin Tied to GND Through a 47 kΩ Resistor
SLOT 1
LRCLK
BCLK
SDATA
20
BCLKs
RIGHT
SLOT 2
SLOT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7 SLOT 8
TRISTATE TRISTATE TRISTATE TRISTATE TRISTATE TRISTATE
LEFT
11265-016
SLOT 1
LRCLK
BCLK
SDATA
20
BCLKs
RIGHT
SLOT 2
SLOT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7 SLOT 8
TRISTATE TRISTATE TRISTATE TRISTATE
LEFT
TRISTATE TRISTATE
11265-017
SLOT 1
LRCLK
BCLK
SDATA
20
BCLKs
RIGHT
SLOT 2
SLOT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7 SLOT 8
TRISTATE TRISTATE TRISTATE TRISTATE LEFT
TRISTATE TRISTATE
11265-018
ADAU7002 Data Sheet
Rev. B | Page 12 of 16
Figure 19. TDM4 Channel 1 and Channel 2, CONFIG Pin Tied to GND
Figure 20. TDM4 Channel 3 and Channel 4, CONFIG Pin Open
Figure 21. TDM2 Channel 1 and Channel 2, CONFIG Pin Tied to GND
SLOT 1
LRCLK
BCLK
SDATA
20
BCLKs
RIGHT
LEFT
SLOT 2
SLOT 3 SLOT 4
TRISTATE TRISTATE
11265-019
SLOT 1
LRCLK
BCLK
SDATA
20
BCLKs
RIGHTLEFT
SLOT 2
SLOT 3 SLOT 4
TRISTATE TRISTATE
11265-020
SLOT 1
LRCLK
BCLK
SDATA
20
BCLKs
RIGHTLEFT
SLOT 2
11265-021
Data Sheet ADAU7002
Rev. B | Page 13 of 16
OUTLINE DIMENSIONS
10-18-2016-A
A
B
C
D
0.560
0.500
0.440
0.230
0.200
0.170
0.330
0.300
0.270
0.800
0.760
0.720
1.600
1.560
1.520
12
BOTTOM VIEW
(BALL SIDE UP)
TOP VIEW
(BALL SIDE DOWN)
SIDE VIEW
0.300
0.260
0.220
1.20
REF
0.40
BSC
0.40 BSC
BALL A1
IDENTIFIER
ORIENTATION
IDENTIFIER
SEATING
PLANE
COPLANARITY
0.05
Figure 22. 8-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-8-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description
Package
Option Branding
ADAU7002ACBZ-R7 −40°C to +85°C 8-Ball Wafer Level Chip Scale Package [WLCSP], 7” Tape and Reel CB-8-6 BE
ADAU7002ACBZ-RL −40°C to +85°C 8-Ball Wafer Level Chip Scale Package [WLCSP], 13” Tape and Reel CB-8-6 BE
EVAL-ADAU7002Z Evaluation Board
1 Z = RoHS Compliant Part.
ADAU7002 Data Sheet
Rev. B | Page 14 of 16
NOTES
Data Sheet ADAU7002
Rev. B | Page 15 of 16
NOTES
SEGIéOEg www.ana|ng.cum
ADAU7002 Data Sheet
Rev. B | Page 16 of 16
NOTES
©2013–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11265-0-11/16(B)

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