dsPIC(33,24)EPzzz(GP,MC)20x,50x Errata Datasheet by Microchip Technology

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2011-2019 Microchip Technology Inc. DS80000533P-page 1
dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X
and PIC24EPXXXGP/MC20X
The dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X
and PIC24EPXXXGP/MC20X
family devices that you
have received conform functionally to the current Device
Data Sheet (DS70000657H), except for the anomalies
described in this document.
The silicon issues discussed in the following pages are
for silicon revisions with the Device and Revision IDs
listed in Table 1. The silicon issues are summarized in
Table 2.
The errata described in this document will be
addressed in future revisions of dsPIC33EPXXXGP50X,
dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
silicon.
Data Sheet clarifications and corrections start on
Page 27, following the discussion of silicon issues.
The silicon revision level can be identified using the
current version of MPLAB® IDE and Microchip’s
programmers, debuggers and emulation tools, which
are available at the Microchip corporate website
(www.microchip.com).
For example, to identify the silicon revision level using
MPLAB IDE in conjunction with MPLAB ICD 3 or
PICkit™ 3:
1. Using the appropriate interface, connect the device
to the MPLAB ICD 3 programmer/debugger or
PICkit 3.
2. From the main menu in MPLAB IDE, select
Configure>Select Device, and then select the
target part number in the dialog box.
3. Select the MPLAB hardware tool
(Debugger>Select Tool).
4. Perform a “Connect” operation to the device
(Debugger>Connect). Depending on the devel-
opment tool used, the part number and Device
Revision ID value appear in the Output window.
The Device and Revision ID values for the various
silicon revisions are shown in Table 1.
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. The current
silicon revision levels are:
dsPIC33/PIC24EP32: A3, A8
dsPIC33/PIC24EP64: A2, A3, A8
dsPIC33/PIC24EP128: A3, A8
dsPIC33/PIC24EP256: A3, A8, A9
dsPIC33/PIC24EP512: A7
“N/A” indicates that the device family is
not released, or that the particular silicon
issue does not apply to this family.
Note: If you are unable to extract the silicon
revision level, please contact your local
Microchip sales office for assistance.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and
PIC24EPXXXGP/MC20X Family Silicon Errata and Data Sheet Clarification
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
DS80000533P-page 2 2011-2019 Microchip Technology Inc.
TABLE 1: SILICON DEVREV VALUES
Part Number Device ID(1)Silicon Revision/Device ID(2)
PIC24EP32GP202 0x1C19
A3
0x4003
A8
0x4008
PIC24EP32GP203 0x1C1A
PIC24EP32GP204 0x1C18
dsPIC33EP32GP502 0x1C0D
dsPIC33EP32GP503 0x1C0E
dsPIC33EP32GP504 0x1C0C
PIC24EP32MC202 0x1C11
PIC24EP32MC203 0x1C12
PIC24EP32MC204 0x1C10
dsPIC33EP32MC202 0x1C01
dsPIC33EP32MC203 0x1C02
dsPIC33EP32MC204 0x1C00
dsPIC33EP32MC502 0x1C05
dsPIC33EP32MC503 0x1C06
dsPIC33EP32MC504 0x1C04
dsPIC33EP32MC506 0x1D27
PIC24EP64GP202 0x1D39
A2
0x4002
A3
0x4003
A8
0x4008
PIC24EP64GP203 0x1D3A
PIC24EP64GP204 0x1D38
PIC24EP64GP206 0x1D3B
dsPIC33EP64GP502 0x1D2D
dsPIC33EP64GP503 0x1D2E
dsPIC33EP64GP504 0x1D2C
dsPIC33EP64GP506 0x1D2F
PIC24EP64MC202 0x1D31
PIC24EP64MC203 0x1D32
PIC24EP64MC204 0x1D30
PIC24EP64MC206 0x1D33
dsPIC33EP64MC202 0x1D21
dsPIC33EP64MC203 0x1D22
dsPIC33EP64MC204 0x1D20
dsPIC33EP64MC206 0x1D23
dsPIC33EP64MC502 0x1D25
dsPIC33EP64MC503 0x1D26
dsPIC33EP64MC504 0x1D24
dsPIC33EP64MC506 0x1D27
Note 1: The Device and Revision IDs (DEVID and DEVREV) are located at the last two implemented addresses in
program memory.
2: Refer to the “dsPIC33E/PIC24E Flash Programming Specification for Devices with Volatile Configuration
Bits” (DS70663) for detailed information on Device and Revision IDs for your specific device.
2011-2019 Microchip Technology Inc. DS80000533P-page 3
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
PIC24EP128GP202 0x1E59
A3
0x4003
A8
0x4008
PIC24EP128GP204 0x1E58
PIC24EP128GP206 0x1E5B
dsPIC33EP128GP502 0x1E4D
dsPIC33EP128GP504 0x1E4C
dsPIC33EP128GP506 0x1E4F
PIC24EP128MC202 0x1E51
PIC24EP128MC204 0x1E50
PIC24EP128MC206 0x1E53
dsPIC33EP128MC202 0x1E41
dsPIC33EP128MC204 0x1E40
dsPIC33EP128MC206 0x1E43
dsPIC33EP128MC502 0x1E45
dsPIC33EP128MC504 0x1E44
dsPIC33EP128MC506 0x1E47
PIC24EP256GP202 0x1F79
A3
0x4003
A8
0x4008
A9
0x4009
PIC24EP256GP204 0x1F78
PIC24EP256GP206 0x1F7B
dsPIC33EP256GP502 0x1F6D
dsPIC33EP256GP504 0x1F6C
dsPIC33EP256GP506 0x1F6F
PIC24EP256MC202 0x1F71
PIC24EP256MC204 0x1F70
PIC24EP256MC206 0x1F73
dsPIC33EP256MC202 0x1F61
dsPIC33EP256MC204 0x1F60
dsPIC33EP256MC206 0x1F63
dsPIC33EP256MC502 0x1F65
dsPIC33EP256MC504 0x1F64
dsPIC33EP256MC506 0x1F67
TABLE 1: SILICON DEVREV VALUES (CONTINUED)
Part Number Device ID(1)Silicon Revision/Device ID(2)
Note 1: The Device and Revision IDs (DEVID and DEVREV) are located at the last two implemented addresses in
program memory.
2: Refer to the “dsPIC33E/PIC24E Flash Programming Specification for Devices with Volatile Configuration
Bits” (DS70663) for detailed information on Device and Revision IDs for your specific device.
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
DS80000533P-page 4 2011-2019 Microchip Technology Inc.
PIC24EP512GP202 0x1799
A7
0x4007 — —
PIC24EP512GP204 0x1798
PIC24EP512GP206 0x179B
dsPIC33EP512GP502 0x178D
dsPIC33EP512GP504 0x178C
dsPIC33EP512GP506 0x178F
PIC24EP512MC202 0x1791
PIC24EP512MC204 0x1790
PIC24EP512MC206 0x1793
dsPIC33EP512MC202 0x1781
dsPIC33EP512MC204 0x1780
dsPIC33EP512MC206 0x1783
dsPIC33EP512MC502 0x1785
dsPIC33EP512MC504 0x1784
dsPIC33EP512MC506 0x1787
TABLE 1: SILICON DEVREV VALUES (CONTINUED)
Part Number Device ID(1)Silicon Revision/Device ID(2)
Note 1: The Device and Revision IDs (DEVID and DEVREV) are located at the last two implemented addresses in
program memory.
2: Refer to the “dsPIC33E/PIC24E Flash Programming Specification for Devices with Volatile Configuration
Bits” (DS70663) for detailed information on Device and Revision IDs for your specific device.
2011-2019 Microchip Technology Inc. DS80000533P-page 5
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
TABLE 2: SILICON ISSUE SUMMARY
Module Feature Item
Number Issue Summary
CPU div.sd 1. When using the div.sd instruction, the Overflow bit is not getting
set when an overflow occurs.
CPU DO Loop 2. PSV access, including Table Reads or Writes in the first or last
instruction of a DO loop, is not allowed.
SPI Frame Sync Pulse 3. Frame Sync pulse is not generated in Master mode when
FRMPOL = 0.
SPI Frame Sync Pulse 4. When in SPI Slave mode, with the Frame Sync pulse set as an
input, FRMDLY must be set to ‘0’.
UART TX Interrupt 5. A Transmit (TX) interrupt may occur before the data transmission is
complete.
Power System Flash Regulator 6. The VREGSF (RCON[11]) bit always reads back as ‘0’.
ADC DONE bit 7. The ADC Conversion Status bit (DONE) does not work when an
external interrupt is selected as the ADC trigger source.
PTG Strobe Output 8. Strobe output pulse width is incorrectly dependent on the
PTGPWD[3:0] (PTGCON[7:4]) bits setting.
Op Amp Enabling Op Amp
mode
9. When using any of these op amp modules, or Analog Channels
AN0, AN3 or AN6, to sample external signals, bit 11 of the CMxCON
register must be set to ‘1’.
Op Amp AC/DC Electrical
Characteristics
10. The AC/DC electrical characteristics for the op amp module (and
the related ADC specifications) are not within the specifications
published in the current data sheet.
PWM Dead-Time
Compensation
11. Dead-time compensation is not enabled for Center-Aligned PWM
mode.
Flash Flash Programming 12. The Stall mechanism may not function properly when erasing or
programming Flash memory.
QEI Index Counter 13. The QEI Index Counter does not count correctly in Quadrature
Detector mode.
QEI Modulo Mode 14. Modulo mode functionality is incorrect when the count polarity bit
is set.
PWM Master Time Base
Mode
15. In Master Time Base mode, writing to the period register and any
other timing parameter of the PWMx module, will cause the update
of the other timing parameter to take effect one PWM cycle after the
period update is effective.
ADC 1.1 Msps Sampling 16. Selecting the same ANx input (AN0 or AN3) for CH0 and CH1 to
achieve a 1.1 Msps sampling rate results in erroneous readings for
CH1.
ADC Channel Scan 17. Channel scanning is limited to AN0 through AN15.
Output Compare Interrupt 18. Under certain circumstances, an output compare match may cause
the Output Compare x Interrupt Flag (OCxIF) bit to become set prior
to the Change-of-State (COS) of the OCx pin.
CAN DMA 19. Write collisions on a DMA-enabled CAN module does not generate
DMAC error traps.
PWM Immediate Update 20. Dead time is not asserted when PDCx is updated to cause an
immediate transition on the PWMxH and PWMxL outputs.
PWM Center-Aligned
Mode
21. PWMxH is asserted for 100% of the PWM period in Complementary
mode under certain circumstances.
PWM Complementary
Mode
22. With dead time greater than zero, 0% and 100% duty cycle cannot
be obtained on PWMxL and PWMxH outputs.
MCLR
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
DS80000533P-page 6 2011-2019 Microchip Technology Inc.
CPU Program Memory 23. Address error trap may occur while accessing certain program
memory locations.
PWM Center-Aligned
Mode
24. Updates to active MDC/PDCx/ALTDTRx/PHASEx registers occur
only once every two PWM periods.
PWM Independent Time
Base Mode
25. Under certain circumstances, updates to the OVRENH and
OVRENL bits may be ignored by the PWMx module.
PWM Center-Aligned
Mode
26. PHASEx register updates are delayed.
CTMU ADC Operation 27. CTMU does not work with the ADC Converter in 12-bit mode.
Input Capture External
Synchronization
28. Input capture and output compare modules cannot be
synchronized.
JTAG I/O 29. MCLR pin operation may be disabled.
I/O Pin Functions that
are Not 5V Tolerant
30. Select pins are not 5V tolerant.
JTAG I/O 31. Active-high logic pulse on the I/O pin with TMS function at POR.
QEI Velocity Counter 32. Under certain circumstances, the Velocity Counter 1 register
(VEL1CNT) misses count pulses.
QEI Position Capture 33. Under certain conditions, the captured position may be off by
±1 count.
QEI Position Capture 34. Position count captured at the rising edge of the HOME signal and
not the INDEX signal.
PWM Center-Aligned
Mode
35. Under certain conditions, PWMxH and PWMxL are deasserted.
PWM Current Reset
Mode
36. When the PWM generator is configured to operate in Current Reset
mode, the PWM Reset will happen only in every alternate PWM
cycle.
Op
Amp/Comparator
External Reference 37. Op Amp/Comparator Voltage Reference fails when the voltage on
VREF+ is less than 1.33V.
PWM PWM Override 38. Glitch on PWMxH or PWMxL pins when override is turned off.
PWM PWM SWAP 39. When in Complementary mode, PWM SWAP feature does not
function properly.
PWM PWM Override 40. PWM override feature is not functional.
CAN Receive Buffer 41. Read-Modify-Write operation on a CxRXFULx register may not
update it correctly.
PWM Edge-Aligned
Mode
42. Missing dead time under certain conditions.
PWM Output Modes 43. Output glitch pulse.
PWM Complementary
Output Mode
44. Missing dead time between complementary outputs under certain
conditions.
PWM PWM SWAP 45. In Center-Aligned mode, there is missing dead time when SWAP is
disabled.
PWM Center-Aligned
Mode
46. Updates to the PHASEx registers occur only at the middle of the
Center-Aligned PWM cycle.
CPU Data Flash Reads 47. Given a specific set of preconditions, when two or more data Flash
read instructions (via Program Space Visibility (PSV) read or Table
Read) are executed back-to-back, one or more subsequent
instructions will be misexecuted.
TABLE 2: SILICON ISSUE SUMMARY (CONTINUED)
Module Feature Item
Number Issue Summary
Work around E Work around SSx ons Affected Fam s and Silicon Revisions Work around Affected Fam s and Silicon Revisions Work around ons
2011-2019 Microchip Technology Inc. DS80000533P-page 7
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
Silicon Errata Issues
1. Module: CPU
When using the Signed 32-by-16-bit Division
instruction, div.sd, the overflow bit does not
always get set when an overflow occurs.
Work around
Test for and handle overflow conditions outside of
the div.sd instruction.
Affected Families and Silicon Revisions
2. Module: CPU
Table Write (TBLWTx), Table Read (TBLRDx) and
PSV Flash read instructions should not be used in
the first or last instruction locations of a DO loop.
Work around
None.
Affected Families and Silicon Revisions
3. Module: SPI
When using the Frame Sync pulse output feature
(FRMEN bit (SPIxCON2[15]) = 1) in Master
mode (SPIFSD bit (SPIxCON2[14]) = 0), the
Frame Sync pulse is not being generated
with an active-low pulse (FRMPOL bit
(SPIxCON2[13]) = 0).
Work around
The SSx pin is used as the Frame Sync pulse
when the Frame Sync pulse output feature is used.
Mapping the SSx input function and output
function to the same pad, by using the Peripheral
Pin Select (PPS) feature, resolves this issue.
Affected Families and Silicon Revisions
4. Module: SPI
When in SPI Slave mode (MSTEN bit
(SPIxCON1[5]) = 0) and using the Frame Sync pulse
output feature (FRMEN bit (SPIxCON2[15]) = 1) in
Slave mode (SPIFSD bit (SPIxCON2[14]) = 1), the
Frame Sync Pulse Edge Select bit must be set to ‘0
(FRMDLY bit (SPIxCON2[1]) = 0).
Work around
There is no work around. The Frame Sync Pulse
Edge Select bit, FRMDLY, cannot be set to
produce a Frame Sync pulse that coincides with
the first bit clock.
Affected Families and Silicon Revisions
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current.
dsPIC33/PIC24EP32 devices A3, A8
dsPIC33/PIC24EP64 devices A2, A3, A8
dsPIC33/PIC24EP128 devices A3, A8
dsPIC33/PIC24EP256 devices A3, A8, A9
dsPIC33/PIC24EP512 devices A7
dsPIC33/PIC24EP32 devices A3, A8
dsPIC33/PIC24EP64 devices A2, A3, A8
dsPIC33/PIC24EP128 devices A3, A8
dsPIC33/PIC24EP256 devices A3, A8, A9
dsPIC33/PIC24EP512 devices A7
dsPIC33/PIC24EP32 devices A3, A8
dsPIC33/PIC24EP64 devices A2, A3, A8
dsPIC33/PIC24EP128 devices A3, A8
dsPIC33/PIC24EP256 devices A3, A8, A9
dsPIC33/PIC24EP512 devices A7
dsPIC33/PIC24EP32 devices A3, A8
dsPIC33/PIC24EP64 devices A2, A3, A8
dsPIC33/PIC24EP128 devices A3, A8
dsPIC33/PIC24EP256 devices A3, A8, A9
dsPIC33/PIC24EP512 devices A7
Work around Affected Fam Work around Affected Fam s and Silicon Revisions s and Silicon Revisions Work around es and Silicon Revisions Work around es and Silicon Revisions
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
DS80000533P-page 8 2011-2019 Microchip Technology Inc.
5. Module: UART
When using UTXISEL[1:0] = 01 (interrupt when
last character is shifted out of the Transmit Shift
Register) and the final character is being shifted
out through the Transmit Shift Register (TSR), the
Transmit (TX) interrupt may occur before the final
bit is shifted out.
Work around
If it is critical that the interrupt processing occurs
only when all transmit operations are complete.
Hold off the interrupt routine processing by adding
a loop at the beginning of the routine that polls the
Transmit Shift Register Empty bit (TRMT) before
processing the rest of the interrupt.
Affected Families and Silicon Revisions
6. Module: Power System
The VREGSF bit functions as documented, but will
always read back as ‘0’. Because of the
Read-Modify-Write process, any BSET or BCLR
instruction of the RCON register will also write a ‘0
to the VREGSF bit.
Work around
If the VREGSF bit is intended to be set to ‘1’, the
user software must also write a1’ to the VREGSF
bit when setting or clearing any other bit in the
RCON register.
Affected Families and Silicon Revisions
7. Module: ADC
The ADC Conversion Status (DONE) bit
(ADxCON1[0]) does not indicate completion of
conversion when an external interrupt is selected
as the ADC trigger source (SSRC[2:0] bits
(AD1CON1[7:5]) = 0x1).
Work around
Use an ADC interrupt or poll the ADxIF bit in the
IFSx registers to determine the completion of
conversion.
Affected Families and Silicon Revisions
8. Module: PTG
When using the strobe output Step commands
(‘PTGCTRL 0b1110’, ‘PTGCTRL 0b1100’ and
PTGCTRL 0b1101’) to write to the AD1CHS0
register, the PTGPWD[3:0] bits (PTGCON[7:4])
determine the number of times the PTG module
will write to the AD1CHS0 register.
Work around
Set the PTGPWD[3:0] bits to ‘0000’ so that the
PTG module does not write to the AD1CHS0
register multiple times.
Affected Families and Silicon Revisions
dsPIC33/PIC24EP32 devices A3, A8
dsPIC33/PIC24EP64 devices A2, A3, A8
dsPIC33/PIC24EP128 devices A3, A8
dsPIC33/PIC24EP256 devices A3, A8, A9
dsPIC33/PIC24EP512 devices A7
dsPIC33/PIC24EP32 devices A3, A8
dsPIC33/PIC24EP64 devices A2, A3, A8
dsPIC33/PIC24EP128 devices A3, A8
dsPIC33/PIC24EP256 devices A3, A8, A9
dsPIC33/PIC24EP512 devices A7
dsPIC33/PIC24EP32 devices A3, A8
dsPIC33/PIC24EP64 devices A2, A3, A8
dsPIC33/PIC24EP128 devices A3, A8
dsPIC33/PIC24EP256 devices A3, A8, A9
dsPIC33/PIC24EP512 devices A7
dsPIC33/PIC24EP32 devices A3, A8
dsPIC33/PIC24EP64 devices A2, A3, A8
dsPIC33/PIC24EP128 devices A3, A8
dsPIC33/PIC24EP256 devices A3, A8, A9
dsPIC33/PIC24EP512 devices A7
Work around Affected Fa ons Work around Affected Farn s and Silicon Revisions
2011-2019 Microchip Technology Inc. DS80000533P-page 9
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
9. Module: Op Amp
When using any of these op amp modules or
analog channels, AN0, AN3 or AN6, to sample
external signals, bit 11 of the CMxCON register
must be set to ‘1’.
Work around
None.
Affected Families and Silicon Revisions
10. Module: Op Amp
The AC/DC electrical characteristics for the
op amp module (and the related ADC module
specifications) differ from the specifications in the
published data sheet. Refer to Ta b l e 3 and Tabl e 4
(below) for the A2 revision silicon specifications.
Work around
None.
Affected Families and Silicon Revisions
TABLE 3: AC/DC CHARACTERISTICS: OP AMP
TABLE 4: AC/DC CHARACTERISTICS: ADC
If Using
This
Feature:
These Conditions Must be Met:
OPMODE (CMxCON[10]) CMxCON[11]
AN0 OPMODE (CM2CON[10]) =
0
CM2CON[11] =
1
AN3 OPMODE (CM1CON[10]) =
0
CM1CON[11] =
1
AN6 OPMODE (CM3CON[10]) =
0
CM3CON[11] =
1
Op Amp 1 OPMODE (CM1CON[10]) =
1
CM1CON[11] =
1
Op Amp 2 OPMODE (CM2CON[10]) =
1
CM2CON[11] =
1
Op Amp 3 OPMODE (CM3CON[10]) =
1
CM3CON[11] =
1
dsPIC33/PIC24EP32 devices
dsPIC33/PIC24EP64 devices A2
dsPIC33/PIC24EP128 devices
dsPIC33/PIC24EP256 devices
dsPIC33/PIC24EP512 devices
dsPIC33/PIC24EP32 devices
dsPIC33/PIC24EP64 devices A2
dsPIC33/PIC24EP128 devices
dsPIC33/PIC24EP256 devices
dsPIC33/PIC24EP512 devices
Param.
No. Symbol Minimum Typical Maximum Units Conditions
CM21a PM40 Degree
CM21b PM30 Degree
CM23a GBW 7 MHz
CM23b GBW 2 MHz
CM49a VOADC AVSS + 0.350
AVSS + 0.500
AVDD – 0.350
AVDD – 0.500
V
V
IOUT = 390 µA, Op Amp 1 and 2
IOUT = 390 µA, Op Amp 3
CM49b VOUT AVSS + 0.375
AVSS + 0.525
AVDD – 0.375
AVDD – 0.525
V
V
IOUT = 390 µA, Op Amp 1 and 2
IOUT = 390 µA, Op Amp 3
CM51a RINT1351 468 613
Parameter
No. Symbol Minimum Typical Maximum Units Conditions
AD57b TSAMP
5 TAD Op Amp 1 and 2, 12-bit mode,
Configuration B
5 TAD Op Amp 3, 10-bit mode,
Configuration B
7 TAD Op Amp 3, 12-bit mode,
Configuration B
Work around Work around Affected Fam s and Silicon Revisions ons
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
DS80000533P-page 10 2011-2019 Microchip Technology Inc.
11. Module: PWM
When dead-time compensation is enabled
(DTC[1:0] (PWMCONx[7:6]) = 11) in
Center-Aligned mode (CAM (PWMCONx[2]) = 1),
the dead time, as specified in the ALTDTRx
register, is not being applied to the PWMxH output.
The leading and trailing edges of the PWMxL
output are extended by one-half the value of the
ALTDTRx register, but the PWMxH leading and
trailing edges are unaffected.
Work around
Using the values from “High-Speed PWM”
(DS70645) in the “dsPIC33/PIC24 Family
Reference Manual”, adjust the PWM parameters
as follows:
Subtract one-half of the ALTDTR dead time
from PDCx
Use twice the value for ALTDTR. For example:
- Frequency of 60 kHz, duty cycle of 50%
- Desired dead time of 833 ns and dead-time
compensation of 833 ns
Using the specified values from “High-Speed
PWM” (DS70645):
PHASEx = 1000
PDCx = 500
ALTDTRx = 833 ns/8.33 ns = 100
DTRx = (833 ns/8.33 ns)/2 = 50
Applying the work around:
ALTDTRx = 2 * 100 = 200
PDCx = PDCx – 25 = 475
Affected Families and Silicon Revisions
12. Module: Flash
The Stall mechanism may not function properly
when erasing or programming Flash memory.
Work around
Disable interrupts until the erase or programming
operation is complete. Test for completion by
inserting a bit test operation of the Write Control
(WR) bit.
Code is provided in Example 1 that can be used to
disable interrupts during RTSP erase/program
operations.
EXAMPLE 1: WORK AROUND CODE
Affected Families and Silicon Revisions
dsPIC33/PIC24EP32 devices A3, A8
dsPIC33/PIC24EP64 devices A2, A3, A8
dsPIC33/PIC24EP128 devices A3, A8
dsPIC33/PIC24EP256 devices A3, A8, A9
dsPIC33/PIC24EP512 devices A7
dsPIC33/PIC24EP32 devices A3, A8
dsPIC33/PIC24EP64 devices A2, A3, A8
dsPIC33/PIC24EP128 devices A3, A8
dsPIC33/PIC24EP256 devices A3, A8, A9
dsPIC33/PIC24EP512 devices A7
; Load write latches if programming
; Setup NVMCON register to erase or program
as required
; Disable interrupts
PUSH SR
MOV #0x00E0, W0
IOR SR
; Write the KEY sequence
MOV #0x55, W0
MOV W0, NVMKEY
MOV #0xAA, W0
MOV W0, NVMKEY
; Start the programming sequence
BSET NVMCON, #15
; Insert two NOPs after programming
NOP
NOP
; Wait for operation to complete
prog_wait:
BTSC NVMCON, #15
BRA prog_wait
; Re-enable interrupts,
POP SR
Work around Affected Fam s and Silicon Revisions Work around Work around Affected Fam es and Silicon Revisions
2011-2019 Microchip Technology Inc. DS80000533P-page 11
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
13. Module: QEI
In Quadrature Encoder mode (CCM[1:0]
(QEIxCON[1:0]) = 00), the Index Counter registers
(INDXxCNTH and INDXxCNTL) cannot be relied
upon to increment when the last known direction
was positive and an index pulse occurs. The Index
Counter register can decrement even if the last
known direction was positive. This does not apply
to the External Clock or Internal Timer QEI modes.
Work around
The index event can be used to implement a
software counter. The direction could be
determined by comparing the current POSxCNT
value to that of the previous Index Event.
Affected Families and Silicon Revisions
14. Module: QEI
When Modulo Count mode (Mode 6) is selected
for the position counter (PIMOD[2:0]
(QEIxCON[12:10]) = 110), and the counter
direction is set to negative (CNTPOL
(QEIxCON[3]) = 1), the functions of the QEIxLEC
and QEIxGEC registers are reversed.
Work around
When using Modulo Count mode in conjunction
with a negative count direction (polarity), use the
QEIxLEC register as the upper count limit and the
QEIxGEC as the lower count limit.
Affected Families and Silicon Revisions
15. Module: PWM
The PWMx module can operate with variable
period, duty cycle, dead-time and phase values.
The master period and other timing parameters can
be updated in the same PWM cycle. With
immediate updates disabled, the new values should
take effect at the start of the next PWM cycle.
As a result of this issue, the updated master period
takes effect on the next PWM cycle, while the
update of the additional timing parameter is
delayed by one PWM cycle. The parameters
affected by this erratum are as follows:
Master Period Registers – Update effective on the
next PWM cycle (PTPER).
Additional PWM Timing Parameters – Update
effective one PWM cycle after master period
update:
Duty Cycle – PDCx and MDC registers
Phase – PHASEx register
Dead Time – DTRx and ALTDTRx registers
and dead-time compensation signals
Clearing of current-limit and Fault conditions,
and application of External Period Reset signal
Work around
If the application requires the master period and
other parameters to be updated at the same time,
enable both immediate updates:
EIPU (PTCON[10]) = 1 – To enable
immediate period updates
IUE (PWMCONx[0]) = 1 – To enable
immediate updates of additional parameters
listed above
Enabling immediate updates will allow updates to
the master period and the other parameter to take
effect immediately after writing to the respective
registers.
Affected Families and Silicon Revisions
dsPIC33/PIC24EP32 devices A3, A8
dsPIC33/PIC24EP64 devices A2, A3, A8
dsPIC33/PIC24EP128 devices A3, A8
dsPIC33/PIC24EP256 devices A3, A8, A9
dsPIC33/PIC24EP512 devices A7
dsPIC33/PIC24EP32 devices A3, A8
dsPIC33/PIC24EP64 devices A2, A3, A8
dsPIC33/PIC24EP128 devices A3, A8
dsPIC33/PIC24EP256 devices A3, A8, A9
dsPIC33/PIC24EP512 devices A7
dsPIC33/PIC24EP32 devices A3, A8
dsPIC33/PIC24EP64 devices A2, A3, A8
dsPIC33/PIC24EP128 devices A3, A8
dsPIC33/PIC24EP256 devices A3, A8, A9
dsPIC33/PIC24EP512 devices A7
Work around 5 and Silicon Revisions Affected Fam Work around ons Work around 5 and Silicon Revisions Affected Fam Work around ons
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
DS80000533P-page 12 2011-2019 Microchip Technology Inc.
16. Module: ADC
Selecting the same ANx input (AN0 or AN3) for
CH0 and CH1 to achieve a 1.1 Msps sampling rate
results in erroneous readings for CH1.
Work around
Bring the analog signal into the device using both
AN0 and AN3, connect externally, and then assign
one input to CH0 and the other to CH1.
If selecting AN0 on CH1 (CH123Sx = 0), select
AN3 on CH0 (CH0Sx = 3). Conversely, if selecting
AN3 on CH1 (CH123Sx = 1), select AN0 on CH0
(CH0Sx = 0).
Affected Families and Silicon Revisions
17. Module: ADC
Selection of channels for channel scan operation
is limited to those available in the AD1CSSL
register (AN0 through AN15). Selections in the
AD1CSSH register, (OA1 through OA3, CTMU
TEMP and CTMU Open) are not available.
Work around
There is no work around of the CTMU TEMP and
CTMU Open selections. OA1 through OA3 can be
scanned using AN3, AN0 and AN6 for Op Amp 1,
Op Amp 2 and Op Amp 3, respectively.
Affected Families and Silicon Revisions
18. Module: Output Compare
Under certain circumstances, an output compare
match may cause the Output Compare Interrupt
Flag (OCxIF) to become set prior to the
Change-of-State (COS) of the OCx pin. This has
been observed when all of the following are true:
The module is in One-Shot mode
(OCM[2:0] = 001, 010 or 100);
One of the timer modules is being used as the
time base; and
A timer prescaler other than 1:1 is selected
If the module is re-initialized by clearing OCM[2:0]
after the One-Shot compare, the OCx pin may not
be driven as expected.
Work around
After OCxIF is set, allow an interval (in CPU
cycles) of at least twice the prescaler factor to
elapse before clearing OCM[2:0]. For example, for
a prescaler value of 1:8, allow 16 CPU cycles to
elapse after the interrupt.
Affected Families and Silicon Revisions
19. Module: CAN
When DMA is used with the CAN module, and the
CPU and DMA write to an CAN Special Function
Register (SFR) at the same time, the DMAC error
trap is not occurring. In addition, neither the
PWCOL[3:0] bits of the DMAPWC SFR or the
DMACERR bit of the INTCON1 SFR are being set.
Since the PWCOLx bits are not set, subsequent
DMA requests to that channel are not ignored.
Work around
There is no work around; however, under normal
circumstances, this situation should not arise.
When DMA is used with the CAN module, the
application should not be writing to the CAN SFRs.
Affected Families and Silicon Revisions
dsPIC33/PIC24EP32 devices A3, A8
dsPIC33/PIC24EP64 devices A2, A3, A8
dsPIC33/PIC24EP128 devices A3, A8
dsPIC33/PIC24EP256 devices A3, A8, A9
dsPIC33/PIC24EP512 devices A7
dsPIC33/PIC24EP32 devices A3, A8
dsPIC33/PIC24EP64 devices A2, A3, A8
dsPIC33/PIC24EP128 devices A3, A8
dsPIC33/PIC24EP256 devices A3, A8, A9
dsPIC33/PIC24EP512 devices A7
dsPIC33/PIC24EP32 devices A3, A8
dsPIC33/PIC24EP64 devices A2, A3, A8
dsPIC33/PIC24EP128 devices A3, A8
dsPIC33/PIC24EP256 devices A3, A8, A9
dsPIC33/PIC24EP512 devices A7
dsPIC33/PIC24EP32 devices A3, A8
dsPIC33/PIC24EP64 devices A2, A3, A8
dsPIC33/PIC24EP128 devices A3, A8
dsPIC33/PIC24EP256 devices A3, A8, A9
dsPIC33/PIC24EP512 devices A7
es and Silicon Revisions a F d m c m A Work around
2011-2019 Microchip Technology Inc. DS80000533P-page 13
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
20. Module: PWM
The PWM generator may not assert dead time on
the edges of transitions. This has been observed
when all of the following conditions are present:
The PWM generator is configured to operate
in Complementary mode with Independent
Time Base (ITB) or master time base;
Immediate update is enabled; and
The value in the PDC register is updated in
such a manner that the PWMxH and PWMxL
outputs make an immediate transition.
The current duty cycle, PDCOLD, newly calculated
duty cycle, PDCNEW, and the point at which a write
to the Duty Cycle register occurs within the PWM
time base, will determine if the PWMxH and
PWMxL outputs make an immediate transition.
PWMxH and PWMxL outputs make an immediate
transition if the Duty Cycle register is written with a
new value, PDCNEW, at a point of time when the
PWM time base is counting a value that is in
between PDCNEW and PDCOLD. Additionally,
writing to the Duty Cycle register, close to the
instant of time where dead time is being applied,
may result in a reduced dead time effective on the
PWMxH and PWMxL transition edges.
In Figure 1, if the duty cycle write occurred in the
shaded box, then PWMxH and PWMxL will make
an immediate transition without dead time.
FIGURE 1: TIMING DIAGRAMS FOR CENTER-ALIGNED AND EDGE-ALIGNED MODES
Work around
None.
However, in most applications the duty cycle update
timing can be controlled using the TRIGx trigger, or
Special Event Trigger, such that the above
mentioned conditions are avoided altogether.
Affected Families and Silicon Revisions
PHASEx
PWMxH
PWMxL
Period
PTMRx
PWMxH
PWMxL
PWMxH
PWMxL
0
PDCOLD
PDCNEW > PDCOLD
PDCNEW < PDCOLD
Center Aligned Mode
0
PHASExPTMRx
Period
PWMxH
PWMxL
PWMxH
PWMxL
PWMxH
PWMxL
PDCOLD
PDCNEW > PDCOLD
PDCNEW < PDCOLD
Edge Aligned Mode
Immediate
Transition Region
dsPIC33/PIC24EP32 devices A3, A8
dsPIC33/PIC24EP64 devices A2, A3, A8
dsPIC33/PIC24EP128 devices A3, A8
dsPIC33/PIC24EP256 devices A3, A8, A9
dsPIC33/PIC24EP512 devices A7
Work around Work around Affected Fam ons
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
DS80000533P-page 14 2011-2019 Microchip Technology Inc.
21. Module: PWM
In Center-Aligned Complementary mode with
Independent Time Base, the PWM generator may
assert the PWMxH output for 100% of the duty
cycle. This has been observed when the value in
its PDCx register is less than one-half the value in
its ALTDTRx register.
Work around
Include a software routine to check that the duty
cycle value written to the PDCx register is always
at least one-half of the value in ALTDTRx.
Example 2 shows one way of doing this, with
PDCtemp representing the value to be written to
the PDCx register.
EXAMPLE 2: WORK AROUND CODE
Affected Families and Silicon Revisions
22. Module: PWM
This issue is applicable when a PWM generator is
configured to operate in Independent Time Base
mode with either Center-Aligned Complementary
mode or Edge-Aligned Complementary mode.
When dead time is non-zero, PWMxL is not
asserted for 100% of the time when PDCx is zero.
Similarly, when dead time is non-zero, PWMxH is
not asserted for 100% of the time when PDCx is
equal to PHASEx. This issue applies to Master
Time Base mode as well.
Work around
In Center-Aligned mode:
To obtain 0% duty cycle, first zero out the
ALTDTRx register, then write zero to the
PDCx register.
To obtain 100% duty cycle, first zero out the
ALTDTRx register, then write (PHASEx + 2) to
the PDCx register.
In Edge-Aligned mode:
To obtain 0% duty cycle, first zero out the
registers, DTRx and ALTDTRx, then write
zero to the PDCx register.
To obtain 100% duty cycle, first zero out the
registers, DTRx and ALTDTRx, then write
(PHASEx + 1) to the PDCx register.
Alternatively, in both Center-Aligned and
Edge-Aligned PWM modes, 0% and 100% duty
cycle can be obtained by enabling the PWM override
(IOCONx[9:8] = 0b11) with the Output Override
Synchronization bit (IOCONx[0]) set as ‘1’:
For 0% duty cycle, set the Override Data bits
(IOCONx[7:6]) for PWMxH and PWMxL as
0b01
For 100% duty cycle, set the Override Data
bits (IOCONx[7:6]) for PWMxH and PWMxL
as ‘0b10
Affected Families and Silicon Revisions
dsPIC33/PIC24EP32 devices A3
dsPIC33/PIC24EP64 devices A2, A3
dsPIC33/PIC24EP128 devices A3
dsPIC33/PIC24EP256 devices A3
dsPIC33/PIC24EP512 devices
Altdtr_by2 = ALTDTRx / 2;
if (PDCtemp < Altdtr_by2)
{
PDCx = Altdtr_by2;
}
else
{
PDCx = PDCtemp;
}
dsPIC33/PIC24EP32 devices A3, A8
dsPIC33/PIC24EP64 devices A2, A3, A8
dsPIC33/PIC24EP128 devices A3, A8
dsPIC33/PIC24EP256 devices A3, A8, A9
dsPIC33/PIC24EP512 devices A7
Work around Work around Affected Fa ’ ons Affected Fam s and Silicon Revisions
2011-2019 Microchip Technology Inc. DS80000533P-page 15
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
23. Module: CPU
An unexpected address error trap may occur
during accesses to program memory addresses,
0x001 through 0x200. This has been observed
when one or more interrupt requests are asserted
while reading or writing program memory
addresses, using TBLRDx, TBLWTx or PSV-based
instructions.
Work around
Before executing instructions that read or write
program memory addresses, 0x001 through
0x200, disable interrupts using the DISI
instruction.
Affected Families and Silicon Revisions
24. Module:PWM
In Center-Aligned mode, updates to active
MDC/PDCx/ALTDTRx/PHASEx registers occur
only once every two PWM periods; that is, when
the PWM timer matches the PHASEx register. In
other words, the double update feature is not
available. Figure 2 illustrates this relationship.
Work around
None.
Affected Families and Silicon Revisions
FIGURE 2: PWM TIMING DIAGRAM
dsPIC33/PIC24EP32 devices A3, A8
dsPIC33/PIC24EP64 devices A2, A3, A8
dsPIC33/PIC24EP128 devices A3, A8
dsPIC33/PIC24EP256 devices A3, A8, A9
dsPIC33/PIC24EP512 devices A7
dsPIC33/PIC24EP32 devices A3
dsPIC33/PIC24EP64 devices A2, A3
dsPIC33/PIC24EP128 devices A3
dsPIC33/PIC24EP256 devices A3
dsPIC33/PIC24EP512 devices
PHASEx
Period
Update Update
0
2x Period
PWMxH
PWMxL
PTMRx
Work around Affected Fa ons Work around Affected Families and Silicon Revisions Work around Affected Fa es and Silicon Revisions MCLR Work around Affected Fam Work around Affected Fa ons
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
DS80000533P-page 16 2011-2019 Microchip Technology Inc.
25. Module:PWM
Under certain circumstances, an update to the
IOCONx register to turn off the override will be
ignored by the PWMx module. The issue has been
observed to occur when the IOCONx update to
turn off the override occurs close to the time when
dead time is being applied.
Work around
1. Turn off the PWM dead time.
2. Alternatively, turn off the PWM override with
the following procedure:
a) Disable the PWMx module (PTEN = 0)
b) Clear the Override Enable bits
(OVRENH = 0 and OVRENL = 0)
c) Enable the PWMx module (PTEN = 1)
Affected Families and Silicon Revisions
26. Module: PWM
In Center-Aligned Complementary mode with
Independent Time Base, updates to the PHASEx
register take effect after a delay of two PWM
periods.
This occurs only when the Immediate Update
feature is disabled (IUE = 0). If Immediate Update
is enabled (IUE = 1), the PHASEx register updates
will take effect immediately.
Work around
None.
Affected Families and Silicon Revisions
27. Module: CTMU
The CTMU cannot be used with the A/D Converter
when the converter is operating in 12-bit mode.
Work around
None.
Affected Families and Silicon Revisions
28. Module: Input Capture
When an input capture module is selected as the
Sync source for either an output compare module
or another input capture module, synchronization
may fail.
Work around
None.
Affected Families and Silicon Revisions
29. Module: JTAG
The MCLR pin (normally input only) may be set as
an output pin through the JTAG interface. If it is set
at an output high level, subsequent device Resets
are prevented until the device is powered down.
Work around
None.
Affected Families and Silicon Revisions
dsPIC33/PIC24EP32 devices A3
dsPIC33/PIC24EP64 devices A2, A3
dsPIC33/PIC24EP128 devices A3
dsPIC33/PIC24EP256 devices A3
dsPIC33/PIC24EP512 devices See Silicon
Issue 40.
dsPIC33/PIC24EP32 devices A3
dsPIC33/PIC24EP64 devices A2, A3
dsPIC33/PIC24EP128 devices A3
dsPIC33/PIC24EP256 devices A3
dsPIC33/PIC24EP512 devices
dsPIC33/PIC24EP32 devices A3, A8
dsPIC33/PIC24EP64 devices A2, A3, A8
dsPIC33/PIC24EP128 devices A3, A8
dsPIC33/PIC24EP256 devices A3, A8, A9
dsPIC33/PIC24EP512 devices A7
dsPIC33/PIC24EP32 devices A3, A8
dsPIC33/PIC24EP64 devices A2, A3, A8
dsPIC33/PIC24EP128 devices A3, A8
dsPIC33/PIC24EP256 devices A3, A8, A9
dsPIC33/PIC24EP512 devices A7
dsPIC33/PIC24EP32 devices
dsPIC33/PIC24EP64 devices
dsPIC33/PIC24EP128 devices
dsPIC33/PIC24EP256 devices
dsPIC33/PIC24EP512 devices
Work around Affected Fam Work around Affected Fa es and Silicon Revisions Work around 5 and Silicon Revisions Affected Fam
2011-2019 Microchip Technology Inc. DS80000533P-page 17
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
30. Module: I/O
On all packages, pins with the following functions
are not 5V tolerant:
• RC3
• RC4
• RC5
•RA9
Work around
None.
Affected Families and Silicon Revisions
31. Module: JTAG
At a Power-on Reset (POR), when JTAG is
disabled in the Configuration bits, the I/O pin with
TMS function produces an active-high logic pulse
with a pulse width in the order of milliseconds.
Work around
None.
Affected Families and Silicon Revisions
32. Module: QEI
The Velocity Counter x (VELxCNT) register is a
16-bit wide register that increments or decrements
based on the signal from the quadrature decoder
logic. Reading this register results in a Counter
Reset. Typically, the user application should read
the Velocity Counter at a rate of 1-4 kHz.
As a result of this issue, the Velocity Counter may
miss a count if the user application reads the
Velocity Counter 1 register at the same time as a
(+1 or -1) count increment occurs.
Work around
None.
Affected Families and Silicon Revisions
24EP32/33EP32 devices A3
24EP64/33EP64 devices A2, A3
24EP128/33EP128 devices A3
24EP256/33EP256 devices A3
dsPIC33/PIC24EP512 devices
dsPIC33/PIC24EP32 devices A3
dsPIC33/PIC24EP64 devices A2, A3
dsPIC33/PIC24EP128 devices A3
dsPIC33/PIC24EP256 devices A3
dsPIC33/PIC24EP512 devices
dsPIC33/PIC24EP32 devices A3, A8
dsPIC33/PIC24EP64 devices A2, A3, A8
dsPIC33/PIC24EP128 devices A3, A8
dsPIC33/PIC24EP256 devices A3, A8, A9
dsPIC33/PIC24EP512 devices A7
Work around es and Silicon Revisions Work around Affected Fa ’ ons
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
DS80000533P-page 18 2011-2019 Microchip Technology Inc.
33. Module: QEI
When index count position capture is being used
(QEIxIOC.QCAPEN = 1), the position count may
be one more or one less than the correct value,
depending on the direction of the count.
This is only observed when the leading edge of the
index pulse occurs prior to the leading edge of the
index match event. When the index pulse starts
after the leading edge of the index match event,
the position count is captured correctly.
Figure 3 shows how this occurs. In these cases,
Encoder Signals A, B and (index) Z are shown,
with the module being configured for index match
when A and B are ‘0’. The effects of a correct and
incorrect capture are shown side by side (shaded
area indicates the index match event); the position
count is shown along the bottom.
FIGURE 3: CORRECT AND INCORRECT
POSITION COUNT
CAPTURES
Work around
There are two different work arounds depending
on the encoder type.
For encoder signals with timing that ensures the
index pulse always starts prior to the start of the
index match event (i.e., encoders with a non-gated
index pulse), measure the direction of the encoder
motion. If the encoder is counting up, add one to
the captured position count; if the encoder is
counting down, subtract one from the captured
position count.
For encoder signals where the index pulse leading
edge approximately coincides with the start of the
index match event (i.e., encoders with a gated
index pulse), a small delay can be added to the
index pulse, for instance, by using a simple R-C
filter.
If the encoder does not meet either of these
criteria, no work around is available.
Affected Families and Silicon Revisions
34. Module: QEI
When QCAPEN (QEIxIOC[15]) is enabled, the
position count is captured at the rising edge of the
HOME signal, instead of the index match event as
indicated by the data sheet.
Work around
None.
Affected Families and Silicon Revisions
A
B
Z
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
A
B
Z
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Incorrect Position Count Capture
Correct Position Count Capture
dsPIC33/PIC24EP32 devices
dsPIC33/PIC24EP64 devices
dsPIC33/PIC24EP128 devices
dsPIC33/PIC24EP256 devices
dsPIC33/PIC24EP512 devices A7
dsPIC33/PIC24EP32 devices A3
dsPIC33/PIC24EP64 devices A2, A3
dsPIC33/PIC24EP128 devices A3
dsPIC33/PIC24EP256 devices A3
dsPIC33/PIC24EP512 devices
2011-2019 Microchip Technology Inc. DS80000533P-page 19
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
35. Module: PWM
In Center-Aligned Complementary mode with
Independent Time Base, if the value in the PDCx
register is less than one-half the value in the
ALTDTRx register, the PWM generator will force
the PWMxL to low, and on the PWMxH, generate
pulses of width less than twice the dead time, as
shown in Figure 4.
FIGURE 4: PWM GENERATOR TIMING DIAGRAM
Period
PTMRx
PWMxH
PWMxL
PWMxH
PWMxL
2 x Period
PDCx = ALTDTRx/2
PDCx < ALTDTRx/2
0
PHASEx
Work around Work around Affected Families and Silicon Revisions es and Silicon Revisions
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
DS80000533P-page 20 2011-2019 Microchip Technology Inc.
Work around
Include a software routine to ensure that the duty
cycle value written to the PDCx register is always at
least one-half of the value in ALTDTRx. Example 3
shows one method, with PDCtemp representing the
variable which has the value to be written to the
PDCx register. Alternatively, for duty cycle values
less than half the desired dead-time value, zero out
the ALTDTRx register or dynamically reduce the
value in the ALTDTRx register, such that ALTDTRx is
always equal to 2 * PDCx, as shown in Example 4.
EXAMPLE 3: WORK AROUND CODE
EXAMPLE 4: WORK AROUND CODE
Affected Families and Silicon Revisions
36. Module: PWM
When the PWM generator is configured to
operate in Current Reset mode (XPRES
(PWMCONx[1]) = 1 with Independent Time Base
mode (ITB (PWMCONx[9]) = 1), the PWM Reset
will happen only in every alternate PWM cycle.
Work around
1. Generate an interrupt when the comparator
state changes. This interrupt should be high
priority and could be either a comparator
interrupt or PWM Fault interrupt. The
current-limit interrupt does not function in
this mode. Inside the interrupt, update
PHASEx (period value) with a value less
than the programmed duty cycle and then
immediately update the PHASEx register
with the value, as required by the application
(PWM_period), shown in Example 5.
EXAMPLE 5: WORK AROUND CODE
2. When the External Current Reset signal is
applied to the PWM generator (configured
using Current-Limit Signal Source Select
bits (CLSRC[4:0]) in the PWMx Fault
Current-Limit Control registers
(FCLCONx[14:10]), depending on the
PWM resolution selected, PCLKDIV[2:0]
(PTCON2[2:0]), the maximum pulse width of
the External Current Reset signal is to be
restricted to less than the values, as shown in
Table 5.
Affected Families and Silicon Revisions
dsPIC33/PIC24EP32 devices A8
dsPIC33/PIC24EP64 devices A8
dsPIC33/PIC24EP128 devices A8
dsPIC33/PIC24EP256 devices A8, A9
dsPIC33/PIC24EP512 devices A7
Altdtr_by2 = ALTDTRx / 2;
if (PDCtemp < Altdtr_by2)
{
PDCx = Altdtr_by2;
}
else
{
PDCx = PDCtemp;
}
#define DESIRED_DEADTIME 100
if (PDCtemp < (DESIRED_DEADTIME/2))
{
ALTDTRx = PDCtemp * 2;
PDCx = PDCtemp;
}
else
{
ALTDTRx = DESIRED_DEADTIME;
PDCx = PDCtemp;
}
TABLE 5: MAXIMUM EXTERNAL CURRENT
RESET SIGNAL WIDTH
PCLKDIV[2:0] Max. External Current Reset
Signal Width (in nS)
000 20
001 40
010 80
011 160
100 320
101 640
110 1280
dsPIC33/PIC24EP32 devices A3
dsPIC33/PIC24EP64 devices A2, A3
dsPIC33/PIC24EP128 devices A3
dsPIC33/PIC24EP256 devices A3
dsPIC33/PIC24EP512 devices A7
PWMx ISR:
{
PHASEx = PDCx - 100;
PHASEx = PWM_period;
PWMxIF = 0;
}
Work around Affected Fam s and Silicon Revisions Work around Affected Fa ons
2011-2019 Microchip Technology Inc. DS80000533P-page 21
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
37. Module: Op Amp/Comparator
Op amp/comparator voltage reference can choose
its source either from VREF+ or AVDD, depending
on the CVRSS bit (CVRCON[4]) setting.
If the CVRSS bit is set to ‘1’, the comparator voltage
reference source will be CVRSRC = (VREF+) – (AVSS).
Due to this issue, if the CVRSS bit is set to ‘1’ and
the voltage on VREF+ is less than 1.33V, the
op amp/comparator voltage reference will
malfunction.
Work around
None.
Affected Families and Silicon Revisions
38. Module: PWM
In Complementary mode after the PWMx module
is enabled (PTEN = 1), if the PWM override is
turned off, a 1 TOSC glitch will be present on
the rising edge of either PWMxH or PWMxL,
whichever occurs first, as shown in Figure 5. The
glitch will be present on PWMxH/PWMxL every
time the override state is changed from enabled to
disabled. The width of this glitch is equal to 1 T
OSC
when PCLKDIV[2:0] = 000; increasing the PWM
input clock prescaler setting will increase the width
of the glitch accordingly.
Since the width of the glitch is just 1 TOSC at higher
values of FOSC, the glitch may not be visible on the
PWMxH/PWMxL pins due to pin and PCB trace
capacitances.
Work around
None.
Affected Families and Silicon Revisions
FIGURE 5: ILLUSTRATION OF 1 TOSC GLITCH WHEN PWM OVERRIDE IS TURNED OFF
dsPIC33/PIC24EP32 devices A3, A8
dsPIC33/PIC24EP64 devices A2, A3, A8
dsPIC33/PIC24EP128 devices A3, A8
dsPIC33/PIC24EP256 devices A3, A8, A9
dsPIC33/PIC24EP512 devices A7
dsPIC33/PIC24EP32 devices A8
dsPIC33/PIC24EP64 devices A8
dsPIC33/PIC24EP128 devices A8
dsPIC33/PIC24EP256 devices A8, A9
dsPIC33/PIC24EP512 devices
PWMxH
PWMxL
TOSC
Override
Disabled
Override
Enabled
Edge-Aligned Mode
Work around s and Silicon Revisions Affected Fam Work around ons Affected Fam s and Silicon Revisions Work around Work around Affected Fa ons
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
DS80000533P-page 22 2011-2019 Microchip Technology Inc.
39. Module: PWM
In Complementary mode, if SWAP (IOCONx[1]) is
set from ‘0’ to ‘1’ after enabling the PWMx module
(PTEN (PTCON[15]) = 1), either PWMxH or
PWMxL may stop functioning until SWAP is set
back to0’.
Work around
Disable dead time.
Affected Families and Silicon Revisions
40. Module: PWM
PWM override feature is not functional.
Work around
None.
Affected Families and Silicon Revisions
41. Module: CAN
When the DMA controller is copying the received
CAN message into an appropriate message buffer
in the user-defined device RAM area, any
Read-Modify-Write operation on a CxRXFULx
(C1RXFUL1, C1RXFUL2, C2RXFUL1 and
C2RXFUL2) register may not update the
CxRXFULx register properly. The CPU can only
clear a bit in the CxRXFULx register. A
Read-Modify-Write operation successfully clears
the intended bit, but it may incorrectly clear the bit
set by the CAN module after a successful transfer
of a message into RAM by the DMA.
Work around
Avoid Read-Modify-Write operations on C1RXFUL1,
C1RXFUL2, C2RXFUL1 and C2RXFUL2 registers.
See Example 6 to clear any bit in the C1RXFUL1,
C1RXFUL2, C2RXFUL1 and C2RXFUL2 registers
while developing code in C:
EXAMPLE 6: WORK AROUND CODE
The CPU can only clear a bit in the CxRXFULx
registers, but the CPU cannot set any bit in any of
the CxRXFULx registers. Therefore, in the work
around (Example 6):
If the FNRB[5:0] (C1FIFO[5:0]) bits value is
less than or equal to 15, only one bit of the
C1RXFUL1 register will be cleared depending
on the FNRB[5:0] bits value.
If the FNRB[5:0] bits value is greater than 15, only
one bit of the C1RXFUL2 register will be cleared
depending on the FNRB[5:0] bits value.
This same method should be adopted for the
C2RXFUL1 and C2RXFUL2 registers.
Affected Families and Silicon Revisions
42. Module: PWM
In Edge-Aligned Complementary mode, changes
to the PHASEx register under certain circum-
stances will result in missing dead time at the
PWMxH-to-PWMxL transition. This has been
observed only when all of the following are true:
Master Time Base mode is enabled
(PWMCONx[9] = 0);
PHASEx is changed after the PWMx module
is enabled; and
The PHASEx register value is changed, so that
either PHASEx < DTRx or PHASEx > PDCx.
Work around
None.
Affected Families and Silicon Revisions
dsPIC33/PIC24EP32 devices A3
dsPIC33/PIC24EP64 devices A2, A3
dsPIC33/PIC24EP128 devices A3
dsPIC33/PIC24EP256 devices A3
dsPIC33/PIC24EP512 devices A7
dsPIC33/PIC24EP32 devices
dsPIC33/PIC24EP64 devices
dsPIC33/PIC24EP128 devices
dsPIC33/PIC24EP256 devices
dsPIC33/PIC24EP512 devices A7
dsPIC33/PIC24EP32 devices A3, A8
dsPIC33/PIC24EP64 devices A2, A3, A8
dsPIC33/PIC24EP128 devices A3, A8
dsPIC33/PIC24EP256 devices A3, A8, A9
dsPIC33/PIC24EP512 devices A7
dsPIC33/PIC24EP32 devices A3, A8
dsPIC33/PIC24EP64 devices A2, A3, A8
dsPIC33/PIC24EP128 devices A3, A8
dsPIC33/PIC24EP256 devices A3, A8, A9
dsPIC33/PIC24EP512 devices A7
if (C1FIFObits.FNRB <= 15)
{
C1RXFUL1 =
(
0x001  C1FIFObits.FNRB);
}
else
{
C1RXFUL2 =
(
0x001  (C1FIFObits.FNRB 16));
}
Work around Work around Affected Fa ons Affected Families and Silicon Revisions
2011-2019 Microchip Technology Inc. DS80000533P-page 23
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
43. Module: PWM
In certain output modes, the PWMx module
produces a pulse glitch of one PWM clock in width
(Figure 6). This has been observed only when all
of the following are true:
Either Redundant or Push-Pull Output mode
is selected (IOCONx[11:10] = 10 or 01);
Immediate Update is disabled
(PWMCONx[0] = 0); and
The value of the current Duty Cycle register
(either the PDCx or MDC register, as deter-
mined by PWMCONx[8]) is updated to zero
from any non-zero value.
The pulse glitch has been observed to occur at the
beginning of the following PWM boundary period.
FIGURE 6:
Work around
If the application requires a duty cycle of zero, two
possible work arounds are available.
1. Use the PWM overrides to force the output to
a low state, instead of writing a0’ to the Duty
Cycle register. When using this method, the
PWM override must be disabled when the
duty cycle is a non-zero value. If output over-
ride synchronization is configured to occur on
CPU clock boundaries (IOCONx[0] = 0),
enabling and disabling the override must be
timed to occur as closely as possible to the
PWM period boundary.
2. Configure the module for Immediate Update
(PWMCONx[0] = 1) before enabling the mod-
ule. In this mode, writes to the Duty Cycle
register have an immediate effect on the
output. As with the previous work around,
writes to the Duty Cycle register must be
timed to occur as close to the PWM period
boundary as possible in order to avoid dis-
tortion of the output.
Affected Families and Silicon Revisions
44. Module: PWM
In Complementary Output mode, the expected
dead time between transitions of the PWMxH and
PWMxL outputs may not be asserted when the
following occurs:
Output override synchronization is configured
to occur on the CPU clock boundary
(IOCONx[0] = 0);
Both PWMxH and PWMxL overrides are
enabled prior to the event (OVRENH and
OVRENL are both ‘1’), and
Both overrides are disabled (OVRENH and
OVRENL are both ‘0’) at the instant the
dead time should be asserted (Figure 7).
This has been observed in both Center-Aligned
and Edge-Aligned modes.
FIGURE 7:
Work around
None.
Affected Families and Silicon Revisions
dsPIC33/PIC24EP32 devices A3, A8
dsPIC33/PIC24EP64 devices A2, A3, A8
dsPIC33/PIC24EP128 devices A3, A8
dsPIC33/PIC24EP256 devices A3, A8, A9
dsPIC33/PIC24EP512 devices A7
1 PWM Clock
Duty Cycle
> 0
Duty Cycle
= 0
PWMxH
PWMxL
dsPIC33/PIC24EP32 devices A3, A8
dsPIC33/PIC24EP64 devices A2, A3, A8
dsPIC33/PIC24EP128 devices A3, A8
dsPIC33/PIC24EP256 devices A3, A8, A9
dsPIC33/PIC24EP512 devices A7
PWMxH
PWMxL
Missing
Dead Time
OVERENH and
OVRENL = 1
OVERENH and
OVRENL = 0
OVRDAT[1:0] = 10 Throughout
Work around Work around W Affected Fa ans
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
DS80000533P-page 24 2011-2019 Microchip Technology Inc.
45. Module: PWM
In Center-Aligned Complementary mode with
Independent Time Base, the expected dead time
between transitions of the PWMxH and PWMxL
outputs may not be asserted when SWAP is
disabled under the following conditions:
PWMx module is enabled (PTEN = 1)
SWAP is enabled prior to this event
Work around
None.
Affected Families and Silicon Revisions
46. Module: PWM
In Center-Aligned Complementary mode with
Independent Time Base, updates to the
PHASEx register take effect in the middle of a
center-aligned PWM cycle, as shown in Figure 8.
This occurs only when the Immediate Update
feature is disabled (IUE = 0). If Immediate Update
is enabled (IUE = 1), the PHASEx register updates
will take effect immediately.
Work around
None.
Affected Families and Silicon Revisions
FIGURE 8:
dsPIC33/PIC24EP32 devices A3, A8
dsPIC33/PIC24EP64 devices A2, A3, A8
dsPIC33/PIC24EP128 devices A3, A8
dsPIC33/PIC24EP256 devices A3, A8, A9
dsPIC33/PIC24EP512 devices A7
dsPIC33/PIC24EP32 devices A8
dsPIC33/PIC24EP64 devices A8
dsPIC33/PIC24EP128 devices A8
dsPIC33/PIC24EP256 devices A8, A9
dsPIC33/PIC24EP512 devices A7
PHASEx
Period
Update Update
0
2x Period
PWMxH
PWMxL
PHASEx
2011-2019 Microchip Technology Inc. DS80000533P-page 25
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
47. Module: CPU
When two or more data Flash read instructions
(via Program Space Visibility (PSV) read or table
read) are executed back-to-back, one or more
subsequent instructions can be misexecuted when
all of the conditions in Table 6 occur.
Figure 9 provides an example of the effective
behavior.
FIGURE 9: SIMPLIFIED BEHAVIOR
Note: This issue is deterministic based on
the instruction sequence executed,
and is not sensitive to manufacturing
process, temperature, voltage or
other application operating conditions
that do not affect the instruction
sequence.
TABLE 6: REQUIRED CONDITIONS
1. A PSV MOV.D instruction is executed, with opcode at address ending in 0x0, 0x4, 0x8 or 0xC; and
2. Some “connecting code” is executed (following the MOV.D of condition 1), with the properties:
a) The connecting code does not include any program flow changes, including: taken branch instructions
(including all versions of BRA, CPBEQ, CPBGT, CPBLT, CPBNE), CALL, CALL.L, GOTO, GOTO.L, RCALL,
RETLW, RETURN, vectoring to an ISR, returning from an interrupt (RETFIE) and certain debug operations,
such as break and one-step; and
b) The connecting code does not include a TBLRDx or non-MOV.D PSV instruction, located at a Flash memory
address ending in 0x0, 0x4, 0x8 or 0xC; and
c) The connecting code is at least two instruction words in length; and
d) The connecting code does not end with a REPEAT instruction, with count > 0; and
3. 2 back-to-back PSV or TBLRDx instructions are executed (following the code of condition 2), where the first
of the back-to-back instructions is located at an address ending in 0x2, 0x6, 0xA or 0xE.
Normal State
(no problem,
default state
after any Reset)
Conditions 1
and 2 Met (no
problem yet)
Issue Manifests – One
or More Subsequent
Instructions are
Misexecuted with the
Opcode of a Prior
Instruction
PSV MOV.D @
Address Ending in
2 Back-to-Back PSV or TBLRDx
Instructions Starting @ Address
Ending in 0x2, 0x6, 0xA or 0xE
Any Program Flow Change
(see condition 2a)
0x0, 0x4, 0x8 or 0xC,
TBLRDx or PSV Instruction (other than
MOV.D) @ Address Ending in 0x0, 0x4, 0x8 or
0xC (see condition 2b)
Followed by
“Connecting Code”
Work around ans
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
DS80000533P-page 26 2011-2019 Microchip Technology Inc.
Work around
The issue can be avoided by ensuring any one or
more of the requirements are not met. For
example:
1. All instances of PSV MOV.D can be
replaced with two PSV MOV instructions
instead. Non-PSV MOV.D instructions
acting on RAM/SFRs do not need to be
modified; or
2. If not already present, a program flow
change instruction (such as BRA $+2) can
be inserted above back-to-back data Flash
read sequences; or
3. Back-to-back data Flash read instruction
sequences can be broken up by inserting a
non-Flash read instruction (such as a NOP)
in between the Flash read instructions; or
4. The alignment of the code can be shifted to
avoid the required opcode location
addresses.
C code built with MPLAB® XC16 Compiler,
Version 1.32, or later, implements the work around
by default. However, if the application uses
Assembly language routines, these should be
manually modified to implement the work around.
Additionally, if precompiled libraries are used,
these should be built with XC16 Version 1.32 or
later. For additional information, please visit:
www.microchip.com/erratum_psrd_psrd.
Affected Families and Silicon Revisions
dsPIC33/PIC24EP32 devices A3, A8
dsPIC33/PIC24EP64 devices A2, A3, A8
dsPIC33/PIC24EP128 devices A3, A8
dsPIC33/PIC24EP256 devices A3, A8, A9
dsPIC33/PIC24EP512 devices A7
(3} 17) 5m
2011-2019 Microchip Technology Inc. DS80000533P-page 27
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
Data Sheet Clarifications
The following typographic corrections and clarifications
are to be noted for the latest version of the device data
sheet (DS70000657H):
1. Module: Electrical Characteristics
Table 30-53 states incorrect values for some of the
parameters. The corrected values are shown in
bold below.
Note: Corrections are shown in bold. Where
possible, the original bold text formatting
has been removed for clarity.
TABLE 30-53: OP AMP/COMPARATOR SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)(1)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min. Typ.(2)Max. Units Conditions
Comparator AC Characteristics
CM10 TRESP Response Time(3)19 ns V+ input step of 100 mV,
V- input held at VDD/2
CM11 TMC2OV Comparator Mode
Change to Output Valid
——10 µs
Comparator DC Characteristics
CM30 VOFFSET Comparator Offset
Voltage
±10 ±15(7)mV
CM31 VHYST Input Hysteresis
Voltage(3)
30 65(7)mV
CM32 TRISE/TFALL Comparator Output
Rise/Fall Time(3)
20 ns 1 pF load capacitance
on input
CM34 VICM Input Voltage Range AVSS AVDD V
Op Amp AC Characteristics
CM20 SRSlew Rate 3.7 7.5 16 V/µs 10 pF load
CM21a PMPhase Margin
(Configuration A)(3,4)
55 Degree G = 4V/V; 10 pF load
CM21b PMPhase Margin
(Configuration B)(3,5)
40 Degree G = 4V/V; 10 pF load
CM22 GMGain Margin(3) 20 db G = 100V/V; 10 pF load
Note 1: Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality
is tested, but not characterized. Analog modules (ADC, op amp/comparator and comparator voltage
reference) may have degraded performance. Refer to Parameter BO10 in Table 30-13 for the minimum and
maximum BOR values.
2: Data in “Typ” column are at 3.3V, +25°C unless otherwise stated.
3: Parameter is characterized but not tested in manufacturing.
4: See Figure 25-6 for configuration information.
5: See Figure 25-7 for configuration information.
6: Resistances can vary by ±10% between op amps.
7: These parameters have a combined effect on the actual performance of the comparator.
n E y n n n n m n u u u v LPRcFu 2x ma n M8 125: a 212 y
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
DS80000533P-page 28 2011-2019 Microchip Technology Inc.
2. Module: DC and AC Device
Characteristics Graphs
The typical LPRC frequency plot over temperature
at VDD = 3.3V has been corrected, as shown in
Figure 32-10 below.
FIGURE 32-10: TYPICAL LPRC
FREQUENCY @ VDD = 3.3V
3. Module: Electrical Characteristics
Table 30-11 had incorrect information in Note 5
and Note 6. The corrected Note 5 and Note 6 are
shown below:
5. VIH source > (VDD + 0.3) for non-5V tolerant pins
only.
6. Digital 5V tolerant pins do not have an internal
high-side diode to VDD, and therefore, cannot
tolerate any “positive” input injection current.
4. Module: Electrical Characteristics
Page Erase Time (TPE) Parameters D137a-D137b
and Word Write Cycle Time (TWW) Parameters
D138a-D138b were incorrectly specified in
Table 30-14. The corrected values are shown in
bold below.
-40C 25C 125C 150C
min 25.2 30.8 30 29.6
mean 28.9 32 31.2 30.8
max 32.8 34.8 34 33.6
24
25
26
27
28
29
30
31
32
33
34
35
36
L
P
R
C
F
r
e
q
u
e
n
c
y
(
K
H
x
)
min
mean
max
)
LPRC Frequency (kHz)
TABLE 30-14: DC CHARACTERISTICS: PROGRAM MEMORY
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min. Typ.(1)Max. Units Conditions
Program Flash Memory
D130 EPCell Endurance 10,000 E/W -40C to +125C
D131 VPR VDD for Read 3.0 3.6 V
D132b VPEW VDD for Self-Timed Write 3.0 3.6 V
D134 TRETD Characteristic Retention 20 Year Provided no other specifications
are violated, -40C to +125C
D135 IDDP Supply Current during
Programming(2)
10 mA
D136 IPEAK Instantaneous Peak Current
During Start-up
150 mA
D137a TPE Page Erase Time 146893 FRC
Cycles
TA = +85°C
D137b TPE Page Erase Time 146893 FRC
Cycles
TA = +125°C
D138a TWW Word Write Cycle Time 346 FRC
Cycles
TA = +85°C
D138b TWW Word Write Cycle Time 346 FRC
Cycles
TA = +125°C
Note 1: Data in “Typical” column are at 3.3V, +25°C unless otherwise stated.
2: Parameter characterized but not tested in manufacturing.
Km
2011-2019 Microchip Technology Inc. DS80000533P-page 29
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
5. Module: Electrical Characteristics
In Ta b l e 30-53, the Feedback Resistance Value
parameter (CM48, RFEEDBACK) was missing a
note describing the minimum input resistance (R1)
requirement and the resulting limitation on the
minimum gain. The updated information is shown
in bold below.
TABLE 30-53: OP AMP/COMPARATOR SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)(1)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min. Typ.(2)Max. Units Conditions
Op Amp DC Characteristics
CM40 VCMR Common-Mode Input
Voltage Range
AVSS AVDD V
CM41 CMRR Common-Mode
Rejection Ratio(3)
40 db VCM = AVDD/2
CM42 VOFFSET Op Amp Offset
Voltage(3)
±5 mV
CM43 VGAIN Open-Loop Voltage
Gain(3)
90 db
CM44 IOS Input Offset Current See pad leakage
currents in
Ta b l e 30-11
CM45 IBInput Bias Current See pad leakage
currents in
Ta b l e 30-11
CM46 IOUT Output Current 420 µA With minimum value
of RFEEDBACK (CM48)
CM48 RFEEDBACK(7)Feedback Resistance
Value
8 — — k
CM49a VOADC Output Voltage
Measured at OAx Using
ADC(3,4)
AVSS + 0.077
AVSS + 0.037
AVSS + 0.018
AVDD – 0.077
AVDD – 0.037
AVDD – 0.018
V
V
V
IOUT = 420 µA
IOUT = 200 µA
IOUT = 100 µA
Note 1: Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality
is tested, but not characterized. Analog modules (ADC, op amp/comparator and comparator voltage
reference) may have degraded performance. Refer to Parameter BO10 in Table 30-13 for the minimum and
maximum BOR values.
2: Data in “Typ” column are at 3.3V, +25°C unless otherwise stated.
3: Parameter is characterized but not tested in manufacturing.
4: See Figure 25-6 for configuration information.
5: See Figure 25-7 for configuration information.
6: Resistances can vary by ±10% between op amps.
7: Input resistance (R1) must be less than or equal to 2 k. The resulting minimum gain of the op amp
circuit is equal to 4.
®@&
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
DS80000533P-page 30 2011-2019 Microchip Technology Inc.
6. Module: High-Temperature Electrical
Characteristics
The High-Temperature Electrical Characteristics
section did not include information regarding the
FRC accuracy at an operating temperature of
+125°C > TA > +150°C. Table 7 provides this missing
information.
7. Module: I/O Ports
The first paragraph of Section 11.2 “Configuring
Analog and Digital Port Pins” is amended with
the following text:
“When ANSEL = 1 (the port is selected as analog)
and TRIS = 1 (digital I/O is enabled), the digital
input value read by the port is always0’.”
8. Module: 10/12-Bit Analog-to-Digital
Converter (ADC)
Note 2 of Register 23-8 (AD1CSSL) is amended
with the following text:
“The outputs for Op Amps 1, 2 and 3 can be
scanned by selecting analog inputs, AN3, AN0 and
AN6, respectively.”
9. Module: Comparator/Op Amp
The following text is amended to the end of
Section 25.1 “Op Amp Application
Considerations”:
“When the op amp output is to be made available
on the corresponding OAxOUT pin, set both the
pin’s TRISx bit and the corresponding ANSELx bit
to ‘1’.”
10. Module: Comparator/Op Amp
Figure 25-1 (shown below) is corrected to show
that the op amp in these modules obtains its
inverting and non-inverting inputs directly from the
CxIN1-/1+ pins. The operation of the actual
module is unchanged. (Footnotes in the original
are unchanged, but are removed here for clarity.)
FIGURE 25-1: OP AMP/COMPARATOR x MODULE BLOCK DIAGRAM (MODULES 1, 2 AND 3)
TABLE 7: INTERNAL FRC ACCURACY
AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature +125°C TA +150°C for High Temperature
Param
No. Characteristic Min Typ Max Units Conditions
Internal FRC Accuracy @ FRC Frequency = 7.37 MHz(1)
Hxx FRC -3 -2 +3 %+125°C TA +150°C VDD = 3.0-3.6V
Note 1: Frequency is calibrated at +25°C and 3.3V.
Blanking
Function
Digital
Filter
CxOUT
(1)
(see Figure 25-4)(see Figure 25-5)
PTG Trigger
Input
0
1
00
01
CxIN1+
CVREFIN(1)
CxIN1-
CXIN2-(1)
CMPx
+
VIN-
VIN+
CCH[1:0] (CMxCON[1:0])
CREF (CMxCON[4])
Op Amp/Comparator(2)
Op Ampx
+
OAx/ANx
(3)
OAxOUT/ANx
OPMODE (CMxCON[10])
(to ADC)
RINT1
2011-2019 Microchip Technology Inc. DS80000533P-page 31
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
11. Module: Electrical Characteristics
Table 30-53 does not include information about
the minimum and maximum values for the op amp
offset voltage. The updated values are shown in
bold below.
12. Module: High-Temperature Electrical
Characteristics
The Op Amp/Comparator Specifications table
(Ta b l e 31-14) is added to the High-Temperature
Electrical Characteristics section as shown below.
TABLE 30-53: OP AMP/COMPARATOR SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
(1)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No. Symbol Characteristic Min. Typ.(2)Max. Units Conditions
Op Amp DC Characteristics
CM40 VCMR Common-Mode Input
Voltage Range
AVSS AVDD V
CM41 CMRR Common-Mode
Rejection Ratio(3)
40 db VCM = AVDD/2
CM42 VOFFSET Op Amp Offset
Voltage
-30 ±5 +30 mV
CM43 VGAIN Open-Loop Voltage
Gain(3)
90 db
TABLE 31-14: OP AMP/COMPARATOR SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +150°C
Param
No. Symbol Characteristic Min. Typ. Max. Units Conditions
Op Amp DC Characteristics
HCM42 VOFFSET Op Amp Offset Voltage -40 ±5 +40 mV
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
DS80000533P-page 32 2011-2019 Microchip Technology Inc.
13. Module: Power-Saving Features
In Section 10.0 “Power-Saving Features”,
there are two changes included.
Change 1: Example 10-1 is modified to show a
condition and a note. The changes are shown
below in bold.
EXAMPLE 10-1: PWRSAV INSTRUCTION SYNTAX
Change 2: The fourth paragraph of
Section 10.2.1 “Sleep Mode” is modified to
include the condition where the Flash voltage reg-
ulator is placed in Standby mode. An additional
example is added to show how to implement the
SLEEP instruction in a 4-instruction word-aligned
function. The modified text is added as follows:
For optimal power savings, the internal regulator
and the Flash regulator can be configured to go
into standby when Sleep mode is entered by
clearing the VREGS (RCON[8]) and VREGSF
(RCON[11]) bits (default configuration).
However, putting the Flash voltage regulator in
Standby mode (VREGSF = 0) when in Sleep
has the effect of corrupting the prefetched
instructions placed in the instruction queue.
When the part wakes up, these instructions may
cause undefined behavior. To remove this prob-
lem, the instruction queue must be flushed after
the part wakes up. A way to flush the instruction
queue is to perform a branch. Therefore, it is
required to implement the SLEEP instruction in a
function with 4-instruction word alignment. The
4-instruction word alignment will assure that the
SLEEP instruction is always placed on the
correct address to make sure the flushing will be
effective. Example 10-2 shows how this is
performed.
EXAMPLE 10-2: SLEEP MODE PWRSAV
INSTRUCTION SYNTAX
(WITH FLASH VOLTAGE
REGULATOR SET TO
STANDBY MODE)
PWRSAV #IDLE_MODE ; Put the device into Idle mode
PWRSAV #SLEEP_MODE ; Put the device into Sleep mode(1)
Note 1: The use of PWRSV #SLEEP_MODE has limitations when the Flash Voltage Regulator bit, VREGSF
(RCON[11]), is set to Standby mode. Refer to Section 10.2.1 “Sleep Mode” for more information.
.global _GoToSleep
.section .text
.align 4
_GoToSleep:
PWRSAV #SLEEP_MODE
BRA TO_FLUSH_QUEUE_LABEL
TO_FLUSH_QUEUE_LABEL:
RETURN
2011-2019 Microchip Technology Inc. DS80000533P-page 33
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
14. Module: Introduction
In Tab le 1 and Ta b le 2 of the data sheet, the 36-pin
UQFN package (shown in bold) is added to the
devices listed in the following tables.
TABLE 1: dsPIC33EPXXXGP50X and PIC24EPXXXGP20X GENERAL PURPOSE FAMILIES
Device
Page Erase Size (Instructions)
Program Flash Memory (Kbytes)
RAM (Kbytes)
Remappable Peripherals
I2C
CRC Generator
10-Bit/12-Bit ADC (Channels)
Op Amps/Comparators
CTMU
PTG
I/O Pins
Pins
Packages
16-Bit/32-Bit Timers
Input Capture
Output Compare
UART
SPI(2)
ECAN™ Technology
External Interrupts(3)
PIC24EP32GP203 512 32 45 4 4 2 2 3 2 1 8 3/4 Yes Yes 25 36 VTLA
UQFN
PIC24EP64GP203 1024 64 8
dsPIC33EP32GP503 512 32 45 4 4 2 2 1 3 2 1 8 3/4 Yes Yes 25 36 VTLA
UQFN
dsPIC33EP64GP503 1024 64 8
TABLE 2: dsPIC33EPXXXMC20X/50X AND PIC24EPXXXMC20X MOTOR CONTROL FAMILIES
Device
Page Erase Size (Instructions)
Program Flash Memory (Kbytes)
RAM (Kbytes)
Remappable Peripherals
I2C
CRC Generator
10-Bit/12-Bit ADC (Channels)
Op Amps/Comparators
CTMU
PTG
I/O Pins
Pins
Packages
16-Bit/32-Bit Timers
Input Capture
Output Compare
Motor Control PWM(4)
(Channels)
Quadrature Encoder Interface
UART
SPI(2)
ECAN™ Technology
External Interrupts(3)
PIC24EP32MC203 512 32 45 4 4 6 1 2 2 3 2 1 8 3/4 Yes Yes 25 36 VTLA
UQFN
PIC24EP64MC203 1024 64 8
dsPIC33EP32MC203 512 32 45 4 4 6 1 2 2 3 2 1 8 3/4 Yes Ye s 25 36 VTLA
UQFN
dsPIC33EP64MC203 1024 64 8
dsPIC33EP32MC503 512 32 45 4 4 6 1 2 2 1 3 2 1 8 3/4 Yes Ye s 25 36 VTLA
UQFN
dsPIC33EP64MC503 1024 64 8
Eu:
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
DS80000533P-page 34 2011-2019 Microchip Technology Inc.
15. Module: Introduction
The following two 36-pin UQFN diagrams are
added to the “Pin Diagrams” section of the data
sheet.
SCK1/RP39/INT0/RB7
PGEC2/ASCL2/RP38/RB6
PGED2/ASDA2/RP37/RB5
VDD
SCL2/RP36/RB4
RPI45/CTPLS/RB13
RPI44/RB12
TDI/RP43/RB11
TDO/RP42/RB10
VCAP
VSS
TMS/ASDA1/SDI1/RP41/RB9
RPI46/T3CK/RB14
RPI47/T5CK/RB15
AVSS
A
V
DD
MCLR
PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1
VSS
OSC1/CLKI/RA2
OSC2/CLKO/RA3
PGEC1/AN4/C1IN1+/RPI34/RB2
PGED1/AN5/C1IN1-/RP35/RB3
AN0/OA2OUT/RA0
AN1/C2IN1+/RA1
dsPIC33EP32GP503
1
3
4
5
7
2
6
18171615
20
19
21
8
9
10 11 12 13 14
27
26
25
24
23
22
2829303136 35 34 33 32
VDD
RP56/RC8
VDD
VSS
VDD
SDA2/RPI24/RA8
AN6/OA3OUT/C4IN1+/OCFB/RC0
AN7/C3IN1-/C4IN1-/RC1 dsPIC33EP64GP503
PIC24EP32GP203
PIC24EP64GP203
TCK/CVREF1O/ASCL1/SDO1/RP40/T4CK/RB8
CVREF2O/RP20/T1CK/RA4
= Pins are up to 5V tolerant
Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4 “Peripheral Pin Select
(PPS)” for available peripherals and information on limitations.
2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 “I/O Ports” for more
information.
3: If the op amp is selected when OPMODE (CMxCON[10]) = 1, the OAx input is used; otherwise, the ANx input is used.
4: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in
Table 27-2.
(4)
36-Pin UQFN(1,2,3)
%. f zagmzsm \_H_H_H_l-\_H_l-'- III-IEEE: j].|:|:|:|:|:JI -V_H_H_H_‘-V_H_‘
2011-2019 Microchip Technology Inc. DS80000533P-page 35
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
SCK1/RP39/INT0/RB7
PGEC2/ASCL2/RP38/RB6
PGED2/ASDA2/RP37/RB5
VDD
FLT32/SCL2/RP36/RB4
RPI45/PWM2L/CTPLS/RB13
RPI44/PWM2H/RB12
TDI/RP43/PWM3L/RB11
TDO/RP42/PWM3H/RB10
VCAP
VSS
TMS/ASDA1/SDI1/RP41/RB9
RPI46/PWM1H/T3CK/RB14
RPI47/PWM/1L/T5CK/RB15
AVSS
A
V
DD
MCLR
PGED3/VREF-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0
PGEC3/VREF+/AN3/OA1OUT/RPI33/CTED1/RB1
VSS
OSC1/CLKI/RA2
OSC2/CLKO/RA3
PGEC1/AN4/C1IN1+/RPI34/RB2
PGED1/AN5/C1IN1-/RP35/RB3
AN0/OA2OUT/RA0
AN1/C2IN1+/RA1
dsPIC33EP32MC203/503
1
3
4
5
7
2
6
18171615
20
19
21
8
9
10 11 12 13 14
27
26
25
24
23
22
2829303136 35 34 33 32
VDD
RP56/RC8
VDD
VSS
VDD
SDA2/RPI24/RA8
AN6/OA3OUT/C4IN1+/OCFB/RC0
AN7/C3IN1-/C4IN1-/RC1 dsPIC33EP64MC203/503
PIC24EP32MC203
PIC24EP64MC203
TCK/CVREF1O/ASCL1/SDO1/RP40/T4CK/RB8
CVREF2O/RP20/T1CK/RA4
= Pins are up to 5V tolerant
(4)
36-Pin UQFN(1,2,3)
Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4 “Peripheral Pin Select
(PPS)” for available peripherals and information on limitations.
2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 “I/O Ports” for more
information.
3: If the op amp is selected when OPMODE (CMxCON[10]) = 1, the OAx input is used; otherwise, the ANx input is used.
4: There is an internal pull-up resistor connected to the TMS pin when the JTAG interface is active. See the JTAGEN bit field in
Table 27-2.
TLC
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
DS80000533P-page 36 2011-2019 Microchip Technology Inc.
16. Module: Packaging Information
The following drawing of the 36-pin UQFN
package marking is added to Section 33.1
“Package Marking Information”.
36-Lead UQFN (5x5 mm)
XXXXXXX
YYWWNNN
Example
33EP64GP
503-I/TL
1310017
e3
XXXXXXX
XXXXXXX
~—D——>—D Ia \ E —>‘\ X/ // ' I // / I I ///// \ / // / ‘ //// i/ ' 77777 if _\I Q I I5: TOP VIEW -- I »I<—i§i:d $-lll3="" :5;="" side="" view="" 5="" uuuulijuuuu="" i:="" wei="" g="" !="" g="" d="" i="" c="" 3="" -="" c="" i="" e,="">< \\\="" c="" r="" \\\\="" e="" j="" i="" .="" .="" c="" ~on="" w§‘mfl="" n="" h="" n="" n‘fi—j="" n="" i="" ii="" i:i—’i="" l?="" 49="" 26057306="" a="" b="" bottom="" view="">
2011-2019 Microchip Technology Inc. DS80000533P-page 37
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
17. Module: Packaging Information
The following three new drawings of the 36-pin UQFN package are added to Section 33-2 “Package Details”.
B
A
0.10 C
0.10 C
0..07 C A B
0.05 C
(DATUM B)
(DATUM A)
CSEATING
PLANE
NOTE 1
1
2
N
2X
TOP VIEW
SIDE VIEW
BOTTOM VIEW
NOTE 1
1
2
N
0.10 C A B
0.10 C A B
0.10 C
0.08 C
Microchip Technology Drawing C04-436A–M5 Sheet 1 of 2
D
E
A
16X b
e
2X
D2
E2
K
L
36X
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
36-Lead Ultra Thin Plastic Quad Flat, No Lead Package (M5) - 5x5 mm Body [UQFN]
With Corner Anchors
SEE
DETAIL A
Nales I. Pm 2. Pa 3. Dwm
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
DS80000533P-page 38 2011-2019 Microchip Technology Inc.
Microchip Technology Drawing C04-436A–M5 Sheet 2 of 2
Number of Terminals
Overall Height
Terminal Width
Overall Width
Terminal Length
Exposed Pad Width
Terminal Thickness
Pitch
Standoff
Units
Dimension Limits
A1
A
b
E2
A3
e
L
E
N
0.40 BSC
0.152 REF
3.60
0.30
0.15
0.50
0.00
0.20
0.40
3.70
0.55
0.02
5.00 BSC
MILLIMETERS
MIN NOM
36
3.80
0.50
0.25
0.60
0.05
MAX
K0.25 REF
REF: Reference Dimension, usually without tolerance, for information purposes only.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
1.
2.
3.
Notes:
Pin 1 visual index feature may vary, but must be located within the hatched area.
Package is saw singulated
Dimensioning and tolerancing per ASME Y14.5M
Terminal-to-Exposed-Pad
36-Lead Ultra Thin Plastic Quad Flat, No Lead Package (M5) - 5x5 mm Body [UQFN]
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
With Corner Anchors
Overall Length
Exposed Pad Length
D
D2 3.60
5.00 BSC
3.70 3.80
C
SEATING
PLANE
(A3)
A1
A
DETAIL A
T i JE— UUUUUEUD] J— ‘T. E0 0 O DEED— LE 2 Z 21% \Lfg 0% F Euunnnnunu TH 4L \ [EL
2011-2019 Microchip Technology Inc. DS80000533P-page 39
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
RECOMMENDED LAND PATTERN
Dimension Limits
Units
C2
Optional Center Pad Width
Contact Pad Spacing
Optional Center Pad Length
Contact Pitch
Y2
X2
3.80
3.80
MILLIMETERS
0.40 BSC
MIN
E
MAX
5.00
Contact Pad Length (X36)
Contact Pad Width (X36)
Y1
X1
0.80
0.20
Microchip Technology Drawing C04-2436A–M5
NOM
36-Lead Ultra Thin Plastic Quad Flat, No Lead Package (M5) - 5x5 mm Body [UQFN]
SILK SCREEN
1
2
36
C2
E
X1
Y1
G1
Y2
X2
C1Contact Pad Spacing 5.00
Contact Pad to Center Pad (X36) G1 0.20
Thermal Via Diameter V
Thermal Via Pitch EV
0.30
1.00
EV
EV
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
Dimensioning and tolerancing per ASME Y14.5M
For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
1.
2.
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
With Corner Anchors
C1
Y3
X3
R1
Corner Pad Length (X36)
Corner Pad Width (X4)
Y3
X3
0.85
0.20
Corner Pad Radius R1 0.10
ØV
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
DS80000533P-page 40 2011-2019 Microchip Technology Inc.
18. Module: Electrical Characteristics
The 36-Pin UQFN package is added to
Table 30-3: Thermal Packaging Characteristics
of the data sheet. The updates are shown in bold.
19. Module: Product Identification System
The Package section of the “Product Identification
System” section in the data sheet is updated with
the added 36-Pin UQFN package (M5). The new
package is shown in bold.
.
20. Module: High-Temperature Electrical
Characteristics
The Operating Junction Temperature Range in
Table 31-2: Thermal Operation Conditions has
been updated. The update is shown below in bold.
TABLE 31-2: THERMAL OPERATING CONDITIONS
TABLE 30-3: THERMAL PACKAGING CHARACTERISTICS
Characteristic Symbol Typ. Max. Unit Notes
Package Thermal Resistance, 36-Pin VTLA 5x5 mm JA 28.5 °C/W 1
Package Thermal Resistance, 36-Pin UQFN, 5x5 mm JA 29.2 °C/W 1
Package Thermal Resistance, 28-Pin QFN-S JA 30.0 °C/W 1
Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations.
Package: M5 = Ultra Thin Plastic Quad Flat, No Lead Package - (36-pin) 5x5 mm body (UQFN)
ML = Plastic Quad, No Lead Package - (44-pin) 8x8 mm body (QFN)
MM = Plastic Quad, No Lead Package - (28-pin) 6x6 mm body (QFN-S)
MR = Plastic Quad, No Lead Package - (64-pin) 9x9 mm body (QFN)
MV = Thin Quad, No Lead Package - (48-pin) 6x6 mm body (UQFN)
PT = Plastic Thin Quad Flatpack - (44-pin) 10x10 mm body (TQFP)
PT = Plastic Thin Quad Flatpack - (64-pin) 10x10 mm body (TQFP)
SO = Plastic Small Outline, Wide - (28-pin) 7.50 mm body (SOIC)
SP = Skinny Plastic Dual In-Line - (28-pin) 300 mil body (SPDIP)
SS = Plastic Shrink Small Outline - (28-pin) 5.30 mm body (SSOP)
TL = Very Thin Leadless Array - (36-pin) 5x5 mm body (VTLA)
TL = Very Thin Leadless Array - (44-pin) 6x6 mm body (VTLA)
Rating Symbol Min Typ Max Unit
High-Temperature Devices
Operating Junction Temperature Range TJ-40 +165 °C
Operating Ambient Temperature Range TA-40 +150 °C
Power Dissipation:
Internal Chip Power Dissipation:
PINT = VDD x (IDD IOH) PDPINT + PI/OW
I/O Pin Power Dissipation:
I/O = ({VDDVOH} x IOH) + (VOL x IOL)
Maximum Allowed Power Dissipation PDMAX (TJ – TA)/JA W
Rev G Document 9/2013 Rev A Document 11/2011 Rev H Document 02/2014 Rev B Document 4/2012 Rev (2 Document 6/2012 Rev J Document 3/2014 Rev D Document 8/2012 Rev K Document 7/2014 Rev E Document 3/2013 Rev F Document 6/2013 Rev L Document 12/2014 Rev M Document 8/2017
2011-2019 Microchip Technology Inc. DS80000533P-page 41
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
APPENDIX A: REVISION HISTORY
Rev A Document (11/2011)
Initial release of this document; issued for revision A2 silicon.
Includes silicon issues 1 (CPU), 2, (CPU) 3 (SPI),
4 (SPI), 5 (UART), 6 (Power System), 7 (ADC), 8 (PTG),
9 (Op Amp), 10 (Op Amp), 11 (PWM), 12 (Flash),
13 (QEI), 14 (QEI) and 15 (PWM).
Rev B Document (4/2012)
Updated silicon issues 9 (Op Amp), 10 (Op Amp), and
12 (Flash).
Added silicon issues 16 (ADC), 17 (ADC), 18 (Output
Compare), and 19 (CAN).
Rev C Document (6/2012)
Updated document to include all related device families
(program memory sizes of 32, 128, 256 and 512 Kbytes)
in this superfamily. In the process, revised the document
format to accommodate the different silicon revision
levels across the different families.
Added silicon issues 20, 21 and 22 (PWM), and
23 (CPU) to all device families.
Added data sheet clarification 1 (Packaging).
Rev D Document (8/2012)
Updated Table 1 to include both A2 and A3
silicon revision device IDs and removed
PIC24EP512/dsPIC32EP512 (A4). Updated all Affected
Families and Silicon Revisions tables.
Added silicon issues 24 (PWM) and 25 (PWM).
Added data sheet clarification 2 (High-Speed PWM Module).
Rev E Document (3/2013)
Adds silicon revision A2 for all 64 Kbyte devices to all
existing silicon issues, except 9 and 10 (Op Amp).
Revises issue 24 (PWM) with a figure to illustrate the
timing of the issue.
Revises issue 25 (PWM) to clarify conditions, and add
work around options.
Added new silicon issues 26 (PWM), 27 (CTMU),
28 (Input Capture), 29 (JTAG), 30 (I/O), 31 (JTAG) and
32 (QEI) to silicon revision A3 for all device families, and
revision A2 for 64 Kbyte device families only.
Updates data sheet revision level to “G”. Removes
previous data sheet clarifications, which have been
addressed in the new revision; adds new data sheet
clarification 1 (Revision History).
Rev F Document (6/2013)
Updates document to include 512 Kbytes memory. Adds
silicon issues 33 (QEI), 34 (QEI), 35 (PWM), 36 (PWM)
and 37 (Op Amp/Comparator). Revises silicon issue
15 (PWM) description. Revises silicon issue 20 (PWM)
with new figure and text. Revises issue 25 (PWM).
Removes data sheet clarification 1 (Pin Diagrams) since
this is now addressed in the current data sheet revision.
Rev G Document (9/2013)
Updates document to include revision A8 silicon.
Adds silicon issues 38-40 (PWM).
Modifies the Affected Families and Silicon Revisions
table for issue 25 (PWM) with respect to the
dsPIC33/PIC24EP512 devices. Updated Figure 1,
relevant to issue 20 (PWM).
Rev H Document (02/2014)
Updates document to include silicon revision A8 for
128-Kbyte devices. All references to “ECAN” in this
document are now changed to “CAN”.
Added silicon issue 41 (CAN).
Updated Table 2, relevant to issue 41 (CAN). Modifies
the Affected Families and Silicon Revisions table for
issue 26 (PWM) and issue 36 (PWM).
Rev J Document (3/2014)
Updates document to include silicon revision A8 for
32-Kbyte devices.
Adds data sheet clarifications 1 (Electrical
Characteristics), 2 (DC and AC Device Characteristics
Graphs), 3 (Electrical Characteristics), 4 (Electrical
Characteristics), 5 (Electrical Characteristics) and
6 (High-Temperature Electrical Characteristics).
Rev K Document (7/2014)
Updates document to add silicon revision A8 to all
256 Kbyte devices. Adds all existing silicon issues
affecting silicon revision A8 for 64 Kbyte devices to
revision A8 for 256 Kbyte devices.
Adds new silicon issues 42, 43 and 44 (PWM).
Amends silicon issue 4 (SPI) by correcting the state of
the SPIFSD bit to ‘0’. (The text of the issue is otherwise
unaffected and the issue is unchanged.)
Amends silicon issue 8 (PTG) by correcting the base
prefix of the affected commands to0b’ instead of ‘0h’.
(The text of the issue is otherwise unaffected and the
issue is unchanged.)
Amends Tab le 5 in the work around for silicon issue
36 (PWM) by deleting the row corresponding to
PCLKDIV[2:0] = 111, since this is a reserved setting.
The basic issue is unchanged.
Amends silicon issue 38 (PWM) by adding additional
text to the first paragraph to clarify the nature of the
observed glitch. The basic issue is unchanged.
Adds data sheet clarifications 7 (I/O Ports), 8 (10/12-Bit
Analog-to-Digital Converter (ADC)) and 9-10
(Comparator/Op Amp).
Rev L Document (12/2014)
Adds silicon revision A9 to dsPIC33EP256MC506.
Adds silicon issues 45 (PWM) and 46 (PWM). Adds
data sheet clarification 11 (Electrical Characteristics),
12 (High-Temperature Electrical Characteristics) and
13 (Power-Saving Features).
Rev M Document (8/2017)
Updates silicon issue 2 (CPU).
Adds silicon issue 47 (CPU).
Rev N Document 5/2018 Rev P Documenl 8/2019
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
DS80000533P-page 42 2011-2019 Microchip Technology Inc.
Rev N Document (5/2018)
Adds 36-pin UQFN package related data sheet
clarifications: 14 (Introduction), 15 (Introduction),
16 (Packaging Information), 17 (Packaging Informa-
tion), 18 (Electrical Characteristics) and 19 (Product
Identification System).
Rev P Document (8/2019)
Adds data sheet clarification 20 (High-Temperature
Electrical Characteristics).
2011-2019 Microchip Technology Inc. DS80000533P-page 43
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec,
AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,
chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,
flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,
LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,
Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,
PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,
Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,
SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA
are registered trademarks of Microchip Technology Incorporated in
the U.S.A. and other countries.
APT, ClockWorks, The Embedded Control Solutions Company,
EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,
IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision
Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire,
SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,
TimePictra, TimeProvider, Vite, WinPath, and ZL are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage
Technology, and Symmcom are registered trademarks of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany
II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2011-2019, Microchip Technology Incorporated, All Rights
Reserved.
ISBN: 978-1-5224-4899-0
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality.
6‘ MICROCHIP AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE
DS80000533P-page 44 2011-2019 Microchip Technology Inc.
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Worldwide Sales and Service
05/14/19

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