DC918 Quick Start Guide Datasheet by Analog Devices Inc.

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QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 918
16/14 BIT 40 TO 105 MSPS ADC
1
LTC2207, LTC2207-14, LTC2206, LTC2206-14, LTC2205, LTC2205-14,
LTC2204
DESCRIPTION
Demonstration circuit 918 supports members of a
family of 16/14 BIT 130 MSPS ADCs. Each assem-
bly features one of the following devices: LTC2207,
LTC2207-14, LTC2206, LTC2206-14, LTC2205,
LTC2205-14, or LTC2204 high speed, high dynamic
range ADCs.
Other members of this family include the LTC2208
16-Bit 130Msps ADC with LVDS outputs, as well as
the LTC2203 and LTC2202 which are 16-Bit 25Msps
and 10Msps single-ended clock versions. These
7x7mm QFN devices are supported by Demonstra-
tion Circuit 919 (for single-ended clock input).
Several versions of the 918C demo board support-
ing the LTC2207 16-Bit and LTC2207-14 14-Bit se-
ries of A/D converters are listed in Table 1. De-
pending on the required resolution, sample rate and
input frequency, the DC918 is supplied with the ap-
propriate ADC and with an optimized input circuit.
The circuitry on the analog inputs is optimized for
analog input frequencies below 70MHz or from
70MHz to 140MHz. For higher input frequencies,
contact the factory for support.
Design files for this circuit board are available.
Call the LTC factory.
LTC is a trademark of Linear Technology Corporation
Table 1.
DC918C Variants
DC918 VARIANTS ADC PART NUMBER RESOLUTION* MAXIMUM SAMPLE RATE INPUT FREQUENCY
918C-A LTC2207 16-Bit 105Msps 1MHz - 70MHz
918C-B LTC2207 16-Bit 105Msps 70MHz -140MHz
918C-C LTC2206 16-Bit 80Msps 1MHz - 70MHz
918C-D LTC2206 16-Bit 80Msps 70MHz -140MHz
918C-E LTC2205 16-Bit 65Msps 1MHz - 70MHz
918C-F LTC2205 16-Bit 65Msps 70MHz -140MHz
918C-G LTC2204 16-Bit 40Msps 1MHz - 70MHz
918C-H LTC2207-14 14-Bit 105Msps 1MHz - 70MHz
918C-I LTC2207-14 14-Bit 105Msps 70MHz -140MHz
918C-J LTC2206-14 14-Bit 80Msps 1MHz - 70MHz
918C-K LTC2206-14 14-Bit 80Msps 70MHz -140MHz
918C-L LTC2205-14 14-Bit 65Msps 1MHz - 70MHz
QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 918
16/14 BIT 40 TO 105 MSPS ADC
2
Table 2.
Performance Summary (T
A
= 25°C)
PARAMETER CONDITION VALUE
Supply Voltage Depending on sampling rate and the A/D converter provided,
this supply must provide up to 500mA.
Optimized for 3.3V
[3.15V 3.45V min/max]
Analog input range Depending on PGA Pin Voltage 1.5V
PP
to 2.25V
PP
Minimum Logic High 2.4V
Logic Input Voltages
Maximum Logic Low 0.8V
Minimum Logic High @ -1.6mA 2.3V (33Series terminations) Logic Output Voltage
(74VCX245 output buffer, V
cc
= 2.5V) Maximum Logic Low @ 1.6mA 0.7V (33 Series terminations)
Sampling Frequency (Convert Clock Frequency) See Table 1
Convert Clock Level 50 Source Impedance, AC coupled or ground referenced
(Convert Clock input is capacitor coupled on board and ter-
minated with 50.)
2V
P-P
2.5V
P-P
Sine Wave
or Square wave
Resolution See Table 1
Input frequency range See Table 1
SFDR See Applicable Data Sheet
SNR See Applicable Data Sheet
QUICK START PROCEDURE
Demonstration circuit 918 is easy to set up to evalu-
ate the performance of the LTC2207/LTC2207-14,
LTC2206/LTC2206-14, LTC2205/LTC2205-14,
LTC2204 A/D converters. Refer to Figure 1 for proper
measurement equipment setup and follow the proce-
dure below:
SETUP
If a DC718 QuickDAACS Data Analysis and Collection
System was supplied with the DC918 demonstration
circuit, follow the DC718 Quick Start Guide to install
the required software and for connecting the DC718 to
the DC918 and to a PC running Windows98, 2000 or
XP.
3.3V Jumpers are shown in Randomizer Not provided by D ,, , , efauit posmons (Requues change m DC718 Clock Polarity se‘ected devme in Pscope) PGA Sense Clock Out MSB Dwgnal Oulputs Io D0718 (2.5V CMOS) Analog input (50 Ohms) LSB Enable ENC dock input (50 Ohms) Figure 1. DC91B Setup (zoom for detail) LTLJUW
QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 918
16/14 BIT 40 TO 105 MSPS ADC
3
DC918DEMONSTRATION CIRCUIT BOARD JUMPERS
The DC918 demonstration circuit board
should have the following jumper set-
tings as default: (as per figure 1)
JP1: Output clock polarity: GND
JP2: SENSE: VDD, (Internal reference)
JP3: PGA: GND 2.25V range
JP4: RAND: GND Not randomized
JP5: SHDN: GND Not Shutdown
JP6: DITH: GND No internal dithering
http://wwwlineamo m/software/ L7LINEN2
QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 918
16/14 BIT 40 TO 105 MSPS ADC
4
APPLYING POWER AND SIGNALS TO THE DC918
DEMONSTRATION CIRCUIT
If a DC718 is used to acquire data from the DC918,
the DC718 must FIRST be connected to a powered
USB port or provided an external 6-9V BEFORE ap-
plying +3.3V across the pins marked +3.3V” and
“PWR GND” on the DC918. The DC918 demonstra-
tion circuit requires up to 500mA depending on the
sampling rate and the A/D converter supplied.
The DC718 data collection board is powered by the
USB cable and does not require an external power
supply unless it must be connected to the PC
through an un-powered hub in which case it must
be supplied an external 6-9V on turrets G7(+) and
G1(-) or the adjacent 2.1mm power jack.
ENCODE CLOCK
NOTE: This is not a logic compatible input. It is
terminated with 50 Ohms. Apply an encode clock
to the SMA connector on the DC918 demonstration
circuit board marked “J3 ENCODE INPUT”.
For the best noise performance, the ENCODE INPUT
must be driven with a very low jitter source. When
using a sinusoidal generator, the amplitude should
be large, up to 3V
P-P
or 13dBm. Using band pass
filters on the clock and the analog input will im-
prove the noise performance by reducing the wide-
band noise power of the signals. Datasheet FFT
plots are taken with 10 pole LC filters made by TTE
(Los Angeles, CA) to suppress signal generator
harmonics, non-harmonically related spurs and
broad band noise. Low phase noise Agilent 8644B
generators are used with TTE band pass filters for
both the Clock input and the Analog input.
Apply the analog input signal of interest to the SMA
connectors on the DC918 demonstration circuit
board marked “J2 ANALOG INPUT”. These inputs
are capacitive coupled to Balun transformers ETC1-
1-13, or directly coupled through Flux coupled
transformers ETC1-1T.
An internally generated conversion clock output is
available on pin 3 of J1 and the data samples are
available on Pins 7-37 for 16-Bits (or 7-33 for 14-
Bits) of J1 which can be collected via a logic ana-
lyzer, cabled to a development system through a
SHORT 2 to 4 inch long 40-pin ribbon cable or col-
lected by the DC718 QuickEval-II Data Acquisition
Board using the
PScope System Software
provided
or down loaded from the Linear Technology website
at http://www.linear.com/software/. If a DC718 was
provided, follow the DC718 Quick Start Guide and
the instructions below.
To start the data collection software if
PScope.exe
”, is installed (by default) in
\Program Files\LTC\PScope\, double click the
PScope Icon or bring up the run window under the
start menu and browse to the PScope directory and
select PScope.
If the DC918 demonstration circuit is properly con-
nected to the DC718, PSCOPE should automatically
detect the DC918, and configure itself accordingly.
If necessary the procedure below explains how to
manually configure PSCOPE.
Configure PScope for the appropriate variant of the
DC918 demonstration circuit by selecting the cor-
rect A/D Converter as installed on the DC918. Un-
der the “Configure” menu, go to “Device.” Under
the “Device” pull down menu, select device, either
LTC2207, LTC2207-14, LTC2206, LTC2206-14,
LTC2205, LTC2205-14, or LTC2204. Select the part
in the Device List and PScope will automatically
blank the last two LSBs when using a DC918 sup-
plied with a 14-Bit part. You may also manually
configure Pscope as follows:
User configure
16-Bit (or 14-Bit if using -14 versions)
Alignment: Left-16
Bipolar (2’s complement)
QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 918
16/14 BIT 40 TO 105 MSPS ADC
5
Positive clock edge
Type: CMOS
If everything is hooked up properly, powered and a
suitable convert clock is present, clicking the “Col-
lect” button should result in time and frequency
plots displayed in the PScope window. Additional
information and help for
PScope
is available in the
DC718 Quick Start Guide and in the online help
available within the
PScope
program itself.
ANALOG INPUT NETWORK
For optimal distortion and noise performance the
RC network on the analog inputs should be opti-
mized for different analog input frequencies. For
input frequencies below 70MHz a capacitor with the
value of 4.7pF should be used for C5. For input fre-
quencies from 70MHz to 140MHz a capacitor with
the value of 8.2pF should be used for C5. These
two input networks cover a broad bandwidth and
are not optimized for operation at a specific input
frequency. For input frequencies less than 5MHz, or
greater than 150MHz, other input networks may be
more appropriate.
In almost all cases, filters will be required on both
analog input and encode clock to provide data sheet
SNR.
Narrow band high Q filters may produce poor re-
sults with preliminary silicon. 10% band-pass
would be preferred over 5% band-pass on the ana-
log input, although narrow band filters can be used
on the clock input. The filters should be located
close to the inputs to avoid reflections from imped-
ance discontinuities at the driven end of a long
transmission line. Most filters do not present 50
ohms outside the passband.
In some cases, 3-10dB pads may be required to
obtain low distortion.
If your generator cannot deliver full-scale signals
without distortion, you may benefit from a medium
power amplifier based on a Gallium Arsenide Gain
block prior to the final filter. This is particularly true
at higher frequencies where IC based operational
amplifiers may be unable to deliver the combination
of low noise figure and High IP3 point required. A
high order filter can be used prior to this final am-
plifier, and a relatively lower Q filter used between
the amplifier and the demo circuit.
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QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 918
16/14 BIT 40 TO 105 MSPS ADC
6

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