www.wiznet.co.kr
WIZ812MJ Datasheet
(Ver. 1.2)
© 2013 WIZnet Co., Ltd. All Rights Reserved.
For more information, visit our website at www.wiznet.co.kr
WIZnet
WIZ812MJ Datasheet
© Copyright 2013 WIZnet Co., Ltd. All rights reserved
2
TOP
W
WI
IZ
Z8
8
1
10
0M
M
J
J
D
Da
at
ta
a
s
sh
he
ee
e
t
t
Document History Information
Revision
Data
Description
Ver. 1.0
September 17, 2008
Release with WIZ812MJ Launching
Ver. 1.1
January 28, 2009
Added temperature specification
Ver. 1.2
January 28, 2013
Hardware revision(Rev1.1)
Changed operation temperature range, partlist and
schematic
I WIZnet www.wiznet.co.kr)
WIZ812MJ Datasheet
© Copyright 2013 WIZnet Co., Ltd. All rights reserved
3
TOP
W
WI
IZ
Z8
8
1
10
0M
M
J
J
D
Da
at
ta
a
s
sh
he
ee
e
t
t
WIZnets Online Technical Support
If you have something to ask about WIZnet Products, Write down your question
on Q&A Board in WIZnet website (www.wiznet.co.kr). WIZnet Engineer will give an
answer as soon as possible.
I WIZnet Table of Contents
WIZ812MJ Datasheet
© Copyright 2013 WIZnet Co., Ltd. All rights reserved
4
TOP
W
WI
IZ
Z8
8
1
10
0M
M
J
J
D
Da
at
ta
a
s
sh
he
ee
e
t
t
Table of Contents
1. Introduction .............................................................................. 5
1.1. Features ............................................................................. 5
1.2. Block Diagram ...................................................................... 5
1.3. Difference between WIZ811MJ and WIZ812MJ .............................. 6
2. Pin Assignments & descriptions ................................................... 7
2.1. Pin Assignments ................................................................... 7
2.2. Power & Ground ................................................................... 8
2.3. MCU Interfaces ..................................................................... 8
2.4. Miscellaneous Signals ............................................................ 9
3. Timing Diagrams ..................................................................... 10
3.1. Reset Timing .................................................................... 10
3.2. Register/Memory READ Timing ............................................... 10
3.3. Register/Memory WRITE Timing .............................................. 11
3.4. SPI Timing......................................................................... 11
4. Dimensions ............................................................................. 12
5. Schematic .............................................................................. 13
6. Partlist ................................................................................... 14
I WIZnet Block Diagram WIZB12MJ
WIZ812MJ Datasheet
© Copyright 2013 WIZnet Co., Ltd. All rights reserved
5
TOP
W
WI
IZ
Z8
8
1
10
0M
M
J
J
D
Da
at
ta
a
s
sh
he
ee
e
t
t
1. Introduction
WIZ812MJ is the network module that includes W5100 (TCP/IP hardwired chip, include PHY),
MAG-JACK (RJ45 with X’FMR) with other glue logics. It can be used as a component and no
effort is required to interface W5100 and Transformer. The WIZ812MJ is an ideal option for users
who want to develop their Internet enabling systems rapidly.
For the detailed information on implementation of Hardware TCP/IP, refer to the W5100
Datasheet.
WIZ812MJ consists of W5100 and MAG-JACK.
TCP/IP, MAC protocol layer: W5100
Physical layer: Included in W5100
Connector: MAG-JACK(RJ45 with Transformer)
1.1. Features
Supports 10/100 Base TX
Supports half/full duplex operation
Supports auto-negotiation and auto cross-over detection
IEEE 802.3/802.3u Compliance
Operates 3.3V with 5V I/O signal tolerance
Supports network status indicator LEDs
Includes Hardware Internet protocols: TCP, IP Ver.4, UDP, ICMP, ARP, PPPoE, IGMP
Includes Hardware Ethernet protocols: DLC, MAC
Supports 4 independent connections simultaneously
Supports MCU bus Interface and SPI Interface
Supports Direct/Indirect mode bus access
Supports Socket API for easy application programming
Interfaces with two 2.54mm pitch 2 x 10 header pin
Temperature :
[PCB rev1.0] : 0 ~ 70 (Operation), -40 ~ 85 (Storage)
[PCB rev1.1] : -40 ~ 85 (Operation), -40 ~ 85 (Storage)
1.2. Block Diagram
WIZnet
WIZ812MJ Datasheet
© Copyright 2013 WIZnet Co., Ltd. All rights reserved
6
TOP
W
WI
IZ
Z8
8
1
10
0M
M
J
J
D
Da
at
ta
a
s
sh
he
ee
e
t
t
1.3. Difference between WIZ811MJ and WIZ812MJ
WIZ811MJ
WIZ812MJ
Two 2.54mm pitch 10x2 header
The same pin-header is mounted
but pin description is different
J2:9 GND -> RX_LED
J2:10 GND -> TX_LED
J2:19 GND -> /LINKLED
Two PCB Through Hole(Ø 3.00mm)
Four PCB Through Hole(Ø 3.00mm)
55.5 x 25 x 23.5mm (W x H x D)
The same size
LINKLED : Active low in link state indicates a
good status for 10/100M.
It is always ON when the link is OK and it flashes
while in a TX or RX state.
/LINKLED : Active low in link state indicates a
good status for 10/100M.
It is always ON when the link is OK.
It does not flashes while in a TX or RX state.
ACT_LED : Active low in active state indicates a
good status for 10/100M.
It is always ON when the link is OK and it flashes
while in a TX or RX state.
mZnet 0000000IUWIZnet 00000000 H “2 50 L .411 ”1 OI!IIIIIII!IIIIIIIIL|U JEEK 0 O 0 O m ' c a 4 rillllllllllllllillllzgzogl—l ® Y1 + O O 0 O 0 0 0 0 0 0 I 1 WIZBIZHJ 0 ......a REV1.0 J1 J2 MUSI ‘ I . 3 msn avaD 1 I . 2 [RESET [)1 3 . . a on SELK 3 . . : ISES D3 5 . . a D2 MR 5 . . 5 [RD D5 7 . . a 04 [ES 2 . . 5 [INT D7 9 . . ‘0 m; n><_led s="" .="" .="" 1o="" tx7led="" end="" u="" .="" .="" 12="" 3vao="" au="" n="" .="" .="" 12="" al="" a8="" ‘3="" .="" .="" ia="" a9="" a2="" 13="" .="" .="" n="" a3="" a10="" ‘5="" .="" .="" 16="" a11="" a4="" :5="" .="" .="" 16="" a5="" a12="" w="" .="" .="" 15="" a13="" ali="" x7="" .="" .15="" a7="" a14="" ‘9="" .="" .="" 20="" m:="" ilinkled="" v.2="" .="" .="" 20="" gnd="">
WIZ812MJ Datasheet
© Copyright 2013 WIZnet Co., Ltd. All rights reserved
7
TOP
W
WI
IZ
Z8
8
1
10
0M
M
J
J
D
Da
at
ta
a
s
sh
he
ee
e
t
t
2. Pin Assignments & descriptions
2.1. Pin Assignments
(V-V}Znet
WIZ812MJ Datasheet
© Copyright 2013 WIZnet Co., Ltd. All rights reserved
8
TOP
W
WI
IZ
Z8
8
1
10
0M
M
J
J
D
Da
at
ta
a
s
sh
he
ee
e
t
t
I : Input O : Output
I/O : Bi-directional Input and output P : Power
2.2. Power & Ground
Symbol
Type
Pin No.
Description
3V3D
P
J1:12 , J2:1
Power : 3.3 V power supply
GND
P
J1:11, J2:20
Ground
2.3. MCU Interfaces
Symbol
Type
Pin No.
Description
SCLK
I
J2:3
SCLK(Serial Clock)
This pin is used to SPI Clock Signal pin.
/SCS
I
J2:4
/SCS (Slave Select) *
This pin is used to SPI Slave Select signal Pin.
This pin controls SPI_EN signal of W5100. When
/SCS signal assert low, W5100 drive SPI mode by
SPI_EN signal toggled high.
MOSI
I
J1:1
MOSI (Master Out Slave In) *
This pin is used to SPI MOSI signal pin.
MISO
I/O
J1:2
MISO (Master In Slave Out) *
This pin is used to SPI MISO signal pin.
A14~A8
I
J1:13 ~ J1:19
Address
Used as Address[14-8] pin
A7~A0
I
J2:11 ~ J2:18
Address
Used as Address[7-0] pin
D7~D0
I/O
J1:3 ~ J1:10
Data
8 bit-wide data bus
/CS
I
J2:7
Module Select : Active low.
/CS of W5100
/RD
I
J2:6
Read Enable : Active low.
/RD of W5100
/WR
I
J2:5
Write Enable : Active low
/WR of W5100
/INT
O
J2:8
Interrupt : Active low
After reception or transmission it indicates that the
W5100 requires MCU attention.
By writing values to the Interrupt Status Register
of W5100 the interrupt will be cleared.
All interrupts can be masked by writing values to
the IMR of W5100 (Interrupt Mask Register).
For more details refer to the W5100 Datasheet
WIZHCI‘
WIZ812MJ Datasheet
© Copyright 2013 WIZnet Co., Ltd. All rights reserved
9
TOP
W
WI
IZ
Z8
8
1
10
0M
M
J
J
D
Da
at
ta
a
s
sh
he
ee
e
t
t
2.4. Miscellaneous Signals
Symbol
Type
Pin No.
Description
/RESET
I
J2:2
Reset : This pin is active low input to
initialize or re-initialize W5100.
By asserting this pin low for at least 2us,
all internal registers will be re-initialized
to their default states.
RX_LED
O
J2:9
RX_LED : Receive activity LED
Active low indicates the presence of
receiving activity.
TX_LED
O
J2:10
TX_LED : Transmit activity LED
Active low indicates the presence of
transmitting activity.
/LINKLED
O
J2:19
LINKLED : Active low in link state
indicates a good status for 10/100M.
It is always ON when the link is OK.
It does not flashes while in a TX or RX
state.
NC
-
J1 : 20
Not Connect
WIZnet 1. Reset Tim_ing 1 RESET PLOCK lmtema‘) i Valvd data
WIZ812MJ Datasheet
© Copyright 2013 WIZnet Co., Ltd. All rights reserved
10
TOP
W
WI
IZ
Z8
8
1
10
0M
M
J
J
D
Da
at
ta
a
s
sh
he
ee
e
t
t
3. Timing Diagrams
WIZ812MJ provides following interfaces of W5100.
-. Direct/Indirect mode bus access
-. SPI access
3.1. Reset Timing
Description
Min
Max
1
Reset Cycle Time
2 us
-
2
/RESET to internal PLOCK
-
10 ms
3.2. Register/Memory READ Timing
Description
Min
Max
1
Read Cycle Time
80 ns
-
2
Valid Address to /CS low time
8 ns
-
3
/CS low to /RD low time
-
1 ns
4
/RD high to /CS high time
-
1 ns
5
/RD low to Valid Data Output time
-
80 ns
6
/RD high to Data High-Z Output time
-
1 ns
Address SCLK (MODEOJ Same MosI/w so MOS‘ Mrso “a
WIZ812MJ Datasheet
© Copyright 2013 WIZnet Co., Ltd. All rights reserved
11
TOP
W
WI
IZ
Z8
8
1
10
0M
M
J
J
D
Da
at
ta
a
s
sh
he
ee
e
t
t
3.3. Register/Memory WRITE Timing
Description
Min
Max
1
Write Cycle Time
70 ns
-
2
Valid Address to /CS low time
7 ns
-
3
/CS low to /WR high time
70 ns
-
4
/CS low to /WR low time
-
1 ns
5
/WR high to /CS high time
-
1 ns
6
/WR low to Valid Data time
-
14 ns
3.4. SPI Timing
Description
Mode
Min
Max
1 /SS low to SCLK
Slave
21 ns
-
2 Input setup time
Slave
7 ns
-
3 Input hold time
Slave
28 ns
-
4 Output setup time
Slave
7 ns
14 ns
5 Output hold time
Slave
21 ns
-
6 SCLK time
Slave
70 ns
I WIZHCI‘ ulzsxzm nzvm :‘I _| 4— . I
WIZ812MJ Datasheet
© Copyright 2013 WIZnet Co., Ltd. All rights reserved
12
TOP
W
WI
IZ
Z8
8
1
10
0M
M
J
J
D
Da
at
ta
a
s
sh
he
ee
e
t
t
4. Dimensions
Symbols
Dimensions (mm)
A
25.00
B
22.86
C
17.00
D
3.00
E
4.00
F
52.00
G
3.20
H
33.02
I
9.00
J
2.54
K
2.54
L
15.90
M
13.50
N
6.00
I @Znet
WIZ812MJ Datasheet
© Copyright 2013 WIZnet Co., Ltd. All rights reserved
13
TOP
W
WI
IZ
Z8
8
1
10
0M
M
J
J
D
Da
at
ta
a
s
sh
he
ee
e
t
t
5. Schematic
C22
10uF/16V
C21
3.3uF/16V C23
10uF/16V
1V8_OUT
C25
0.1uF
C24
0.1uF
R11
4.7K
1V8D
C26
0.1uF C27
0.1uF
3V3D
C29
0.1uF
C28
0.1uF
/SCS
D5
D4
D3
D2
CHGND
D7
1V8D
XTLP
D6
R1
1M
C2 15pF
Y1
25MHz (SMD)
C1 15pF
XTLP
R6
12K (1%)
R7
300 (1%)
XTLN
3V3D
XTLN
VCC
RSET_BG
/LINKLED
ACT_LED
1V8D
1V8D
3V3A
3V3D
1V8D
RXIP
1V8D
/RESET
C12
0.1uF
3V3D
RXIN
R2
49.9
R3
49.9
C3
0.1uF
C4
0.1uF
R8
49.9
R9
49.9
TXOP
C5
0.1uF
R5
200
R4
200
SPI_EN
TXON
C13
0.1uF
SCLK
C14
0.1uF
1V8A
MOSI
/SCS
C6 0.1uF
C10 0.1uF
CHGND
CHGND
/WR
/RD
MISO
/CS
/INT
1V8A A2
A1
A0
A4
A3
A5
A7
A6
TXOP
RXIP
A8
RXIN
TXON
U1
W5100
RSET_BG
1
VCC3V3A
2
NC
3
GNDA
4
RXIP
5
RXIN
6
VCC1V8A
7
TXOP
8
TXON
9
GNDA
10
1V8_OUT
11
VCC3V3D
12
GNDD
13
GNDD
14
VCC1V8D
15
VCC1V8D
16
GNDD
17
VCC3V3D
18
DATA7
19
DATA6
20
DATA5
21
DATA4
22
DATA3
23
DATA2
24
DATA1
25
DATA0
26
MISO
27
MOSI
28
/SCS
29
SCLK
30
SEN
31
GNDD
32
VCC1V8D
33
TEST_MODE3
34
TEST_MODE2
35
TEST_MODE1
36
TEST_MODE0
37
ADDR14
38
ADDR13
39
ADDR12
40
ADDR11 41
ADDR10 42
GNDD 43
VCC3V3D 44
ADDR9 45
ADDR8 46
ADDR7 47
ADDR6 48
ADDR5 49
ADDR4 50
ADDR3 51
ADDR2 52
ADDR1 53
ADDR0 54
/CS 55
/INT 56
/WR 57
/RD 58
/RESET 59
NC 60
NC 61
NC 62
OPMODE0 63
OPMODE1 64
OPMODE2 65
LINKLED 66
SPDLED 67
GNDD 68
VCC1V8D 69
FDXLED 70
COLLED 71
RXLED 72
TXLED 73
VCC1V8A 74
XTLN 75
XTLP 76
GNDA 77
NC 78
NC 79
NC 80
A9
U2
BS-RB10005
TD+
1
TD-
2
TCT
3
NC1
4
NC2
5
NC3
6
RD+
7
RD-
8
L1+
12 L2-
11
L3+
10 L4-
9
CH_GND1
13
CH_GND2
14
3V3D
1V8_OUT
LINK_LED
A10
3V3A
3V3D
A13
A12
A11
A14
FB2 1uH 1V8A
C11
10uF/16V C7
10uF/16V
C9
0.01uF
FB1 1uH
3V3D
1V8A
3V3A
D1
D0
U5
SN74LVC1G79DCK
D
1
CLK
2GND 3
Q4
VCC 5
TX_LED
C19
0.1uF
RX_LED
/LINKLED
3V3D
J1
HEADER 10X2 2.54 Pitch
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
J2
HEADER 10X2 2.54 Pitch
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
C18
0.1uF
MOSI
D3
D5
D7
MISO
D2
D4
D6
GH4
CON8
1
2
3
4
5
6
7
8
CHGND
GH5
CON8
1
2
3
4
5
6
7
8
CHGND
D0
GH3
CON1
1
GH1
CON8
1
2
3
4
5
6
7
8
3V3D
CHGND
U6
SN74LVC1G32DCK
A
1
B
2GND 3
Y4
VCC 5
U7
SN74LVC2G08DCT
1A
1
1B
2
2Y 3
GND 4
2A
5
2B
6
1Y 7
VCC 8
SPI_EN
GH2
CON8
1
2
3
4
5
6
7
8
CHGND
/RESET
/INT
/RD
/CS
/WR
SCLK
TX_LED
A0 A1
/SCS
A2
/LINKLED
U4
SN74LVC2G14DCK
1A
1
GND 2
2A
32Y 4
VCC 5
1Y 6
A4
A6
A3
A5
RX_LED
A7
3V3D
C17
0.1uF
A8 A9
A10 A11
A12 A13
D1
A14
3V3D
C20
0.1uF
3V3D
3V3D
RX_LED
Title
Size Document Number Rev
Date: Sheet of
<Doc> 1.1
WIZ812MJ
A3
1 1Thursday, October 04, 2012
LINK_LED ACT_LED
TX_LED
I mZnet STRAIGHT Header
WIZ812MJ Datasheet
© Copyright 2013 WIZnet Co., Ltd. All rights reserved
14
TOP
W
WI
IZ
Z8
8
1
10
0M
M
J
J
D
Da
at
ta
a
s
sh
he
ee
e
t
t
6. Partlist
Item
Q.ty
Reference
Part
Tech. Characteristics
Package
1
2
C1,C2
15pF
50V-20% Ceramic
CASE 0603
2
18
C3,C4,C5,C6,C10,
C12,C13,C14,C17,
C18,C19,C20,C24,
C25,C26,C27,C28,
C29
0.1uF
50V-20% Ceramic
CASE 0603
3
4
C7,C11,C22,C23
10uF/16V
16Vmin 10%
EIA/IECQ 3216
4
1
C21
3.3uF/16V
16Vmin 10%
EIA/IECQ 3216
5
1
C9
0.01uF
50V-20% Ceramic
CASE 0603
6
2
FB1,FB2
1uH Ferrite Inductor
CASE 0805
7
2
J1,J2
2X10 2.54mm DIP
STRAIGHT Header
2 X 10 2.54mm pitch
8
1
R1
1M
1/10W-5% SMD
CASE 0603
9
4
R2,R3,R8,R9
49.9 (1%)
1/10W-1% SMD
CASE 0603
10
2
R4,R5
200
1/10W-5% SMD
CASE 0603
11
1
R6
12K (1%)
1/10W-1% SMD
CASE 0603
12
1
R7
300 (1%)
1/10W-1% SMD
CASE 0603
13
1
R11
4.7K
1/10W-5% SMD
CASE 0603
14
1
U1
W5100
WIZnet Hardware TCP/IP
LQFP80
15
1
U2
BS-RB10005
Transformer + RJ45
16
1
U4
SN74LVC2G14DCK
Dual Inverting Buffer
SC70-6
17
1
U5
SN74LVC1G79DCK
D-type Flip Flop (vendor : TI)
SC70-5
18
1
U6
SN74LVC1G32DCK
OR-Gate (vendor : TI)
SC70-5
19
1
U7
SN74LVC2G08DCT
Dual AND-Gate (vendor : TI)
SM8
20
1
Y1
25MHz (SMD)
SMD Type, Industrial
SX-1
21
1
PCB REV1.1
FR4, 1.6T, 4Layer

Products related to this Datasheet

CNTRLR ETHERNET 10/100 BASE-T/TX