VL-MM7-1SBN (VL47B2863A-F8SE) Datasheet by VersaLogic Corporation

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V Virtium Order Information: VL4 F8 3 E x DRAM MANUFACIURER MODULE SPEED WWW.
Product Specifications
PART NO.:
VL47B2863A-F8SE
REV: 1.0
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA www.virtium.com 1
General Information
1GB 128Mx64 DDR3 SDRAM NON-ECC UNBUFFERED SODIMM 204-PIN
Description
The VL47B2863A is a 128Mx64 DDR3 SDRAM high density SODIMM. This single rank memory module consists of
eight CMOS 128Mx8 bits with 8 banks DDR3 Synchronous DRAMs in BGA packages and a 2K EEPROM with
thermal sensor in an 8-pin MLF package. This module is a 204-pin small-outline dual in-line memory module and is
intended for mounting into an edge connector socket. Decoupling capacitors are mounted on the printed circuit board
for each DDR3 SDRAM.
Features
Pin Description
204-pin, small-outline dual in-line memory module (SODIMM)
Fast data transfer rate: PC3-8500
VDD = VDDQ = 1.5V +/-0.075V
JEDEC standard 1.5V +/-0.075V I/O (SSTL_15 compatible)
VDDSPD = 3.0V to 3.6V
Eight internal component banks for concurrent operation
8-bit pre-fetch architecture
Bi-directional differential data-strobe
Nominal and dynamic on-die termination (ODT)
ZQ calibration support
Programmable CAS# latency: 7 (DDR3-1066)
Programmable burst; length (8)
Average refresh period 7.8 us
Asynchronous reset
Fly-by topology
On board terminated command, address, and control bus
Serial presence detect (SPD) EEPROM with thermal sensor
Thermal sensor range: -40oC to +125oC (Max +/-3oC accuracy)
JEDEC pinout
Gold edge contacts
Lead-free, RoHS compliant
PCB: Height 30.00mm (1.181”), double sided component
Operating temperature (TOPER): - Commercial (0oC <= Tc <= 95oC)
- Industrial (-40oC <= Tc <= 95oC)
Notes: Double refresh rate is required when 85oC < TOPER <= 95oC.
TOPER is DRAM case temperature (Tc)
Pin Name
A0~A13
A10/AP
A12/BC#
BA0~BA2
DQ0~DQ63
DQS0~DQS7
DQS0#~DQS7#
DM0~DM7
CK0, CK0#
ODT0
CKE0
CS0#
RAS#
CAS#
WE#
RESET#
VDD
VSS
SA0~SA1
SDA
SCL
EVENT#
VREFCA
VREFDQ
VDDSPD
VTT
NC
Order Information:
VL47B2863A- F8 S E-X
OPERATING TEMPERATURE
None: Commercial
S1: Industrial screening
DRAM DIE
E-DIE
DRAM MANUFACTURER
S - SAMSUNG
MODULE SPEED
F8: PC3-8500 @ CL7
VL: Lead-free/RoHS
Dram component: Samsung K4B1G0846E-BCH9
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Product Specifications
PART NO.:
VL47B2863A-F8SE
REV: 1.0
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA www.virtium.com 2
Pin Configuration
204-PIN DDR3 SODIMM FRONT
204-PIN DDR3 SODIMM BACK
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
1
VREFDQ
53
DQ19
105
VDD
157
DQ42
2
VSS
54
VSS
106
VDD
158
DQ46
3
VSS
55
VSS
107
A10
159
DQ43
4
DQ4
56
DQ28
108
BA1
160
DQ47
5
DQ0
57
DQ24
109
BA0
161
VSS
6
DQ5
58
DQ29
110
RAS#
162
VSS
7
DQ1
59
DQ25
111
VDD
163
DQ48
8
VSS
60
VSS
112
VDD
164
DQ52
9
VSS
61
VSS
113
WE#
165
DQ49
10
DQS0#
62
DQS3#
114
CS0#
166
DQ53
11
DM0
63
DM3
115
CAS#
167
VSS
12
DQS0
64
DQS3
116
ODT0
168
VSS
13
VSS
65
VSS
117
VDD
169
DQS6#
14
VSS
66
VSS
118
VDD
170
DM6
15
DQ2
67
DQ26
119
A13
171
DQS6
16
DQ6
68
DQ30
120
ODT1*
172
VSS
17
DQ3
69
DQ27
121
CS1#*
173
VSS
18
DQ7
70
DQ31
122
NC
174
DQ54
19
VSS
71
VSS
123
VDD
175
DQ50
20
VSS
72
VSS
124
VDD
176
DQ55
21
DQ8
73
CKE0
125
NC
177
DQ51
22
DQ12
74
CKE1*
126
VREFCA
178
VSS
23
DQ9
75
VDD
127
VSS
179
VSS
24
DQ13
76
VDD
128
VSS
180
DQ60
25
VSS
77
NC
129
DQ32
181
DQ56
26
VSS
78
A15 *
130
DQ36
182
DQ61
27
DQS1#
79
BA2
131
DQ33
183
DQ57
28
DM1
80
A14 *
132
DQ37
184
VSS
29
DQS1
81
VDD
133
VSS
185
VSS
30
RESET#
82
VDD
134
VSS
186
DQS7#
31
VSS
83
A12
135
DQS4#
187
DM7
32
VSS
84
A11
136
DM4
188
DQS7
33
DQ10
85
A9
137
DQS4
189
VSS
34
DQ14
86
A7
138
VSS
190
VSS
35
DQ11
87
VDD
139
VSS
191
DQ58
36
DQ15
88
VDD
140
DQ38
192
DQ62
37
VSS
89
A8
141
DQ34
193
DQ59
38
VSS
90
A6
142
DQ39
194
DQ63
39
DQ16
91
A5
143
DQ35
195
VSS
40
DQ20
92
A4
144
VSS
196
VSS
41
DQ17
93
VDD
145
VSS
197
SA0
42
DQ21
94
VDD
146
DQ44
198
EVENT#
43
VSS
95
A3
147
DQ40
199
VDDSPD
44
VSS
96
A2
148
DQ45
200
SDA
45
DQS2#
97
A1
149
DQ41
201
SA1
46
DM2
98
A0
150
VSS
202
SCL
47
DQS2
99
VDD
151
VSS
203
VTT
48
VSS
100
VDD
152
DQS5#
204
VTT
49
VSS
101
CK0
153
DM5
50
DQ22
102
CK1*
154
DQS5
51
DQ18
103
CK0#
155
VSS
52
DQ23
104
CK1#*
156
VSS
*: These pins are not used in this module.
has nos. w Duo jl pm pm % w WWW.
Product Specifications
PART NO.:
VL47B2863A-F8SE
REV: 1.0
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA www.virtium.com 3
Function Block Diagram
0.1uF
DQ1
DQS
DQ46
CK0
D0
DQS
DQ3
SCL
CS#
DQ63
DQS2#
DQ0
ZQ
DQ18
DQ48
BA0-BA2: SDRAMs D0-D7
DQS0#
DQ2
DQ4
CKE0: SDRAMs D0-D7
VREFCA
CS#
DQ4
SDA
D1
DQ40
DM2
DQS#
ZQ
DQ19 DQ50
RESET#
VDDSPD
DQ3
DQ2
CK0#
VTT
DQ6
DQS
SA1
DQ1
DQ52
DQS3#
DQ6
ZQ
DQ23
DQ57
RESET#: SDRAMs D0-D7
DQS4
DQ4
D2
D0-D7
D0-D7
DQ5
CS#
w ith integrated thermal sensor
DQS
DQ53
DM3
CS#
ZQ
DQ22
DQ35
D0-D7
Serial PD/
Thermal sensor
DQ5
DQ5
CKE0
39 ohm +/-5%
DQ2
DQ6
EVENT#
DQ5
DQ58
DQS3
ZQ
DQ7 ZQ
DQ17
DQ34
D0-D7
VTT
DQ6
DQ3
WE#: SDRAMs D0-D7
DQS0
DQ0
DQ5
A1
DM
DQ42
DQS5#
ZQ
DM
CS#
ZQ
DQ21
DQ37
D0-D7
CS0#
DQ7
DQ1
CAS#: SDRAMs D0-D7
VREFDQ
DQ1
DQ2
Vss
DQ3 DQ43
DQS5
Vss
DQS
DQ6
DQ20
DQ33
D0-D7
DQ0
DQ8
DQ0
CAS#
CK0
D5
DQ0
A0
DQ0
DQ51
DM5
Vss
DQS4#
DQ4
DQ5
DQ2
DQ24
DQ39
DQS#
DQ10
DQS#
RAS#: SDRAMs D0-D7
CS#
DQS#
DQ1
A2
DQ4
DQ59
DQS6
Vss
DM4
DQ2
DQ2
DQ3
DQ26
DQ32
DQS
DQ0
DQ9
DQ6
A0-A13
VDD
DQ7
D7
Serial PD
DQ2
DQ47
DQS6#
Vss
DM0
D4
DQ0
DQ4
DQ27
DQ38
DQ4
DQ1
DQ15
CS#
ODT0: SDRAMs D0-D7
Command, address, control, and clock line terminations
DM
DQS#
EVENT#
DQ7
DQ62
DM6
Vss
CK0#
DQ5
DQ1
DQ5
DQ31
DQ36
DQ2
DQ14
DQ41
DQ7
A0-A13: SDRAMs D0-D7
VSS
DQ3
DQ7
DQ6 DQ54
DQS7 Vss
DM
DQ3
D6
DQ6
DQ30
DQS1
D3
DQ12
DQ60
DM
WE#
36 ohm +/-5%
DQ4
DM
CS#
DQ49
DM7
Vss
A0-A13, BA0-BA2
RAS#, CAS#, WE#,
CS0#, CKE0, ODT0
DQ1
DQS#
DQ7
DQ25
DQS1#
DQ5
2. ZQ resistors are 240 ohms +/-1%
DQ11
DQ45
RAS#
DDR3
SDRAM
DQS
DQ3
DQ7 DQ55
DQS7#
Vss
DDR3
SDRAM
DQ0
DQ7
DQ6
DQ29
DM1
DQ3
1. Unless otherw ise noted, resistor values are 15 ohms +/-5%
DQ13
DQ56
BA0-BA2
DQS
DQ4
DM
DQ61
ODT0
VDD
DQS#
DM
SA0
DQS#
DQ28
DQS2
DQ1
Notes:
DQ16
DQ44
3.3pF
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Product Specifications
PART NO.:
VL47B2863A-F8SE
REV: 1.0
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA www.virtium.com 4
Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
VDD
Voltage on VDD pin relative to VSS
-0.4
1.975
V
VDDQ
Voltage on VDDQ pin relative to VSS
-0.4
1.975
V
VIN, VOUT
Voltage on any pin relative to VSS
-0.4
1.975
V
TSTG
Storage temperature
-55
100
0C
IL
Input leakage current; Any input 0V<VIN<VDD;
VREF input 0V<VIN<0.95V;
Other pins not under test = 0V
Address, RAS#,
CAS#, WE#, BA
-16
16
uA
CS#, CKE, ODT,
CK, CK#
-16
16
uA
DM
-2
2
uA
IOZ
Output leakage current;
0V<VOUT<VDDQ; DQs and ODT are disabled
DQ, DQS, DQS#
-5
5
uA
IVREF
VREF supply leakage current; VREF = Valid VREF level
-8
8
uA
DC Operating Conditions
Symbol
Parameter
Min
Typical
Max
Unit
Notes
VDD
Supply Voltage
1.425
1.5
1.575
V
1,2
VDDQ
I/O Supply Voltage
1.425
1.5
1.575
V
1,2
VREFDQ (DC)
I/O reference voltage DQ bus
0.49 x VDD
0.5 x VDD
0.51 x VDD
V
3,4
VREFCA (DC)
Input reference voltage CMD/ADD bus
0.49 x VDD
0.5 x VDD
0.51 x VDD
V
3,4
VTT
Termination Reference Voltage
-0.483 x VDDQ
0.5 x VDDQ
+0.517 x VDDQ
V
5
Notes:
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
3. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than +/-1% VDD
4. For reference: approximate VDD/2 +/-15mV.
5. VTT termination voltage in excess of stated limit will adversely affect the command and address signals voltage margin and will reduce
timing margins.
Operating Temperature Condition
Symbol
Parameter
Rating
Units
Notes
TOPER
Operating temperature
Commercial
0 to 95
0C
1,2
Industrial
-40 to +95
Notes:
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer
to JEDEC JESD51-2.
2. At -40 to +85oC, operation temperature range, all DRAM specifications will be supported. The refresh rate is required to double when
85oC < TOPER <= 95oC.
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Product Specifications
PART NO.:
VL47B2863A-F8SE
REV: 1.0
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA www.virtium.com 5
Input DC Logic Level
All voltages referenced to VSS
Symbol
Parameter
Min
Max
Unit
Command and Address
VIHCA(DC)
Input High (Logic 1) Voltage
VREF + 0.100
VDD
V
VILCA(DC)
Input Low (Logic 0) Voltage
VSS
VREF - 0.100
V
DQ and DM
VIHDQ(DC)
Input High (Logic 1) Voltage
VREF + 0.100
VDD
V
VILDQ(DC)
Input Low (Logic 0) Voltage
VSS
VREF - 0.100
V
Input AC Logic Level
All voltages referenced to VSS
Symbol
Parameter
Min
Max
Unit
Command and Address
VIHCA(AC)
Input High (Logic 1) Voltage
VREF + 0.175
-
V
VILCA(AC)
Input Low (Logic 0) Voltage
-
VREF - 0.175
V
DQ and DM
VIHDQ(AC)
Input High (Logic 1) Voltage
VREF + 0.175
-
V
VILDQ(AC)
Input Low (Logic 0) Voltage
-
VREF - 0.175
V
Input/Output Capacitance
TA=250C, f=100MHz
Parameter
Symbol
F8
(DDR3-1066)
Unit
Min
Max
Input capacitance (A0~A13, BA0~BA2, RAS#, CAS#, WE#)
CIN1
10
16
pF
Input capacitance (CKE0, ODT0, CS0#)
CIN2
10
16
pF
Input capacitance (CK0, CK0#)
CIN3
10.4
16.8
pF
Input/Output capacitance (DQ, DQS, DQS#, DM)
CIO
5.5
6.7
pF
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Product Specifications
PART NO.:
VL47B2863A-F8SE
REV: 1.0
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA www.virtium.com 6
IDD Specification
Condition
Symbol
F8
(DDR3-1066)
Unit
Operating one bank active-precharge current;
tCK= tCK(IDD); tRC= tRC(IDD); tRAS= tRAS MIN(IDD); CKE is HIGH, CS# is
HIGH between valid commands; Address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
IDD0*
480
mA
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 8; CL = CL(IDD); AL = 0; tCK= tCK(IDD); tRC= tRC(IDD);
tRAS= tRAS MIN(IDD); tRCD= tRCD(IDD); CKE is HIGH, CS# is HIGH between
valid commands; Address bus inputs are SWITCHING; Data pattern is same as
IDD4W.
IDD1*
600
mA
Precharge power-down current;
All device banks idle; tCK= tCK(IDD); CKE is LOW; Other control and address
bus inputs are STABLE; Data bus inputs are FLOATING
IDD2P-F**
200
mA
IDD2P-S**
80
mA
Precharge standby current;
All device banks idle; tCK= tCK(IDD); CKE is HIGH; CS# is HIGH; Other control
and address bus inputs are SWITCHING; Data bus inputs are SWITCHING.
IDD2N**
240
mA
Precharge quiet standby current;
All device banks idle; tCK= tCK(IDD); CKE is HIGH; CS# is HIGH; Other control
and address bus inputs are STABLE; Data bus inputs are FLOATING
IDD2Q**
240
mA
Active power-down current;
All device banks open; tCK= tCK(IDD); CKE is LOW; Other control and address
bus inputs are STABLE; Data bus inputs are FLOATING.
IDD3P**
200
mA
Active standby current;
All device banks open; tCK= tCK(IDD); tRP= tRP(IDD); tRAS= tRAS MAX(IDD));
CKE is HIGH, CS# is HIGH between valid commands; Other control and address
bus inputs are SWITCHING; Data bus inputs are SWITCHING.
IDD3N**
360
mA
Operating burst read current;
All device banks open; Continuous burst reads; IOUT = 0mA; BL = 8; CL =
CL(IDD); AL = 0; tCK= tCK(IDD); tRAS= tRAS MAX(IDD); tRP= tRP(IDD); CKE is
HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data pattern is same as IDD4W.
IDD4R*
880
mA
Operating burst write current;
All device banks open; Continuous burst writes; BL = 8; CL = CL(IDD); AL = 0;
tCK= tCK(IDD); tRAS= tRAS MAX(IDD); tRP= tRP(IDD); CKE is HIGH, CS# is
HIGH between valid commands; Address bus inputs are SWITCHING; Data bus
inputs are SWITCHING.
IDD4W*
920
mA
Burst refresh current;
tCK=tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH;
CS# is HIGH between valid commands; Other control and address bus inputs
are SWITCHING; Data bus inputs are SWITCHING.
IDD5**
1200
mA
Self refresh current;
CK and CK# at 0V; CKE < 0.2V; Other control and address bus inputs are
FLOATING; Data bus inputs are FLOATING.
IDD6**
80
mA
Operating bank interleave read current;
All bank interleaving reads; IOUT = 0mA; BL = 8; CL = CL(IDD); AL = tRCD(IDD)
- 1*tCK(IDD); tCK= tCK(IDD); tRC= tRC(IDD); tRRD = tRRD(IDD); tRCD =
1*tCK(IDD) ; CKE is HIGH; CS# is HIGH between valid commands; Address bus
inputs are STABLE during DESELECTs; Data pattern is same as IDD4R.
IDD7*
1480
mA
Note: IDD specification is based on Samsung E-die components.
*: Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW) mode.
**: Value calculated reflects all module ranks in this operating condition.
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Product Specifications
PART NO.:
VL47B2863A-F8SE
REV: 1.0
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AC TIMING PARAMETERS & SPECIFICATIONS
Parameter
Symbol
K0
(DDR3-1600)
K9
(DDR3-1333)
F8
(DDR3-1066)
Unit
MIN
MAX
MIN
MAX
MIN
MAX
Clock Timing
Minimum Clock Cycle Time (DLL off mode)
tCK(DLL_OFF)
8
-
8
-
8
-
ns
Average Clock Period
tCK(avg)
1.25
<1.50
1.5
<1.875
1.875
<2.5
ns
Clock Period
tCK(abs)
tCK(avg)min
+
tJIT(per)min
tCK(avg)max
+
tJIT(per)max
tCK(avg)min
+
tJIT(per)min
tCK(avg)max
+
tJIT(per)max
tCK(avg)min
+
tJIT(per)min
tCK(avg)max
+
tJIT(per)max
ns
Average high pulse width
tCH(avg)
0.47
0.53
0.47
0.53
0.47
0.53
tCK(avg)
Average low pulse width
tCL(avg)
0.47
0.53
0.47
0.53
0.47
0.53
tCK(avg)
Clock Period Jitter
tJIT(per)
-70
70
-80
80
-90
90
ps
Clock Period Jitter during DLL locking period
tJIT(per, lck)
-60
60
-70
70
-80
80
ps
Cycle to Cycle Period Jitter
tJIT(cc)
140
160
180
ps
Cycle to Cycle Period Jitter during DLL locking period
tJIT(cc, lck)
120
140
160
ps
Cumulative error across 2 cycles
tERR(2per)
-103
103
-118
118
-132
132
ps
Cumulative error across 3 cycles
tERR(3per)
-122
122
-140
140
-157
157
ps
Cumulative error across 4 cycles
tERR(4per)
-136
136
-155
155
-175
175
ps
Cumulative error across 5 cycles
tERR(5per)
-147
147
-168
168
-188
188
ps
Cumulative error across 6 cycles
tERR(6per)
-155
155
-177
177
-200
200
ps
Cumulative error across 7 cycles
tERR(7per)
-163
163
-186
186
-209
209
ps
Cumulative error across 8 cycles
tERR(8per)
-169
169
-193
193
-217
217
ps
Cumulative error across 9 cycles
tERR(9per)
-175
175
-200
200
-224
224
ps
Cumulative error across 10 cycles
tERR(10per)
-180
180
-205
205
-231
231
ps
Cumulative error across 11 cycles
tERR(11per)
-184
184
-210
210
-237
237
ps
Cumulative error across 12 cycles
tERR(12per)
-188
188
-215
215
-242
242
ps
Cumulative error across n = 13, 14 ... 49, 50 cycles
tERR(nper)
tERR(nper)min =(1+ 0.68ln(n))*tJIT(per)min
tERR(nper)max=(1+ 0.68ln(n))*tJIT(per)max
ps
Absolute clock HIGH pulse width
tCH(abs)
0.43
-
0.43
-
0.43
-
tCK(avg)
Absolute clock Low pulse width
tCL(abs)
0.43
-
0.43
-
0.43
-
tCK(avg)
Data Timing
DQS,DQS# to DQ skew, per group, per access
tDQSQ
-
100
-
125
-
150
ps
DQ output hold time from DQS, DQS#
tQH
0.38
-
0.38
-
0.38
-
tCK(avg)
DQ low-impedance time from CK, CK#
tLZ(DQ)
-450
225
-500
250
-600
300
ps
DQ high-impedance time from CK, CK#
tHZ(DQ)
-
225
-
250
-
300
ps
Data setup time to DQS, DQS# referenced to Vih(ac)Vil(ac)
levels
tDS(base)
(AC175)
-
-
-
-
25
-
ps
Data setup time to DQS, DQS# referenced to Vih(ac)Vil(ac)
levels
tDS(base)
(AC150)
10
-
30
-
-
-
ps
Data hold time to DQS, DQS# referenced to Vih(ac)Vil(ac)
levels
tDH(base)
45
-
65
-
100
-
ps
DQ and DM Input pulse width for each input
tDIPW
360
-
400
-
490
-
ps
www.virtium.cam
Product Specifications
PART NO.:
VL47B2863A-F8SE
REV: 1.0
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA www.virtium.com 8
AC TIMING PARAMETERS & SPECIFICATIONS
Parameter
Symbol
K0
(DDR3-1600)
K9
(DDR3-1333)
F8
(DDR3-1066)
Unit
MIN
MAX
MIN
MAX
MIN
MAX
Data Strobe Timing
DQS, DQS# READ Preamble
tRPRE
0.9
-
0.9
-
0.9
-
tCK
DQS, DQS# differential READ Postamble
tRPST
0.3
-
0.3
-
0.3
-
tCK
DQS, DQS# output high time
tQSH
0.4
-
0.4
-
0.38
-
tCK(avg)
DQS, DQS# output low time
tQSL
0.4
-
0.4
-
0.38
-
tCK(avg)
DQS, DQS# WRITE Preamble
tWPRE
0.9
-
0.9
-
0.9
-
tCK
DQS, DQS# WRITE Postamble
tWPST
0.3
-
0.3
-
0.3
-
tCK
DQS, DQS# rising edge output access time from rising CK,
CK#
tDQSCK
-225
225
-255
255
-300
300
ps
DQS, DQS# low-impedance time (Referenced from
RL-1)
tLZ(DQS)
-450
225
-500
250
-600
300
ps
DQS, DQS# high-impedance time (Referenced from RL+BL/ 2)
tHZ(DQS)
-
225
-
250
-
300
ps
DQS, DQS# differential input low pulse width
tDQSL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
DQS, DQS# differential input high pulse width
tDQSH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
DQS, DQS# rising edge to CK, CK# rising edge
tDQSS
-0.27
0.27
-0.25
0.25
-0.25
0.25
tCK(avg)
DQS,DQS# failing edge setup time to CK, CK# rising edge
tDSS
0.18
-
0.2
-
0.2
-
tCK(avg)
DQS,DQS# failing edge hold time to CK, CK# rising edge
tDSH
0.18
-
0.2
-
0.2
-
tCK(avg)
Command and Address Timing
DLL locking time
tDLLK
512
-
512
-
512
-
nCK
Internal READ Command to PRECHARGE Command delay
tRTP
max
(4tCK,7.5ns)
-
max
(4tCK,7.5ns)
-
max
(4tCK,7.5ns)
-
Delay from start of internal write transaction to internal read
command
tWTR
max
(4tCK,7.5ns)
-
max
(4tCK,7.5ns)
-
max
(4tCK,7.5ns)
-
WRITE recovery time
tWR
15
-
15
-
15
-
ns
Mode Register Set command cycle time
tMRD
4
-
4
-
4
-
nCK
Mode Register Set command update delay
tMOD
max
(12tCK,15ns)
-
max
(12tCK,15ns)
-
max
(12tCK,15ns)
-
CAS# to CAS# command delay
tCCD
4
-
4
-
4
-
nCK
Auto precharge write recovery + precharge time
tDAL(min)
WR + roundup (tRP / tCK(AVG))
nCK
Multi-Purpose Register Recovery Time
tMPRR
1
-
1
-
1
-
nCK
ACTIVE to PRECHARGE command period
tRAS
35
9*tREFI
36
9*tREFI
37.5
9*tREFI
ns
ACTIVE to internal read or write delay time
tRCD
13.75
-
13.5
-
13.13
-
ns
PRECHARGE command period
tRP
13.75
-
13.5
-
13.13
-
ns
ACTIVE to ACTIVE or REF command period
tRC
48.75
-
49.5
-
50.63
-
ns
ACTIVE to ACTIVE command period for 1KB page size
tRRD
max (4tCK,
6ns)
-
max (4tCK,
6ns)
-
max (4tCK,
7.5ns)
-
ACTIVE to ACTIVE command period for 2KB page size
tRRD
max
(4tCK,7.5ns)
-
max
(4tCK,7.5ns)
-
max
(4tCK,10ns)
-
Four activate window for 1KB page size
tFAW
30
-
30
-
37.5
-
ns
Four activate window for 2KB page size
tFAW
40
-
45
-
50
-
ns
Command and Address setup time to CK, CK# referenced to
Vih(ac) / Vil(ac) levels
tIS(base)
(AC175)
-
-
-
-
125
-
ps
Command and Address setup time to CK, CK# referenced to
Vih(ac) / Vil(ac) levels
tIS(base)
(AC150)
170
-
190
-
-
-
ps
Command and Address hold time from CK, CK# referenced to
Vih(ac) / Vil(ac) levels
tIH(base)
120
-
140
-
200
-
ps
Control & Address Input pulse width for each input
tIPW
560
-
620
-
780
-
ps
www.virtium.com
Product Specifications
PART NO.:
VL47B2863A-F8SE
REV: 1.0
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA www.virtium.com 9
AC TIMING PARAMETERS & SPECIFICATIONS
Parameter
Symbol
K0
(DDR3-1600)
K9
(DDR3-1333)
F8
(DDR3-1066)
Unit
MIN
MAX
MIN
MAX
MIN
MAX
Refresh Timing
1Gb REFRESH to REFRESH or REFRESH to ACTIVE
command interval
tRFC
110
-
110
-
110
-
ns
Average periodic refresh interval
(0°C<= TCASE <= 85 °C)
tREFI
7.8
-
7.8
-
7.8
-
us
Average periodic refresh interval
(85°C<= TCASE <= 95 °C)
tREFI
3.9
-
3.9
-
3.9
-
us
Calibration Timing
Power-up and RESET calibration time
tZQinitI
512
-
512
-
512
-
tCK
Normal operation Full calibration time
tZQoper
256
-
256
-
256
-
tCK
Normal operation Short calibration time
tZQCS
64
-
64
-
64
-
tCK
Reset Timing
Exit Reset from CKE HIGH to a valid command
tXPR
max
(5tCK,
tRFC + 10ns)
-
max
(5tCK,
tRFC + 10ns)
-
max
(5tCK,
tRFC + 10ns)
-
Self Refresh Timing
Exit Self Refresh to commands not requiring a locked DLL
tXS
max(5tC,
tRFC+10ns)
-
max(5tC,
tRFC+10ns)
-
max(5tC,
tRFC +10ns)
-
Exit Self Refresh to commands requiring a locked DLL
tXSDLL
tDLLK(min)
-
tDLLK(min)
-
tDLLK(min)
-
nCK
Minimum CKE low width for Self refresh entry to exit timing
tCKESR
tCKE(min) +
1tCK
-
tCKE(min) +
1tCK
-
tCKE(min) +
1tCK
-
Valid Clock Requirement after Self Refresh Entry (SRE)
tCKSRE
max(5tC,
10ns)
-
max(5tCK,
10ns)
-
max(5tCK,
10ns)
-
Valid Clock Requirement before Self Refresh Exit (SRX)
tCKSRX
max(5tC,
10ns)
-
max(5tCK,
10ns)
-
max(5tCK,
10ns)
-
Power Down Timing
Exit Power Down with DLL to any valid command; Exit
Precharge Power Down with DLL frozen to commands not
requiring a locked DLL
tXP
max (3tCK,
6ns)
-
max (3tCK,
6ns)
-
max (3tCK,
7.5ns)
-
Exit Precharge Power Down with DLL frozen to commands
requiring a locked DLL
tXPDLL
max
(10tCK,24ns)
-
max
(10tCK,24ns)
-
max
(10tCK,24ns)
-
CKE minimum pulse width
tCKE
max (3tCK,
5ns)
-
max (3tCK,
5.625ns)
-
max (3tCK,
5.625ns)
-
Command pass disable delay
tCPDED
1
-
1
-
1
-
nCK
Power Down Entry to Exit Timing
tPD
tCKE(min)
9*tREFI
tCKE(min)
9*tREFI
tCKE(min)
9*tREFI
tCK
Timing of ACT command to Power Down entry
tACTPDEN
1
-
1
-
1
-
nCK
Timing of PRE command to Power Down entry
tPRPDEN
1
-
1
-
1
-
nCK
Timing of RD/RDA command to Power Down entry
tRDPDEN
RL + 4 +1
-
RL + 4 +1
-
RL + 4 +1
-
Timing of WR command to Power Down entry BL8 (OTF,
MRS), BL4OTF
tWRPDEN
WL + 4
+ (tWR/
tCK(avg))
-
WL + 4
+ (tWR/
tCK(avg))
-
WL + 4
+ (tWR/
tCK(avg))
-
nCK
Timing of WRA command to Power Down entry BL8 (OTF,
MRS), BL4OTF
tWRAPDEN
WL+4
+WR+1
-
WL+4
+WR+1
-
WL+4
+WR+1
-
nCK
Timing of WR command to Power Down entry (BL4MRS)
tWRPDEN
WL + 2
+ (tWR/
tCK(avg))
-
WL + 2
+ (tWR/
tCK(avg))
-
WL + 2
+ (tWR/
tCK(avg))
-
nCK
Timing of WRA command to Power Down entry (BL4MRS)
tWRAPDEN
WL+2
+WR+1
-
WL+2
+WR+1
-
WL+2
+WR+1
-
nCK
Timing of REF command to Power Down entry
tREFPDEN
1
-
1
-
1
-
Timing of MRS command to Power Down entry
tMRSPDEN
tMOD(min)
-
tMOD(min)
-
tMOD(min)
-
www.virtium.cam
Product Specifications
PART NO.:
VL47B2863A-F8SE
REV: 1.0
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA www.virtium.com 10
AC TIMING PARAMETERS & SPECIFICATIONS
Parameter
Symbol
K0
(DDR3-1600)
K9
(DDR3-1333)
F8
(DDR3-1066)
Unit
MIN
MAX
MIN
MAX
MIN
MAX
ODT Timing
ODT high time without write command or with write command
and BC4
ODTH4
4
-
4
-
4
-
nCK
ODT high time with Write command and BL8
ODTH8
6
-
6
-
6
-
nCK
Asynchronous RTT turn-on delay (Power-Down with DLL
frozen)
tAONPD
2
8.5
2
8.5
2
8.5
ns
Asynchronous RTT turn-off delay (Power-Down with DLL
frozen)
tAOFPD
2
8.5
2
8.5
2
8.5
ns
ODT turn-on
tAON
-225
225
-250
250
-300
300
ps
RTT_NOM and RTT_WR turn-off time from ODTL off reference
tAOF
0.3
0.7
0.3
0.7
0.3
0.7
tCK(avg)
RTT dynamic change skew
tADC
0.3
0.7
0.3
0.7
0.3
0.7
tCK(avg)
Write Leveling Timing
First DQS pulse rising edge after tDQSS margining mode is
programmed
tWLMRD
40
-
40
-
40
-
tCK
DQS/DQS delay after tDQS margining mode is programmed
tWLDQSEN
25
-
25
-
25
-
tCK
Setup time for tDQSS latch
tWLS
165
-
195
-
245
-
ps
Hold time for tDQSS latch
tWLH
165
-
195
-
245
-
ps
Write leveling output delay
tWLO
0
7.5
0
9
0
9
ns
Write leveling output error
tWLOE
0
2
0
2
0
2
ns
V Virtium H : + % |:||:| |:||:| |:||:| IIIIIIIIIIIIIIIIIIIIIIIII IIIllllfilcflllli-Iliillcllfillfil—Illlfilfilll fiUw D («D |:n:n:n:n:n:n:n:| |:n:| |:I|:I|:I|:I|:n:| G) W w UL www.virtium.com
Product Specifications
PART NO.:
VL47B2863A-F8SE
REV: 1.0
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA www.virtium.com 11
Package Dimensions
Note: 1. All dimensions are in millimeters with tolerance +/- 0.15mm unless otherwise specified.
2. The dimensional diagram is for reference only.
FRONT VIEW
1.0 +/- 0.10
TYP
4.00 TYP
6.00 TYP
21.00 TYP
PIN 204
1.80 (2X)
3.00 TYP
39.00 TYP
PIN 203
3.40
MAX
2.15 TYP
BACK VIEW
1.0 +/- 0.10
PIN 2
PIN 1 0.45 TYP
67.60
63.60 TYP
0.60 TYP
20.00 TYP
30.00
TYP
24.80 TYP
TYP
0.5 R
4.0 +/- 0.10 (2X)
2.55 TYP
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Product Specifications
PART NO.:
VL47B2863A-F8SE
REV: 1.0
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA www.virtium.com 12
Revision History:
Date
Rev.
Page
Changes
10/24/2012
1.0
All
Spec release

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