SGx525A Datasheet by STMicroelectronics

View All Related Products | Download PDF Datasheet
INV. INPUT N. I ,Iwur svuc osc. OLIYPUV DISCHARGE son - swat 15 15 u 13 u n m s-inA Vnzr .v. BUYPUY a
SG2525A
SG3525A
REGULATING PULSE WIDTH MODULATORS
.8 TO 35 V OPERATION
.5.1 V REFERENCE TRIMMED TO ± 1 %
.100 Hz TO 500 KHz OSCILLATOR RANGE
.SEPARATE OSCILLATOR SYNC TERMINAL
.ADJUSTABLE DEADTIME CONTROL
.INTERNAL SOFT-START
.PULSE-BY-PULSE SHUTDOWN
.INPUT UNDERVOLTAGE LOCKOUT WITH
HYSTERESIS
.LATCHING PWM TO PREVENT MULTIPLE
PULSES
.DUAL SOURCE/SINK OUTPUT DRIVERS
DESCRIPTION
The SG3525A series of pulse width modulator inte-
grated circuits are designed to offer improved per-
formance and lowered external parts count when
used in designing all types of switching power sup-
plies. The on-chip + 5.1 V reference is trimmed to ±
1 % and the input common-mode range of the error
amplifier includes the reference voltage eliminating
external resistors. A sync input to the oscillator al-
lows multiple units to be slaved or a single unit to be
synchronized to an external system clock. A single
resistor between the CT and the discharge terminals
provide a wide range of dead time ad- justment.
These devices also feature built-in soft-start circuitry
with only an external timing capacitor required. A
shutdown terminal controls both the soft-start circu-
ity and the output stages, providing instantaneous
turn off through the PWM latch with pulsed shut-
down, as well as soft-start recycle with longer shut-
down commands. These functions are also control-
led by an undervoltage lockout which keeps the out-
puts off and the soft-start capacitor discharged for
sub-normal input voltages. This lockout circuitry in-
cludes approximately 500 mV of hysteresis for jitter-
free operation. Another feature of these PWM cir-
cuits is a latch following the comparator. Once a
PWM pulses has been terminated for any reason,
the outputs will remain off for the duration of the pe-
riod. The latch is reset with each clock pulse. The
output stages are totem-pole designs capable of
sourcing or sinking in excess of 200 mA. The
SG3525A output stage features NOR logic, giving a
LOW output for an OFF state.
DIP16 16(Narrow)
Type Plastic DIP SO16
SG2525A SG2525AN SG2525AP
SG3525A SG3525AN SG3525AP
PIN CONNECTIONS AND ORDERING NUMBERS (top view)
®
June 2000 1/12
my n hi5 u a c as“ man an mm m mum cutumn mum. Mm 7. rm sm- -. m4 mm son-sum I 5-0"an sun In 1 ii m 40“ J1— wu-xu _n_ mm nun-m sun: '4: 40 I: mn-ul A _o.. M'—
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
ViSupply Voltage 40 V
VCCollector Supply Voltage 40 V
IOSC Oscillator Charging Current 5 mA
IoOutput Current, Source or Sink 500 mA
IRReference Output Current 50 mA
ITCurrent through CT Terminal
Logic Inputs
Analog Inputs
5
– 0.3 to + 5.5
– 0.3 to Vi
mA
V
V
Ptot Total Power Dissipation at Tamb = 70 °C 1000 mW
TjJunction Temperature Range – 55 to 150 °C
Tstg Storage Temperature Range – 65 to 150 °C
Top Operating Ambient Temperature : SG2525A
SG3525A – 25 to 85
0 to 70 °C
°C
THERMAL DATA
Symbol Parameter SO16 DIP16 Unit
Rth j-pins
Rth j-amb
Rth j-alumina
Thermal Resistance Junction-pins Max
Thermal Resistance Junction-ambient Max
Thermal Resistance Junction-alumina (*) Max 50
50
80 °C/W
°C/W
°C/W
*Thermal resistance junction-alumina with the device soldered on the middle of an alumina supporting substrate measuring 15 × 20 mm ; 0.65 mm
thickness with infinite heatsink.
BLOCK DIAGRAM
SG2525A-SG3525A
2/12
ELECTRICAL CHARACTERISTICS
(V# i = 20 V, and over operating temperature, unless otherwise specified)
Symbol Parameter Test Conditions SG2525A SG3525A Unit
Min. Typ. Max. Min. Typ. Max.
REFERENCE SECTION
VREF Output Voltage Tj = 25 °C 5.05 5.1 5.15 5 5.1 5.2 V
VREF Line Regulation Vi = 8 to 35 V 10 20 10 20 mV
VREF Load Regulation IL = 0 to 20 mA 20 50 20 50 mV
VREF/T* Temp. Stability Over Operating Range 20 50 20 50 mV
* Total Output Variation Line, Load and
Temperature 5 5.2 4.95 5.25 V
Short Circuit Current VREF = 0 Tj = 25 °C 80 100 80 100 mA
* Output Noise Voltage 10 Hz f 10 kHz,
Tj = 25 °C40 200 40 200 µVrms
VREF* Long Term Stability Tj = 125 °C, 1000 hrs 20 50 20 50 mV
OSCILLATOR SECTION * *
*, Initial Accuracy Tj = 25 °C± 2 ± 6 ± 2 ± 6%
*, Voltage Stability Vi = 8 to 35 V ± 0.3 ± 1 ± 1 ± 2%
f/T* Temperature Stability Over Operating Range ± 3 ± 6 ± 3 ± 6%
f
MIN Minimum Frequency RT = 200 K CT = 0.1 µF 120 120 Hz
fMAX Maximum Frequency RT = 2 K CT = 470 pF 400 400 KHz
Current Mirror IRT = 2 mA 1.7 2 2.2 1.7 2 2.2 mA
*, Clock Amplitude 3 3.5 3 3.5 V
*, Clock Width Tj = 25 °C 0.3 0.5 1 0.3 0.5 1 µs
Sync Threshold 1.2 2 2.8 1.2 2 2.8 V
Sync Input Current Sync Voltage = 3.5 V 1 2.5 1 2.5 mA
ERROR AMPLIFIER SECTION (VCM = 5.1 V)
VOS Input Offset Voltage 0.5 5 2 10 mV
IbInput Bias Current 1 10 1 10 µA
Ios Input Offset Current 1 1 µA
DC Open Loop Gain RL 10 M60 75 60 75 dB
* Gain Bandwidth
Product Gv = 0 dB Tj = 25 °C 1 2 1 2 MHz
*, DC Transconduct. 30 K RL 1 M
Tj = 25 °C1.1 1.5 1.1 1.5 ms
Output Low Level 0.2 0.5 0.2 0.5 V
Output High Level 3.8 5.6 3.8 5.6 V
CMR Comm. Mode Reject. VCM = 1.5 to 5.2 V 60 75 60 75 dB
PSR Supply Voltage
Rejection Vi = 8 to 35 V 50 60 50 60 dB
SG2525A-SG3525A
3/12
ELECTRICAL CHARACTERISTICS (continued)
Symbol Parameter Test Conditions SG2525A SG3525A
Unit
Min. Typ. Max. Min. Typ. Max.
PWM COMPARATOR
Minimum Duty-cycle 0 0 %
Maximum Duty-cycle 45 49 45 49 %
Input Threshold Zero Duty-cycle 0.7 0.9 0.7 0.9 V
Maximum Duty-cycle 3.3 3.6 3.3 3.6 V
* Input Bias Current 0.05 1 0.05 1 µA
SHUTDOWN SECTION
Soft Start Current VSD = 0 V, VSS = 0 V 255080255080 µA
Soft Start Low Level VSD = 2.5 V 0.4 0.7 0.4 0.7 V
Shutdown Threshold To outputs, VSS = 5.1 V
Tj = 25 °C0.6 0.8 1 0.6 0.8 1 V
Shutdown Input Current VSD = 2.5 V 0.4 1 0.4 1 mA
* Shutdown Delay VSD = 2.5 V Tj = 25 °C 0.2 0.5 0.2 0.5 µs
OUTPUT DRIVERS (each output) (VC = 20 V)
Output Low Level Isink = 20 mA 0.2 0.4 0.2 0.4 V
Isink = 100 mA 1 2 1 2 V
Output High Level Isource = 20 mA 18 19 18 19 V
Isource = 100 mA 17 18 17 18 V
Under-Voltage Lockout Vcomp and Vss = High 678678 V
I
CCollector Leakage VC = 35 V 200 200 µA
tr* Rise Time CL = 1 nF, Tj = 25 °C 100 600 100 600 ns
tf* Fall Time CL = 1 nF, Tj = 25 °C 50 300 50 300 ns
TOTAL STANDBY CURRENT
IsSupply Current Vi = 35 V 14 20 14 20 mA
*These parameters, although guaranteed over the recommended operating conditions, are not 100 % tested in production.
Tested at fosc = 40 KHz (RT = 3.6 K, CT = 10nF, RD = 0 ). Approximate oscillator frequency is defined by :
1
f = CT (0.7 RT + 3 RD)
.DC transconductance (gM) relates to DC open-loop voltage gain (Gv) according to the following equation : Gv = gM RL where RL is the resistance
from pin 9 to ground. The minimum gM specification is used to calculate minimum Gv when the error amplifier output is loaded.
SG2525A-SG3525A
4/12
In N L. \J . I n 55...; 0 3».— J and omu—Au1v—oz Ezu ~3:.=5ux uflmxumux
TEST CIRCUIT
SG2525A-SG3525A
5/12
s-m. mm "n=° 5n n ,qr m 0.01 1 5 m 20 sommmnmmwu smx saw. v0L u 1.0) s-lln m) 2m: / 0.2 m 1 ‘l a w 2:: so was) unu- (an) In L... ‘0 ”RA mu. Mo- ” lmfillhninlnfiufil m. mum... my qua are» m- nus: .m- .210' .am' m m «an mu m mm H
Figure 1 : Oscillator Charge Time vs. RT
and CT.Figure 2 : Oscillator Discharge Time vs. RD
and CT.
RECOMMENDED OPERATING CONDITIONS ()
Parameter Value
Input Voltage (Vi) 8 to 35 V
Collector Supply Voltage (VC) 4.5 to 35 V
Sink/Source Load Current (steady state) 0 to 100 mA
Sink/Source Load Current (peak) 0 to 400 mA
Reference Load Current 0 to 20 mA
Oscillator Frequency Range 100 Hz to 400 KHz
Oscillator Timing Resistor 2 K to 150 K
Oscillator Timing Capacitor 0.001 µF to 0.1 µF
Dead Time Resistor Range 0 to 500
() Range over which the device is functional and parameter limits are guaranteed.
Figure 3 : Output Saturation
Characteristics. Figure 4 : Error Amplifier Voltage Gain and
Phase vs. Frequency.
SG2525A-SG3525A
6/12
T0 PWM COMPARATOR Imon o COME
SHUTDOWN OPTIONS (see Block Diagram)
Since both the compensation and soft-start termi-
nals (Pins 9 and 8) have current source pull-ups,
either can readily accept a pull-down signal which
only has to sink a maximum of 100 µA to turn off the
outputs. This is subject to the added requirement of
discharging whatever external capacitance may be
attached to these pins.
An alternate approach is the use of the shutdown cir-
cuitry of Pin 10 which has been improved to en-
hance the available shutdown options. Activating
this circuit by applying a positive signal on Pin 10
performs two functions : the PWM latch is immedi-
ately set providing the fastest turn-off signal to the
outputs ; and a 150 µA current sink begins to dis-
charge the external soft-start capacitor. If the shut-
down command is short, the PWM signal is termi-
nated without significant discharge of the soft-start
capacitor, thus, allowing, for example, a convenient
implementation of pulse-by-pulse current limiting.
Holding Pin 10 high for a longer duration, however,
will ultimately discharge this external capacitor, re-
cycling slow turn-on upon release.
Pin 10 should not be left floating as noise pickup
could conceivably interrupt normal operation.
Figure 5 : Error Amplifier.
PRINCIPLES OF OPERATION
SG2525A-SG3525A
7/12
VREF @ m as no ““1 at n: c, @— us an M11 ] L In RAMP. 10 mm 15m SVNI. 3 : 332mm; museums: I um" (III I! 3 _ mg] 150 n am 12 - G _ ”m m '3 "a as m m. N am 8 5 A +VR£F II _. oun=ur I‘ c l 8 WI'IYED 0“ Kn om mm cmcn FIF Pvm m 5515:“ um s-Imn
Figure 7 : Output Circuit (1/2 circuit shown).
Figure 6 : Oscillator Schematic.
SG2525A-SG3525A
8/12
n :1 oz - “ a “ n: n 5"" 5m: J: c s-lilm s..." .15 "Q m u m :1 V: '3 n n w n m £ uz 11 c2 1‘ sun “1 m a: u I 543“ -- s—iln
Figure 10. Figure 11.
For single-ended supplies, the driver outputs are
grounded. The VC terminal is switched to ground by
the totem-pole source transistors on alternate oscil-
lator cycles.
In conventional push-pull bipolar designs, forward
base drive is controlled by R1 - R3. Rapid turn-off
times for the power devices are achieved with
speed-up capacitors C1 and C2.
The low source impedance of the output drivers pro-
vides rapid charging of Power Mos input capaci-
tance while minimizing external components.
Low power transformers can be driven directly.
Automatic reset occurs during dead time, when both
ends of the primary winding are switched to ground.
Figure 8. Figure 9.
SG2525A-SG3525A
9/12
a1 |
DIP16
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
a1 0.51 0.020
B 0.77 1.65 0.030 0.065
b 0.5 0.020
b1 0.25 0.010
D 20 0.787
E 8.5 0.335
e 2.54 0.100
e3 17.78 0.700
F 7.1 0.280
I 5.1 0.201
L 3.3 0.130
Z 1.27 0.050
OUTLINE AND
MECHANICAL DATA
SG2525A-SG3525A
10/12
SO16 Narrow
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 1.75 0.069
a1 0.1 0.25 0.004 0.009
a2 1.6 0.063
b 0.35 0.46 0.014 0.018
b1 0.19 0.25 0.007 0.010
C 0.5 0.020
c1 45˚ (typ.)
D (1) 9.8 10 0.386 0.394
E 5.8 6.2 0.228 0.244
e 1.27 0.050
e3 8.89 0.350
F (1) 3.8 4 0.150 0.157
G 4.6 5.3 0.181 0.209
L 0.4 1.27 0.016 0.050
M 0.62 0.024
S
(1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch).
OUTLINE AND
MECHANICAL DATA
8˚(max.)
SG2525A-SG3525A
11/12
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the conse-
quences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this
publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMi-
croelectronics products are not authorized for use as critical components in life support devices or systems without express written
approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics
© 2000 STMicroelectronics – Printed in Italy – All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco -
Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
http://www.st.com
SG2525A-SG3525A
12/12

Products related to this Datasheet

IC REG CTRLR BCK/PSH-PULL 16SOIC
IC REG CTRLR BCK/PUSH-PULL 16DIP
IC REG CTRLR BCK/PSH-PULL 16SOIC
IC REG CTRLR BCK/PSH-PULL 16SOIC
IC REG CTRLR BCK/PSH-PULL 16SOIC
IC REG CTRLR BCK/PSH-PULL 16SOIC
IC REG CTRLR BCK/PUSH-PULL 16DIP
IC REG CTRLR BCK/PSH-PULL 16SOIC
IC REG CTRLR BCK/PSH-PULL 16SOIC
IC REG CTRLR BCK/PUSH-PULL 16DIP
IC REG CTRLR BCK/PUSH-PULL 16DIP
IC REG CTRLR BCK/PSH-PULL 16SOIC
IC REG CTRLR BCK/PSH-PULL 16SOIC
IC REG CTRLR BCK/PSH-PULL 16SOIC
IC REG CTRLR BCK/PSH-PULL 16SOIC