STM32F103x(8,B) Datasheet by STMicroelectronics

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April 2009 Doc ID 13587 Rev 10 1/91
1
STM32F103x8
STM32F103xB
Medium-density performance line ARM-based 32-bit MCU with 64 or
128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 communication interfaces
Features
Core: ARM 32-bit Cortex™-M3 CPU
72 MHz maximum frequency,
1.25 DMIPS/MHz (Dhrystone 2.1)
performance at 0 wait state memory
access
Single-cycle multiplication and hardware
division
Memories
64 or 128 Kbytes of Flash memory
20 Kbytes of SRAM
Clock, reset and supply management
2.0 to 3.6 V application supply and I/Os
POR, PDR, and programmable voltage
detector (PVD)
4-to-16 MHz crystal oscillator
Internal 8 MHz factory-trimmed RC
Internal 40 kHz RC
PLL for CPU clock
32 kHz oscillator for RTC with calibration
Low power
Sleep, Stop and Standby modes
–V
BAT supply for RTC and backup registers
2 x 12-bit, 1 µs A/D converters (up to 16
channels)
Conversion range: 0 to 3.6 V
Dual-sample and hold capability
Temperature sensor
DMA
7-channel DMA controller
Peripherals supported: timers, ADC, SPIs,
I2Cs and USARTs
Up to 80 fast I/O ports
26/37/51/80 I/Os, all mappable on 16
external interrupt vectors and almost all
5 V-tolerant
Debug mode
Serial wire debug (SWD) & JTAG interfaces
7 timers
Three 16-bit timers, each with up to 4
IC/OC/PWM or pulse counter and
quadrature (incremental) encoder input
16-bit, motor control PWM timer with dead-
time generation and emergency stop
2 watchdog timers (Independent and
Window)
SysTick timer: a 24-bit downcounter
Up to 9 communication interfaces
Up to 2 x I2C interfaces (SMBus/PMBus)
Up to 3 USARTs (ISO 7816 interface, LIN,
IrDA capability, modem control)
Up to 2 SPIs (18 Mbit/s)
CAN interface (2.0B Active)
USB 2.0 full-speed interface
CRC calculation unit, 96-bit unique ID
Packages are ECOPACK®
Table 1. Device summary
Reference Part number
STM32F103x8 STM32F103C8, STM32F103R8
STM32F103V8, STM32F103T8
STM32F103xB STM32F103RB STM32F103VB,
STM32F103CB
BGA100 10 × 10 mm
BGA64 5 × 5 mm
VFQFPN36
6 × 6 mm
LQFP48 7 × 7 m
LQFP100 14 × 14 m
LQFP64 10 × 10 m
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Contents STM32F103x8, STM32F103xB
2/91 Doc ID 13587 Rev 10
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3.1 ARM® CortexTM-M3 core with embedded Flash and SRAM . . . . . . . . 12
2.3.2 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3.3 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 12
2.3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3.5 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 12
2.3.6 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 13
2.3.7 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3.8 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3.9 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3.10 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3.11 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.12 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.13 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.14 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 15
2.3.15 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.16 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.17 Universal synchronous/asynchronous receiver transmitter (USART) . . 17
2.3.18 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.19 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.20 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.21 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.22 ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.23 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3.24 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 18
3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
STM32F103x8, STM32F103xB Contents
Doc ID 13587 Rev 10 3/91
5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 36
5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 36
5.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.3.11 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 55
5.3.12 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.3.13 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.3.14 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.3.15 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.3.16 CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . . . 66
5.3.17 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.3.18 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.2.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 82
7 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Contents STM32F103x8, STM32F103xB
4/91 Doc ID 13587 Rev 10
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
STM32F103x8, STM32F103xB List of tables
Doc ID 13587 Rev 10 5/91
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. STM32F103xx medium-density device features and peripheral counts . . . . . . . . . . . . . . . 10
Table 3. STM32F103xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 4. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5. Medium-density STM32F103xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 6. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 7. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 8. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 9. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 10. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 11. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 12. Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 13. Maximum current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 14. Maximum current consumption in Run mode, code with data processing
running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 15. Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 41
Table 16. Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 42
Table 17. Typical current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 18. Typical current consumption in Sleep mode, code running from Flash or
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 19. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 20. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 21. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 22. HSE 4-16 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 23. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 24. HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 25. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 26. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 27. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 28. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 29. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 30. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 31. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 32. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 33. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 34. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 35. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 36. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 37. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 38. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 39. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 40. SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 41. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 42. USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 43. USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 44. USB: Full-speed electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
List of tables STM32F103x8, STM32F103xB
6/91 Doc ID 13587 Rev 10
Table 45. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 46. RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 47. ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 48. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 49. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 50. VFQFPN36 6 x 6 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . 73
Table 51. LFBGA100 - low profile fine pitch ball grid array package mechanical data. . . . . . . . . . . . 74
Table 52. LQPF100, 100-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . 76
Table 53. LQFP64, 64-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . 77
Table 54. TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package mechanical data. . . 78
Table 55. LQFP48, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . 80
Table 56. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 57. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
STM32F103x8, STM32F103xB List of figures
Doc ID 13587 Rev 10 7/91
List of figures
Figure 1. STM32F103xx performance line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 3. STM32F103xx performance line LFBGA100 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 4. STM32F103xx performance line LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 5. STM32F103xx performance line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 6. STM32F103xx performance line TFBGA64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 7. STM32F103xx performance line LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 8. STM32F103xx Performance Line VFQFPN36 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 9. Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 10. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 11. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 12. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 13. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 14. Typical current consumption in Run mode versus frequency (at 3.6 V) -
code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 40
Figure 15. Typical current consumption in Run mode versus frequency (at 3.6 V) -
code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 40
Figure 16. Typical current consumption in Stop mode with regulator in Run mode versus
temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 17. Typical current consumption in Stop mode with regulator in Low-power mode versus
temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 18. Typical current consumption in Standby mode versus temperature at
VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 19. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 20. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 21. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 22. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 23. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 24. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 25. I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 26. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 27. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 28. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 29. USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 30. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 31. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 32. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . . 70
Figure 33. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . . 71
Figure 34. VFQFPN36 6 x 6 mm, 0.5 mm pitch, package outline(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 35. Recommended footprint (dimensions in mm)(1)(2)(3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 36. LFBGA100 - low profile fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . 74
Figure 37. Recommended PCB design rules (0.80/0.75 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . . . 75
Figure 38. LQFP100, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 39. Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 40. LQFP64, 64-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 41. Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 42. TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package outline . . . . . . . . . . 78
Figure 43. Recommended PCB design rules for pads (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . 79
List of figures STM32F103x8, STM32F103xB
8/91 Doc ID 13587 Rev 10
Figure 44. LQFP48, 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 45. Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 46. LQFP100 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
STM32F103x8, STM32F103xB Introduction
Doc ID 13587 Rev 10 9/91
1 Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F103x8 and STM32F103xB medium-density performance line microcontrollers.
For more details on the whole STMicroelectronics STM32F103xx family, please refer to
Section 2.2: Full compatibility throughout the family.
The medium-density STM32F103xx datasheet should be read in conjunction with the low-,
medium- and high-density STM32F10xxx reference manual.
The reference and Flash programming manuals are both available from the
STMicroelectronics website www.st.com.
For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical
Reference Manual, available from the www.arm.com website at the following address:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/.
2 Description
The STM32F103x8 and STM32F103xB performance line family incorporates the high-
performance ARM Cortex™-M3 32-bit RISC core operating at a 72 MHz frequency, high-
speed embedded memories (Flash memory up to 128 Kbytes and SRAM up to 20 Kbytes),
and an extensive range of enhanced I/Os and peripherals connected to two APB buses. All
devices offer two 12-bit ADCs, three general purpose 16-bit timers plus one PWM timer, as
well as standard and advanced communication interfaces: up to two I2Cs and SPIs, three
USARTs, an USB and a CAN.
The STM32F103xx medium-density performance line family operates from a 2.0 to 3.6 V
power supply. It is available in both the –40 to +85 °C temperature range and the –40 to
+105 °C extended temperature range. A comprehensive set of power-saving mode allows
the design of low-power applications.
The STM32F103xx medium-density performance line family includes devices in six different
package types: from 36 pins to 100 pins. Depending on the device chosen, different sets of
peripherals are included, the description below gives an overview of the complete range of
peripherals proposed in this family.
These features make the STM32F103xx medium-density performance line microcontroller
family suitable for a wide range of applications:
Motor drive and application control
Medical and handheld equipment
PC peripherals gaming and GPS platforms
Industrial applications: PLC, inverters, printers, and scanners
Alarm systems, Video intercom, and HVAC
Figure 1 shows the general block diagram of the device family.
CERTIFIED usp Cdr't'é)?“ Intelhgent Processors by ARM‘ ARM I POWERED
Description STM32F103x8, STM32F103xB
10/91 Doc ID 13587 Rev 10
2.1 Device overview
Table 2. STM32F103xx medium-density device features and peripheral counts
Peripheral STM32F103Tx STM32F103Cx STM32F103Rx STM32F103Vx
Flash - Kbytes 64 64 128 64 128 64 128
SRAM - Kbytes 20 20 20 20 20
Timers
General-purpose 333 3 3
Advanced-control 11 1 1
Communication
SPI 122 2 2
I2C122 2 2
USART 233 3 3
USB 111 1 1
CAN 111 1 1
GPIOs 26 37 51 80
12-bit synchronized ADC
Number of channels
2
10 channels
2
10 channels
2
16 channels
2
16 channels
CPU frequency 72 MHz
Operating voltage 2.0 to 3.6 V
Operating temperatures Ambient temperatures: –40 to +85 °C /–40 to +105 °C (see Ta b l e 9 )
Junction temperature: –40 to + 125 °C (see Ta ble 9 )
Packages VFQFPN36 LQFP48 LQFP64,
TFBGA64
LQFP100,
LFBGA100
STM32F103x8, STM32F103xB Description
Doc ID 13587 Rev 10 11/91
2.2 Full compatibility throughout the family
The STM32F103xx is a complete family whose members are fully pin-to-pin, software and
feature compatible. In the reference manual, the STM32F103x4 and STM32F103x6 are
identified as low-density devices, the STM32F103x8 and STM32F103xB are referred to as
medium-density devices, and the STM32F103xC, STM32F103xD and STM32F103xE are
referred to as high-density devices.
Low- and high-density devices are an extension of the STM32F103x8/B devices, they are
specified in the STM32F103x4/6 and STM32F103xC/D/E datasheets, respectively. Low-
density devices feature lower Flash memory and RAM capacities, less timers and
peripherals. High-density devices have higher Flash memory and RAM capacities, and
additional peripherals like SDIO, FSMC, I2S and DAC, while remaining fully compatible with
the other members of the STM32F103xx family.
The STM32F103x4, STM32F103x6, STM32F103xC, STM32F103xD and STM32F103xE
are a drop-in replacement for STM32F103x8/B medium-density devices, allowing the user
to try different memory densities and providing a greater degree of freedom during the
development cycle.
Moreover, the STM32F103xx performance line family is fully compatible with all existing
STM32F101xx access line and STM32F102xx USB access line devices.
Table 3. STM32F103xx family
Pinout
Low-density devices Medium-density devices High-density devices
16 KB
Flash
32 KB
Flash(1)
1. For orderable part numbers that do not show the A internal code after the temperature range code (6 or 7),
the reference datasheet for electrical characteristics is that of the STM32F103x8/B medium-density
devices.
64 KB
Flash
128 KB
Flash
256 KB
Flash
384 KB
Flash
512 KB
Flash
6 KB RAM 10 KB RAM 20 KB RAM 20 KB RAM 48 KB RAM 64 KB RAM 64 KB RAM
144 5 × USARTs
4 × 16-bit timers, 2 × basic timers
3 × SPIs, 2 × I2Ss, 2 × I2Cs
USB, CAN, 2 × PWM timers
3 × ADCs, 1 × DAC, 1 × SDIO
FSMC (100 and 144 pins)
100 3 × USARTs
3 × 16-bit timers
2 × SPIs, 2 × I2Cs, USB,
CAN, 1 × PWM timer
2 × ADC
64 2 × USARTs
2 × 16-bit timers
1 × SPI, 1 × I2C, USB,
CAN, 1 × PWM timer
2 × ADCs
48
36
Description STM32F103x8, STM32F103xB
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2.3 Overview
2.3.1 ARM® CortexTM-M3 core with embedded Flash and SRAM
The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
The STM32F103xx performance line family having an embedded ARM core, is therefore
compatible with all ARM tools and software.
Figure 1 shows the general block diagram of the device family.
2.3.2 Embedded Flash memory
64 or 128 Kbytes of embedded Flash is available for storing programs and data.
2.3.3 CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
2.3.4 Embedded SRAM
Twenty Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states.
2.3.5 Nested vectored interrupt controller (NVIC)
The STM32F103xx performance line embeds a nested vectored interrupt controller able to
handle up to 43 maskable interrupt channels (not including the 16 interrupt lines of
Cortex™-M3) and 16 priority levels.
Closely coupled NVIC gives low-latency interrupt processing
Interrupt entry vector table address passed directly to the core
Closely coupled NVIC core interface
Allows early processing of interrupts
Processing of late arriving higher priority interrupts
Support for tail-chaining
Processor state automatically saved
Interrupt entry restored on interrupt exit with no instruction overhead
STM32F103x8, STM32F103xB Description
Doc ID 13587 Rev 10 13/91
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
2.3.6 External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 19 edge detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 80 GPIOs can be connected
to the 16 external interrupt lines.
2.3.7 Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).
Several prescalers allow the configuration of the AHB frequency, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and
the high-speed APB domains is 72 MHz. The maximum allowed frequency of the low-speed
APB domain is 36 MHz. See Figure 2 for details on the clock tree.
2.3.8 Boot modes
At startup, boot pins are used to select one of three boot options:
Boot from User Flash
Boot from System Memory
Boot from embedded SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART1. For further details please refer to AN2606.
2.3.9 Power supply schemes
VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.
Provided externally through VDD pins.
VSSA, VDDA = 2.0 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs
and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC is used).
VDDA and VSSA must be connected to VDD and VSS, respectively.
VBAT = 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup
registers (through power switch) when VDD is not present.
For more details on how to connect power pins, refer to Figure 12: Power supply scheme.
2.3.10 Power supply supervisor
The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is
always active, and ensures proper operation starting from/down to 2 V. The device remains
Description STM32F103x8, STM32F103xB
14/91 Doc ID 13587 Rev 10
in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an
external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be
generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher
than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
Refer to Table 11: Embedded reset and power control block characteristics for the values of
VPOR/PDR and VPVD.
2.3.11 Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR) and power down.
MR is used in the nominal regulation mode (Run)
LPR is used in the Stop mode
Power down is used in Standby mode: the regulator output is in high impedance: the
kernel circuitry is powered down, inducing zero consumption (but the contents of the
registers and SRAM are lost)
This regulator is always enabled after reset. It is disabled in Standby mode, providing high
impedance output.
2.3.12 Low-power modes
The STM32F103xx performance line supports three low-power modes to achieve the best
compromise between low power consumption, short startup time and available wakeup
sources:
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
Stop mode
The Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low power mode.
The device can be woken up from Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB
wakeup.
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the Backup
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a
rising edge on the WKUP pin, or an RTC alarm occurs.
Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
STM32F103x8, STM32F103xB Description
Doc ID 13587 Rev 10 15/91
2.3.13 DMA
The flexible 7-channel general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management avoiding the generation of interrupts when the controller
reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose and
advanced-control timers TIMx and ADC.
2.3.14 RTC (real-time clock) and backup registers
The RTC and the backup registers are supplied through a switch that takes power either on
VDD supply when present or through the VBAT pin. The backup registers are ten 16-bit
registers used to store 20 bytes of user application data when VDD power is not present.
The real-time clock provides a set of continuously running counters which can be used with
suitable software to provide a clock calendar function, and provides an alarm interrupt and a
periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the
internal low-power RC oscillator or the high-speed external clock divided by 128. The
internal low-power RC has a typical frequency of 40 kHz. The RTC can be calibrated using
an external 512 Hz output to compensate for any natural crystal deviation. The RTC features
a 32-bit programmable counter for long-term measurement using the Compare register to
generate an alarm. A 20-bit prescaler is used for the time base clock and is by default
configured to generate a time base of 1 second from a clock at 32.768 kHz.
2.3.15 Timers and watchdogs
The medium-density STM32F103xx performance line devices include an advanced-control
timer, three general-purpose timers, two watchdog timers and a SysTick timer.
Ta bl e 4 compares the features of the advanced-control and general-purpose timers.
Advanced-control timer (TIM1)
The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6
channels. It has complementary PWM outputs with programmable inserted dead-times. It
Table 4. Timer feature comparison
Timer Counter
resolution
Counter
type
Prescaler
factor
DMA request
generation
Capture/compare
channels
Complementary
outputs
TIM1 16-bit
Up,
down,
up/down
Any integer
between 1
and 65536
Ye s 4 Ye s
TIM2,
TIM3,
TIM4
16-bit
Up,
down,
up/down
Any integer
between 1
and 65536
Ye s 4 N o
Description STM32F103x8, STM32F103xB
16/91 Doc ID 13587 Rev 10
can also be seen as a complete general-purpose timer. The 4 independent channels can be
used for
Input capture
Output compare
PWM generation (edge- or center-aligned modes)
One-pulse mode output
If configured as a general-purpose 16-bit timer, it has the same features as the TIMx timer. If
configured as the 16-bit PWM generator, it has full modulation capability (0-100%).
In debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled to turn off any power switch driven by these outputs.
Many features are shared with those of the general-purpose TIM timers which have the
same architecture. The advanced-control timer can therefore work together with the TIM
timers via the Timer Link feature for synchronization or event chaining.
General-purpose timers (TIMx)
There are up to three synchronizable general-purpose timers embedded in the
STM32F103xx performance line devices. These timers are based on a 16-bit auto-reload
up/down counter, a 16-bit prescaler and feature 4 independent channels each for input
capture/output compare, PWM or one-pulse mode output. This gives up to 12 input
captures/output compares/PWMs on the largest packages.
The general-purpose timers can work together with the advanced-control timer via the Timer
Link feature for synchronization or event chaining. Their counter can be frozen in debug
mode. Any of the general-purpose timers can be used to generate PWM outputs. They all
have independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 40 kHz internal RC and as it operates independently of the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes. The counter
can be frozen in debug mode.
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from the
main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
STM32F103x8, STM32F103xB Description
Doc ID 13587 Rev 10 17/91
SysTick timer
This timer is dedicated for OS, but could also be used as a standard downcounter. It
features:
A 24-bit downcounter
Autoreload capability
Maskable system interrupt generation when the counter reaches 0
Programmable clock source
2.3.16 I²C bus
Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support
standard and fast modes.
They support dual slave addressing (7-bit only) and both 7/10-bit addressing in master
mode. A hardware CRC generation/verification is embedded.
They can be served by DMA and they support SM Bus 2.0/PM Bus.
2.3.17 Universal synchronous/asynchronous receiver transmitter (USART)
One of the USART interfaces is able to communicate at speeds of up to 4.5 Mbit/s. The
other available interfaces communicate at up to 2.25 Mbit/s. They provide hardware
management of the CTS and RTS signals, IrDA SIR ENDEC support, are ISO 7816
compliant and have LIN Master/Slave capability.
All USART interfaces can be served by the DMA controller.
2.3.18 Serial peripheral interface (SPI)
Up to two SPIs are able to communicate up to 18 Mbits/s in slave and master modes in full-
duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes.
Both SPIs can be served by the DMA controller.
2.3.19 Controller area network (CAN)
The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It
can receive and transmit standard frames with 11-bit identifiers as well as extended frames
with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and
14 scalable filter banks.
2.3.20 Universal serial bus (USB)
The STM32F103xx performance line embeds a USB device peripheral compatible with the
USB full-speed 12 Mbs. The USB interface implements a full-speed (12 Mbit/s) function
interface. It has software-configurable endpoint setting and suspend/resume support. The
dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use
a HSE crystal oscillator).
Description STM32F103x8, STM32F103xB
18/91 Doc ID 13587 Rev 10
2.3.21 GPIOs (general-purpose inputs/outputs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-
capable except for analog inputs.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
I/Os on APB2 with up to 18 MHz toggling speed
2.3.22 ADC (analog-to-digital converter)
Two 12-bit analog-to-digital converters are embedded into STM32F103xx performance line
devices and each ADC shares up to 16 external channels, performing conversions in single-
shot or scan modes. In scan mode, automatic conversion is performed on a selected group
of analog inputs.
Additional logic functions embedded in the ADC interface allow:
Simultaneous sample and hold
Interleaved sample and hold
Single shunt
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
The events generated by the general-purpose timers (TIMx) and the advanced-control timer
(TIM1) can be internally connected to the ADC start trigger, injection trigger, and DMA
trigger respectively, to allow the application to synchronize A/D conversion and timers.
2.3.23 Temperature sensor
The temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally
connected to the ADC12_IN16 input channel which is used to convert the sensor output
voltage into a digital value.
2.3.24 Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP Interface is embedded. and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a
specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
E: m: 2 :MW fl iiivwi; 5%
STM32F103x8, STM32F103xB Description
Doc ID 13587 Rev 10 19/91
Figure 1. STM32F103xx performance line block diagram
1. TA = –40 °C to +105 °C (junction temperature up to 125 °C).
2. AF = alternate function on I/O port pin.
USBDP/CAN_TX
PA[15:0]
EXTI
WWDG
12bit ADC1
16AF
JTDI
JTCK/SWCLK
JTMS/SWDIO
NJTRSTTRST
JTDO
NRST
V
DD
= 2 to 3.6V
80AF
PB[15:0]
PC[15:0]
AHB2
MOSI,MISO,SCK,NSS
SRAM
2x(8x16bit)
WAKEUP
GPIOA
GPIOB
GPIOC
F
max
: 72 M
Hz
V
SS
SCL,SDA
I2C2
V
REF+
GP DMA
TIM2
TIM3
XTAL OSC
4-16 MHz
XTAL 32 kHz
OSC_IN
OSC_OUT
OSC32_OUT
OSC32_IN
PLL &
APB1 : F
max
=24 / 36 MHz
PCLK1
HCLK CLOCK
MANAGT
PCLK2
as AF
as AF
Flash 128 KB
VOLT. REG.
3.3V TO 1.8V
POWER
Backup interf ace
as AF
TIM 4
BusMatrix
64 bit
Interface
20 KB
RTC
RC 8 MHz
Cortex-M3 CPU
Ibu s
Dbus
pbu s
obl
flash
SRAM 512B
Trace
Controlle r
USART1
USART2
SPI2
bxCAN
7 ch annels
Back up
reg
4 Chann els
TIM1
3 compl. Chann el s
SCL,SDA,SMBA
I2C1
as AF
RX,TX, CTS, RTS,
USART3
Temp sensor
V
REF-
PD[15:0] GPIOD
PE[15:0] GPIOE
AHB:F max=48/72 MHz
ETR and BKIN
4 Chann els
4 Chann els
4 Chann els
FCLK
RC 40 kHz
Stand by
IWDG
@VBAT
POR / PDR
SUPPLY
@VDDA
VDDA
VSSA
@VDDA
V
BAT
RX,TX, CTS, RTS,
Smart Card as AF
RX,TX, CTS, RTS,
CK, SmartCard as AF
APB2 : F
max
=48 / 72 MHz
NVIC
SPI1
MOSI,MISO,
SCK,NSS as AF
12bit ADC2
IF
IFIF
interface
@VDDA
SUPERVISION
PVD
Rst
Int
@VDD
AHB2
APB2 APB 1
AWU TAMPER-RTC
@VDD
USB 2.0 FS USBDM/CAN_RX
System
ai14390d
TRACECLK
TRACED[0:3]
as AS
SW/JTAG
TPIU
Trace/trig
CK, SmartCard as AF
Description STM32F103x8, STM32F103xB
20/91 Doc ID 13587 Rev 10
Figure 2. Clock tree
1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is
64 MHz.
2. For the USB function to be available, both HSE and PLL must be enabled, with the CPU running at either
48 MHz or 72 MHz.
3. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz, 28 MHz or 56 MHz.
HSE OSC
4-16 MHz
OSC_IN
OSC_OUT
OSC32_IN
OSC32_OUT
LSE OSC
32.768 kHz
HSI RC
8 MHz
LSI RC
40 kHz
to Independent Watchdog (IWDG)
PLL
x2, x3, x4
PLLMUL
Legend:
MCO
Clock Output
Main
PLLXTPRE
/2
..., x16 AHB
Prescaler
/1, 2..512
/2 PLLCLK
HSI
HSE
APB1
Prescaler
/1, 2, 4, 8, 16
ADC
Prescaler
/2, 4, 6, 8 ADCCLK
PCLK1
HCLK
PLLCLK
to AHB bus, core,
memory and DMA
USBCLK
to USB interface
to TIM2, 3
and 4
USB
Prescaler
/1, 1.5
to ADC
LSE
LSI
HSI
/128
/2
HSI
HSE
peripherals
to APB1
Peripheral Clock
Enable (13 bits)
Enable (3 bits)
Peripheral Clock
APB2
Prescaler
/1, 2, 4, 8, 16
PCLK2
to TIM1
peripherals
to APB2
Peripheral Clock
Enable (11 bits)
Enable (1 bit)
Peripheral Clock
48 MHz
72 MHz max
72 MHz
72 MHz max
36 MHz max
to RTC
PLLSRC SW
MCO
CSS
to Cortex System timer
/8
Clock
Enable (3 bits)
SYSCLK
max
RTCCLK
RTCSEL[1:0]
TIM1CLK
TIMXCLK
IWDGCLK
SYSCLK
FCLK Cortex
free running clock
TIM2,3, 4
If (APB1 prescaler =1) x1
else x2
TIM1 timer
If (APB2 prescaler =1) x1
else x2
HSE = high-speed external clock signal
HSI = high-speed internal clock signal
LSI = low-speed internal clock signal
LSE = low-speed external clock signal
ai14903
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STM32F103x8, STM32F103xB Pinouts and pin description
Doc ID 13587 Rev 10 21/91
3 Pinouts and pin description
Figure 3. STM32F103xx performance line LFBGA100 ballout
AI16001c
PE10
PC14-
OSC32_IN
PC5PA5
PC3
PB4
PE15
PB2
PC4PA4
H
PE14
PE11PE7
D PD4
PD3
PB8PE3
C
PD0
PC12
PE5
PB5
PC0
PE2
B PC11PD2
PC15-
OSC32_OUT
PB7
PB6
A
87654321
VSS_5
OSC_IN
OSC_OUT VDD_5
G
F
E
PC1
VREF–
PC13-
TAMPER-RTC PB9 PA15
PB3
PE4 PE1
PE0
VSS_1 PD1PE6NRST PC2 VSS_3
VSS_4
NCVDD_3
VDD_4
PB15
VBAT PD5
PD6
BOOT0 PD7
VSS_2
VSSA
PA1
VDD_2 VDD_1
PB14
PA0-WKUP
109
K
J
PD10
PD11
PA8
PA9
PA10
PA11
PA12
PC10
PA13
PA14
PC9 PC7
PC6
PD15
PC8
PD14
PE12
PB1PA7 PB11
PE8
PB0PA6 PB10
PE13PE9VDDA
PB13
VREF+
PA3 PB12
PA2
PD8
PD9 PD13
PD12
Pinouts and pin description STM32F103x8, STM32F103xB
22/91 Doc ID 13587 Rev 10
Figure 4. STM32F103xx performance line LQFP100 pinout
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDD_2
VSS_2
NC
PA 13
PA 12
PA 11
PA 10
PA 9
PA 8
PC9
PC8
PC7
PC6
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
PB15
PB14
PB13
PB12
PA 3
VSS_4
VDD_4
PA 4
PA 5
PA 6
PA 7
PC4
PC5
PB0
PB1
PB2
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PB10
PB11
VSS_1
VDD_1
VDD_3
VSS_3
PE1
PE0
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PC12
PC11
PC10
PA15
PA14
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PE2
PE3
PE4
PE5
PE6
VBAT
PC13-TAMPER-RTC
PC14-OSC32_IN
PC15-OSC32_OUT
VSS_5
VDD_5
OSC_IN
OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA
VREF-
VREF+
VDDA
PA 0 - W K UP
PA1
PA2
ai14391
LQFP100
STM32F103x8, STM32F103xB Pinouts and pin description
Doc ID 13587 Rev 10 23/91
Figure 5. STM32F103xx performance line LQFP64 pinout
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17 18 19 20 21 22 23 24 29 30 31 3225 26 27 28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VBAT
PC13-TAMPER-RTC
PC14-OSC32_IN
PC15-OSC32_OUT
PD0 OSC_IN
PD1 OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA
VDDA
PA 0 - W K U P
PA1
PA2
VDD_3
VSS_3
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PD2
PC12
PC11
PC10
PA 15
PA 14
VDD_2
VSS_2
PA 13
PA 12
PA 11
PA 10
PA 9
PA 8
PC9
PC8
PC7
PC6
PB15
PB14
PB13
PB12
PA3
VSS_4
VDD_4
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PB10
PB11
VSS_1
VDD_1
LQFP64
ai14392
.’ PAz‘; J PAS ,
Pinouts and pin description STM32F103x8, STM32F103xB
24/91 Doc ID 13587 Rev 10
Figure 6. STM32F103xx performance line TFBGA64 ballout
STM32F103x8, STM32F103xB Pinouts and pin description
Doc ID 13587 Rev 10 25/91
Figure 7. STM32F103xx performance line LQFP48 pinout
Figure 8. STM32F103xx Performance Line VFQFPN36 pinout
44 43 42 41 40 39 38 37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
12
13 14 15 16 17 18 19 20 21 22
1
2
3
4
5
6
7
8
9
10
11
48 47 46 45
PA 3
PA 4
PA 5
PA 6
PA 7
PB0
PB1
PB2
PB10
PB11
VSS_1
VDD_1
VDD_2
VSS_2
PA1 3
PA1 2
PA1 1
PA1 0
PA9
PA8
PB15
PB14
PB13
PB12
VBAT
PC13-TAMPER-RTC
PC14-OSC32_IN
PC15-OSC32_OUT
PD0-OSC_IN
PD1-OSC_OUT
NRST
VSSA
VDDA
PA 0 - W K U P
PA 1
PA 2
VDD_3
VSS_3
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PA1 5
PA1 4
LQFP48
ai14393b
V
SS_3
BOOT0
PB7
PB6
PB5
PB4
PB3
PA15
PA14
36 35 34 33 32 31 30 29 28
V
DD_3
127 V
DD_2
OSC_IN/PD0 226 V
SS_2
OSC_OUT/PD1 325 PA13
NRST 4
QFN36
24 PA12
V
SSA
523 PA11
V
DDA
622 PA10
PA0-WKUP 721 PA 9
PA 1 820 PA 8
PA 2 9 19 V
DD_1
10 11 12 13 14 15 16 17 18
PA 3
PA 4
PA 5
PA 6
PA 7
PB0
PB1
PB2
V
SS_1
ai14654
Pinouts and pin description STM32F103x8, STM32F103xB
26/91 Doc ID 13587 Rev 10
Table 5. Medium-density STM32F103xx pin definitions
Pins
Pin name
Type(1)
I / O Level(2)
Main
function(3)
(after reset)
Alternate functions
LFBGA100
LQFP48
TFBGA64
LQFP64
LQFP100
VFQFPN36
Default Remap
A3 - - 1 - PE2 I/O FT PE2 TRACECK
B3 - - 2 - PE3 I/O FT PE3 TRACED0
C3 - - 3 - PE4 I/O FT PE4 TRACED1
D3 - - 4 - PE5 I/O FT PE5 TRACED2
E3 - - 5 - PE6 I/O FT PE6 TRACED3
B2 1 B2 1 6 - VBAT SV
BAT
A2 2 A2 2 7 - PC13-TAMPER-
RTC(4) I/O PC13(5) TAMPER-RTC
A1 3 A1 3 8 - PC14-OSC32_IN(4) I/O PC14(5) OSC32_IN
B1 4 B1 4 9 - PC15-
OSC32_OUT(4) I/O PC15(5) OSC32_OUT
C2---10- V
SS_5 SV
SS_5
D2---11- V
DD_5 SV
DD_5
C1 5 C1 5 12 2 OSC_IN I OSC_IN
D1 6 D1 6 13 3 OSC_OUT O OSC_OUT
E1 7 E1 7 14 4 NRST I/O NRST
F1 - E3 8 15 - PC0 I/O PC0 ADC12_IN10
F2 - E2 9 16 - PC1 I/O PC1 ADC12_IN11
E2 - F2 10 17 - PC2 I/O PC2 ADC12_IN12
F3 - -(6) 11 18 - PC3 I/O PC3 ADC12_IN13
G1 8 F1 12 19 5 VSSA SV
SSA
H1---20- V
REF- SV
REF-
J1 - G1(6) -21- V
REF+ SV
REF+
K1 9 H1 13 22 6 VDDA SV
DDA
G2 10 G2 14 23 7 PA0-WKUP I/O PA0
WKUP/
USART2_CTS(7)/
ADC12_IN0/
TIM2_CH1_ETR(7)
H2 11 H2 15 24 8 PA1 I/O PA1
USART2_RTS(7)/
ADC12_IN1/
TIM2_CH2(7)
J2 12 F3 16 25 9 PA2 I/O PA2
USART2_TX(7)/
ADC12_IN2/
TIM2_CH3(7)
STM32F103x8, STM32F103xB Pinouts and pin description
Doc ID 13587 Rev 10 27/91
K2 13 G3 17 26 10 PA3 I/O PA3
USART2_RX(7)/
ADC12_IN3/
TIM2_CH4(7)
E4 - C2 18 27 - VSS_4 SV
SS_4
F4 - D2 19 28 - VDD_4 SV
DD_4
G3 14 H3 20 29 11 PA4 I/O PA4
SPI1_NSS(7)/
USART2_CK(7)/
ADC12_IN4
H3 15 F4 21 30 12 PA5 I/O PA5 SPI1_SCK(7)/
ADC12_IN5
J3 16 G4 22 31 13 PA6 I/O PA6
SPI1_MISO(7)/
ADC12_IN6/
TIM3_CH1(7)
TIM1_BKIN
K3 17 H4 23 32 14 PA7 I/O PA7
SPI1_MOSI(7)/
ADC12_IN7/
TIM3_CH2(7)
TIM1_CH1N
G4 - H5 24 33 PC4 I/O PC4 ADC12_IN14
H4 - H6 25 34 PC5 I/O PC5 ADC12_IN15
J4 18 F5 26 35 15 PB0 I/O PB0 ADC12_IN8/
TIM3_CH3(7) TIM1_CH2N
K4 19 G5 27 36 16 PB1 I/O PB1 ADC12_IN9/
TIM3_CH4(7) TIM1_CH3N
G5 20 G6 28 37 17 PB2 I/O FT PB2/BOOT1
H5 - - - 38 - PE7 I/O FT PE7 TIM1_ETR
J5 - - - 39 - PE8 I/O FT PE8 TIM1_CH1N
K5 - - - 40 - PE9 I/O FT PE9 TIM1_CH1
G6 - - - 41 - PE10 I/O FT PE10 TIM1_CH2N
H6 - - - 42 - PE11 I/O FT PE11 TIM1_CH2
J6 - - - 43 - PE12 I/O FT PE12 TIM1_CH3N
K6 - - - 44 - PE13 I/O FT PE13 TIM1_CH3
G7 - - - 45 - PE14 I/O FT PE14 TIM1_CH4
H7 - - - 46 - PE15 I/O FT PE15 TIM1_BKIN
J7 21 G7 29 47 - PB10 I/O FT PB10 I2C2_SCL/
USART3_TX(7) TIM2_CH3
K7 22 H7 30 48 - PB11 I/O FT PB11 I2C2_SDA/
USART3_RX(7) TIM2_CH4
E7 23 D6 31 49 18 VSS_1 SV
SS_1
Table 5. Medium-density STM32F103xx pin definitions (continued)
Pins
Pin name
Type(1)
I / O Level(2)
Main
function(3)
(after reset)
Alternate functions
LFBGA100
LQFP48
TFBGA64
LQFP64
LQFP100
VFQFPN36
Default Remap
Pinouts and pin description STM32F103x8, STM32F103xB
28/91 Doc ID 13587 Rev 10
F7 24 E6 32 50 19 VDD_1 SV
DD_1
K8 25 H8 33 51 - PB12 I/O FT PB12
SPI2_NSS/
I2C2_SMBAl/
USART3_CK(7)/
TIM1_BKIN(7)
J8 26 G8 34 52 - PB13 I/O FT PB13
SPI2_SCK/
USART3_CTS(7)/
TIM1_CH1N (7)
H8 27 F8 35 53 - PB14 I/O FT PB14
SPI2_MISO/
USART3_RTS(7)
TIM1_CH2N (7)
G8 28 F7 36 54 - PB15 I/O FT PB15 SPI2_MOSI/
TIM1_CH3N(7)
K9 - - - 55 - PD8 I/O FT PD8 USART3_TX
J9 - - - 56 - PD9 I/O FT PD9 USART3_RX
H9 - - - 57 - PD10 I/O FT PD10 USART3_CK
G9 - - - 58 - PD11 I/O FT PD11 USART3_CTS
K10 - - - 59 - PD12 I/O FT PD12 TIM4_CH1 /
USART3_RTS
J10 - - - 60 - PD13 I/O FT PD13 TIM4_CH2
H10 - - - 61 - PD14 I/O FT PD14 TIM4_CH3
G10 - - - 62 - PD15 I/O FT PD15 TIM4_CH4
F10 - F6 37 63 - PC6 I/O FT PC6 TIM3_CH1
E10 E7 38 64 - PC7 I/O FT PC7 TIM3_CH2
F9 E8 39 65 - PC8 I/O FT PC8 TIM3_CH3
E9 - D8 40 66 - PC9 I/O FT PC9 TIM3_CH4
D9 29 D7 41 67 20 PA8 I/O FT PA8 USART1_CK/
TIM1_CH1(7)/MCO
C9 30 C7 42 68 21 PA9 I/O FT PA9 USART1_TX(7)/
TIM1_CH2(7)
D1031C6436922 PA10 I/OFT PA10 USART1_RX(7)/
TIM1_CH3(7)
C1032C8447023 PA11 I/OFT PA11
USART1_CTS/
CANRX(7)/ USBDM
TIM1_CH4(7)
B1033B8457124 PA12 I/OFT PA12
USART1_RTS/
CANTX(7) //USBDP
TIM1_ETR(7)
Table 5. Medium-density STM32F103xx pin definitions (continued)
Pins
Pin name
Type(1)
I / O Level(2)
Main
function(3)
(after reset)
Alternate functions
LFBGA100
LQFP48
TFBGA64
LQFP64
LQFP100
VFQFPN36
Default Remap
STM32F103x8, STM32F103xB Pinouts and pin description
Doc ID 13587 Rev 10 29/91
A10 34 A8 46 72 25 PA13 I/O FT JTMS/SWDIO PA13
F8 - - - 73 - Not connected
E6 35 D5 47 74 26 VSS_2 SV
SS_2
F6 36 E5 48 75 27 VDD_2 SV
DD_2
A9 37 A7 49 76 28 PA14 I/O FT JTCK/SWCLK PA14
A8 38 A6 50 77 29 PA15 I/O FT JTDI TIM2_CH1_ETR/
PA 15 /SPI 1 _ N S S
B9 - B7 51 78 PC10 I/O FT PC10 USART3_TX
B8 - B6 52 79 PC11 I/O FT PC11 USART3_RX
C8 - C5 53 80 PC12 I/O FT PC12 USART3_CK
D8 5 C1 5 81 2 PD0 I/O FT OSC_IN(8) CANRX
E8 6 D1 6 82 3 PD1 I/O FT OSC_OUT(8) CANTX
B7 B5 54 83 - PD2 I/O FT PD2 TIM3_ETR
C7 - - - 84 - PD3 I/O FT PD3 USART2_CTS
D7 - - - 85 - PD4 I/O FT PD4 USART2_RTS
B6 - - - 86 - PD5 I/O FT PD5 USART2_TX
C6 - - - 87 - PD6 I/O FT PD6 USART2_RX
D6 - - - 88 - PD7 I/O FT PD7 USART2_CK
A7 39 A5 55 89 30 PB3 I/O FT JTDO
TIM2_CH2 / PB3
TRACESWO
SPI1_SCK
A6 40 A4 56 90 31 PB4 I/O FT JNTRST TIM3_CH1/ PB4/
SPI1_MISO
C5 41 C4 57 91 32 PB5 I/O PB5 I2C1_SMBAl TIM3_CH2 /
SPI1_MOSI
B5 42 D3 58 92 33 PB6 I/O FT PB6 I2C1_SCL(7)/
TIM4_CH1(7) USART1_TX
A5 43 C3 59 93 34 PB7 I/O FT PB7 I2C1_SDA(7)/
TIM4_CH2(7) USART1_RX
D5 44 B4 60 94 35 BOOT0 I BOOT0
B4 45 B3 61 95 - PB8 I/O FT PB8 TIM4_CH3(7) I2C1_SCL /
CANRX
A4 46 A3 62 96 - PB9 I/O FT PB9 TIM4_CH4(7) I2C1_SDA/
CANTX
Table 5. Medium-density STM32F103xx pin definitions (continued)
Pins
Pin name
Type(1)
I / O Level(2)
Main
function(3)
(after reset)
Alternate functions
LFBGA100
LQFP48
TFBGA64
LQFP64
LQFP100
VFQFPN36
Default Remap
Pinouts and pin description STM32F103x8, STM32F103xB
30/91 Doc ID 13587 Rev 10
D4 - - - 97 - PE0 I/O FT PE0 TIM4_ETR
C4 - - - 98 - PE1 I/O FT PE1
E5 47 D4 63 99 36 VSS_3 SV
SS_3
F5 48 E4 64 100 1 VDD_3 SV
DD_3
1. I = input, O = output, S = supply, HiZ = high impedance.
2. FT = 5 V tolerant.
3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower
number of peripheral that is included. For example, if a device has only one SPI and two USARTs, they will be called SPI1
and USART1 & USART2, respectively. Refer to Table 2 on page 10.
4. PC13, PC14 and PC15 are supplied through the power switch and since the switch only sinks a limited amount of current
(3 mA), the use of GPIOs PC13 to PC15 is restricted: only one I/O at a time can be used as an output, the speed has to be
limited to 2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive an LED).
5. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even
after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the
Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the
STMicroelectronics website: www.st.com.
6. Unlike in the LQFP64 package, there is no PC3 in the TFBGA64 package. The VREF+ functionality is provided instead.
7. This alternate function can be remapped by software to some other port pins (if available on the used package). For more
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available
from the STMicroelectronics website: www.st.com.
8. The pins number 2 and 3 in the VFQFPN36 package, 5 and 6 in the LQFP48 and LQFP64 packages, and C1 and C2 in the
TFBGA64 package are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be
remapped by software on these pins. For the LQFP100 package, PD0 and PD1 are available by default, so there is no
need for remapping. For more details, refer to the Alternate function I/O and debug configuration section in the
STM32F10xxx reference manual.
The use of PD0 and PD1 in output mode is limited as they can only be used at 50 MHz in output mode.
Table 5. Medium-density STM32F103xx pin definitions (continued)
Pins
Pin name
Type(1)
I / O Level(2)
Main
function(3)
(after reset)
Alternate functions
LFBGA100
LQFP48
TFBGA64
LQFP64
LQFP100
VFQFPN36
Default Remap
STM32F103x8, STM32F103xB Memory mapping
Doc ID 13587 Rev 10 31/91
4 Memory mapping
The memory map is shown in Figure 9.
Figure 9. Memory map
reserved
0x4000 0000
0x4000 0400
0x4000 0800
0x4000 0C00
0x4000 2800
0x4000 2C00
0x4000 3000
0x4000 3400
0x4000 3800
0x4000 3C00
0x4000 4400
0x4000 4800
0x4000 4C00
0x4001 0C00
0x4001 1000
0x4001 1400
0x4001 1800
0x4002 1400
APB memory space
DMA
0x4002 1000
TIM2
Reserved
0x4001 0800
0x4001 1C00
0x4001 2400
0x4001 2800
0x4001 2C00
0x4001 3000
0x4001 3400
0x4001 3800
TIM3
TIM4
reserved
RTC
WWDG
IWDG
reserved
SPI2
USART2
USART3
AFIO
Port A
Port C
Port D
rese rve d
ADC1
reserved
USART1
reserved
0x4002 0400
0x4002 0000
0x4001 3C00
0x4000 5400
0x4000 5800
reserved
ADC2
TIM1
SPI1
reserved
I2C1
BKP
0x4000 6000
0x4000 5C00
Port E
PWR
Port B
I2C2
reserved
bxCAN
EXTI
reserved
RCC
reserved
Flash Interface
reserved
reserved
reserved
0x4000 6400
0x4000 6800
0x4000 6C00
0x4000 7000
0x4000 7400
0x4001 0000
0x4001 0400
0x4002 2000
0x4002 2400
0x4002 3000
0x4002 3400
0x6000 0000
0xE010 0000
reserved
0xFFFF FFFF
USB Registers
CRC
0
1
2
3
4
5
6
7
0x2000 0000
0x4000 0000
0x6000 0000
0x8000 0000
0xA000 0000
0xC000 0000
0xE000 0000
0xFFFF FFFF
0x0000 0000
Peripherals
SRAM
Flash memory
rese rved
rese rved
0x0800 0000
0x0801 FFFF
0x1FFF F000
0x1FFF FFFF
System memory
Option Bytes
0x1FFF F800
0x1FFF F80F
Cortex- M3 Internal
Peripherals
0xE010 0000
ai14394f
shared 512 byte
USB/CAN SRAM
Aliased to Flash or system
memory depending on
BOOT pins
0x0000 0000
Electrical characteristics STM32F103x8, STM32F103xB
32/91 Doc ID 13587 Rev 10
5 Electrical characteristics
5.1 Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
5.1.1 Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3).
5.1.2 Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the
2VVDD 3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2).
5.1.3 Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
5.1.4 Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 10.
5.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 11.
STM32F103x8, STM32F103xB Electrical characteristics
Doc ID 13587 Rev 10 33/91
5.1.6 Power supply scheme
Figure 12. Power supply scheme
Caution: In Figure 12, the 4.7 µF capacitor must be connected to VDD3.
Figure 10. Pin loading conditions Figure 11. Pin input voltage
ai14141
C = 50 pF
STM32F103xx pin
ai14142
STM32F103xx pin
VIN
ai14125d
VDD
1/2/3/4/5
Analog:
RCs, PLL,
...
Power switch
VBAT
GP I/O s
OUT
IN
Kernel logic
(CPU,
Digital
& Memories)
Backup circuitry
(OSC32K,RTC,
Backup registers)
Wake-up logic
5 × 100 nF
+ 1 × 4.7 µF
1.8-3.6V
Regulator
VSS
1/2/3/4/5
VDDA
VREF+
VREF-
VSSA
ADC
Level shifter
IO
Logic
VDD
10 nF
+ 1 µF
VREF
10 nF
+ 1 µF
VDD
Electrical characteristics STM32F103x8, STM32F103xB
34/91 Doc ID 13587 Rev 10
5.1.7 Current consumption measurement
Figure 13. Current consumption measurement scheme
5.2 Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 6: Voltage characteristics,
Table 7: Current characteristics, and Table 8: Thermal characteristics may cause permanent
damage to the device. These are stress ratings only and functional operation of the device
at these conditions is not implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
ai14126
VBAT
VDD
VDDA
IDD_VBAT
IDD
Table 6. Voltage characteristics
Symbol Ratings Min Max Unit
VDD–VSS
External main supply voltage (including VDDA
and VDD)(1)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
–0.3 4.0
V
VIN
Input voltage on five volt tolerant pin(2)
2. IINJ(PIN) must never be exceeded (see Table 7: Current characteristics). This is implicitly insured if VIN
maximum is respected. If VIN maximum cannot be respected, the injection current must be limited
externally to the IINJ(PIN) value. A positive injection is induced by VIN> VINmax while a negative injection is
induced by VIN < VSS.
VSS 0.3 +5.5
Input voltage on any other pin(2) VSS 0.3 VDD+0.3
|VDDx| Variations between different VDD power pins 50 mV
|VSSX VSS| Variations between all the different ground pins 50
VESD(HBM)
Electrostatic discharge voltage (human body
model)
see Section 5.3.11:
Absolute maximum ratings
(electrical sensitivity)
STM32F103x8, STM32F103xB Electrical characteristics
Doc ID 13587 Rev 10 35/91
5.3 Operating conditions
5.3.1 General operating conditions
Table 7. Current characteristics
Symbol Ratings Max. Unit
IVDD Total current into VDD/VDDA power lines (source)(1)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
150
mA
IVSS Total current out of VSS ground lines (sink)(1) 150
IIO
Output current sunk by any I/O and control pin 25
Output current source by any I/Os and control pin 25
IINJ(PIN) (2)(3)
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS.
3. Negative injection disturbs the analog performance of the device. See note in Section 5.3.17: 12-bit ADC
characteristics.
Injected current on NRST pin ± 5
Injected current on HSE OSC_IN and LSE OSC_IN pins ± 5
Injected current on any other pin(4)
4. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values). These results are based on
characterization with IINJ(PIN) maximum current injection on four I/O port pins of the device.
± 5
IINJ(PIN)(2) Total injected current (sum of all I/O and control pins)(4) ± 25
Table 8. Thermal characteristics
Symbol Ratings Value Unit
TSTG Storage temperature range –65 to +150 °C
TJMaximum junction temperature 150 °C
Table 9. General operating conditions
Symbol Parameter Conditions Min Max Unit
fHCLK Internal AHB clock frequency 0 72
MHzfPCLK1 Internal APB1 clock frequency 0 36
fPCLK2 Internal APB2 clock frequency 0 72
VDD Standard operating voltage 2 3.6 V
VDDA(1)
Analog operating voltage
(ADC not used) Must be the same potential
as VDD(2)
23.6
V
Analog operating voltage
(ADC used) 2.4 3.6
VBAT Backup operating voltage 1.8 3.6 V
8
Electrical characteristics STM32F103x8, STM32F103xB
36/91 Doc ID 13587 Rev 10
5.3.2 Operating conditions at power-up / power-down
Subject to general operating conditions for TA.
Table 10. Operating conditions at power-up / power-down
5.3.3 Embedded reset and power control block characteristics
The parameters given in Ta b le 1 1 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Ta bl e 9 .
PD
Power dissipation at TA = 85 °C
for suffix 6 or TA = 105 °C for
suffix 7(3)
LFBGA100 454
mW
LQFP100 434
TFBGA64 308
LQFP64 444
LQFP48 363
VFQFPN36 1110
TA
Ambient temperature for 6
suffix version
Maximum power dissipation –40 85 °C
Low power dissipation(4) –40 105
Ambient temperature for 7
suffix version
Maximum power dissipation –40 105 °C
Low power dissipation(4) –40 125
TJ Junction temperature range 6 suffix version –40 105 °C
7 suffix version –40 125
1. When the ADC is used, refer to Table 45: ADC characteristics.
2. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV
between VDD and VDDA can be tolerated during power-up and operation.
3. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 6.2: Thermal
characteristics on page 81).
4. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see
Table 6.2: Thermal characteristics on page 81).
Table 9. General operating conditions (continued)
Symbol Parameter Conditions Min Max Unit
Symbol Parameter Conditions Min Max Unit
tVDD
VDD rise time rate 0 µs/V
VDD fall time rate 20
STM32F103x8, STM32F103xB Electrical characteristics
Doc ID 13587 Rev 10 37/91
Table 11. Embedded reset and power control block characteristics
Symbol Parameter Conditions Min Typ Max Unit
VPVD
Programmable voltage
detector level selection
PLS[2:0]=000 (rising edge) 2.1 2.18 2.26 V
PLS[2:0]=000 (falling edge) 2 2.08 2.16 V
PLS[2:0]=001 (rising edge) 2.19 2.28 2.37 V
PLS[2:0]=001 (falling edge) 2.09 2.18 2.27 V
PLS[2:0]=010 (rising edge) 2.28 2.38 2.48 V
PLS[2:0]=010 (falling edge) 2.18 2.28 2.38 V
PLS[2:0]=011 (rising edge) 2.38 2.48 2.58 V
PLS[2:0]=011 (falling edge) 2.28 2.38 2.48 V
PLS[2:0]=100 (rising edge) 2.47 2.58 2.69 V
PLS[2:0]=100 (falling edge) 2.37 2.48 2.59 V
PLS[2:0]=101 (rising edge) 2.57 2.68 2.79 V
PLS[2:0]=101 (falling edge) 2.47 2.58 2.69 V
PLS[2:0]=110 (rising edge) 2.66 2.78 2.9 V
PLS[2:0]=110 (falling edge) 2.56 2.68 2.8 V
PLS[2:0]=111 (rising edge) 2.76 2.88 3 V
PLS[2:0]=111 (falling edge) 2.66 2.78 2.9 V
VPVDhyst(2) PVD hysteresis 100 mV
VPOR/PDR
Power on/power down
reset threshold
Falling edge 1.8(1)
1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
1.88 1.96 V
Rising edge 1.84 1.92 2.0 V
VPDRhyst(2) PDR hysteresis 40 mV
TRSTTEMPO(2)
2. Guaranteed by design, not tested in production.
Reset temporization 1 2.5 4.5 ms
Electrical characteristics STM32F103x8, STM32F103xB
38/91 Doc ID 13587 Rev 10
5.3.4 Embedded reference voltage
The parameters given in Ta b le 1 2 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Ta bl e 9 .
5.3.5 Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 13: Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to Dhrystone 2.1 code.
Maximum current consumption
The MCU is placed under the following conditions:
All I/O pins are in input mode with a static value at VDD or VSS (no load)
All peripherals are disabled except when explicitly mentioned
The Flash memory access time is adjusted to the fHCLK frequency (0 wait state from 0
to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above)
Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling)
When the peripherals are enabled fPCLK1 = fHCLK/2, fPCLK2 = fHCLK
The parameters given in Ta b le 1 3 , Ta bl e 1 4 and Ta b l e 1 5 are derived from tests performed
under ambient temperature and VDD supply voltage conditions summarized in Ta bl e 9 .
Table 12. Embedded internal reference voltage
Symbol Parameter Conditions Min Typ Max Unit
VREFINT Internal reference voltage –40 °C < TA < +105 °C 1.16 1.20 1.26 V
–40 °C < TA < +85 °C 1.16 1.20 1.24 V
TS_vrefint(1)
1. Shortest sampling time can be determined in the application by multiple iterations.
ADC sampling time when
reading the internal reference
voltage
5.1 17.1(2)
2. Guaranteed by design, not tested in production.
µs
STM32F103x8, STM32F103xB Electrical characteristics
Doc ID 13587 Rev 10 39/91
Table 13. Maximum current consumption in Run mode, code with data processing
running from Flash
Symbol Parameter Conditions fHCLK
Max(1)
1. Based on characterization, not tested in production.
Unit
TA = 85 °C TA = 105 °C
IDD
Supply current in
Run mode
External clock(2), all
peripherals enabled
2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
72 MHz 50 50.3
mA
48 MHz 36.1 36.2
36 MHz 28.6 28.7
24 MHz 19.9 20.1
16 MHz 14.7 14.9
8 MHz 8.6 8.9
External clock(2), all
peripherals disabled
72 MHz 32.8 32.9
48 MHz 24.4 24.5
36 MHz 19.8 19.9
24 MHz 13.9 14.2
16 MHz 10.7 11
8 MHz 6.8 7.1
Table 14. Maximum current consumption in Run mode, code with data processing
running from RAM
Symbol Parameter Conditions fHCLK
Max(1)
1. Based on characterization, tested in production at VDD max, fHCLK max.
Unit
TA = 85 °C TA = 105 °C
IDD
Supply
current in
Run mode
External clock(2), all
peripherals enabled
2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
72 MHz 48 50
mA
48 MHz 31.5 32
36 MHz 24 25.5
24 MHz 17.5 18
16 MHz 12.5 13
8 MHz 7.5 8
External clock(2), all
peripherals disabled
72 MHz 29 29.5
48 MHz 20.5 21
36 MHz 16 16.5
24 MHz 11.5 12
16 MHz 8.5 9
8 MHz 5.5 6
Electrical characteristics STM32F103x8, STM32F103xB
40/91 Doc ID 13587 Rev 10
Figure 14. Typical current consumption in Run mode versus frequency (at 3.6 V) -
code with data processing running from RAM, peripherals enabled
Figure 15. Typical current consumption in Run mode versus frequency (at 3.6 V) -
code with data processing running from RAM, peripherals disabled
0
5
10
15
20
25
30
35
40
45
-40 0 25 70 85 105
Temperature (°C)
Consumption (mA)
72 MHz
36 MHz
16 MHz
8 MHz
0
5
10
15
20
25
30
-40 0 25 70 85 105
Temperature (°C)
Consumption (mA)
72 MHz
36 MHz
16 MHz
8 MHz
STM32F103x8, STM32F103xB Electrical characteristics
Doc ID 13587 Rev 10 41/91
Table 15. Maximum current consumption in Sleep mode, code running from Flash
or RAM
Symbol Parameter Conditions fHCLK
Max(1)
1. based on characterization, tested in production at VDD max, fHCLK max with peripherals enabled.
Unit
TA = 85 °C TA = 105 °C
IDD
Supply current in
Sleep mode
External clock(2), all
peripherals enabled
2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
72 MHz 30 32
mA
48 MHz 20 20.5
36 MHz 15.5 16
24 MHz 11.5 12
16 MHz 8.5 9
8 MHz 5.5 6
External clock(2), all
peripherals disabled
72 MHz 7.5 8
48 MHz 6 6.5
36 MHz 5 5.5
24 MHz 4.5 5
16 MHz 4 4.5
8 MHz 3 4
Electrical characteristics STM32F103x8, STM32F103xB
42/91 Doc ID 13587 Rev 10
Figure 16. Typical current consumption in Stop mode with regulator in Run mode versus
temperature at VDD = 3.3 V and 3.6 V
Table 16. Typical and maximum current consumptions in Stop and Standby modes
Symbol Parameter Conditions
Typ(1) Max
Unit
VDD/VBAT
= 2.4 V
VDD/VBAT
= 3.3 V
TA =
85 °C
TA =
105 °C
IDD
Supply current in
Stop mode
Regulator in Run mode, low-speed and
high-speed internal RC oscillators and
high-speed oscillator OFF (no
independent watchdog)
23.5 24 200 370
µA
Regulator in Low Power mode, low-
speed and high-speed internal RC
oscillators and high-speed oscillator
OFF (no independent watchdog)
13.5 14 180 340
Supply current in
Standby mode
Low-speed internal RC oscillator and
independent watchdog ON 2.6 3.4 - -
Low-speed internal RC oscillator ON,
independent watchdog OFF 2.4 3.2 - -
Low-speed internal RC oscillator and
independent watchdog OFF, low-speed
oscillator and RTC OFF
1.7 2 4 5
IDD_VBAT
Backup domain
supply current Low-speed oscillator and RTC ON 1.1 1.4 1.9(2) 2.2
1. Typical values are measured at TA = 25 °C.
2. Based on characterization, not tested in production.
0
50
100
150
200
250
300
-45 25 70 90 110
Temperature (°C)
Consumption (µA)
3.3 V
3.6 V
STM32F103x8, STM32F103xB Electrical characteristics
Doc ID 13587 Rev 10 43/91
Figure 17. Typical current consumption in Stop mode with regulator in Low-power mode versus
temperature at VDD = 3.3 V and 3.6 V
Figure 18. Typical current consumption in Standby mode versus temperature at
VDD = 3.3 V and 3.6 V
0
50
100
150
200
250
300
-40 0 25 70 85 105
Temperature (°C)
Consumption (µA)
3.3 V
3.6 V
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
–45 °C 25 °C 85 °C 105 °C
Temperature (°C)
Consumption (µA)
3.3 V
3.6 V
Electrical characteristics STM32F103x8, STM32F103xB
44/91 Doc ID 13587 Rev 10
Typical current consumption
The MCU is placed under the following conditions:
All I/O pins are in input mode with a static value at VDD or VSS (no load).
All peripherals are disabled except if it is explicitly mentioned.
The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1
wait state from 24 to 48 MHz and 2 wait states above).
Ambient temperature and VDD supply voltage conditions summarized in Ta b l e 9 .
Prefetch is ON (Reminder: this bit must be set before clock setting and bus prescaling)
When the peripherals are enabled fPCLK1 = fHCLK/4, fPCLK2 = fHCLK/2, fADCCLK =
fPCLK2/4
Table 17. Typical current consumption in Run mode, code with data processing
running from Flash
Symbol Parameter Conditions fHCLK
Typ(1)
1. Typical values are measures at TA = 25 °C, VDD = 3.3 V.
Unit
All peripherals
enabled(2)
2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this
consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).
All peripherals
disabled
IDD
Supply
current in
Run mode
External clock(3)
3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
72 MHz 36 27
mA
48 MHz 24.2 18.6
36 MHz 19 14.8
24 MHz 12.9 10.1
16 MHz 9.3 7.4
8 MHz 5.5 4.6
4 MHz 3.3 2.8
2 MHz 2.2 1.9
1 MHz 1.6 1.45
500 kHz 1.3 1.25
125 kHz 1.08 1.06
Running on high
speed internal RC
(HSI), AHB
prescaler used to
reduce the
frequency
64 MHz 31.4 23.9
mA
48 MHz 23.5 17.9
36 MHz 18.3 14.1
24 MHz 12.2 9.5
16 MHz 8.5 6.8
8 MHz 4.9 4
4 MHz 2.7 2.2
2 MHz 1.6 1.4
1 MHz 1.02 0.9
500 kHz 0.73 0.67
125 kHz 0.5 0.48
STM32F103x8, STM32F103xB Electrical characteristics
Doc ID 13587 Rev 10 45/91
Table 18. Typical current consumption in Sleep mode, code running from Flash or
RAM
Symbol Parameter Conditions fHCLK
Typ(1)
1. Typical values are measures at TA = 25 °C, VDD = 3.3 V.
Unit
All peripherals
enabled(2)
2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this
consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).
All peripherals
disabled
IDD
Supply
current in
Sleep mode
External clock(3)
3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
72 MHz 14.4 5.5
mA
48 MHz 9.9 3.9
36 MHz 7.6 3.1
24 MHz 5.3 2.3
16 MHz 3.8 1.8
8 MHz 2.1 1.2
4 MHz 1.6 1.1
2 MHz 1.3 1
1 MHz 1.11 0.98
500 kHz 1.04 0.96
125 kHz 0.98 0.95
Running on high
speed internal RC
(HSI), AHB prescaler
used to reduce the
frequency
64 MHz 12.3 4.4
48 MHz 9.3 3.3
36 MHz 7 2.5
24 MHz 4.8 1.8
16 MHz 3.2 1.2
8 MHz 1.6 0.6
4 MHz 1 0.5
2 MHz 0.72 0.47
1 MHz 0.56 0.44
500 kHz 0.49 0.42
125 kHz 0.43 0.41
Electrical characteristics STM32F103x8, STM32F103xB
46/91 Doc ID 13587 Rev 10
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in Ta b l e 1 9 . The MCU is placed
under the following conditions:
all I/O pins are in input mode with a static value at VDD or VSS (no load)
all peripherals are disabled unless otherwise mentioned
the given value is calculated by measuring the current consumption
with all peripherals clocked off
with only one peripheral clocked on
ambient operating temperature and VDD supply voltage conditions summarized in
Ta b le 6
Table 19. Peripheral current consumption(1)
1. fHCLK = 72 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, default prescaler value for each peripheral.
Peripheral Typical consumption at 25 °C Unit
APB1
TIM2 1.2
mA
TIM3 1.2
TIM4 0.9
SPI2 0.2
USART2 0.35
USART3 0.35
I2C1 0.39
I2C2 0.39
USB 0.65
CAN 0.72
APB2
GPIO A 0.47
mA
GPIO B 0.47
GPIO C 0.47
GPIO D 0.47
GPIO E 0.47
ADC1(2)
2. Specific conditions for ADC: fHCLK = 56 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, fADCCLK = fAPB2/4, ADON bit
in the ADC_CR2 register is set to 1.
1.81
ADC2 1.78
TIM1 1.6
SPI1 0.43
USART1 0.85
STM32F103x8, STM32F103xB Electrical characteristics
Doc ID 13587 Rev 10 47/91
5.3.6 External clock source characteristics
High-speed external user clock generated from an external source
The characteristics given in Tabl e 2 0 result from tests performed using an high-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Ta b l e 9 .
Low-speed external user clock generated from an external source
The characteristics given in Tabl e 2 1 result from tests performed using an low-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Ta b l e 9 .
Table 20. High-speed external user clock characteristics
Symbol Parameter Conditions Min Typ Max Unit
fHSE_ext
User external clock source
frequency(1) 0825MHz
VHSEH OSC_IN input pin high level voltage 0.7VDD VDD V
VHSEL OSC_IN input pin low level voltage VSS 0.3VDD
tw(HSE)
tw(HSE)
OSC_IN high or low time(1)
1. Guaranteed by design, not tested in production.
16
ns
tr(HSE)
tf(HSE)
OSC_IN rise or fall time(1) 20
Cin(HSE) OSC_IN input capacitance(1) 5pF
DuCy(HSE) Duty cycle 45 55 %
ILOSC_IN Input leakage current VSS VIN VD
D
±1 µA
Table 21. Low-speed external user clock characteristics
Symbol Parameter Conditions Min Typ Max Unit
fLSE_ext
User External clock source
frequency(1) 32.768 1000 kHz
VLSEH
OSC32_IN input pin high level
voltage 0.7VDD VDD
V
VLSEL
OSC32_IN input pin low level
voltage VSS 0.3VDD
tw(LSE)
tw(LSE)
OSC32_IN high or low time(1) 450
ns
tr(LSE)
tf(LSE)
OSC32_IN rise or fall time(1) 50
Cin(LSE) OSC32_IN input capacitance(1) 5pF
DuCy(LSE) Duty cycle 30 70 %
IL
OSC32_IN Input leakage
current
VSS VIN VD
D
±1 µA
Electrical characteristics STM32F103x8, STM32F103xB
48/91 Doc ID 13587 Rev 10
Figure 19. High-speed external clock source AC timing diagram
Figure 20. Low-speed external clock source AC timing diagram
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on characterization
results obtained with typical external components specified in Ta b l e 2 2 . In the application,
the resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
1. Guaranteed by design, not tested in production.
ai14143
OSC _I N
EXTERNAL
STM32F103xx
CLOCK SOURC E
VHSEH
tf(HSE) tW(HSE)
IL
90%
10%
THSE
t
tr(HSE) tW(HSE)
fHSE_ext
VHSEL
ai14144b
OSC32_IN
EXTERNAL
STM32F103xx
CLOCK SOURC E
VLSEH
tf(LSE) tW(LSE)
IL
90%
10%
TLSE
t
tr(LSE) tW(LSE)
fLSE_ext
VLSEL
STM32F103x8, STM32F103xB Electrical characteristics
Doc ID 13587 Rev 10 49/91
Figure 21. Typical application with an 8 MHz crystal
1. REXT value depends on the crystal characteristics. Typical value is in the range of 5 to 6RS.
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on characterization
results obtained with typical external components specified in Ta b l e 2 3 . In the application,
the resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
Table 22. HSE 4-16 MHz oscillator characteristics(1) (2)
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Based on characterization, not tested in production.
Symbol Parameter Conditions Min Typ Max Unit
fOSC_IN Oscillator frequency 4 8 16 MHz
RFFeedback resistor 200 k
CL1
CL2(3)
3. For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 pF to 25 pF range (typ.),
designed for high-frequency applications, and selected to match the requirements of the crystal or
resonator. CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load
capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be
included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.
Recommended load capacitance
versus equivalent serial
resistance of the crystal (RS)(4)
4. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a
humid environment, due to the induced leakage and the bias condition change. However, it is
recommended to take this point into account if the MCU is used in tough humidity conditions.
RS = 30 30 pF
i2HSE driving current VDD = 3.3 V, VIN =V
SS
with 30 pF load 1mA
gmOscillator transconductance Startup 25 mA/V
tSU(HSE(5)
5. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
startup time VDD is stabilized 2 ms
ai14145
OSC_OUT
OSC_IN fHSE
CL1
RF
STM32F103xx
8 MHz
resonator
REXT(1)
CL2
Resonator with
integrated capacitors
Bias
controlled
gain
Electrical characteristics STM32F103x8, STM32F103xB
50/91 Doc ID 13587 Rev 10
Note: For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 pF to
15 pF range selected to match the requirements of the crystal or resonator. CL1 and CL2, are
usually the same size. The crystal manufacturer typically specifies a load capacitance which
is the series combination of CL1 and CL2.
Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where
Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is
between 2 pF and 7 pF.
Caution: To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended
to use a resonator with a load capacitance CL
7 pF. Never use a resonator with a load
capacitance of 12.5 pF.
Example: if you choose a resonator with a load capacitance of CL = 6 pF, and Cstray = 2 pF,
then CL1 = CL2 = 8 pF.
Figure 22. Typical application with a 32.768 kHz crystal
5.3.7 Internal clock source characteristics
The parameters given in Ta b le 2 4 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Ta bl e 9 .
Table 23. LSE oscillator characteristics (fLSE = 32.768 kHz) (1)
1. Based on characterization, not tested in production.
Symbol Parameter Conditions Min Typ Max Unit
RFFeedback resistor 5 M
CL1
CL2(2)
2. Refer to the note and caution paragraphs above the table.
Recommended load capacitance
versus equivalent serial
resistance of the crystal (RS)(3)
3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with
small RS value for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details
RS = 30 k15 pF
I2LSE driving current VDD = 3.3 V, VIN = VSS 1.4 µA
gmOscillator Transconductance 5 µA/V
tSU(LSE)(4)
4. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768
kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary
significantly with the crystal manufacturer
startup time VDD is stabilized 3 s
ai14146
OSC32_OUT
OSC32_IN fLSE
CL1
RF
STM32F103xx
32.768 kHz
resonator
CL2
Resonator with
integrated capacitors
Bias
controlled
gain
STM32F103x8, STM32F103xB Electrical characteristics
Doc ID 13587 Rev 10 51/91
High-speed internal (HSI) RC oscillator
Low-speed internal (LSI) RC oscillator
Wakeup time from low-power mode
The wakeup times given in Ta ble 2 6 is measured on a wakeup phase with a 8-MHz HSI RC
oscillator. The clock source used to wake up the device depends from the current operating
mode:
Stop or Standby mode: the clock source is the RC oscillator
Sleep mode: the clock source is the clock that was set before entering Sleep mode.
All timings are derived from tests performed under ambient temperature and VDD supply
voltage conditions summarized in Ta b l e 9 .
Table 24. HSI oscillator characteristics(1) (2)
1. Guaranteed by design, not tested in production.
2. VDD = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
fHSI Frequency 8 MHz
ACCHSI Accuracy of HSI oscillator
TA = –40 to 105 °C –2 12.5%
TA = –10 to 85 °C –1.5 12.2%
TA = 0 to 70 °C –1.3 12%
TA = 25 °C –1.1 11.8%
tsu(HSI) HSI oscillator startup time 1 2 µs
IDD(HSI)
HSI oscillator power
consumption 80 100 µA
Table 25. LSI oscillator characteristics (1)
1. VDD = 3 V, TA = –40 to 105 °C unless otherwise specified.
Symbol Parameter Min Typ Max Unit
fLSI(2)
2. Based on characterization, not tested in production.
Frequency 30 40 60 kHz
tsu(LSI)(3)
3. Guaranteed by design, not tested in production.
LSI oscillator startup time 85 µs
IDD(LSI)(3) LSI oscillator power consumption 0.65 1.2 µA
Electrical characteristics STM32F103x8, STM32F103xB
52/91 Doc ID 13587 Rev 10
5.3.8 PLL characteristics
The parameters given in Ta b le 2 7 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Ta bl e 9 .
5.3.9 Memory characteristics
Flash memory
The characteristics are given at TA = 40 to 105 °C unless otherwise specified.
Table 26. Low-power mode wakeup timings
Symbol Parameter Conditions Typ Unit
tWUSLEEP(1)
1. The wakeup times are measured from the wakeup event to the point in which the user application code
reads the first instruction.
Wakeup from Sleep mode Wakeup on HSI RC clock 1.8 µs
tWUSTOP(1)
Wakeup from Stop mode
(regulator in run mode) HSI RC wakeup time = 2 µs 3.6
µs
Wakeup from Stop mode
(regulator in low power mode)
HSI RC wakeup time = 2 µs, Regulator
wakeup from LP mode time = 5 µs 5.4
tWUSTDBY(1) Wakeup from Standby mode HSI RC wakeup time = 2 µs, Regulator
wakeup from power down time = 38 µs 50 µs
Table 27. PLL characteristics
Symbol Parameter Test conditions
Value
Unit
Min(1)
1. Based on characterization, not tested in production.
Typ Max(1)
fPLL_IN
PLL input clock(2)
2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT.
18.0 25 MHz
PLL input clock duty cycle 40 60 %
fPLL_OUT PLL multiplier output clock 16 72 MHz
tLOCK PLL lock time 200 µs
Table 28. Flash memory characteristics
Symbol Parameter Conditions Min(1) Typ Max(1) Unit
tprog 16-bit programming time TA–40 to +105 °C 40 52.5 70 µs
tERASE Page (1 KB) erase time TA –40 to +105 °C 20 40 ms
tME Mass erase time TA –40 to +105 °C 20 40 ms
STM32F103x8, STM32F103xB Electrical characteristics
Doc ID 13587 Rev 10 53/91
Table 29. Flash memory endurance and data retention
5.3.10 EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the
device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 1000-4-2 standard.
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Ta b l e 3 0 . They are based on the EMS levels and classes
defined in application note AN1709.
IDD Supply current
Read mode
fHCLK = 72 MHz with 2 wait
states, VDD = 3.3 V
20 mA
Write / Erase modes
fHCLK = 72 MHz, VDD = 3.3 V 5mA
Power-down mode / Halt,
VDD = 3.0 to 3.6 V 50 µA
Vprog Programming voltage 2 3.6 V
1. Guaranteed by design, not tested in production.
Symbol Parameter Conditions
Value
Unit
Min(1)
1. Based on characterization, not tested in production.
Typ Max
NEND Endurance TA = –40 to +85 °C (6 suffix versions)
TA = –40 to +105 °C (7 suffix versions) 10 kcycles
tRET Data retention
1 kcycle(2) at TA = 85 °C
2. Cycling performed over the whole temperature range.
30
Years1 kcycle(2) at TA = 105 °C 10
10 kcycles(2) at TA = 55 °C 20
Table 28. Flash memory characteristics (continued)
Symbol Parameter Conditions Min(1) Typ Max(1) Unit
Electrical characteristics STM32F103x8, STM32F103xB
54/91 Doc ID 13587 Rev 10
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
Corrupted program counter
Unexpected reset
Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with SAE J
1752/3 standard which specifies the test board and the pin loading.
Table 30. EMS characteristics
Symbol Parameter Conditions Level/
Class
VFESD
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
VDD 3.3 V, TA +25 °C,
fHCLK 72 MHz
conforms to IEC 1000-4-2
2B
VEFTB
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD3.3 V, TA +25 °C,
fHCLK 72 MHz
conforms to IEC 1000-4-4
4A
Table 31. EMI characteristics
Symbol Parameter Conditions Monitored
frequency band
Max vs. [fHSE/fHCLK]
Unit
8/48 MHz 8/72 MHz
SEMI Peak level
VDD 3.3 V, TA 25 °C,
LQFP100 package
compliant with SAE J
1752/3
0.1 to 30 MHz 12 12
dBµV30 to 130 MHz 22 19
130 MHz to 1GHz 23 29
SAE EMI Level 4 4 -
STM32F103x8, STM32F103xB Electrical characteristics
Doc ID 13587 Rev 10 55/91
5.3.11 Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 32. ESD absolute maximum ratings
Symbol Ratings Conditions Class Maximum value(1)
1. Based on characterization results, not tested in production.
Unit
VESD(HBM)
Electrostatic discharge
voltage (human body model)
TA +25 °C
conforming to
JESD22-A114
2 2000
V
VESD(CDM)
Electrostatic discharge
voltage (charge device
model)
TA +25 °C
conforming to
JESD22-C101
II 500
Table 33. Electrical sensitivities
Symbol Parameter Conditions Class
LU Static latch-up class TA +105 °C conforming to JESD78A II level A
Electrical characteristics STM32F103x8, STM32F103xB
56/91 Doc ID 13587 Rev 10
5.3.12 I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Ta b l e 3 4 are derived from tests
performed under the conditions summarized in Ta b l e 9 . All I/Os are CMOS and TTL
compliant.
All I/Os are CMOS and TTL compliant (no software configuration required), their
characteristics consider the most strict CMOS-technology or TTL parameters:
For VIH:
–if V
DD is in the [2.00 V - 3.08 V] range: CMOS characteristics but TTL included
–if V
DD is in the [3.08 V - 3.60 V] range: TTL characteristics but CMOS included
For VIL:
–if V
DD is in the [2.00 V - 2.28 V] range: TTL characteristics but CMOS included
–if V
DD is in the [2.28 V - 3.60 V] range: CMOS characteristics but TTL included
Table 34. I/O static characteristics
Symbol Parameter Conditions Min Typ Max Unit
VIL Input low level voltage
TTL ports
–0.5 0.8
V
VIH
Standard IO input high level
voltage 2V
DD+0.5
IO FT(1) input high level voltage
1. FT = Five-volt tolerant.
25.5V
VIL Input low level voltage CMOS ports –0.5 0.35 VDD V
VIH Input high level voltage 0.65 VDD VDD+0.5
Vhys
Standard IO Schmitt trigger
voltage hysteresis(2)
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in
production.
200 mV
IO FT Schmitt trigger voltage
hysteresis(2) 5% VDD(3)
3. With a minimum of 100 mV.
mV
Ilkg Input leakage current (4)
4. Leakage could be higher than max. if negative current is injected on adjacent pins.
VSS VIN VDD
Standard I/Os 1
µA
VIN= 5 V
I/O FT 3
RPU
Weak pull-up equivalent
resistor(5)
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable
PMOS/NMOS. This MOS/NMOS contribution to the series resistance is minimum (~10% order).
VIN VSS 30 40 50 k
RPD
Weak pull-down equivalent
resistor(5) VIN VDD 30 40 50 k
CIO I/O pin capacitance 5 pF
STM32F103x8, STM32F103xB Electrical characteristics
Doc ID 13587 Rev 10 57/91
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink
+20 mA (with a relaxed VOL).
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2:
The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
IVDD (see Ta b le 7 ).
The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
IVSS (see Ta b l e 7 ).
Output voltage levels
Unless otherwise specified, the parameters given in Ta b l e 3 5 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Ta bl e 9 . All I/Os are CMOS and TTL compliant.
Table 35. Output voltage characteristics
Symbol Parameter Conditions Min Max Unit
VOL(1)
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 7
and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
Output low level voltage for an I/O pin
when 8 pins are sunk at same time TTL port
IIO = +8 mA
2.7 V < VDD < 3.6 V
0.4
V
VOH(2)
2. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 7 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.
Output high level voltage for an I/O pin
when 8 pins are sourced at same time VDD–0.4
VOL (1) Output low level voltage for an I/O pin
when 8 pins are sunk at same time CMOS port
IIO =+ 8mA
2.7 V < VDD < 3.6 V
0.4
V
VOH (2) Output high level voltage for an I/O pin
when 8 pins are sourced at same time 2.4
VOL(1)(3)
3. Based on characterization data, not tested in production.
Output low level voltage for an I/O pin
when 8 pins are sunk at same time IIO = +20 mA
2.7 V < VDD < 3.6 V
1.3
V
VOH(2)(3) Output high level voltage for an I/O pin
when 8 pins are sourced at same time VDD–1.3
VOL(1)(3) Output low level voltage for an I/O pin
when 8 pins are sunk at same time IIO = +6 mA
2 V < VDD < 2.7 V
0.4
V
VOH(2)(3) Output high level voltage for an I/O pin
when 8 pins are sourced at same time VDD–0.4
MODEX[1:0]
Electrical characteristics STM32F103x8, STM32F103xB
58/91 Doc ID 13587 Rev 10
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 23 and
Ta bl e 3 6 , respectively.
Unless otherwise specified, the parameters given in Ta b l e 3 6 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Ta b l e 9 .
Table 36. I/O AC characteristics(1)
1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a
description of GPIO Port configuration register.
MODEx[1:0]
bit value(1) Symbol Parameter Conditions Min Max Unit
10
fmax(IO)out Maximum frequency(2)
2. The maximum frequency is defined in Figure 23.
CL = 50 pF, VDD = 2 V to 3.6 V 2 MHz
tf(IO)out
Output high to low
level fall time CL = 50 pF, VDD = 2 V to 3.6 V
125(3)
3. Guaranteed by design, not tested in production.
ns
tr(IO)out
Output low to high
level rise time 125(3)
01
fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V 10 MHz
tf(IO)out
Output high to low
level fall time CL = 50 pF, VDD = 2 V to 3.6 V
25(3)
ns
tr(IO)out
Output low to high
level rise time 25(3)
11
Fmax(IO)out Maximum frequency(2)
CL = 30 pF, VDD = 2.7 V to 3.6 V 50 MHz
CL = 50 pF, VDD = 2.7 V to 3.6 V 30 MHz
CL = 50 pF, VDD = 2 V to 2.7 V 20 MHz
tf(IO)out
Output high to low
level fall time
CL = 30 pF, VDD = 2.7 V to 3.6 V 5(3)
ns
CL = 50 pF, VDD = 2.7 V to 3.6 V 8(3)
CL = 50 pF, VDD = 2 V to 2.7 V 12(3)
tr(IO)out
Output low to high
level rise time
CL = 30 pF, VDD = 2.7 V to 3.6 V 5(3)
CL = 50 pF, VDD = 2.7 V to 3.6 V 8(3)
CL = 50 pF, VDD = 2 V to 2.7 V 12(3)
-t
EXTIpw
Pulse width of
external signals
detected by the EXTI
controller
10 ns
STM32F103x8, STM32F103xB Electrical characteristics
Doc ID 13587 Rev 10 59/91
Figure 23. I/O AC characteristics definition
5.3.13 NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Ta b l e 3 4 ).
Unless otherwise specified, the parameters given in Ta b l e 3 7 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Ta b l e 9 .
ai14131
10%
90%
50%
tr(IO)out
OUTPUT
EXT ERNAL
ON 50pF
Maximum frequency is achieved if (tr + tf) 2/3)T and if the duty cycle is (45-55%)
10 %
50%
90%
when loaded by 50pF
T
tr(IO)out
Table 37. NRST pin characteristics
Symbol Parameter Conditions Min Typ Max Unit
VIL(NRST)(1)
1. Guaranteed by design, not tested in production.
NRST Input low level voltage –0.5 0.8 V
VIH(NRST)(1) NRST Input high level voltage 2 VDD+0.5
Vhys(NRST)
NRST Schmitt trigger voltage
hysteresis 200 mV
RPU Weak pull-up equivalent resistor(2)
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
to the series resistance must be minimum (~10% order).
VIN VSS 30 40 50 k
VF(NRST)(1) NRST Input filtered pulse 100 ns
VNF(NRST)(1) NRST Input not filtered pulse 300 ns
Electrical characteristics STM32F103x8, STM32F103xB
60/91 Doc ID 13587 Rev 10
Figure 24. Recommended NRST pin protection
2. The reset network protects the device against parasitic resets.
3. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 37. Otherwise the reset will not be taken into account by the device.
5.3.14 TIM timer characteristics
The parameters given in Ta b le 3 8 are guaranteed by design.
Refer to Section 5.3.12: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
ai14132b
STM32F10xxx
RPU
NRST
(2)
VDD
FILTER
Internal Reset
0.1 µF
External
reset circuit
(1)
Table 38. TIMx(1) characteristics
1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3 and TIM4 timers.
Symbol Parameter Conditions Min Max Unit
tres(TIM) Timer resolution time
1tTIMxCLK
fTIMxCLK = 72 MHz 13.9 ns
fEXT Timer external clock
frequency on CH1 to CH4
0
fTIMxCLK/2 MHz
fTIMxCLK = 72 MHz 036MHz
ResTIM Timer resolution 16 bit
tCOUNTER
16-bit counter clock period
when internal clock is
selected
1 65536 tTIMxCLK
fTIMxCLK = 72 MHz 0.0139 910 µs
tMAX_COUNT Maximum possible count
65536 × 65536 tTIMxCLK
fTIMxCLK = 72 MHz 59.6 s
STM32F103x8, STM32F103xB Electrical characteristics
Doc ID 13587 Rev 10 61/91
5.3.15 Communications interfaces
I2C interface characteristics
Unless otherwise specified, the parameters given in Ta b l e 3 9 are derived from tests
performed under the ambient temperature, fPCLK1 frequency and VDD supply voltage
conditions summarized in Ta b l e 9 .
The STM32F103xx performance line I2C interface meets the requirements of the standard
I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are
mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected
between the I/O pin and VDD is disabled, but is still present.
The I2C characteristics are described in Ta b l e 3 9 . Refer also to Section 5.3.12: I/O port
characteristics for more details on the input/output alternate function characteristics (SDA
and SCL).
Table 39. I2C characteristics
Symbol Parameter
Standard mode I2C(1)
1. Guaranteed by design, not tested in production.
Fast mode I2C(1)(2)
2. fPCLK1 must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. It must be
higher than 4 MHz to achieve the maximum fast mode I2C frequency.
Unit
Min Max Min Max
tw(SCLL) SCL clock low time 4.7 1.3 µs
tw(SCLH) SCL clock high time 4.0 0.6
tsu(SDA) SDA setup time 250 100
ns
th(SDA) SDA data hold time 0(3)
3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low
period of SCL signal.
0(4)
4. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
900(3)
tr(SDA)
tr(SCL)
SDA and SCL rise time 1000 20 + 0.1Cb300
tf(SDA)
tf(SCL)
SDA and SCL fall time 300 300
th(STA) Start condition hold time 4.0 0.6
µs
tsu(STA)
Repeated Start condition
setup time 4.7 0.6
tsu(STO) Stop condition setup time 4.0 0.6 s
tw(STO:STA)
Stop to Start condition time
(bus free) 4.7 1.3 s
Cb
Capacitive load for each bus
line 400 400 pF
PPPPP
Electrical characteristics STM32F103x8, STM32F103xB
62/91 Doc ID 13587 Rev 10
Figure 25. I2C bus AC waveforms and measurement circuit
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
Table 40. SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V)(1)(2)
1. RP = External pull-up resistance, fSCL = I2C speed,
2. For speeds around 200 kHz, the tolerance on the achieved speed is of 5%. For other speed ranges, the
tolerance on the achieved speed 2%. These variations depend on the accuracy of the external
components used to design the application.
fSCL (kHz)
I2C_CCR value
RP = 4.7 k
400 0x801E
300 0x8028
200 0x803C
100 0x00B4
50 0x0168
20 0x0384
ai14149b
START
SD A
100Ω
4.7kΩ
I
2
C bus
4.7kΩ
100Ω
VDD
VDD
STM32F103xx
SDA
SCL
tf(SDA) tr(SDA)
SCL
th(STA)
tw(SCKH)
tw(SCKL)
tsu(SDA)
tr(SCK) tf(SCK)
th(SDA)
S TART REPEATED
START
tsu(STA)
tsu(STO)
S TOP tsu(STA:STO)
STM32F103x8, STM32F103xB Electrical characteristics
Doc ID 13587 Rev 10 63/91
SPI interface characteristics
Unless otherwise specified, the parameters given in Ta b l e 4 1 are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Ta b l e 9 .
Refer to Section 5.3.12: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO).
Table 41. SPI characteristics(1)
1. Remapped SPI1 characteristics to be determined.
Symbol Parameter Conditions Min Max Unit
fSCK
1/tc(SCK)
SPI clock frequency Master mode 0 18 MHz
Slave mode 0 18
tr(SCK)
tf(SCK)
SPI clock rise and fall
time Capacitive load: C = 30 pF 8
ns
tsu(NSS)(2)
2. Based on characterization, not tested in production.
NSS setup time Slave mode 4 tPCLK
th(NSS)(2) NSS hold time Slave mode 73
tw(SCKH)(2)
tw(SCKL)(2) SCK high and low time Master mode, fPCLK = 36 MHz,
presc = 4 50 60
tsu(MI) (2) Data input setup time
Master mode
SPI1 1
SPI2 5
tsu(SI)(2) Data input setup time
Slave mode 1
th(MI) (2) Data input hold time
Master mode
SPI1 1
SPI2 5
th(SI)(2) Data input hold time
Slave mode 3
ta(SO)(2)(3)
3. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
Data output access
time
Slave mode, fPCLK = 36 MHz,
presc = 4 055
Slave mode, fPCLK = 24 MHz 0 4 tPCLK
tdis(SO)(2)(4)
4. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
Data output disable
time Slave mode 10
tv(SO) (2)(1) Data output valid time Slave mode (after enable edge) 25
tv(MO)(2)(1) Data output valid time Master mode (after enable edge) 3
th(SO)(2)
Data output hold time Slave mode (after enable edge) 25
th(MO)(2) Master mode (after enable edge) 4
Electrical characteristics STM32F103x8, STM32F103xB
64/91 Doc ID 13587 Rev 10
Figure 26. SPI timing diagram - slave mode and CPHA = 0
Figure 27. SPI timing diagram - slave mode and CPHA = 1(1)
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
ai14134c
SCK Input
CPHA= 0
MOSI
INPUT
MISO
OUT P UT
CPHA= 0
MS B O UT
MSB IN
BI T6 O U T
LSB IN
LSB OUT
CPOL=0
CPOL=1
BIT1 IN
NSS input
tSU(NSS)
tc(SCK)
th(NSS)
ta(SO)
tw(SCKH)
tw(SCKL)
tv(SO) th(SO) tr(SCK)
tf(SCK)
tdis(SO)
tsu(SI)
th(SI)
ai14135
SCK Input
CPHA=1
MOSI
INPUT
MISO
OUT P UT
CPHA=1
MS B O UT
MSB IN
BI T6 O U T
LSB IN
LSB OUT
CPOL=0
CPOL=1
BIT1 IN
tSU(NSS) tc(SCK) th(NSS)
ta(SO)
tw(SCKH)
tw(SCKL)
tv(SO) th(SO) tr(SCK)
tf(SCK)
tdis(SO)
tsu(SI) th(SI)
NSS input
STM32F103x8, STM32F103xB Electrical characteristics
Doc ID 13587 Rev 10 65/91
Figure 28. SPI timing diagram - master mode(1)
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
USB characteristics
The USB interface is USB-IF certified (Full Speed).
Table 42. USB startup time
Symbol Parameter Max Unit
tSTARTUP(1)
1. Guaranteed by design, not tested in production.
USB transceiver startup time 1 µs
ai14136
SCK Input
CPHA= 0
MOSI
OUTUT
MISO
INP UT
CPHA= 0
MS BIN
M SB OUT
BI T6 IN
LSB OUT
LSB IN
CPOL=0
CPOL=1
B IT1 OUT
NSS input
tc(SCK)
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
th(MI)
High
SCK Input
CPHA=1
CPHA=1
CPOL=0
CPOL=1
tsu(MI)
tv(MO) th(MO)
Electrical characteristics STM32F103x8, STM32F103xB
66/91 Doc ID 13587 Rev 10
Figure 29. USB timings: definition of data signal rise and fall time
5.3.16 CAN (controller area network) interface
Refer to Section 5.3.12: I/O port characteristics for more details on the input/output alternate
function characteristics (CAN_TX and CAN_RX).
Table 43. USB DC electrical characteristics
Symbol Parameter Conditions Min.(1)
1. All the voltages are measured from the local ground potential.
Max.(1) Unit
Input levels
VDD USB operating voltage(2)
2. To be compliant with the USB 2.0 full-speed electrical specification, the USBDP (D+) pin should be pulled
up with a 1.5 k resistor to a 3.0-to-3.6 V voltage range.
3.0(3)
3. The STM32F103xx USB functionality is ensured down to 2.7 V but not the full USB electrical
characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range.
3.6 V
VDI(4)
4. Guaranteed by design, not tested in production.
Differential input sensitivity I(USBDP, USBDM) 0.2
VVCM(4) Differential common mode range Includes VDI range 0.8 2.5
VSE(4) Single ended receiver threshold 1.3 2.0
Output levels
VOL Static output level low RL of 1.5 k to 3.6 V(5)
5. RL is the load connected on the USB drivers
0.3 V
VOH Static output level high RL of 15 k to VSS(5) 2.8 3.6
Table 44. USB: Full-speed electrical characteristics(1)
1. Guaranteed by design, not tested in production.
Symbol Parameter Conditions Min Max Unit
Driver characteristics
trRise time(2)
2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
CL = 50 pF 420ns
tfFall time(2) CL = 50 pF 4 20 ns
trfm Rise/ fall time matching tr/tf90 110 %
VCRS Output signal crossover voltage 1.3 2.0 V
ai14137
tf
Differen tial
data lines
VSS
V
CR S
tr
Crossover
points
STM32F103x8, STM32F103xB Electrical characteristics
Doc ID 13587 Rev 10 67/91
5.3.17 12-bit ADC characteristics
Unless otherwise specified, the parameters given in Ta b l e 4 5 are derived from tests
performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage
conditions summarized in Ta b l e 9 .
Note: It is recommended to perform a calibration after each power-up.
Table 45. ADC characteristics
Symbol Parameter Conditions Min Typ Max Unit
VDDA Power supply 2.4 3.6 V
VREF+ Positive reference voltage 2.4 VDDA V
IVREF Current on the VREF input pin 160(1) 220(1) µA
fADC ADC clock frequency 0.6 14 MHz
fS(2) Sampling rate 0.05 1 MHz
fTRIG(2) External trigger frequency fADC = 14 MHz 823 kHz
17 1/fADC
VAIN(3) Conversion voltage range 0 (VSSA or VREF-
tied to ground) VREF+ V
RAIN(2) External input impedance See Equation 1 and Ta b l e 4 6 k
RADC(2) Sampling switch resistance 1 k
CADC(2) Internal sample and hold
capacitor 12 pF
tCAL(2) Calibration time fADC = 14 MHz 5.9 µs
83 1/fADC
tlat(2) Injection trigger conversion
latency
fADC = 14 MHz 0.214 µs
3(4) 1/fADC
tlatr(2) Regular trigger conversion
latency
fADC = 14 MHz 0.143 µs
2(4) 1/fADC
tS(2) Sampling time fADC = 14 MHz 0.107 17.1 µs
1.5 239.5 1/fADC
tSTAB(2) Power-up time 0 0 1 µs
tCONV(2) Total conversion time
(including sampling time)
fADC = 14 MHz 1 18 µs
14 to 252 (tS for sampling +12.5 for
successive approximation) 1/fADC
1. Based on characterization, not tested in production.
2. Guaranteed by design, not tested in production.
3. In devices delivered in VFQFPN and LQFP packages, VREF+ is internally connected to VDDA and VREF- is internally
connected to VSSA. Devices that come in the TFBGA64 package have a VREF+ pin but no VREF- pin (VREF- is internally
connected to VSSA), see Table 5 and Figure 6.
4. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 45.
Al N 1ADC
Electrical characteristics STM32F103x8, STM32F103xB
68/91 Doc ID 13587 Rev 10
Equation 1: RAIN max formula:
The formula above (Equation 1) is used to determine the maximum external impedance allowed for an
error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
Table 46. RAIN max for fADC = 14 MHz(1)
1. Based on characterization, not tested in production.
Ts (cycles) tS (µs) RAIN max (k)
1.5 0.11 1.2
7.5 0.54 10
13.5 0.96 19
28.5 2.04 41
41.5 2.96 60
55.5 3.96 80
71.5 5.11 104
239.5 17.1 350
Table 47. ADC accuracy - limited test conditions(1) (2)
1. ADC DC accuracy values are measured after internal calibration.
2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-
robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to
standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 5.3.12 does not
affect the ADC accuracy.
Symbol Parameter Test conditions Typ Max(3)
3. Based on characterization, not tested in production.
Unit
ET Total unadjusted error fPCLK2 = 56 MHz,
fADC = 14 MHz, RAIN < 10 k,
VDDA = 3 V to 3.6 V
TA = 25 °C
Measurements made after
ADC calibration
±1.3 ±2
LSB
EO Offset error ±1 ±1.5
EG Gain error ±0.5 ±1.5
ED Differential linearity error ±0.7 ±1
EL Integral linearity error ±0.8 ±1.5
RAIN
TS
fADC CADC 2N2+
ln
--------------------------------------------------------------RADC
STM32F103x8, STM32F103xB Electrical characteristics
Doc ID 13587 Rev 10 69/91
Figure 30. ADC accuracy characteristics
Table 48. ADC accuracy(1) (2) (3)
1. ADC DC accuracy values are measured after internal calibration.
2. Better performance could be achieved in restricted VDD, frequency and temperature ranges.
3. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-
robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to
standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 5.3.12 does not
affect the ADC accuracy.
Symbol Parameter Test conditions Typ Max(4)
4. Based on characterization, not tested in production.
Unit
ET Total unadjusted error
fPCLK2 = 56 MHz,
fADC = 14 MHz, RAIN < 10 k,
VDDA = 2.4 V to 3.6 V
Measurements made after
ADC calibration
±2 ±5
LSB
EO Offset error ±1.5 ±2.5
EG Gain error ±1.5 ±3
ED Differential linearity error ±1 ±2
EL Integral linearity error ±1.5 ±3
EO
EG
1LSB
IDEAL
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
ET=Total Unadjusted Error: maximum deviation
between the actual and the ideal transfer curves.
EO=Offset Error: deviation between the first actual
transition and the first ideal one.
EG=Gain Error: deviation between the last ideal
transition and the last actual one.
ED=Differential Linearity Error: maximum deviation
between actual steps and the ideal one.
EL=Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.
4095
4094
4093
5
4
3
2
1
0
7
6
1234567 4093 4094 4095 4096
(1)
(2)
ET
ED
EL
(3)
VDDA
VSSA
ai14395b
VREF+
4096 (or depending on package)]
VDDA
4096
[1LSBIDEAL =
Electrical characteristics STM32F103x8, STM32F103xB
70/91 Doc ID 13587 Rev 10
Figure 31. Typical connection diagram using the ADC
1. Refer to Ta b l e 4 5 for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 32 or Figure 33,
depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 32. Power supply and reference decoupling (VREF+ not connected to VDDA)
1. VREF+ and VREF– inputs are available only on 100-pin packages.
ai14150c
STM32F103xx
VDD
AINx
IL±1 µA
0.6 V
VT
RAIN(1)
Cparasitic
VAIN
0.6 V
VT
RADC(1) 12-bit
converter
CADC(1)
Sample and hold ADC
converter
V
REF+
(see note 1)
STM32F103xx
V
DDA
V
SSA
/V
REF–
(see note 1)
1 µF // 10 nF
1 µF // 10 nF
ai14388b
REF+ DDA
STM32F103x8, STM32F103xB Electrical characteristics
Doc ID 13587 Rev 10 71/91
Figure 33. Power supply and reference decoupling (VREF+ connected to VDDA)
1. VREF+ and VREF– inputs are available only on 100-pin packages.
5.3.18 Temperature sensor characteristics
V
REF+
/V
DDA
STM32F103xx
1 µF // 10 nF
V
REF–
/V
SSA
ai14389
(See note 1)
(See note 1)
Table 49. TS characteristics
Symbol Parameter Min Typ Max Unit
TL(1)
1. Based on characterization, not tested in production.
VSENSE linearity with temperature 12°C
Avg_Slope(1) Average slope 4.0 4.3 4.6 mV/°C
V25(1) Voltage at 25 °C 1.34 1.43 1.52 V
tSTART(2)
2. Guaranteed by design, not tested in production.
Startup time 4 10 µs
TS_temp(3)(2)
3. Shortest sampling time can be determined in the application by multiple iterations.
ADC sampling time when reading the
temperature 17.1 µs
Package characteristics STM32F103x8, STM32F103xB
72/91 Doc ID 13587 Rev 10
6 Package characteristics
6.1 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
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STM32F103x8, STM32F103xB Package characteristics
Doc ID 13587 Rev 10 73/91
1. Drawing is not to scale.
2. The back-side pad is not internally connected to the VSS or VDD power pads.
3. There is an exposed die pad on the underside of the VFQFPN package. It should be soldered to the PCB. All leads should
also be soldered to the PCB.
Figure 34. VFQFPN36 6 x 6 mm, 0.5 mm pitch,
package outline(1) Figure 35. Recommended footprint
(dimensions in mm)(1)(2)(3)
Seating plane
ddd C
C
A3 A1
AA2
Pin # 1 ID
R = 0.20
ZR_ME
E2
b
19
10
18
27
28
36
19
D2
E
D
e
L
0.30
6.30
0.50
1.00
4.30
4.30
4.80
4.80
4.10
4.10
1
28
9
19
ai14870b
36
27
18
10
0.75
Table 50. VFQFPN36 6 x 6 mm, 0.5 mm pitch, package mechanical data
Symbol
millimeters inches(1)
Min Typ Max Min Typ Max
A 0.800 0.900 1.000 0.0315 0.0354 0.0394
A1 0.020 0.050 0.0008 0.0020
A2 0.650 1.000 0.0256 0.0394
A3 0.250 0.0098
b 0.180 0.230 0.300 0.0071 0.0091 0.0118
D 5.875 6.000 6.125 0.2313 0.2362 0.2411
D2 1.750 3.700 4.250 0.0689 0.1457 0.1673
E 5.875 6.000 6.125 0.2313 0.2362 0.2411
E2 1.750 3.700 4.250 0.0689 0.1457 0.1673
e 0.450 0.500 0.550 0.0177 0.0197 0.0217
L 0.350 0.550 0.750 0.0138 0.0217 0.0295
ddd 0.080 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package characteristics STM32F103x8, STM32F103xB
74/91 Doc ID 13587 Rev 10
Figure 36. LFBGA100 - low profile fine pitch ball grid array package outline
1. Drawing is not to scale.
Table 51. LFBGA100 - low profile fine pitch ball grid array package mechanical data
Dim.
mm inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Min Typ Max Min Typ Max
A 1.700 0.0669
A1 0.270 0.0106
A2 1.085 0.0427
A3 0.30 0.0118
A4 0.80 0.0315
b 0.45 0.50 0.55 0.0177 0.0197 0.0217
D 9.85 10.00 10.15 0.3878 0.3937 0.3996
D1 7.20 0.2835
E 9.85 10.00 10.15 0.3878 0.3937 0.3996
E1 7.20 0.2835
e 0.80 0.0315
F 1.40 0.0551
ddd 0.12 0.0047
eee 0.15 0.0059
fff 0.08 0.0031
N (number of balls) 100
ai14396
A2 A4 A3 A1 A
Seating plane
B
A1 corner index area
(see note 5)
(100 balls)
Bottom view
12345678910
F
E1 E
e
A
D
D1
eF
K
J
H
G
F
E
D
C
B
A
ddd C
C
eee
fff
CA B
CM
M
b
STM32F103x8, STM32F103xB Package characteristics
Doc ID 13587 Rev 10 75/91
Figure 37. Recommended PCB design rules (0.80/0.75 mm pitch BGA)
Dpad
Dsm
Dpad 0.37 mm
Dsm 0.52 mm typ. (depends on solder
mask registration tolerance
Solder paste 0.37 mm aperture diameter
Non solder mask defined pads are recommended
4 to 6 mils screen print
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Package characteristics STM32F103x8, STM32F103xB
76/91 Doc ID 13587 Rev 10
Figure 38. LQFP100, 100-pin low-profile quad flat
package outline(1) Figure 39. Recommended footprint(1)(2)
1. Drawing is not to scale.
2. Dimensions are in millimeters.
D
D1
D3
75 51
50
76
100 26
125
E3 E1 E
e
b
Pin 1
identification
SEATING PLANE
GAGE PLANE
C
A
A2
A1
Cccc
0.25 mm
0.10 inch
L
L1
k
C
1L_ME
75 51
5076 0.5
0.3
16.7 14.3
100 26
12.3
25
1.2
16.7
1
ai14906
Table 52. LQPF100, 100-pin low-profile quad flat package mechanical data
Symbol
millimeters inches(1)
Typ Min Max Typ Min Max
A 1.6 0.063
A1 0.05 0.15 0.002 0.0059
A2 1.4 1.35 1.45 0.0551 0.0531 0.0571
b 0.22 0.17 0.27 0.0087 0.0067 0.0106
c 0.09 0.2 0.0035 0.0079
D 16 15.8 16.2 0.6299 0.622 0.6378
D1 14 13.8 14.2 0.5512 0.5433 0.5591
D3 12 0.4724
E 16 15.8 16.2 0.6299 0.622 0.6378
E1 14 13.8 14.2 0.5512 0.5433 0.5591
E3 12 0.4724
e 0.5 0.0197
L 0.6 0.45 0.75 0.0236 0.0177 0.0295
L1 1 0.0394
k 3.5° 0.0° 7.0° 3.5° 0.0° 7.0°
ccc 0.08 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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STM32F103x8, STM32F103xB Package characteristics
Doc ID 13587 Rev 10 77/91
Figure 40. LQFP64, 64-pin low-profile quad flat package
outline(1) Figure 41. Recommended
footprint(1)(2)
1. Drawing is not to scale.
2. Dimensions are in millimeters.
A
A2
A1
c
L1
L
EE1
D
D1
e
b
ai14398b
48
3249
64 17
116
1.2
0.3
33
10.3
12.7
10.3
0.5
7.8
12.7
ai14909
Table 53. LQFP64, 64-pin low-profile quad flat package mechanical data
Dim.
mm inches(1)
Min Typ Max Min Typ Max
A 1.60 0.0630
A1 0.05 0.15 0.0020 0.0059
A2 1.35 1.40 1.45 0.0531 0.0551 0.0571
b 0.17 0.22 0.27 0.0067 0.0087 0.0106
c 0.09 0.20 0.0035 0.0079
D 12.00 0.4724
D1 10.00 0.3937
E 12.00 0.4724
E1 10.00 0.3937
e 0.50 0.0197
0° 3.5° 7° 0° 3.5° 7°
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 1.00 0.0394
NNumber of pins
64
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package characteristics STM32F103x8, STM32F103xB
78/91 Doc ID 13587 Rev 10
Figure 42. TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package outline
1. Drawing is not to scale.
Table 54. TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package
mechanical data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Typ Min Max Typ Min Max
A 1.200 0.0472
A1 0.150 0.0059
A2 0.785 0.0309
A3 0.200 0.0079
A4 0.600 0.0236
b 0.300 0.250 0.350 0.0118 0.0098 0.0138
D 5.000 4.850 5.150 0.1969 0.1909 0.2028
D1 3.500 0.1378
E 5.000 4.850 5.150 0.1969 0.1909 0.2028
E1 3.500 0.1378
e 0.500 0.0197
F 0.750 0.0295
ddd 0.080 0.0031
eee 0.150 0.0059
fff 0.050 0.0020
A3
A4
A2
A1
A
Seating
plane
B
A
D
D1
eF
F
E1 E
e
H
G
F
E
D
C
B
A
12345678
A1 ball pad corner(2) Øb (64 balls)
Bottom view
C
ME_R8
STM32F103x8, STM32F103xB Package characteristics
Doc ID 13587 Rev 10 79/91
Figure 43. Recommended PCB design rules for pads (0.5 mm pitch BGA)
1. Non solder mask defined (NSMD) pads are recommended
2. 4 to 6 mils solder paste screen printing process
Pitch 0.5 mm
D pad 0.27 mm
Dsm 0.35 mm typ (depends on
the soldermask registration
tolerance)
Solder paste 0.27 mm aperture diameter
Dpad
Dsm
ai15495
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Package characteristics STM32F103x8, STM32F103xB
80/91 Doc ID 13587 Rev 10
Figure 44. LQFP48, 48-pin low-profile quad flat package
outline(1) Figure 45. Recommended
footprint(1)(2)
1. Drawing is not to scale.
2. Dimensions are in millimeters.
D
D1
D3 A1
L1
L
k
c
b
ccc C
A1
A2A
C
Seating plane
0.25 mm
Gage plane
E3 E1 E
12
13
24
25
48
1
36
37
Pin 1
identification
5B_ME
9.70 5.80 7.30
12
24
0.20
7.30
1
37
36
1.20
5.80
9.70
0.30
25
1.20
0.50
ai14911b
1348
Table 55. LQFP48, 48-pin low-profile quad flat package mechanical data
Symbol
millimeters inches(1)
Typ Min Max Typ Min Max
A 1.600 0.0630
A1 0.050 0.150 0.0020 0.0059
A2 1.400 1.350 1.450 0.0551 0.0531 0.0571
b 0.220 0.170 0.270 0.0087 0.0067 0.0106
c 0.090 0.200 0.0035 0.0079
D 9.000 8.800 9.200 0.3543 0.3465 0.3622
D1 7.000 6.800 7.200 0.2756 0.2677 0.2835
D3 5.500 0.2165
E 9.000 8.800 9.200 0.3543 0.3465 0.3622
E1 7.000 6.800 7.200 0.2756 0.2677 0.2835
E3 5.500 0.2165
e 0.500 0.0197
L 0.600 0.450 0.750 0.0236 0.0177 0.0295
L1 1.000 0.0394
k 3.5°0° 7°3.5°0° 7°
ccc 0.080 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
STM32F103x8, STM32F103xB Package characteristics
Doc ID 13587 Rev 10 81/91
6.2 Thermal characteristics
The maximum chip junction temperature (TJmax) must never exceed the values given in
Table 9: General operating conditions on page 35.
The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max × JA)
Where:
TA max is the maximum ambient temperature in C,
JA is the package junction-to-ambient thermal resistance, in C/W,
PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = (VOL × IOL) + ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
6.2.1 Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
Table 56. Package thermal characteristics
Symbol Parameter Value Unit
JA
Thermal resistance junction-ambient
LFBGA100 - 10 × 10 mm / 0.8 mm pitch 44
°C/W
Thermal resistance junction-ambient
LQFP100 - 14 × 14 mm / 0.5 mm pitch 46
Thermal resistance junction-ambient
LQFP64 - 10 × 10 mm / 0.5 mm pitch 45
Thermal resistance junction-ambient
TFBGA64 - 5 × 5 mm / 0.5 mm pitch 65
Thermal resistance junction-ambient
LQFP48 - 7 x 7 mm / 0.5 mm pitch 55
Thermal resistance junction-ambient
VFQFPN 36 - 6 × 6 mm / 0.5 mm pitch 18
Package characteristics STM32F103x8, STM32F103xB
82/91 Doc ID 13587 Rev 10
6.2.2 Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Table 57: Ordering information scheme.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature.
As applications do not commonly use the STM32F103xx at maximum dissipation, it is useful
to calculate the exact power consumption and junction temperature to determine which
temperature range will be best suited to the application.
The following examples show how to calculate the temperature range needed for a given
application.
Example 1: High-performance application
Assuming the following application conditions:
Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2),
IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output
at low level with IOL = 20 mA, VOL= 1.3 V
PINTmax = 50 mA × 3.5 V= 175 mW
PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
This gives: PINTmax = 175 mW and PIOmax = 272 mW:
PDmax = 175 + 272 = 447 mW
Thus: PDmax = 447 mW
Using the values obtained in Ta ble 5 6 TJmax is calculated as follows:
For LQFP100, 46 °C/W
TJmax = 82 °C + (46 °C/W × 447 mW) = 82 °C + 20.6 °C = 102.6 °C
This is within the range of the suffix 6 version parts (–40 < TJ < 105 °C).
In this case, parts must be ordered at least with the temperature range suffix 6 (see
Table 57: Ordering information scheme).
Example 2: High-temperature application
Using the same rules, it is possible to address applications that run at high ambient
temperatures with a low dissipation, as long as junction temperature TJ remains within the
specified range.
Assuming the following application conditions:
Maximum ambient temperature TAmax = 115 °C (measured according to JESD51-2),
IDDmax = 20 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V
PINTmax = 20 mA × 3.5 V= 70 mW
PIOmax = 20 × 8 mA × 0.4 V = 64 mW
This gives: PINTmax = 70 mW and PIOmax = 64 mW:
PDmax = 70 + 64 = 134 mW
Thus: PDmax = 134 mW
STM32F103x8, STM32F103xB Package characteristics
Doc ID 13587 Rev 10 83/91
Using the values obtained in Ta ble 5 6 TJmax is calculated as follows:
For LQFP100, 46 °C/W
TJmax = 115 °C + (46 °C/W × 134 mW) = 115 °C + 6.2 °C = 121.2 °C
This is within the range of the suffix 7 version parts (–40 < TJ < 125 °C).
In this case, parts must be ordered at least with the temperature range suffix 7 (see
Table 57: Ordering information scheme).
Figure 46. LQFP100 PD max vs. TA
0
100
200
300
400
500
600
700
65 75 85 95 105 115 125 135
TA (°C)
PD (mW)
Suffix 6
Suffix 7
%
Ordering information scheme STM32F103x8, STM32F103xB
84/91 Doc ID 13587 Rev 10
7 Ordering information scheme
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
Table 57. Ordering information scheme
Example: STM32 F 103 C 8 T 7 xxx
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
F = general-purpose
Device subfamily
103 = performance line
Pin count
T = 36 pins
C = 48 pins
R = 64 pins
V = 100 pins
Flash memory size(1)
1. Although STM32F103x6 devices are not described in this datasheet, orderable part numbers that do not
show the A internal code after temperature range code 6 or 7 should be referred to this datasheet for the
electrical characteristics. The low-density datasheet only covers STM32F103x6 devices that feature the
A code.
8 = 64 Kbytes of Flash memory
B = 128 Kbytes of Flash memory
Package
H = BGA
T = LQFP
U = VFQFPN
Temperature range
6 = Industrial temperature range, –40 to 85 °C.
7 = Industrial temperature range, –40 to 105 °C.
Options
xxx = programmed parts
TR = tape and real
STM32F103x8, STM32F103xB Revision history
Doc ID 13587 Rev 10 85/91
8 Revision history
Table 58. Document revision history
Date Revision Changes
01-jun-2007 1 Initial release.
20-Jul-2007 2
Flash memory size modified in Note 7, Note 4, Note 7, Note 8 and
BGA100 pins added to Table 5: Medium-density STM32F103xx pin
definitions. Figure 3: STM32F103xx performance line LFBGA100
ballout added.
THSE changed to TLSE in Figure 20: Low-speed external clock source
AC timing diagram. VBAT ranged modified in Power supply schemes.
tSU(LSE) changed to tSU(HSE) in Table 22: HSE 4-16 MHz oscillator
characteristics. IDD(HSI) max value added to Table 24: HSI oscillator
characteristics.
Sample size modified and machine model removed in Electrostatic
discharge (ESD).
Number of parts modified and standard reference updated in Static
latch-up. 25 °C and 85 °C conditions removed and class name modified
in Table 33: Electrical sensitivities. RPU and RPD min and max values
added to Table 34: I/O static characteristics. RPU min and max values
added to Table 37: NRST pin characteristics.
Figure 25: I2C bus AC waveforms and measurement circuit and
Figure 24: Recommended NRST pin protection corrected.
Notes removed below Tab l e 9 , Ta bl e 3 7 , Tabl e 43.
IDD typical values changed in Table 11: Maximum current consumption
in Run and Sleep modes. Table 38: TIMx characteristics modified.
tSTAB, VREF+ value, tlat and fTRIG added to Table 45: ADC
characteristics.
In Table 29: Flash memory endurance and data retention, typical
endurance and data retention for TA = 85 °C added, data retention for
TA = 25 °C removed.
VBG changed to VREFINT in Table 12: Embedded internal reference
voltage. Document title changed. Controller area network (CAN)
section modified.
Figure 12: Power supply scheme modified.
Features on page 1 list optimized. Small text changes.
Revision history STM32F103x8, STM32F103xB
86/91 Doc ID 13587 Rev 10
18-Oct-2007 3
STM32F103CBT6, STM32F103T6 and STM32F103T8 root part
numbers added (see Table 2: STM32F103xx medium-density device
features and peripheral counts)
VFQFPN36 package added (see Section 6: Package characteristics).
All packages are ECOPACK® compliant. Package mechanical data
inch values are calculated from mm and rounded to 4 decimal digits
(see Section 6: Package characteristics).
Table 5: Medium-density STM32F103xx pin definitions updated and
clarified.
Table 26: Low-power mode wakeup timings updated.
TA min corrected in Table 12: Embedded internal reference voltage.
Note 2 added below Table 22: HSE 4-16 MHz oscillator characteristics.
VESD(CDM) value added to Table 32: ESD absolute maximum ratings.
Note 3 added and VOH parameter description modified in Table 35:
Output voltage characteristics.
Note 1 modified under Table 36: I/O AC characteristics.
Equation 1 and Ta b l e 46: RAIN max for fADC = 14 MHz added to
Section 5.3.17: 12-bit ADC characteristics.
VAIN, tS max, tCONV
, VREF+ min and tlat max modified, notes modified
and tlatr added in Table 45: ADC characteristics.
Figure 30: ADC accuracy characteristics updated. Note 1 modified
below Figure 31: Typical connection diagram using the ADC.
Electrostatic discharge (ESD) on page 55 modified.
Number of TIM4 channels modified in Figure 1: STM32F103xx
performance line block diagram.
Maximum current consumption Ta bl e 1 3 , Tabl e 1 4 and Tabl e 1 5
updated. Vhysmodified in Table 34: I/O static characteristics.
Table 48: ADC accuracy updated. tVDD modified in Table 10: Operating
conditions at power-up / power-down. VFESD value added in Ta bl e 3 0:
EMS characteristics.
Values corrected, note 2 modified and note 3 removed in Tabl e 26:
Low-power mode wakeup timings.
Table 16: Typical and maximum current consumptions in Stop and
Standby modes: Typical values added for VDD/VBAT = 2.4 V, Note 2
modified, Note 2 added.
Table 21: Typical current consumption in Standby mode added. On-chip
peripheral current consumption on page 46 added.
ACCHSI values updated in Table 24: HSI oscillator characteristics.
Vprog added to Table 28: Flash memory characteristics.
Upper option byte address modified in Figure 9: Memory map.
Typical fLSI value added in Table 25: LSI oscillator characteristics and
internal RC value corrected from 32 to 40 kHz in entire document.
TS_temp added to Table 49: TS characteristics. NEND modified in
Table 29: Flash memory endurance and data retention.
TS_vrefint added to Table 12: Embedded internal reference voltage.
Handling of unused pins specified in General input/output
characteristics on page 56. All I/Os are CMOS and TTL compliant.
Figure 32: Power supply and reference decoupling (VREF+ not
connected to VDDA) modified.
tJITTER and fVCO removed from Table 27: PLL characteristics.
Appendix A: Important notes on page 81 added.
Added Figure 14, Figure 15, Figure 16 and Figure 18.
Table 58. Document revision history (continued)
Date Revision Changes
STM32F103x8, STM32F103xB Revision history
Doc ID 13587 Rev 10 87/91
22-Nov-2007 4
Document status promoted from preliminary data to datasheet.
The STM32F103xx is USB certified. Small text changes.
Power supply schemes on page 13 modified. Number of
communication peripherals corrected for STM32F103Tx and number of
GPIOs corrected for LQFP package in Table 2: STM32F103xx medium-
density device features and peripheral counts.
Main function and default alternate function modified for PC14 and
PC15 in, Note 5 added and Remap column added in Table 5: Medium-
density STM32F103xx pin definitions.
VDD–VSS ratings and Note 1 modified in Table 6: Voltage
characteristics, Note 1 modified in Table 7: Current characteristics.
Note 1 and Note 2 added in Table 11: Embedded reset and power
control block characteristics.
IDD value at 72 MHz with peripherals enabled modified in Ta bl e 1 4:
Maximum current consumption in Run mode, code with data
processing running from RAM.
IDD value at 72 MHz with peripherals enabled modified in Ta bl e 1 5:
Maximum current consumption in Sleep mode, code running from
Flash or RAM on page 41.
IDD_VBAT typical value at 2.4 V modified and IDD_VBAT maximum values
added in Table 16: Typical and maximum current consumptions in Stop
and Standby modes. Note added in Table 17 on page 44 and Table 18
on page 45. ADC1 and ADC2 consumption and notes modified in
Table 19: Peripheral current consumption.
tSU(HSE) and tSU(LSE) conditions modified in Ta ble 2 2 and Tabl e 2 3,
respectively.
Maximum values removed from Table 26: Low-power mode wakeup
timings. tRET conditions modified in Table 29: Flash memory endurance
and data retention. Figure 12: Power supply scheme corrected.
Figure 17: Typical current consumption in Stop mode with regulator in
Low-power mode versus temperature at VDD = 3.3 V and 3.6 V added.
Note removed below Figure 26: SPI timing diagram - slave mode and
CPHA = 0. Note added below Figure 27: SPI timing diagram - slave
mode and CPHA = 1(1).
Details on unused pins removed from General input/output
characteristics on page 56.
Table 41: SPI characteristics updated. Table 42: USB startup time
added. VAIN, tlat and tlatr modified, note added and Ilkg removed in
Table 45: ADC characteristics. Test conditions modified and note added
in Table 48: ADC accuracy. Note added below Ta bl e 4 6 and Ta b l e 4 9 .
Inch values corrected in Table 52: LQPF100, 100-pin low-profile quad
flat package mechanical data, Table 53: LQFP64, 64-pin low-profile
quad flat package mechanical data and Table 55: LQFP48, 48-pin low-
profile quad flat package mechanical data.
JAvalue for VFQFPN36 package added in Table 56: Package thermal
characteristics
Order codes replaced by Section 7: Ordering information scheme.
MCU ‘s operating conditions modified in Typical current consumption
on page 44. Avg_Slope and V25 modified in Ta ble 49: TS
characteristics. I2C interface characteristics on page 61 modified.
Impedance size specified in A.4: Voltage glitch on ADC input 0 on
page 81.
Table 58. Document revision history (continued)
Date Revision Changes
Revision history STM32F103x8, STM32F103xB
88/91 Doc ID 13587 Rev 10
14-Mar-2008 5
Figure 2: Clock tree on page 20 added.
Maximum TJ value given in Table 8: Thermal characteristics on
page 35.
CRC feature added (see CRC (cyclic redundancy check) calculation
unit on page 9 and Figure 9: Memory map on page 31 for address).
IDD modified in Table 16: Typical and maximum current consumptions in
Stop and Standby modes.
ACCHSI modified in Table 24: HSI oscillator characteristics on page 51,
note 2 removed.
PD, TA and TJ added, tprog values modified and tprog description clarified
in Table 28: Flash memory characteristics on page 52.
tRET modified in Table 29: Flash memory endurance and data retention.
VNF(NRST) unit corrected in Table 37: NRST pin characteristics on
page 59.
Table 41: SPI characteristics on page 63 modified.
IVREF added to Table 45: ADC characteristics on page 67.
Table 47: ADC accuracy - limited test conditions added. Table 48: ADC
accuracy modified.
LQFP100 package specifications updated (see Section 6: Package
characteristics on page 72).
Recommended LQFP100, LQFP 64, LQFP48 and VFQFPN36
footprints added (see Figure 39, Figure 41, Figure 45 and Figure 35).
Section 6.2: Thermal characteristics on page 81 modified,
Section 6.2.1 and Section 6.2.2 added.
Appendix A: Important notes on page 81 removed.
21-Mar-2008 6
Small text changes. Figure 9: Memory map clarified.
In Table 29: Flash memory endurance and data retention:
–N
END tested over the whole temperature range
cycling conditions specified for tRET
–t
RET min modified at TA = 55 °C
V25, Avg_Slope and TL modified in Table 49: TS characteristics.
CRC feature removed.
22-May-2008 7
CRC feature added back. Small text changes. Section 1: Introduction
modified. Section 2.2: Full compatibility throughout the family added.
IDD at TA max = 105 °C added to Table 16: Typical and maximum
current consumptions in Stop and Standby modes on page 42.
IDD_VBAT removed from Table 21: Typical current consumption in
Standby mode on page 47.
Values added to Table 40: SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3
V) on page 62.
Figure 26: SPI timing diagram - slave mode and CPHA = 0 on page 64
modified. Equation 1 corrected.
tRET at TA = 105 °C modified in Table 29: Flash memory endurance and
data retention on page 53.
VUSB added to Table 43: USB DC electrical characteristics on page 66.
Figure 46: LQFP100 PD max vs. TA on page 83 modified.
Axx option added to Table 57: Ordering information scheme on
page 84.
Table 58. Document revision history (continued)
Date Revision Changes
STM32F103x8, STM32F103xB Revision history
Doc ID 13587 Rev 10 89/91
21-Jul-2008 8
Power supply supervisor updated and VDDA added to Tabl e 9 : General
operating conditions.
Capacitance modified in Figure 12: Power supply scheme on page 33.
Table notes revised in Section 5: Electrical characteristics.
Table 16: Typical and maximum current consumptions in Stop and
Standby modes modified.
Data added to Table 16: Typical and maximum current consumptions in
Stop and Standby modes and Table 21: Typical current consumption in
Standby mode removed.
fHSE_ext modified in Table 20: High-speed external user clock
characteristics on page 47. fPLL_IN modified in Table 27: PLL
characteristics on page 52.
Minimum SDA and SCL fall time value for Fast mode removed from
Table 39: I2C characteristics on page 61, note 1 modified.
th(NSS) modified in Table 41: SPI characteristics on page 63 and
Figure 26: SPI timing diagram - slave mode and CPHA = 0 on page 64.
CADC modified in Table 45: ADC characteristics on page 67 and
Figure 31: Typical connection diagram using the ADC modified.
Typical TS_temp value removed from Table 49: TS characteristics on
page 71.
LQFP48 package specifications updated (see Ta ble 5 5 and Ta b l e 4 5 ),
Section 6: Package characteristics revised.
Axx option removed from Table 57: Ordering information scheme on
page 84.
Small text changes.
22-Sep-2008 9
STM32F103x6 part numbers removed (see Table 57: Ordering
information scheme). Small text changes.
General-purpose timers (TIMx) and Advanced-control timer (TIM1) on
page 15 updated.
Notes updated in Table 5: Medium-density STM32F103xx pin
definitions on page 26.
Note 2 modified below Table 6: Voltage characteristics on page 34,
|VDDx| min and |VDDx| min removed.
Measurement conditions specified in Section 5.3.5: Supply current
characteristics on page 38.
IDD in standby mode at 85 °C modified in Table 16: Typical and
maximum current consumptions in Stop and Standby modes on
page 42.
General input/output characteristics on page 56 modified.
fHCLK conditions modified in Table 30: EMS characteristics on page 54.
JA and pitch value modified for LFBGA100 package in Table 56:
Package thermal characteristics. Small text changes.
Table 58. Document revision history (continued)
Date Revision Changes
Revision history STM32F103x8, STM32F103xB
90/91 Doc ID 13587 Rev 10
23-Apr-2009 10
I/O information clarified on page 1.
Figure 3: STM32F103xx performance line LFBGA100 ballout modified.
Figure 9: Memory map modified. Table 4: Timer feature comparison
added.
PB4, PB13, PB14, PB15, PB3/TRACESWO moved from Default
column to Remap column in Table 5: Medium-density STM32F103xx
pin definitions.
PD for LFBGA100 corrected in Table 9: General operating conditions.
Note modified in Table 13: Maximum current consumption in Run
mode, code with data processing running from Flash and Ta bl e 1 5:
Maximum current consumption in Sleep mode, code running from
Flash or RAM.
Table 20: High-speed external user clock characteristics and Ta bl e 2 1:
Low-speed external user clock characteristics modified.
Figure 17 shows a typical curve (title modified). ACCHSI max values
modified in Table 24: HSI oscillator characteristics.
TFBGA64 package added (see Ta bl e 5 4 and Tab l e 4 2 ). Small text
changes.
Table 58. Document revision history (continued)
Date Revision Changes
STM32F103x8, STM32F103xB
Doc ID 13587 Rev 10 91/91
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