PI6C20400 Datasheet by Diodes Incorporated

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(EPER/COMm 1:4 Clock Driver for Intel _I__I__I__I__I__J_I__J_I__I:J_I__J_I_ u .L_L.L_L.L_L_L_L.L.L_L.L_L_L
1www.pericom.com 03/26/13
Features
• FourPairsofDifferentialClocks
• Lowskew<50ps
• Lowjitter<50ps
• OutputEnableforalloutputs
• OutputstristatecontrolviaSMBus
• PowerManagementControl
• ProgrammablePLLBandwidth
• PLLorFanoutoperation
• 3.3VOperation
• Packaging(Pb-freeandGreen):
—28-PinSSOP(H28)&28-PinTSSOP(L28)
PI6C20400
Description
PericomSemiconductor'sPI6C20400isahigh-speed,low-noise
differentialclockbufferdesignedtobecompaniontoPI6C410B.
ThedevicedistributesthedifferentialSRCclockfromPI6C410B
tofourdifferentialpairsofclockoutputseitherwithorwithout
PLL.  The clock outputs are controlled by input selection of
SRC_STOP#,PWRDWN#andSMBus,SCLKandSDA.When
input of either SRC_STOP# or PWRDWN# is low, the output
clocks are Tristated. When PWRDWN# is low, the SDA and
SCLKinputsmustbeTri-stated.
Block Diagram
1:4 Clock Driver for Intel
PCI Express Chipsets
Pin Configuration
VDD_A
VSS_A
IREF
OE_INV
VDD
OUT3
OUT3#
OE_3
OUT2
OUT2#
VDD
PLL_BW#
SRC_STOP#
PWRDWN#
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VDD
SRC
SCR#
VSS
VDD
OUT0
OUT0#
OE_0
OUT1
OUT1#
VDD
PLL/BYPASS#
SCLK
SDA
OUT0
OUT0#
OUT0
OUT1#
OUT2
OUT2#
OUT3
OUT3#
DIV
Output
Control
SMBus
Controller
PLL
PLL_BW#
SRC
SRC#
PLL/BYPASS#
SCLK
SDA
OE_INV
OE_0 & OE_3
SRC_STOP#
PWRDWN#
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Pin Descriptions
Pin Name Type Pin No Description
SRC&SRC# Input 2,3 0.7VDifferentialSRCinputfromPI6C410clocksynthesizer
OE_0&OE_3 Input 8,21
3.3VLVTTLinputforenablingoutputs,activehigh.
OE_0forOUT0/OUT0#
OE_3forOUT3/OUT3#
OE_INV Input 25
3.3VLVTTLinputforinvertingtheOE,SRC_STOP#and
PWRDWN#pins.
When0=samestage
When1=OE_0,OE_3,SRC_STOP#,PWRDWN#inverted.
OUT[0:3]&OUT[0:3]# Output 6,7,9,10,19,20,
22,23 0.7VDifferentialoutputs
PLL/BYPASS# Input 12 3.3VLVTTLinputforselectingfan-outofPLLoperation.
SCLK Input 13 SMBuscompatibleSCLOCKinput
SDA I/O 14 SMBuscompatibleSDATA
IREF Input 26 Externalresistorconnectiontosetthedifferentialoutputcurrent
SRC_STOP# Input 16 3.3VLVTTLinputforSRCstop,activelow
PLL_BW# Input 17 3.3VLVTTLinputforselectingthePLLbandwidth
PWRDWN# Input 15 3.3VLVTTLinputforPowerDownoperation,activelow
VDD Power 1,5,11,18,24 3.3VPowerSupplyforOutputs
VSS Ground 4 GroundforOutputs
VSS_A Ground 27 GroundforPLL
VDD_A Power 28 3.3VPowerSupplyforPLL
Serial Data Interface (SMBus)
ThispartisaslaveonlySMBusdevicethatsupportsindexedblockreadandindexedblockwriteprotocolusingasingle7-bit
addressandread/writebitasshownbelow.
Address assignment
A6 A5 A4 A3 A2 A1 A0 W/R
1101 1 1 0 0/1
Data Protocol
1bit 7bits 1 1 8bits 18bits 18bits 18bits 11bit
Start
bit
Slave
Addr R/W Ack Register
offset Ack
Byte
Count
=N
Ack Data
Byte0 Ack
Data
ByteN
-1
Ack Stop
bit
Notes:
1. Registeroffsetforindicatingthestartingregisterforindexedblockwriteandindexedblockread.ByteCountinwritemodecannotbe0.
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Data Byte 0: Control Register
Bit Descriptions Type Power Up Condition Output(s) Affected Source
Pin
0
OutputsMode
0=Divideby2
1=Normal
RW 1=Normal OUT[0:3],OUT[0:3]# NA
1
PLL/BYPASS#
0=Fanout
1=PLL
RW 1=PLL OUT[0:3],OUT[0:3]# NA
2
PLLBandwidth
0=HighBandwidth,
1=LowBandwidth
RW 1=Low OUT[0:3],OUT[0:3]# NA
3TBD NA
4 TBD NA
5 TBD NA
6
SRC_STOP#
0=Drivenwhenstopped
1=Tristate
RW 0=Drivenwhenstopped OUT[0:3],OUT[0:3]#
7
PWRDWN#
0=Drivenwhenstopped
1=Tristate
RW 0=Drivenwhenstopped OUT[0:3],OUT[0:3]# NA
Data Byte 1: Control Register
Bit Descriptions Type Power Up Condition Output(s) Affected Source
Pin
0
1OUTPUTSenable
1=Enabled
0=Disabled
RW 1=Enabled OUT0,OUT0# NA
2RW 1=Enabled OUT1,OUT1# NA
3
4
5 OUTPUTSenable
1=Enabled
0=Disabled
RW 1=Enabled OUT2,OUT2# NA
6RW 1=Enabled OUT3,OUT3# NA
7
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Data Byte 2: Control Register
Bit Descriptions Type Power Up Condition Output(s) Affected Source
Pin
0
1AllowcontrolofOUTPUTSwith
assertionofSRC_STOP#
0=Freerunning
1=StoppedwithSRC_Stop#
RW 0=Freerunning OUT0,OUT0# NA
2RW 0=Freerunning OUT1,OUT1# NA
3
4
5 AllowcontrolofOUTPUTSwith
assertionofSRC_STOP#
0=Freerunning
1=StoppedwithSRC_Stop#
RW 0=Freerunning OUT2,OUT2# NA
6RW 0=Freerunning OUT3,OUT3# NA
7
Data Byte 3: Control Register
Bit Descriptions Type Power Up Condition Output(s) Affected Source
Pin
0
TBD
RW
1RW
2RW
3RW
4RW
5RW
6RW
7RW
Data Byte 4: Pericom ID Register
Bit Descriptions Type Power Up Condition Output(s) Affected Pin
0
PericomID
R 0 NA NA
1R 0 NA NA
2 R 0 NA NA
3R 0 NA NA
4 R 0 NA NA
5 R 1NA NA
6 R 0 NA NA
7 R 0 NA NA
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PWRDWN#
OUT
OUT#
Tdrive_PwrDwn#
<300us, >200mV
Tstable
<1ms
Functionality
PWRDWN# OUT OUT# SRC_Stop# OUT OUT#
1Normal Normal 1Normal Normal
0 IREF×2orFloat Low 0 IREF×6orFloat Low
Power Down (PWRDWN# assertion)
Figure 1. Power down sequence
PWRDWN#
OUT#
OUT
Power Down (PWRDWN# De-assertion)
Figure 2. Power down de-assert sequence
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Current-mode output buffer characteristics of OUT[0:3], OUT[0:3]#
Figure 9. Simplified diagram of current-mode output buffer
0V
IOUT
0.85V
Slope ~ 1/Rs
RO
ROS
VOUT = 0.85V max
Iout
V
DD
(3.3V ± 5%)
Differential Clock Buffer characteristics
Symbol Minimum Maximum
RO3000Ω N/A
ROS unspecified unspecified
VOUT N/A 850mV
Current Accuracy
Symbol Conditions Configuration Load Min. Max.
IOUT VDD=3.30±5% RREF=475Ω1%
IREF=2.32mA
Nominaltestloadforgiven
configuration
-12%
INOMINAL
+12%
INOMINAL
Note:
1. INOMINALreferstotheexpectedcurrentbasedontheconfigurationofthedevice.
Differential Clock Output Current
Board Target Trace/Term Z Reference R, Iref = VDD/(3xRr) Output Current VOH @ Z
100Ω
(100Ωdifferential15%couplingratio)
RREF=475Ω1%,
IREF=2.32mA IOH=6xIREF 0.7V@50
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Absolute Maximum Ratings (Overoperatingfree-airtemperaturerange)
Symbol Parameters Min. Max. Units
VDD_A 3.3VCoreSupplyVoltage -0.5 4.6
V
VDD 3.3VI/OSupplyVoltage -0.5 4.6
VIH InputHighVoltage 4.6
VIL InputLowVoltage -0.5
Ts StorageTemperature -65 150 °C
VESD ESDProtection 2000 V
Note:
1. Stressbeyondthoselistedunder“AbsoluteMaximumRatings”maycausepermanentdamagetothedevice.
DC Electrical Characteristics (VDD=3.3±5%,VDD_A=3.3±5%)
Symbol Parameters Condition Min. Max. Units
VDD_A 3.3VCoreSupplyVoltage 3.135 3.465
V
VDD 3.3VI/OSupplyVoltage 3.135 3.465
VIH 3.3VInputHighVoltage VDD 2.0 VDD+0.3
VIL 3.3VInputLowVoltage VSS–0.3 0.8
IIK InputLeakageCurrent 0<VIN<VDD -5 +5 μA
VOH 3.3VOutputHighVoltage IOH=-1mA 2.4 V
VOL 3.3VOutputLowVoltage IOL=1mA 0.4
IOH OutputHighCurrent IOH=6xIREF,
IREF=2.32mA
12.2 mA
15.6
CIN InputPinCapacitance 35pF
COUT OutputPinCapacitance 6
LPIN PinInductance 7 nH
IDD PowerSupplyCurrent VDD=3.465V,FCPU=200MHz 200
mAISS PowerDownCurrent Drivenoutputs 40
ISS PowerDownCurrent Tristateoutputs 12
TAAmbientTemperature 0 70 °C
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AC Switching Characteristics (VDD=3.3±5%,VDD_A=3.3±5%)
Symbol Parameters Min Max. Units Notes
Trise/Tfall RiseandFallTime(measuredbetween0.175Vto0.525V) 175 700 ps 2
ΔTrise/
ΔTfall RiseandFallTimeVariation 125 ps 2
Rise/FallMatching 20 % 2
Tpd
PLLMode ±250 ps
Non-PLLMode 2.5 6.5 ns
Tskew Output-to-OutputSkew 50 ps 3
Tjitter Cycle–CycleJitter 50 ps 3,4
VHIGH VoltageHighincludingovershoot 660 1150 mV 2
VLOW VoltageLowincludingundershoot -300 mV 2
Vcross Absolutecrossingpointvoltages 250 550 mV 2
ΔVcross TotalVariationofVcrossoveralledges 140 mV 2
TDC DutyCycle 45 55 % 3
Notes:
1. TestconfigurationisRs=33.2Ω,Rp=49.9Ω,and2pF.
2. MeasurementtakenfromSingleEndedwaveform.
3. MeasurementtakenfromDifferentialwaveform.
4. MeasurementtakenusingM1datacaptureanalysistool.
Configuration Test Load Board Termination
475
1%
49.9
1%
Rp
49.9
1%
Rp
33
5%
Rs
33
5%
Rs
PI6C20400
TLA
TLB
OUT
OUT#
2pF
5%
2pF
5%
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(DPER/COM‘ PI6c204oo 1:4 Clock Driver for Intel PCI Express Chipsets VARWONS (ALL D‘MENS‘DNS SHOWN \N W) SYMEOLS M‘N NOM. MAX A 7 7 ‘ 20 M 0.05 7 0 15 A; u an ‘ an ‘ 05 b El V9 7 0 30 7 u 09 7 020 D 9 60 9,70 9 50 E‘ 4 JD 4 40 4750 E 5740 ESE El 0,65 55c H mm REF L U 45 U 50 0 75 S U 20 7 7 b 0‘ 7 E' u L7, n Emu g SUNNG PLANE 7 7 + \ wag W m 2 Emma m om p U IDPBWCDM‘ MWWM
9
PI6C20400
1:4 Clock Driver for Intel PCI Express Chipsets
www.pericom.com 03/26/13
DATE: 05/03/12
PACKAGE CODE: L
DOCUMENT CONTROL #: PD-1313 REVISION: E
Notes:
1. Refer JEDEC: MO-153F/AE
2. Controlling dimensions in millimeters
3. Package outline exclusive of mold flash and metal burr
DESCRIPTION: 28 pin, 173mil wide, TSSOP
12-0375
14-0197
(DPER/COM‘ PI6c204oo 1:4 Clock Driver for Intel PCI Express Chipsets vAwAnoNs (ALL B‘MENS‘OVS SHOWN w W) 25 ‘5 SYMBOLS WN NOM. MAX A r r V 20 HHHHHHWWWWi M , AZ U 50 ‘ 00 V 05 b [I ‘9 7 O 30 U 09 7 D 10 , m D 9 5o 9 7a 9 50 “J E‘ 4 so 4 4o 4 50 5.40 BSC @ E 0.55 Est: LV 1 00 REF H HHHH HHHHHHi L 7 7 S El 10 7 7 ‘ ‘4 (l D‘ 7 5' E! b u L,» W I 2 ‘1 w W? :f q 2 H }g f5mm m U (DPER/caM‘ MM
10
PI6C20400
1:4 Clock Driver for Intel PCI Express Chipsets
www.pericom.com 03/26/13
Ordering Information(1-3)
Ordering Code Package Code Package Description
PI6C20400HE HE 28-pin,209-milwide,SSOP,Pb-FreeandGreen
PI6C20400LE LE 28-pin,173-milwide,TSSOP,Pb-FreeandGreen
Notes:
1. Thermalcharacteristicscanbefoundonthecompanywebsiteatwww.pericom.com/packaging/
2. E=Pb-freeandGreen
3. AddinganXsuffix=Tape/Reel
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
DATE: 05/03/12
PACKAGE CODE: L
DOCUMENT CONTROL #: PD-1313 REVISION: E
Notes:
1. Refer JEDEC: MO-153F/AE
2. Controlling dimensions in millimeters
3. Package outline exclusive of mold flash and metal burr
DESCRIPTION: 28 pin, 173mil wide, TSSOP
12-0375
14-0197

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