CYRF8935 Datasheet by Cypress Semiconductor Corp

View All Related Products | Download PDF Datasheet
CYPRESS” 29me 30c L8 8295809 ”.02 w 0 R R o M o T m D E D D E a M E A if
CYRF8935
WirelessUSB™ NL 2.4 GHz
Low Power Radio
Cypress Semiconductor Corporation 198 Champion Court San Jose,CA 95134-1709 408-943-2600
Document Number: 001-61351 Rev. *K Revised May 19, 2017
WirelessUSB™ NL 2.4 GHz Low Power Radio
Features
Fully integrated 2.4 GHz radio on a chip
1 Mbps over-the-air data rate
Transmit power typical: 0 dBm
Receive sensitivity typical: –87 dBm
1 µA typical [1] current consumption in sleep state
Closed-loop frequency synthesis
Supports frequency-hopping spread spectrum
On-chip packet framer with 64-byte first in first out (FIFO) data
buffer
Built-in auto-retry-acknowledge protocol simplifies usage
Built-in cyclic redundancy check (CRC), forward error
correction (FEC), data whitening
Supports DC ~ 12 MHz SPI bus interface
Additional outputs for interrupt request (IRQ) generation
Digital readout of received signal strength indication (RSSI)
4 × 4 mm quad flat no-leads (QFN) package, bare die, or wafer
sales
Functional Description
WirelessUSB™-NL, optimized to operate in the 2.4-GHz ISM
band, is Cypress's third generation of 2.4-GHz low-power RF
technology, bringing the next level of low-power performance
into a small 4-mm × 4-mm footprint. WirelessUSB-NL
implements a Gaussian frequency-shift keying (GFSK) radio
using a differentiated single-mixer, closed-loop modulation
design that optimizes power efficiency and interference
immunity. Closed-loop modulation effectively eliminates the
problem of frequency drift, enabling WirelessUSB-NL to transmit
up to 255-byte payloads without repeatedly having to pay power
penalties for re-locking the phase locked loop (PLL) as in
open-loop designs.
Among the advantages of WirelessUSB-NL are its fast lock times
and channel switching, along with the ability to transmit larger
payloads. Use of longer payload packets, compared to multiple
short payload packets, can reduce overhead, improve overall
power efficiency, and help alleviate spectrum crowding.
Combined with Cypress's enCoRe™ family of USB and wireless
microcontrollers, WirelessUSB-NL also provides the lowest bill
of materials (BOM) cost solution for PC peripheral applications
such as wireless keyboards and mice, as well as best-in-class
wireless performance in other demanding applications such as
toys, remote controls, fitness, automation, presenter tools, and
gaming.
Applications
Wireless keyboards and mice
Handheld remote controls
Wireless game controllers
Hobby craft control links
Home automation
Industrial wireless links and networks
Cordless audio and low-rate video
Note
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VIN = 3 VDC, Ta = +25 °C.
Not recommended for new designs
mcgmmu >5: L8 umucmEEooE Hoz
CYRF8935
Document Number: 001-61351 Rev. *K Page 2 of 40
Logic Block Diagram
MISO
RST_n
CLK
MOSI
SPI_SS
FIFO
PKT
XTALo
Synthesizer
BRCLK
XTALi
VOUT
VDD_IO
VIN
ANT
Xtal Osc X
VCO
LNA + BPF
GFSK
Modulator
LDO Linear
Regulator
PA
Image
Rej. Mxr.
SPI Registers
Framer
ANTb
GFSK
Demodulator
GND GND
Pwr/ Reset
VDD1 ...VDD7
[2]
Note
2. BRCLK signal is available on bare die only, not packaged parts.
Not recommended for new designs
CYPRESS smmm m munnow A 2-” 29me 30: L8 vmvcmEEoomL “oz
CYRF8935
Document Number: 001-61351 Rev. *K Page 3 of 40
Contents
Pin Configuration .............................................................4
Pin Descriptions ...............................................................4
Functional Overview ........................................................5
Power-on and Register Initialization Sequence ........... 5
Enter Sleep and Wakeup ............................................ 6
Packet Data Structure .................................................6
FIFO Pointers ..............................................................6
Packet Payload Length ...............................................6
Framer: Packet Length Handling .................................7
MCU or Application Handles Packet Length ............... 9
Typical Application .........................................................12
Setting the Radio Frequency ..................................... 13
Crystal Oscillator .......................................................13
Minimum Pin Count ................................................... 14
Reset Pull-up ............................................................. 14
Transmit Power Control .............................................14
Reading RSSI ............................................................14
Automatic ACK .......................................................... 15
Receive CRC and FEC Result .................................. 15
Sync Word Selection .................................................15
Scramble On/Off Selection ........................................ 16
Measuring Receiver Sensitivity .................................16
Receive Spurious Responses ................................... 17
RF VCO Calibration ...................................................17
Regulatory Compliance .................................................18
United States FCC ....................................................18
Register Settings for Test Purposes .......................... 19
Recommendations for PCB Layout ..............................19
Antenna Type and Location ..........................................19
IR Reflow Standard .........................................................20
Register Definitions ........................................................21
Recommended Register Values ................................ 26
Absolute Maximum Ratings ..........................................28
Operating Range .............................................................28
Electrical Characteristics ...............................................28
SPI ....................................................................................31
SPI Transaction Formats and Timing ........................ 31
Specifications ............................................................ 32
Electrical Operating Characteristics .............................33
State Diagram .................................................................34
Ordering Information ......................................................35
Ordering Code Definitions ......................................... 35
Package Diagram ............................................................36
Acronyms ........................................................................37
Document Conventions .................................................37
Units of Measure ....................................................... 37
Document History Page .................................................38
Sales, Solutions, and Legal Information ......................40
Worldwide Sales and Design Support ....................... 40
Products .................................................................... 40
PSoC® Solutions ...................................................... 40
Cypress Developer Community ................................. 40
Technical Support ..................................................... 40
Not recommended for new designs
mcgmmv >>mc Lou, UmvcmEEooE “oz mmnznmmumw CYPRESS A 2-)
CYRF8935
Document Number: 001-61351 Rev. *K Page 4 of 40
Pin Configuration
Figure 1. 24-pin QFN pinout (Top View)
Pin Descriptions
Table 1. CYRF8935 24-pin QFN (4 × 4 mm) pinout
Pin Number Pin Name Type Description
6, 7 Test2, Test3 -- Reserved for factory test. Do not connect.
1, 2, 5, 8, 9, 19, 22 VDD1 to VDD7 PWR Core power supply voltage. Connect all VDD pins to VOUT pin.
3, 4 ANTb, ANT RF Differential RF input/output. See Typical Application on page 12 for recom-
mended antenna hookup. Each of these pins must be DC grounded, 20 k or
less
10 FIFO O FIFO status indicator bit
12, 25 GND GND Ground connection
11 VDD_IO PWR VDD for the digital interface
13 SPI_SS I Enable input for SPI, active low. Also used to bring device out of sleep state.
14 PKT O Transmit/receive packet status indicator bit
15 CLK I Clock input for SPI interface
16 MOSI I Data input for the SPI bus
17 MISO O/High-Z Data output (tristate when not active)
18 RST_n I RST_n Low: Chip shutdown to conserve power. Register values lost
RST_n High: Turn on chip, registers restored to default value
20 VIN PWR Unregulated input voltage to the on-chip low drop out (LDO) voltage regulator
21 VOUT PWR +1.8 V output from on-chip LDO. Connect to all VDD pins, do not connect to
external loads.
23 XTALo AO Output of the crystal oscillator gain block
24 XTALi AI Input to the crystal oscillator gain block
Not recommended for new designs
unlnnw 91.55.39 A 2-) mcgmmu >5: L8 umucmEEooE Hoz
CYRF8935
Document Number: 001-61351 Rev. *K Page 5 of 40
Functional Overview
The CYRF8935 RF transceiver can add wireless capability to a
wide variety of applications.
The product is a low-cost, fully-integrated CMOS RF transceiver,
GFSK data modem, and packet framer, optimized for use in the
2.4-GHz ISM band. It contains transmit, receive, RF synthesizer,
and digital modem functions, with few external components. The
transmitter supports digital power control. The receiver uses
extensive digital processing for excellent overall performance,
even in the presence of interference and transmitter
impairments.
The product transmits GFSK data at approximately 0-dBm
output power. Sigma-Delta PLL delivers high-quality DC-coupled
transmit data path.
The low-IF receiver architecture produces good selectivity and
image rejection, with typical sensitivity of –87 dBm or better on
most channels. Sensitivity on channels that are integer multiples
of the crystal reference oscillator frequency (12 MHz) may show
approximately 5 dB degradation. Digital RSSI values are
available to monitor channel quality.
On-chip transmit and receive FIFO registers are available to
buffer the data transfer with MCU. Over-the-air data rate is
always 1 Mbps even when connected to a slow, low-cost MCU.
Built-in CRC, FEC, data whitening, and automatic
retry/acknowledge are all available to simplify and optimize
performance for individual applications.
Power-on and Register Initialization Sequence
For proper initialization at power up, VIN must ramp up at the
minimum overall ramp rate no slower than shown by TVIN speci-
fication in the following figure. During this time, the RST_n line
must track the VIN voltage ramp-up profile to within approxi-
mately 0.2 V. Since most MCU GPIO pins automatically default
to a high-Z condition at power up, it only requires a pull-up
resistor, as shown in Figure 11 on page 14. When power is stable
and the MCU POR releases, and MCU begins to execute instruc-
tions, RST_n must then be pulsed low as shown in Figure 2,
followed by writing Reg[27] = 0x4200. During or after this SPI
transaction, the State Machine status can be read to confirm
FRAMER_ST= 1, indicating a proper initialization.
Figure 2. Power-on and Register Programming Sequence
After RST_n transitions from 0 to 1, BRCLK[3] begins running at 12-MHz clock.
After register initialization, CYRF8935 is ready to transmit or receive.
VIN
RST_n
BRCLK
SPI_SS
Clock unstable
Clock stable
SPI Activity
TRSU
TRPW
TCMIN (not drawn to scale)
Write Reg[27]=
0x4200
TVIN
Table 2. Initialization Timing Requirements
Timing Parameter Min Max Unit Notes
TRSU 20 ms 2 < TVIN6.5 [ms/V] Reset setup time necessary to ensure
complete reset
TRPW 1 10 µs Reset pulse width necessary to ensure complete reset
TCMIN 3 ms Minimum recommended crystal oscillator and APLL settling time
TVIN 6.5 ms/V Maximum ramp time for VIN, measured from 0 to 100% of final voltage. For
example, if VIN= 3.3 V, the max ramp time is 6.5 × 3.3 = 21.45 ms. If VIN=
1.9 V, the max ramp time = 6.5 × 1.9 = 12.35 ms.
Note
3. BRCLK signal is available on bare die only, not packaged parts.
Not recommended for new designs
A E wcgwoc Em: L8 coccoEEoom: “oz
CYRF8935
Document Number: 001-61351 Rev. *K Page 6 of 40
Figure 3. Initialization Flowchart
Enter Sleep and Wakeup
When the MCU or application writes to the CYRF8935 register 35[14] to enter sleep mode and deasserts SPI_SS, CYRF8935 enters
the sleep state where current consumption is extremely low.
Later, when SPI_SS is reasserted, CYRF8935 automatically wakes up from the sleep state. At this time the crystal oscillator is
reactivated. The crystal oscillator takes 1 to 3 ms to become fully stable. During wakeup, there is no requirement to clear register
35[14] and no requirement to hold SPI_SS asserted.
There are two sleep current choices available, selectable by Reg[27] setting: 1 µA[4] and 8 µA. If you use the 1-µA setting, Vin must
be greater than or equal to 3.0 VDC. If Vin is ever expected to be < 3.0 VDC during Sleep, use the 8-µA setting. The 1-µA Sleep
setting should only be used for long-term sleep such as 8 to 10 seconds or more.
To achieve the lowest sleep current, a special sleep state firmware patch is required. The patch is as follows:
SLEEP PATCH: Before writing register 35 to enter sleep, write Reg[10]= 0x8FFD, wait 30 µs or more, then write Reg[10] back to the
default value of 0x7FFD. Next, write Reg[35] to enter sleep, as usual.
Packet Data Structure
Figure 4. Packet Structure
Each over-the-air CYRF8935 packet is structured as follows:
Preamble: 1 to 8 bytes, programmable
SYNC: 16/32/48/64 bits, programmable as device sync word
Trailer: 4 to 18 bits, programmable
Payload: TX/RX data
CRC:16-bit CRC (Optional)
FIFO Pointers
The FIFO write pointer must be cleared before the application
writes data to FIFO for transmit. This is done by writing '1' to
register 52[15].
After receiving a packet, the write pointer at register 52[13:8]
indicates how many bytes of receive data are waiting in the FIFO
buffer to be read by the user MCU or the application.
The FIFO write pointer is automatically cleared when the
receiver receives SYNC.
The FIFO read pointer is automatically cleared when the receiver
receives SYNC, or after transmitting SYNC in transmit mode.
Packet Payload Length
There are two ways to handle the TX/RX packet lengths in
CYRF8935. If register 41[13] is equal to 1, the CYRF8935
internal framer detects the packet length based on the value of
the first payload byte. If register 41[13] is equal to 0, the first byte
of the payload has no particular meaning, and packet length is
determined by either TX FIFO running empty or TX_EN bit
cleared (see Ta bl e 3).
Initialize
CYRF8935 at
power-up
MCU generates
negative- going
RST_n pulse
Wait Crystal
Enable Time
Initialize
Registers,
beginning with
Reg[27]
Initialization
Done
RST_n pulls up
along with Vin
Preamble Sync word(s) Trailer <== P a y l o a d ==> CRC
Note
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VIN = 3 VDC, Ta = +25 °C.
Not recommended for new designs
29me >5: L8 umucmEEooE goz r——_——1 X77 "‘Z unlnnw 9,133.39 A 2-)
CYRF8935
Document Number: 001-61351 Rev. *K Page 7 of 40
The following sections show the detailed timing diagrams. All timing diagrams show active high for PKT and FIFO flags. Active low is
also available through register 41[10] setting.
Framer: Packet Length Handling
The CYRF8935 framer handles packet length by setting register
41[13] = 1. The first byte of the payload is regarded as packet
length (this length byte is not counted in the packet length). The
CYRF8935 supports packet lengths up to 255 bytes. The framer
handles Tx/Rx start and stop.
Transmit Timing
The Tx timing diagram is shown in Figure 5. After MCU writes
register 7[8]= TX_EN = 1, the framer automatically generates the
Tx packet using payload data from the FIFO register. The
frequency (RF channel) will be as specified in register 7 at the
time TX_EN is written to 1.
The MCU or application must load transmit data into the FIFO
register before the framer sends trailer bits. You can do this by
loading the transmit payload data into the FIFO register either
before or after writing TX_EN = 1. For slower applications, it is
easier to load the FIFO register, and then write TX_EN = 1. For
the higher frame rate (faster) applications, write register 7
TX_EN = 1, and then load the FIFO register with payload data
during the Tx on delay time, as shown in Figure 5.
If the packet length exceeds the FIFO length, the MCU must
write FIFO data multiple times. The FIFO flag indicates whether
FIFO is empty in transmit state.
Figure 5. Tx Timing Diagram when Register 41[13] = 1 (Framer Handles Packet Length)
PKT and FIFO Flags are Active High
Table 3. CYRF8935 Configuration for Packet Length
Register 41[13]
PACK_LENGTH_EN Register 41[12]
FW_TERM_TX CYRF8935 Framer Start/Stop
0
(MCU or application handles
packet length)
0 Transmit stops only when Register 7 TX_EN = 0.
See FW_TERM_TX = 0 (Transmit) on page 10 for details.
Receive stops only when Register 7 RX_EN = 0.
See FW_TERM_TX= 0 (Receive) on page 11 for details.
1 Transmit automatically stops whenever FIFO runs empty.
Receive stops only when Register 7 RX_EN = 0.
See Receive Timing on page 8.
1
(CYRF8935 framer handles
packet length)
x
(do not care)
The first byte of payload is regarded as packet length, 0 to 255 bytes.
Transmit automatically stops when all 0 to 255 bytes are transmitted.
See Framer: Packet Length Handling on page 7 for details.
SPI_SS
Internal
Tx On 2 µs
Tx On Delay PA Ramp Up
Tx Packet
Transmit Data
Write Reg. 7
FIFO
MCU fills FIFO before framer sends trailer bits.
PKT = 1 after Tx packet has been sent.
FIFO = 1 when FIFO is empty
PKT
Not recommended for new designs
wcgwoc 26: L8 coccoEEoom: “oz r—————1 74
CYRF8935
Document Number: 001-61351 Rev. *K Page 8 of 40
Receive Timing
Figure 6 shows the Rx timing diagram. The receive process
begins when the MCU writes register 7[7] = 1. At this time, the
CYRF8935 framer turns on the receiver and waits while
attempting to detect a valid syncword. The receive frequency is
specified within register 7. The two register 7 fields of interest,
RX_EN and RF_PLL_CH_NO, may be sent to CYRF8935 during
the same SPI transaction. If sent in separate SPI transactions,
send the RF_PLL_CH_NO first, followed by RX_EN.
If a valid syncword is found, the CYRF8935 framer processes the
packet automatically. When the received packet processing is
complete, the CYRF8935 framer sets the state to IDLE.
If the received packet length is longer than 63 bytes, the FIFO
flag goes active, which means the MCU must read out data from
the FIFO.
A valid syncword might not always be found, either due to a weak
signal, multi-path cancellation, or devices being out of range. To
accommodate such a condition and to prevent lockup, the
application or the MCU must incorporate a 'receive timeout' timer
to clear RX_EN and return to the IDLE state.
Figure 6. Rx Timing Diagram when Register 41[13] = 1 (Framer Handles Packet Length)
PKT and FIFO Flags are Active High
SPI_SS
Internal Rx_on
2 µs
Receive On Delay
Rx Packet
Received Data
Write Reg. 7
FIFO
PKT = 1 when Rx packet has been
received by Framer.
FIFO = 1 when FIFO is full.
PKT
Not recommended for new designs
A L _J 4’ 4b ayfi <— ya="" x—="" :="" i="" i="" not="" recommended="" for="" new="" designs="">
CYRF8935
Document Number: 001-61351 Rev. *K Page 9 of 40
MCU or Application Handles Packet Length
When register 41[13] = 0, the first byte of the payload data has no special significance and the packet length depends on register
41[12].
FW_TERM_TX = 1
If register 41[12] = 1, the CYRF8935 framer continues to compare the FIFO write point and the FIFO read point during packet
transmission. If the MCU or application stops writing data to FIFO, the framer eventually detects that there is no data to send (FIFO
is empty), and CYRF8935 exits ‘cease transmission’ automatically (see Figure 7).
Figure 7. Tx Timing When Register 41[13:12] = '01b PKT and FIFO Flags are Set as Active High
Note When register 41[13] = 0 (MCU or application handles packet length), never let FIFO underflow or overflow. FIFO full and empty
thresholds can be controlled using register 40 FIFO_EMPTY_THRESHOLD and FIFO_FULL_THRESHOLD settings. The best value
depends on SPI speed and the speed at which the MCU or application can stream the data into FIFO.
SPI_SS
Internal
Tx on 2 µs
Tx On Delay PA On Delay
Packet Tx
Internal
Tx Data
Write Reg. 7
TX_ EN = 1
MCU fills FIFO before framer sends trailer bits.FIFO = 1 when
FIFO is empty.
Framer will terminate Tx when FIFO
write point equals FIFO read point.
PKT
FIFO
Not recommended for new designs
unlnnw Elflfifiss A E 39on >5: L8 vovcoEEoom: “oz
CYRF8935
Document Number: 001-61351 Rev. *K Page 10 of 40
FW_TERM_TX = 0 (Transmit)
When register 41[13:12] = '00b, the CYRF8935 framer does not stop packet transmission until MCU or application writes register 7[8]
TX_EN bit = 0. Packet transmission continues even if FIFO is empty (see Figure 8).
Figure 8. TX Timing Diagram when Register 41[13:12] = '00b PKT and FIFO Flags are Shown Active High
Note When register 41[13] = 0 (MCU or application handles packet length), never let FIFO underflow or overflow. FIFO full and empty
thresholds can be controlled through register 40 FIFO_EMPTY_THRESHOLD and FIFO_FULL_THRESHOLD settings. The best
value depends on SPI speed and the speed at which the MCU or application can stream the data into FIFO.
SPI_SS
Internal Tx
2 µs
Transmit Delay PA On Delay
Packet TXInternal Tx Data
Write Reg. 7
TX_ EN = 1
PKT
FIFO
MCU fills FIFO before framer sends trailer bits.
FIFO = 1
when FIFO is empty.
Framer terminates Tx when MCU or
application writes Reg. 7 TX_ EN = 0.
Write Reg. 7
TX_ EN = 0
2 µs
Not recommended for new designs
Raw A E wcgwoc 26: L8 coccoEEoom: “oz
CYRF8935
Document Number: 001-61351 Rev. *K Page 11 of 40
FW_TERM_TX= 0 (Receive)
When register 41[13] = 0, packet reception starts when MCU or
application writes register 7[7] RX_EN = 1. At this time, the
framer automatically turns on the receiver to the frequency and
channel specified in register 7. After waiting for the internal
synthesizer and receiver delays, the framer circuitry of the
CYRF8935 begins searching the incoming signal for a syncword.
When the syncword is detected, the framer sets the PKT flag
active, and then starts to fill the FIFO with receive data bytes. The
PKT flag remains active until the MCU or application reads out
the first byte of data from the FIFO register. After the MCU or
application reads the first byte of receive data, the PKT flag goes
inactive until the next Tx/Rx period.
With register 41[13:12] = '00b or '01b, the CYRF8935 framer
always needs the MCU or application to write register 7[7] to 0
to stop the Rx state.
The Rx timing diagram is shown in Figure 9.
Figure 9. RX Timing Diagram when Register 41[13:12] = '00b or '01b
PKT_flag and FIFO_flag are Active High
SPI_SS
Internal Rx On
2 µs
Internal Rx On Delay
Packet Rx Data
Internal Rx Data
Write
Reg. 7
PKT
FIFO
PKT = 1 when syncword received.
PKT = 0 when MCU/application reads first byte from FIFO register.
Write
Reg. 7
2 µs
FIFO = 1 when FIFO is full.
Not recommended for new designs
acvanss ' muons» In Vollonlow’ Iii Hu- Not recommended for new designs
CYRF8935
Document Number: 001-61351 Rev. *K Page 12 of 40
Typical Application
C7
15pF
C6
4.7uF
C5
0.10uF
C8
15pF
C1
0.10uF
R3
2.2k
C4
0.10uF
SPI_miso
RST_n
SPI_mosi
SPI_ss
FIFO_flag
PKT_flag
+1.8V
+3.3V
+1.8V
+1.8V
Y1
Quartz xtal 12MHz
C3
1.0pF L1
2.2nH
+3.3V
R2
680k
50 Ohm
1
3
2
4
J1
SMA
R4
20k Antenna conn.
Notes:
1. ANT pin requires DC path to ground. If
antenna or RF test equipment does not provide
this, R4= 20k Ohm is required.
2. Max. input noise on Vin: 50 mV pk.
R1
51
Note 1
XTALo
23
XTALi
24
CLK
15
GND 12
PKT
14
VDD2 2
ANT 4
ANTb 3
RST_n
18
MISO
17
VDD3 5
VDD5 9
SPI_SS
13
VDD4 8
MOSI
16
VDD6
19
VDD_IO 11
FIFO 10
Vin
20
VDD1 1
Test2 6
Test3 7
Vout
21
VDD7
22
GND
25
GND
25
U1
CYRF8935
SPI_CLK
R5
10k
Ceramic
ESR < 4 Ohms
Note 2
+3.3V
MCU Interface
Not recommended for new designs
{EMPRESS ' mznmmmnnnnw OD Not recommended for new designs
CYRF8935
Document Number: 001-61351 Rev. *K Page 13 of 40
Setting the Radio Frequency
Programming by channel number is the easiest way to set
frequency. In the CYRF8935, RF carrier frequency and RF
channel number are always related by the expression:
Freq. = 2402 + Ch. #
Channel number is loaded into bits [6:0] of Register 7. Bits 7 and
8 initiate the desired Rx or Tx operation, respectively.
Some sample Register 7 examples are as shown in Tab le 4.
During Regulatory Compliance testing, you can jump directly to
another frequency any time without going through IDLE state. If
you change between Tx and Rx, however, you must pass
through IDLE state. For IDLE state, write Register 7 to clear bits
8 and 7. Tx or Rx operation is initiated when Register 7 bit 8 or
7 is set. Radio frequency is also determined at that time.
Crystal Oscillator
The CYRF8935 contains the on-chip gain block for the quartz
crystal frequency standard.
Quartz Crystal Application
As shown in Figure 10 on page 14, the series resistor Rs limits
power to the crystal and contributes to the phase-shift necessary
for oscillation. The ideal Rs value may need to be determined
empirically, adjusted for certain crystal manufacturer part
numbers and designs. The series equivalent combinations of C1
and C2 largely determine the capacitive load seen by the crystal,
which should match the crystal vendor's specification. These
capacitor values are chosen to center the crystal oscillator
frequency at the correct value, 12 MHz. The feedback resistor Rf
from the buffer output to input serves to self-bias the on-chip
buffer to the center of the linear region for maximum gain.
Verifying correct crystal oscillator frequency may require special
test methods. Because connecting a frequency counter probe to
either XTALi or XTALo adds capacitive loading and alters the
crystal oscillation frequency, other methods must be used. For
bare die applications involving COB packaging, use the
BRCLK[5] test point to verify correct frequency of oscillation. This
requires register 32[3:1] set accordingly (see Register Defini-
tions on page 21). For 24-QFN packaged parts, the correct
crystal frequency is determined by transmitting a continuous
carrier frequency (see Register Settings for Test Purposes on
page 19) and using a RF frequency counter to ensure correct
frequency. Irrespective of which method is used, initial tolerance
should be within budget as recommended in Ta bl e 5, such that
the total frequency error stays within budget.
Note For proper operation, the total frequency error must not
exceed what is shown in Tabl e 5. Individual error contributions
can be adjusted; for example 10+20+5+5=40, or 5+30+2+3=40.
Table 4. Sample Register 7 Settings
Carrier Frequency,
MHz DUT Channel Number
(decimal)
DUT Channel
Number
(hex)
Tx setting:
Reg. 7 value
for TX_EN= 1
Rx setting:
Reg. 7 value
for RX_EN= 1
2402 0 00 0100 0080
2403 1 01 0101 0081
2404 2 02 0102 0082
| | | | |
2434 32 20 0120 00A0
| | | | |
2441 39 27 0127 00A7
| | | | |
2480 78 4E 014E 00CE
Table 5. Crystal Specifications
Crystal Parameter Specification
Frequency 12.000 MHz
Initial frequency tolerance ±15 ppm
Frequency tolerance over
temperature
±15 ppm
Frequency tolerance after
aging
±5 ppm
Frequency drift due to load
cap. drift
±5 ppm
Total ±40 ppm
Equivalent series resistance 80 max
Resonance mode Fundamental, parallel resonant
Load capacitance In accordance with external load
capacitors (see C1 and C2 in
Figure 10)
Note
5. BRCLK signal is available on bare die only, not packaged parts.
Not recommended for new designs
muons») m vow-now- we CYPRESS A . ) '1 89mg 26: Lou, 8958882 62 w m W W
CYRF8935
Document Number: 001-61351 Rev. *K Page 14 of 40
Figure 10. Simplified Schematic of Crystal Oscillator
Note When crystal oscillator is constructed as shown in Typical
Application on page 12, Ta bl e 5 on page 13, and Figure 10, the
oscillation frequency should be stable within 3 mS (max) after
startup.
Minimum Pin Count
When a low-cost MCU drives the CYRF8935, the MCU pin count
must be minimized.
FIFO pin: Only needed when the Tx or Rx packet length is
greater than around 63 bytes, up to infinity. For short packets
(< 63 bytes), FIFO is not needed.
PKT pin: Gives a hardware indication of a packet received. If
you are willing to poll register 48 for this information, then this
pin is not needed.
SPI lines: All four lines are needed.
Reset Pull-up
For proper power-up initialization, the RST_n pin must have a
pull-up to VIN, as shown in Figure 11. The exact value of the 10-k
pull-up resistor is not critical. The pull-up resistor ensures proper
operation of the CYRF8935 internal-level shifter circuitry while
power is applied. Subsequently, the RST_npulse resets the
internal registers to their default state.
Figure 11. Reset Pull-up Circuit
Transmit Power Control
Tabl e 6 lists recommended settings for register 9 for short-range
applications, where reduced transmit RF power is a desirable
trade off for lower current.:
Reading RSSI
The CYRF8935 contains internal RSSI circuitry that is roughly
linearized to 1 dB for every LSB. Results are read from register
6[15:10], RAW_RSSI. See Register Definitions on page 21 for
details.
The framer must read the RSSI register after the receiver is
enabled and set on frequency using register 7, and after the RF
PLL has settled according to the correct receive frequency.
Clock
Logic
Xtal. Osc.
Gain Block
CYRF8935
Connect to
Frequency Counter
to verify correct
crystal osc. frequency.
(bare die only)
XTALo
XTALi
BRCLK
C1C2 CRYSTAL
Rs
Rf
Table 6. Transmit Power Control
Power Setting
Description
Typical
Transmit
Power
(dBm)
Value of Register 9
Silicon ID
0x1002 [6] Silicon ID
0x2002 [6]
PA0 - Highest power +1 0x1820 0x7820
PA2 - High power 0 0x1920 0x7920
PA4 - High power –3 0x1A20 0x7A20
PA8 - Low power –7.5 0x1C20 0x7C20
PA12 - Lower power –11.2 0x1E20 0x7E20
RST_n
XTALo
23
XTALi
24
CLK
15
GND 12
PKT
14
VDD2 2
ANT 4
ANTb 3
RST_n
18
MISO
17
VDD3 5
VDD5 9
SPI_SS
13
VDD4 8
MOSI
16
VDD6
19
VDD_IO 11
FIFO 10
Vin
20
VDD1 1
Test2 6
Test3 7
Vout
21
VDD7
22
GND
25
GND
25
U1
CYRF8935
Vin
Vin
R5
10k
Note
6. Silicon Id can be read from Register 31.
Not recommended for new designs
ECYPRESS‘ Enlinnm m Inunnnaw T: 25)C. N=30 — Mean -- MinIMax - tSVRange - tlakangt nssl 3 430 40 ~70 40 750 40 ~30 an Input mm mm) Not recommended for new designs
CYRF8935
Document Number: 001-61351 Rev. *K Page 15 of 40
The wait time between programming RX_EN, and reading
Register 6, can be determined by any of the following methods,
or any desired combination, depending on the application:
Wait in accordance with RF PLL Settling Time spec. to be sure
RF PLL is settled.
Read register 3[12] RF_SYNTH_LOCK to be sure CYRF8935
RF PLL is settled.
Read register 48[7] SYNCWORD_RECV to indicate the signal
being received is a desired packet.
Note that RSSI can be read without receiving a syncword. In
other words, CYRF8935 RSSI circuitry also responds to CW and
interference signals.
If the RSSI feature is not needed, disable it to conserve receiver
DC current budget. When register 11[9] is changed from 0 to 1,
the receiver current consumption decreases by about 0.3 mA.
Figure 12. Typical Room Temperature RSSI Response
Following is the pseudocode for measuring RSSI:
Write Reg11 = 0x0208 ;disable RSSI before reading
Read RSSI = Reg6[15:10] ;do the read
Write Reg11 = 0x0008 ;enable RSSI for next measurement
Automatic ACK
The CYRF8935 provides an automatic retry/acknowledge
feature. This means that if the TX packet does not successfully
arrive at the receiving end, the TX end automatically attempts a
given number of retries. In a weak signal environment, this
feature makes the bit error rate (BER) appear to be zero at the
expense of the frame error rate (FER). Refer to State Diagram
on page 34 for details.
To use automatic retry/acknowledge, see Register Definitions on
page 21 for register 41[11] and register 35[11:8].
Receive CRC and FEC Result
The CYRF8935 returns CRC and FEC error check status in
register 48[15:14]. For convenience, the entire top byte of
register 48 is returned in the SPI status word. These eight bits
are normally available from the SPI hardware block of the MCU
or application, saving the time necessary to do an additional read
of register 48 for the same information.
CRC is calculated only on the payload portion of the packet.
CRC_ERROR only clears after another valid syncword is
detected by the receiver or after transmission of a packet
payload.
Sync Word Selection
At the beginning of each packet, after transmission of a
01010101 preamble, is a sync word, programmable to be 16, 32,
48, or 64 bits long. For the devices to communicate, these must
be programmed to the same value at both ends of the link. The
sync word can be thought of as a MAC address in this respect.
In the CYRF8935 receiver, there is an adjustable tolerance for
sync word bit errors that may occur. This adjustment is called
SYNCWORD_THRESHOLD, set via Register 40, bits 5:0. If set
too tight, performance is good but less-than-optimum receive
sensitivity and link budget is obtained. If set too loose, Frame
Errors increase because of false synchronization.
The situation can sometimes be further complicated if the
chosen sync word, combined with the 01010101 preamble, has
unusually high auto correlation, or correlation with other devices
that may be on the air on a different sync word network. This
undesired condition is likely to happen when the sync word bits
that immediately follow the 01010101 preamble continues the
1010... sequence. In such cases, it becomes difficult for the
receiver to separate the actual sync word from the preamble. The
solution is to either tighten the SYNCWORD_THRESHOLD, or
choose a better sync word. Sometimes increasing the sync word
length is also an option.
Register 36 sets the sync word for the bits that immediately follow
the preamble. If a false sync problem is observed, try changing
this word first.
The following table summarizes some recommended settings.
Table 7. Recommended SYNCWORD_THRESHOLD Settings
Application Sync Word
Length (see
Register 32)
Sync Word
Selection
Recommended
Reg. 40
SYNCWORD_THR
ESHOLD setting
(decimal)
Simple 32 Better
(almost every sync
word must work)
1
32 Good
(Most sync words
work)
2
Advanced 64 Better
(almost every sync
word must work)
6 or tighter
64 Good
(Most sync words
work)
7
Not recommended for new designs
A cyPRmEss ii unlnnw €9me >>mc L8 vmvcmEEoomL “oz
CYRF8935
Document Number: 001-61351 Rev. *K Page 16 of 40
Scramble On/Off Selection
The CYRF8935 incorporates a built-in hardware data scrambling
and descrambling function. This function is designed to make the
transmit data more random, removing long strings of continuous
mark or space. When enabled, it causes payload data to be
modified by a PN code that is initialized according to the setting
of Register 35 SCRAMBLE_DATA.
Systems based on CYRF8935 will normally function either way,
scramble on or off.
Setting SCRAMBLE_ON=1 will indeed cause a small 'token'
increase in over-the-air security, similar to what WEP adds to
WiFi. In other words, it renders the OTA data coded, but it should
not be considered highly secure. For truly secure applications,
consider using scramble combined with other security
algorithms.
To function properly, both ends of the RF link need the same
setting, enabled or disabled. Both ends must also have the same
Register 35 SCRAMBLE_DATA setting.
Measuring Receiver Sensitivity
Receive sensitivity and BER can be measured using these
methods:
Method 1: Link Budget Method
In this method, another CYRF8935 or a compatible transceiver
is used as a transmit packet source. It connects to the device
under test (DUT) through a calibrated attenuation path. The
transmit power should also be known or measured. The receiver
sensitivity can be calculated from the following equation, based
on the largest RF attenuation that can be sustained between Tx
and Rx, while maintaining adequate link performance.
Link_Budget = (TxP – RxSens) [dB]
Where
TxP = Transmit Power [dBm]
RxSens = Receive Sensitivity [dBm]
Figure 13. Measuring Overall Link Budget, Method 1
When using this method, make sure that the RF signal is not
leaking around the attenuator or coupling directly into the
receiver, which renders the attenuation setting meaningless. You
can verify this by simply increasing the attenuation and verifying
that the packets cease to be received at higher attenuator
settings.
RF leakage around the attenuator can be caused by:
Loose RF cable connector
Poorly shielded RF cables
Poor PCB layout at either Tx or Rx
RF boards too close together
Coupling by or over the DC power leads
Note that interference from other 2.4-GHz services could be
leaking into the test setup and degrade the BER measurement.
When properly set up and working, the link budget method is a
simple and reliable way to test and characterize CYRF8935 RF
performance.
Test Variations
Automatic loopback can be added to test both Tx and Rx in the
same test.
Frequency hopping can be added to test over the design
frequency range.
Method 2: Packet Signal Generator method
In this method, an RF signal generator is used as the packet
source. The shielded, adjustable RF output of the signal
generator connects to the receiver input. The signal generator
must have digital pattern storage ability for the modulation. A
packet of valid data is downloaded into the signal generator, and
these packets are repetitively sent to the CYRF8935 receiver
under test. An MCU or PC program monitors the CYRF8935 PKT
flag signal, which causes the MCU or PC to download each
packet as it is received, compare the packet against the
expected values, and report the packet statistics to the end user.
MCU CYRF
8935
CYRF
8935
DUT
Packet TX
MCU
Variable atten.
Trilithic BMA-35110
or equiv.
Packet RX
Not recommended for new designs
EMPRESS ' mmnsnmnunnnuw Packet Transmluar Packet Racelvar Not recommended for new designs
CYRF8935
Document Number: 001-61351 Rev. *K Page 17 of 40
Figure 14. Measuring Receiver Sensitivity with Signal Generator, Method 2
In this setup, the signal generator is set as follows:
Modulation: GFSK, 2-level, Bt = 0.5, peak deviation 320 kHz,
symbol rate 1 Msps.
Frequency, amplitude: As required for test.
Receive Spurious Responses
This receiver, like many other low-cost receivers, may exhibit
spurious responses in-band, often at multiples of certain digital
frequencies. In the case of the CYRF8935, this response
sometimes occurs at multiples of 4 MHz or four channels, offset
from the desired receiver passband. During frequency hopping,
a signal may be found on the wrong frequency, causing incorrect
hopping synchronization.
The workaround for this is to program one of the payload bytes
to contain the channel number on which the packet is being
transmitted. When a packet is received, this byte is checked to
determine if it matches the receive channel setting. If not, the
packet should be discarded.
RF VCO Calibration
Over-the-air Transmit and Receive frequencies for the
CYRF6935 RF transceiver are derived from the 12 MHz crystal
oscillator, multiplied up by the internal fractional-N RF PLL. Low
phase noise is obtained by keeping the PLL KVCO relatively low.
In order for the VCO to cover the desired frequency range over
the expected VDD, temperature, and process extremes, the VCO
must be calibrated prior to use. The CYRF8935 contains a fully
automatic calibration algorithm, but the algorithm does require
approximately 150 us extra time, compared to automatic
calibration turned off.
RF Signal Generator
With Pattern Gen.
CYRF
8935
DUT
Packet Transmitter
Packet data pattern downloaded
into signal generator
Packet Receiver
PC
Programmer
RS-232
Term.
MCU
bd.
Not recommended for new designs
mama: m munlnnw CYPRESS A .) '1 mcgmmv >>mc L2 UmvcmEEooE Hoz
CYRF8935
Document Number: 001-61351 Rev. *K Page 18 of 40
Regulatory Compliance
United States FCC
When operating in the 2402- to 2480-MHz band, the second and third harmonics always fall into what is defined in 47CFR, section
15.205 as ‘restricted bands of operation’. The field strength of radiated emissions greater than 1 GHz in a restricted band must not
exceed 500 µV/m at a distance of 3 meters. Using the equation for free space propagation, you can translate the field strength to an
equivalent RF power level at the DUT, if an assumption is made regarding the effective antenna gain at the second and third harmonic
frequencies.
Figure 15. Calculation of Maximum Spurious Level
The antenna gain assumption of +6 dBi is based on the fact that the measurement requires that the position of the DUT and
measurement antennae be maximized to yield the highest spurious signal. Since the second and third harmonics, by definition, fall
on integer multiples of the carrier wavelength, many common DUT antennae may have good, usable gain at higher frequencies such
as 0 dBi. Accounting for the maximization of the measurement, +6 dBi is a good, conservative antenna gain for harmonic frequencies.
In practice, harmonic emissions are much less of a problem, primarily because the antenna is not specifically optimized for such
harmonics.
The calculation in Figure 15 shows the maximum spurious level at the antenna as –47 dBm. Because the typical second harmonic is
specified as –45 dBm, it follows that an additional 2 dB attenuation could be required. However, no additional attenuation is required
to pass the FCC-radiated emissions test. Individual test results may vary.
Tab l e 8 lists a summary of FCC precompliance test results. The antenna used is a common half-wave end-fed dipole. The results
easily pass the U.S. FCC test for a Part 15.247 device. If there is a problem with qualification because of spurious emissions in
restricted bands, you can add a filter, or perhaps reduce Tx Power through Register 9.
Table 8. FCC Test Results
Run
No. Mode Channel Power
Setting Measured
Power Test Performed Limit Result/Margin
1a Non hopping 2402 MHz Default NA Restricted band edge
(2390 MHz)
FCC Part 15.209 /
15.247(c)
46.8 dbV/m at
2390.0 MHz (–7.2 dB)
Default NA Radiated emissions
(1–0 GHz)
FCC Part 15.209 /
15.247(c)
45.7 dbV/m at
4804.1 MHz (–8.3 dB)
1b Non hopping 2441 MHz Default NA Radiated emissions
(1–18 GHz)
FCC Part 15.209 /
15.247(c)
45.0 dbV/m at
4882.2 MHz (–9.0 dB)
1c Non hopping 2480 MHz Default NA Restricted band edge
(2483.5 MHz)
FCC Part 15.209 /
15.247(c)
47.8 dbV/m at
2484.1 MHz (–6.2 dB)
Default NA Radiated emissions
(1–10 GHz)
FCC Part 15.209 /
15.247(c)
45.3 dbmV/m at
4960.1 MHz (–8.7 dB)
Paramete
r
Unit of
Measure
Field Strength
54.0
dBµV/m
o
r
501
µV/m
o
r
0.501 mV/m
Tx an tenna gain over isotropic 6
dBi
o
r
3.981071706 power ratio
Impedance of free space 377 ohms
o
r
120*pi
ohms
distance
0.003 km o
r
3m
Result
T
x pwr, desired signal 0 dBm o
r
0.001 W
Tx pwr, undesired spurious -47.2 dBm o
r
1.89287E-
08 W
or
-47.2 dBc
Not recommended for new designs
magma—u 26: L8 UmvcmEEooE 52 nlnuw EXEBESS A 2-)
CYRF8935
Document Number: 001-61351 Rev. *K Page 19 of 40
Register Settings for Test Purposes
To pass various regulatory agency EMC tests, the DUT may need to enter various test states as shown below. After loading the
recommended register values shown in Table 12 on page 26, load the registers in the order shown in the following table.
Recommendations for PCB Layout
Though the PCB layout is not too critical, here are some
recommendations:
RF path: Adhere closely to the recommended reference design
circuit.
Clock traces: Keep the quartz crystal traces simple and direct.
The self-bias resistor should be close to the XTALi and XTALo
pins. The oscillation loop, consisting of the series resistor and
crystal, should be a simple, small loop. The crystal-loading
capacitors should be near the crystal. The ground connection
to these capacitors must be good, clean, and quiet. This
prevents noise from being injected into the oscillator. It is best
to have one ground plane for the entire RF section.
Power distribution and decoupling: Capacitors should be
located near the VDD pins, as shown in Typical Application on
page 12.
Antenna placement: When using an antenna, follow the
manufacturer's recommendation regarding layout.
Digital interface: To provide a good ground return for the digital
lines, it is a good idea to provide at least two pins for ground
on the digital interface connector. Good grounding between RF
and MCU can help reduce noise 'seen' at the antenna, thus
improving performance.
Antenna Type and Location
The most significant factor affecting RF performance for the
CYRF8935 or any other over-the-air RF device is the antenna
type, placement, and orientation. Antenna gain is normally
measured with respect to isotropic, that is, an ideal radiator that
sends or receives power equally to or from any direction. An ideal
antenna choice for most low-power, short-range wireless
applications is the theoretical isotropic reference antenna.
Unfortunately, these do not exist in practice. A simple dipole with
a theoretical gain of +2 dBi is usually a good choice. However,
you should take care when placing the antenna, because dipole
antennas have a radiation pattern where the null can be very
deep.
The antenna must be kept away from human tissue, particularly
sensitive spots like the heart, brain, and eyes. Violating this
design principle makes the end product perform poorly and can
be dangerous for the user. Refer to www.fcc.gov/oet/rfsafety for
guidance on this subject. For best operation, design the product
so that the main antenna radiation is away from the body, or at
least not proximity-loaded by the human body or dielectric
objects within the product.
Remember to keep the antenna away from clock lines and digital
bus signals; otherwise, harmonics of the clock frequency will jam
certain receive frequencies.
Table 9. Register Settings for Test Purposes
Test State Notes Register Settings
Tx continuously,
CW mode
Primarily used to verify proper crystal oscillator
frequency.
The Tx turns on and stays on continuously. There will
be no on/off bursting of the carrier. Modulation will be
absent. Carrier frequency will be half-way between
mark and space.
Occasionally used during EMC testing.
Reg. 11= 0x8008
(CW_MODE= 1)
Reg. 41= 0xC000
(SCRAMBLE_ON= 1,
PACK_LENGTH_EN= 0, and
FW_TERM_TX= 0)
Reg. 7 as shown in Tabl e 4 on page 13.
Tx continuously,
Random data mode
During EMC testing, this is the most commonly used
Tx test.
Modulation will be normal, GFSK. Tx data will continu-
ously cycle through the FIFO data bits. A data scram-
bling function will be applied. In other words, even if the
FIFO has all zeros (not yet loaded with data), Tx data
will appear random. Radiated emissions resemble
normal operation except that the carrier is on continu-
ously, which significantly speeds up testing.
Reg. 11= 0x0008
(CW_MODE= 0)
Reg. 41= 0xC000
(SCRAMBLE_ON= 1,
PACK_LENGTH_EN= 0, and
FW_TERM_TX= 0)
Reg. 7 as shown in Tabl e 4 on page 13.
Rx continuously Sometimes required for EMC testing. Reg. 41= 0xC000
(PACK_LENGTH_EN= 0, and
FW_TERM_TX= 0)
Reg. 7 as shown in Tabl e 4 on page 13.
Tx and Rx off
(IDLE state)
When neither Tx nor Rx is desired. Reg. 7:
clear bits 8 and 7.
Reg. 7 binary:
xxxx xxx0 0xxx xxxx
(x = don’t care)
Not recommended for new designs
magma—u 26: L8 UmvcmEEooE #oZ Eulznnin m munlnuw CYPRESS A .) '1
CYRF8935
Document Number: 001-61351 Rev. *K Page 20 of 40
IR Reflow Standard
Reference: IPC/JEDEC J-STD-020D.1
Figure 16. Recommended IR Reflow Profile
Liquidous temp.
TL= 217
Tp = 250 +0, -5
30 seconds
(See Jedec J-STD-020 latest rev.)
Ramp-up
3 °C per second (max)
Ramp-down
6 °C per sec. (max)
Tsmax = 200
Temp: °C
Tsmin = 150
60 to 150
seconds
60 to 120
seconds
T= 25
8 minutes max. Time
Not recommended for new designs
{EMPRESS ' munnznmmunmnw Not recommended for new designs
CYRF8935
Document Number: 001-61351 Rev. *K Page 21 of 40
Register Definitions
The following registers are accessed using the SPI protocol.
Some of the internal registers and bit fields are not intended for end-user adjustment. Such registers are not described here and
should not be altered from the factory-recommended value
Table 10. RF Register Information
Bit No. Bit Name Description
Register 3 – Read only
15:13 (Reserved) (Reserved)
12 RF_SYNTH_LOCK Indicates the phase lock status of RF synthesizer.
1: Locked
0: Unlocked
11:0 (Reserved) (Reserved)
Register 6 – Read only
15:10 RAW_RSSI[5:0] Indicates 6-bit raw RSSI value from analog circuit.
Each LSB is approximately 1 dB. See Reading
RSSI on page 14 for details.
9:0 (Reserved) (Reserved)
Register 7
15:9 (Reserved) (Reserved)
8 TX_EN Initiates the transmit sequence for state machine
control.
Note that TX_EN and RX_EN cannot be set to ‘1’
at the same time.
7 RX_EN Initiates the receive sequence for state machine
control.
Note that TX_EN and RX_EN cannot be set to ‘1’
at the same time.
6:0 RF_PLL_CH_NO [6:0] Sets Tx and Rx RF channel number, for example:
Write 0 for channel 0 (2402 MHz)
Write 39 for channel 39 (2441 MHz)
Write 78 for channel 78 (2480 MHz)
Register 9
15:11 (Reserved) (Reserved)
10:7 PA_GN[3:0] PA power level control
6:0 (Reserved) (Reserved)
Register 10
15:1 (Reserved) (Reserved)
0 XTAL_OSC_EN 1: Enable crystal oscillator gain block
0: Disable crystal oscillator gain block
15:1 (Reserved) (Reserved)
Register 11
15 CW_MODE 1: Disables Tx modulation; CW only.
0: Normal Tx mode
14:10 (Reserved) (Reserved)
9 RSSI_DIS 1: Disable RSSI
0: RSSI operates normally.
8:0 (Reserved) (Reserved)
Not recommended for new designs
{EMPRESS ' Emlznninmmxnnnnw x x Not recommended for new designs
CYRF8935
Document Number: 001-61351 Rev. *K Page 22 of 40
Register 23
15:3 (Reserved) (Reserved)
2 TXRX_VCO_CAL_EN 1: enable automatic VCO calibration with every
Tx/Rx.
0: disable feature
1:0 (Reserved) (Reserved)
Register 27
15:11 LDO_SP_SLEEP Sets LDO sleep current. See Electrical
Characteristics on page 28 for Register 27
settings.
10:0 (Reserved) (Reserved)
Register 29 - Read only - 0x00xx
15:8 (Reserved) (Reserved)
7:4 RF_VER_ID [3:0] This field is used to identify minor RF revisions to
the design.
3 (Reserved) (Reserved)
2:0 Digital version This field is used to identify minor digital revisions
to the design.
Register 30 - Read only - 0xf413
15:0 (Reserved) (Reserved)
Register 31 - Read only
15:0 Silicon ID This field is used to identify Silicon ID. Valid values
are 0x1002 and 0x2002
Table 10. RF Register Information (continued)
Bit No. Bit Name Description
Not recommended for new designs
{EMPRESS ' mznnmmmunnnw Not recommended for new designs
CYRF8935
Document Number: 001-61351 Rev. *K Page 23 of 40
Table 11. Framer Register Information
Bit No. Bit Name R/W Description Default
Register 32
15:13 PREAMBLE_LEN R/W 000b: 1 byte
001b: 2 bytes
010b: 3 bytes
.
.
111b: 8 bytes
010b
12:11 SYNCWORD_LEN R/W 11b: 64 bits
{{Reg39[15:0],Reg38[15:0],Reg37[15:0],Reg36[15:0]}
10b: 48 bits, {Reg39[15:0],Reg38[15:0],Reg36[15:0]}
01b: 32 bits, {Reg39[15:0],Reg36[15:0]
00b: 16 bits,{Reg36[15:0]}
11b
10:8 TRAILER_LEN R/W 000b: 4 bits
001b: 6 bits
010b: 8 bits
011b: 10 bits
.
.
111b: 18 bits
000b
7:6 DATA_PACKET_TYPE R/W 00b: Non return to zero (NRZ) law data 00b
5:4 FEC_TYPE R/W 00b: No FEC
01b: Reserved
10b: FEC23
11b: Reserved
00b
3:1 BRCLK_SEL R/W Selects output clock signal to BRCLK[7] pin:
000b: Keep low
001b: Crystal buffer out
010b: Crystal divided by 2
011b: Crystal divided by 4
100b: Crystal divided by 12
101b: TXCLK 1 MHz
110b: APLL_CLK (12 MHz during Tx, Rx)
111b: Keep low
011b
0 (Reserved) W/R (Reserved) 0B
Register 35
15 (Reserved) (Reserved)
14 SLEEP_MODE W 1: Enter SLEEP state (set crystal gain block to off. Keep LDO
regulator on (register values will be preserved).
Wakeup begins when SPI_SS goes low. This restarts the on-chip
clock oscillator to begin normal operation.
0: Normal (IDLE) state
0B
13 (Reserved) (Reserved)
12 BRCLK_ON_SLEEP R/W 1: Crystal running at sleep mode
Draws more current but enables fast wakeup
0: Crystal stops during sleep mode
Saves current but takes longer to wake up
1B
Note
7. BRCLK signal is available on bare die only, not packaged parts.
Not recommended for new designs
{EMPRESS ' Eulinnznmmunmnw Not recommended for new designs
CYRF8935
Document Number: 001-61351 Rev. *K Page 24 of 40
11:8 RE-TRANSMIT_TIMES R/W Max retransmit packet attempts when AUTO_ACK= 1. 3H
7 MISO_TRI_OPT R/W 1: MISO drives low-Z even when SPI_SS = 1 (Only one SPI slave
device on the SPI)
0: MISO goes tristate when SPI_SS = 1 (Allows multiple SPI
slave devices on the SPI)
0B
6:0 SCRAMBLE_DATA R/W Whitening seed for data scramble. Must be set the same at both
ends of radio link (Tx and Rx). Must be nonzero.
00H
Register 36
15:0 SYNC_WORD[15:0] R/W Least significant bits of sync word are sent first 0000H
Register 37
15:0 SYNC_WORD[31:16] R/W Least significant bits of sync word are sent first 0000H
Register 38
15:0 SYNC_WORD[47:32] R/W Least significant bits of sync word are sent first 0000H
Register 39
15:0 SYNC_WORD[63:48] R/W Least significant bits of sync word are sent first 0000H
Register 40
15:11 FIFO_EMPTY_THRESHOLD R/W During Tx, this field adjusts the point at which the FIFO flag signal
notifies the MCU or application to indicate that the FIFO register
is almost empty.
The best value depends on the individual application and the
speed at which the MCU or application can access the FIFO.
00100B
10:6 FIFO_FULL_THRESHOLD R/W During Rx, this field adjusts the point at which the FIFO flag signal
notifies the MCU or application to indicate that the FIFO register
is almost full.
The best value depends on the individual application and the
speed at which the MCU or application can access the FIFO.
00100B
5:0 SYNCWORD_THRESHOLD R/W Sets maximum number of received syncword bits that may be in
error to start a packet receive. The number of bits is
(SYNCWORD_THRESHOLD - 1). For example, a setting of 7
means up to 6 sync word bits can be in error
07H
Register 41
15 CRC_ON R/W 1: CRC on
0: CRC off
1B
14 SCRAMBLE_ON R/W Removes long patterns of continuous 0 or 1 in transmit data.
Automatically restores original unscrambled data on receive.
1: Scramble on
0: Scramble off
0B
13 PACK_LENGTH_EN R/W 1: CYRF8935 regards the first byte of payload as packet length
descriptor byte.
1B
12 FW_TERM_TX R/W 1: When FIFO write point equals read point, CYRF8935
terminates Tx when the FW handles packet length.
0: FW (MCU) handles length and terminates Tx
1B
11 AUTO_ACK R/W 1: After receiving data, automatically send ACK to acknowledge
that the packet was received correctly.
0: After receiving data, do not send ACK; just go to IDLE.
1B
Table 11. Framer Register Information (continued)
Bit No. Bit Name R/W Description Default
Not recommended for new designs
{EMPRESS ' mmnznmmumw Not recommended for new designs
CYRF8935
Document Number: 001-61351 Rev. *K Page 25 of 40
10 PKT_FIFO_POLARITY R/W 1: PKT flag, FIFO flag active low
0: Active high
0B
9:8 (Reserved) R/W (Reserved) 00B
7:0 CRC_INITIAL_DATA R/W Initialization constant for CRC calculation 00H
Register 48 – Read only
15 CRC_ERROR R Received CRC error
14 FEC23_ERROR R Indicate FEC23 error
13:8 FRAMER_ST R Framer status
7 SYNCWORD_RECV R 1: syncword received. It is only available in receive status,
After out receive status, always set to ‘0’
6 PKT_FLAG R PKT flag indication
5 FIFO_FLAG R FIFO flag indication
4:0 (Reserved) R (Reserved)
Register 50
15:0 TXRX_FIFO_REG R/W For MCU read/write data between the FIFO
Reading this register removes data from FIFO;
Writing to this register adds data to FIFO.
Note MCU or application access to the FIFO register is
byte by byte (8 bits at a time), not 16 bits as with other registers.
00H
Register 52
15 CLR_W_PTR W 1: Clear Tx FIFO pointer to 0 when writing this bit to ‘1’
It is not available in RX status.
0B
14 (Reserved) W
13:8 FIFO_WR_PTR R FIFO write pointer
7 CLR_R_PTR W 1: Clear Rx FIFO point to 0 when writing this bit to ‘1’
It is not available in Tx status.
0B
6 (Reserved)
5:0 FIFO_RD_PTR R FIFO read pointer (number of bytes to be read by MCU)
Table 11. Framer Register Information (continued)
Bit No. Bit Name R/W Description Default
Not recommended for new designs
{EMPRESS ' Eulennznmmunmnw [a] [5] Not recommended for new designs
CYRF8935
Document Number: 001-61351 Rev. *K Page 26 of 40
Recommended Register Values
The following register values are recommended for most typical applications. Some changes may be required depending on the
application.
Table 12. Recommended Register Values
Register No. Power-up Reset Value
(hex) Recommended value for applications (hex) Notes
Silicon ID 0x1002 [8] Silicon ID 0x2002 [8]
0 6FEF 6FE1 6FE1 Internal Usage
1 5681 5681 5681 Internal Usage
2 6619 5517 5517 Internal Usage
4 5447 9CC9 9CD4 Internal Usage
5 F000 6647 651F Internal Usage
7 0030 0000 0000 Use for setting RF frequency, and to
start/stop Tx/Rx packets.
Register details in Table 10
8 71AF 6C90 6C90 Internal Usage
9 3000 1920 7920 Sets Tx power level.
Register details in Table 10
10 7FFD 7FFD 7FFD Crystal oscillator enabled. Used for
sleep patch.
Register details in Table 10
11 4008 0008 0008 RSSI enabled
Register details in Table 10
12 0000 0000 0000 Internal Usage
13 4855 4880 48BF Internal Usage
22 C0FF 00FF 00FF Internal Usage
23 8005 0005 0005 Register details in Table 10
24 307b 0067 0067 Internal Usage
25 1659 1659 1659 Internal Usage
26 1833 19E0 1A30 Internal Usage
27 9100 4200 4200 8 µA sleep current
Register details in Table 10
28 1800 1800 1800 Internal Usage
32 1806 1000 1000 Packet data type: NRZ, no FEC,
BRCLK[9] = 12 divided by 4 = 3 MHz
Register details in Table 11
33 6307 32A0 32A0 Internal Usage
34 030B 1000 1000 Internal Usage
35 1300 0F01 0F01 AutoACK max Tx retries = 3
Register details in Table 11
36 0000 Unique sync word Unique sync word Similar to a MAC address
Register details in Table 11
37 0000 Unique sync word Unique sync word Similar to a MAC address
Register details in Table 11
38 0000 Unique sync word Unique sync word Similar to a MAC address
Register details in Table 11
39 0000 Unique sync word Unique sync word Similar to a MAC address
Register details in Table 11
Notes
8. Silicon Id can be read from Register 31.
9. BRCLK signal is available on bare die only, not packaged parts.
Not recommended for new designs
magma—u 26: L8 UmvcmEEooE 52 [5] [5]
CYRF8935
Document Number: 001-61351 Rev. *K Page 27 of 40
40 2107 2047 2047 Configure FIFO flag
Register details in Table 11
41 B800 F800 F800 CRC on. SCRAMBLE off
First byte is packet length
AutoACK off
Register details in Table 11
42 FD6B FDFF FDFF Internal Usage
43 000F 000F 000F Internal Usage
Table 12. Recommended Register Values (continued)
Register No. Power-up Reset Value
(hex) Recommended value for applications (hex) Notes
Silicon ID 0x1002 [8] Silicon ID 0x2002 [8]
Not recommended for new designs
CYPRESS mmnznmmumw Commercial 0 FT: lo 70 ”C +19 m 3,6 V +19 m 3,6 V Vw ‘ ‘ ‘ DD \0 VIN [13] 'DD TX12 H 1 I [13] DD Rx I [13] DD IDLEW [1 1 Tem Us 5‘ R VIN Dmo VDDIO VDD ‘0 OH OL ' LEAK OUT T RISE OUT Not recommended for new designs
CYRF8935
Document Number: 001-61351 Rev. *K Page 28 of 40
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.[10, 11]
Storage temperature ................................ –55 °C to +125 °C
Ambient temperature with
power applied .......................................... –55 °C to +125 °C
Supply voltage on VDD relative to GND ............ 0 to + 1.98 V
Supply voltage on VDD_IO
or VIN relative to GND ........................................0 to +3.63 V
DC voltage applied to outputs
in tristate .................................. (VSS – 0.5) to (VDD_IO + 0.5)
DC input voltage ...................... (VSS – 0.5) to (VDD_IO + 0.5)
Current into outputs (LOW) ........................................ 10 mA
Electrostatic discharge voltage, HBM (QFN package only)
RF pins (ANT, ANTb) .......................................... >500 V
Analog pins XTALi, XTALo .................................. >500 V
All other pins ....................................................... 2000 V
Latch up current (JEDEC JESD78B, Class II) ........ ±140 mA
Operating Range
Range Ambient
Temperature VIN VDD_IO
Commercial 0 °C to 70 °C +1.9 to 3.6 V +1.9 to 3.6 V
Notes
10. Absolute maximum ratings indicate limits beyond which damage to the device may occur. Recommended operating conditions indicate conditions for which the device
is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see Electrical Characteristics.
11. These devices are electrostatic-sensitive. Devices should be transported and stored in anti-static containers. Equipment and personnel contacting the devices need
to be properly grounded. Cover workbenches with grounded conductive mats.
12. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VIN = 3 VDC, Ta = +25 °C.
13. BRCLK signal is available on bare die only, not packaged parts.
Electrical Characteristics
For wafer and die products, RF and AC specifications are guaranteed by characterization only – not production tested.
Symbol Description Min Typ Max Units Test Condition and Notes
Supply voltage
VIN DC power supply voltage range 1.9 3.6 VDC Input to VDD_IO and VIN pins
Current consumption
IDD_TX2 Current consumption – Tx 18.5 mA Transmit power PA2. BRCLK[13] off.
IDD_TX12 13.7 mA Transmit power PA12. BRCLK[13] off
IDD_RX Current consumption – Rx 18 mA BRCLK[13] off
IDD_IDLE1 Current consumption – idle 1.1 mA Configured for BRCLK[13] output off
IDD_SLPx Current consumption – sleep 1 µA[12] Temperature = +25 °C.
Using firmware sleep patch. (Enter
Sleep and Wakeup on page 6)
Register 27 = 0x1200, for
VIN 3.00 VDC only
IDD_SLPr 8 µA Temperature = +25 °C; using
firmware sleep patch (Enter Sleep
and Wakeup on page 6)
Register 27 = 0x4200.
IDD_SLPh 38 µA Temperature = +70 °C
‘C’ grade part; using firmware sleep
patch (Enter Sleep and Wakeup on
page 6)
Register 27 = 0x4200
VIH Logic input high 0.8 VDDIO 1.2 VDDIO V
VIL Logic input low 0 0.8 V
I_LEAK_IN Input leakage current 10 µA
VOH Logic output high 0.8 VDD_IO ––VI
OH = 100 µA source
VOL Logic output low 0.4 V IOL = 100 µA sink
I_LEAK_OUT Output leakage current 10 µA MISO in tristate
T_RISE_OUT Rise/fall time (SPI MISO) 8 25 ns 7 pF cap. load
Not recommended for new designs
{EMPRESS ' mmnznmmumw R XmaXVSIg m 0' cochannel w [14] Not recommended for new designs
CYRF8935
Document Number: 001-61351 Rev. *K Page 29 of 40
T_RISE_IN Rise/fall time (SPI MOSI) 25 ns
Tr_spi CLK rise, fall time (SPI) 25 ns Requirement for error-free register
reading, writing.
F_OP Operating frequency range 2400 2482 MHz Usage on-the-air is subject to local
regulatory agency restrictions
regarding operating frequency.
VSWR_I Antenna port mismatch
(Z0 = 50 )
<2:1 VSWR Receive mode. Measured using LC
matching circuit shown in Typical
Application on page 12
VSWR_O <2:1 VSWR Transmit mode. Measured using LC
matching circuit shown in Typical
Application on page 12
Receive section Measured using LC matching circuit
shown in
Typical Application on page 12
For BER 0.1%
RxSbase Receiver sensitivity
(FEC off)
–87 dBm Room temperature only
0-ppm crystal frequency error.
RxStemp –84 dBm Over temperature;
0-ppm crystal frequency error.
RxSppm –84 dBm Room temperature only
80-ppm total frequency error
(± 40-ppm crystal frequency error,
each end of RF link)
RxStemp+ppm –80 dBm Over temperature;
80-ppm total frequency error
(± 40-ppm crystal frequency error,
each end of RF link)
Rxmax-sig Maximum usable signal –20 0 dBm Room temperature only
Ts Data (Symbol) rate 1 µs
Minimum Carrier/Interference ratio For BER 0.1%.
Room temperature only.
CI_cochannel Co-channel interference +9 dB –60-dBm desired signal
CI_1 Adjacent channel interference,
1-MHz offset
+6 dB –60-dBm desired signal
CI_2 Adjacent channel
interference, 2-MHz offset
–12 dB –60-dBm desired signal
CI_3 Adjacent channel
interference, 3-MHz offset
–24 dB –67-dBm desired signal
OBB Out-of-band blocking –27 dBm 30 MHz to 12.75 GHz [14]
Measured with ACX BF2520
ceramic filter [15] on ant. pin.
–67-dBm desired signal,
BER 0.1%.
Room temperature only.
Electrical Characteristics (continued)
For wafer and die products, RF and AC specifications are guaranteed by characterization only – not production tested.
Symbol Description Min Typ Max Units Test Condition and Notes
Notes
14. The test is run at one midband frequency, typically 2460 MHz. With blocking frequency swept in 1-MHz steps, up to 24 exception frequencies are allowed. Of these,
no more than five will persist with blocking signal reduced to –50 dBm. For blocking frequencies below desired receive frequency, in-band harmonics of the out-of-band
blocking signal are the most frequent cause of failure, so be sure blocking signal has adequate harmonic filtering.
15. In some applications, this filter may be incorporated into the antenna, or be approximated by the effective antenna bandwidth.
Not recommended for new designs
A m m Not recommended for new designs
CYRF8935
Document Number: 001-61351 Rev. *K Page 30 of 40
Transmit section Measured using a LC matching
circuit as shown in Typical
Application on page 12[16]
PAVH RF output power +1 dBm PA0 (PA_GN = 0,
Reg9 = 0x1820
for Silicon ID [17] 0x1002 /
Reg9 = 0x7820
for Silicon ID [17] 0x2002).
Room temperature only.
PAVL –11.2 dBm PA12 (PA_GN = 12,
Reg9 = 0x1E20
for Silicon ID [17] 0x1002 /
Reg9 = 0x7E20
for Silicon ID [17] 0x2002).
Room temperature only.
TxPfx2 Second harmonic –45 dBm Measured using a LC matching
circuit as shown in
Typical Application on page 12.
Room temperature only.
TxPfx3 Third and higher harmonics –45 dBm Measured using a LC matching
circuit as shown in
Typical Application on page 12.
Room temperature only.
Modulation characteristics
Df1avg 263 kHz Modulation pattern: 11110000...
Df2avg 255 kHz Modulation pattern: 10101010...
In-band spurious emission
IBS_2 2-MHz offset –20 dBm
IBS_3 3-MHz offset –30 dBm
IBS_4 4-MHz offset –30 – dBm
RF VCO and PLL section
Fstep Channel (Step) size 1 MHz
L100k SSB phase noise –75 dBc/Hz 100-kHz offset
L1M –105 dBc/Hz 1-MHz offset
dFX0 Crystal oscillator frequency
error
–40 +40 ppm Relative to 12-MHz crystal reference
frequency
THOP RF PLL settling time[18] 100 150 µs Settle to within 30 kHz of final value.
AutoCAL off.
THOP_AC 250 350 µs Settle to within 30 kHz of final value.
AutoCAL on.
LDO voltage regulator section
VDO Dropout voltage 0.17 0.3 V Measured during receive state
Electrical Characteristics (continued)
For wafer and die products, RF and AC specifications are guaranteed by characterization only – not production tested.
Symbol Description Min Typ Max Units Test Condition and Notes
Notes
16. Transmit power measurement is at output of matching circuit shown in Typical Application on page 12.
17. Silicon Id can be read from Register 31.
18. Max PLL settling time is guaranteed by design (not production tested).
Not recommended for new designs
{EMPRESS ' mmnmmmunnnw 4‘ Not recommended for new designs
CYRF8935
Document Number: 001-61351 Rev. *K Page 31 of 40
SPI
The CYRF8935 supports a 4-wire slave SPI. All of the function control is under SPI command.
There are four pins in the SPI.
SPI_SS: Slave selection input (active low)
CLK: Serial clock input
MOSI: Master out slave in
MISO: Master in slave out
SPI Transaction Formats and Timing
SPI read and write data is always in multiples of bytes. The first byte (MSB) consists of the R/W direction bit, followed by a 7-bit register
address. Following this byte, there are one or more data bytes.
When using the SPI to access the internal registers, note that some registers are accessed differently than others. Table 13 shows
the three types of registers:
Figure 17. Single-Byte Data Format
Figure 18. Two-Byte Data Format
Figure 19. Multi-Byte Data Format[19]
Table 13. SPI Access Methods for Various Registers
Group No. Register
Number(s) Description Access Method
Group 1 0 to 31 RF/analog registers Write an even number of data bytes
Read out any number of data bytes; Register high
byte is read out first
Group 2 32 to 42, 52 State and framer configuration registers Read/writeable any data bytes
Group 3 50 FIFO read/write Always byte by byte
SPI_SS
CLK
MOSI W/R A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
MISO S7 S6 S5 S4 S3 S2 S1 S0 d7 d6 d5 d4 d3 d2 d1 d0
TSSS TSSH
T1 TSS_HD
SPI_SS
CLK
MOSI W/R A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
MISO S7 S6 S5 S4 S3 S2 S1 S0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0
T1 T1
TSSS TSSH TSS_HD
SPI_SS
CLK
MOSI W/R A6 A5 A4 A3 A2 A1 A0 D7 D6 D7 D7 D7 D0
MISO S7 S6 S5 S4 S3 S2 S1 S0 d7 d6 d7 d7 d7 d7 d0
D7
D0 D0
d0
D0 D0
d0d0 d0
address address + n
address + 1
T1 T1 T1
TSSS TSSH TSS_HD
Note
19. For all registers except register 50, the internal register address auto-increments by one when reading or writing more than two bytes of data in a single SPI transaction.
This is an optional, built-in feature designed to save time when reading or writing multiple registers in ascending sequence.
Not recommended for new designs
mm A 2-) mcgmmv >>mc L2 UmvcmEEooE Hoz / .......... H... 88 $8 <§> 88 8S
CYRF8935
Document Number: 001-61351 Rev. *K Page 32 of 40
Specifications
W/R bit:
0: Write SPI
1: Read SPI
Dx: Data bits from SPI master. When reading, these bits are ignored.
dx: Data bits from SPI slave. When writing, dx is the same as Sx.
Sx: Data from Reg48[15:8], MSB first (status byte).
Figure 20. SPI Timing Diagram
SPI_SS
CLK
MOSI
MISO
TSCKH
TSCKL
TSSS TSSH
TSSU TSHD
TSDO
TSDO1
TSDO2
TSCK
TSS_SU
Table 14. SPI Timing Requirements
Timing Parameter Min Max Unit Notes
TSSS 20 ns Setup time from assertion of SPI_SS to CLK edge
TSSH 200 ns Hold time required deassertion of SPI_SS
TSCKH 40 ns CLK minimum high time
TSCKL 40 ns CLK minimum low time
TSCK 83 ns Maximum CLK clock is 12 MHz
TSSU 30 ns MOSI setup time
TSHD 10 ns MOSI hold time
TSS_SU 10 ns Before SPI_SS enable, CLK hold low time requirement
TSS_HD 200 ns Minimum SPI inactive time
TSDO 35 ns MISO setup time, ready to read
TSDO1 5 ns If MISO is configured as tristate, MISO assertion time
TSDO2 250 ns If MISO is configured as tristate, MISO deassertion time
T1 Min_R50 350 ns When reading register 50 (FIFO)
T1 Min 83 ns When writing Register 50 (FIFO), or reading/writing any registers other than register 50.
Not recommended for new designs
A '— msunsn m Inunlnnw CYPRESS ”7157.500 HZ 131392 63 TRRCE c: cn1 2st Err Spec c Marker 20 st Err 5.8 39 zrns 68 15.995 Dk at syn o nag Err 3I6.43 nzrms Logm 971.72 1r Bk :4! syn 73 Carr Dist = 14.557 kHz 5 Dzvlutlon = 273.37 kHz as ralv IrEye :100 1-1 law -1.5 Center: 1.953125 MHZ Swan: 3. 90625 MHZ INPUT/SUUREE STHTE MEHSUREMENT sTHTE n.nge/ Input meg“ Snurce -- thermal 1 »- Status on Rang: -a dBm Input 2 SB um '1ng nee run slepe + 1:1»1 ee1eg ,Z 5 Ext arm DH‘ firm elepe above Hulduff DFF Seems en Tgpa hxee eme [lutpul 2 am um Level 8 v firm level n v Hm delag a s 111:1 delag a 5 Level ’12 1:13" on: Freq a H: Inst Nude Freq 3.1111,. 1' 1-.- D1gne1 Demndulaunn Channels Meee he". mpm Reeewer Formax 2 FSK Ru: filpha 2.5 Mess F1 her Nemehze an Raf filter 1:11 Rd] a sym Spam 7 MHZ Center Rm ma kHz umaem Vuls-srch a” Sync-arch PIS/sgm 1a Srch Reem ma :gm Sync Men Sng: word 111111111 Seems er: Num averages Tgpe ms expo Repeat avg flvev‘lap a 2 Fast avg 1 RF 2553 MHz 1 1111: en 5143551317 2. 47a EH: r11“ mp 2 ms E 315111 15 ac: an Not recommended for new designs
CYRF8935
Document Number: 001-61351 Rev. *K Page 33 of 40
Electrical Operating Characteristics
Figure 21. Typical Transmit EVM, EVM spectrum, Tx eye
Figure 22. EVM equip. setup
Not recommended for new designs
A 2-” wcgwoc Em: L8 coccoEEoom: “oz
CYRF8935
Document Number: 001-61351 Rev. *K Page 34 of 40
State Diagram
OFF
IDLE
VCO_Wait Sleep
Wake Up
VCO_SEL
RX
packet TX
packet
TX ack RX ack
vco_cal
TX_enRX_en
sleep
wake up
ACK
received
NACK
no auto_ack
no auto_ack
no CRC error
packet
error
auto_ack
auto_ack
Not recommended for new designs
A 2-) magma—u 26: L8 UmvcmEEooE #oZ
CYRF8935
Document Number: 001-61351 Rev. *K Page 35 of 40
Ordering Information
Ordering Code Definitions
Ordering Code[20] Package Temperature Range
CYRF8935A-24LQXC 24 pin (4 × 4 × 0.55 mm) Sawn QFN Commercial
CYRF8935A-4X14C Die (14-mil) in waffle pack Commercial
CYRF8935A-4XW14C Die (14-mil) in wafer form Commercial
Thermal Rating
C = Commercial, I = Industrial, E = Extended
CY RF
Part Number
8935 ( 24 LQX (C, I, E)
A
Internal revision code
Marketing code
/ XXX )
Company ID: CY = Cypress
radio frequency
: RF = Wireless
() product family
KGD Level /Package Type/ Die Thickness
24 - pin Sawn QFN package
X = Pb- free
Note
20. For die and wafer sales, consult your Cypress sales representative.
Not recommended for new designs
CYPRESS means.) In Inunlnnw TOP VTEW SDE VTEW BOTTOM VTEW mutate 24 ‘9 To ‘5 \-PTN l DOT 4.001910 r2 555101 /pw V m 0.50:0.05 T i a o 2510 07 7 12 4‘.7005 MAX 2 050 MAX 2 5510.10 NOTES : Lg HATCH TS SOLDERABLE EXPOSED METAL. 2. REFERENCE JEDEC # M07248 3. PACKAGE WETGHT : 29 1 3 mg 4. ALL DTMENSTONS ARE TN MTLLTMETERS vmom 10 Not recommended for new designs
CYRF8935
Document Number: 001-61351 Rev. *K Page 36 of 40
Package Diagram
Figure 23. 24-pin QFN (4 × 4 × 0.55 mm) LQ24A 2.65 × 2.65 E-Pad (Sawn) Package Outline, 001-13937
001-13937 *F
Not recommended for new designs
{EMPRESS ' Eulennznmmunmnw Not recommended for new designs
CYRF8935
Document Number: 001-61351 Rev. *K Page 37 of 40
Acronyms Document Conventions
Units of Measure
Table 15. Acronyms Used in this Document
Acronym Description
ACK Acknowledge (packet received, no errors)
BER Bit Error Rate
BOM Bill Of Materials
CMOS Complementary Metal Oxide Semiconductor
COB Chip On Board
CRC Cyclic Redundancy Check
DUT Device Under Test
EMC Electromagnetic Compatibility
EVM Error Vector Magnitude
FEC Forward Error Correction
FER Frame Error Rate
GFSK Gaussian Frequency-Shift Keying
HBM Human Body Model
ISM Industrial, Scientific, and Medical
IRQ Interrupt Request
MAC Media Access Control
MCU Microcontroller Unit
NRZ Non Return to Zero
OTA Over-the-Air
PLL Phase Locked Loop
PN Pseudo-Noise
QFN Quad Flat No-leads
RSSI Received Signal Strength Indication
RF Radio Frequency
Rx Receive
Tx Transmit
VCO Voltage Controlled Oscillator
WEP Wired Equivalent Privacy
Table 16. Units of Measure
Symbol Unit of Measure
°C degree Celsius
dB decibels
dBc decibel relative to carrier
dBm decibel-milliwatt
Hz hertz
KB 1024 bytes
Kbit 1024 bits
kHz kilohertz
kkilohm
MHz megahertz
Mmegaohm
Amicroampere
smicrosecond
Vmicrovolts
Vrms microvolts root-mean-square
Wmicrowatts
mA milliampere
ms millisecond
mV millivolts
nA nanoampere
ns nanosecond
nV nanovolts
ohm
pp peak-to-peak
ppm parts per million
ps picosecond
sps samples per second
Vvolts
VDC volts direct current
Not recommended for new designs
mcgmmv >5: L2 UmvcmEEooE Hoz mm A 2-)
CYRF8935
Document Number: 001-61351 Rev. *K Page 38 of 40
Document History Page
Document Title: CYRF8935, WirelessUSB™ NL 2.4 GHz Low Power Radio
Document Number: 001-61351
Rev. ECN No. Orig. of
Change Submission
Date Description of Change
** 2963911 HEMP 06/28/2010 New data sheet.
*A 3039285 HEMP 09/27/2010 Updated Block diagram
Updated Init, Xtal Osc, RxSens measurement.
Revised state diagram and package diagram.
Updated Functional Description.
Payload format NRZ only. Revised power control table; showed absolute, not
relative power.
Deleted reference to NAK.
Added RSSI curve.
Corrected Reg. 7, 32, 41 definition.
Updated recommended register values table.
Updated Absolute Maximum voltages and temperature range.
Updated Rx I typical value.
Used PAxx to show power level settings.
Updated third harmonics and VDO values.
Added die information to ordering code.
*B 3112690 HEMP 12/16/2010 No technical updates.
Integrated with EROS.
*C 3296429 HEMP /
KKCN
06/29/2011 Changed status from Preliminary to Final.
Modified product description.
Changed GND1...GND5 to GND in the Logic Block Diagram.
Added note about BRCLK’s availability only on bare die.
Replaced 32-pin with 24-pin and package details.
Updated ‘Enter Sleep and Wakeup’ functional description.
Updated figures 7 and 8.
Updated typical application diagram.
Adding ‘Setting the Radio Frequency’ section.
Modified ‘Crystal Oscillator’ section
Deleted BRCLK pin, CKPHA signal, and FEC13 mode.
Updated ‘Reading RSSI’ section.
Updated register definitions
Updated various electrical specs.
Updated ordering information.
*D 3363798 HEMP 09/07/2011 Added information on die and wafer parts in Features, Ordering Information,
and Ordering Code Definitions.
*E 3440958 HEMP 11/17/2011 Updated Power-on and Register Initialization Sequence section.
Updated Initialization Timing Requirements table.
Updated Initialization Flowchart.
Updated Typical Application and Reset Pull-up Circuit diagram.
Added Reset Pull-up section.
Added Register 27 in RF Register Information table.
Added footnote for RF PLL settling time.
Updated TSDO max value.
*F 3794924 SELV 12/10/2012 Updated Logic Diagram.
Added notes 1, 3, 4, 5, 7, 9, and 13.
Updated values of TSCKH, TSCKL, TSSU parameters in Tab le 14.
Updated Package Diagram as per spec 001-13937 *E.
Not recommended for new designs
29me >5: L8 cmvcmEEooE goz
CYRF8935
Document Number: 001-61351 Rev. *K Page 39 of 40
*G 3841304 SELV 01/10/2013 Updated Typical Application:
Updated Ta b le 6 under Transmit Power Control to include values of Register 9
for each Silicon ID.
Added Note 6 and referred the same Note in both Silicon ID columns.
Updated Register Definitions:
Updated details of “Register 31 - Read only” in Table 10.
Updated Table 12 under Recommended Register Values to include
recommended value for applications for each Silicon ID.
Added Note 8 and referred the same Note for Silicon ID columns.
Updated Electrical Characteristics:
Updated Test Condition and Notes of PAVH and PAVL parameters to include
values of Register 9 for each silicon ID.
Added Note 17 and referred the same Note for Silicon IDs in PAVH and PAVL
parameters.
*H 3928385 SELV 03/11/2013 Updated Enter Sleep and Wakeup, Receive Timing, and Reset Pull-up
sections.
*I 3980337 SELV 04/24/2013 Updated Register Definitions:
Updated Table 12 under Recommended Register Values with new values in
columns “Silicon ID 0x1002” and “Silicon ID 0x2002” for Registers 7, 23, 32,
33, 34, 35, and 41.
*J 4036152 SELV 06/21/2013 Updated Register Definitions:
Updated Table 12 under Recommended Register Values with new value in
column “Silicon ID 0x2002” for Register 26.
Completing Sunset Review.
*K 5742845 SGUP 05/19/2017 Added watermark “Not recommended for new designs” across the document.
Updated Package Diagram:
spec 001-13937 – Changed revision from *E to *F.
Updated to new template.
Document History Page (continued)
Document Title: CYRF8935, WirelessUSB™ NL 2.4 GHz Low Power Radio
Document Number: 001-61351
Rev. ECN No. Orig. of
Change Submission
Date Description of Change
Not recommended for new designs
CYPRESS smmn m vaunnow A V.‘ @9me 3m: L8 vmvcmEEooE “oz
Document Number: 001-61351 Rev. *K Revised May 19, 2017 Page 40 of 40
WirelessUSB and enCoRe are trademarks of Cypress Semiconductor Corporation.
CYRF8935
© Cypress Semiconductor Corporation, 2010–2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
ARM® Cortex® Microcontrollers cypress.com/arm
Automotive cypress.com/automotive
Clocks & Buffers cypress.com/clocks
Interface cypress.com/interface
Internet of Things cypress.com/iot
Memory cypress.com/memory
Microcontrollers cypress.com/mcu
PSoC cypress.com/psoc
Power Management ICs cypress.com/pmic
Touch Sensing cypress.com/touch
USB Controllers cypress.com/usb
Wireless Connectivity cypress.com/wireless
PSoC® Solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Forums | WICED IOT Forums | Projects | Video | Blogs |
Training | Components
Technical Support
cypress.com/support
Not recommended for new designs

Products related to this Datasheet

NO WARRANTY
IC RF TXRX ISM>1GHZ 24UFQFN