NTD3055L104 Datasheet by ON Semiconductor

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© Semiconductor Components Industries, LLC, 2016
May, 2019 Rev. 10
1Publication Order Number:
NTD3055L104/D
NTD3055L104,
NTDV3055L104
MOSFET – Power, N-Channel,
Logic Level, DPAK/IPAK
12 A, 60 V
Designed for low voltage, high speed switching applications in power
supplies, converters and power motor controls and bridge circuits.
Features
Lower RDS(on)
Lower VDS(on)
Tighter VSD Specification
Lower Diode Reverse Recovery Time
Lower Reverse Recovery Stored Charge
NTDV and STDV Prefixes for Automotive and Other Applications
Requiring Unique Site and Control Change Requirements;
AECQ101 Qualified and PPAP Capable
These Devices are PbFree and are RoHS Compliant
Typical Applications
Power Supplies
Converters
Power Motor Controls
Bridge Circuits
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating Symbol Value Unit
DraintoSource Voltage VDSS 60 Vdc
DraintoGate Voltage (RGS = 10 MW)VDGR 60 Vdc
GatetoSource Voltage, Continuous
NonRepetitive (tpv10 ms)
VGS
VGS
"15
"20
Vdc
Drain Current
Continuous @ TA = 25°C
Continuous @ TA = 100°C
Single Pulse (tpv10 ms)
ID
ID
IDM
12
10
45
Adc
Apk
Total Power Dissipation @ TA = 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C (Note 1)
Total Power Dissipation @ TA = 25°C (Note 2)
PD48
0.32
2.1
1.5
W
W/°C
W
W
Operating and Storage Temperature Range TJ, Tstg 55 to
+175
°C
Single Pulse DraintoSource Avalanche
Energy Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 5.0 Vdc, L = 1.0 mH
IL(pk) = 11 A, VDS = 60 Vdc)
EAS 61 mJ
Thermal Resistance, JunctiontoCase
JunctiontoAmbient (Note 1)
JunctiontoAmbient (Note 2)
RqJC
RqJA
RqJA
3.13
71.4
100
°C/W
Maximum Lead Temperature for Soldering
Purposes, 1/8 from case for 10 seconds
TL260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. When surface mounted to an FR4 board using 1 pad size,
(Cu Area 1.127 in2).
NChannel
D
S
G
60 V 104 mW
RDS(on) TYP
12 A
ID MAXV(BR)DSS
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
1
Gate
3
Source
2
Drain
4
Drain
DPAK
CASE 369C
STYLE 2
MARKING DIAGRAMS
& PIN ASSIGNMENTS
12
3
4
1
Gate
3
Source
2
Drain
4
Drain
IPAK
CASE 369D
STYLE 2
123
4
AYWW
55L
104G
AYWw
55L
104G
A = Assembly Location*
55L104 = Device Code
Y = Year
WW = Work Week
G = PbFree Package
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* The Assembly Location code (A) is front side
optional. In cases where the Assembly Location is
stamped in the package, the front side assembly
code may be blank.
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2
2. When surface mounted to an FR4 board using the minimum recommended
pad size, (Cu Area 0.412 in2).
Gate-Body Leakage Currem 1sz 5 mm vDS less www.cnsemi.com
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3
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
DraintoSource Breakdown Voltage (Note 3)
(VGS = 0 Vdc, ID = 250 mAdc)
Temperature Coefficient (Positive)
V(BR)DSS
60
70
62.9
Vdc
mV/°C
Zero Gate Voltage Drain Current
(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C)
IDSS
1.0
10
mAdc
GateBody Leakage Current (VGS = ±15 Vdc, VDS = 0 Vdc) IGSS ±100 nAdc
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage (Note 3)
(VDS = VGS, ID = 250 mAdc)
Threshold Temperature Coefficient (Negative)
VGS(th)
1.0
1.6
4.2
2.0
Vdc
mV/°C
Static DraintoSource OnResistance (Note 3)
(VGS = 5.0 Vdc, ID = 6.0 Adc)
RDS(on)
89 104
mW
Static DraintoSource OnVoltage (Note 3)
(VGS = 5.0 Vdc, ID = 12 Adc)
(VGS = 5.0 Vdc, ID = 6.0 Adc, TJ = 150°C)
VDS(on)
0.98
0.86
1.50
Vdc
Forward Transconductance (Note 3) (VDS = 8.0 Vdc, ID = 6.0 Adc) gFS 9.1 mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Ciss 316 440 pF
Output Capacitance Coss 105 150
Transfer Capacitance Crss 35 70
SWITCHING CHARACTERISTICS (Note 4)
TurnOn Delay Time
(VDD = 30 Vdc, ID = 12 Adc,
VGS = 5.0 Vdc, RG = 9.1 W) (Note 3)
td(on) 9.2 20 ns
Rise Time tr104 210
TurnOff Delay Time td(off) 19 40
Fall Time tf40.5 80
Gate Charge
(VDS = 48 Vdc, ID = 12 Adc,
VGS = 5.0 Vdc) (Note 3)
QT7.4 20 nC
Q12.0
Q24.0
SOURCEDRAIN DIODE CHARACTERISTICS
Forward OnVoltage (IS = 12 Adc, VGS = 0 Vdc) (Note 3)
(IS = 12 Adc, VGS = 0 Vdc, TJ = 150°C)
VSD
0.95
0.82
1.2
Vdc
Reverse Recovery Time
(IS = 12 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/ms) (Note 3)
trr 35 ns
ta21
tb14
Reverse Recovery Stored Charge QRR 0.04 mC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Pulse Test: Pulse Width 300 ms, Duty Cycle 2%.
4. Switching characteristics are independent of operating junction temperatures.
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4
TYPICAL CHARACTERISTICS
0
0.12
1612
0.08
0.04
0
820
0.32
24
1.6
1.2
1.4
1
0.8
0.6 1
100
10,000
08
8
21
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)
ID, DRAIN CURRENT (AMPS)
0
VGS, GATETOSOURCE VOLTAGE (VOLTS)
Figure 1. OnRegion Characteristics Figure 2. Transfer Characteristics
ID, DRAIN CURRENT (AMPS)
0
0.16
8
0.08
0
412
Figure 3. OnResistance versus
GatetoSource Voltage
ID, DRAIN CURRENT (AMPS)
Figure 4. OnResistance versus Drain Current
and Gate Voltage
ID, DRAIN CURRENT (AMPS)
RDS(on), DRAINTOSOURCE RESISTANCE (W)
RDS(on), DRAINTOSOURCE RESISTANCE (W)
Figure 5. OnResistance Variation with
Temperature
TJ, JUNCTION TEMPERATURE (°C)
Figure 6. DraintoSource Leakage Current
versus Voltage
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)
RDS(on), DRAINTOSOURCE RESISTANCE
(NORMALIZED)
IDSS, LEAKAGE (nA)
24
50 5025025 75 125100
1 2.5 6
0403020 6010
3
4
12
8 V
VDS 10 V
TJ = 25°C
TJ = 55°C
TJ = 100°C
TJ = 100°C
VGS = 5 V VGS = 10 V
150 175
VGS = 0 V
ID = 6 A
VGS = 5 V
16
0.32
VGS = 10 V
TJ = 25°C
TJ = 55°C
TJ = 100°C
24
TJ = 150°C
TJ = 100°C
0
24
8
16
3.5 4
TJ = 25°C
TJ = 55°C
50
10
6 V
4.5 V
4 V
3 V
1.8
4 5 6 7 1.5 2 3 4.5 5 5.5
0.24
16 20
0.24
0.28
2
20
5 V
3.5 V
4
0.20
0.16
1000
20
4
12
0.12
0.04
0.28
0.20
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5
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because draingate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP
. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the offstate condition when
calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
Crss
10 0 10 15 20 25
GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)
C, CAPACITANCE (pF)
Figure 7. Capacitance Variation
1000
200
0
VGS VDS
400
55
VGS = 0 VVDS = 0 V TJ = 25°C
Ciss
Coss
Crss
Ciss
600
800
15010 TJ:25>c
NTD3055L104, NTDV3055L104
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6
16
0
0.3
DRAINTOSOURCE DIODE CHARACTERISTICS
VSD, SOURCETODRAIN VOLTAGE (VOLTS)
Figure 8. GateToSource and DrainToSource
Voltage versus Total Charge
IS, SOURCE CURRENT (AMPS)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
RG, GATE RESISTANCE (OHMS)
1 10 100
1000
1
t, TIME (ns)
VGS = 0 V
Figure 10. Diode Forward Voltage versus Current
VGS, GATETOSOURCE VOLTAGE (VOLTS)
0
5
3
1
0
QG, TOTAL GATE CHARGE (nC)
6
4
2
4
100
28
0.5 1
2
4
6
ID = 12 A
TJ = 25°C
VGS
Q2
Q1
QT
tr
td(off)
td(on)
tf
10
VDS = 30 V
ID = 12 A
VGS = 5 V
0.7 0.9
6
8
0.80.60.4
10
12
14
TJ = 150°C
TJ = 25°C
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance
General Data and Its Use.”
Switching between the offstate and the onstate may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 ms. In addition the total
power averaged over a complete switching cycle must not
exceed (TJ(MAX) TC)/(RqJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of
draintosource avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous ID can safely be assumed to
equal the values indicated.
V55 S‘NGLE PULSE Tc : 25¢c / ———— Huston) UM”
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7
SAFE OPERATING AREA
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
TJ, STARTING JUNCTION TEMPERATURE (°C)
E
AS, SINGLE PULSE DRAINTOSOURCE
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
0.1 1 100
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)
Figure 13. Thermal Response
1
100
AVALANCHE ENERGY (mJ)
ID, DRAIN CURRENT (AMPS)
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1 0
25 50 75 100 125
10
ID = 11 A
10
10 175
Figure 14. Diode Reverse Recovery Waveform
di/dt
trr
ta
tp
IS
0.25 IS
TIME
IS
tb
30
70
VGS = 15 V
SINGLE PULSE
TC = 25°C
1 ms
100 ms
10 ms dc
10 ms
150
50
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
(NORMALIZED)
t, TIME (s)
0.1
1.0
0.01
1100.10.010.0010.00010.00001
20
40
50
60
0.2
D = 0.5
0.1
RqJC(t) = r(t) RqJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) - TC = P(pk) RqJC(t)
P(pk)
t1
t2
DUTY CYCLE, D = t1/t2
0.05
0.01
SINGLE PULSE
0.02
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8
ORDERING INFORMATION
Device Package Shipping
NTD3055L104G DPAK
(PbFree)
75 Units / Rail
NTD3055L1041G IPAK
(PbFree)
75 Units / Rail
NTD3055L104T4G DPAK
(PbFree)
2500 / Tape & Reel
NTDV3055L1041G IPAK
(PbFree)
75 Units / Rail
NTDV3055L104T4G* DPAK
(PbFree)
2500 / Tape & Reel
STDV3055L104T4G* DPAK
(PbFree)
2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NTDV and STDV Prefixes for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AECQ101
Qualified and PPAP Capable.
D N b «>—I A1 mane; ‘For addmonal \nlorm dams, please dow Mountmg Techmqu www.cnsemi.com
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PACKAGE DIMENSIONS
DPAK (SINGLE GAUGE)
CASE 369C
ISSUE F
5.80
0.228
2.58
0.102
1.60
0.063
6.20
0.244
3.00
0.118
6.17
0.243
ǒmm
inchesǓ
SCALE 3:1
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
b
D
E
b3
L3
L4
b2
M
0.005 (0.13) C
c2
A
c
C
Z
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
D0.235 0.245 5.97 6.22
E0.250 0.265 6.35 6.73
A0.086 0.094 2.18 2.38
b0.025 0.035 0.63 0.89
c2 0.018 0.024 0.46 0.61
b2 0.028 0.045 0.72 1.14
c0.018 0.024 0.46 0.61
e0.090 BSC 2.29 BSC
b3 0.180 0.215 4.57 5.46
L4 −−− 0.040 −−− 1.01
L0.055 0.070 1.40 1.78
L3 0.035 0.050 0.89 1.27
Z0.155 −−− 3.93 −−−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-
MENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
7. OPTIONAL MOLD FEATURE.
12 3
4
H0.370 0.410 9.40 10.41
A1 0.000 0.005 0.00 0.13
L1 0.114 REF 2.90 REF
L2 0.020 BSC 0.51 BSC
A1
H
DETAIL A
SEATING
PLANE
A
B
C
L1
L
H
L2 GAUGE
PLANE
DETAIL A
ROTATED 90 CW5
e
BOTTOM VIEW
Z
BOTTOM VIEW
SIDE VIEW
TOP VIEW
ALTERNATE
CONSTRUCTIONS
NOTE 7
Z
g 4
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10
PACKAGE DIMENSIONS
IPAK
CASE 369D
ISSUE C
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
123
4
V
SA
K
T
SEATING
PLANE
R
B
F
G
D3 PL
M
0.13 (0.005) T
C
E
J
H
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.235 0.245 5.97 6.35
B0.250 0.265 6.35 6.73
C0.086 0.094 2.19 2.38
D0.027 0.035 0.69 0.88
E0.018 0.023 0.46 0.58
F0.037 0.045 0.94 1.14
G0.090 BSC 2.29 BSC
H0.034 0.040 0.87 1.01
J0.018 0.023 0.46 0.58
K0.350 0.380 8.89 9.65
R0.180 0.215 4.45 5.45
S0.025 0.040 0.63 1.01
V0.035 0.050 0.89 1.27
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
Z
Z0.155 −−− 3.93 −−−
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